From patchwork Wed Dec 8 22:50:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 522333 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08CEAC433FE for ; Wed, 8 Dec 2021 22:50:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240704AbhLHWyR (ORCPT ); Wed, 8 Dec 2021 17:54:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45160 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240746AbhLHWyP (ORCPT ); Wed, 8 Dec 2021 17:54:15 -0500 Received: from mail-io1-xd2f.google.com (mail-io1-xd2f.google.com [IPv6:2607:f8b0:4864:20::d2f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8CEFFC0617A1; Wed, 8 Dec 2021 14:50:43 -0800 (PST) Received: by mail-io1-xd2f.google.com with SMTP id y16so4573278ioc.8; Wed, 08 Dec 2021 14:50:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KH5Jne9WcYen8VLv63slDNPB/A+EenVaY1NFcEd7AL0=; b=L/0F/biiGi3tDtP9CI9j6864dUmuoHZqb5Q/X+GvYmx3Mm4HEg/p+c1Czc7Da9LgCJ UdWNefGwzk2WM3YfKmKSx6UqxjG7dDFvD9B9OTTcsRJZhQOnncisacdL8YqrNSg47xgD rQu2I+AaqWvqmWpKxrnpSn19UHABu0IYr4OEyxgaqWZEfbmhsu8TTIGd6UavLZfh6gmd +Xy69KNHKLECsBts3AJOTyR6p1u4SZEFJtKw13Nzcd2BVcUJU8mTMHx7t9KLoKT5E0KX +a5UArm9mpUYNwbK8NUrrre05LuU9GHXmYgFgcND4O9A9/pKvuYXyppMP0TLqs6d2IwD xncA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KH5Jne9WcYen8VLv63slDNPB/A+EenVaY1NFcEd7AL0=; b=E1flWGuxiBSi1Cmf10RIeqCHbNhd5Y6qE38f0incPFvv15Df9XDsllKYx87RL8aFnu G6WrFtD+tJ5j0NDVH+CJjb76jfkShweCrO+gpafjfTYmo3q/ZVzutV+VrnOLoYTR1A8T rsqnxxLCG9CZqfRKqBH2vZrNZ4k0nvPKbBLtfp6XQOtx4suQ8XnFZHE+9kiv6yduLh3k K36HzG6ZgIbB4A5HChcT7Pkx8NvsIfmRogd6dmBxYZ+K0mmYRGno0s2uRq1OKo+/qZrl BsPrVGtUGRdyk6/aQbt+iC6y56IGK4C1matvv4Ks28Wr0hye9qHx+OEbgpRL4XEvx2uK LscA== X-Gm-Message-State: AOAM531nE/8W6uV8QVXpL2NDlQ9+omyg9maUlFdikAdL7fpbzAlLFtiI 7Qz8EmHXu7Rwz5skv9PZw/WhlnMxu9ujRA== X-Google-Smtp-Source: ABdhPJycuHd5Hezj4qLt3M/C9skFUUVnANcKtzFop7/ugQMyK2ceqeFxYBtgBpPkudeWLp6OnqmLcg== X-Received: by 2002:a05:6638:140c:: with SMTP id k12mr3463194jad.89.1639003842466; Wed, 08 Dec 2021 14:50:42 -0800 (PST) Received: from aford-IdeaCentre-A730.lan ([2601:448:8400:9e8:269a:1aa2:f1d9:8dbb]) by smtp.gmail.com with ESMTPSA id t6sm2378751ioi.51.2021.12.08.14.50.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Dec 2021 14:50:42 -0800 (PST) From: Adam Ford To: linux-media@vger.kernel.org Cc: benjamin.gaignard@collabora.com, cphealy@gmail.com, aford@beaconembedded.com, nicolas@ndufresne.ca, Lucas Stach , Adam Ford , Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Greg Kroah-Hartman , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH 02/10] dt-bindings: soc: add binding for i.MX8MQ VPU blk-ctrl Date: Wed, 8 Dec 2021 16:50:21 -0600 Message-Id: <20211208225030.2018923-3-aford173@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211208225030.2018923-1-aford173@gmail.com> References: <20211208225030.2018923-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Lucas Stach This adds the DT binding for the i.MX8MQ VPU blk-ctrl. Signed-off-by: Lucas Stach Signed-off-by: Adam Ford --- .../soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml new file mode 100644 index 000000000000..7263ebedf09f --- /dev/null +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8MQ VPU blk-ctrl + +maintainers: + - Lucas Stach + +description: + The i.MX8MQ VPU blk-ctrl is a top-level peripheral providing access to + the NoC and ensuring proper power sequencing of the VPU peripherals + located in the VPU domain of the SoC. + +properties: + compatible: + items: + - const: fsl,imx8mq-vpu-blk-ctrl + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + + power-domains: + minItems: 3 + maxItems: 3 + + power-domain-names: + items: + - const: bus + - const: g1 + - const: g2 + + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: g1 + - const: g2 + +required: + - compatible + - reg + - power-domains + - power-domain-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + vpu_blk_ctrl: blk-ctrl@38320000 { + compatible = "fsl,imx8mq-vpu-blk-ctrl"; + reg = <0x38320000 0x100>; + power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; + power-domain-names = "bus", "g1", "g2"; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, + <&clk IMX8MQ_CLK_VPU_G2_ROOT>; + clock-names = "g1", "g2"; + #power-domain-cells = <1>; + }; From patchwork Wed Dec 8 22:50:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 522332 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D1A9C4332F for ; Wed, 8 Dec 2021 22:50:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240860AbhLHWyW (ORCPT ); Wed, 8 Dec 2021 17:54:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240803AbhLHWyU (ORCPT ); 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Wed, 08 Dec 2021 14:50:46 -0800 (PST) From: Adam Ford To: linux-media@vger.kernel.org Cc: benjamin.gaignard@collabora.com, cphealy@gmail.com, aford@beaconembedded.com, nicolas@ndufresne.ca, Adam Ford , Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Greg Kroah-Hartman , Lucas Stach , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH 04/10] dt-bindings: media: nxp,imx8mq-vpu: Support split G1 and G2 nodes with vpu-blk-ctrl Date: Wed, 8 Dec 2021 16:50:23 -0600 Message-Id: <20211208225030.2018923-5-aford173@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211208225030.2018923-1-aford173@gmail.com> References: <20211208225030.2018923-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The G1 and G2 are separate decoder blocks that are enabled by the vpu-blk-ctrl power-domain controller, which now has a proper driver. Update the bindings to support separate nodes for the G1 and G2 decoders using the proper driver or the older unified node with the legacy controls. To be compatible with older DT the driver, mark certain items as deprecated and retain the backwards compatible example. Signed-off-by: Adam Ford --- .../bindings/media/nxp,imx8mq-vpu.yaml | 83 ++++++++++++++----- 1 file changed, 64 insertions(+), 19 deletions(-) diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml index 762be3f96ce9..eeb7bd6281f9 100644 --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml @@ -15,29 +15,39 @@ description: properties: compatible: - const: nxp,imx8mq-vpu + oneOf: + - const: nxp,imx8mq-vpu + deprecated: true + - const: nxp,imx8mq-vpu-g1 + - const: nxp,imx8mq-vpu-g2 reg: + minItems: 1 maxItems: 3 reg-names: + minItems: 1 items: - const: g1 - const: g2 - const: ctrl interrupts: + minItems: 1 maxItems: 2 interrupt-names: + minItems: 1 items: - const: g1 - const: g2 clocks: + minItems: 1 maxItems: 3 clock-names: + minItems: 1 items: - const: g1 - const: g2 @@ -58,22 +68,57 @@ required: additionalProperties: false examples: + # Device node example backwards compatibility - | - #include - #include - - vpu: video-codec@38300000 { - compatible = "nxp,imx8mq-vpu"; - reg = <0x38300000 0x10000>, - <0x38310000 0x10000>, - <0x38320000 0x10000>; - reg-names = "g1", "g2", "ctrl"; - interrupts = , - ; - interrupt-names = "g1", "g2"; - clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, - <&clk IMX8MQ_CLK_VPU_G2_ROOT>, - <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; - clock-names = "g1", "g2", "bus"; - power-domains = <&pgc_vpu>; - }; + #include + #include + + vpu: video-codec@38300000 { + compatible = "nxp,imx8mq-vpu"; + reg = <0x38300000 0x10000>, + <0x38310000 0x10000>, + <0x38320000 0x10000>; + reg-names = "g1", "g2", "ctrl"; + interrupts = , + ; + interrupt-names = "g1", "g2"; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, + <&clk IMX8MQ_CLK_VPU_G2_ROOT>, + <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; + clock-names = "g1", "g2", "bus"; + power-domains = <&pgc_vpu>; + }; + + # VPU G1 with vpu-blk-ctrl + - | + #include + #include + #include + + vpu_g1: video-codec@38300000 { + compatible = "nxp,imx8mq-vpu-g1"; + reg = <0x38300000 0x10000>; + reg-names "g1"; + interrupts = ; + interrupt-names = "g1"; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>; + clock-names = "g1"; + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>; + }; + + # VPU G2 with vpu-blk-ctrl + - | + #include + #include + #include + + vpu_g2: video-codec@38310000 { + compatible = "nxp,imx8mq-vpu-g2"; + reg = <0x38310000 0x10000>; + reg-names "g2"; + interrupts = ; + interrupt-names = "g2"; + clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>; + clock-names = "g2"; + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>; + }; From patchwork Wed Dec 8 22:50:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 522331 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5105C43219 for ; Wed, 8 Dec 2021 22:50:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240882AbhLHWy3 (ORCPT ); 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Wed, 08 Dec 2021 14:50:49 -0800 (PST) From: Adam Ford To: linux-media@vger.kernel.org Cc: benjamin.gaignard@collabora.com, cphealy@gmail.com, aford@beaconembedded.com, nicolas@ndufresne.ca, Adam Ford , Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Greg Kroah-Hartman , Lucas Stach , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH 05/10] media: hantro: Allow i.MX8MQ G1 and G2 to run independently Date: Wed, 8 Dec 2021 16:50:24 -0600 Message-Id: <20211208225030.2018923-6-aford173@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211208225030.2018923-1-aford173@gmail.com> References: <20211208225030.2018923-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The VPU in the i.MX8MQ is really the combination of Hantro G1 and Hantro G2. With the updated vpu-blk-ctrl, the power domains system can enable and disable them separately as well as pull them out of reset. This simplifies the code and lets them run independently while still retaining backwards compatibility with older device trees for those using G1. Signed-off-by: Adam Ford --- drivers/staging/media/hantro/hantro_drv.c | 1 + drivers/staging/media/hantro/hantro_hw.h | 1 + drivers/staging/media/hantro/imx8m_vpu_hw.c | 56 ++++++++++++++++----- 3 files changed, 45 insertions(+), 13 deletions(-) diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c index ab2467998d29..e7afda388ee5 100644 --- a/drivers/staging/media/hantro/hantro_drv.c +++ b/drivers/staging/media/hantro/hantro_drv.c @@ -609,6 +609,7 @@ static const struct of_device_id of_hantro_match[] = { #endif #ifdef CONFIG_VIDEO_HANTRO_IMX8M { .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, }, + { .compatible = "nxp,imx8mq-vpu-g1", .data = &imx8mq_vpu_g1_variant }, { .compatible = "nxp,imx8mq-vpu-g2", .data = &imx8mq_vpu_g2_variant }, #endif #ifdef CONFIG_VIDEO_HANTRO_SAMA5D4 diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h index cff817ca8d22..96b14b43a4af 100644 --- a/drivers/staging/media/hantro/hantro_hw.h +++ b/drivers/staging/media/hantro/hantro_hw.h @@ -299,6 +299,7 @@ enum hantro_enc_fmt { ROCKCHIP_VPU_ENC_FMT_UYVY422 = 3, }; +extern const struct hantro_variant imx8mq_vpu_g1_variant; extern const struct hantro_variant imx8mq_vpu_g2_variant; extern const struct hantro_variant imx8mq_vpu_variant; extern const struct hantro_variant px30_vpu_variant; diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c index 1a43f6fceef9..e0af4b93d3c6 100644 --- a/drivers/staging/media/hantro/imx8m_vpu_hw.c +++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c @@ -223,13 +223,6 @@ static void imx8m_vpu_g1_reset(struct hantro_ctx *ctx) imx8m_soft_reset(vpu, RESET_G1); } -static void imx8m_vpu_g2_reset(struct hantro_ctx *ctx) -{ - struct hantro_dev *vpu = ctx->dev; - - imx8m_soft_reset(vpu, RESET_G2); -} - /* * Supported codec ops. */ @@ -255,17 +248,33 @@ static const struct hantro_codec_ops imx8mq_vpu_codec_ops[] = { }, }; +static const struct hantro_codec_ops imx8mq_vpu_g1_codec_ops[] = { + [HANTRO_MODE_MPEG2_DEC] = { + .run = hantro_g1_mpeg2_dec_run, + .init = hantro_mpeg2_dec_init, + .exit = hantro_mpeg2_dec_exit, + }, + [HANTRO_MODE_VP8_DEC] = { + .run = hantro_g1_vp8_dec_run, + .init = hantro_vp8_dec_init, + .exit = hantro_vp8_dec_exit, + }, + [HANTRO_MODE_H264_DEC] = { + .run = hantro_g1_h264_dec_run, + .init = hantro_h264_dec_init, + .exit = hantro_h264_dec_exit, + }, +}; + static const struct hantro_codec_ops imx8mq_vpu_g2_codec_ops[] = { [HANTRO_MODE_HEVC_DEC] = { .run = hantro_g2_hevc_dec_run, - .reset = imx8m_vpu_g2_reset, .init = hantro_hevc_dec_init, .exit = hantro_hevc_dec_exit, }, [HANTRO_MODE_VP9_DEC] = { .run = hantro_g2_vp9_dec_run, .done = hantro_g2_vp9_dec_done, - .reset = imx8m_vpu_g2_reset, .init = hantro_vp9_dec_init, .exit = hantro_vp9_dec_exit, }, @@ -285,6 +294,10 @@ static const struct hantro_irq imx8mq_g2_irqs[] = { static const char * const imx8mq_clk_names[] = { "g1", "g2", "bus" }; static const char * const imx8mq_reg_names[] = { "g1", "g2", "ctrl" }; +static const char * const imx8mq_g1_clk_names[] = { "g1" }; +static const char * const imx8mq_g1_reg_names[] = { "g1" }; +static const char * const imx8mq_g2_clk_names[] = { "g2" }; +static const char * const imx8mq_g2_reg_names[] = { "g2" }; const struct hantro_variant imx8mq_vpu_variant = { .dec_fmts = imx8m_vpu_dec_fmts, @@ -305,6 +318,23 @@ const struct hantro_variant imx8mq_vpu_variant = { .num_regs = ARRAY_SIZE(imx8mq_reg_names) }; +const struct hantro_variant imx8mq_vpu_g1_variant = { + .dec_fmts = imx8m_vpu_dec_fmts, + .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_dec_fmts), + .postproc_fmts = imx8m_vpu_postproc_fmts, + .num_postproc_fmts = ARRAY_SIZE(imx8m_vpu_postproc_fmts), + .postproc_ops = &hantro_g1_postproc_ops, + .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | + HANTRO_H264_DECODER, + .codec_ops = imx8mq_vpu_g1_codec_ops, + .irqs = imx8mq_irqs, + .num_irqs = ARRAY_SIZE(imx8mq_irqs), + .clk_names = imx8mq_g1_clk_names, + .num_clocks = ARRAY_SIZE(imx8mq_g1_clk_names), + .reg_names = imx8mq_g1_reg_names, + .num_regs = ARRAY_SIZE(imx8mq_g1_reg_names), +}; + const struct hantro_variant imx8mq_vpu_g2_variant = { .dec_offset = 0x0, .dec_fmts = imx8m_vpu_g2_dec_fmts, @@ -314,10 +344,10 @@ const struct hantro_variant imx8mq_vpu_g2_variant = { .postproc_ops = &hantro_g2_postproc_ops, .codec = HANTRO_HEVC_DECODER | HANTRO_VP9_DECODER, .codec_ops = imx8mq_vpu_g2_codec_ops, - .init = imx8mq_vpu_hw_init, - .runtime_resume = imx8mq_runtime_resume, .irqs = imx8mq_g2_irqs, .num_irqs = ARRAY_SIZE(imx8mq_g2_irqs), - .clk_names = imx8mq_clk_names, - .num_clocks = ARRAY_SIZE(imx8mq_clk_names), + .clk_names = imx8mq_g2_clk_names, + .num_clocks = ARRAY_SIZE(imx8mq_g2_clk_names), + .reg_names = imx8mq_g2_reg_names, + .num_regs = ARRAY_SIZE(imx8mq_g2_reg_names), }; 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Wed, 08 Dec 2021 14:50:54 -0800 (PST) Received: from aford-IdeaCentre-A730.lan ([2601:448:8400:9e8:269a:1aa2:f1d9:8dbb]) by smtp.gmail.com with ESMTPSA id t6sm2378751ioi.51.2021.12.08.14.50.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Dec 2021 14:50:53 -0800 (PST) From: Adam Ford To: linux-media@vger.kernel.org Cc: benjamin.gaignard@collabora.com, cphealy@gmail.com, aford@beaconembedded.com, nicolas@ndufresne.ca, Adam Ford , Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Greg Kroah-Hartman , Lucas Stach , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH 07/10] arm64: dts: imx8mm: Fix VPU Hanging Date: Wed, 8 Dec 2021 16:50:26 -0600 Message-Id: <20211208225030.2018923-8-aford173@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211208225030.2018923-1-aford173@gmail.com> References: <20211208225030.2018923-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The vpumix power domain has a reset assigned to it, however when used, it causes a system hang. Testing has shown that it does not appear to be needed anywhere. Fixes: d39d4bb15310 ("arm64: dts: imx8mm: add GPC node") Signed-off-by: Adam Ford --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index c2f3f118f82e..f13d31ebfcbd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -681,7 +681,6 @@ pgc_vpumix: power-domain@6 { clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>; assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>; - resets = <&src IMX8MQ_RESET_VPU_RESET>; }; pgc_vpu_g1: power-domain@7 { From patchwork Wed Dec 8 22:50:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 522329 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DB19C433EF for ; Wed, 8 Dec 2021 22:51:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241093AbhLHWys (ORCPT ); Wed, 8 Dec 2021 17:54:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240933AbhLHWyg (ORCPT ); Wed, 8 Dec 2021 17:54:36 -0500 Received: from mail-io1-xd2d.google.com (mail-io1-xd2d.google.com [IPv6:2607:f8b0:4864:20::d2d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 328B1C0698C5; Wed, 8 Dec 2021 14:51:03 -0800 (PST) Received: by mail-io1-xd2d.google.com with SMTP id y16so4573979ioc.8; Wed, 08 Dec 2021 14:51:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CmYKrk6BY+JkB/hlDlt3q1jLnYSH9OFSxGsl7p/faDY=; b=g/I4+F+JXnzH/TubCYTX76MFnsz+ZsY2EqNzT1DTl+068Y3W5T5xKg5k8zT5az8lhy Kl1+ZyGfSPXGYsIOqQf8C5JdzbjscEZwDhs8hqY9OjcS/hOlW/nPj7nY5BWE9qkGxifi jP0lvHHCW2w5WiW1wrw0hyssDH+Gie8/xln4hA3Gj7ZTNT2JHu7kql7ZzG8+d4PGDuob DKtBRa/yi7ScSqeUjOrx5AHvZy3Lnh8l7Odt1XqODPb+bsaHbBQeR+7VD+DiTph7ShWq VURawxVCm84z8SQ8h74V/wL5wJQsXSfDgCy+YUjjaK/gt8Yfc8nzNjoGF+GXxxStrKde F3MQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CmYKrk6BY+JkB/hlDlt3q1jLnYSH9OFSxGsl7p/faDY=; b=YA4TPmh+e++pM49MZR2tNTF/xe55DeyKyHgiZaEo/HsDu7rr3dWS6AEvCIBsz1jVXB x+5b9BLCiBjE35JROPy5cVUXy4aJGolfKyfKggSq8Fs/CJkj8TV2iSEMJqRpnxW5N1x+ ve29+w28SXwjeWb7RsQJRX8ZvActDRkDgpf9HyaFwG1m0rc+P0FFrIC/9U02+XJsN3NY rvX8PVAi5qOAv0977ByGBAXT1ZoT5A9ey7j9VwPnj+GT+N1OjHI0El+zcyF63c/8djTZ nquDxh3IEFuRyPbE0uPQnGzXZA6l6n6Lyi1SGPsIG8pDIBu1nLisvMgbu52zxcPJDwd1 8DYg== X-Gm-Message-State: AOAM531Ec0Px2TTZCxlp0fvgpUsTXal41aQYi1gCfAnJKy0GoNBfM6cM +I2iep97c7k7PWBSe4jtrC1wd5JeOAmATg== X-Google-Smtp-Source: ABdhPJxiaJAYaeU0Z9vSpYSyUwXqVRBqeiOQq85i/0XyqKBA/pEz+No5RNx2VUK0NfXDTsaq0yOICA== X-Received: by 2002:a05:6602:3c2:: with SMTP id g2mr11081040iov.65.1639003862036; Wed, 08 Dec 2021 14:51:02 -0800 (PST) Received: from aford-IdeaCentre-A730.lan ([2601:448:8400:9e8:269a:1aa2:f1d9:8dbb]) by smtp.gmail.com with ESMTPSA id t6sm2378751ioi.51.2021.12.08.14.51.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Dec 2021 14:51:01 -0800 (PST) From: Adam Ford To: linux-media@vger.kernel.org Cc: benjamin.gaignard@collabora.com, cphealy@gmail.com, aford@beaconembedded.com, nicolas@ndufresne.ca, Adam Ford , Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Greg Kroah-Hartman , Lucas Stach , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH 10/10] arm64: dts: imx8mm: Enable Hantro G1 and G2 video decoders Date: Wed, 8 Dec 2021 16:50:29 -0600 Message-Id: <20211208225030.2018923-11-aford173@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211208225030.2018923-1-aford173@gmail.com> References: <20211208225030.2018923-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org There are two decoders on the i.MX8M Mini controlled by the vpu-blk-ctrl. The G1 supports H264 and VP8 while the G2 support HEVC and VP9. Signed-off-by: Adam Ford --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 28 +++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index f13d31ebfcbd..4682f1f5238d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1196,6 +1196,28 @@ gpu_2d: gpu@38008000 { power-domains = <&pgc_gpu>; }; + vpu_g1: video-codec@38300000 { + compatible = "nxp,imx8mm-vpu-g1"; + reg = <0x38300000 0x10000>; + reg-names = "g1"; + interrupts = ; + interrupt-names = "g1"; + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>; + clock-names = "g1"; + power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>; + }; + + vpu_g2: video-codec@38310000 { + compatible = "nxp,imx8mm-vpu-g2"; + reg = <0x38310000 0x10000>; + reg-names = "g2"; + interrupts = ; + interrupt-names = "g2"; + clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>; + clock-names = "g2"; + power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>; + }; + vpu_blk_ctrl: blk-ctrl@38330000 { compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon"; reg = <0x38330000 0x100>; @@ -1206,6 +1228,12 @@ vpu_blk_ctrl: blk-ctrl@38330000 { <&clk IMX8MM_CLK_VPU_G2_ROOT>, <&clk IMX8MM_CLK_VPU_H1_ROOT>; clock-names = "g1", "g2", "h1"; + assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>, + <&clk IMX8MM_CLK_VPU_G2>; + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, + <&clk IMX8MM_VPU_PLL_OUT>; + assigned-clock-rates = <600000000>, + <600000000>; #power-domain-cells = <1>; };