From patchwork Thu Dec 16 14:13:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 524747 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91A5AC43217 for ; Thu, 16 Dec 2021 14:11:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237754AbhLPOLc (ORCPT ); Thu, 16 Dec 2021 09:11:32 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:4013 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237766AbhLPOLc (ORCPT ); Thu, 16 Dec 2021 09:11:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1639663892; x=1671199892; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=DSaF+rce8x7D+Hdysx6zQcXry3snwSGAnsCyiWnFVNw=; b=a6vGTp6pPnMnaanHuprrsdi6mkZRKe6aAI0yGossFQ2IgLmAwxJ4vtbw 5pZ0Qa2Bz27UI1Kqv0MveKvvmQVByrZkKWGz/z4GCWTJ3PuA8G3Eklv/K 1ayxn2Fzf/eem5olaw2vEF8ntY08wpucx0axZaX+p6wtXXpZGsvMK0PT0 ZbJXJgp2Cl2oCYH2+4tJYDTZeFfPeRknzcoXcSiT6sq7x+VVz2eTocC9Z AyWWiXxtIFnbPCE72oyMN0fhSPPxXVG70s1IB7ICzpxC47ZWne2laWVHG hEOQ7FsS0MV4bPfLO8+pqiVTi4RCJZmEtItX/edNbdc1X2ltsl0gOWhrE g==; IronPort-SDR: 26KbRLjsFVEu7kzGesrBsmYP0+8JS1futd22WR8gy3aIoDjfTvn514C7cV398ehOzpCMwWI7Qm bu/46vEf5o/fxA2u0ncAi/2sgEA1uzEnSTKHHEzKdEWcwzS5Sr1s58b4U/FdflILpztc11apig /yIvXU2kcHMJtOicHwvzM6pD7/WTadoz2vYMoESl1e99e5+IMB3CUmgtPb40ED7y53iVKqHfHD d2Ez/S+LeCJ1j++O99msdShzqB9mqiHIX0AqLZcjPC9KfRMwU3y6AFX0m+MSO2vl+E91CplNlX P4MfJ70NiA9k7f3dEtwEg7wa X-IronPort-AV: E=Sophos;i="5.88,211,1635231600"; d="scan'208";a="142638372" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Dec 2021 07:11:31 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 16 Dec 2021 07:11:30 -0700 Received: from rob-dk-mpu02.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 16 Dec 2021 07:11:28 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , Subject: [PATCH 2/8] ARM: at91: ddr: align macro definitions Date: Thu, 16 Dec 2021 16:13:32 +0200 Message-ID: <20211216141338.35144-3-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211216141338.35144-1-claudiu.beznea@microchip.com> References: <20211216141338.35144-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Align all macro definitions. Signed-off-by: Claudiu Beznea --- include/soc/at91/sama7-ddr.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/soc/at91/sama7-ddr.h b/include/soc/at91/sama7-ddr.h index 13b47e26cdbe..817b360efbb8 100644 --- a/include/soc/at91/sama7-ddr.h +++ b/include/soc/at91/sama7-ddr.h @@ -13,11 +13,11 @@ /* DDR3PHY */ #define DDR3PHY_PIR (0x04) /* DDR3PHY PHY Initialization Register */ -#define DDR3PHY_PIR_DLLBYP (1 << 17) /* DLL Bypass */ +#define DDR3PHY_PIR_DLLBYP (1 << 17) /* DLL Bypass */ #define DDR3PHY_PIR_ITMSRST (1 << 4) /* Interface Timing Module Soft Reset */ -#define DDR3PHY_PIR_DLLLOCK (1 << 2) /* DLL Lock */ +#define DDR3PHY_PIR_DLLLOCK (1 << 2) /* DLL Lock */ #define DDR3PHY_PIR_DLLSRST (1 << 1) /* DLL Soft Rest */ -#define DDR3PHY_PIR_INIT (1 << 0) /* Initialization Trigger */ +#define DDR3PHY_PIR_INIT (1 << 0) /* Initialization Trigger */ #define DDR3PHY_PGCR (0x08) /* DDR3PHY PHY General Configuration Register */ #define DDR3PHY_PGCR_CKDV1 (1 << 13) /* CK# Disable Value */ @@ -65,7 +65,7 @@ #define UDDRC_SWSTAT_SW_DONE_ACK (1 << 0) /* Register programming done */ #define UDDRC_PSTAT (0x3FC) /* UDDRC Port Status Register */ -#define UDDRC_PSTAT_ALL_PORTS (0x1F001F) /* Read + writes outstanding transactions on all ports */ +#define UDDRC_PSTAT_ALL_PORTS (0x1F001F) /* Read + writes outstanding transactions on all ports */ #define UDDRC_PCTRL_0 (0x490) /* UDDRC Port 0 Control Register */ #define UDDRC_PCTRL_1 (0x540) /* UDDRC Port 1 Control Register */ From patchwork Thu Dec 16 14:13:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 524746 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E792C433F5 for ; Thu, 16 Dec 2021 14:11:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237800AbhLPOLl (ORCPT ); Thu, 16 Dec 2021 09:11:41 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:10973 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237784AbhLPOLj (ORCPT ); Thu, 16 Dec 2021 09:11:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1639663899; x=1671199899; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=tdY/B8hRRCxkMeWlkMCdQd3n47eoyj1Pt6q/MH/LGRg=; b=CDQn4W+iVHCzGwtRV7JjXY7ebxEJ+KMJsFzsiIiIKw98vCZ5bsV3W0km jrM+oD6yNQZSxkcqR7XrzyrJ3O0cDSkcUQU7BYax20LRN7SaSH+/fda5g Lq9/vtwdb0MEJEMV6JHGOLU5vZwY8BuU7amYp0B7kAmMQsysyT1Xd5+m6 zkpbmmkpTmFyb1jCIifJTE6FVFrdGEHj7rVaFdSnIm4Qce/4tr5YL9iT1 CqiPJFV8z+HTNrpjCa+68tqMkcYlaL0vDG9cWuTVoswIifwdDuLBvvKU5 M4ENZnsjKmZNHSK4SaL3IbCppUQ1ORFD44QQAE97lrt9YTE1SBiSO1uEp g==; IronPort-SDR: D1+OaanKn564ObLRs5KR4ccJ+quoUtcoMr+IPSWsxCoD8Yhj+DJld1pOPyFs10mBhwh7tJdWEn EoCsIkba+L7sGtzr5NhnDqDRnIojo4toK7MM2bvhsIr88wDlT7PPMyAkagkYfvTMx17wqJ6jUy 6r1rx3LphRXMMCRdN38M11GLFqp20vDVP6YH0bjWZSaLSrE+G/uxtQfFcgM4qesUya99Vv86Kp CfrrHHoVpAvhs3nVhGnzz0oc8/JEA7nsiioTUCl6przIt4p+wduxB2x7x+j3boqokEM0WNi2Tu PDSuuMwbbA6FoijNYr/Uxx8i X-IronPort-AV: E=Sophos;i="5.88,211,1635231600"; d="scan'208";a="147461446" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Dec 2021 07:11:38 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 16 Dec 2021 07:11:36 -0700 Received: from rob-dk-mpu02.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 16 Dec 2021 07:11:34 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , Subject: [PATCH 4/8] ARM: at91: PM: add cpu idle support for sama7g5 Date: Thu, 16 Dec 2021 16:13:34 +0200 Message-ID: <20211216141338.35144-5-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211216141338.35144-1-claudiu.beznea@microchip.com> References: <20211216141338.35144-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add CPU idle support for SAMA7G5. Support will make use of PMC_CPU_RATIO register to divide the CPU clock by 16 before switching it to idle and use automatic self-refresh option of DDR controller. Signed-off-by: Claudiu Beznea Acked-by: Stephen Boyd --- arch/arm/mach-at91/pm.c | 27 ++++++++++++++++++++++++++- include/linux/clk/at91_pmc.h | 4 ++++ include/soc/at91/sama7-ddr.h | 1 + 3 files changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index dd6f4ce3f766..0fd609e26615 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -605,6 +605,30 @@ static void at91sam9_sdram_standby(void) at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); } +static void sama7g5_standby(void) +{ + int pwrtmg, ratio; + + pwrtmg = readl(soc_pm.data.ramc[0] + UDDRC_PWRCTL); + ratio = readl(soc_pm.data.pmc + AT91_PMC_RATIO); + + /* + * Place RAM into self-refresh after a maximum idle clocks. The maximum + * idle clocks is configured by bootloader in + * UDDRC_PWRMGT.SELFREF_TO_X32. + */ + writel(pwrtmg | UDDRC_PWRCTL_SELFREF_EN, + soc_pm.data.ramc[0] + UDDRC_PWRCTL); + /* Divide CPU clock by 16. */ + writel(ratio & ~AT91_PMC_RATIO_RATIO, soc_pm.data.pmc + AT91_PMC_RATIO); + + cpu_do_idle(); + + /* Restore previous configuration. */ + writel(ratio, soc_pm.data.pmc + AT91_PMC_RATIO); + writel(pwrtmg, soc_pm.data.ramc[0] + UDDRC_PWRCTL); +} + struct ramc_info { void (*idle)(void); unsigned int memctrl; @@ -615,6 +639,7 @@ static const struct ramc_info ramc_infos[] __initconst = { { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC}, { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR}, { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR}, + { .idle = sama7g5_standby, }, }; static const struct of_device_id ramc_ids[] __initconst = { @@ -622,7 +647,7 @@ static const struct of_device_id ramc_ids[] __initconst = { { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] }, { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] }, { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] }, - { .compatible = "microchip,sama7g5-uddrc", }, + { .compatible = "microchip,sama7g5-uddrc", .data = &ramc_infos[4], }, { /*sentinel*/ } }; diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h index ccb3f034bfa9..3484309b59bf 100644 --- a/include/linux/clk/at91_pmc.h +++ b/include/linux/clk/at91_pmc.h @@ -78,6 +78,10 @@ #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ #define AT91_CKGR_PLLAR 0x28 /* PLL A Register */ + +#define AT91_PMC_RATIO 0x2c /* Processor clock ratio register [SAMA7G5 only] */ +#define AT91_PMC_RATIO_RATIO (0xf) /* CPU clock ratio. */ + #define AT91_CKGR_PLLBR 0x2c /* PLL B Register */ #define AT91_PMC_DIV (0xff << 0) /* Divider */ #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ diff --git a/include/soc/at91/sama7-ddr.h b/include/soc/at91/sama7-ddr.h index fee1b11bddca..9e17247474fa 100644 --- a/include/soc/at91/sama7-ddr.h +++ b/include/soc/at91/sama7-ddr.h @@ -53,6 +53,7 @@ #define UDDRC_STAT_OPMODE_MSK (0x7 << 0) /* Operating mode mask */ #define UDDRC_PWRCTL (0x30) /* UDDRC Low Power Control Register */ +#define UDDRC_PWRCTL_SELFREF_EN (1 << 0) /* Automatic self-refresh */ #define UDDRC_PWRCTL_SELFREF_SW (1 << 5) /* Software self-refresh */ #define UDDRC_DFIMISC (0x1B0) /* UDDRC DFI Miscellaneous Control Register */ From patchwork Thu Dec 16 14:13:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 524745 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BAF5C43219 for ; Thu, 16 Dec 2021 14:11:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237818AbhLPOLp (ORCPT ); Thu, 16 Dec 2021 09:11:45 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:4047 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237784AbhLPOLn (ORCPT ); Thu, 16 Dec 2021 09:11:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1639663904; x=1671199904; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=b86IW3HhpJSwbuz3dLx8QLN49UnEtkntajIQOuJgw18=; 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Thu, 16 Dec 2021 07:11:42 -0700 Received: from rob-dk-mpu02.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 16 Dec 2021 07:11:39 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , Subject: [PATCH 6/8] ARM: dts: at91: sama7g5: add opps Date: Thu, 16 Dec 2021 16:13:36 +0200 Message-ID: <20211216141338.35144-7-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211216141338.35144-1-claudiu.beznea@microchip.com> References: <20211216141338.35144-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add OPPs for SAMA7G5 along with clock for CPU. Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/sama7g5.dtsi | 37 ++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index 7039311bf678..22352ef5bc72 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -30,6 +30,43 @@ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x0>; + clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + }; + }; + + cpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-90000000 { + opp-hz = /bits/ 64 <90000000>; + opp-microvolt = <1050000 1050000 1225000>; + clock-latency-ns = <320000>; + }; + + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <1050000 1050000 1225000>; + clock-latency-ns = <320000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1050000 1050000 1225000>; + clock-latency-ns = <320000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1150000 1125000 1225000>; + clock-latency-ns = <320000>; + }; + + opp-1000000002 { + opp-hz = /bits/ 64 <1000000002>; + opp-microvolt = <1250000 1225000 1300000>; + clock-latency-ns = <320000>; }; };