From patchwork Wed Dec 22 03:06:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Wu X-Patchwork-Id: 527884 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03F86C433EF for ; Wed, 22 Dec 2021 03:07:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235520AbhLVDHO (ORCPT ); Tue, 21 Dec 2021 22:07:14 -0500 Received: from out28-170.mail.aliyun.com ([115.124.28.170]:59181 "EHLO out28-170.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229741AbhLVDHN (ORCPT ); Tue, 21 Dec 2021 22:07:13 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1124211|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0614957-0.00474604-0.933758; FP=3273083516590370965|1|1|5|0|-1|-1|-1; HT=ay29a033018047193; MF=michael@allwinnertech.com; NM=1; PH=DS; RN=11; RT=11; SR=0; TI=SMTPD_---.MMijYBS_1640142430; Received: from sunxibot.allwinnertech.com(mailfrom:michael@allwinnertech.com fp:SMTPD_---.MMijYBS_1640142430) by smtp.aliyun-inc.com(10.147.40.44); Wed, 22 Dec 2021 11:07:11 +0800 From: Michael Wu To: ulf.hansson@linaro.org, mripard@kernel.org, wens@csie.org, samuel@sholland.org, andre.przywara@arm.com Cc: jernej.skrabec@gmail.com, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Michael Wu Subject: [PATCH 1/3] mmc:sunxi-mmc:add support on discrete device power supply Date: Wed, 22 Dec 2021 11:06:34 +0800 Message-Id: <20211222030634.33816-1-michael@allwinnertech.com> X-Mailer: git-send-email 2.29.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Because some platform has no regulator, only use discrete devices to supply power,For this situation, to use sd/mmc card, we add ocr manually Signed-off-by: Michael Wu --- drivers/mmc/host/sunxi-mmc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c index 2702736a1c57..afeefead6501 100644 --- a/drivers/mmc/host/sunxi-mmc.c +++ b/drivers/mmc/host/sunxi-mmc.c @@ -1300,6 +1300,14 @@ static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host, if (ret) return ret; + /** + * Some platforms has no regulator. Discrete devices are used instead. + * To support sd/mmc card, we need to add ocr manually. + */ + if (!host->mmc->ocr_avail) + host->mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; + + host->reg_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(host->reg_base)) return PTR_ERR(host->reg_base); From patchwork Wed Dec 22 03:15:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Wu X-Patchwork-Id: 527322 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9933BC433EF for ; Wed, 22 Dec 2021 03:15:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242072AbhLVDPs (ORCPT ); Tue, 21 Dec 2021 22:15:48 -0500 Received: from out28-145.mail.aliyun.com ([115.124.28.145]:35462 "EHLO out28-145.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238645AbhLVDPs (ORCPT ); Tue, 21 Dec 2021 22:15:48 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1217135|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0561819-0.000317092-0.943501; FP=7011064724060272356|1|1|5|0|-1|-1|-1; HT=ay29a033018047199; MF=michael@allwinnertech.com; NM=1; PH=DS; RN=11; RT=11; SR=0; TI=SMTPD_---.MMifRmp_1640142945; Received: from sunxibot.allwinnertech.com(mailfrom:michael@allwinnertech.com fp:SMTPD_---.MMifRmp_1640142945) by smtp.aliyun-inc.com(10.147.42.135); Wed, 22 Dec 2021 11:15:45 +0800 From: Michael Wu To: ulf.hansson@linaro.org, mripard@kernel.org, wens@csie.org, samuel@sholland.org, andre.przywara@arm.com Cc: jernej.skrabec@gmail.com, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Michael Wu Subject: [PATCH 2/3] mmc:sunxi-mmc:fix clock division for timing mode Date: Wed, 22 Dec 2021 11:15:21 +0800 Message-Id: <20211222031521.34170-1-michael@allwinnertech.com> X-Mailer: git-send-email 2.29.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org When use new timings,all speed mode requires a doubled module clock if speed mode is ddr,requires a four times module clock When use old timings,only 8 bit ddr requires a doubled module clock Signed-off-by: Michael Wu --- drivers/mmc/host/sunxi-mmc.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c index afeefead6501..7b47ec453fb6 100644 --- a/drivers/mmc/host/sunxi-mmc.c +++ b/drivers/mmc/host/sunxi-mmc.c @@ -774,20 +774,23 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, if (!ios->clock) return 0; - /* - * Under the old timing mode, 8 bit DDR requires the module - * clock to be double the card clock. Under the new timing - * mode, all DDR modes require a doubled module clock. - * - * We currently only support the standard MMC DDR52 mode. - * This block should be updated once support for other DDR - * modes is added. + /** + * When use new timings, all speed mode requires a doubled module clock. + * if speed mode is ddr, requires a four times module clock. + * When use old timings, only 8 bit ddr requires a doubled module clock. */ - if (ios->timing == MMC_TIMING_MMC_DDR52 && - (host->use_new_timings || - ios->bus_width == MMC_BUS_WIDTH_8)) { - div = 2; + if (host->use_new_timings) { clock <<= 1; + if (ios->timing == MMC_TIMING_MMC_DDR52) { + div = 2; + clock <<= 1; + } + } else { + if (ios->timing == MMC_TIMING_MMC_DDR52 && + (ios->bus_width == MMC_BUS_WIDTH_8)) { + div = 2; + clock <<= 1; + } } if (host->use_new_timings && host->cfg->ccu_has_timings_switch) { From patchwork Wed Dec 22 03:15:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Wu X-Patchwork-Id: 527883 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5661C433EF for ; Wed, 22 Dec 2021 03:16:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242114AbhLVDQU (ORCPT ); Tue, 21 Dec 2021 22:16:20 -0500 Received: from out28-74.mail.aliyun.com ([115.124.28.74]:34054 "EHLO out28-74.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242098AbhLVDQR (ORCPT ); Tue, 21 Dec 2021 22:16:17 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07439341|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0152868-0.0082419-0.976471; FP=12208373059880385638|1|1|5|0|-1|-1|-1; HT=ay29a033018047208; MF=michael@allwinnertech.com; NM=1; PH=DS; RN=11; RT=11; SR=0; TI=SMTPD_---.MMkHKcv_1640142974; Received: from sunxibot.allwinnertech.com(mailfrom:michael@allwinnertech.com fp:SMTPD_---.MMkHKcv_1640142974) by smtp.aliyun-inc.com(10.147.40.26); Wed, 22 Dec 2021 11:16:15 +0800 From: Michael Wu To: ulf.hansson@linaro.org, mripard@kernel.org, wens@csie.org, samuel@sholland.org, andre.przywara@arm.com Cc: jernej.skrabec@gmail.com, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Michael Wu Subject: [PATCH 3/3] mmc: sunxi-mmc: use pll to increase clock speed Date: Wed, 22 Dec 2021 11:15:57 +0800 Message-Id: <20211222031557.34242-1-michael@allwinnertech.com> X-Mailer: git-send-email 2.29.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Default clock soucre is 24M,if we want clock over 24M We should use pll as clock source Signed-off-by: Michael Wu --- drivers/mmc/host/sunxi-mmc.c | 57 +++++++++++++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c index 7b47ec453fb6..0039ee58b303 100644 --- a/drivers/mmc/host/sunxi-mmc.c +++ b/drivers/mmc/host/sunxi-mmc.c @@ -756,6 +756,57 @@ static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host, return 0; } +/** + * + * sunxi_clk_get_parent() - get parent pll from dts + * @host: sunxi_mmc_host struct point + * @@clock: the clock frequency that requested + * + * Default clock source is 24M,if we want clock over 24M,We should use + * pll as clock soure + * + * Return:the 0:ok,other:failed + */ +static int sunxi_clk_get_parent(struct sunxi_mmc_host *host, u32 clock) +{ + struct clk *sclk = NULL; + char *sclk_name = NULL; + u32 src_clk = 0; + s32 err = 0; + struct device *dev = mmc_dev(host->mmc); + + sclk = clk_get(dev, "osc24m"); + sclk_name = "osc24m"; + + if (IS_ERR(sclk)) { + dev_err(mmc_dev(host->mmc), "Error to get source clock %s\n", + sclk_name); + return PTR_ERR(sclk); + } + + src_clk = clk_get_rate(sclk); + if (clock > src_clk) { + clk_put(sclk); + sclk = clk_get(dev, "pll_periph"); + sclk_name = "pll_periph"; + } + if (IS_ERR(sclk)) { + dev_err(mmc_dev(host->mmc), "Error to get source clock %s\n", + sclk_name); + return PTR_ERR(sclk); + } + + err = clk_set_parent(host->clk_mmc, sclk); + if (err) { + dev_err(mmc_dev(host->mmc), "set parent failed\n"); + clk_put(sclk); + return err; + } + clk_put(sclk); + return 0; +} + + static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, struct mmc_ios *ios) { @@ -801,7 +852,11 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, return ret; } } - + /** + * No check return value,because dts may not have osc24M, and pll_periph, + * at that time,use default value from clk system + */ + sunxi_clk_get_parent(host, clock); rate = clk_round_rate(host->clk_mmc, clock); if (rate < 0) { dev_err(mmc_dev(mmc), "error rounding clk to %d: %ld\n",