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[209.132.180.67]) by mx.google.com with ESMTP id d14si43039102pln.57.2017.05.29.23.09.23; Mon, 29 May 2017 23:09:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@gmail.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750999AbdE3GJP (ORCPT + 7 others); Tue, 30 May 2017 02:09:15 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:34548 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750993AbdE3GJM (ORCPT ); Tue, 30 May 2017 02:09:12 -0400 Received: by mail-pf0-f195.google.com with SMTP id w69so15604787pfk.1; Mon, 29 May 2017 23:09:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=lvPywTkmGMLZl867ozokmGXjpDbL0pywbqJj0ACGnXo=; b=uniLLXjYhseTTAAPnZWbGpymVoo7Tus2+JTlAF7qxDtXewLjTBmCW2Kz5fjnSyas2W Zu+WcnIBGyy4VLMP5y1xgA9wspt3Vp9mx9pHZuh0kpaaED2P2MMf5P5LeCi2QxcnBQnh uVcys7jVIqtTQyzNRBETYSXn4JiWqobrjkZAeDLTgyhGIqhYTEo1ULkNdarj+61DR9iV g3u6u7dDXaVj1s4NdkegXYfEXSls4ol7T+EpsGgZjzQj81Rxl7lLpzvNBN31w/6sQWmv Xe9SSEAOGqjxPtCWgXwBE16QLscXxPefxahh3CEn/5Gd4Dv0AwGKWxDETnhJ7O6QtLrW 1qWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=lvPywTkmGMLZl867ozokmGXjpDbL0pywbqJj0ACGnXo=; b=gX/2inupaX6eb4bGonGjr3WO6xY9Hd5gRx2EuWNkr9oezGb90umi/Nh+bU26FR4WGn qVmot8ffuI35AzjQNZOJIBYx/b83hhyrvK3fvOCY+d/giB7tQxYd4lZWr/Yz5+g+l7Q9 C0avCy4MJ0I6cFzLyHlBrMLoltmVesWQHJ1ZM9DvNVaSoJmEk/+6nIDtWzDMuOENEjEH jGX+hO6NMX8HhjmjNlnbgG1lufuTuH+oguCIDs6H4BUyfmPRx9chNllATe5WncjMcM6n JPMW5CtAEFza62SfzezVlPpQckVsYLx7T+oXTGq6jGQLJiBVT3GMuU7Sfr3lSUuFCm1Z CPCA== X-Gm-Message-State: AODbwcBU4tqnCmUI9/ZfnAVGkzvwzqcfFlJJPsERFN3lB50YyddQjXGL agajxJ1T/IpJ/g== X-Received: by 10.99.127.89 with SMTP id p25mr23491224pgn.92.1496124551677; Mon, 29 May 2017 23:09:11 -0700 (PDT) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id a72sm20650686pfe.133.2017.05.29.23.09.07 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 29 May 2017 23:09:11 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Tue, 30 May 2017 15:39:04 +0930 From: Joel Stanley To: Philipp Zabel , Rob Herring , Mark Rutland Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Benjamin Herrenschmidt , Andrew Jeffery Subject: [PATCH v2 1/2] dt-bindings: reset: Add bindings for basic reset controller Date: Tue, 30 May 2017 15:38:50 +0930 Message-Id: <20170530060851.29923-2-joel@jms.id.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170530060851.29923-1-joel@jms.id.au> References: <20170530060851.29923-1-joel@jms.id.au> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds the bindings documentation for a basic single-register reset controller. The bindings describe a single 32-bit register that contains up to 32 reset lines, each deasserted by clearing the appropriate bit in the register. Optionally a property can be provided that changes this behaviour to assert on clear. Signed-off-by: Joel Stanley --- V2: Address review from Philipp: - add note about not auto clearing - add property for set to assert behaviour - use a decimal for the bit number Signed-off-by: Joel Stanley --- .../devicetree/bindings/reset/reset-basic.txt | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/reset-basic.txt -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/reset/reset-basic.txt b/Documentation/devicetree/bindings/reset/reset-basic.txt new file mode 100644 index 000000000000..c19e5368be67 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/reset-basic.txt @@ -0,0 +1,43 @@ +Basic single-register reset controller +====================================== + +This describes a generic reset controller where the reset lines are controlled +by single bits within a 32-bit memory location. The memory location is assumed +to be part of a syscon regmap. + +By default the bit will be cleared on deassert. This behaviour can be inverted +with the assert-on-clear property mentioned below. + +The bits are assumed to not be auto-clearing, and therefore can be read back to +determine the status. + +Reset controller required properties: + - compatible: should be "reset-basic" + - #reset-cells: must be set to 1 + - reg: reset register location within regmap + +Reset controller optional properties: + - assert-on-clear: add this property when the hardware should clear (set to 0) + the bit should to assert the reset. + When this property is omitted the default is to set the bit to assert the + reset + +Device node required properties: + - resets phandle + - bit number, counting from zero, for the desired reset line. Max is 31. + +Example: + +syscon { + compatible = "syscon"; + + uart_reset: reset-controller@c { + compatible = "reset-basic"; + #reset-cells = <1>; + reg = <0xc>; + }; +} + +&uart { + resets = <&uart_rest 4>; +}