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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch01.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(2616005)(44832011)(36756003)(336012)(70206006)(186003)(8936002)(26005)(70586007)(8676002)(82310400004)(7636003)(47076005)(5660300002)(107886003)(426003)(4326008)(508600001)(966005)(2906002)(6666004)(356005)(6266002)(42186006)(316002)(1076003)(54906003)(6916009)(36860700001); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2022 22:50:34.8990 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bd2babec-11b0-40a3-5527-08d9d09dc8fa X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT053.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR02MB7922 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Create device tree binding document for partitions and pr isolation on Xilinx Alveo platform. Signed-off-by: Sonal Santan Signed-off-by: Max Zhen Signed-off-by: Lizhi Hou --- .../bindings/fpga/xlnx,alveo-partition.yaml | 76 +++++++++++++++++++ .../fpga/xlnx,alveo-pr-isolation.yaml | 40 ++++++++++ 2 files changed, 116 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,alveo-partition.yaml create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,alveo-pr-isolation.yaml diff --git a/Documentation/devicetree/bindings/fpga/xlnx,alveo-partition.yaml b/Documentation/devicetree/bindings/fpga/xlnx,alveo-partition.yaml new file mode 100644 index 000000000000..ee50cb51d08e --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xlnx,alveo-partition.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/xlnx,alveo-partition.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Alveo platform partition bindings + +description: | + Xilinx Alveo platform is a PCI device and has one or more partitions. A + partition is programmed dynamically and contains a set of hardware + peripherals also referred to as endpoints which appear on the PCI BARs. + This binding is defined for endpoint address translation which uses the + the following encoding: + + 0xIooooooo 0xoooooooo + + Where: + + I = BAR index + oooooo oooooooo = BAR offset + + As a PCI device, the Alveo platform is enumerated at runtime. Thus, + the partition node is created by Alveo device driver. The device driver + gets the BAR base address of the PCI device and creates the 'range' + property for address translation. + +allOf: + - $ref: /schemas/simple-bus.yaml# + +maintainers: + - Lizhi Hou + +properties: + compatible: + contains: + const: xlnx,alveo-partition + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + +patternProperties: + "^.*@[0-9a-f]+$": + description: hardware endpoints belong to this partition. + type: object + +required: + - compatible + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + xrt-part-bus@0 { + compatible = "xlnx,alveo-partition", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xe0000000 0x0 0x2000000 + 0x20000000 0x0 0x0 0xe4200000 0x0 0x40000>; + pr-isolate-ulp@41000 { + compatible = "xlnx,alveo-pr-isolation"; + reg = <0x0 0x41000 0 0x1000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/fpga/xlnx,alveo-pr-isolation.yaml b/Documentation/devicetree/bindings/fpga/xlnx,alveo-pr-isolation.yaml new file mode 100644 index 000000000000..8db949093ee0 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xlnx,alveo-pr-isolation.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/xlnx,alveo-pr-isolation.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Partial Reconfig Isolation for Alveo platforms + +description: | + The Partial Reconfig ensures glitch free operation of the inputs from + a reconfigurable partition during partial reconfiguration on Alveo + platform. + +maintainers: + - Lizhi Hou + +properties: + compatible: + const: xlnx,alveo-pr-isolation + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + pr-isolation-ulp@41000 { + compatible = "xlnx,alveo-pr-isolation"; + reg = <0 0x41000 0 0x1000>; + }; + }; From patchwork Wed Jan 5 22:50:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lizhi Hou X-Patchwork-Id: 530241 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06C36C433F5 for ; Wed, 5 Jan 2022 22:52:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245220AbiAEWwC (ORCPT ); Wed, 5 Jan 2022 17:52:02 -0500 Received: from mail-co1nam11on2050.outbound.protection.outlook.com ([40.107.220.50]:43851 "EHLO NAM11-CO1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S245178AbiAEWvD (ORCPT ); Wed, 5 Jan 2022 17:51:03 -0500 ARC-Seal: i=1; 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CAT:NONE; SFS:(4636009)(36840700001)(46966006)(316002)(42186006)(4326008)(44832011)(70206006)(70586007)(5660300002)(6666004)(1076003)(8676002)(26005)(186003)(2906002)(54906003)(107886003)(6916009)(36756003)(2616005)(8936002)(7636003)(36860700001)(47076005)(356005)(426003)(336012)(82310400004)(6266002)(508600001); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2022 22:51:00.9694 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 726a3ae5-dbd0-4eaf-c128-08d9d09dd886 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT012.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB6810 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Alveo platform has to PCI fucntions. Each function has its own driver attached. The common interfaces are created to support both drivers. Signed-off-by: Sonal Santan Signed-off-by: Max Zhen Signed-off-by: Lizhi Hou --- drivers/fpga/Kconfig | 3 + drivers/fpga/Makefile | 3 + drivers/fpga/xrt/Kconfig | 6 + drivers/fpga/xrt/include/xpartition.h | 28 ++++ drivers/fpga/xrt/lib/Kconfig | 17 +++ drivers/fpga/xrt/lib/Makefile | 15 +++ drivers/fpga/xrt/lib/lib-drv.c | 178 ++++++++++++++++++++++++++ drivers/fpga/xrt/lib/lib-drv.h | 15 +++ 8 files changed, 265 insertions(+) create mode 100644 drivers/fpga/xrt/Kconfig create mode 100644 drivers/fpga/xrt/include/xpartition.h create mode 100644 drivers/fpga/xrt/lib/Kconfig create mode 100644 drivers/fpga/xrt/lib/Makefile create mode 100644 drivers/fpga/xrt/lib/lib-drv.c create mode 100644 drivers/fpga/xrt/lib/lib-drv.h diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 991b3f361ec9..93ae387c97c5 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -243,4 +243,7 @@ config FPGA_MGR_VERSAL_FPGA configure the programmable logic(PL). To compile this as a module, choose M here. + +source "drivers/fpga/xrt/Kconfig" + endif # FPGA diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 0bff783d1b61..5bd41cf4c7ec 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -49,3 +49,6 @@ obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000) += dfl-n3000-nios.o # Drivers for FPGAs which implement DFL obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o + +# XRT drivers for Alveo +obj-$(CONFIG_FPGA_XRT_LIB) += xrt/lib/ diff --git a/drivers/fpga/xrt/Kconfig b/drivers/fpga/xrt/Kconfig new file mode 100644 index 000000000000..04c3bb5aaf4f --- /dev/null +++ b/drivers/fpga/xrt/Kconfig @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Xilinx Alveo FPGA device configuration +# + +source "drivers/fpga/xrt/lib/Kconfig" diff --git a/drivers/fpga/xrt/include/xpartition.h b/drivers/fpga/xrt/include/xpartition.h new file mode 100644 index 000000000000..d72090ddfbee --- /dev/null +++ b/drivers/fpga/xrt/include/xpartition.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2022 Xilinx, Inc. + * + * Authors: + * Lizhi Hou + */ + +#ifndef _XRT_PARTITION_H_ +#define _XRT_PARTITION_H_ + +struct xrt_partition_range { + u32 bar_idx; + u64 base; + u64 size; +}; + +struct xrt_partition_info { + int num_range; + struct xrt_partition_range *ranges; + void *fdt; + u32 fdt_len; +}; + +int xrt_partition_create(struct device *dev, struct xrt_partition_info *info, void **handle); +void xrt_partition_destroy(void *handle); + +#endif diff --git a/drivers/fpga/xrt/lib/Kconfig b/drivers/fpga/xrt/lib/Kconfig new file mode 100644 index 000000000000..73de1f50d5c6 --- /dev/null +++ b/drivers/fpga/xrt/lib/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# XRT Alveo FPGA device configuration +# + +config FPGA_XRT_LIB + tristate "XRT Alveo Driver Library" + depends on HWMON && PCI && HAS_IOMEM && OF + select REGMAP_MMIO + select OF_OVERLAY + help + Select this option to enable Xilinx XRT Alveo driver library. This + library is core infrastructure of XRT Alveo FPGA drivers which + provides functions for working with device nodes, iteration and + lookup of platform devices, common interfaces for platform devices, + plumbing of function call and ioctls between platform devices and + parent partitions. diff --git a/drivers/fpga/xrt/lib/Makefile b/drivers/fpga/xrt/lib/Makefile new file mode 100644 index 000000000000..698877c39657 --- /dev/null +++ b/drivers/fpga/xrt/lib/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. +# +# Authors: Sonal.Santan@xilinx.com +# + +FULL_XRT_PATH=$(srctree)/$(src)/.. + +obj-$(CONFIG_FPGA_XRT_LIB) += xrt-lib.o + +xrt-lib-objs := \ + lib-drv.o + +ccflags-y := -I$(FULL_XRT_PATH)/include diff --git a/drivers/fpga/xrt/lib/lib-drv.c b/drivers/fpga/xrt/lib/lib-drv.c new file mode 100644 index 000000000000..56334b2b9bec --- /dev/null +++ b/drivers/fpga/xrt/lib/lib-drv.c @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020-2022 Xilinx, Inc. + * + * Authors: + * Cheng Zhen + * Lizhi Hou + */ + +#include +#include +#include +#include +#include +#include +#include +#include "xpartition.h" +#include "lib-drv.h" + +#define XRT_PARTITION_FDT_ALIGN 8 +#define XRT_PARTITION_NAME_LEN 64 + +struct xrt_partition { + struct device *dev; + u32 id; + char name[XRT_PARTITION_NAME_LEN]; + void *fdt; + struct property ranges; + struct of_changeset chgset; + bool chgset_applied; + void *dn_mem; +}; + +DEFINE_IDA(xrt_partition_id); + +static int xrt_partition_set_ranges(struct xrt_partition *xp, struct xrt_partition_range *ranges, + int num_range) +{ + __be64 *prop; + u32 prop_len; + int i; + + prop_len = num_range * (sizeof(u64) * 3); + prop = kzalloc(prop_len, GFP_KERNEL); + if (!prop) + return -ENOMEM; + + xp->ranges.name = "ranges"; + xp->ranges.length = prop_len; + xp->ranges.value = prop; + + for (i = 0; i < num_range; i++) { + *prop = cpu_to_be64((u64)ranges[i].bar_idx << 60); + prop++; + *prop = cpu_to_be64(ranges[i].base); + prop++; + *prop = cpu_to_be64(ranges[i].size); + prop++; + } + + return 0; +} + +void xrt_partition_destroy(void *handle) +{ + struct xrt_partition *xp = handle; + + if (xp->chgset_applied) + of_changeset_revert(&xp->chgset); + of_changeset_destroy(&xp->chgset); + + ida_free(&xrt_partition_id, xp->id); + kfree(xp->dn_mem); + kfree(xp->fdt); + kfree(xp->ranges.value); + kfree(xp); +} +EXPORT_SYMBOL_GPL(xrt_partition_destroy); + +int xrt_partition_create(struct device *dev, struct xrt_partition_info *info, void **handle) +{ + struct device_node *parent_dn = NULL, *dn, *part_dn; + struct xrt_partition *xp = NULL; + void *fdt_aligned; + int ret; + + xp = kzalloc(sizeof(*xp), GFP_KERNEL); + if (!xp) + return -ENOMEM; + + ret = ida_alloc(&xrt_partition_id, GFP_KERNEL); + if (ret < 0) { + dev_err(dev, "alloc id failed, ret %d", ret); + kfree(xp); + return ret; + } + xp->id = ret; + of_changeset_init(&xp->chgset); + + parent_dn = of_find_node_by_path("/"); + if (!parent_dn) { + dev_err(dev, "did not find xrt node"); + ret = -EINVAL; + goto failed; + } + + xp->dev = dev; + snprintf(xp->name, XRT_PARTITION_NAME_LEN, "xrt-part@%x", xp->id); + ret = xrt_partition_set_ranges(xp, info->ranges, info->num_range); + if (ret) + goto failed; + + xp->fdt = kmalloc(info->fdt_len + XRT_PARTITION_FDT_ALIGN, GFP_KERNEL); + if (!xp->fdt) { + ret = -ENOMEM; + goto failed; + } + fdt_aligned = PTR_ALIGN(xp->fdt, XRT_PARTITION_FDT_ALIGN); + memcpy(fdt_aligned, info->fdt, info->fdt_len); + + xp->dn_mem = of_fdt_unflatten_tree(fdt_aligned, NULL, &part_dn); + if (!xp->dn_mem) { + ret = -EINVAL; + goto failed; + } + + of_node_get(part_dn); + part_dn->full_name = xp->name; + part_dn->parent = parent_dn; + for (dn = part_dn; dn; dn = of_find_all_nodes(dn)) + of_changeset_attach_node(&xp->chgset, dn); + + ret = of_changeset_add_property(&xp->chgset, part_dn, &xp->ranges); + if (ret) { + dev_err(dev, "failed to add property, ret %d", ret); + goto failed; + } + + ret = of_changeset_apply(&xp->chgset); + if (ret) { + dev_err(dev, "failed to apply changeset, ret %d", ret); + goto failed; + } + xp->chgset_applied = true; + of_node_put(parent_dn); + + ret = of_platform_populate(part_dn, NULL, NULL, dev); + if (ret) { + dev_err(dev, "failed to populate devices, ret %d", ret); + goto failed; + } + + *handle = xp; + return 0; + +failed: + if (parent_dn) + of_node_put(parent_dn); + xrt_partition_destroy(xp); + return ret; +} +EXPORT_SYMBOL_GPL(xrt_partition_create); + +static __init int xrt_lib_init(void) +{ + return 0; +} + +static __exit void xrt_lib_fini(void) +{ +} + +module_init(xrt_lib_init); +module_exit(xrt_lib_fini); + +MODULE_AUTHOR("XRT Team "); +MODULE_DESCRIPTION("Xilinx Alveo IP Lib driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/fpga/xrt/lib/lib-drv.h b/drivers/fpga/xrt/lib/lib-drv.h new file mode 100644 index 000000000000..77ed5c399dcf --- /dev/null +++ b/drivers/fpga/xrt/lib/lib-drv.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2022 Xilinx, Inc. + * + * Authors: + * Cheng Zhen + */ + +#ifndef _LIB_DRV_H_ +#define _LIB_DRV_H_ + +extern u8 __dtb_xrt_begin[]; +extern u8 __dtb_xrt_end[]; + +#endif /* _LIB_DRV_H_ */ From patchwork Wed Jan 5 22:50:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lizhi Hou X-Patchwork-Id: 530240 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E649C433EF for ; Wed, 5 Jan 2022 22:52:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245241AbiAEWww (ORCPT ); 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CAT:NONE; SFS:(4636009)(36840700001)(46966006)(36860700001)(54906003)(6666004)(508600001)(82310400004)(2906002)(6266002)(47076005)(336012)(186003)(107886003)(8676002)(26005)(4326008)(8936002)(44832011)(70586007)(426003)(2616005)(70206006)(1076003)(42186006)(83380400001)(6916009)(36756003)(7636003)(356005)(316002)(5660300002); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2022 22:51:26.7550 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 61e5eb32-7b57-4418-7998-08d9d09de7ec X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT033.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR02MB2861 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The PCIE device driver which attaches to management function on Alveo devices. It instantiates one or more partition. Each partition consists a set of hardward endpoints. A flat device tree is associated with each partition. The first version of this driver uses test version flat device tree and call xrt lib API to unflatten it. Signed-off-by: Sonal Santan Signed-off-by: Max Zhen Signed-off-by: Lizhi Hou --- drivers/fpga/Makefile | 1 + drivers/fpga/xrt/Kconfig | 1 + drivers/fpga/xrt/mgmt/Kconfig | 14 +++ drivers/fpga/xrt/mgmt/Makefile | 16 +++ drivers/fpga/xrt/mgmt/dt-test.dts | 12 +++ drivers/fpga/xrt/mgmt/dt-test.h | 15 +++ drivers/fpga/xrt/mgmt/xmgmt-drv.c | 158 ++++++++++++++++++++++++++++++ 7 files changed, 217 insertions(+) create mode 100644 drivers/fpga/xrt/mgmt/Kconfig create mode 100644 drivers/fpga/xrt/mgmt/Makefile create mode 100644 drivers/fpga/xrt/mgmt/dt-test.dts create mode 100644 drivers/fpga/xrt/mgmt/dt-test.h create mode 100644 drivers/fpga/xrt/mgmt/xmgmt-drv.c diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 5bd41cf4c7ec..544e2144878f 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -52,3 +52,4 @@ obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o # XRT drivers for Alveo obj-$(CONFIG_FPGA_XRT_LIB) += xrt/lib/ +obj-$(CONFIG_FPGA_XRT_XMGMT) += xrt/mgmt/ diff --git a/drivers/fpga/xrt/Kconfig b/drivers/fpga/xrt/Kconfig index 04c3bb5aaf4f..50422f77c6df 100644 --- a/drivers/fpga/xrt/Kconfig +++ b/drivers/fpga/xrt/Kconfig @@ -4,3 +4,4 @@ # source "drivers/fpga/xrt/lib/Kconfig" +source "drivers/fpga/xrt/mgmt/Kconfig" diff --git a/drivers/fpga/xrt/mgmt/Kconfig b/drivers/fpga/xrt/mgmt/Kconfig new file mode 100644 index 000000000000..a978747482be --- /dev/null +++ b/drivers/fpga/xrt/mgmt/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Xilinx XRT FPGA device configuration +# + +config FPGA_XRT_XMGMT + tristate "Xilinx Alveo Management Driver" + depends on FPGA_XRT_LIB + select FPGA_BRIDGE + select FPGA_REGION + help + Select this option to enable XRT PCIe driver for Xilinx Alveo FPGA. + This driver provides interfaces for userspace application to access + Alveo FPGA device. diff --git a/drivers/fpga/xrt/mgmt/Makefile b/drivers/fpga/xrt/mgmt/Makefile new file mode 100644 index 000000000000..c5134bf71cca --- /dev/null +++ b/drivers/fpga/xrt/mgmt/Makefile @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. +# +# Authors: Sonal.Santan@xilinx.com +# + +FULL_XRT_PATH=$(srctree)/$(src)/.. + +obj-$(CONFIG_FPGA_XRT_LIB) += xrt-mgmt.o + +xrt-mgmt-objs := \ + xmgmt-drv.o \ + dt-test.dtb.o + +ccflags-y := -I$(FULL_XRT_PATH)/include diff --git a/drivers/fpga/xrt/mgmt/dt-test.dts b/drivers/fpga/xrt/mgmt/dt-test.dts new file mode 100644 index 000000000000..68dbcb7fd79d --- /dev/null +++ b/drivers/fpga/xrt/mgmt/dt-test.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +/ { + compatible = "xlnx,alveo-partition", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + pr_isolate_ulp@0,41000 { + compatible = "xlnx,alveo-pr-isolation"; + reg = <0x0 0x41000 0x0 0x1000>; + }; +}; diff --git a/drivers/fpga/xrt/mgmt/dt-test.h b/drivers/fpga/xrt/mgmt/dt-test.h new file mode 100644 index 000000000000..6ec4203afbd2 --- /dev/null +++ b/drivers/fpga/xrt/mgmt/dt-test.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2022 Xilinx, Inc. + * + * Authors: + * Lizhi Hou + */ + +#ifndef _DT_TEST_H_ +#define _DT_TEST_H_ + +extern u8 __dtb_dt_test_begin[]; +extern u8 __dtb_dt_test_end[]; + +#endif /* _DT_TEST_H_ */ diff --git a/drivers/fpga/xrt/mgmt/xmgmt-drv.c b/drivers/fpga/xrt/mgmt/xmgmt-drv.c new file mode 100644 index 000000000000..87abe5b86e0b --- /dev/null +++ b/drivers/fpga/xrt/mgmt/xmgmt-drv.c @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Alveo Management Function Driver + * + * Copyright (C) 2020-2022 Xilinx, Inc. + * + * Authors: + * Cheng Zhen + * Lizhi Hou + */ + +#include +#include +#include +#include +#include +#include "xpartition.h" +#include "dt-test.h" + +#define XMGMT_MODULE_NAME "xrt-mgmt" + +#define XMGMT_PDEV(xm) ((xm)->pdev) +#define XMGMT_DEV(xm) (&(XMGMT_PDEV(xm)->dev)) +#define xmgmt_err(xm, fmt, args...) \ + dev_err(XMGMT_DEV(xm), "%s: " fmt, __func__, ##args) +#define xmgmt_warn(xm, fmt, args...) \ + dev_warn(XMGMT_DEV(xm), "%s: " fmt, __func__, ##args) +#define xmgmt_info(xm, fmt, args...) \ + dev_info(XMGMT_DEV(xm), "%s: " fmt, __func__, ##args) +#define xmgmt_dbg(xm, fmt, args...) \ + dev_dbg(XMGMT_DEV(xm), "%s: " fmt, __func__, ##args) +#define XMGMT_DEV_ID(_pcidev) \ + ({ typeof(_pcidev) (pcidev) = (_pcidev); \ + ((pci_domain_nr((pcidev)->bus) << 16) | \ + PCI_DEVID((pcidev)->bus->number, (pcidev)->devfn)); }) + +#define XRT_MAX_READRQ 512 + +/* PCI Device IDs */ +#define PCI_DEVICE_ID_U50 0x5020 +static const struct pci_device_id xmgmt_pci_ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_U50), }, /* Alveo U50 */ + { 0, } +}; + +struct xmgmt { + struct pci_dev *pdev; + void *base_partition; + + bool ready; +}; + +static int xmgmt_config_pci(struct xmgmt *xm) +{ + struct pci_dev *pdev = XMGMT_PDEV(xm); + int rc; + + rc = pcim_enable_device(pdev); + if (rc < 0) { + xmgmt_err(xm, "failed to enable device: %d", rc); + return rc; + } + + rc = pci_enable_pcie_error_reporting(pdev); + if (rc) + xmgmt_warn(xm, "failed to enable AER: %d", rc); + + pci_set_master(pdev); + + rc = pcie_get_readrq(pdev); + if (rc > XRT_MAX_READRQ) + pcie_set_readrq(pdev, XRT_MAX_READRQ); + return 0; +} + +static int xmgmt_probe(struct pci_dev *pdev, const struct pci_device_id *id) +{ + struct xrt_partition_range ranges[PCI_NUM_RESOURCES]; + struct xrt_partition_info xp_info = { 0 }; + struct device *dev = &pdev->dev; + int ret, i, idx = 0; + struct xmgmt *xm; + + xm = devm_kzalloc(dev, sizeof(*xm), GFP_KERNEL); + if (!xm) + return -ENOMEM; + xm->pdev = pdev; + pci_set_drvdata(pdev, xm); + + ret = xmgmt_config_pci(xm); + if (ret) + goto failed; + + for (i = 0; i < PCI_NUM_RESOURCES; i++) { + if (pci_resource_len(pdev, i) > 0) { + ranges[idx].bar_idx = i; + ranges[idx].base = pci_resource_start(pdev, i); + ranges[idx].size = pci_resource_len(pdev, i); + idx++; + } + } + xp_info.num_range = idx; + xp_info.ranges = ranges; + xp_info.fdt = __dtb_dt_test_begin; + xp_info.fdt_len = (u32)(__dtb_dt_test_end - __dtb_dt_test_begin); + ret = xrt_partition_create(&pdev->dev, &xp_info, &xm->base_partition); + if (ret) + goto failed; + + xmgmt_info(xm, "%s started successfully", XMGMT_MODULE_NAME); + return 0; + +failed: + if (xm->base_partition) + xrt_partition_destroy(xm->base_partition); + pci_set_drvdata(pdev, NULL); + return ret; +} + +static void xmgmt_remove(struct pci_dev *pdev) +{ + struct xmgmt *xm = pci_get_drvdata(pdev); + + xrt_partition_destroy(xm->base_partition); + pci_disable_pcie_error_reporting(xm->pdev); + xmgmt_info(xm, "%s cleaned up successfully", XMGMT_MODULE_NAME); +} + +static struct pci_driver xmgmt_driver = { + .name = XMGMT_MODULE_NAME, + .id_table = xmgmt_pci_ids, + .probe = xmgmt_probe, + .remove = xmgmt_remove, +}; + +static int __init xmgmt_init(void) +{ + int res = 0; + + res = pci_register_driver(&xmgmt_driver); + if (res) + return res; + + return 0; +} + +static __exit void xmgmt_exit(void) +{ + pci_unregister_driver(&xmgmt_driver); +} + +module_init(xmgmt_init); +module_exit(xmgmt_exit); + +MODULE_DEVICE_TABLE(pci, xmgmt_pci_ids); +MODULE_AUTHOR("XRT Team "); +MODULE_DESCRIPTION("Xilinx Alveo management function driver"); +MODULE_LICENSE("GPL v2");