From patchwork Thu Jan 6 10:41:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 530353 Delivered-To: patch@linaro.org Received: by 2002:ad5:544f:0:0:0:0:0 with SMTP id a15csp1075308imp; Thu, 6 Jan 2022 03:06:17 -0800 (PST) X-Google-Smtp-Source: ABdhPJzYHvS1Uz24wIjfaDoUdS30994A2MJtb0m79zT2zejf/v/Y/Om98AvcIXYVOKdYc9shpNam X-Received: by 2002:a25:b3c2:: with SMTP id x2mr77443780ybf.565.1641467177255; Thu, 06 Jan 2022 03:06:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1641467177; cv=none; d=google.com; s=arc-20160816; b=hLXiWrEcZQ0j+NSX23rpjHQklI17nRMkcz1K8Iu9ezGES5NJ3t4eMWNtfHtkd8Cond uFmCz7AnrWgNo3iSyi8l25MVHZMUv+hWe3f+dOULo9qdUYkSPtVFdjjFqBGisYoVYo23 GFuLV3hbB4ed9vQe52Xj68fc/8UKiHvU7U8sIYAWvNAgiIicEDiq59Qa2bnYvpm7B3rJ BLloZpChjmzCpPEmCo0kKfZSDyHhI494L7s2B/fHwfP3cjsHbZ9pb7QwAAGeIgTVJrdt 3rrKVUR/zIspq95QPE0rzvcTHTYoNPgZp4vvVEk0jVDiwQ5Rc5Qt41z+egKSg7YQBaAF RcTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from; bh=R3FdjvlF2uaUQLijsRjKRNDByjXsphG7QI+YiTssohw=; b=oxbVI4haADrQ9lEEb/X3wFGZGZf89Abys9m2/vLTErQ0jRIHRWc6ec4t7hUnUE718+ LmWAxRyHg85+t/JGnf7A39qgt1kMCPBZTOlMe5aTprhY0g1G6XSDDPx0e9XV7qcSj3T3 V9epStIS/PWjMH8NxwXSn0skp1dUCR2RuZAL8E0Xczs9+9bFFUvP5d5+dJUMmtVh7Hnd oZIKDf4gmijd7FrZrgiSYUV5zWxQ3v4j4O2/fTDdV4GaR6KwO9KWhGiLr1Znm8I5YJDs OrnwsgDGdBDWJ5+gd2/+pjk7SK8jbfLHcsKvQLjvvQk4+TlbftBryZyNHm6xz7+eYztW BluQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w29si1172833ybi.156.2022.01.06.03.06.17 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jan 2022 03:06:17 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:51750 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5Qb2-00075m-L8 for patch@linaro.org; Thu, 06 Jan 2022 06:06:16 -0500 Received: from eggs.gnu.org ([209.51.188.92]:32844) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDc-0007r3-9k for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:42:05 -0500 Received: from mout.kundenserver.de ([212.227.126.187]:41099) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDT-0004kS-B4 for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:42:04 -0500 Received: from quad ([82.142.12.178]) by mrelayeu.kundenserver.de (mreue009 [212.227.15.167]) with ESMTPSA (Nemesis) id 1MLR5f-1mnTYS3Q3v-00IWrB; Thu, 06 Jan 2022 11:41:44 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PULL 07/27] linux-user: Split out do_prctl and subroutines Date: Thu, 6 Jan 2022 11:41:17 +0100 Message-Id: <20220106104137.732883-8-laurent@vivier.eu> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220106104137.732883-1-laurent@vivier.eu> References: <20220106104137.732883-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:dzprA5NzmlNllchFjHgPBk5X//NKNlzBhYadH7rNQ4/zgjv8pxF ExSksWYiNJoLDAK52DRBGbfC6Kj2zL/EMtdb0gCias/DODPN6FxghT/HuxR10lorgycW0Ou C+qHRXfkHruvCK7s8xK1fyLljPcC59ZmAh5Bmd4E1SDagqsaBrq/f3Mr8CXNJ2e2eJYkI54 1xXpYC/VLJvV3I1su+l5g== X-UI-Out-Filterresults: notjunk:1;V03:K0:/d8DkJx+QCM=:wi1O8TgFwTAhNh/yi8l2kZ fYJXDaTSNPAHfp7bBIsUy1PCZuHdVdKSLORIxsQzzSiyrHvl0L3v2n0esUMstruSd/Pd3X/LK JKS50tTsRn0PRi2jPczKbmH0t1SAjRDAsNPsgE4kspL7YbZY0tmQ5ct5xU8em9GAm63iNetbv z+Kd+00qfde5UyfT0EabJbGvws+jDCljiKqSSpKrM/8v6MecZwyfRTy63Ov0CYUkYkHh/HEyd IQL+pRqxAu5y5nHa++tWtmuWAnxL/FytONa5fO8d4Kn6qrg8X006oOZHCSJFBf1g4qn9yVgcm f0EVTznB/dMgcYAS709RicFzrLVfz/BfBYFhqi/YUIS41oEmUogd4zuGPVVxKLSuB9UwNNbf4 RIXl+Aj9nfeuutDVKDOiYrIMHcZCqkT+EHALJy9YohGvg08h0z1opPHuTpc1Dtfm90gTL8iN+ aZffoofmpIfAWP4w2RSAu9efWrKvB9JEBDC0TGlqRDV9a+wikeMlgT1+xkBcgGrrSs7UVbsya FSiZ+oYJKOziJSizWh61W+2abP6ejLT34dEPG4cGSzKHuhfDVb3YL7U3YeqgQh2CyRqaGXJWL eHSmFRXb8zKTQ/ldRUv7eOKNWU+FBZXbI2ne46hXXexYumfhXyhElfhl8qcBgdMVE+M1B6mJf D48qIM66KaK+CaYyrq44C5MjPcOAwDBIcOh8fopoesaaO1ezSe+N/UivA868QoSCs+rU= Received-SPF: none client-ip=212.227.126.187; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Since the prctl constants are supposed to be generic, supply any that are not provided by the host. Split out subroutines for PR_GET_FP_MODE, PR_SET_FP_MODE, PR_GET_VL, PR_SET_VL, PR_RESET_KEYS, PR_SET_TAGGED_ADDR_CTRL, PR_GET_TAGGED_ADDR_CTRL. Return EINVAL for guests that do not support these options rather than pass them on to the host. Reviewed-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-Id: <20211227150127.2659293-2-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier --- linux-user/aarch64/target_prctl.h | 160 ++++++++++ linux-user/aarch64/target_syscall.h | 23 -- linux-user/alpha/target_prctl.h | 1 + linux-user/arm/target_prctl.h | 1 + linux-user/cris/target_prctl.h | 1 + linux-user/hexagon/target_prctl.h | 1 + linux-user/hppa/target_prctl.h | 1 + linux-user/i386/target_prctl.h | 1 + linux-user/m68k/target_prctl.h | 1 + linux-user/microblaze/target_prctl.h | 1 + linux-user/mips/target_prctl.h | 88 ++++++ linux-user/mips/target_syscall.h | 6 - linux-user/mips64/target_prctl.h | 1 + linux-user/mips64/target_syscall.h | 6 - linux-user/nios2/target_prctl.h | 1 + linux-user/openrisc/target_prctl.h | 1 + linux-user/ppc/target_prctl.h | 1 + linux-user/riscv/target_prctl.h | 1 + linux-user/s390x/target_prctl.h | 1 + linux-user/sh4/target_prctl.h | 1 + linux-user/sparc/target_prctl.h | 1 + linux-user/syscall.c | 433 +++++++++------------------ linux-user/x86_64/target_prctl.h | 1 + linux-user/xtensa/target_prctl.h | 1 + 24 files changed, 414 insertions(+), 320 deletions(-) create mode 100644 linux-user/aarch64/target_prctl.h create mode 100644 linux-user/alpha/target_prctl.h create mode 100644 linux-user/arm/target_prctl.h create mode 100644 linux-user/cris/target_prctl.h create mode 100644 linux-user/hexagon/target_prctl.h create mode 100644 linux-user/hppa/target_prctl.h create mode 100644 linux-user/i386/target_prctl.h create mode 100644 linux-user/m68k/target_prctl.h create mode 100644 linux-user/microblaze/target_prctl.h create mode 100644 linux-user/mips/target_prctl.h create mode 100644 linux-user/mips64/target_prctl.h create mode 100644 linux-user/nios2/target_prctl.h create mode 100644 linux-user/openrisc/target_prctl.h create mode 100644 linux-user/ppc/target_prctl.h create mode 100644 linux-user/riscv/target_prctl.h create mode 100644 linux-user/s390x/target_prctl.h create mode 100644 linux-user/sh4/target_prctl.h create mode 100644 linux-user/sparc/target_prctl.h create mode 100644 linux-user/x86_64/target_prctl.h create mode 100644 linux-user/xtensa/target_prctl.h diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h new file mode 100644 index 000000000000..3f5a5d3933a0 --- /dev/null +++ b/linux-user/aarch64/target_prctl.h @@ -0,0 +1,160 @@ +/* + * AArch64 specific prctl functions for linux-user + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef AARCH64_TARGET_PRCTL_H +#define AARCH64_TARGET_PRCTL_H + +static abi_long do_prctl_get_vl(CPUArchState *env) +{ + ARMCPU *cpu = env_archcpu(env); + if (cpu_isar_feature(aa64_sve, cpu)) { + return ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16; + } + return -TARGET_EINVAL; +} +#define do_prctl_get_vl do_prctl_get_vl + +static abi_long do_prctl_set_vl(CPUArchState *env, abi_long arg2) +{ + /* + * We cannot support either PR_SVE_SET_VL_ONEXEC or PR_SVE_VL_INHERIT. + * Note the kernel definition of sve_vl_valid allows for VQ=512, + * i.e. VL=8192, even though the current architectural maximum is VQ=16. + */ + if (cpu_isar_feature(aa64_sve, env_archcpu(env)) + && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) { + ARMCPU *cpu = env_archcpu(env); + uint32_t vq, old_vq; + + old_vq = (env->vfp.zcr_el[1] & 0xf) + 1; + vq = MAX(arg2 / 16, 1); + vq = MIN(vq, cpu->sve_max_vq); + + if (vq < old_vq) { + aarch64_sve_narrow_vq(env, vq); + } + env->vfp.zcr_el[1] = vq - 1; + arm_rebuild_hflags(env); + return vq * 16; + } + return -TARGET_EINVAL; +} +#define do_prctl_set_vl do_prctl_set_vl + +static abi_long do_prctl_reset_keys(CPUArchState *env, abi_long arg2) +{ + ARMCPU *cpu = env_archcpu(env); + + if (cpu_isar_feature(aa64_pauth, cpu)) { + int all = (PR_PAC_APIAKEY | PR_PAC_APIBKEY | + PR_PAC_APDAKEY | PR_PAC_APDBKEY | PR_PAC_APGAKEY); + int ret = 0; + Error *err = NULL; + + if (arg2 == 0) { + arg2 = all; + } else if (arg2 & ~all) { + return -TARGET_EINVAL; + } + if (arg2 & PR_PAC_APIAKEY) { + ret |= qemu_guest_getrandom(&env->keys.apia, + sizeof(ARMPACKey), &err); + } + if (arg2 & PR_PAC_APIBKEY) { + ret |= qemu_guest_getrandom(&env->keys.apib, + sizeof(ARMPACKey), &err); + } + if (arg2 & PR_PAC_APDAKEY) { + ret |= qemu_guest_getrandom(&env->keys.apda, + sizeof(ARMPACKey), &err); + } + if (arg2 & PR_PAC_APDBKEY) { + ret |= qemu_guest_getrandom(&env->keys.apdb, + sizeof(ARMPACKey), &err); + } + if (arg2 & PR_PAC_APGAKEY) { + ret |= qemu_guest_getrandom(&env->keys.apga, + sizeof(ARMPACKey), &err); + } + if (ret != 0) { + /* + * Some unknown failure in the crypto. The best + * we can do is log it and fail the syscall. + * The real syscall cannot fail this way. + */ + qemu_log_mask(LOG_UNIMP, "PR_PAC_RESET_KEYS: Crypto failure: %s", + error_get_pretty(err)); + error_free(err); + return -TARGET_EIO; + } + return 0; + } + return -TARGET_EINVAL; +} +#define do_prctl_reset_keys do_prctl_reset_keys + +static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2) +{ + abi_ulong valid_mask = PR_TAGGED_ADDR_ENABLE; + ARMCPU *cpu = env_archcpu(env); + + if (cpu_isar_feature(aa64_mte, cpu)) { + valid_mask |= PR_MTE_TCF_MASK; + valid_mask |= PR_MTE_TAG_MASK; + } + + if (arg2 & ~valid_mask) { + return -TARGET_EINVAL; + } + env->tagged_addr_enable = arg2 & PR_TAGGED_ADDR_ENABLE; + + if (cpu_isar_feature(aa64_mte, cpu)) { + switch (arg2 & PR_MTE_TCF_MASK) { + case PR_MTE_TCF_NONE: + case PR_MTE_TCF_SYNC: + case PR_MTE_TCF_ASYNC: + break; + default: + return -EINVAL; + } + + /* + * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. + * Note that the syscall values are consistent with hw. + */ + env->cp15.sctlr_el[1] = + deposit64(env->cp15.sctlr_el[1], 38, 2, arg2 >> PR_MTE_TCF_SHIFT); + + /* + * Write PR_MTE_TAG to GCR_EL1[Exclude]. + * Note that the syscall uses an include mask, + * and hardware uses an exclude mask -- invert. + */ + env->cp15.gcr_el1 = + deposit64(env->cp15.gcr_el1, 0, 16, ~arg2 >> PR_MTE_TAG_SHIFT); + arm_rebuild_hflags(env); + } + return 0; +} +#define do_prctl_set_tagged_addr_ctrl do_prctl_set_tagged_addr_ctrl + +static abi_long do_prctl_get_tagged_addr_ctrl(CPUArchState *env) +{ + ARMCPU *cpu = env_archcpu(env); + abi_long ret = 0; + + if (env->tagged_addr_enable) { + ret |= PR_TAGGED_ADDR_ENABLE; + } + if (cpu_isar_feature(aa64_mte, cpu)) { + /* See do_prctl_set_tagged_addr_ctrl. */ + ret |= extract64(env->cp15.sctlr_el[1], 38, 2) << PR_MTE_TCF_SHIFT; + ret = deposit64(ret, PR_MTE_TAG_SHIFT, 16, ~env->cp15.gcr_el1); + } + return ret; +} +#define do_prctl_get_tagged_addr_ctrl do_prctl_get_tagged_addr_ctrl + +#endif /* AARCH64_TARGET_PRCTL_H */ diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/target_syscall.h index 508219d62aba..a98f568ab4d7 100644 --- a/linux-user/aarch64/target_syscall.h +++ b/linux-user/aarch64/target_syscall.h @@ -19,27 +19,4 @@ struct target_pt_regs { #define TARGET_MCL_FUTURE 2 #define TARGET_MCL_ONFAULT 4 -#define TARGET_PR_SVE_SET_VL 50 -#define TARGET_PR_SVE_GET_VL 51 - -#define TARGET_PR_PAC_RESET_KEYS 54 -# define TARGET_PR_PAC_APIAKEY (1 << 0) -# define TARGET_PR_PAC_APIBKEY (1 << 1) -# define TARGET_PR_PAC_APDAKEY (1 << 2) -# define TARGET_PR_PAC_APDBKEY (1 << 3) -# define TARGET_PR_PAC_APGAKEY (1 << 4) - -#define TARGET_PR_SET_TAGGED_ADDR_CTRL 55 -#define TARGET_PR_GET_TAGGED_ADDR_CTRL 56 -# define TARGET_PR_TAGGED_ADDR_ENABLE (1UL << 0) -/* MTE tag check fault modes */ -# define TARGET_PR_MTE_TCF_SHIFT 1 -# define TARGET_PR_MTE_TCF_NONE (0UL << TARGET_PR_MTE_TCF_SHIFT) -# define TARGET_PR_MTE_TCF_SYNC (1UL << TARGET_PR_MTE_TCF_SHIFT) -# define TARGET_PR_MTE_TCF_ASYNC (2UL << TARGET_PR_MTE_TCF_SHIFT) -# define TARGET_PR_MTE_TCF_MASK (3UL << TARGET_PR_MTE_TCF_SHIFT) -/* MTE tag inclusion mask */ -# define TARGET_PR_MTE_TAG_SHIFT 3 -# define TARGET_PR_MTE_TAG_MASK (0xffffUL << TARGET_PR_MTE_TAG_SHIFT) - #endif /* AARCH64_TARGET_SYSCALL_H */ diff --git a/linux-user/alpha/target_prctl.h b/linux-user/alpha/target_prctl.h new file mode 100644 index 000000000000..eb53b31ad554 --- /dev/null +++ b/linux-user/alpha/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/arm/target_prctl.h b/linux-user/arm/target_prctl.h new file mode 100644 index 000000000000..eb53b31ad554 --- /dev/null +++ b/linux-user/arm/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/cris/target_prctl.h b/linux-user/cris/target_prctl.h new file mode 100644 index 000000000000..eb53b31ad554 --- /dev/null +++ b/linux-user/cris/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/hexagon/target_prctl.h b/linux-user/hexagon/target_prctl.h new file mode 100644 index 000000000000..eb53b31ad554 --- /dev/null +++ b/linux-user/hexagon/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/hppa/target_prctl.h b/linux-user/hppa/target_prctl.h new file mode 100644 index 000000000000..eb53b31ad554 --- /dev/null +++ b/linux-user/hppa/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/i386/target_prctl.h b/linux-user/i386/target_prctl.h new file mode 100644 index 000000000000..eb53b31ad554 --- /dev/null +++ b/linux-user/i386/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/m68k/target_prctl.h b/linux-user/m68k/target_prctl.h new file mode 100644 index 000000000000..eb53b31ad554 --- /dev/null +++ b/linux-user/m68k/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/microblaze/target_prctl.h b/linux-user/microblaze/target_prctl.h new file mode 100644 index 000000000000..eb53b31ad554 --- /dev/null +++ b/linux-user/microblaze/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/mips/target_prctl.h b/linux-user/mips/target_prctl.h new file mode 100644 index 000000000000..e028333db95d --- /dev/null +++ b/linux-user/mips/target_prctl.h @@ -0,0 +1,88 @@ +/* + * MIPS specific prctl functions for linux-user + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef MIPS_TARGET_PRCTL_H +#define MIPS_TARGET_PRCTL_H + +static abi_long do_prctl_get_fp_mode(CPUArchState *env) +{ + abi_long ret = 0; + + if (env->CP0_Status & (1 << CP0St_FR)) { + ret |= PR_FP_MODE_FR; + } + if (env->CP0_Config5 & (1 << CP0C5_FRE)) { + ret |= PR_FP_MODE_FRE; + } + return ret; +} +#define do_prctl_get_fp_mode do_prctl_get_fp_mode + +static abi_long do_prctl_set_fp_mode(CPUArchState *env, abi_long arg2) +{ + bool old_fr = env->CP0_Status & (1 << CP0St_FR); + bool old_fre = env->CP0_Config5 & (1 << CP0C5_FRE); + bool new_fr = arg2 & PR_FP_MODE_FR; + bool new_fre = arg2 & PR_FP_MODE_FRE; + const unsigned int known_bits = PR_FP_MODE_FR | PR_FP_MODE_FRE; + + /* If nothing to change, return right away, successfully. */ + if (old_fr == new_fr && old_fre == new_fre) { + return 0; + } + /* Check the value is valid */ + if (arg2 & ~known_bits) { + return -TARGET_EOPNOTSUPP; + } + /* Setting FRE without FR is not supported. */ + if (new_fre && !new_fr) { + return -TARGET_EOPNOTSUPP; + } + if (new_fr && !(env->active_fpu.fcr0 & (1 << FCR0_F64))) { + /* FR1 is not supported */ + return -TARGET_EOPNOTSUPP; + } + if (!new_fr && (env->active_fpu.fcr0 & (1 << FCR0_F64)) + && !(env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { + /* cannot set FR=0 */ + return -TARGET_EOPNOTSUPP; + } + if (new_fre && !(env->active_fpu.fcr0 & (1 << FCR0_FREP))) { + /* Cannot set FRE=1 */ + return -TARGET_EOPNOTSUPP; + } + + int i; + fpr_t *fpr = env->active_fpu.fpr; + for (i = 0; i < 32 ; i += 2) { + if (!old_fr && new_fr) { + fpr[i].w[!FP_ENDIAN_IDX] = fpr[i + 1].w[FP_ENDIAN_IDX]; + } else if (old_fr && !new_fr) { + fpr[i + 1].w[FP_ENDIAN_IDX] = fpr[i].w[!FP_ENDIAN_IDX]; + } + } + + if (new_fr) { + env->CP0_Status |= (1 << CP0St_FR); + env->hflags |= MIPS_HFLAG_F64; + } else { + env->CP0_Status &= ~(1 << CP0St_FR); + env->hflags &= ~MIPS_HFLAG_F64; + } + if (new_fre) { + env->CP0_Config5 |= (1 << CP0C5_FRE); + if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { + env->hflags |= MIPS_HFLAG_FRE; + } + } else { + env->CP0_Config5 &= ~(1 << CP0C5_FRE); + env->hflags &= ~MIPS_HFLAG_FRE; + } + + return 0; +} +#define do_prctl_set_fp_mode do_prctl_set_fp_mode + +#endif /* MIPS_TARGET_PRCTL_H */ diff --git a/linux-user/mips/target_syscall.h b/linux-user/mips/target_syscall.h index 7a82661fdb47..08ead678104f 100644 --- a/linux-user/mips/target_syscall.h +++ b/linux-user/mips/target_syscall.h @@ -35,10 +35,4 @@ static inline abi_ulong target_shmlba(CPUMIPSState *env) return 0x40000; } -/* MIPS-specific prctl() options */ -#define TARGET_PR_SET_FP_MODE 45 -#define TARGET_PR_GET_FP_MODE 46 -#define TARGET_PR_FP_MODE_FR (1 << 0) -#define TARGET_PR_FP_MODE_FRE (1 << 1) - #endif /* MIPS_TARGET_SYSCALL_H */ diff --git a/linux-user/mips64/target_prctl.h b/linux-user/mips64/target_prctl.h new file mode 100644 index 000000000000..18da9ae6192f --- /dev/null +++ b/linux-user/mips64/target_prctl.h @@ -0,0 +1 @@ +#include "../mips/target_prctl.h" diff --git a/linux-user/mips64/target_syscall.h b/linux-user/mips64/target_syscall.h index 2c7a881c7434..358dc2d64c99 100644 --- a/linux-user/mips64/target_syscall.h +++ b/linux-user/mips64/target_syscall.h @@ -32,10 +32,4 @@ static inline abi_ulong target_shmlba(CPUMIPSState *env) return 0x40000; } -/* MIPS-specific prctl() options */ -#define TARGET_PR_SET_FP_MODE 45 -#define TARGET_PR_GET_FP_MODE 46 -#define TARGET_PR_FP_MODE_FR (1 << 0) -#define TARGET_PR_FP_MODE_FRE (1 << 1) - #endif /* MIPS64_TARGET_SYSCALL_H */ diff --git a/linux-user/nios2/target_prctl.h b/linux-user/nios2/target_prctl.h new file mode 100644 index 000000000000..eb53b31ad554 --- /dev/null +++ b/linux-user/nios2/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/openrisc/target_prctl.h b/linux-user/openrisc/target_prctl.h new file mode 100644 index 000000000000..eb53b31ad554 --- /dev/null +++ b/linux-user/openrisc/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/ppc/target_prctl.h b/linux-user/ppc/target_prctl.h new file mode 100644 index 000000000000..eb53b31ad554 --- /dev/null +++ b/linux-user/ppc/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/riscv/target_prctl.h b/linux-user/riscv/target_prctl.h new file mode 100644 index 000000000000..eb53b31ad554 --- /dev/null +++ b/linux-user/riscv/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/s390x/target_prctl.h b/linux-user/s390x/target_prctl.h new file mode 100644 index 000000000000..eb53b31ad554 --- /dev/null +++ b/linux-user/s390x/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/sh4/target_prctl.h b/linux-user/sh4/target_prctl.h new file mode 100644 index 000000000000..eb53b31ad554 --- /dev/null +++ b/linux-user/sh4/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/sparc/target_prctl.h b/linux-user/sparc/target_prctl.h new file mode 100644 index 000000000000..eb53b31ad554 --- /dev/null +++ b/linux-user/sparc/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 56a3e1718370..0f0f67d56721 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6294,9 +6294,155 @@ abi_long do_arch_prctl(CPUX86State *env, int code, abi_ulong addr) return ret; } #endif /* defined(TARGET_ABI32 */ - #endif /* defined(TARGET_I386) */ +/* + * These constants are generic. Supply any that are missing from the host. + */ +#ifndef PR_SET_NAME +# define PR_SET_NAME 15 +# define PR_GET_NAME 16 +#endif +#ifndef PR_SET_FP_MODE +# define PR_SET_FP_MODE 45 +# define PR_GET_FP_MODE 46 +# define PR_FP_MODE_FR (1 << 0) +# define PR_FP_MODE_FRE (1 << 1) +#endif +#ifndef PR_SVE_SET_VL +# define PR_SVE_SET_VL 50 +# define PR_SVE_GET_VL 51 +# define PR_SVE_VL_LEN_MASK 0xffff +# define PR_SVE_VL_INHERIT (1 << 17) +#endif +#ifndef PR_PAC_RESET_KEYS +# define PR_PAC_RESET_KEYS 54 +# define PR_PAC_APIAKEY (1 << 0) +# define PR_PAC_APIBKEY (1 << 1) +# define PR_PAC_APDAKEY (1 << 2) +# define PR_PAC_APDBKEY (1 << 3) +# define PR_PAC_APGAKEY (1 << 4) +#endif +#ifndef PR_SET_TAGGED_ADDR_CTRL +# define PR_SET_TAGGED_ADDR_CTRL 55 +# define PR_GET_TAGGED_ADDR_CTRL 56 +# define PR_TAGGED_ADDR_ENABLE (1UL << 0) +#endif +#ifndef PR_MTE_TCF_SHIFT +# define PR_MTE_TCF_SHIFT 1 +# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_MASK (3UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TAG_SHIFT 3 +# define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT) +#endif + +#include "target_prctl.h" + +static abi_long do_prctl_inval0(CPUArchState *env) +{ + return -TARGET_EINVAL; +} + +static abi_long do_prctl_inval1(CPUArchState *env, abi_long arg2) +{ + return -TARGET_EINVAL; +} + +#ifndef do_prctl_get_fp_mode +#define do_prctl_get_fp_mode do_prctl_inval0 +#endif +#ifndef do_prctl_set_fp_mode +#define do_prctl_set_fp_mode do_prctl_inval1 +#endif +#ifndef do_prctl_get_vl +#define do_prctl_get_vl do_prctl_inval0 +#endif +#ifndef do_prctl_set_vl +#define do_prctl_set_vl do_prctl_inval1 +#endif +#ifndef do_prctl_reset_keys +#define do_prctl_reset_keys do_prctl_inval1 +#endif +#ifndef do_prctl_set_tagged_addr_ctrl +#define do_prctl_set_tagged_addr_ctrl do_prctl_inval1 +#endif +#ifndef do_prctl_get_tagged_addr_ctrl +#define do_prctl_get_tagged_addr_ctrl do_prctl_inval0 +#endif + +static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, + abi_long arg3, abi_long arg4, abi_long arg5) +{ + abi_long ret; + + switch (option) { + case PR_GET_PDEATHSIG: + { + int deathsig; + ret = get_errno(prctl(PR_GET_PDEATHSIG, &deathsig, + arg3, arg4, arg5)); + if (!is_error(ret) && arg2 && put_user_s32(deathsig, arg2)) { + return -TARGET_EFAULT; + } + return ret; + } + case PR_GET_NAME: + { + void *name = lock_user(VERIFY_WRITE, arg2, 16, 1); + if (!name) { + return -TARGET_EFAULT; + } + ret = get_errno(prctl(PR_GET_NAME, (uintptr_t)name, + arg3, arg4, arg5)); + unlock_user(name, arg2, 16); + return ret; + } + case PR_SET_NAME: + { + void *name = lock_user(VERIFY_READ, arg2, 16, 1); + if (!name) { + return -TARGET_EFAULT; + } + ret = get_errno(prctl(PR_SET_NAME, (uintptr_t)name, + arg3, arg4, arg5)); + unlock_user(name, arg2, 0); + return ret; + } + case PR_GET_FP_MODE: + return do_prctl_get_fp_mode(env); + case PR_SET_FP_MODE: + return do_prctl_set_fp_mode(env, arg2); + case PR_SVE_GET_VL: + return do_prctl_get_vl(env); + case PR_SVE_SET_VL: + return do_prctl_set_vl(env, arg2); + case PR_PAC_RESET_KEYS: + if (arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + return do_prctl_reset_keys(env, arg2); + case PR_SET_TAGGED_ADDR_CTRL: + if (arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + return do_prctl_set_tagged_addr_ctrl(env, arg2); + case PR_GET_TAGGED_ADDR_CTRL: + if (arg2 || arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + return do_prctl_get_tagged_addr_ctrl(env); + case PR_GET_SECCOMP: + case PR_SET_SECCOMP: + /* Disable seccomp to prevent the target disabling syscalls we need. */ + return -TARGET_EINVAL; + default: + /* Most prctl options have no pointer arguments */ + return get_errno(prctl(option, arg2, arg3, arg4, arg5)); + } +} + #define NEW_STACK_SIZE 0x40000 @@ -10635,290 +10781,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, return ret; #endif case TARGET_NR_prctl: - switch (arg1) { - case PR_GET_PDEATHSIG: - { - int deathsig; - ret = get_errno(prctl(arg1, &deathsig, arg3, arg4, arg5)); - if (!is_error(ret) && arg2 - && put_user_s32(deathsig, arg2)) { - return -TARGET_EFAULT; - } - return ret; - } -#ifdef PR_GET_NAME - case PR_GET_NAME: - { - void *name = lock_user(VERIFY_WRITE, arg2, 16, 1); - if (!name) { - return -TARGET_EFAULT; - } - ret = get_errno(prctl(arg1, (unsigned long)name, - arg3, arg4, arg5)); - unlock_user(name, arg2, 16); - return ret; - } - case PR_SET_NAME: - { - void *name = lock_user(VERIFY_READ, arg2, 16, 1); - if (!name) { - return -TARGET_EFAULT; - } - ret = get_errno(prctl(arg1, (unsigned long)name, - arg3, arg4, arg5)); - unlock_user(name, arg2, 0); - return ret; - } -#endif -#ifdef TARGET_MIPS - case TARGET_PR_GET_FP_MODE: - { - CPUMIPSState *env = ((CPUMIPSState *)cpu_env); - ret = 0; - if (env->CP0_Status & (1 << CP0St_FR)) { - ret |= TARGET_PR_FP_MODE_FR; - } - if (env->CP0_Config5 & (1 << CP0C5_FRE)) { - ret |= TARGET_PR_FP_MODE_FRE; - } - return ret; - } - case TARGET_PR_SET_FP_MODE: - { - CPUMIPSState *env = ((CPUMIPSState *)cpu_env); - bool old_fr = env->CP0_Status & (1 << CP0St_FR); - bool old_fre = env->CP0_Config5 & (1 << CP0C5_FRE); - bool new_fr = arg2 & TARGET_PR_FP_MODE_FR; - bool new_fre = arg2 & TARGET_PR_FP_MODE_FRE; - - const unsigned int known_bits = TARGET_PR_FP_MODE_FR | - TARGET_PR_FP_MODE_FRE; - - /* If nothing to change, return right away, successfully. */ - if (old_fr == new_fr && old_fre == new_fre) { - return 0; - } - /* Check the value is valid */ - if (arg2 & ~known_bits) { - return -TARGET_EOPNOTSUPP; - } - /* Setting FRE without FR is not supported. */ - if (new_fre && !new_fr) { - return -TARGET_EOPNOTSUPP; - } - if (new_fr && !(env->active_fpu.fcr0 & (1 << FCR0_F64))) { - /* FR1 is not supported */ - return -TARGET_EOPNOTSUPP; - } - if (!new_fr && (env->active_fpu.fcr0 & (1 << FCR0_F64)) - && !(env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { - /* cannot set FR=0 */ - return -TARGET_EOPNOTSUPP; - } - if (new_fre && !(env->active_fpu.fcr0 & (1 << FCR0_FREP))) { - /* Cannot set FRE=1 */ - return -TARGET_EOPNOTSUPP; - } - - int i; - fpr_t *fpr = env->active_fpu.fpr; - for (i = 0; i < 32 ; i += 2) { - if (!old_fr && new_fr) { - fpr[i].w[!FP_ENDIAN_IDX] = fpr[i + 1].w[FP_ENDIAN_IDX]; - } else if (old_fr && !new_fr) { - fpr[i + 1].w[FP_ENDIAN_IDX] = fpr[i].w[!FP_ENDIAN_IDX]; - } - } - - if (new_fr) { - env->CP0_Status |= (1 << CP0St_FR); - env->hflags |= MIPS_HFLAG_F64; - } else { - env->CP0_Status &= ~(1 << CP0St_FR); - env->hflags &= ~MIPS_HFLAG_F64; - } - if (new_fre) { - env->CP0_Config5 |= (1 << CP0C5_FRE); - if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { - env->hflags |= MIPS_HFLAG_FRE; - } - } else { - env->CP0_Config5 &= ~(1 << CP0C5_FRE); - env->hflags &= ~MIPS_HFLAG_FRE; - } - - return 0; - } -#endif /* MIPS */ -#ifdef TARGET_AARCH64 - case TARGET_PR_SVE_SET_VL: - /* - * We cannot support either PR_SVE_SET_VL_ONEXEC or - * PR_SVE_VL_INHERIT. Note the kernel definition - * of sve_vl_valid allows for VQ=512, i.e. VL=8192, - * even though the current architectural maximum is VQ=16. - */ - ret = -TARGET_EINVAL; - if (cpu_isar_feature(aa64_sve, env_archcpu(cpu_env)) - && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) { - CPUARMState *env = cpu_env; - ARMCPU *cpu = env_archcpu(env); - uint32_t vq, old_vq; - - old_vq = (env->vfp.zcr_el[1] & 0xf) + 1; - vq = MAX(arg2 / 16, 1); - vq = MIN(vq, cpu->sve_max_vq); - - if (vq < old_vq) { - aarch64_sve_narrow_vq(env, vq); - } - env->vfp.zcr_el[1] = vq - 1; - arm_rebuild_hflags(env); - ret = vq * 16; - } - return ret; - case TARGET_PR_SVE_GET_VL: - ret = -TARGET_EINVAL; - { - ARMCPU *cpu = env_archcpu(cpu_env); - if (cpu_isar_feature(aa64_sve, cpu)) { - ret = ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16; - } - } - return ret; - case TARGET_PR_PAC_RESET_KEYS: - { - CPUARMState *env = cpu_env; - ARMCPU *cpu = env_archcpu(env); - - if (arg3 || arg4 || arg5) { - return -TARGET_EINVAL; - } - if (cpu_isar_feature(aa64_pauth, cpu)) { - int all = (TARGET_PR_PAC_APIAKEY | TARGET_PR_PAC_APIBKEY | - TARGET_PR_PAC_APDAKEY | TARGET_PR_PAC_APDBKEY | - TARGET_PR_PAC_APGAKEY); - int ret = 0; - Error *err = NULL; - - if (arg2 == 0) { - arg2 = all; - } else if (arg2 & ~all) { - return -TARGET_EINVAL; - } - if (arg2 & TARGET_PR_PAC_APIAKEY) { - ret |= qemu_guest_getrandom(&env->keys.apia, - sizeof(ARMPACKey), &err); - } - if (arg2 & TARGET_PR_PAC_APIBKEY) { - ret |= qemu_guest_getrandom(&env->keys.apib, - sizeof(ARMPACKey), &err); - } - if (arg2 & TARGET_PR_PAC_APDAKEY) { - ret |= qemu_guest_getrandom(&env->keys.apda, - sizeof(ARMPACKey), &err); - } - if (arg2 & TARGET_PR_PAC_APDBKEY) { - ret |= qemu_guest_getrandom(&env->keys.apdb, - sizeof(ARMPACKey), &err); - } - if (arg2 & TARGET_PR_PAC_APGAKEY) { - ret |= qemu_guest_getrandom(&env->keys.apga, - sizeof(ARMPACKey), &err); - } - if (ret != 0) { - /* - * Some unknown failure in the crypto. The best - * we can do is log it and fail the syscall. - * The real syscall cannot fail this way. - */ - qemu_log_mask(LOG_UNIMP, - "PR_PAC_RESET_KEYS: Crypto failure: %s", - error_get_pretty(err)); - error_free(err); - return -TARGET_EIO; - } - return 0; - } - } - return -TARGET_EINVAL; - case TARGET_PR_SET_TAGGED_ADDR_CTRL: - { - abi_ulong valid_mask = TARGET_PR_TAGGED_ADDR_ENABLE; - CPUARMState *env = cpu_env; - ARMCPU *cpu = env_archcpu(env); - - if (cpu_isar_feature(aa64_mte, cpu)) { - valid_mask |= TARGET_PR_MTE_TCF_MASK; - valid_mask |= TARGET_PR_MTE_TAG_MASK; - } - - if ((arg2 & ~valid_mask) || arg3 || arg4 || arg5) { - return -TARGET_EINVAL; - } - env->tagged_addr_enable = arg2 & TARGET_PR_TAGGED_ADDR_ENABLE; - - if (cpu_isar_feature(aa64_mte, cpu)) { - switch (arg2 & TARGET_PR_MTE_TCF_MASK) { - case TARGET_PR_MTE_TCF_NONE: - case TARGET_PR_MTE_TCF_SYNC: - case TARGET_PR_MTE_TCF_ASYNC: - break; - default: - return -EINVAL; - } - - /* - * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. - * Note that the syscall values are consistent with hw. - */ - env->cp15.sctlr_el[1] = - deposit64(env->cp15.sctlr_el[1], 38, 2, - arg2 >> TARGET_PR_MTE_TCF_SHIFT); - - /* - * Write PR_MTE_TAG to GCR_EL1[Exclude]. - * Note that the syscall uses an include mask, - * and hardware uses an exclude mask -- invert. - */ - env->cp15.gcr_el1 = - deposit64(env->cp15.gcr_el1, 0, 16, - ~arg2 >> TARGET_PR_MTE_TAG_SHIFT); - arm_rebuild_hflags(env); - } - return 0; - } - case TARGET_PR_GET_TAGGED_ADDR_CTRL: - { - abi_long ret = 0; - CPUARMState *env = cpu_env; - ARMCPU *cpu = env_archcpu(env); - - if (arg2 || arg3 || arg4 || arg5) { - return -TARGET_EINVAL; - } - if (env->tagged_addr_enable) { - ret |= TARGET_PR_TAGGED_ADDR_ENABLE; - } - if (cpu_isar_feature(aa64_mte, cpu)) { - /* See above. */ - ret |= (extract64(env->cp15.sctlr_el[1], 38, 2) - << TARGET_PR_MTE_TCF_SHIFT); - ret = deposit64(ret, TARGET_PR_MTE_TAG_SHIFT, 16, - ~env->cp15.gcr_el1); - } - return ret; - } -#endif /* AARCH64 */ - case PR_GET_SECCOMP: - case PR_SET_SECCOMP: - /* Disable seccomp to prevent the target disabling syscalls we - * need. */ - return -TARGET_EINVAL; - default: - /* Most prctl options have no pointer arguments */ - return get_errno(prctl(arg1, arg2, arg3, arg4, arg5)); - } + return do_prctl(cpu_env, arg1, arg2, arg3, arg4, arg5); break; #ifdef TARGET_NR_arch_prctl case TARGET_NR_arch_prctl: diff --git a/linux-user/x86_64/target_prctl.h b/linux-user/x86_64/target_prctl.h new file mode 100644 index 000000000000..eb53b31ad554 --- /dev/null +++ b/linux-user/x86_64/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ diff --git a/linux-user/xtensa/target_prctl.h b/linux-user/xtensa/target_prctl.h new file mode 100644 index 000000000000..eb53b31ad554 --- /dev/null +++ b/linux-user/xtensa/target_prctl.h @@ -0,0 +1 @@ +/* No special prctl support required. */ From patchwork Thu Jan 6 10:41:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 530345 Delivered-To: patch@linaro.org Received: by 2002:ad5:544f:0:0:0:0:0 with SMTP id a15csp1063641imp; Thu, 6 Jan 2022 02:49:32 -0800 (PST) X-Google-Smtp-Source: ABdhPJxODdY95AWykbXdvagzHHYL7keYgb99AYacNc5BfGtO0lDYdOspYcP6obszqrLJh+Awf/eb X-Received: by 2002:a25:2543:: with SMTP id l64mr59153069ybl.4.1641466172506; Thu, 06 Jan 2022 02:49:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1641466172; cv=none; d=google.com; s=arc-20160816; b=Zc8wVAuukZobxosrOY7IbATJ1En+Y5Am2hlz4o4+cy5HTuV06/7D/sFRD/p3UMtd3T puIZ0EPsRUeYHCAdw5iov8EcTeM5wDwPH1pBbs+F6u1QWVu57u0ebtYsjIr9J3NIRjwX o7euYUcp6wsk46zcW5Rj7Pf4GyjEifclPr6LAqeTzzIj9CNUa/KyjkQC93yrc6q5/eqQ a1ZOeISW2bvm+g8jZIPK/1aKDNRt53vqenrYLQDRD1/+3AeOU3zzwh2/Y78OFmyoUNWR bmkavt0Y7uqx2n78OuoRTzSS4kWDdEtKFebv5qNwDBOioFsZKxuK+NOmz60mH1wBbL/D +qnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from; bh=GApDC1N8c1BGUmV12Srd9lwt2mic5QW4KHLkpQG7TPo=; b=k2T5IPgxk4hc1R8e1A3FMasDQAXEZ5OLa9PN0JIBpoV4Xo2SXZItaOEmE+NyDj6Yv9 toHm4Jb+MR3V6eC8d74u71FCx8ravvbWjTDpacxTrCm1LiDnFQX6vUBzlMxAH88sOJCc SPTWX2djK9Elt9xEufD40h7AWn0LcS6ZTIZPg+GhuFvO41bHr5QmX2H2g8REMVq4LIcB PkVm1xraxs4ZvWK2FZze3LmJ0tzjz//vQ6NfHeXqRKeuXdDijZaYsK1tfKZ4i5BLzOdH PK8ret31sVDYxnTM4lNWsHCQZEOx4TxTkbLwOIcGIhpo5AMf9AnaIX3cPzVN4J8scaN9 M3hA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q11si1760727ybu.314.2022.01.06.02.49.32 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jan 2022 02:49:32 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:60888 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5QKp-0008EP-Uu for patch@linaro.org; Thu, 06 Jan 2022 05:49:31 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60978) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDZ-0007ng-GK for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:42:01 -0500 Received: from mout.kundenserver.de ([212.227.126.131]:59497) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDS-0004k4-99 for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:42:01 -0500 Received: from quad ([82.142.12.178]) by mrelayeu.kundenserver.de (mreue009 [212.227.15.167]) with ESMTPSA (Nemesis) id 1MFsdD-1nAhOx3J0B-00HM7h; Thu, 06 Jan 2022 11:41:44 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PULL 08/27] linux-user: Disable more prctl subcodes Date: Thu, 6 Jan 2022 11:41:18 +0100 Message-Id: <20220106104137.732883-9-laurent@vivier.eu> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220106104137.732883-1-laurent@vivier.eu> References: <20220106104137.732883-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:exBT1H1rszwPC8FJI7xe18/8Sp8Ud31mxEMUrECmJ9fB3wCQ71j vvocxS9CmbansrTdY0gBkhLYEe7jHO08uQSeMVQJFjoFRNcKk1q4LiOKFvPoAhsNNaWqhnL xOxAbZ4Zb+DoFoCplTCXvToJpKnCrkB/eKRGPIoZACSPp8kzwud1odI+XCr/ThHtbspG7kU cU8TPj2Eyf6S+412vZ+Pw== X-UI-Out-Filterresults: notjunk:1;V03:K0:AuFtkTdDAo8=:4E1TezFD/uBa4nyFpEbkPA DoBOuHT03Xv+Fp7ObpnYGLd9za+AkkULRWILmwEeYFQkKeTO8uX8BNd4MJZ92k9cn0YHF984S gNpZKIpDCRdsR/IOyaJkBzRj4qlDoqKPW87u74zyVljGZHUjDyqMA6vAy3VHYp6J0v26iptFF ZBeanFLWRcfPqeAbi0Y9tTzoy/w36vB1bSKkG9vGWYW/+koBJEcRQ4enpTYIcDq+j5bovUdND e6FAlN1UCt6QJ+CcA6Ib80KsEtmn/nljAKmEk5nYUAgf1uRrV2G+Poer005b6YcBgYFwziAqT Y5y5AWfLq2InBylh0VyHJ0r27TsCkQa/ezMlqL0uOE8LavMGSTtbM2a4DUtbe3/K1rQCgOS5w /0uOWE7h6YHIgfcXKNl3YdW3TRXsgojCwb358/yli/ENo0Pu9IsYdg8Kh0LnLL/FgaB5DP2Xr KiqZ3EKwMaxrYjuk9rN9tJdiKwAJ4seZe0M+pVySdyObq8OyzItDokoZR357oznbB04UmSYgu O3O9DZbQ88m4Nc1r806tj2WQfEhKIMehN9GrH/nj15UKmSOPeiVjxWIninqUi37OliWVT9V6a TxXuQ2W4ilfrY2Oxsekxmeb/nilkGyahQk32cgCjB2kwIkrVwbZBYTTiNVJfYdJhY0wVGPg4t rijtSdSs/QSgXvRsAolXqZH4jB4q5WRWdQQy5HUm0ZgMmsK/4f56/R0jbToNuyPhXzC4= Received-SPF: none client-ip=212.227.126.131; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Create a list of subcodes that we want to pass on, a list of subcodes that should not be passed on because they would affect the running qemu itself, and a list that probably could be implemented but require extra work. Do not pass on unknown subcodes. Reviewed-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-Id: <20211227150127.2659293-3-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier --- linux-user/syscall.c | 58 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 55 insertions(+), 3 deletions(-) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 0f0f67d56721..d868ef291085 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6337,6 +6337,13 @@ abi_long do_arch_prctl(CPUX86State *env, int code, abi_ulong addr) # define PR_MTE_TAG_SHIFT 3 # define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT) #endif +#ifndef PR_SET_IO_FLUSHER +# define PR_SET_IO_FLUSHER 57 +# define PR_GET_IO_FLUSHER 58 +#endif +#ifndef PR_SET_SYSCALL_USER_DISPATCH +# define PR_SET_SYSCALL_USER_DISPATCH 59 +#endif #include "target_prctl.h" @@ -6433,13 +6440,58 @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, return -TARGET_EINVAL; } return do_prctl_get_tagged_addr_ctrl(env); + + case PR_GET_DUMPABLE: + case PR_SET_DUMPABLE: + case PR_GET_KEEPCAPS: + case PR_SET_KEEPCAPS: + case PR_GET_TIMING: + case PR_SET_TIMING: + case PR_GET_TIMERSLACK: + case PR_SET_TIMERSLACK: + case PR_MCE_KILL: + case PR_MCE_KILL_GET: + case PR_GET_NO_NEW_PRIVS: + case PR_SET_NO_NEW_PRIVS: + case PR_GET_IO_FLUSHER: + case PR_SET_IO_FLUSHER: + /* Some prctl options have no pointer arguments and we can pass on. */ + return get_errno(prctl(option, arg2, arg3, arg4, arg5)); + + case PR_GET_CHILD_SUBREAPER: + case PR_SET_CHILD_SUBREAPER: + case PR_GET_SPECULATION_CTRL: + case PR_SET_SPECULATION_CTRL: + case PR_GET_TID_ADDRESS: + /* TODO */ + return -TARGET_EINVAL; + + case PR_GET_FPEXC: + case PR_SET_FPEXC: + /* Was used for SPE on PowerPC. */ + return -TARGET_EINVAL; + + case PR_GET_ENDIAN: + case PR_SET_ENDIAN: + case PR_GET_FPEMU: + case PR_SET_FPEMU: + case PR_SET_MM: case PR_GET_SECCOMP: case PR_SET_SECCOMP: - /* Disable seccomp to prevent the target disabling syscalls we need. */ + case PR_SET_SYSCALL_USER_DISPATCH: + case PR_GET_THP_DISABLE: + case PR_SET_THP_DISABLE: + case PR_GET_TSC: + case PR_SET_TSC: + case PR_GET_UNALIGN: + case PR_SET_UNALIGN: + /* Disable to prevent the target disabling stuff we need. */ return -TARGET_EINVAL; + default: - /* Most prctl options have no pointer arguments */ - return get_errno(prctl(option, arg2, arg3, arg4, arg5)); + qemu_log_mask(LOG_UNIMP, "Unsupported prctl: " TARGET_ABI_FMT_ld "\n", + option); + return -TARGET_EINVAL; } } From patchwork Thu Jan 6 10:41:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 530342 Delivered-To: patch@linaro.org Received: by 2002:ad5:544f:0:0:0:0:0 with SMTP id a15csp1063306imp; Thu, 6 Jan 2022 02:48:54 -0800 (PST) X-Google-Smtp-Source: ABdhPJxIBFmcmGs8yd1n/p3txjwMwqTyfG5+QoBfuXApoCZzcLSeLoaRUfgVG37yqbGd/WCfcC3Y X-Received: by 2002:a25:b87:: with SMTP id 129mr66620370ybl.467.1641466134662; Thu, 06 Jan 2022 02:48:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1641466134; cv=none; d=google.com; s=arc-20160816; b=pdwQYaLVjA5fau9dj9jzDoLtnt4eOjdRF2oFuhdSicsBZQBynNLZIXAtiEmyjXUk0J D5hV87ZvHmqj2KaAldwAxnk/XfPm5i3WqPzhbc7F48r/+dm2/IQh0lagWy+EYOyyybDS 4g/6DPzWZOPPiX1+bfpQgRlJxGOJ8u0DlGrFo5NtJSvVwstQYV8/MyUW1ajROUp6+mh6 2DfCZiZq2QVlRHS+cw2d67p79k4c8qGgdDt/YHVDZV5t7LE4L27RlTIZnAUizOmu70pD XLMInDVGBP9Xg5hCMJWwVYO8ymoLb9/HVT1hbMCoyj29jPiNRgozhZK15kc6Obogn5M/ n63w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from; bh=hNL20rSi9Ds99+Zi1dnrj2CMusbibxRXI2BbRGhzTOo=; b=0992XOpjnXDHwfkJen5A/T1RqawZydTUsklXAYY1O+Dqv/UjhdDJHsS9WBLPc5i/r4 91R52A6jgKa0a6AzVSx9Gzi0/od8EREh4GX6NMRAhAvyDP2deGZBrQq1tOjgL/YjB65O YVxT+IQgdI88fZKH3cCAllHehloKVrzcJqlCAEqdU+6uEo2A9uFZdlKHzfxGquKYmDqk kj9ueRfD2jq0sZvOfWoEU8vPLHVFx4Xd5Kz0lm32ju61NZcCy2Wr5mdfr5jLXQQe9oMC ORFIM9chPENYGXVlIwQ8Fwlg7PnmGY+GaXo+Ed5wspRcBNJwWymNF4Ih/s+Kw2gwGwlC 02ow== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x4si1108772ybs.12.2022.01.06.02.48.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jan 2022 02:48:54 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:59290 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5QKE-00077A-3r for patch@linaro.org; Thu, 06 Jan 2022 05:48:54 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60772) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDU-0007cM-I0 for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:41:56 -0500 Received: from mout.kundenserver.de ([212.227.126.134]:59737) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDO-0004jJ-Ps for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:41:56 -0500 Received: from quad ([82.142.12.178]) by mrelayeu.kundenserver.de (mreue009 [212.227.15.167]) with ESMTPSA (Nemesis) id 1MYeV1-1mrvX01FHX-00Vi8v; Thu, 06 Jan 2022 11:41:45 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PULL 09/27] linux-user: Add code for PR_GET/SET_UNALIGN Date: Thu, 6 Jan 2022 11:41:19 +0100 Message-Id: <20220106104137.732883-10-laurent@vivier.eu> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220106104137.732883-1-laurent@vivier.eu> References: <20220106104137.732883-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:TUEOrmH/hZxcqE7J5ubrNdT0wFbaHHCSStrL48mcd29iat3HgwG UpVGX4ga/6cgyFaOwfITFOPPQ0IuY2RNm2ICdC3a9G4OZtwtVgDBQsLzsJ6EF9vV7Okdnek 6iGzVccwIWQhdNjYvK2RosijCPmfahIjld02Hv9Th/bk3G+78pL0Ttc30RRSEwhYyg8Jq9b ThyVvWgJpWrm3+SGdPTuA== X-UI-Out-Filterresults: notjunk:1;V03:K0:O80bhlyC4cM=:gB6xfR4360QT8qahfDKlMB bX4ybgM9YzD4lo7lzTFI+6087c2MEXVQl7TB5btFV64WY4LBfZJt0VsZrVmdXOrlnfRsQNf/y Tngx+xWtDgrvxSedKZ59TuyXpChp2GNPnYKiE8m15Wi9DItcJWWL2oVV4UPj8V3y0e2/ZaOJR 3OjSSKRBNe+Fp9LLo4XG99Kxbaphd0lGOh08zSYt+p9QHfzapk39CP1k0zxBudKpqsDMsyq14 0R8FtsELFhTR4ABZchP5hBNfT8YpPqy9oXjajwhK7sH58erqKXPt8u83gY5Y4ahsKBk5GhU3r ABERrP04Oxh66MI+bcHGkypbmQX/1M9dfSPoom3eD17WqrSnJWAV3aMmEzPvKxsOq1kT6gvl+ EPIfESPZrVOIzl1iiINN5fBWWwKEXbx4yv09lw64COZFqe2xCdyDJU3GADxkDzXPWrmYu6wCC IwnGczHE+xd96Sjzb+pg+VFkPEtnxeIM9rGikAtxH3mrxStzQ77SGKCv4xdw4mayJcky5ekAf qwmAvdy7/2cmsEUfRWuqyCXVS0zvP5qSKfN2c0E774d6A8ZQd/RkN1Jm/KYsrstfv+hRNC7ex 2PBG5xRKjhyBANHMwAosX3YwmsnikTze0DplhO/KF1DyziLV+QtMzGy+Ceu57Mp2iDZ3koqAq dsdVok1a5d8fetyoJqpYYks1BN9H2jUkHIjjA5669LmptdnlOmcu+avLTGK/4heWnhc8= Received-SPF: none client-ip=212.227.126.134; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Laurent Vivier , Warner Losh , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This requires extra work for each target, but adds the common syscall code, and the necessary flag in CPUState. Reviewed-by: Warner Losh Reviewed-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-Id: <20211227150127.2659293-4-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier --- cpu.c | 20 ++++++++++++----- include/hw/core/cpu.h | 3 +++ linux-user/generic/target_prctl_unalign.h | 27 +++++++++++++++++++++++ linux-user/syscall.c | 13 +++++++++-- 4 files changed, 56 insertions(+), 7 deletions(-) create mode 100644 linux-user/generic/target_prctl_unalign.h diff --git a/cpu.c b/cpu.c index 945dd3dded4a..016bf06a1aec 100644 --- a/cpu.c +++ b/cpu.c @@ -174,13 +174,23 @@ void cpu_exec_unrealizefn(CPUState *cpu) cpu_list_remove(cpu); } +/* + * This can't go in hw/core/cpu.c because that file is compiled only + * once for both user-mode and system builds. + */ static Property cpu_common_props[] = { -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + /* + * Create a property for the user-only object, so users can + * adjust prctl(PR_SET_UNALIGN) from the command-line. + * Has no effect if the target does not support the feature. + */ + DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState, + prctl_unalign_sigbus, false), +#else /* - * Create a memory property for softmmu CPU object, - * so users can wire up its memory. (This can't go in hw/core/cpu.c - * because that file is compiled only once for both user-mode - * and system builds.) The default if no link is set up is to use + * Create a memory property for softmmu CPU object, so users can + * wire up its memory. The default if no link is set up is to use * the system address space. */ DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index e948e81f1a97..76ab3b851c87 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -413,6 +413,9 @@ struct CPUState { bool ignore_memory_transaction_failures; + /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */ + bool prctl_unalign_sigbus; + struct hax_vcpu_state *hax_vcpu; struct hvf_vcpu_state *hvf; diff --git a/linux-user/generic/target_prctl_unalign.h b/linux-user/generic/target_prctl_unalign.h new file mode 100644 index 000000000000..bc3b83af2a6b --- /dev/null +++ b/linux-user/generic/target_prctl_unalign.h @@ -0,0 +1,27 @@ +/* + * Generic prctl unalign functions for linux-user + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef GENERIC_TARGET_PRCTL_UNALIGN_H +#define GENERIC_TARGET_PRCTL_UNALIGN_H + +static abi_long do_prctl_get_unalign(CPUArchState *env, target_long arg2) +{ + CPUState *cs = env_cpu(env); + uint32_t res = PR_UNALIGN_NOPRINT; + if (cs->prctl_unalign_sigbus) { + res |= PR_UNALIGN_SIGBUS; + } + return put_user_u32(res, arg2); +} +#define do_prctl_get_unalign do_prctl_get_unalign + +static abi_long do_prctl_set_unalign(CPUArchState *env, target_long arg2) +{ + env_cpu(env)->prctl_unalign_sigbus = arg2 & PR_UNALIGN_SIGBUS; + return 0; +} +#define do_prctl_set_unalign do_prctl_set_unalign + +#endif /* GENERIC_TARGET_PRCTL_UNALIGN_H */ diff --git a/linux-user/syscall.c b/linux-user/syscall.c index d868ef291085..b5112891b046 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6378,6 +6378,12 @@ static abi_long do_prctl_inval1(CPUArchState *env, abi_long arg2) #ifndef do_prctl_get_tagged_addr_ctrl #define do_prctl_get_tagged_addr_ctrl do_prctl_inval0 #endif +#ifndef do_prctl_get_unalign +#define do_prctl_get_unalign do_prctl_inval1 +#endif +#ifndef do_prctl_set_unalign +#define do_prctl_set_unalign do_prctl_inval1 +#endif static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, abi_long arg3, abi_long arg4, abi_long arg5) @@ -6441,6 +6447,11 @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, } return do_prctl_get_tagged_addr_ctrl(env); + case PR_GET_UNALIGN: + return do_prctl_get_unalign(env, arg2); + case PR_SET_UNALIGN: + return do_prctl_set_unalign(env, arg2); + case PR_GET_DUMPABLE: case PR_SET_DUMPABLE: case PR_GET_KEEPCAPS: @@ -6483,8 +6494,6 @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, case PR_SET_THP_DISABLE: case PR_GET_TSC: case PR_SET_TSC: - case PR_GET_UNALIGN: - case PR_SET_UNALIGN: /* Disable to prevent the target disabling stuff we need. */ return -TARGET_EINVAL; From patchwork Thu Jan 6 10:41:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 530344 Delivered-To: patch@linaro.org Received: by 2002:ad5:544f:0:0:0:0:0 with SMTP id a15csp1063574imp; Thu, 6 Jan 2022 02:49:26 -0800 (PST) X-Google-Smtp-Source: ABdhPJy9xquZ/njfaRCSbhpszr/fP8lbomKjWNtBamR7v2tDY69bRI2/m5aly247AAKofddKDpeC X-Received: by 2002:a25:1483:: with SMTP id 125mr23449908ybu.548.1641466166719; Thu, 06 Jan 2022 02:49:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1641466166; cv=none; d=google.com; s=arc-20160816; b=eYLNCMjuME5ZNQQydqEF8UxErq0AVRE75Rk6sseu76mclWADJ7gfW7s3ItQfOxorZQ 3zrXDcU+PDpt8jIWLVX8tGA+91KvFixGdce/M0ZDL77uW0ZN0zU4DZIdUc++X7zzOfXz LCJBMYuQl5HHRB0LnHaAwyg5F+qL2ihEKbNzV9HFTLBTtoj/aI37SRxOyKE90hZ9HT1N ZGMm9rHYUE2GnP8Kd4laTsFqBc5blEitPyXzNwoLQbL245ZI4HCDv1wc2mKfFKGx8rik r15xEser4k1KeMrjqrE1nU+p9QHuqFy9IQhOf+T3kUi4BGQSCKMIefnB+XqKvNu1omOg 7qwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from; bh=ra9/8AqVbV2xwi1hco8qXoYnjytfRg8GhJNSi0cq9aM=; b=VGPZW74uEx7u1VIki0wIt90g0WXk0AYRmsa1iwHkKOLC8F7tpKIVZkhFs4Af3gcy+x o4pQ1gR9liDiwg3OvyBPpHXSYPiZRzjWITqNPWQMsINSdnXG5EgjXRVqGGfCKbCiH2x0 qKZ5hPLzYEe/UeQWnMHg3OL+IR6nQOzP7mCBOJA4G2CmBGVWjDzFe4vCN86FrnmFnEDV nzNSCf1N5HMswKqMsjx8vJnpDhwujNztesgz6J9uXLmOLWeaixjI1BoVoUwtJVnb8Ku4 1SyIQNfn3/j3sDjQf9s4e/GkaSieXqB5uRT6QT7AncadQ9wdTgJyVSZtQZC9RhUEjpsX 80ag== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n138si1085104ybf.39.2022.01.06.02.49.26 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jan 2022 02:49:26 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:60466 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5QKk-0007vZ-4o for patch@linaro.org; Thu, 06 Jan 2022 05:49:26 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60896) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDX-0007hT-LG for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:41:59 -0500 Received: from mout.kundenserver.de ([212.227.126.131]:42329) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDQ-0004ie-Hz for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:41:58 -0500 Received: from quad ([82.142.12.178]) by mrelayeu.kundenserver.de (mreue009 [212.227.15.167]) with ESMTPSA (Nemesis) id 1MlwBf-1medty3FQp-00ixdp; Thu, 06 Jan 2022 11:41:45 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PULL 10/27] target/alpha: Implement prctl_unalign_sigbus Date: Thu, 6 Jan 2022 11:41:20 +0100 Message-Id: <20220106104137.732883-11-laurent@vivier.eu> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220106104137.732883-1-laurent@vivier.eu> References: <20220106104137.732883-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:/w194w6AUFk/pPGKVSE8+c/8Eou0scAsl6irsRgodjQ0NHtE7Sn H6X4R/3oSwy8U58hfJI6bCsN4GuhgyvjQ76dS7EbowUL9jngnRVTrjRRe9+lwpOpKPUZqNn H8dVZReDy+uNSHeRn38izaZW99+gK+U/TqfzqtfxZcCGtLuFBLNB8gREj0EYcWqt1O3AN2X /8z0L4ZkJ8fudUyA7cQ+g== X-UI-Out-Filterresults: notjunk:1;V03:K0:oQS3X5SDv0Q=:SWezH0zMpSpoBB0lf3ODxd E8O8jS9XoSgjzO1pc3FRg3IfX1s6mQU+O54ffQn3BQ2SFoUIUXCnVU6GHGp0XN9JD+/WWTuz9 BPDg/3eE8USmYChEWNHiu8/3zV3hxeQe4y7sAEnDM1xMuoQb+ieIiaDDG3xvQmoqDnKEB2f27 p/MuvkXrmglbhin9HTLoreeexCswl0sH++ORmLfXoQ/fH2OObuNivdP7VbKR9/PcU0GTiO23g D8ufBSigI0zaz1rSZrbwaQRKM5FgRflF8Dn/7pVIwV0snclGctDXRkqDhHxg46Y/v5qkglK6g UJMcQIng1VqRRoTFwKVtJkDtp7VshTYecAx1r+kZW43zTcrZ3lT/tNXoDSe02t+y1PGNcmGBn Gr66cuw6OH/ejVW0mAQVGD0bXdh/mcW3WV3VV49EexlD5W8NkIZ9r/d80m5LOeTy+AEW2i8db a+Iz5e+nWeFegRVkk2ONEQYhsVgVGqVW4A0h82uzLULX/ZSfr2ctEM1DbeDIcGHLoqRAejBQN bw/cPMhO54Mpr5pMTR8KzYZb24ny9HLDkDRflu8jqAAY/bDxPUZA2oLPVVN4xI7dtf7jX38wy bDh5v8azkIgLBuemLCitO47B2L1bIuv4b9nSxMia+cpVncd9EGE5WT5vrIwr59+ZhEMhzuJyW /cdmFLnmL5a0W39y1elk14LHn4+iVo6HO4G+zZeqOG6EV5j3mIW2ACpCiPlkjYP3PXfE= Received-SPF: none client-ip=212.227.126.131; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap. Signed-off-by: Richard Henderson Reviewed-by: Laurent Vivier Message-Id: <20211227150127.2659293-5-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier --- linux-user/alpha/target_prctl.h | 2 +- target/alpha/cpu.h | 5 +++++ target/alpha/translate.c | 31 ++++++++++++++++++++++--------- 3 files changed, 28 insertions(+), 10 deletions(-) diff --git a/linux-user/alpha/target_prctl.h b/linux-user/alpha/target_prctl.h index eb53b31ad554..5629ddbf39cd 100644 --- a/linux-user/alpha/target_prctl.h +++ b/linux-user/alpha/target_prctl.h @@ -1 +1 @@ -/* No special prctl support required. */ +#include "../generic/target_prctl_unalign.h" diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index afd975c87801..e81921150392 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -383,6 +383,8 @@ enum { #define ENV_FLAG_TB_MASK \ (ENV_FLAG_PAL_MODE | ENV_FLAG_PS_USER | ENV_FLAG_FEN) +#define TB_FLAG_UNALIGN (1u << 1) + static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch) { int ret = env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_IDX; @@ -470,6 +472,9 @@ static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc, *pc = env->pc; *cs_base = 0; *pflags = env->flags & ENV_FLAG_TB_MASK; +#ifdef CONFIG_USER_ONLY + *pflags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif } #ifdef CONFIG_USER_ONLY diff --git a/target/alpha/translate.c b/target/alpha/translate.c index a4c3f43e720a..208ae5fbd50d 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -45,7 +45,9 @@ typedef struct DisasContext DisasContext; struct DisasContext { DisasContextBase base; -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + MemOp unalign; +#else uint64_t palbr; #endif uint32_t tbflags; @@ -68,6 +70,12 @@ struct DisasContext { TCGv sink; }; +#ifdef CONFIG_USER_ONLY +#define UNALIGN(C) (C)->unalign +#else +#define UNALIGN(C) 0 +#endif + /* Target-specific return values from translate_one, indicating the state of the TB. Note that DISAS_NEXT indicates that we are not exiting the TB. */ @@ -270,7 +278,7 @@ static inline DisasJumpType gen_invalid(DisasContext *ctx) static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv_i32 tmp32 = tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); gen_helper_memory_to_f(dest, tmp32); tcg_temp_free_i32(tmp32); } @@ -278,7 +286,7 @@ static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv addr) static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv tmp = tcg_temp_new(); - tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); gen_helper_memory_to_g(dest, tmp); tcg_temp_free(tmp); } @@ -286,14 +294,14 @@ static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv addr) static void gen_lds(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv_i32 tmp32 = tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); gen_helper_memory_to_s(dest, tmp32); tcg_temp_free_i32(tmp32); } static void gen_ldt(DisasContext *ctx, TCGv dest, TCGv addr) { - tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); } static void gen_load_fp(DisasContext *ctx, int ra, int rb, int32_t disp16, @@ -324,6 +332,8 @@ static void gen_load_int(DisasContext *ctx, int ra, int rb, int32_t disp16, tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16); if (clear) { tcg_gen_andi_i64(addr, addr, ~0x7); + } else if (!locked) { + op |= UNALIGN(ctx); } dest = ctx->ir[ra]; @@ -340,7 +350,7 @@ static void gen_stf(DisasContext *ctx, TCGv src, TCGv addr) { TCGv_i32 tmp32 = tcg_temp_new_i32(); gen_helper_f_to_memory(tmp32, addr); - tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); tcg_temp_free_i32(tmp32); } @@ -348,7 +358,7 @@ static void gen_stg(DisasContext *ctx, TCGv src, TCGv addr) { TCGv tmp = tcg_temp_new(); gen_helper_g_to_memory(tmp, src); - tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); tcg_temp_free(tmp); } @@ -356,13 +366,13 @@ static void gen_sts(DisasContext *ctx, TCGv src, TCGv addr) { TCGv_i32 tmp32 = tcg_temp_new_i32(); gen_helper_s_to_memory(tmp32, src); - tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); tcg_temp_free_i32(tmp32); } static void gen_stt(DisasContext *ctx, TCGv src, TCGv addr) { - tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); } static void gen_store_fp(DisasContext *ctx, int ra, int rb, int32_t disp16, @@ -383,6 +393,8 @@ static void gen_store_int(DisasContext *ctx, int ra, int rb, int32_t disp16, tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16); if (clear) { tcg_gen_andi_i64(addr, addr, ~0x7); + } else { + op |= UNALIGN(ctx); } src = load_gpr(ctx, ra); @@ -2942,6 +2954,7 @@ static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) #ifdef CONFIG_USER_ONLY ctx->ir = cpu_std_ir; + ctx->unalign = (ctx->tbflags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); #else ctx->palbr = env->palbr; ctx->ir = (ctx->tbflags & ENV_FLAG_PAL_MODE ? cpu_pal_ir : cpu_std_ir); From patchwork Thu Jan 6 10:41:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 530346 Delivered-To: patch@linaro.org Received: by 2002:ad5:544f:0:0:0:0:0 with SMTP id a15csp1064954imp; Thu, 6 Jan 2022 02:51:55 -0800 (PST) X-Google-Smtp-Source: ABdhPJxTpfEoRSc3agJQQ/Ti3lrcOJAagdioEZThxDcRs++2ODwbo5uYKokdQnztfJ1dqqh6711t X-Received: by 2002:a5b:552:: with SMTP id r18mr71140565ybp.30.1641466315716; Thu, 06 Jan 2022 02:51:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1641466315; cv=none; d=google.com; s=arc-20160816; b=peQWoFOub7V743qQ20oALlKnBWEgpqnFP//u3hEFwFRZ/QiGB1PhYtKcnCVB6MTXCL 0vy2N5wXLIHxExurNucoT9KWvu8Hz6QSgxZ1MwsZvmpkUOvba6YpAVA8jbjvaTFTPAmK IagcgXHZtljO6libZS/hSJEntDsczDK+L5BiAMc8Isd9U52avEcSRy2rpU6dpN54leqh u8HkQ/KsMSqWLnaFaQ3IDSlZT/s6vmgLta/hQvlO8wAvex7jl3nqGI9wgxfSxPMbK+NE tQsDA6q+hmKq4aGDM5ZOBCCaEdQWumUXYKIwqisr8hRzddUmBGGNcvXDtYKxadWQb4ZU a62Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from; bh=4QxM044tHsEgv6L2gXumiIaiYcBO+LPIeCtk5Aq/s7Y=; b=VBtoqCW9ClMsePDG9BPAj3rDBOs/mbBMHwE3Gm5WDLevUloIZbUvwGnZt+IRfLfZhL YKopD+qZCF6EtmqcOcvKjt/P6jL4iO0yPqW47VypWhSpu4SL3oSjb4Z5NZf2mcapjWjJ rVKTa6WGmGp6hXOr/GCVNl8BJeX1Z3y5GYn6Kfh4B9i4M145//zwyfsqgxdi4PUCvne2 pSuZuT12oNfkEWbTYrlRRyvMtWndmWHrCa/6KBPD9ZZPaN23pFAP/tRlIgawKKb/p9Go ENWaTMBFlme2v5H2Ms2wkvaH1nxYv4gvxy68KuFlkB5k6JZVVJVLEhy1QsirsvUKEaSf Dcnw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 198si1142789ybe.639.2022.01.06.02.51.55 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jan 2022 02:51:55 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:39488 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5QN9-0004WR-3R for patch@linaro.org; Thu, 06 Jan 2022 05:51:55 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60824) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDV-0007dX-Nc for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:41:57 -0500 Received: from mout.kundenserver.de ([212.227.126.130]:34251) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDO-0004ii-Q9 for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:41:57 -0500 Received: from quad ([82.142.12.178]) by mrelayeu.kundenserver.de (mreue009 [212.227.15.167]) with ESMTPSA (Nemesis) id 1Mgvj3-1mT5C30ruv-00hNCZ; Thu, 06 Jan 2022 11:41:46 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PULL 11/27] target/hppa: Implement prctl_unalign_sigbus Date: Thu, 6 Jan 2022 11:41:21 +0100 Message-Id: <20220106104137.732883-12-laurent@vivier.eu> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220106104137.732883-1-laurent@vivier.eu> References: <20220106104137.732883-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:kiwqWioa8pwH62vt2bj2DK8vZUodcrthSFww0+yA4gGf7F37kT7 Scm4mzJPzGjTU7zWY8HhnkDwdop+QIjYtN69i+X35I+AJpRXy8KEu9LS+uSWVzSP4KTsu5z us69Oz+Kemk2mn4tomo3Gx/tDJJ19Ybh/VuNFcZ7B0F4sU9APturR7XeeIAP14qLncxZhQ6 dI0peWLWzOz6xyPqvH1Aw== X-UI-Out-Filterresults: notjunk:1;V03:K0:9KTJbbrXwsY=:U0o8JBZbyFi+M/6JHRuTUa KfqJPaWY9AggjFa71hQYg5QVIRyOstHiznM7PZGrpp0Lc5wLoslyyFEOipRCiNNPTf3PDau5c t/+Mr7jf6HDi8BXeigWOwLXEXCwJ6GxOGAQp5y8PDsNuAVmA5DxaBeHb06dq0cJanov0zVv38 ctPcCAurv3J91A8NpCnTB+DCzX1E/UsPtbPlmn2+5rLXIn50Wo6KQBVCx2IGseHlKi74dndpB uDWSI6XLwIgRi7QWkcK3IMvWmGf4lcZ3Rv43DydyDGf1Tbrrh4O/D4e5/CBG8obvFqydA0K3f ModusbRllON/yYkGsQlufvTxQkxkrHkBFPPIPi6/8KUBQe3znbkXAzQ5pUO8rubNBoBIgTofu DydYZje8DZduWke6bSLj6koQy4Y86VsPaRWWOBfRi3ZJ/jhcUWuCuKu6c4gZjuY9kJrLkXiLU 89awLaolkmdbJC1ooEAv0yrPqwqMmUkEPM7h6wJLUQOQqQ9fR94APU3gK7PXc1Tf3EIpFl2gj lgIn1iRqAARcKHt8m2JkTy/G/aJFOIV5gAMlmGR1pliBOpouA1WnsXMSgA+mKOy0uAVl6N5kY p3m9JJhuoB80KNaUoPoimMnOFyL6q9+aMj/UKGdzTa8tiiAUWJFrSbqIbqIdJEyyU2MI8uNyX hsI1/wHoZ0voSiN29NscXm5QYo08ZBGctpXlHT3tl0lvVYwuuDUPknPBy1b2aRDch0pE= Received-SPF: none client-ip=212.227.126.130; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap. Signed-off-by: Richard Henderson Reviewed-by: Laurent Vivier Message-Id: <20211227150127.2659293-6-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier --- linux-user/hppa/target_prctl.h | 2 +- target/hppa/cpu.h | 5 ++++- target/hppa/translate.c | 19 +++++++++++++++---- 3 files changed, 20 insertions(+), 6 deletions(-) diff --git a/linux-user/hppa/target_prctl.h b/linux-user/hppa/target_prctl.h index eb53b31ad554..5629ddbf39cd 100644 --- a/linux-user/hppa/target_prctl.h +++ b/linux-user/hppa/target_prctl.h @@ -1 +1 @@ -/* No special prctl support required. */ +#include "../generic/target_prctl_unalign.h" diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 294fd7297f91..45fd338b02f8 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -259,12 +259,14 @@ static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc, return hppa_form_gva_psw(env->psw, spc, off); } -/* Since PSW_{I,CB} will never need to be in tb->flags, reuse them. +/* + * Since PSW_{I,CB} will never need to be in tb->flags, reuse them. * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the * same value. */ #define TB_FLAG_SR_SAME PSW_I #define TB_FLAG_PRIV_SHIFT 8 +#define TB_FLAG_UNALIGN 0x400 static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, target_ulong *cs_base, @@ -279,6 +281,7 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, #ifdef CONFIG_USER_ONLY *pc = env->iaoq_f & -4; *cs_base = env->iaoq_b & -4; + flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; #else /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ flags |= env->psw & (PSW_W | PSW_C | PSW_D); diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 952027a28e12..a2392a1b64a4 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -274,8 +274,18 @@ typedef struct DisasContext { int mmu_idx; int privilege; bool psw_n_nonzero; + +#ifdef CONFIG_USER_ONLY + MemOp unalign; +#endif } DisasContext; +#ifdef CONFIG_USER_ONLY +#define UNALIGN(C) (C)->unalign +#else +#define UNALIGN(C) 0 +#endif + /* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */ static int expand_sm_imm(DisasContext *ctx, int val) { @@ -1475,7 +1485,7 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb, form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx == MMU_PHYS_IDX); - tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -1493,7 +1503,7 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb, form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx == MMU_PHYS_IDX); - tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -1511,7 +1521,7 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb, form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx == MMU_PHYS_IDX); - tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -1529,7 +1539,7 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb, form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx == MMU_PHYS_IDX); - tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -4107,6 +4117,7 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->mmu_idx = MMU_USER_IDX; ctx->iaoq_f = ctx->base.pc_first | MMU_USER_IDX; ctx->iaoq_b = ctx->base.tb->cs_base | MMU_USER_IDX; + ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); #else ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; ctx->mmu_idx = (ctx->tb_flags & PSW_D ? ctx->privilege : MMU_PHYS_IDX); From patchwork Thu Jan 6 10:41:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 530341 Delivered-To: patch@linaro.org Received: by 2002:ad5:544f:0:0:0:0:0 with SMTP id a15csp1062305imp; Thu, 6 Jan 2022 02:47:07 -0800 (PST) X-Google-Smtp-Source: ABdhPJxXJJKkWO626c7Z8/Fzvk3TBGShAe7g5wcSY6riU35SQTf8f8LCL4ohRw85UWKTNTQyeh39 X-Received: by 2002:a05:6122:1687:: with SMTP id 7mr20104791vkl.5.1641466027665; Thu, 06 Jan 2022 02:47:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1641466027; cv=none; d=google.com; s=arc-20160816; b=imeQcaNhM3vR/Hn+0mywqhipQXeICExVpWA0NnHJqxJyIaiNqnAQcdzRt2ayHmNjxL 2PpB1Cn+TBUv2LTsreAkLOTUBRzqFdt7M0TDRb9XChlTps+MPPJqk3ck56gOU8jYAB8G UKnGrV8fJlHnsxge14p5BM3ULUbCnWBVs7PiLdQ9fcykFWHI17iVVUlmN3Wv2JbWMWzm OFJBERhzQtrbjErANE/cMYfjSrpyx/oPdXhMmzb+E24XrIOW0Dn5lkMgvSvaSX4fKoaB wDQNx51rdonMTcPE3XPPwmsjitBteo3neQn9zXVMiurL79gLtdR1WVMgpHw14S9UcPa+ P8Rg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from; bh=+hHyz5h43hWYpTDg+QhX9zzMS7VkUX/Nt1eeH47ezkk=; b=f0M1f6InRXQt1u8C4i28KOYa8XltKGlDMEuY3qXa073e8b0YhHLsPevGYhSiTGWmFO 9xpccJJUjmN6SePG7ZuO38l33RHI+lYfIKZoL32FpccfgxagHaGcqz8EWwkSBeGZbCYi ndicDYNd9CG2Wu7HQhUDC7ADa5A4WLtGlhveLuaTFgOKv3t9/vUdbZe4vr8W8hS9UD3l MOWx2DQgiddT6w4rTtK6ufJA5IYsjaQuC7Y0ib3L12fossQcE5qbmVBKGR3kBM2d5jwU gpQ0Vqtpy51BRp/2tsSanITCbf1uJ8QgJHDbsAb+5rlyteolmYAZcFswwhCIDZC+Hc8x Rhag== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s6si219342vsh.287.2022.01.06.02.47.07 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jan 2022 02:47:07 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:52160 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5QIT-00029T-Ll for patch@linaro.org; Thu, 06 Jan 2022 05:47:05 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60846) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDW-0007eJ-5Q for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:41:58 -0500 Received: from mout.kundenserver.de ([212.227.126.130]:49959) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDO-0004it-QT for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:41:57 -0500 Received: from quad ([82.142.12.178]) by mrelayeu.kundenserver.de (mreue009 [212.227.15.167]) with ESMTPSA (Nemesis) id 1MKbc4-1morGY2nVM-00L126; Thu, 06 Jan 2022 11:41:46 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PULL 12/27] target/sh4: Implement prctl_unalign_sigbus Date: Thu, 6 Jan 2022 11:41:22 +0100 Message-Id: <20220106104137.732883-13-laurent@vivier.eu> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220106104137.732883-1-laurent@vivier.eu> References: <20220106104137.732883-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:qK3IYWdXldFT2qs49de94K53jCPohICyfYxMavRxHaGPipJZUI3 v7fxV4WWtOGYlZqDPO/SyOTIsSRFe/yDNz3Hs385v4chADh+EdpC39bc9HgPyHd27gNlc3K dYwRhigvRmN4y7lLCji4Nz4RnO6v2e4rLcj8OtVMX14qOGyjm94rEt0n9OqgeH6frE/kO4i D3LFPOcgnHlRKTZjjJ/Og== X-UI-Out-Filterresults: notjunk:1;V03:K0:iCTP67RgF8k=:pMbXKyIdwmMTT/QB8FghSA qV3BorisA4cTYu49oQNIms+EXNs0FyyUSusCNCQ58JX61FOExpEEETgdzST6IMOqlaN2Sf9bn XJi61m6Ie12/+wJh6u+kBygwGv9aX19wZWOfl+NaZyyDtMeu2LrU+txeeyjWPtRUIjADK/zli KjkxuKArESgyR/1jnqEUW49MoU0Wy3395A6smJYP+br+qJeLlxA4geSuomv/kec/Gi39O4zmL p8NNgDM62e07kQl+I/Odx3q9CRc4k+yliiKpXDuqN9368rMfUdDS7U3cg65rYHOebBy2VTGCn 039jdx4sYdFu1N6L1LOn2IqtbXGkubR3Yow32InohRxaqLHiavYUDViqmknEQG0MwUDK79Gf6 hcUavI1ClhfVW4qdW/RrK4TBgizZzq790MDHlPEn86bC3SikitiRYOsu85nCbhnHb/XWLxAFN T9hWH5BQb56dUBZdDTtgQnBUc1f5HNIzL93Jk/SBlzjw/xCk0EDcXVOvhOtrUOV1FIhWaEZne shCDhYU9m8FKKBlx0pgO5wIpKweumCAvCRHF4b863IHbKsR7gv1Oa9pviQ1qaidNy/uaxoHnd GAWEnk2euzaMu41mraUI/vJxGsZiEL9EuahjC77mhBi1cBOv0Lk/jskKdqlAhpgKT+mSa0EJ5 1mQh2VpGV6p5Sd6mrioN7VNuhiJDvxhRlchHH7i2BRn1rvLaHrIOKWA092CP1qM8uIHs= Received-SPF: none client-ip=212.227.126.130; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap. The Linux kernel does not handle all memory operations: no floating-point and no MAC. Signed-off-by: Richard Henderson Reviewed-by: Laurent Vivier Message-Id: <20211227150127.2659293-7-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier --- linux-user/sh4/target_prctl.h | 2 +- target/sh4/cpu.h | 4 +++ target/sh4/translate.c | 50 ++++++++++++++++++++++++----------- 3 files changed, 39 insertions(+), 17 deletions(-) diff --git a/linux-user/sh4/target_prctl.h b/linux-user/sh4/target_prctl.h index eb53b31ad554..5629ddbf39cd 100644 --- a/linux-user/sh4/target_prctl.h +++ b/linux-user/sh4/target_prctl.h @@ -1 +1 @@ -/* No special prctl support required. */ +#include "../generic/target_prctl_unalign.h" diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 4cfb109f5668..fb9dd9db2ffd 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -83,6 +83,7 @@ #define DELAY_SLOT_RTE (1 << 2) #define TB_FLAG_PENDING_MOVCA (1 << 3) +#define TB_FLAG_UNALIGN (1 << 4) #define GUSA_SHIFT 4 #ifdef CONFIG_USER_ONLY @@ -373,6 +374,9 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc, | (env->sr & ((1u << SR_MD) | (1u << SR_RB))) /* Bits 29-30 */ | (env->sr & (1u << SR_FD)) /* Bit 15 */ | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ +#ifdef CONFIG_USER_ONLY + *flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif } #endif /* SH4_CPU_H */ diff --git a/target/sh4/translate.c b/target/sh4/translate.c index ce5d674a520e..50493c61ea65 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -50,8 +50,10 @@ typedef struct DisasContext { #if defined(CONFIG_USER_ONLY) #define IS_USER(ctx) 1 +#define UNALIGN(C) (ctx->tbflags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN) #else #define IS_USER(ctx) (!(ctx->tbflags & (1u << SR_MD))) +#define UNALIGN(C) 0 #endif /* Target-specific values for ctx->base.is_jmp. */ @@ -495,7 +497,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUL | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -503,7 +506,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4); - tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, + MO_TESL | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -558,19 +562,23 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_UB); return; case 0x2001: /* mov.w Rm,@Rn */ - tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUW); + tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, + MO_TEUW | UNALIGN(ctx)); return; case 0x2002: /* mov.l Rm,@Rn */ - tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, + MO_TEUL | UNALIGN(ctx)); return; case 0x6000: /* mov.b @Rm,Rn */ tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_SB); return; case 0x6001: /* mov.w @Rm,Rn */ - tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW); + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, + MO_TESW | UNALIGN(ctx)); return; case 0x6002: /* mov.l @Rm,Rn */ - tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, + MO_TESL | UNALIGN(ctx)); return; case 0x2004: /* mov.b Rm,@-Rn */ { @@ -586,7 +594,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_subi_i32(addr, REG(B11_8), 2); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUW | UNALIGN(ctx)); tcg_gen_mov_i32(REG(B11_8), addr); tcg_temp_free(addr); } @@ -595,7 +604,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_subi_i32(addr, REG(B11_8), 4); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUL | UNALIGN(ctx)); tcg_gen_mov_i32(REG(B11_8), addr); tcg_temp_free(addr); } @@ -606,12 +616,14 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1); return; case 0x6005: /* mov.w @Rm+,Rn */ - tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW); + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, + MO_TESW | UNALIGN(ctx)); if ( B11_8 != B7_4 ) tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2); return; case 0x6006: /* mov.l @Rm+,Rn */ - tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, + MO_TESL | UNALIGN(ctx)); if ( B11_8 != B7_4 ) tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); return; @@ -627,7 +639,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_add_i32(addr, REG(B11_8), REG(0)); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUW | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -635,7 +648,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_add_i32(addr, REG(B11_8), REG(0)); - tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, + MO_TEUL | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -651,7 +665,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_add_i32(addr, REG(B7_4), REG(0)); - tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW); + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, + MO_TESW | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -659,7 +674,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_add_i32(addr, REG(B7_4), REG(0)); - tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, + MO_TESL | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -1253,7 +1269,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2); - tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUW); + tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, + MO_TEUW | UNALIGN(ctx)); tcg_temp_free(addr); } return; @@ -1269,7 +1286,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr = tcg_temp_new(); tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2); - tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESW); + tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, + MO_TESW | UNALIGN(ctx)); tcg_temp_free(addr); } return; From patchwork Thu Jan 6 10:41:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 530343 Delivered-To: patch@linaro.org Received: by 2002:ad5:544f:0:0:0:0:0 with SMTP id a15csp1063560imp; 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[209.51.188.17]) by mx.google.com with ESMTPS id b96si1124410ybi.487.2022.01.06.02.49.24 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jan 2022 02:49:25 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:60492 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5QKi-0007wY-Bq for patch@linaro.org; Thu, 06 Jan 2022 05:49:24 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60900) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDX-0007hZ-Ns for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:41:59 -0500 Received: from mout.kundenserver.de ([212.227.126.133]:45181) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDQ-0004jZ-Hz for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:41:59 -0500 Received: from quad ([82.142.12.178]) by mrelayeu.kundenserver.de (mreue009 [212.227.15.167]) with ESMTPSA (Nemesis) id 1MVNF1-1mvCmY2Uvn-00SOlJ; Thu, 06 Jan 2022 11:41:49 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PULL 17/27] linux-user/nios2: Properly emulate EXCP_TRAP Date: Thu, 6 Jan 2022 11:41:27 +0100 Message-Id: <20220106104137.732883-18-laurent@vivier.eu> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220106104137.732883-1-laurent@vivier.eu> References: <20220106104137.732883-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:qG6vv5OFKb6Yy0S4W/IXZOP6sug6DV/0tU8kkyuNGlqZutDa2aL HLnE19xMVs8u1U0bxGyEjNMBjfpVWQ5pa+aMyn2JGA9YlqoZu63Lu649Yo4KwDVLHH+eftQ B+hiC95yAbzQXyYW8sJPLMH0t2/A7DHJwqQQY6l71ogrgWzGMGyi17flnBsZDJbkZ+vp5ZN 2b1JeI/yGQFm32bOfBN2A== X-UI-Out-Filterresults: notjunk:1;V03:K0:07BPLdb04k4=:gslS6L2yedPYlWz7JPzWS+ 7/L/46a+zXc8/MY/5CZU6NVV4ITrbS44Ncyz7NVAtT1RCAMs6ax6jyvpn0W7SmNihUBUy4Ruv b2IiC9m2jlL2OdZhXa8Clm5xKw8TuYPSy7zZuOlsuIYtDLN99Y4IZFka3W1uNbXomX4NbsO6K VMrv98p71KtXOvqf8dXk5svNBxa+y4n+l30cqJDVuq2CL7fm2oCSo9rES0/LfEUwmLwqkiTzh U1eb5PAdrgW7QpeFOvr2MwYI/JNLL5raHH5awGD2YTWnNTW8BEu/4fy4HFLxDU5Ta3g4QPbur Y8FaFwOhyjBdPPMI4a3XmXFJ7xWiiJvA/ESkUpe8nUEggv9J/SNXsHk7ocAsLm38vnyIp68i8 i8zg8MLfcpKi2JgHM4Un0zrN55HE9Cf/gTnZIxUDEC7rhNTAzU6lRab8YjaDFu2IwN3kIXSxW A6kAIQqMs9g39ZqlljqMxCH4NONxvP/kdIsmFBZvPeCDrftkTr/Xja1K8mqkDBErjYhf9tnbe 65XbaIWE6grWdmxibbY8KFWpq9F5W1BCTPq7kUp6OGAp0Tk1d9diWCl3A9mTM/f1u2Q0ws1rB QkzdTIJG8Gn3t6WWOjGQrbvjdou3F4lpNlme4p1K3OiEy103qa1FcCQWUA67HXypkKcLBi4I/ Rq7iLyeUa5DPdu9vzn6vmT6qIRQ4nqupcZezvCjlWCnFTq2SZ65zzu1nN4VZd6qs0I2k= Received-SPF: none client-ip=212.227.126.133; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The real kernel has to load the instruction and extract the imm5 field; for qemu, modify the translator to do this. The use of R_AT for this in cpu_loop was a bug. Handle the other trap numbers as per the kernel's trap_table. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Reviewed-by: Laurent Vivier Message-Id: <20211221025012.1057923-2-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier --- linux-user/nios2/cpu_loop.c | 40 ++++++++++++++++++++----------------- target/nios2/cpu.h | 2 +- target/nios2/translate.c | 17 +++++++++++++++- 3 files changed, 39 insertions(+), 20 deletions(-) diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index 34290fb3b51c..5c3d01d22dd7 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -26,7 +26,6 @@ void cpu_loop(CPUNios2State *env) { CPUState *cs = env_cpu(env); - Nios2CPU *cpu = NIOS2_CPU(cs); target_siginfo_t info; int trapnr, ret; @@ -39,9 +38,10 @@ void cpu_loop(CPUNios2State *env) case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; + case EXCP_TRAP: - if (env->regs[R_AT] == 0) { - abi_long ret; + switch (env->error_code) { + case 0: qemu_log_mask(CPU_LOG_INT, "\nSyscall\n"); ret = do_syscall(env, env->regs[2], @@ -55,26 +55,30 @@ void cpu_loop(CPUNios2State *env) env->regs[2] = abs(ret); /* Return value is 0..4096 */ - env->regs[7] = (ret > 0xfffffffffffff000ULL); - env->regs[CR_ESTATUS] = env->regs[CR_STATUS]; - env->regs[CR_STATUS] &= ~0x3; - env->regs[R_EA] = env->regs[R_PC] + 4; + env->regs[7] = ret > 0xfffff000u; env->regs[R_PC] += 4; break; - } else { - qemu_log_mask(CPU_LOG_INT, "\nTrap\n"); - - env->regs[CR_ESTATUS] = env->regs[CR_STATUS]; - env->regs[CR_STATUS] &= ~0x3; - env->regs[R_EA] = env->regs[R_PC] + 4; - env->regs[R_PC] = cpu->exception_addr; - info.si_signo = TARGET_SIGTRAP; - info.si_errno = 0; - info.si_code = TARGET_TRAP_BRKPT; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + case 1: + qemu_log_mask(CPU_LOG_INT, "\nTrap 1\n"); + force_sig_fault(TARGET_SIGUSR1, 0, env->regs[R_PC]); + break; + case 2: + qemu_log_mask(CPU_LOG_INT, "\nTrap 2\n"); + force_sig_fault(TARGET_SIGUSR2, 0, env->regs[R_PC]); + break; + case 31: + qemu_log_mask(CPU_LOG_INT, "\nTrap 31\n"); + force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->regs[R_PC]); + break; + default: + qemu_log_mask(CPU_LOG_INT, "\nTrap %d\n", env->error_code); + force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLTRP, + env->regs[R_PC]); break; } + break; + case EXCP_DEBUG: info.si_signo = TARGET_SIGTRAP; info.si_errno = 0; diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 1a69ed7a49c7..d2ba0c5bbd82 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -160,9 +160,9 @@ struct CPUNios2State { #if !defined(CONFIG_USER_ONLY) Nios2MMU mmu; - uint32_t irq_pending; #endif + int error_code; }; /** diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 08d7ac539834..a75987751926 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -636,6 +636,21 @@ static void divu(DisasContext *dc, uint32_t code, uint32_t flags) tcg_temp_free(t0); } +static void trap(DisasContext *dc, uint32_t code, uint32_t flags) +{ +#ifdef CONFIG_USER_ONLY + /* + * The imm5 field is not stored anywhere on real hw; the kernel + * has to load the insn and extract the field. But we can make + * things easier for cpu_loop if we pop this into env->error_code. + */ + R_TYPE(instr, code); + tcg_gen_st_i32(tcg_constant_i32(instr.imm5), cpu_env, + offsetof(CPUNios2State, error_code)); +#endif + t_gen_helper_raise_exception(dc, EXCP_TRAP); +} + static const Nios2Instruction r_type_instructions[] = { INSTRUCTION_ILLEGAL(), INSTRUCTION(eret), /* eret */ @@ -682,7 +697,7 @@ static const Nios2Instruction r_type_instructions[] = { INSTRUCTION_ILLEGAL(), INSTRUCTION_ILLEGAL(), INSTRUCTION_ILLEGAL(), - INSTRUCTION_FLG(gen_excp, EXCP_TRAP), /* trap */ + INSTRUCTION(trap), /* trap */ INSTRUCTION(wrctl), /* wrctl */ INSTRUCTION_ILLEGAL(), INSTRUCTION_FLG(gen_cmpxx, TCG_COND_LTU), /* cmpltu */ From patchwork Thu Jan 6 10:41:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 530349 Delivered-To: patch@linaro.org Received: by 2002:ad5:544f:0:0:0:0:0 with SMTP id a15csp1067678imp; Thu, 6 Jan 2022 02:56:38 -0800 (PST) X-Google-Smtp-Source: ABdhPJzY5N1PJOHDc2nVQ7ZajgDq+/kocUo6T/McizHLwE6sUZtj/7aqQKXwH5sFZ2nDLxDHOPH7 X-Received: by 2002:a25:23c8:: with SMTP id j191mr67684135ybj.85.1641466597950; Thu, 06 Jan 2022 02:56:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1641466597; cv=none; d=google.com; s=arc-20160816; b=zo33V+mRE4xHP8buswW5TrsGpTxaxtgbKqCNcO2yTm1LQMOR6iNjE4NpWWx0fKR8GK HR2admEsMrl0RpWFC4EY74+ckypxqCuAo2EldzzI7/nHLQ5S6rg5pJCfhgyTuUHmD25W Yx13MJnNHN29dboSehhFwri2fkfUDVjg5MtueZQ2G1HLv63TRXv2y1w/s3h9SbmGpk64 HZ3M82D9WaUCs9uur25VWj+pmKh+EfRbLcDQgbFdKbsRbb1Yg25vXkO3ChaVIeX1jN1e LJme3wMZTqbk+tqpU1M7XSq/uGKcD6X4h2pJA9J07/LX04uIXDXzjz7XbiscsMedws/s 9CRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from; bh=WqRdhKgNg3v3+auPt1JrkaykXxLEs7XUvknBO0FOmYU=; b=jau4/lbCRYbfFUR0h22ekz88BFboTylg+kR4SxLZPBwci/D+XwXXlmKB9x87bZYj6K qv/PF7DftcdQYpK6Io1UIjHccROd1kdCXdANCYhs6qgenIRCBkYfTYYdirMtQOFk+Ns/ bdju9SrBcpZFFE24dfS4TEtzKekJaW3KNuHh8oLRqDeIScZ6kznw3IIsDTA3Fq75ZSNh JJnXoKJQ8+SoDZg9ZtVgEjTeuAkSNuV4eCOsc7Y8/ntlq9NbVEYWKGXnJsuUgyRw5Iwu KbXI2mPwkVWDmltAZOUV/V39osX13KF5NjofCNgMnbJxp6jZY255XsAE2auNQeopm93U BGqA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p124si1190377ybc.274.2022.01.06.02.56.37 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jan 2022 02:56:37 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:56504 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5QRh-0007Vi-EO for patch@linaro.org; Thu, 06 Jan 2022 05:56:37 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60898) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDX-0007hX-N9 for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:41:59 -0500 Received: from mout.kundenserver.de ([212.227.126.133]:33365) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDQ-0004jg-I2 for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:41:59 -0500 Received: from quad ([82.142.12.178]) by mrelayeu.kundenserver.de (mreue009 [212.227.15.167]) with ESMTPSA (Nemesis) id 1M6DSi-1n3FQM0VAm-006f0M; Thu, 06 Jan 2022 11:41:50 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PULL 18/27] linux-user/nios2: Fixes for signal frame setup Date: Thu, 6 Jan 2022 11:41:28 +0100 Message-Id: <20220106104137.732883-19-laurent@vivier.eu> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220106104137.732883-1-laurent@vivier.eu> References: <20220106104137.732883-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:n4PmSp8DhyGWOJ+w0pJKMyIQ3ECft+pn8dPmJGnpNAzTTRNyJMB El5Z4w1fWDcY8bu9mIkI68XBmHQd4DaEVT4GjT5P4QOjCqIyrMbbHUmbM32gbLNac4ZS8iB Z8jtl5CHmhceOBqi5kmfW4gXjs1859/8IdK2hirYtJW1xdtgSsPzvUA2Prb2XtN+3r07AHi 7qkgG3mkD5Jf/D4M+gVYA== X-UI-Out-Filterresults: notjunk:1;V03:K0:Y+ARbSwUk8k=:oOPBZU+KZovnxBROXNetay cgAFpcbGmghQpTlwud9Qi94YRAp4dxrsxUsD/2XFASheg1Q9iJFIzG/oMEl0MvtN81QF+yzIY sZm1lvwGSWXQBmlvu1H0SS+3ZKCf46yO8ANIvna+7h0nE+KeLdiHgd1r2YI7lff8XIKA2gFLz pYYmUsfDrRZJQGl31VHHhzn506yqOP7oYb7b+X6OQ48Vqd/QjnRkRrcbXqdIaldP7RQ6T8JTe KtU/SQr/oRMwoyqmi8vqXPWEChKV8LAFmPpGv+HeVwtSU6WKaQy/2RfLSYC6Zl/oe/+1KBtRZ oT5tQqcpMSW1bJ99rMWEZCt1Xsv2WHiPT3Px6h1PymeO9z8bDrWfTzUW1rq0CFg4NPaNMGNXr CStskYnVYgjlIVwXN5zZYPX759TZmCcYR+pytFR2SvK1RtrjqK44l+nm0A2DAbki2VGAZZGjG 3L7yuU2HeKu8aIjKq4xDNgMu+g8UjPMlhVnuNAD8DIPL/bLJjbx7eyHTLbSyjrrXb+CHB9uds xjaN+73O0vyJOGSMhmncygkeofgeygsEMuM21hlogmmgB6uSQ6qbLuZPh+nTAuX5RXqwVg4ZG IawqLs3JjnMKgNDaN7BKTEiMlmTmqxPfuq3SiGi/v62BQsAOdJ3EsdNdX/yhHJgBo0nG8vCDs z6CUDbZNDktlMhUwTJ48W3H8dHNfRMfP88myhjPOD6kLEh5f2mKtroZbnOXZInZ8cM8Q= Received-SPF: none client-ip=212.227.126.133; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Laurent Vivier , Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Do not confuse host and guest addresses. Lock and unlock the target_rt_sigframe structure in setup_rt_sigframe. Since rt_setup_ucontext always returns 0, drop the return value entirely. This eliminates the only write to the err variable in setup_rt_sigframe. Always copy the siginfo structure. Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20211221025012.1057923-3-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier --- linux-user/nios2/signal.c | 51 ++++++++++++++++----------------------- 1 file changed, 21 insertions(+), 30 deletions(-) diff --git a/linux-user/nios2/signal.c b/linux-user/nios2/signal.c index a77e8a40f468..adbffe32e3c8 100644 --- a/linux-user/nios2/signal.c +++ b/linux-user/nios2/signal.c @@ -42,7 +42,7 @@ struct target_rt_sigframe { struct target_ucontext uc; }; -static int rt_setup_ucontext(struct target_ucontext *uc, CPUNios2State *env) +static void rt_setup_ucontext(struct target_ucontext *uc, CPUNios2State *env) { unsigned long *gregs = uc->tuc_mcontext.gregs; @@ -75,8 +75,6 @@ static int rt_setup_ucontext(struct target_ucontext *uc, CPUNios2State *env) __put_user(env->regs[R_GP], &gregs[25]); __put_user(env->regs[R_EA], &gregs[27]); __put_user(env->regs[R_SP], &gregs[28]); - - return 0; } static int rt_restore_ucontext(CPUNios2State *env, struct target_ucontext *uc, @@ -135,8 +133,8 @@ static int rt_restore_ucontext(CPUNios2State *env, struct target_ucontext *uc, return 0; } -static void *get_sigframe(struct target_sigaction *ka, CPUNios2State *env, - size_t frame_size) +static abi_ptr get_sigframe(struct target_sigaction *ka, CPUNios2State *env, + size_t frame_size) { unsigned long usp; @@ -144,7 +142,7 @@ static void *get_sigframe(struct target_sigaction *ka, CPUNios2State *env, usp = target_sigsp(get_sp_from_cpustate(env), ka); /* Verify, is it 32 or 64 bit aligned */ - return (void *)((usp - frame_size) & -8UL); + return (usp - frame_size) & -8; } void setup_rt_frame(int sig, struct target_sigaction *ka, @@ -153,26 +151,25 @@ void setup_rt_frame(int sig, struct target_sigaction *ka, CPUNios2State *env) { struct target_rt_sigframe *frame; - int i, err = 0; + abi_ptr frame_addr; + int i; - frame = get_sigframe(ka, env, sizeof(*frame)); - - if (ka->sa_flags & SA_SIGINFO) { - tswap_siginfo(&frame->info, info); + frame_addr = get_sigframe(ka, env, sizeof(*frame)); + if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) { + force_sigsegv(sig); + return; } + tswap_siginfo(&frame->info, info); + /* Create the ucontext. */ __put_user(0, &frame->uc.tuc_flags); __put_user(0, &frame->uc.tuc_link); target_save_altstack(&frame->uc.tuc_stack, env); - err |= rt_setup_ucontext(&frame->uc, env); + rt_setup_ucontext(&frame->uc, env); for (i = 0; i < TARGET_NSIG_WORDS; i++) { __put_user((abi_ulong)set->sig[i], - (abi_ulong *)&frame->uc.tuc_sigmask.sig[i]); - } - - if (err) { - goto give_sigsegv; + (abi_ulong *)&frame->uc.tuc_sigmask.sig[i]); } /* Set up to return from userspace; jump to fixed address sigreturn @@ -180,19 +177,13 @@ void setup_rt_frame(int sig, struct target_sigaction *ka, env->regs[R_RA] = (unsigned long) (0x1044); /* Set up registers for signal handler */ - env->regs[R_SP] = (unsigned long) frame; - env->regs[4] = (unsigned long) sig; - env->regs[5] = (unsigned long) &frame->info; - env->regs[6] = (unsigned long) &frame->uc; - env->regs[R_EA] = (unsigned long) ka->_sa_handler; - return; - -give_sigsegv: - if (sig == TARGET_SIGSEGV) { - ka->_sa_handler = TARGET_SIG_DFL; - } - force_sigsegv(sig); - return; + env->regs[R_SP] = frame_addr; + env->regs[4] = sig; + env->regs[5] = frame_addr + offsetof(struct target_rt_sigframe, info); + env->regs[6] = frame_addr + offsetof(struct target_rt_sigframe, uc); + env->regs[R_EA] = ka->_sa_handler; + + unlock_user_struct(frame, frame_addr, 1); } long do_sigreturn(CPUNios2State *env) From patchwork Thu Jan 6 10:41:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 530352 Delivered-To: patch@linaro.org Received: by 2002:ad5:544f:0:0:0:0:0 with SMTP id a15csp1072453imp; Thu, 6 Jan 2022 03:02:51 -0800 (PST) X-Google-Smtp-Source: ABdhPJz4rw/ddv+a2RsZkHENYLzKW+T6az0L2jqPc3Ch73L4keWi3yW1jwl+EA4MdjJS9lE+Wewd X-Received: by 2002:a25:97c1:: with SMTP id j1mr71304413ybo.264.1641466971667; Thu, 06 Jan 2022 03:02:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1641466971; cv=none; d=google.com; s=arc-20160816; b=OdzLWUYQD2JdG1nQdAYrTfk11ymOq0WwI2SNTmIGAhoDRPtjg+mq2IedDydq54rH+h GNjeUigo4OXrGeVTDMylFDUvNcOQMsP/y4ZZbHGAY6vsKmJpjDFy6zb9CAnPSeffHM7Y tRToI+8KQhLReQ4BDI8gaPXe+d4jLkKxauEadJRUUSdIcWiQ4zBUVsU0sz8/C9NYhAxw FCaH66L1z7Tgt2beELsmuiMgyUZcWpYjgyxiJLaa8qSIU2etWA+uwWOxZaRg0sBnFU2e UknlhRyWVFeKBxnsH/85DnGefk9VirfMPmBioY3s2Rer89wvXB3kgyEg6G5gwZsOnv/o UBnQ== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id 185si1043475ybw.539.2022.01.06.03.02.51 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jan 2022 03:02:51 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:44528 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5QXj-0002Gw-3C for patch@linaro.org; Thu, 06 Jan 2022 06:02:51 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60976) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDZ-0007ne-Gi for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:42:01 -0500 Received: from mout.kundenserver.de ([212.227.126.135]:50397) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDR-0004jr-El for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:42:00 -0500 Received: from quad ([82.142.12.178]) by mrelayeu.kundenserver.de (mreue012 [212.227.15.167]) with ESMTPSA (Nemesis) id 1MbC5g-1mYINz1zlw-00bYSd; Thu, 06 Jan 2022 11:41:51 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PULL 19/27] linux-user/elfload: Rename ARM_COMMPAGE to HI_COMMPAGE Date: Thu, 6 Jan 2022 11:41:29 +0100 Message-Id: <20220106104137.732883-20-laurent@vivier.eu> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220106104137.732883-1-laurent@vivier.eu> References: <20220106104137.732883-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:1lauh6L71dtd4UvQ6MPHlgdYKC13fq8DbNE3emgtpe6t1q7k8I3 AS1g0EV4RqyYkFGHHNucHEfZ8WyqF+02c8/rrQ9axMdER9LHDHpIaAoC8hM0qzvBvmwoUJb OnD9ESsPsqV1lc1s8zjWe7biBPBSePirW0Ff9pO9TpjigCG/9ohzaf6OdB2urY2N+3p8qLI 1UDqt25vnwPBP5AmsL6mQ== X-UI-Out-Filterresults: notjunk:1;V03:K0:JoTCOb9r2TM=:QwMel8YmCwgzyyeLCpGTGY p56kRD+OLSIrpNrumIeF8h9buLfjBmrqTkUUUud7WLFHgbzkfFgjofuoSgbER9JUnnLVc50fs xjBwQTUnADaQsaO3DIV+wZ9IIwsVFI3KpUBZVNO8SdqZWaEcS8urGMsfqXotKFYSzE19C6pwk 1Nf/hLJ4buv15BA+SOcTP9eGLTtqhDRQEky4BwskFsHujg25B9VnoJZceRS/6j6iq5ZW7tLMb 4wlXFIh/KXzyhsYWQ/Hg+d+uffvaTCgxOjSlg39LjZ5wlY7ACKwAK5OXX8mu5su4wdR/RDRU4 MSHW7QzilAYsTIciTKkxBB2RhH9BQZfYTJR1P3luS7tr4ErVHjAhubmFmBe6cMfEZIuMl+tTv znCOVK+MrACSywnKD8bbCPMRyOXbloH7SV+cLv+SBFG15ROMEY6O/Nhc04p5Y9haT1vnPSAVv Iz9wxQqnSAUZzeAKQHT15//XSc1TwU2FgyI4IJFbOvnDbU2EdVhexTmAQs4eOiE+9P0/vnGuj sDkJbU6xRvjtXCAYhUjfkj9FYhmSsZ0/mpcLPJleZDrH3y1fRkVfVvgY8q5Y4k8MPBWdYRWUR FwgSLxjvfvP8QpF6A3t+QHnrh2S7dNHGkzhnjvox2UHLlVSvewuni719CAgHUhiM4GTgQknWk 7lHft5H15epwQTlIw7h2nu0xZkmCeLBbhpZWSqBHAe2ny/RWmZC5SZrZRmW7/I4n+rsw= Received-SPF: none client-ip=212.227.126.135; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Arm will no longer be the only target requiring a commpage, but it will continue to be the only target placing the page at the high end of the address space. Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson Message-Id: <20211221025012.1057923-4-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier --- linux-user/elfload.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 767f54c76dc5..d34cd4fe43fb 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -390,11 +390,11 @@ enum { /* The commpage only exists for 32 bit kernels */ -#define ARM_COMMPAGE (intptr_t)0xffff0f00u +#define HI_COMMPAGE (intptr_t)0xffff0f00u static bool init_guest_commpage(void) { - void *want = g2h_untagged(ARM_COMMPAGE & -qemu_host_page_size); + void *want = g2h_untagged(HI_COMMPAGE & -qemu_host_page_size); void *addr = mmap(want, qemu_host_page_size, PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE | MAP_FIXED, -1, 0); @@ -2160,8 +2160,8 @@ static abi_ulong create_elf_tables(abi_ulong p, int argc, int envc, return sp; } -#ifndef ARM_COMMPAGE -#define ARM_COMMPAGE 0 +#ifndef HI_COMMPAGE +#define HI_COMMPAGE 0 #define init_guest_commpage() true #endif @@ -2361,7 +2361,7 @@ static void pgb_static(const char *image_name, abi_ulong orig_loaddr, } loaddr &= -align; - if (ARM_COMMPAGE) { + if (HI_COMMPAGE) { /* * Extend the allocation to include the commpage. * For a 64-bit host, this is just 4GiB; for a 32-bit host we @@ -2372,14 +2372,14 @@ static void pgb_static(const char *image_name, abi_ulong orig_loaddr, if (sizeof(uintptr_t) == 8 || loaddr >= 0x80000000u) { hiaddr = (uintptr_t) 4 << 30; } else { - offset = -(ARM_COMMPAGE & -align); + offset = -(HI_COMMPAGE & -align); } } addr = pgb_find_hole(loaddr, hiaddr - loaddr, align, offset); if (addr == -1) { /* - * If ARM_COMMPAGE, there *might* be a non-consecutive allocation + * If HI_COMMPAGE, there *might* be a non-consecutive allocation * that can satisfy both. But as the normal arm32 link base address * is ~32k, and we extend down to include the commpage, making the * overhead only ~96k, this is unlikely. @@ -2400,7 +2400,7 @@ static void pgb_dynamic(const char *image_name, long align) * All we need is a commpage that satisfies align. * If we do not need a commpage, leave guest_base == 0. */ - if (ARM_COMMPAGE) { + if (HI_COMMPAGE) { uintptr_t addr, commpage; /* 64-bit hosts should have used reserved_va. */ @@ -2410,7 +2410,7 @@ static void pgb_dynamic(const char *image_name, long align) * By putting the commpage at the first hole, that puts guest_base * just above that, and maximises the positive guest addresses. */ - commpage = ARM_COMMPAGE & -align; + commpage = HI_COMMPAGE & -align; addr = pgb_find_hole(commpage, -commpage, align, 0); assert(addr != -1); guest_base = addr; From patchwork Thu Jan 6 10:41:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 530350 Delivered-To: patch@linaro.org Received: by 2002:ad5:544f:0:0:0:0:0 with SMTP id a15csp1069777imp; Thu, 6 Jan 2022 02:59:41 -0800 (PST) X-Google-Smtp-Source: ABdhPJxiaUjD8SHyaK8Vr7XEjUHaoEAfUdq7sl5fpi8QLqZM6boH18f1V7aCN3avOfQsnGS7xPRi X-Received: by 2002:a25:55c2:: with SMTP id j185mr20901526ybb.763.1641466781519; Thu, 06 Jan 2022 02:59:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1641466781; cv=none; d=google.com; s=arc-20160816; b=Ltx/m5h7eGQMo08QKLqQ93OkiPsm/jTxctvDcTSeWVhaDapMuthdOJS/Rwf1H7pykz 7KfgRszTev/EwpA6ZiwFPWMnmxMB4h8SgvvnAKlGMdq/AtvtlLPaReM4eev/+6s/3cva ZuPDq1mZSq5vLb8uojsQv73fwKYD69TqWwvDGSz9y9YOVK0LOIQ4elffM03HkaCPwEU0 dtPPyGMiyywhAd4HJnohT6VVl+TG/tFiMN8RDFzw6KCIalRIUMVOwAa4hLvvbuuvBIlR PnVAqFk5v8nTtgAds/8UQKNKR1FSYUlY3e1G0mrcj7OYlwmads44fY8wNI+n8rmIG96q NxYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from; bh=aoRkyjWWUAQpuKXdsC/DH2gnlfVs1GrgBD9b6fT+x2Y=; b=wiYDLXrWu3A5NVfc+W7A7Aq1EkfWU4yepS3TPexyRUtSFs23aMLGLxVngvB9ul0EyJ BmqDyha+tRUoM2s5LTMbNFDB57bskRv7AP0Tf31jMsTTmkZ9lBZR/eXWyYKzFYSmsbrR IspUxPBfSdL2Y8y81HqVm4roCd6MS/5To6m/wGLkTSF6QkCJkaF16jhclardlxI4TDn5 WFR8U7MzFcsmezZT5OUpQXnQq4lknoaPlruz3O4GEg1ft/bhFOaqvCmk1L9nYfg8zhZI 4tzK0dJhaA/kFciy5vpJRvObuMu9YoijrtCWWVHEqhbHVZH2uYKAVMnyZij6Qj5ZQZ8M kSkA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 192si1091686ybt.103.2022.01.06.02.59.41 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jan 2022 02:59:41 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:36722 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5QUe-000528-VD for patch@linaro.org; Thu, 06 Jan 2022 05:59:40 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60980) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDZ-0007nh-H4 for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:42:01 -0500 Received: from mout.kundenserver.de ([212.227.126.133]:59149) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDR-0004k0-Sj for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:42:00 -0500 Received: from quad ([82.142.12.178]) by mrelayeu.kundenserver.de (mreue012 [212.227.15.167]) with ESMTPSA (Nemesis) id 1MEUaQ-1nBWsf3hRS-00Fz6D; Thu, 06 Jan 2022 11:41:52 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PULL 20/27] linux-user/nios2: Map a real kuser page Date: Thu, 6 Jan 2022 11:41:30 +0100 Message-Id: <20220106104137.732883-21-laurent@vivier.eu> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220106104137.732883-1-laurent@vivier.eu> References: <20220106104137.732883-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:V5mQcKaknO/dQ4BbmLpggz5nfGAs+HZS3fVhdM6wIjkh2Ad7UL0 1L1fNRnQucUCeLWne5MuHKdr6GsX60NyWZZKIvVnQ/ACchBbsPnN+jYfNVPunCEJjZfHcYN J2GSHVFq8EBEadz3TQlUpSAMZn00+GTGL2QomnCWmlUCjgsAeCzpUgfShIviQ0VX0634egF /6oFDU6ISk7lpSM5BQCUw== X-UI-Out-Filterresults: notjunk:1;V03:K0:vhlb68p/hRI=:Ur7CfeKUJdJCW9RQU1SpOo YTfRgyBsVJTF00lFf3BGWXrJsslqTqCOBJGQl73qji9fNfnyMn2SQmO08JF+hvMs9FcHZDhM/ ++kJhAMik7gpIdEvcdSiy7oKmnu8UdpmHrEqQX2nY9nZxS4gJTh0bvfkg9O3346mRXXL9oopt NU3gvUQ0jKnq63ncfj8p6lAjBrFW6m1S6KkzkxhvaHEGrSY5pNEpMvT+7h53GJ93ra0kuz5He Mihw9MHPi0zFCgz4OjKx3srq1u7acVEwLqcNENBVj/6R2oPoF5nL9drdbOAGhRPEBI72dbqyF QDzE3WPjcqbZ/Or07X/KYbNjqsBrMb4b15KXEq0y2R+mixeX5KZDDvx5y814EIG3JKpK6qoJc yGDh4WP4EJPTDD/kjpm8+fDElEUWul5z87Q6R+Rq8U+MtZy0ZMWUMhq6gq7Jw9n/h4oKHngkJ YO5QmKIAidl48HchrEsA+5qMgiSaw4jJC9N2k0QTxu7PTVFVbH6C56UEG1uGafrOVTDjrmLe3 fclk4Sk8aykKoYGMarSQ65WVFwFyvb9EPjeg/WtAqrgmPUPnbaqcD+oas3NZqYZxEojFqOXXK jMJInVuuRAVp81fvMGZzDhbej+qKUoSH+bwRnMzmewqh4X6tZlqxX7fXnl2RNEBNvToy5hxKM mZF8zd0GmHugjeptuv1SPlBbTPXDu4VPGPaFD9COGiQUB1ew2pn0IeDKjju8pvSl5ZWk= Received-SPF: none client-ip=212.227.126.133; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The first word of page1 is data, so the whole thing can't be implemented with emulation of addresses. Use init_guest_commpage for the allocation. Hijack trap number 16 to implement cmpxchg. Signed-off-by: Richard Henderson Reviewed-by: Laurent Vivier Message-Id: <20211221025012.1057923-5-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier --- linux-user/elfload.c | 50 ++++++++++++++++++++++++++++++++++++- linux-user/nios2/cpu_loop.c | 50 ++++++++++++++++++++----------------- target/nios2/translate.c | 9 ------- 3 files changed, 76 insertions(+), 33 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index d34cd4fe43fb..329b2375ef15 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1099,6 +1099,47 @@ static void init_thread(struct target_pt_regs *regs, struct image_info *infop) regs->estatus = 0x3; } +#define LO_COMMPAGE TARGET_PAGE_SIZE + +static bool init_guest_commpage(void) +{ + static const uint8_t kuser_page[4 + 2 * 64] = { + /* __kuser_helper_version */ + [0x00] = 0x02, 0x00, 0x00, 0x00, + + /* __kuser_cmpxchg */ + [0x04] = 0x3a, 0x6c, 0x3b, 0x00, /* trap 16 */ + 0x3a, 0x28, 0x00, 0xf8, /* ret */ + + /* __kuser_sigtramp */ + [0x44] = 0xc4, 0x22, 0x80, 0x00, /* movi r2, __NR_rt_sigreturn */ + 0x3a, 0x68, 0x3b, 0x00, /* trap 0 */ + }; + + void *want = g2h_untagged(LO_COMMPAGE & -qemu_host_page_size); + void *addr = mmap(want, qemu_host_page_size, PROT_READ | PROT_WRITE, + MAP_ANONYMOUS | MAP_PRIVATE | MAP_FIXED, -1, 0); + + if (addr == MAP_FAILED) { + perror("Allocating guest commpage"); + exit(EXIT_FAILURE); + } + if (addr != want) { + return false; + } + + memcpy(addr, kuser_page, sizeof(kuser_page)); + + if (mprotect(addr, qemu_host_page_size, PROT_READ)) { + perror("Protecting guest commpage"); + exit(EXIT_FAILURE); + } + + page_set_flags(LO_COMMPAGE, LO_COMMPAGE + TARGET_PAGE_SIZE, + PAGE_READ | PAGE_EXEC | PAGE_VALID); + return true; +} + #define ELF_EXEC_PAGESIZE 4096 #define USE_ELF_CORE_DUMP @@ -2160,8 +2201,13 @@ static abi_ulong create_elf_tables(abi_ulong p, int argc, int envc, return sp; } -#ifndef HI_COMMPAGE +#if defined(HI_COMMPAGE) +#define LO_COMMPAGE 0 +#elif defined(LO_COMMPAGE) +#define HI_COMMPAGE 0 +#else #define HI_COMMPAGE 0 +#define LO_COMMPAGE 0 #define init_guest_commpage() true #endif @@ -2374,6 +2420,8 @@ static void pgb_static(const char *image_name, abi_ulong orig_loaddr, } else { offset = -(HI_COMMPAGE & -align); } + } else if (LO_COMMPAGE) { + loaddr = MIN(loaddr, LO_COMMPAGE & -align); } addr = pgb_find_hole(loaddr, hiaddr - loaddr, align, offset); diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index 5c3d01d22dd7..de0fc63e2196 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -76,6 +76,32 @@ void cpu_loop(CPUNios2State *env) force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLTRP, env->regs[R_PC]); break; + + case 16: /* QEMU specific, for __kuser_cmpxchg */ + { + abi_ptr g = env->regs[4]; + uint32_t *h, n, o; + + if (g & 0x3) { + force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN, g); + break; + } + ret = page_get_flags(g); + if (!(ret & PAGE_VALID)) { + force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, g); + break; + } + if (!(ret & PAGE_READ) || !(ret & PAGE_WRITE)) { + force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_ACCERR, g); + break; + } + h = g2h(cs, g); + o = env->regs[5]; + n = env->regs[6]; + env->regs[2] = qatomic_cmpxchg(h, o, n) - o; + env->regs[R_PC] += 4; + } + break; } break; @@ -86,29 +112,7 @@ void cpu_loop(CPUNios2State *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case 0xaa: - switch (env->regs[R_PC]) { - /*case 0x1000:*/ /* TODO:__kuser_helper_version */ - case 0x1004: /* __kuser_cmpxchg */ - start_exclusive(); - if (env->regs[4] & 0x3) { - goto kuser_fail; - } - ret = get_user_u32(env->regs[2], env->regs[4]); - if (ret) { - end_exclusive(); - goto kuser_fail; - } - env->regs[2] -= env->regs[5]; - if (env->regs[2] == 0) { - put_user_u32(env->regs[6], env->regs[4]); - } - end_exclusive(); - env->regs[R_PC] = env->regs[R_RA]; - break; - /*case 0x1040:*/ /* TODO:__kuser_sigtramp */ - default: - ; -kuser_fail: + { info.si_signo = TARGET_SIGSEGV; info.si_errno = 0; /* TODO: check env->error_code */ diff --git a/target/nios2/translate.c b/target/nios2/translate.c index a75987751926..f9abc2fdd200 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -795,15 +795,6 @@ static void nios2_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) dc->base.pc_next = pc + 4; /* Decode an instruction */ - -#if defined(CONFIG_USER_ONLY) - /* FIXME: Is this needed ? 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[209.51.188.17]) by mx.google.com with ESMTPS id o18si1161193ybg.358.2022.01.06.03.00.24 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jan 2022 03:00:24 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:38502 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5QVM-0006Do-17 for patch@linaro.org; Thu, 06 Jan 2022 06:00:24 -0500 Received: from eggs.gnu.org ([209.51.188.92]:32804) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDb-0007qa-Eb for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:42:05 -0500 Received: from mout.kundenserver.de ([212.227.126.134]:36477) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDS-0004k7-9w for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:42:01 -0500 Received: from quad ([82.142.12.178]) by mrelayeu.kundenserver.de (mreue012 [212.227.15.167]) with ESMTPSA (Nemesis) id 1MgiPE-1mSoCy1N5I-00h2dv; Thu, 06 Jan 2022 11:41:52 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PULL 21/27] linux-user/nios2: Fix EA vs PC confusion Date: Thu, 6 Jan 2022 11:41:31 +0100 Message-Id: <20220106104137.732883-22-laurent@vivier.eu> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220106104137.732883-1-laurent@vivier.eu> References: <20220106104137.732883-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:fpma7rgrQfMkXeh/gmxujbOIZZ+gON8IEBva0thvttFJabWTRgz AmoD1gUIwMuMBRE9ZqtYOYoMHOvnKy8K0LmMAepdPM2VoIlcc8qOq0s5yDjs9hyPp9H/TjE j2smxwB4W0SdbFH0ntiWcQdJ35t9Dp8k0F07t5S3H9CcqRo84/j6y8iR38ybqzBoI5k9Sts 4EwQeBHT9SbabDo1pQS8Q== X-UI-Out-Filterresults: notjunk:1;V03:K0:Q+38r0NksW0=:1tS/clRubEgF3TQxL3cesn 9krz+O1NahMe+fxec3/9zevP8aXsG7SnyUIKOV7Ccxtsv064ZCmncFfzyYeBma8IKarZh8vW5 oMe8fXjHAbc2wpIfogqYskdK7bzWVPur2w4dWNR5rmLLQdo1KmyvrzaTclQitur+ijbCIJsA2 l8kiE5ZY7IeP5DWu8wAs5Kfsq1SwUTb0XVmUnjW+NqKnRqbzfSRPXnMELRxkDN3Qh0PbPhdvo zAbvAwX/BTZxZxYl8/1B/gA+uqXh/wa+0DWbVfRROu4MwjWFXTB0UW4NIhdWj37GIP25qF5qK T+yffcczYSHEGSmISLi++0RSqVw1JM8FK2fhphaNN4bQpF1wqCHXVCqDxUpZLfNUbhw33X+sW JdybWTAaMkkxeOzftkculPPmQJcruQ/5yjMaKHo8mNOPqHr9OUSuvI0EPkjyXkWFTkEWa4ORV 1fOm91EnPOHWk0+ypNGPETrrMiD++v0N3mIcidu26wQxYlfyZdAvFJyQ7bVVaTWRy1IIvTimu UfGzsJMiwvgkGMIATpwgtc7c2xde81TfWQNEPgRCM6dKqn6OLGLpy3reicuUOct4eh0vwr7CG j3ZIse0Tj7Bc5ACyCuA8lHPn3UnCBFXYvj3FfJruyn8guPfTjE6Zw/zX4svib9Km6cdCLumKc duYNqNdmKWh+H70NRnkIgtLtf5K3X1DG5F0u5kysq2ez1iWSzawnxGIpzXup4VAfo7pg= Received-SPF: none client-ip=212.227.126.134; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The real kernel will talk about the user PC as EA, because that's where the hardware will have copied it, and where it expects to put it to then use ERET. But qemu does not emulate all of the exception stuff while emulating user-only. Manipulate PC directly. This fixes signal entry and return, and eliminates some slight confusion from target_cpu_copy_regs. Signed-off-by: Richard Henderson Reviewed-by: Laurent Vivier Message-Id: <20211221025012.1057923-6-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier --- linux-user/nios2/cpu_loop.c | 5 +---- linux-user/nios2/signal.c | 6 +++--- 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index de0fc63e2196..1e93ef34e649 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -155,9 +155,6 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) env->regs[R_SP] = regs->sp; env->regs[R_GP] = regs->gp; env->regs[CR_ESTATUS] = regs->estatus; - env->regs[R_EA] = regs->ea; - /* TODO: unsigned long orig_r7; */ - - /* Emulate eret when starting thread. */ env->regs[R_PC] = regs->ea; + /* TODO: unsigned long orig_r7; */ } diff --git a/linux-user/nios2/signal.c b/linux-user/nios2/signal.c index adbffe32e3c8..20b65aa06e08 100644 --- a/linux-user/nios2/signal.c +++ b/linux-user/nios2/signal.c @@ -73,7 +73,7 @@ static void rt_setup_ucontext(struct target_ucontext *uc, CPUNios2State *env) __put_user(env->regs[R_RA], &gregs[23]); __put_user(env->regs[R_FP], &gregs[24]); __put_user(env->regs[R_GP], &gregs[25]); - __put_user(env->regs[R_EA], &gregs[27]); + __put_user(env->regs[R_PC], &gregs[27]); __put_user(env->regs[R_SP], &gregs[28]); } @@ -122,7 +122,7 @@ static int rt_restore_ucontext(CPUNios2State *env, struct target_ucontext *uc, __get_user(env->regs[R_GP], &gregs[25]); /* Not really necessary no user settable bits */ __get_user(temp, &gregs[26]); - __get_user(env->regs[R_EA], &gregs[27]); + __get_user(env->regs[R_PC], &gregs[27]); __get_user(env->regs[R_RA], &gregs[23]); __get_user(env->regs[R_SP], &gregs[28]); @@ -181,7 +181,7 @@ void setup_rt_frame(int sig, struct target_sigaction *ka, env->regs[4] = sig; env->regs[5] = frame_addr + offsetof(struct target_rt_sigframe, info); env->regs[6] = frame_addr + offsetof(struct target_rt_sigframe, uc); - env->regs[R_EA] = ka->_sa_handler; + env->regs[R_PC] = ka->_sa_handler; unlock_user_struct(frame, frame_addr, 1); } From patchwork Thu Jan 6 10:41:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 530348 Delivered-To: patch@linaro.org Received: by 2002:ad5:544f:0:0:0:0:0 with SMTP id a15csp1066004imp; Thu, 6 Jan 2022 02:53:37 -0800 (PST) X-Google-Smtp-Source: ABdhPJxveo1OuPIov8iJCwdrVQdb/tSR4vYk/ACjXR42rauVMCgN+DCvLux2dcdXFCRNITdlmPfp X-Received: by 2002:a25:3890:: with SMTP id f138mr64746800yba.703.1641466417340; Thu, 06 Jan 2022 02:53:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1641466417; cv=none; d=google.com; s=arc-20160816; b=G3AtNFFQMQJ6Oz46k37e+fDtPMA4m5lebvpIMSy30nVlcW14jQJVRke0ljz6jq7iSu +23Ra8ylY+oYfaY5bcsmblWWMWBUzS8AZTXuqHWEU23sIApJ0fTAbDc1JvhwVwUZKKwc 8NjwR6uqXLuymHzSsH20uL/hVRHAOP+nacpsjvx2ZGEFTkmhvBeLfbDPO0L6IiqymVpg OCQOjHVnd67YmO6xnLc5sI7+yH1aw3V4ZPR5NNIeMY9638YvrC+D2XLbDNm8GyXiKr11 EuRUOyGk8mzjLEtjWnxS1ja4B9PImvfAMgIaPKtAA1Y8xSB5kFFLk3VrMYMmsETjU/79 WraA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from; bh=Lg6JGVzQ2lKiTbDOatsxGJTIkzP95RBUVAY2Az31Ph0=; b=BTrsVvZTvBtObY8cj6CkziWoUAObQVm7Ti5vGuS9yymXr8jwSy4xHnMeyrQTn7URqc EULxrcdbhv1vXhNGkfyHv1ZbW0VSdys6ZPUOYrz5JM7XTQRqcpqOCU6LOJuT2X2xkdEg wG09pkhLPjbXED5XNAsI/oa68QE5mIFnJTs/OjnElMUS1eXog8+4OkPTkc2f5fPKlmwD JzL4IDU4aGA/Kz4H3/5QU4zD6wfSUVK2YFStJjpIraQmV0Gz/iUffXplT4qj3BE/LtrM sTN2IdHxZFWLFQJ07B1GdzJh+GIi6vPkpQF37HfIua+u0c53H5DQxMg3XjfKX6xZDRHz TtGQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g14si1169463ybf.447.2022.01.06.02.53.37 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jan 2022 02:53:37 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:48998 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5QOm-0002XV-Qd for patch@linaro.org; Thu, 06 Jan 2022 05:53:36 -0500 Received: from eggs.gnu.org ([209.51.188.92]:32808) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDb-0007qc-FC for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:42:05 -0500 Received: from mout.kundenserver.de ([212.227.126.135]:44273) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDS-0004kE-Ob for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:42:01 -0500 Received: from quad ([82.142.12.178]) by mrelayeu.kundenserver.de (mreue012 [212.227.15.167]) with ESMTPSA (Nemesis) id 1Mm9NA-1mev9U3GYy-00iCIx; Thu, 06 Jan 2022 11:41:52 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PULL 22/27] linux-user/nios2: Fix sigmask in setup_rt_frame Date: Thu, 6 Jan 2022 11:41:32 +0100 Message-Id: <20220106104137.732883-23-laurent@vivier.eu> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220106104137.732883-1-laurent@vivier.eu> References: <20220106104137.732883-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:JuM+arCOkuDblzDDdPbSmwupkdklfOxrrbLKq8HEAz63N/0VEJS uDBGl357/KcVQNgddT5b0WXO+rdyUZZtw4zNgvUI/e6oNskEaALVFEs0aspnuMFFDVhA1cY 8XyulpOyo/oIp05e1oochfwE1LVgJIwvn88ZzI8GirFT7N2qj3/E5Z4+K1hTMk5+VZKzJhN NjVBfHSPz7VrSwTyXO0Kg== X-UI-Out-Filterresults: notjunk:1;V03:K0:yiBBcNyWuDI=:hRj3wpdN8QKgW2ZD6SZAZR eB/aG3o62qxX2CtSWAvARo9/THPqhY8f9WQJZsrK2k/RHILqvu5g+wcZBJ4c5yV49emRmzX0f uN8qgwx4wMDBv2a7PmsXnis+d01n3zIAbKxq4cLG4w2rLXgz1hSFAXaQUxRFHQmOQsdspILUs AkbcrWrQxMsSeTqgx0H6AbNul8LMGfw1bOCL0JwoX6RlUThKqXgNOFAhnkCHX2VkZ4wIBtT5z VgaR1E3+mNsUM9NGmQc1ehTw1rcsIDFzSjoroFwC4NWLl8nxK6SEQr00YbpCQQKQtJt9aU/Ix EZyYerx/brdLTR6D02QOVJh7mtcua6lePOj14L9Yl8qezWdBJINdfX91BSw8q2mZDo/vHLxAM IqL8RbJrLGJMpI4PWKyMBVskHLc5b/fDpJJyV8DqLLt/8UzC6cQPNFppxCXcVVqbAiLDKh0ty 9Ojwpvw498iXEKPhL/nke4swp6b5otHnPsQuCHG+ODVRRhgG9JCLtHmNuMXWmQPIkD8Mgd9ZS ZE1HMTN79SWTDhht2Q27Oguqvmv7MkogZRVvGYOV/D5TLb3o5G3VpHNgGIAlO21e4+jlOviG+ b14UNTlWIsj3k8tccndaRzTB+bNpS9EjNfBna+4VM6gV0LIMWiEqjRYp2vKJ8/kCmolIq/k+t tyzGhVDogqG/NpcNXvIdJs+FlyPgEjstnH7O9jXALONmPmgT/UBGCgPkVJUsax4/LMQU= Received-SPF: none client-ip=212.227.126.135; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Do not cast the signal mask elements; trust __put_user. Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson Message-Id: <20211221025012.1057923-7-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier --- linux-user/nios2/signal.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/linux-user/nios2/signal.c b/linux-user/nios2/signal.c index 20b65aa06e08..80e3d42fc965 100644 --- a/linux-user/nios2/signal.c +++ b/linux-user/nios2/signal.c @@ -168,8 +168,7 @@ void setup_rt_frame(int sig, struct target_sigaction *ka, target_save_altstack(&frame->uc.tuc_stack, env); rt_setup_ucontext(&frame->uc, env); for (i = 0; i < TARGET_NSIG_WORDS; i++) { - __put_user((abi_ulong)set->sig[i], - (abi_ulong *)&frame->uc.tuc_sigmask.sig[i]); + __put_user(set->sig[i], &frame->uc.tuc_sigmask.sig[i]); } /* Set up to return from userspace; jump to fixed address sigreturn From patchwork Thu Jan 6 10:41:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 530347 Delivered-To: patch@linaro.org Received: by 2002:ad5:544f:0:0:0:0:0 with SMTP id a15csp1065102imp; Thu, 6 Jan 2022 02:52:11 -0800 (PST) X-Google-Smtp-Source: ABdhPJyqjv1EIa/oohQRFkBuSYFBceUYXGyLwBuqswe87IAKAdRIHitLmhK1MQXB+AAMyQgsfVbU X-Received: by 2002:a25:b315:: with SMTP id l21mr55397349ybj.207.1641466331082; Thu, 06 Jan 2022 02:52:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1641466331; cv=none; d=google.com; s=arc-20160816; b=pNx8FJVPhLudF/7PwT3XM4xYyCHfIX774hyUyYMgXgUonIYD+zM1o9TTmgzsYcf4CN TrQ6uCG5zmeZ8C2w5XDDEGvlUKtkotlCrVxVYLkMENp+tnp58jnrHnyIJAYudtpu4z01 7dGSJcnU8wl6ypXXAHIyCUpYHDEDotVVz6j2ccJ5lGPyXvkrfcGLhmZXd2UdHzkOy26E kdShvbu7b3Yjk9whxTQwMQrZsSNh4r5FdxBY4DyPfwoY3OQ/IzriUa+wO8FKRWVE/Kd/ rMa+ib0wq14SxOmAHANQMb8CHnONH3DzDK40tnNUn2b5fufRAyIRIn2VoP0iRvZnFra1 g7dw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from; bh=11F3XQ28vJ8vzUyiMulcGxBc0rqrboBlUT6RbDiwl+c=; b=n0NMU383VY2FJpI5oFV2HwSkw9tORyljwTJYtk6l5V/YZmOsSm4p/k/rVm6AR0zqW9 6UYc+9UBDDnZJgKtVkRcmNmxv77RDs2/pbOAdwnu6m8sR2RQImPPi2raPvP4N/rYXWo1 gQhr7i8tU46DaICZK5R54Q3Ny9+TMVLcy59KOyXg40WBKAG3R/yaAWbBB9yWx974IfDJ NFeOsSJZrkxCSgvwcQOaZrDY+o5NkGLgKeaizo3F3BBd2xv2b17l+GP9OSsQt1wWIyKX FKVBNuYMhwwMN9wZu8R8MRLpx2oDDLwZNS3c4cX5m2GWzEhcNHEi5dQ/88i89HAtbjlU 6DJw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p8si1372369ybu.301.2022.01.06.02.52.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jan 2022 02:52:11 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:41016 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5QNO-0005fS-HD for patch@linaro.org; Thu, 06 Jan 2022 05:52:10 -0500 Received: from eggs.gnu.org ([209.51.188.92]:32816) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDb-0007qe-G9 for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:42:05 -0500 Received: from mout.kundenserver.de ([212.227.126.187]:37973) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDT-0004kK-1l for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:42:02 -0500 Received: from quad ([82.142.12.178]) by mrelayeu.kundenserver.de (mreue012 [212.227.15.167]) with ESMTPSA (Nemesis) id 1N1u2b-1mPjeS0iXx-012KWU; Thu, 06 Jan 2022 11:41:53 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PULL 23/27] linux-user/nios2: Use set_sigmask in do_rt_sigreturn Date: Thu, 6 Jan 2022 11:41:33 +0100 Message-Id: <20220106104137.732883-24-laurent@vivier.eu> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220106104137.732883-1-laurent@vivier.eu> References: <20220106104137.732883-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:G1CYcwi24EKj4DBof4R5whAD+q4axTF8BdkqPd4/LM9HETQdRz1 p9Qu1FHaQcIfOPszPbz57EuQrtp8LhBkuS19OvWw8ToQKsbbujGblzWqaCkD7XiM38cB3cn I3bnFyBWT4kM4OCtyyO+mw347TV+8cG9Rn5utEFnlCSC/d71M4SyIp2p+5kPXYbyQkIXQwV 1Z7ibGtFFrnBDNKF2gkKg== X-UI-Out-Filterresults: notjunk:1;V03:K0:kg3W/yigEMI=:lHWSmiuO1Xyi95l9MiNAMI VPPYvKPV6NTdzzRl7eJnJeBt1k1BvuFJY1DgIa6GZIwnxEDt1X88z3f1eydEkgRJ8sW5V7wSC Vci/TpPoviqwA2JlTg7CJLjRhnH7MZi/xxtQUeHzORLnm6VleAEKDa/b5tnfvSCKwvGltV2wb 90n2uKetZUXGPsPXUMKh9JB45isX+rRkR8eZjTS15vk/BlFptK0sc2FlPX36rz97e04uYSebA MBZQ9i1ivt4UJAbqn8I0uLXemSiqK/QcWcdhzUE7b46JMrXOko1deTapqB8t6+K7uLvKX8zKl rpFJci1a6+TE3DZD1v2iLQM1xLht1YQ1jCGyBQrk3eOOigKO0aDo7ErR7xM1n2Xy11PUhB1UQ W6mluu033uD9dMvQFj9J8M5QDkpu7kQAxooERDYSR+1nD9FhRRHJDrYfcxXDUx7JIwX1Md/qW 7ARfb1Is8W6umDKajAgu9wDGCJb+0r4qMRcM2mULaK1hNu06B2cUWU84At7/5EEJqMiItbUEg FTfZYij0FP5rSfaD1Z9a2cRaIvzzYIPEjqO504YTnYwspUKxL80UDxon15ZxPpLxFz/PtFO8y NooZ4j5Rn9dI0cRitAqsyJ0QdrnnS7q3EDbI7QPzWUD3EO+BdhHt760kYxIi3mmfW3E9aP3gy lRlKYVcOKpv3jJIgTvE0CfDZJthCH/Xg9Ea2hAUDtXgUHR5zWEEdDD7SLU4xBM9ShhnQ= Received-SPF: none client-ip=212.227.126.187; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Using do_sigprocmask directly was incorrect, as it will leave the signal blocked by the outer layers of linux-user. Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson Message-Id: <20211221025012.1057923-8-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier --- linux-user/nios2/signal.c | 2 +- linux-user/signal.c | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/linux-user/nios2/signal.c b/linux-user/nios2/signal.c index 80e3d42fc965..517cd392701c 100644 --- a/linux-user/nios2/signal.c +++ b/linux-user/nios2/signal.c @@ -205,7 +205,7 @@ long do_rt_sigreturn(CPUNios2State *env) } target_to_host_sigset(&set, &frame->uc.tuc_sigmask); - do_sigprocmask(SIG_SETMASK, &set, NULL); + set_sigmask(&set); if (rt_restore_ucontext(env, &frame->uc, &rval)) { goto badframe; diff --git a/linux-user/signal.c b/linux-user/signal.c index 1229fecf5cd4..f813b4f18e44 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -258,7 +258,6 @@ int do_sigprocmask(int how, const sigset_t *set, sigset_t *oldset) return 0; } -#if !defined(TARGET_NIOS2) /* Just set the guest's signal mask to the specified value; the * caller is assumed to have called block_signals() already. */ @@ -268,7 +267,6 @@ void set_sigmask(const sigset_t *set) ts->signal_mask = *set; } -#endif /* sigaltstack management */