From patchwork Mon Nov 19 01:01:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 151441 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2057596ljp; Sun, 18 Nov 2018 17:00:37 -0800 (PST) X-Google-Smtp-Source: AJdET5doxxqPLIMgCLq245MZCh0HPendRr8bI7sYp1IduRKxRXcNHJ+/+9dIh8mccMp4yhuVhFmT X-Received: by 2002:a63:5026:: with SMTP id e38mr18282184pgb.123.1542589237514; Sun, 18 Nov 2018 17:00:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542589237; cv=none; d=google.com; s=arc-20160816; b=025pVyZ0zrL090sduVpmT+VQ/F+yu/2dvXdf3BW2vsoYKVBPGsYWQ++xCE6VYAS1fx IEUlEZph0D7jj6r5mnPDksHR0HbwsoBhmWNqXJ/ppqJ3/JA5tIC+h4Xw1OnhpK8TynWy ODPqPx1gN2DF8SA0EePizhtjrGtZFOgC5JBHrfESQiWfn5guQpY15FSTbBPzHRTItd6l boKMZU16ird+GNi+KgSqoyC5YNVaWElbIUSbGFH2iy9uMrJc72Hh5t2pomBbyiL0uf2e yRn4wapiqovneKA7YM5o2dbjOnpnechkcXPjy8Nqygikkrh1j/o105LseIVsgjFh+v1O MqgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=rhwFspUU6/85fbLt7VjLBzvHaFRAv7suBfz+11KwdZ4=; b=tGwl2HTPBFOLa62DW+M2Uu9HChvyMgoYd+3G3iGYzaN7WZjxrNLzV9CkzCaWEusux6 FGTeYq47WHMuAdxvi3EZ0Ls3XKAzGB7WN26+IrNs6HiYgFBAx6VvOHr4yhN1Nsl3TtdE WcTIZMIIDA4qapbJA//8TBXnm0PZcxc2smwkpIOHrxQzbaP/LrgxYWlE2L7QFroDjZxB LCwSoda75PJGkucuklYaI6b/WEquUMDtnI5gODNMORTZeaFSK4Dn2jEvR0VxUp9tpbv0 jWoeNvV5kVsQmE8/aSCWe4kwXCTCXWAn+MVo/teZPSh4DFDW6KLfww6wbOipaG243SvR St3Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z13si2646694pgh.31.2018.11.18.17.00.37; Sun, 18 Nov 2018 17:00:37 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727490AbeKSLW2 (ORCPT + 32 others); Mon, 19 Nov 2018 06:22:28 -0500 Received: from mx.socionext.com ([202.248.49.38]:40664 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726520AbeKSLW1 (ORCPT ); Mon, 19 Nov 2018 06:22:27 -0500 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 19 Nov 2018 10:00:32 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 37484180111; Mon, 19 Nov 2018 10:00:32 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Mon, 19 Nov 2018 10:00:32 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id B3AA640387; Mon, 19 Nov 2018 10:00:31 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 92832120455; Mon, 19 Nov 2018 10:00:31 +0900 (JST) From: Sugaya Taichi To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Russell King , Jiri Slaby , Masami Hiramatsu , Jassi Brar , Sugaya Taichi Subject: [PATCH 02/14] dt-bindings: soc: milbeaut: Add Milbeaut trampoline description Date: Mon, 19 Nov 2018 10:01:07 +0900 Message-Id: <1542589274-13878-3-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1542589274-13878-1-git-send-email-sugaya.taichi@socionext.com> References: <1542589274-13878-1-git-send-email-sugaya.taichi@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add DT bindings document for Milbeaut trampoline. Signed-off-by: Sugaya Taichi --- .../devicetree/bindings/soc/socionext/socionext,m10v.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,m10v.txt -- 1.9.1 diff --git a/Documentation/devicetree/bindings/soc/socionext/socionext,m10v.txt b/Documentation/devicetree/bindings/soc/socionext/socionext,m10v.txt new file mode 100644 index 0000000..f5d906c --- /dev/null +++ b/Documentation/devicetree/bindings/soc/socionext/socionext,m10v.txt @@ -0,0 +1,12 @@ +Socionext M10V SMP trampoline driver binding + +This is a driver to wait for sub-cores while boot process. + +- compatible: should be "socionext,smp-trampoline" +- reg: should be <0x4C000100 0x100> + +EXAMPLE + trampoline: trampoline@0x4C000100 { + compatible = "socionext,smp-trampoline"; + reg = <0x4C000100 0x100>; + }; From patchwork Mon Nov 19 01:01:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 151442 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2057642ljp; Sun, 18 Nov 2018 17:00:40 -0800 (PST) X-Google-Smtp-Source: AJdET5euPIVsTrGzJSydm6B5Uft45hPDe8gPNkDA+iiNDLtMZZ75fm2KhpyEWgZV7EP7ae5kFIV1 X-Received: by 2002:a17:902:bb86:: with SMTP id m6mr20555629pls.315.1542589240839; Sun, 18 Nov 2018 17:00:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542589240; cv=none; d=google.com; s=arc-20160816; b=TyfIvwTxixqCM2CBHTuyxUHTN/gmDRonTDZHJBmrPiERcMfFEKtaVFfxlhqzTelQkE MlZmzqauWFMEoGJgpBXWwvSp5TMrjhwD4HOGqeOZzSw4y+E4ZCpqx/SK/dXCRiQ18Cyv /WU9Bgh5VpEVoDpU4kRsIJvfvG7ghK95Lr/A9F5EBo3lCLvuXhCcc5n0pFlLpoo0/jDR O4P37H28yDFP9vbfS+1LKi4IUAq2gcpVZFk9BmLPrd926LnSSkws7YLJguTnIT4QjSDp suJOnViWz5kyl30nkII30Y03IxU1TTkqWTd4uWUHGQDYSxHOGUk/4NSwBQ9goy8u9HeK U08g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=+ZzJLIOddXXCJiJ/uq4PNVXLO4hPhqn1t2ruihFITak=; b=WwaElWmEmAav3oA/iJAK1iDUkmO54WIFKPAF+ZBwYUxzBWLvSjtnKb5FtclAbFRiIz 4sFGX9uJ+3rRNQYatfzCl7TSVLs8pDkMPbu/XEs8WVryKUB23M6yljoeua8RsQnKx85X CxDUntAVhys8u9ieY918RwF2bj3WFmAyzISJRAnhE7h0r6E0xRmYK0HwEyEw3XvRimds eKSkK4uMfyADgrS4skAG8lMngBoB5zvq40fITpyilAM5/h1EBguhdAcC8vnbw+I4WqJL ABtUzMOCEZDJ+HAI/s9cPdwRZ7dnP/XwSDpcwWMTXmov09s23wkUqx71M78YQFLzx5oj SJYQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 37-v6si40400258ple.389.2018.11.18.17.00.40; Sun, 18 Nov 2018 17:00:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727675AbeKSLWb (ORCPT + 32 others); Mon, 19 Nov 2018 06:22:31 -0500 Received: from mx.socionext.com ([202.248.49.38]:40673 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726520AbeKSLWb (ORCPT ); Mon, 19 Nov 2018 06:22:31 -0500 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 19 Nov 2018 10:00:35 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 4F7F6180111; Mon, 19 Nov 2018 10:00:35 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Mon, 19 Nov 2018 10:00:35 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id B0C8740387; Mon, 19 Nov 2018 10:00:33 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 8EDB2120455; Mon, 19 Nov 2018 10:00:33 +0900 (JST) From: Sugaya Taichi To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Russell King , Jiri Slaby , Masami Hiramatsu , Jassi Brar , Sugaya Taichi Subject: [PATCH 03/14] ARM: milbeaut: Add Milbeaut M10V early printk Date: Mon, 19 Nov 2018 10:01:08 +0900 Message-Id: <1542589274-13878-4-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1542589274-13878-1-git-send-email-sugaya.taichi@socionext.com> References: <1542589274-13878-1-git-send-email-sugaya.taichi@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add Milbeaut M10V earlyprintk. Signed-off-by: Sugaya Taichi --- arch/arm/Kconfig.debug | 12 ++++++++++-- arch/arm/include/debug/milbeaut.S | 25 +++++++++++++++++++++++++ 2 files changed, 35 insertions(+), 2 deletions(-) create mode 100644 arch/arm/include/debug/milbeaut.S -- 1.9.1 diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index d6a49f5..5c44533 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -1413,6 +1413,11 @@ choice options; the platform specific options are deprecated and will be soon removed. + config DEBUG_LL_MILBEAUT_UART + bool "Kernel low-level debug output via USIO" + depends on ARCH_MILBEAUT + help + Say Y here if you want to debug with USIO endchoice config DEBUG_AT91_UART @@ -1534,6 +1539,7 @@ config DEBUG_LL_INCLUDE default "debug/bcm63xx.S" if DEBUG_BCM63XX_UART default "debug/digicolor.S" if DEBUG_DIGICOLOR_UA0 default "debug/brcmstb.S" if DEBUG_BRCMSTB_UART + default "debug/milbeaut.S" if DEBUG_LL_MILBEAUT_UART default "mach/debug-macro.S" # Compatibility options for PL01x @@ -1580,6 +1586,7 @@ config DEBUG_UART_PHYS default 0x18020000 if DEBUG_SIRFATLAS7_UART1 default 0x18023000 if DEBUG_BCM_IPROC_UART3 default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1 + default 0x1e700010 if ARCH_MILBEAUT_M10V default 0x20001000 if DEBUG_HIP01_UART default 0x20060000 if DEBUG_RK29_UART0 default 0x20064000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2 @@ -1681,7 +1688,7 @@ config DEBUG_UART_PHYS DEBUG_S3C64XX_UART || \ DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \ DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0 || \ - DEBUG_AT91_UART + DEBUG_AT91_UART || DEBUG_LL_MILBEAUT_UART config DEBUG_UART_VIRT hex "Virtual base address of debug UART" @@ -1755,6 +1762,7 @@ config DEBUG_UART_VIRT default 0xfe100000 if DEBUG_IMX23_UART || DEBUG_IMX28_UART default 0xfe230000 if DEBUG_PICOXCELL_UART default 0xfe300000 if DEBUG_BCM_KONA_UART + default 0xfe700010 if ARCH_MILBEAUT_M10V default 0xfe800000 if ARCH_IOP32X default 0xfeb00000 if DEBUG_HI3620_UART || DEBUG_HIX5HD2_UART default 0xfeb24000 if DEBUG_RK3X_UART0 @@ -1796,7 +1804,7 @@ config DEBUG_UART_VIRT DEBUG_S3C64XX_UART || \ DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \ DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0 || \ - DEBUG_AT91_UART + DEBUG_AT91_UART || DEBUG_LL_MILBEAUT_UART config DEBUG_UART_8250_SHIFT int "Register offset shift for the 8250 debug UART" diff --git a/arch/arm/include/debug/milbeaut.S b/arch/arm/include/debug/milbeaut.S new file mode 100644 index 0000000..0660e0f --- /dev/null +++ b/arch/arm/include/debug/milbeaut.S @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Socionext Inc. + */ + + .macro addruart, rp, rv, tmp + ldr \rp, =CONFIG_DEBUG_UART_PHYS + ldr \rv, =CONFIG_DEBUG_UART_VIRT + .endm + + .macro senduart,rd,rx + strh \rd, [\rx, #0x04] @ write to TxData register + .endm + + .macro waituart,rd,rx +1: ldrb \rd, [\rx, #0x03] @ SSR + tst \rd, #1 << 1 @ check TDRE bit + beq 1b + .endm + + .macro busyuart,rd,rx +2: ldrb \rd, [\rx, #0x03] @ SSR + tst \rd, #1 << 1 @ check TEMT bit + beq 2b + .endm From patchwork Mon Nov 19 01:01:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 151453 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2058700ljp; Sun, 18 Nov 2018 17:01:39 -0800 (PST) X-Google-Smtp-Source: AJdET5c8ItOVft7Ye+I/WtCpanUnYwDmcEAwiDqTsMtJ2uEyenfZ7Sz+KoMAmegX91imKIwLSn+f X-Received: by 2002:a63:101d:: with SMTP id f29mr18358429pgl.38.1542589299353; Sun, 18 Nov 2018 17:01:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542589299; cv=none; d=google.com; s=arc-20160816; b=rTno1IpWbUbyuCjUd4DoN77M1NJSmh1SaqTcJ3q5ZzNJcTgJNzj7YXmkRgKsfriE7a X5YUJIB83jqNLBhjBdnrzICuo2Qo1/OcPooeQRuDSQxpCDwITLRK8SEq26mZHAKjzVu3 O36Gl7YYe/C+fvw46uAPwYayENhEsDJsyuf1q74PE7jH3Njx7BXvKcwvTcLA2E+tokqb 3jZDmZ78wGC0+bkP+GU9Jn02ZwJ0Ifa0KmTjzRdAleV/Vj3Mwo+Gw/JS5xzT72TrKra9 QTDAfk4FwBUGiUcWlZiMCTalTBIR2/8bjYx4PsM54IWa3Im3jO1w3vUOw677vr46z2yk HRmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=llkiED9iR0TtFZHiP1jsNA5wixWkE1OXqsRM3RgKyww=; b=PoUfhLij+JPaFdPQvxOMP5AGvzKLs6nu2TogxEOnmJDJyjove9Qvc8QXSNtyoHjQFV xgkVuHluVTPX9HL3CaEwHIAJYPA5dbaM1eobbaP46vnjs055saJOtPt9qknOyvoVj9I/ Ne09k7gF5zRMfBOWMZTmvtfWdptR2kJXO80H5MMwqZZyq32A6Yn36uKwM7VvxNDv4TOk cpYZoZB1L2WrVqa7fXcE1sPDOqv9o/kvgzzQ790+RVD79qanK8qfoxFHCYEqcIrFVwek jzFWRmr4auUgUka0po/cbFa3U+AyVCGxZ3l0OSz4FnvaFSdLuxeHZ1V5m6rhS7V6LgUP g4yQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j14si27250996pgg.44.2018.11.18.17.01.38; Sun, 18 Nov 2018 17:01:39 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727843AbeKSLWd (ORCPT + 32 others); Mon, 19 Nov 2018 06:22:33 -0500 Received: from mx.socionext.com ([202.248.49.38]:40673 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727507AbeKSLWd (ORCPT ); Mon, 19 Nov 2018 06:22:33 -0500 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 19 Nov 2018 10:00:36 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 63F9C180111; Mon, 19 Nov 2018 10:00:36 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Mon, 19 Nov 2018 10:00:36 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id 1066840387; Mon, 19 Nov 2018 10:00:36 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id DCB0F120455; Mon, 19 Nov 2018 10:00:35 +0900 (JST) From: Sugaya Taichi To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Russell King , Jiri Slaby , Masami Hiramatsu , Jassi Brar , Sugaya Taichi Subject: [PATCH 05/14] clocksource/drivers/timer-milbeaut: Add Milbeaut M10V timer Date: Mon, 19 Nov 2018 10:01:10 +0900 Message-Id: <1542589274-13878-6-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1542589274-13878-1-git-send-email-sugaya.taichi@socionext.com> References: <1542589274-13878-1-git-send-email-sugaya.taichi@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add Milbeaut M10V timer using 32bit timer in peripheral. Signed-off-by: Sugaya Taichi --- drivers/clocksource/Kconfig | 8 +++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-m10v.c | 146 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 155 insertions(+) create mode 100644 drivers/clocksource/timer-m10v.c -- 1.9.1 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 55c77e4..a278d72 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -638,4 +638,12 @@ config GX6605S_TIMER help This option enables support for gx6605s SOC's timer. +config M10V_TIMER + bool "Milbeaut M10V timer driver" if COMPILE_TEST + depends on OF + depends on ARM + select TIMER_OF + help + Enables the support for Milbeaut M10V timer driver. + endmenu diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index dd91381..8e908b4 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -55,6 +55,7 @@ obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o obj-$(CONFIG_OWL_TIMER) += timer-owl.o +obj-$(CONFIG_M10V_TIMER) += timer-m10v.o obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o obj-$(CONFIG_NPCM7XX_TIMER) += timer-npcm7xx.o diff --git a/drivers/clocksource/timer-m10v.c b/drivers/clocksource/timer-m10v.c new file mode 100644 index 0000000..ff97c23 --- /dev/null +++ b/drivers/clocksource/timer-m10v.c @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Socionext Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "timer-of.h" + +#define FSL_TMR_TMCSR_OFS 0x0 +#define FSL_TMR_TMR_OFS 0x4 +#define FSL_TMR_TMRLR1_OFS 0x8 +#define FSL_TMR_TMRLR2_OFS 0xc +#define FSL_RMT_REGSZPCH 0x10 + +#define FSL_TMR_TMCSR_OUTL BIT(5) +#define FSL_TMR_TMCSR_RELD BIT(4) +#define FSL_TMR_TMCSR_INTE BIT(3) +#define FSL_TMR_TMCSR_UF BIT(2) +#define FSL_TMR_TMCSR_CNTE BIT(1) +#define FSL_TMR_TMCSR_TRG BIT(0) + +#define FSL_TMR_TMCSR_CSL_DIV2 0 +#define FSL_TMR_TMCSR_CSL BIT(10) + +#define M10V_TIMER_RATING 500 + +static irqreturn_t m10v_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *clk = dev_id; + struct timer_of *to = to_timer_of(clk); + u32 val; + + val = readl_relaxed(timer_of_base(to) + FSL_TMR_TMCSR_OFS); + val &= ~FSL_TMR_TMCSR_UF; + writel_relaxed(val, timer_of_base(to) + FSL_TMR_TMCSR_OFS); + + clk->event_handler(clk); + + return IRQ_HANDLED; +} + +static int m10v_set_state_periodic(struct clock_event_device *clk) +{ + struct timer_of *to = to_timer_of(clk); + u32 val = (FSL_TMR_TMCSR_CSL_DIV2 * FSL_TMR_TMCSR_CSL); + + writel_relaxed(val, timer_of_base(to) + FSL_TMR_TMCSR_OFS); + + writel_relaxed(to->of_clk.period, timer_of_base(to) + + FSL_TMR_TMRLR1_OFS); + val |= FSL_TMR_TMCSR_RELD | FSL_TMR_TMCSR_CNTE | + FSL_TMR_TMCSR_TRG | FSL_TMR_TMCSR_INTE; + writel_relaxed(val, timer_of_base(to) + FSL_TMR_TMCSR_OFS); + return 0; +} + +static int m10v_set_state_oneshot(struct clock_event_device *clk) +{ + struct timer_of *to = to_timer_of(clk); + u32 val = (FSL_TMR_TMCSR_CSL_DIV2 * FSL_TMR_TMCSR_CSL); + + writel_relaxed(val, timer_of_base(to) + FSL_TMR_TMCSR_OFS); + return 0; +} + +static int m10v_clkevt_next_event(unsigned long event, + struct clock_event_device *clk) +{ + struct timer_of *to = to_timer_of(clk); + + writel_relaxed(event, timer_of_base(to) + FSL_TMR_TMRLR1_OFS); + writel_relaxed((FSL_TMR_TMCSR_CSL_DIV2 * FSL_TMR_TMCSR_CSL) | + FSL_TMR_TMCSR_CNTE | FSL_TMR_TMCSR_INTE | + FSL_TMR_TMCSR_TRG, timer_of_base(to) + + FSL_TMR_TMCSR_OFS); + return 0; +} + +static int m10v_config_clock_source(struct timer_of *to) +{ + writel_relaxed(0, timer_of_base(to) + FSL_TMR_TMCSR_OFS); + writel_relaxed(~0, timer_of_base(to) + FSL_TMR_TMR_OFS); + writel_relaxed(~0, timer_of_base(to) + FSL_TMR_TMRLR1_OFS); + writel_relaxed(~0, timer_of_base(to) + FSL_TMR_TMRLR2_OFS); + writel_relaxed(BIT(4) | BIT(1) | BIT(0), timer_of_base(to) + + FSL_TMR_TMCSR_OFS); + return 0; +} + +static int m10v_config_clock_event(struct timer_of *to) +{ + writel_relaxed(0, timer_of_base(to) + FSL_TMR_TMCSR_OFS); + return 0; +} + +static struct timer_of to = { + .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK, + + .clkevt = { + .name = "m10v-clkevt", + .rating = M10V_TIMER_RATING, + .cpumask = cpu_possible_mask, + }, + + .of_irq = { + .flags = IRQF_TIMER | IRQF_IRQPOLL, + }, +}; + +static int __init m10v_timer_init(struct device_node *node) +{ + int ret; + + to.clkevt.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT; + to.clkevt.set_state_oneshot = m10v_set_state_oneshot; + to.clkevt.set_state_periodic = m10v_set_state_periodic; + to.clkevt.set_next_event = m10v_clkevt_next_event; + to.of_irq.handler = m10v_timer_interrupt; + + ret = timer_of_init(node, &to); + if (ret) + goto err; + + m10v_config_clock_source(&to); + clocksource_mmio_init(timer_of_base(&to) + FSL_TMR_TMR_OFS, + node->name, timer_of_rate(&to), M10V_TIMER_RATING, 32, + clocksource_mmio_readl_down); + m10v_config_clock_event(&to); + clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), + 15, 0xffffffff); + + return 0; +err: + timer_of_cleanup(&to); + return ret; +} +TIMER_OF_DECLARE(m10v_peritimer, "socionext,milbeaut-m10v-timer", + m10v_timer_init); From patchwork Mon Nov 19 01:01:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 151444 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2057686ljp; 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[209.132.180.67]) by mx.google.com with ESMTP id u8-v6si35184988pgj.409.2018.11.18.17.00.43; Sun, 18 Nov 2018 17:00:43 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727958AbeKSLWe (ORCPT + 32 others); Mon, 19 Nov 2018 06:22:34 -0500 Received: from mx.socionext.com ([202.248.49.38]:40693 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727622AbeKSLWd (ORCPT ); Mon, 19 Nov 2018 06:22:33 -0500 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 19 Nov 2018 10:00:37 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 5BD0060062; Mon, 19 Nov 2018 10:00:37 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Mon, 19 Nov 2018 10:00:37 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id C36A740387; Mon, 19 Nov 2018 10:00:36 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id A489C120455; Mon, 19 Nov 2018 10:00:36 +0900 (JST) From: Sugaya Taichi To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Russell King , Jiri Slaby , Masami Hiramatsu , Jassi Brar , Sugaya Taichi Subject: [PATCH 06/14] dt-bindings: clock: milbeaut: add Milbeaut clock description Date: Mon, 19 Nov 2018 10:01:11 +0900 Message-Id: <1542589274-13878-7-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1542589274-13878-1-git-send-email-sugaya.taichi@socionext.com> References: <1542589274-13878-1-git-send-email-sugaya.taichi@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add DT bindings document for Milbeaut clock. Signed-off-by: Sugaya Taichi --- .../devicetree/bindings/clock/milbeaut-clock.txt | 93 ++++++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/milbeaut-clock.txt -- 1.9.1 diff --git a/Documentation/devicetree/bindings/clock/milbeaut-clock.txt b/Documentation/devicetree/bindings/clock/milbeaut-clock.txt new file mode 100644 index 0000000..5c093c8 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/milbeaut-clock.txt @@ -0,0 +1,93 @@ +Milbeaut M10V Clock Controller Binding +---------------------------------------- +Milbeaut clock controller is consists of few oscillators, PLL, multiplexer +and few divider modules + +This binding uses common clock bindings +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible: shall be "socionext,milbeaut-m10v-clk-regs" +- reg: shall contain base address and length of clock registers +- #clock-cells: shall be 0 + +Example: + m10v-clk-tree@ { + compatible = "socionext,milbeaut-m10v-clk-regs"; + reg = <0x1d021000 0x4000>; + + clocks { + #address-cells = <0>; + #size-cells = <0>; + + uclk40xi: uclk40xi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + }; + } + +The clock consumer shall specify the desired clock-output of the clock +controller (as defined in [2]) by specifying output-id in its "clock" +phandle cell +[2] arch/arm/boot/dts/milbeaut-m10v-clk.h + +For example for UART1: + usio1: usio_uart@1e700010 { + index = <0>; + compatible = "socionext,milbeaut-m10v-usio-uart"; + reg = <0x1e700010 0x10>; + interrupts = <0 141 0x4>, <0 149 0x4>; + interrupt-names = "rx", "tx"; + clocks = <&hclk>; + }; + + + + +Required properties: +- compatible: + "socionext,milbeaut-m10v-clk-mux" + -clock-cells: should be 0 + -clocks: should be two factor + "socionext,milbeaut-m10v-pll-fixed-factor" + -clock-cells: should be 0 + -clocks: should be one factor + -offset: offset + -clock-div: div number + -clock-mult: multiple number + "socionext,milbeaut-m10v-clk-div" + -clock-cells: should be 0 + -clocks: should be one factor + -offset: offset + -mask: mask bit + -ratios: div ratio + +Example + piclk_mux_0: spiclk_mux_0 { + compatible = "socionext,m10v-clk-div"; + #clock-cells = <0>; + clocks = <&pll10_div_1_2>; + offset = ; + mask = <0x3>; + ratios = <4 0x5 2 0x4>; + }; + + pll10: pll10 { + compatible = "socionext,m10v-pll-fixed-factor"; + #clock-cells = <0>; + clocks = <&uclk40xi>; + offset = <10>; + clock-div = <5>; + clock-mult = <108>; + }; + + emmcclk: emmcclk { + compatible = "socionext,m10v-clk-div"; + #clock-cells = <0>; + clocks = <&pll11>; + offset = ; + mask = <0x3>; + ratios = <15 0x7 10 0x6 9 0x5 8 0x4>; + }; From patchwork Mon Nov 19 01:01:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 151446 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2057697ljp; Sun, 18 Nov 2018 17:00:44 -0800 (PST) X-Google-Smtp-Source: AJdET5dElzcTC+4Ynpm5VQAwW+rZVyQ407ngLmxL6x28m4pU8bUWmd6MoA4eYhtDLQMss8456QxL X-Received: by 2002:a63:e80e:: with SMTP id s14mr18260007pgh.30.1542589243998; Sun, 18 Nov 2018 17:00:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542589243; cv=none; d=google.com; s=arc-20160816; b=fhO34yDXuohJ/aknTr7TXw6t2I2/mnPjGhmT25Mn+syAvDrZsJ59RAzkDyzQJBMPeu eZayFC1ER1z1UlkzxBtCnYxd54OjzO+RqTdSaE62glNKX2XQ+zDFVBD+gEn4oOuetB00 OFs7K5YZN9sM1c8pogxQPytx5vKhzFITimsvb3//AblL7MNnD0IcPFd8ceB96cxVyUVA 9bTw+8e9z8uKVBwtiOygkCyRBZpPYqN6qp9n7lZNaFPh3Hv05IfiTboxqx3FDCq1Zjug 11271GimiQzTqtPBtn547BWQV877Z2FaYjmuVhyuB+ef6qq0uDhtD3plLrGolaGbNboe A73A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=XFzSUAh89IrHUVFePFTbTdNkJhcM7u5iabsMk3rHBSU=; b=F3TEkaPIxPgTOEN1DUyU82ieU+yL/X5C7qT+i2aqtBkWI2tzuno/exN0UCvLwoiadt NEh63qTjg4XmhvRgtO/cK4x2/yWC+FJd+NB2S+IQuGCTobuvlRFVPCkF/hFbNSXNppFA XLJCN567yNnzgJCPt2MfZrj/KUilubo8opTfa99x2qrfvROC/zjZ11B7TJ3GiEu4chng eGu9d9BSt84e7J/6KHbWmzPaTAY1GjlrhdKvdwlIq30Mn6bDnoqwBF3/Y5gCLiEOajNP JTTIyCgwQTUfTU/0PLmxJLRS/32oVJY1nK70VB27iNzhTfSem3oE6a+14m3p6c9acQNT /d/w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u8-v6si35184988pgj.409.2018.11.18.17.00.43; Sun, 18 Nov 2018 17:00:43 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728085AbeKSLWf (ORCPT + 32 others); Mon, 19 Nov 2018 06:22:35 -0500 Received: from mx.socionext.com ([202.248.49.38]:40685 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726520AbeKSLWf (ORCPT ); Mon, 19 Nov 2018 06:22:35 -0500 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 19 Nov 2018 10:00:38 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id E7888180111; Mon, 19 Nov 2018 10:00:37 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Mon, 19 Nov 2018 10:00:37 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id 8232240387; Mon, 19 Nov 2018 10:00:37 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 63A2A120455; Mon, 19 Nov 2018 10:00:37 +0900 (JST) From: Sugaya Taichi To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Russell King , Jiri Slaby , Masami Hiramatsu , Jassi Brar , Sugaya Taichi Subject: [PATCH 07/14] clock: milbeaut: Add Milbeaut M10V clock control Date: Mon, 19 Nov 2018 10:01:12 +0900 Message-Id: <1542589274-13878-8-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1542589274-13878-1-git-send-email-sugaya.taichi@socionext.com> References: <1542589274-13878-1-git-send-email-sugaya.taichi@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add Milbeaut M10V clock ( including PLL ) control. Signed-off-by: Sugaya Taichi --- drivers/clk/Makefile | 1 + drivers/clk/clk-m10v.c | 671 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 672 insertions(+) create mode 100644 drivers/clk/clk-m10v.c -- 1.9.1 diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 72be7a3..da5b282 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o +obj-$(CONFIG_ARCH_MILBEAUT_M10V) += clk-m10v.o obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o obj-$(CONFIG_COMMON_CLK_MAX9485) += clk-max9485.o obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o diff --git a/drivers/clk/clk-m10v.c b/drivers/clk/clk-m10v.c new file mode 100644 index 0000000..aa92a69 --- /dev/null +++ b/drivers/clk/clk-m10v.c @@ -0,0 +1,671 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Socionext Inc. + * Copyright (C) 2016 Linaro Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define CLKSEL1 0x0 +#define CLKSEL(n) (((n) - 1) * 4 + CLKSEL1) + +#define PLLCNT1 0x30 +#define PLLCNT(n) (((n) - 1) * 4 + PLLCNT1) + +#define CLKSTOP1 0x54 +#define CLKSTOP(n) (((n) - 1) * 4 + CLKSTOP1) + +#define CRSWR 0x8c +#define CRRRS 0x90 +#define CRRSM 0x94 + +#define to_m10v_mux(_hw) container_of(_hw, struct m10v_mux, hw) +#define to_m10v_gate(_hw) container_of(_hw, struct m10v_gate, hw) +#define to_m10v_div(_hw) container_of(_hw, struct m10v_div, hw) +#define to_m10v_pll(_hw) container_of(_hw, struct m10v_pll, hw) + +static void __iomem *clk_base; +static struct device_node *np_top; +static DEFINE_SPINLOCK(crglock); + +static __init void __iomem *m10v_clk_iomap(void) +{ + if (clk_base) + return clk_base; + + np_top = of_find_compatible_node(NULL, NULL, + "socionext,milbeaut-m10v-clk-regs"); + if (!np_top) { + pr_err("%s: CLK iomap failed!\n", __func__); + return NULL; + } + + clk_base = of_iomap(np_top, 0); + of_node_put(np_top); + + return clk_base; +} + +struct m10v_mux { + struct clk_hw hw; + const char *cname; + u32 parent; +}; + +static u8 m10v_mux_get_parent(struct clk_hw *hw) +{ + struct m10v_mux *mcm = to_m10v_mux(hw); + struct clk_hw *parent; + int i; + + i = clk_hw_get_num_parents(hw); + while (i--) { + parent = clk_hw_get_parent_by_index(hw, i); + if (clk_hw_get_rate(parent)) + break; + } + + if (i < 0) { + pr_info("%s:%s no parent?!\n", + __func__, mcm->cname); + i = 0; + } + + return i; +} + +static int m10v_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct m10v_mux *mcm = to_m10v_mux(hw); + + mcm->parent = index; + return 0; +} + +static const struct clk_ops m10v_mux_ops = { + .get_parent = m10v_mux_get_parent, + .set_parent = m10v_mux_set_parent, + .determine_rate = __clk_mux_determine_rate, +}; + +void __init m10v_clk_mux_setup(struct device_node *node) +{ + const char *clk_name = node->name; + struct clk_init_data init; + const char **parent_names; + struct m10v_mux *mcm; + struct clk *clk; + int i, parents; + + if (!m10v_clk_iomap()) + return; + + of_property_read_string(node, "clock-output-names", &clk_name); + + parents = of_clk_get_parent_count(node); + if (parents < 2) { + pr_err("%s: not a mux\n", clk_name); + return; + } + + parent_names = kzalloc((sizeof(char *) * parents), GFP_KERNEL); + if (!parent_names) + return; + + for (i = 0; i < parents; i++) + parent_names[i] = of_clk_get_parent_name(node, i); + + mcm = kzalloc(sizeof(*mcm), GFP_KERNEL); + if (!mcm) + goto err_mcm; + + init.name = clk_name; + init.ops = &m10v_mux_ops; + init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT; + init.num_parents = parents; + init.parent_names = parent_names; + + mcm->cname = clk_name; + mcm->parent = 0; + mcm->hw.init = &init; + + clk = clk_register(NULL, &mcm->hw); + if (IS_ERR(clk)) + goto err_clk; + + of_clk_add_provider(node, of_clk_src_simple_get, clk); + return; + +err_clk: + kfree(mcm); +err_mcm: + kfree(parent_names); +} +CLK_OF_DECLARE(m10v_clk_mux, "socionext,milbeaut-m10v-clk-mux", + m10v_clk_mux_setup); + +struct m10v_pll { + struct clk_hw hw; + const char *cname; + const struct clk_ops ops; + u32 offset; + u32 div, mult; + bool ro; +}; + +#define ST 1 +#define SEL 2 + +static void _mpg_enable(struct clk_hw *hw, unsigned int enable) +{ + struct m10v_pll *mpg = to_m10v_pll(hw); + unsigned long flags; + u32 val; + + if (mpg->ro) { + pr_debug("%s:%d %s: read-only\n", + __func__, __LINE__, mpg->cname); + return; + } + + spin_lock_irqsave(&crglock, flags); + + val = readl(clk_base + PLLCNT(SEL)); + if (enable) + val |= BIT(mpg->offset); + else + val &= ~BIT(mpg->offset); + writel(val, clk_base + PLLCNT(SEL)); + + spin_unlock_irqrestore(&crglock, flags); +} + +static int mpg_enable(struct clk_hw *hw) +{ + _mpg_enable(hw, 1); + return 0; +} + +static void mpg_disable(struct clk_hw *hw) +{ + _mpg_enable(hw, 0); +} + +static int mpg_is_enabled(struct clk_hw *hw) +{ + struct m10v_pll *mpg = to_m10v_pll(hw); + + return readl(clk_base + PLLCNT(SEL)) & (1 << mpg->offset); +} + +static void _mpg_prepare(struct clk_hw *hw, unsigned int on) +{ + struct m10v_pll *mpg = to_m10v_pll(hw); + unsigned long flags; + u32 val; + + if (mpg->ro) { + pr_debug("%s:%d %s: read-only\n", + __func__, __LINE__, mpg->cname); + return; + } + + val = readl(clk_base + PLLCNT(ST)); + if (!on == !(val & BIT(mpg->offset))) + return; + + /* disable */ + mpg_disable(hw); + + spin_lock_irqsave(&crglock, flags); + + val = readl(clk_base + PLLCNT(ST)); + if (on) + val |= BIT(mpg->offset); + else + val &= ~BIT(mpg->offset); + writel(val, clk_base + PLLCNT(ST)); + + spin_unlock_irqrestore(&crglock, flags); + + udelay(on ? 200 : 10); +} + +static int mpg_prepare(struct clk_hw *hw) +{ + _mpg_prepare(hw, 1); + return 0; +} + +static void mpg_unprepare(struct clk_hw *hw) +{ + _mpg_prepare(hw, 0); +} + +static int mpg_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate) +{ + return 0; +} + +static unsigned long mpg_recalc_rate(struct clk_hw *hw, + unsigned long prate) +{ + struct m10v_pll *mpg = to_m10v_pll(hw); + unsigned long long rate = prate; + + if (mpg_is_enabled(hw)) { + rate = (unsigned long long)prate * mpg->mult; + do_div(rate, mpg->div); + } + + return (unsigned long)rate; +} + +static long mpg_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct m10v_pll *mpg = to_m10v_pll(hw); + unsigned long long temp_rate = (unsigned long long)*prate * mpg->mult; + + if (mpg->ro) + return mpg_recalc_rate(hw, *prate); + + return do_div(temp_rate, mpg->div); +} + +static const struct clk_ops m10v_pll_ops = { + .prepare = mpg_prepare, + .enable = mpg_enable, + .is_enabled = mpg_is_enabled, + .disable = mpg_disable, + .unprepare = mpg_unprepare, + .round_rate = mpg_round_rate, + .set_rate = mpg_set_rate, + .recalc_rate = mpg_recalc_rate, +}; + +void __init m10v_pll_setup(struct device_node *node) +{ + const char *clk_name = node->name; + struct clk_init_data init; + const char *parent_name; + u32 offset, div, mult; + struct m10v_pll *mpg; + struct clk *clk; + int ret; + + if (!m10v_clk_iomap()) + return; + + of_property_read_string(node, "clock-output-names", &clk_name); + + ret = of_property_read_u32(node, "offset", &offset); + if (ret) { + pr_err("%s: missing 'offset' property\n", clk_name); + return; + } + + div = mult = 1; + of_property_read_u32(node, "clock-div", &div); + of_property_read_u32(node, "clock-mult", &mult); + + parent_name = of_clk_get_parent_name(node, 0); + + mpg = kzalloc(sizeof(*mpg), GFP_KERNEL); + if (!mpg) + return; + + init.name = clk_name; + init.ops = &m10v_pll_ops; + init.flags = CLK_IS_BASIC | CLK_SET_RATE_GATE; + init.parent_names = &parent_name; + init.num_parents = 1; + + mpg->cname = clk_name; + mpg->offset = offset; + mpg->div = div; + mpg->mult = mult; + mpg->hw.init = &init; + if (of_get_property(node, "read-only", NULL)) + mpg->ro = true; + + clk = clk_register(NULL, &mpg->hw); + if (IS_ERR(clk)) + kfree(mpg); + else + of_clk_add_provider(node, of_clk_src_simple_get, clk); +} +CLK_OF_DECLARE(m10v_clk_pll_gate, "socionext,milbeaut-m10v-pll-fixed-factor", + m10v_pll_setup); + +struct m10v_div { + struct clk_hw hw; + const char *cname; + bool waitdchreq; + u32 offset; + u32 mask; + u32 *table; + u32 tlen; + bool ro; +}; + +static void mdc_set_div(struct m10v_div *mdc, u32 div) +{ + u32 off, shift, val; + + off = mdc->offset / 32 * 4; + shift = mdc->offset % 32; + + val = readl(clk_base + CLKSEL1 + off); + val &= ~(mdc->mask << shift); + val |= (div << shift); + writel(val, clk_base + CLKSEL1 + off); + + if (mdc->waitdchreq) { + unsigned int count = 250; + + writel(1, clk_base + CLKSEL(11)); + + do { + udelay(1); + } while (--count && readl(clk_base + CLKSEL(11)) & 1); + + if (!count) + pr_err("%s:%s CLK(%d) couldn't stabilize\n", + __func__, mdc->cname, mdc->offset); + } +} + +static u32 mdc_get_div(struct m10v_div *mdc) +{ + u32 off, shift, div; + + off = mdc->offset / 32 * 4; + shift = mdc->offset % 32; + + div = readl(clk_base + CLKSEL1 + off); + div >>= shift; + div &= mdc->mask; + + return div; +} + +static int mdc_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate) +{ + struct m10v_div *mdc = to_m10v_div(hw); + u64 pr; + int i; + + if (mdc->ro) { + pr_debug("%s:%d %s: read-only\n", + __func__, __LINE__, mdc->cname); + return 0; + } + + /* divisors are already in descending order in DT */ + for (i = mdc->tlen - 2; i >= 0; i -= 2) { + pr = prate; + do_div(pr, mdc->table[i]); + + if (rate >= pr) + break; + } + if (i < 0) + i = 0; + + mdc_set_div(mdc, mdc->table[i + 1]); + + return 0; +} + +static unsigned long mdc_div_recalc_rate(struct clk_hw *hw, + unsigned long prate) +{ + struct m10v_div *mdc = to_m10v_div(hw); + u64 prate64 = prate; + u32 div; + int i; + + div = mdc_get_div(mdc); + + for (i = 1; i < mdc->tlen && div != mdc->table[i]; i += 2) + if (div == (mdc->table[i] & mdc->mask)) + break; /* the MSB is already read back as 0 */ + + if (i > mdc->tlen) /* some other is enabled in the mux */ + prate64 = 0; + else + do_div(prate64, mdc->table[i - 1]); + + return (unsigned long)prate64; +} + +static long mdc_div_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent) +{ + struct m10v_div *mdc = to_m10v_div(hw); + u64 prate; + int i; + + if (mdc->ro) + return mdc_div_recalc_rate(hw, *parent); + + /* divisors are already in descending order in DT */ + for (i = mdc->tlen - 2; i >= 0; i -= 2) { + prate = *parent; + do_div(prate, mdc->table[i]); + + if (rate >= prate) + break; + } + + return (unsigned long)prate; +} + +static const struct clk_ops m10v_div_ops = { + .round_rate = mdc_div_round_rate, + .set_rate = mdc_div_set_rate, + .recalc_rate = mdc_div_recalc_rate, +}; + +void __init m10v_clk_div_setup(struct device_node *node) +{ + const char *clk_name = node->name; + struct clk_init_data init; + const char *parent_name; + struct m10v_div *mdc; + struct clk *clk; + u32 *table, mask; + u32 offset; + int count, ret; + + if (!m10v_clk_iomap()) + return; + + of_property_read_string(node, "clock-output-names", &clk_name); + + parent_name = of_clk_get_parent_name(node, 0); + if (!parent_name) { + pr_err("%s: no parent specified\n", clk_name); + return; + } + + ret = of_property_read_u32(node, "offset", &offset); + if (ret) { + pr_err("%s: missing 'offset' property\n", clk_name); + return; + } + + ret = of_property_read_u32(node, "mask", &mask); + if (ret) { + pr_err("%s: missing 'mask' property\n", clk_name); + return; + } + + count = of_property_count_u32_elems(node, "ratios"); + if (count < 2 || count%2) { + pr_err("%s: invalid 'ratios' property\n", clk_name); + return; + } + + table = kzalloc(sizeof(*table) * count, GFP_KERNEL); + if (!table) + return; + + /* + * The 'ratios' must be in descending order, we park at + * first ratio (biggest divider) when disabled. + */ + ret = of_property_read_u32_array(node, "ratios", table, count); + if (ret) { + pr_err("%s: 'ratios' property read fail\n", clk_name); + goto err_mdc; + } + + mdc = kzalloc(sizeof(*mdc), GFP_KERNEL); + if (!mdc) + goto err_mdc; + + if (of_get_property(node, "wait-on-dchreq", NULL)) + mdc->waitdchreq = true; + + init.name = clk_name; + init.ops = &m10v_div_ops; + init.flags = CLK_IS_BASIC; + init.parent_names = &parent_name; + init.num_parents = 1; + + mdc->cname = clk_name; + mdc->offset = offset; + mdc->mask = mask; + mdc->table = table; + mdc->tlen = count; + mdc->hw.init = &init; + if (of_get_property(node, "read-only", NULL)) + mdc->ro = true; + + clk = clk_register(NULL, &mdc->hw); + if (IS_ERR(clk)) + goto err_clk; + + of_clk_add_provider(node, of_clk_src_simple_get, clk); + return; + +err_clk: + kfree(mdc); +err_mdc: + kfree(table); +} +CLK_OF_DECLARE(m10v_clk_div, "socionext,milbeaut-m10v-clk-div", + m10v_clk_div_setup); + +struct m10v_gate { + struct clk_hw hw; + const char *cname; + u32 offset; + bool ro; +}; + +static void _mgc_enable(struct clk_hw *hw, bool en) +{ + struct m10v_gate *mgc = to_m10v_gate(hw); + u32 off, mask; + + if (mgc->ro) { + pr_debug("%s:%d %s: read-only\n", + __func__, __LINE__, mgc->cname); + return; + } + + off = CLKSTOP1 + (mgc->offset / 32) * 4; + + mask = (en ? 2 : 3) << (mgc->offset % 32); + + writel(mask, clk_base + off); +} + +static int mgc_enable(struct clk_hw *hw) +{ + _mgc_enable(hw, true); + return 0; +} + +static void mgc_disable(struct clk_hw *hw) +{ + _mgc_enable(hw, false); +} + +static int mgc_is_enabled(struct clk_hw *hw) +{ + struct m10v_gate *mgc = to_m10v_gate(hw); + u32 off, val, mask = 1 << (mgc->offset % 32); + + off = CLKSTOP1 + (mgc->offset / 32) * 4; + val = readl(clk_base + off); + + return !(val & mask); +} + +static const struct clk_ops m10v_gate_ops = { + .enable = mgc_enable, + .disable = mgc_disable, + .is_enabled = mgc_is_enabled, +}; + +void __init m10v_clk_gate_setup(struct device_node *node) +{ + const char *clk_name = node->name; + struct clk_init_data init; + const char *parent_name; + struct m10v_gate *mgc; + struct clk *clk; + u32 offset; + int ret; + + if (!m10v_clk_iomap()) + return; + + of_property_read_string(node, "clock-output-names", &clk_name); + + ret = of_property_read_u32(node, "offset", &offset); + if (ret) { + pr_err("%s: missing 'offset' property\n", clk_name); + return; + } + + parent_name = of_clk_get_parent_name(node, 0); + + mgc = kzalloc(sizeof(*mgc), GFP_KERNEL); + if (!mgc) + return; + + init.name = clk_name; + init.ops = &m10v_gate_ops; + init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT; + init.parent_names = &parent_name; + init.num_parents = 1; + + mgc->cname = clk_name; + mgc->offset = offset; + mgc->hw.init = &init; + if (of_get_property(node, "read-only", NULL)) + mgc->ro = true; + + clk = clk_register(NULL, &mgc->hw); + if (IS_ERR(clk)) + kfree(mgc); + else + of_clk_add_provider(node, of_clk_src_simple_get, clk); +} +CLK_OF_DECLARE(m10v_clk_gate, "socionext,milbeaut-m10v-clk-gate", + m10v_clk_gate_setup); From patchwork Mon Nov 19 01:01:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 151447 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2057756ljp; Sun, 18 Nov 2018 17:00:47 -0800 (PST) X-Google-Smtp-Source: AJdET5fiSa43iBe80syBG9X9XGuPHVFlfZd0QEbRTl4gk2/OilKojgQu5wtwaamZ6sNMS6y29QPb X-Received: by 2002:a63:b94c:: with SMTP id v12mr18060681pgo.221.1542589247786; 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[209.132.180.67]) by mx.google.com with ESMTP id r26-v6si39062353pgb.372.2018.11.18.17.00.47; Sun, 18 Nov 2018 17:00:47 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728133AbeKSLWj (ORCPT + 32 others); Mon, 19 Nov 2018 06:22:39 -0500 Received: from mx.socionext.com ([202.248.49.38]:40700 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727622AbeKSLWh (ORCPT ); Mon, 19 Nov 2018 06:22:37 -0500 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 19 Nov 2018 10:00:39 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id EA8B8180111; Mon, 19 Nov 2018 10:00:39 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Mon, 19 Nov 2018 10:00:39 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id 686CC40387; Mon, 19 Nov 2018 10:00:39 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 44E6B120455; Mon, 19 Nov 2018 10:00:39 +0900 (JST) From: Sugaya Taichi To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Russell King , Jiri Slaby , Masami Hiramatsu , Jassi Brar , Sugaya Taichi Subject: [PATCH 09/14] serial: Add Milbeaut M10V serial control Date: Mon, 19 Nov 2018 10:01:14 +0900 Message-Id: <1542589274-13878-10-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1542589274-13878-1-git-send-email-sugaya.taichi@socionext.com> References: <1542589274-13878-1-git-send-email-sugaya.taichi@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add Milbeaut M10V serial control. Signed-off-by: Sugaya Taichi --- drivers/tty/serial/Kconfig | 24 ++ drivers/tty/serial/Makefile | 1 + drivers/tty/serial/m10v_usio.c | 605 +++++++++++++++++++++++++++++++++++++++ include/uapi/linux/serial_core.h | 3 + 4 files changed, 633 insertions(+) create mode 100644 drivers/tty/serial/m10v_usio.c -- 1.9.1 diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 32886c3..cd28a7e 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1529,6 +1529,30 @@ config SERIAL_OWL_CONSOLE Say 'Y' here if you wish to use Actions Semiconductor S500/S900 UART as the system console. +config SERIAL_M10V_USIO + tristate "M10V USIO/UART serial port support" + depends on ARCH_MILBEAUT + default y + select SERIAL_CORE + help + This selects the USIO/UART IP found in Socionext Milbeaut M10V. + +config SERIAL_M10V_USIO_PORTS + int "Maximum number of CSIO/UART ports (1-8)" + range 1 8 + depends on SERIAL_M10V_USIO + default "4" + +config SERIAL_M10V_USIO_CONSOLE + bool "Support for console on M10V USIO/UART serial port" + depends on SERIAL_M10V_USIO=y + select SERIAL_CORE_CONSOLE + help + Say 'Y' here if you wish to use a USIO/UART of Socionext Milbeaut + M10V as the system console (the system console is the device which + receives all kernel messages and warnings and which allows logins in + single user mode). + endmenu config SERIAL_MCTRL_GPIO diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index daac675..5ea46bc 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -89,6 +89,7 @@ obj-$(CONFIG_SERIAL_MVEBU_UART) += mvebu-uart.o obj-$(CONFIG_SERIAL_PIC32) += pic32_uart.o obj-$(CONFIG_SERIAL_MPS2_UART) += mps2-uart.o obj-$(CONFIG_SERIAL_OWL) += owl-uart.o +obj-$(CONFIG_SERIAL_M10V_USIO) += m10v_usio.o # GPIOLIB helpers for modem control lines obj-$(CONFIG_SERIAL_MCTRL_GPIO) += serial_mctrl_gpio.o diff --git a/drivers/tty/serial/m10v_usio.c b/drivers/tty/serial/m10v_usio.c new file mode 100644 index 0000000..3abb465 --- /dev/null +++ b/drivers/tty/serial/m10v_usio.c @@ -0,0 +1,605 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Socionext Inc. + */ + +#if defined(CONFIG_SERIAL_M10V_USIO_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) +#define SUPPORT_SYSRQ +#endif + +#include +#include +#include +#include +#include +#include +#include +#include + + +#define USIO_NAME "sn-usio-uart" +#define USIO_UART_DEV_NAME "ttyUSI" + +static struct uart_port usio_ports[CONFIG_SERIAL_M10V_USIO_PORTS]; + +#define RX 0 +#define TX 1 +static int usio_irq[CONFIG_SERIAL_M10V_USIO_PORTS][2]; + +#define SN_USIO_REG_SMR 0 +#define SN_USIO_REG_SCR 1 +#define SN_USIO_REG_ESCR 2 +#define SN_USIO_REG_SSR 3 +#define SN_USIO_REG_DR 4 +#define SN_USIO_REG_BGR 6 +#define SN_USIO_REG_FCR 12 +#define SN_USIO_REG_FBYTE 14 + +#define SN_USIO_SMR_SOE BIT(0) +#define SN_USIO_SMR_SBL BIT(3) +#define SN_USIO_SCR_TXE BIT(0) +#define SN_USIO_SCR_RXE BIT(1) +#define SN_USIO_SCR_TBIE BIT(2) +#define SN_USIO_SCR_TIE BIT(3) +#define SN_USIO_SCR_RIE BIT(4) +#define SN_USIO_SCR_UPCL BIT(7) +#define SN_USIO_ESCR_L_8BIT 0 +#define SN_USIO_ESCR_L_5BIT 1 +#define SN_USIO_ESCR_L_6BIT 2 +#define SN_USIO_ESCR_L_7BIT 3 +#define SN_USIO_ESCR_P BIT(3) +#define SN_USIO_ESCR_PEN BIT(4) +#define SN_USIO_ESCR_FLWEN BIT(7) +#define SN_USIO_SSR_TBI BIT(0) +#define SN_USIO_SSR_TDRE BIT(1) +#define SN_USIO_SSR_RDRF BIT(2) +#define SN_USIO_SSR_ORE BIT(3) +#define SN_USIO_SSR_FRE BIT(4) +#define SN_USIO_SSR_PE BIT(5) +#define SN_USIO_SSR_REC BIT(7) +#define SN_USIO_SSR_BRK BIT(8) +#define SN_USIO_FCR_FE1 BIT(0) +#define SN_USIO_FCR_FE2 BIT(1) +#define SN_USIO_FCR_FCL1 BIT(2) +#define SN_USIO_FCR_FCL2 BIT(3) +#define SN_USIO_FCR_FSET BIT(4) +#define SN_USIO_FCR_FTIE BIT(9) +#define SN_USIO_FCR_FDRQ BIT(10) +#define SN_USIO_FCR_FRIIE BIT(11) + +static void usio_stop_tx(struct uart_port *port) +{ + writew(readw(port->membase + SN_USIO_REG_FCR) & ~SN_USIO_FCR_FTIE, + port->membase + SN_USIO_REG_FCR); + writeb(readb(port->membase + SN_USIO_REG_SCR) & ~SN_USIO_SCR_TBIE, + port->membase + SN_USIO_REG_SCR); +} + +static void usio_tx_chars(struct uart_port *port) +{ + struct circ_buf *xmit = &port->state->xmit; + int count; + + writew(readw(port->membase + SN_USIO_REG_FCR) & ~SN_USIO_FCR_FTIE, + port->membase + SN_USIO_REG_FCR); + writeb(readb(port->membase + SN_USIO_REG_SCR) & + ~(SN_USIO_SCR_TIE | SN_USIO_SCR_TBIE), + port->membase + SN_USIO_REG_SCR); + + if (port->x_char) { + writew(port->x_char, port->membase + SN_USIO_REG_DR); + port->icount.tx++; + port->x_char = 0; + return; + } + if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { + usio_stop_tx(port); + return; + } + + count = port->fifosize - + (readw(port->membase + SN_USIO_REG_FBYTE) & 0xff); + + do { + writew(xmit->buf[xmit->tail], port->membase + SN_USIO_REG_DR); + + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + port->icount.tx++; + if (uart_circ_empty(xmit)) + break; + + } while (--count > 0); + + writew(readw(port->membase + SN_USIO_REG_FCR) & ~SN_USIO_FCR_FDRQ, + port->membase + SN_USIO_REG_FCR); + + writeb(readb(port->membase + SN_USIO_REG_SCR) | SN_USIO_SCR_TBIE, + port->membase + SN_USIO_REG_SCR); + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(port); + + if (uart_circ_empty(xmit)) + usio_stop_tx(port); +} + +static void usio_start_tx(struct uart_port *port) +{ + u16 fcr = readw(port->membase + SN_USIO_REG_FCR); + + writew(fcr | SN_USIO_FCR_FTIE, port->membase + SN_USIO_REG_FCR); + if (!(fcr & SN_USIO_FCR_FDRQ)) + return; + + writeb(readb(port->membase + SN_USIO_REG_SCR) | SN_USIO_SCR_TBIE, + port->membase + SN_USIO_REG_SCR); + + if (readb(port->membase + SN_USIO_REG_SSR) & SN_USIO_SSR_TBI) + usio_tx_chars(port); +} + +static void usio_stop_rx(struct uart_port *port) +{ + writeb(readb(port->membase + SN_USIO_REG_SCR) & ~SN_USIO_SCR_RIE, + port->membase + SN_USIO_REG_SCR); +} + +static void usio_enable_ms(struct uart_port *port) +{ + writeb(readb(port->membase + SN_USIO_REG_SCR) | + SN_USIO_SCR_RIE | SN_USIO_SCR_RXE, + port->membase + SN_USIO_REG_SCR); +} + +static void usio_rx_chars(struct uart_port *port) +{ + struct tty_port *ttyport = &port->state->port; + unsigned long flag = 0; + char ch = 0; + u8 status; + int max_count = 2; + + while (max_count--) { + status = readb(port->membase + SN_USIO_REG_SSR); + + if (!(status & SN_USIO_SSR_RDRF)) + break; + + if (!(status & (SN_USIO_SSR_ORE | SN_USIO_SSR_FRE | + SN_USIO_SSR_PE))) { + ch = readw(port->membase + SN_USIO_REG_DR); + flag = TTY_NORMAL; + port->icount.rx++; + if (uart_handle_sysrq_char(port, ch)) + continue; + uart_insert_char(port, status, SN_USIO_SSR_ORE, + ch, flag); + continue; + } + if (status & SN_USIO_SSR_PE) + port->icount.parity++; + if (status & SN_USIO_SSR_ORE) + port->icount.overrun++; + status &= port->read_status_mask; + if (status & SN_USIO_SSR_BRK) { + flag = TTY_BREAK; + ch = 0; + } else + if (status & SN_USIO_SSR_PE) { + flag = TTY_PARITY; + ch = 0; + } else + if (status & SN_USIO_SSR_FRE) { + flag = TTY_FRAME; + ch = 0; + } + if (flag) + uart_insert_char(port, status, SN_USIO_SSR_ORE, + ch, flag); + + writeb(readb(port->membase + SN_USIO_REG_SSR) | SN_USIO_SSR_REC, + port->membase + SN_USIO_REG_SSR); + + max_count = readw(port->membase + SN_USIO_REG_FBYTE) >> 8; + writew(readw(port->membase + SN_USIO_REG_FCR) | + SN_USIO_FCR_FE2 | SN_USIO_FCR_FRIIE, + port->membase + SN_USIO_REG_FCR); + } + + tty_flip_buffer_push(ttyport); +} + +static irqreturn_t usio_rx_irq(int irq, void *dev_id) +{ + struct uart_port *port = dev_id; + + spin_lock(&port->lock); + usio_rx_chars(port); + spin_unlock(&port->lock); + + return IRQ_HANDLED; +} + +static irqreturn_t usio_tx_irq(int irq, void *dev_id) +{ + struct uart_port *port = dev_id; + + spin_lock(&port->lock); + if (readb(port->membase + SN_USIO_REG_SSR) & SN_USIO_SSR_TBI) + usio_tx_chars(port); + spin_unlock(&port->lock); + + return IRQ_HANDLED; +} + +static unsigned int usio_tx_empty(struct uart_port *port) +{ + return (readb(port->membase + SN_USIO_REG_SSR) & SN_USIO_SSR_TBI) ? + TIOCSER_TEMT : 0; +} + +static void usio_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ +} + +static unsigned int usio_get_mctrl(struct uart_port *port) +{ + return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; + +} + +static void usio_break_ctl(struct uart_port *port, int break_state) +{ +} + +static int usio_startup(struct uart_port *port) +{ + const char *portname = to_platform_device(port->dev)->name; + unsigned long flags; + int ret, index = port->line; + unsigned char escr; + + ret = request_irq(usio_irq[index][RX], usio_rx_irq, 0, portname, port); + if (ret) + return ret; + ret = request_irq(usio_irq[index][TX], usio_tx_irq, 0, portname, port); + if (ret) { + free_irq(usio_irq[index][RX], port); + return ret; + } + + escr = readb(port->membase + SN_USIO_REG_ESCR); + if (of_property_read_bool(port->dev->of_node, "uart-flow-enable")) + escr |= SN_USIO_ESCR_FLWEN; + spin_lock_irqsave(&port->lock, flags); + writeb(0, port->membase + SN_USIO_REG_SCR); + writeb(escr, port->membase + SN_USIO_REG_ESCR); + writeb(SN_USIO_SCR_UPCL, port->membase + SN_USIO_REG_SCR); + writeb(SN_USIO_SSR_REC, port->membase + SN_USIO_REG_SSR); + writew(0, port->membase + SN_USIO_REG_FCR); + writew(SN_USIO_FCR_FCL1 | SN_USIO_FCR_FCL2, + port->membase + SN_USIO_REG_FCR); + writew(SN_USIO_FCR_FE1 | SN_USIO_FCR_FE2 | SN_USIO_FCR_FRIIE, + port->membase + SN_USIO_REG_FCR); + writew(0, port->membase + SN_USIO_REG_FBYTE); + writew(BIT(12), port->membase + SN_USIO_REG_FBYTE); + + writeb(SN_USIO_SCR_TXE | SN_USIO_SCR_RIE | SN_USIO_SCR_TBIE | + SN_USIO_SCR_RXE, port->membase + SN_USIO_REG_SCR); + spin_unlock_irqrestore(&port->lock, flags); + + return 0; +} + +static void usio_shutdown(struct uart_port *port) +{ + int index = port->line; + + free_irq(usio_irq[index][RX], port); + free_irq(usio_irq[index][TX], port); +} + +static void usio_set_termios(struct uart_port *port, struct ktermios *termios, + struct ktermios *old) +{ + unsigned int escr, smr = SN_USIO_SMR_SOE; + unsigned long flags, baud, quot; + + switch (termios->c_cflag & CSIZE) { + case CS5: + escr = SN_USIO_ESCR_L_5BIT; + break; + case CS6: + escr = SN_USIO_ESCR_L_6BIT; + break; + case CS7: + escr = SN_USIO_ESCR_L_7BIT; + break; + case CS8: + default: + escr = SN_USIO_ESCR_L_8BIT; + break; + } + + if (termios->c_cflag & CSTOPB) + smr |= SN_USIO_SMR_SBL; + + if (termios->c_cflag & PARENB) { + escr |= SN_USIO_ESCR_PEN; + if (termios->c_cflag & PARODD) + escr |= SN_USIO_ESCR_P; + } + /* Set hard flow control */ + if (of_property_read_bool(port->dev->of_node, "uart-flow-enable") || + (termios->c_cflag & CRTSCTS)) + escr |= SN_USIO_ESCR_FLWEN; + + baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk); + if (baud > 1) + quot = port->uartclk / baud - 1; + else + quot = 0; + + spin_lock_irqsave(&port->lock, flags); + uart_update_timeout(port, termios->c_cflag, baud); + port->read_status_mask = SN_USIO_SSR_ORE | SN_USIO_SSR_RDRF | + SN_USIO_SSR_TDRE; + if (termios->c_iflag & INPCK) + port->read_status_mask |= SN_USIO_SSR_FRE | SN_USIO_SSR_PE; + + port->ignore_status_mask = 0; + if (termios->c_iflag & IGNPAR) + port->ignore_status_mask |= SN_USIO_SSR_FRE | SN_USIO_SSR_PE; + if ((termios->c_iflag & IGNBRK) && (termios->c_iflag & IGNPAR)) + port->ignore_status_mask |= SN_USIO_SSR_ORE; + if ((termios->c_cflag & CREAD) == 0) + port->ignore_status_mask |= SN_USIO_SSR_RDRF; + + writeb(0, port->membase + SN_USIO_REG_SCR); + writeb(SN_USIO_SCR_UPCL, port->membase + SN_USIO_REG_SCR); + writeb(SN_USIO_SSR_REC, port->membase + SN_USIO_REG_SSR); + writew(0, port->membase + SN_USIO_REG_FCR); + writeb(smr, port->membase + SN_USIO_REG_SMR); + writeb(escr, port->membase + SN_USIO_REG_ESCR); + writew(quot, port->membase + SN_USIO_REG_BGR); + writew(0, port->membase + SN_USIO_REG_FCR); + writew(SN_USIO_FCR_FCL1 | SN_USIO_FCR_FCL2 | SN_USIO_FCR_FE1 | + SN_USIO_FCR_FE2 | SN_USIO_FCR_FRIIE, + port->membase + SN_USIO_REG_FCR); + writew(0, port->membase + SN_USIO_REG_FBYTE); + writew(BIT(12), port->membase + SN_USIO_REG_FBYTE); + writeb(SN_USIO_SCR_RIE | SN_USIO_SCR_RXE | SN_USIO_SCR_TBIE | + SN_USIO_SCR_TXE, port->membase + SN_USIO_REG_SCR); + spin_unlock_irqrestore(&port->lock, flags); +} + +static const char *usio_type(struct uart_port *port) +{ + return ((port->type == PORT_SN_USIO) ? USIO_NAME : NULL); +} + +static void usio_config_port(struct uart_port *port, int flags) +{ + if (flags & UART_CONFIG_TYPE) + port->type = PORT_SN_USIO; +} + +static const struct uart_ops usio_ops = { + .tx_empty = usio_tx_empty, + .set_mctrl = usio_set_mctrl, + .get_mctrl = usio_get_mctrl, + .stop_tx = usio_stop_tx, + .start_tx = usio_start_tx, + .stop_rx = usio_stop_rx, + .enable_ms = usio_enable_ms, + .break_ctl = usio_break_ctl, + .startup = usio_startup, + .shutdown = usio_shutdown, + .set_termios = usio_set_termios, + .type = usio_type, + .config_port = usio_config_port, +}; + +#ifdef CONFIG_SERIAL_M10V_USIO_CONSOLE + +static void usio_console_putchar(struct uart_port *port, int c) +{ + while (!(readb(port->membase + SN_USIO_REG_SSR) & SN_USIO_SSR_TDRE)) + cpu_relax(); + + writew(c, port->membase + SN_USIO_REG_DR); +} + +static void usio_console_write(struct console *co, const char *s, + unsigned int count) +{ + struct uart_port *port = &usio_ports[co->index]; + + uart_console_write(port, s, count, usio_console_putchar); +} + +static int __init usio_console_setup(struct console *co, char *options) +{ + struct uart_port *port; + int baud = 115200; + int parity = 'n'; + int flow = 'n'; + int bits = 8; + + if (co->index >= CONFIG_SERIAL_M10V_USIO_PORTS) + return -ENODEV; + + port = &usio_ports[co->index]; + if (!port->membase) + return -ENODEV; + + + if (options) + uart_parse_options(options, &baud, &parity, &bits, &flow); + + if (of_property_read_bool(port->dev->of_node, "uart-flow-enable")) + flow = 'r'; + + return uart_set_options(port, co, baud, parity, bits, flow); +} + + +static struct uart_driver usio_uart_driver; +static struct console usio_console = { + .name = USIO_UART_DEV_NAME, + .write = usio_console_write, + .device = uart_console_device, + .setup = usio_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, + .data = &usio_uart_driver, +}; + +static int __init usio_console_init(void) +{ + register_console(&usio_console); + return 0; +} +console_initcall(usio_console_init); + +#define USIO_CONSOLE (&usio_console) +#else +#define USIO_CONSOLE NULL +#endif + + +static struct uart_driver usio_uart_driver = { + .owner = THIS_MODULE, + .driver_name = USIO_NAME, + .dev_name = USIO_UART_DEV_NAME, + .cons = USIO_CONSOLE, + .nr = CONFIG_SERIAL_M10V_USIO_PORTS, +}; + +static int usio_probe(struct platform_device *pdev) +{ + struct clk *clk = devm_clk_get(&pdev->dev, 0); + struct uart_port *port; + struct resource *res; + int index = 0; + int ret; + + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "Missing clock\n"); + return PTR_ERR(clk); + } + ret = clk_prepare_enable(clk); + if (ret) { + dev_err(&pdev->dev, "Clock enable failed: %d\n", ret); + return ret; + } + of_property_read_u32(pdev->dev.of_node, "index", &index); + port = &usio_ports[index]; + + port->private_data = (void *)clk; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&pdev->dev, "Missing regs\n"); + ret = -ENODEV; + goto failed; + } + port->mapbase = res->start; + port->membase = ioremap(res->start, (res->end - res->start + 1)); + port->membase = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + + ret = platform_get_irq_byname(pdev, "rx"); + usio_irq[index][RX] = ret; + + ret = platform_get_irq_byname(pdev, "tx"); + usio_irq[index][TX] = ret; + + port->irq = usio_irq[index][RX]; + port->uartclk = clk_get_rate(clk); + port->fifosize = 128; + port->iotype = UPIO_MEM32; + port->flags = UPF_BOOT_AUTOCONF | UPF_SPD_VHI; + port->line = index; + port->ops = &usio_ops; + port->dev = &pdev->dev; + + ret = uart_add_one_port(&usio_uart_driver, port); + if (ret) { + dev_err(&pdev->dev, "Adding port failed: %d\n", ret); + goto failed1; + } + return 0; + +failed1: + iounmap(port->membase); + +failed: + clk_disable_unprepare(clk); + clk_put(clk); + + return ret; +} + +static int usio_remove(struct platform_device *pdev) +{ + struct uart_port *port = &usio_ports[pdev->id]; + struct clk *clk = port->private_data; + + uart_remove_one_port(&usio_uart_driver, port); + clk_disable_unprepare(clk); + clk_put(clk); + + return 0; +} + +#define usio_suspend NULL +#define usio_resume NULL + +static const struct of_device_id m10v_usio_dt_ids[] = { + { .compatible = "socionext,milbeaut-m10v-usio-uart" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, m10v_usio_dt_ids); + +static struct platform_driver usio_driver = { + .probe = usio_probe, + .remove = usio_remove, + .suspend = usio_suspend, + .resume = usio_resume, + .driver = { + .name = USIO_NAME, + .of_match_table = m10v_usio_dt_ids, + }, +}; + +static int __init usio_init(void) +{ + int ret = uart_register_driver(&usio_uart_driver); + + if (ret) { + pr_err("%s: uart registration failed: %d\n", __func__, ret); + return ret; + } + ret = platform_driver_register(&usio_driver); + if (ret) { + uart_unregister_driver(&usio_uart_driver); + pr_err("%s: drv registration failed: %d\n", __func__, ret); + return ret; + } + + return 0; +} + +static void __exit usio_exit(void) +{ + platform_driver_unregister(&usio_driver); + uart_unregister_driver(&usio_uart_driver); +} + +module_init(usio_init); +module_exit(usio_exit); + +MODULE_AUTHOR("SOCIONEXT"); +MODULE_DESCRIPTION("SN_USIO/UART Driver"); +MODULE_LICENSE("GPL"); + diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h index dce5f9d..984df0d 100644 --- a/include/uapi/linux/serial_core.h +++ b/include/uapi/linux/serial_core.h @@ -281,4 +281,7 @@ /* MediaTek BTIF */ #define PORT_MTK_BTIF 117 +/* Socionext UART */ +#define PORT_SN_USIO 118 + #endif /* _UAPILINUX_SERIAL_CORE_H */ From patchwork Mon Nov 19 01:02:12 2018 Content-Type: text/plain; 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[209.132.180.67]) by mx.google.com with ESMTP id f5si38977196pgr.411.2018.11.18.17.01.00; Sun, 18 Nov 2018 17:01:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728170AbeKSLWw (ORCPT + 32 others); Mon, 19 Nov 2018 06:22:52 -0500 Received: from mx.socionext.com ([202.248.49.38]:40713 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727622AbeKSLWv (ORCPT ); Mon, 19 Nov 2018 06:22:51 -0500 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 19 Nov 2018 10:00:55 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 96EFC180111; Mon, 19 Nov 2018 10:00:55 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Mon, 19 Nov 2018 10:00:55 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id 0BB8840387; Mon, 19 Nov 2018 10:00:55 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id DFBBE120455; Mon, 19 Nov 2018 10:00:54 +0900 (JST) From: Sugaya Taichi To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Russell King , Jiri Slaby , Masami Hiramatsu , Jassi Brar , Sugaya Taichi Subject: [PATCH 10/14] dt-bindings: pinctrl: milbeaut: Add Milbeaut M10V pinctrl description Date: Mon, 19 Nov 2018 10:02:12 +0900 Message-Id: <1542589336-13925-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add DT bindings document for Milbeaut M10V pinctrl. Signed-off-by: Sugaya Taichi --- .../pinctrl/socionext,milbeaut-pinctrl.txt | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt -- 1.9.1 diff --git a/Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt new file mode 100644 index 0000000..7469189 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt @@ -0,0 +1,33 @@ +Milbeaut SoCs pin controller + +Required properties: +- compatible: should be one of the following: + "socionext,milbeaut-m10v-pinctrl" - for m10v SoC +- reg: offset and length of the register set. +- reg-names: should be "pinctrl", "exiu". +- gpio-cells; should be 2. +- interrupt-cells: should be 2. +- clocks: phandle to the input clock. +- interrupts: three interrupts specifer. +- interrupt-names: corresponds "interrupts" factor. + +Example: + pinctrl: pinctrl@1d022000 { + compatible = "socionext,milbeaut-m10v-pinctrl"; + reg = <0x1d022000 0x1000>, + <0x1c26f000 0x1000>; + reg-names = "pinctrl", "exiu"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&dummy_clk>; + interrupts = <0 54 4>, <0 55 4>, <0 56 4>, <0 57 4>, + <0 58 4>, <0 59 4>, <0 60 4>, <0 61 4>, + <0 62 4>, <0 63 4>, <0 64 4>, <0 65 4>, + <0 66 4>, <0 67 4>, <0 68 4>, <0 69 4>; + interrupt-names = "pin-48", "pin-49", "pin-50", "pin-51", + "pin-52", "pin-53", "pin-54", "pin-55", + "pin-56", "pin-57", "pin-58", "pin-59", + "pin-60", "pin-61", "pin-62", "pin-63"; + } From patchwork Mon Nov 19 01:02:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 151452 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2058316ljp; Sun, 18 Nov 2018 17:01:18 -0800 (PST) X-Google-Smtp-Source: AJdET5exxfpek9NSkMGszYN8cihG2xY20b3oe8k3w/Jx4C19uk4xP697C8DhTcyi1olkQY5pDx8K X-Received: by 2002:a17:902:6686:: with SMTP id e6-v6mr20053853plk.173.1542589278256; Sun, 18 Nov 2018 17:01:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542589278; cv=none; d=google.com; s=arc-20160816; b=DZOc0liBECyHiudmDVnKdyFtar1flR0R4tSGvu8qVRvIo2+DiU7uhUp1kdluf3PdlQ 9T0ZpyQfUu92Pmb4dO86PtYW+4LpRdfE+6iJgcmd424Npfxs91xR6i9/qf4mAPjOMM3p t7a9TP9/IWTrCcoslBlFAerDUOiTDe/jI8fShYQsQ9BM1fonuhmqcJztmSw+kMwlSeyU lamaPYkFL0u63nINzNXJ0G70167hljwrGN3IWQqOOuIUY84YdKTwtoHNMvDGCbUGtzcZ uX+8iwhIrXM9HTVUh7zYWO23RfOBI1r5BvQuV3fK/x8N8dZl3iWSjsBynIRduaUQaYlg zZPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=iSXbdihhVKWrbAaKAqZxAvJVEL5DtKk+7+BzX2sJ0es=; b=F68SPfNJHMhxBTBimej4w536uEyeIE4Eg1bGrvxWgKRfBqipIB0vjY+DRLTRcpIZwl JcXHvdyYgdNNGGu3RZJSxpTfTReqxRXphvnRI4AvWTj1SJ2ZTvHwDs8mOeNWLFf8CDtY JqFxgfpjtpuFMSTRhH17U2F1LE0b0/l3UMG3FdwOIm+mud8V6Cu1k+D+e8/mPr3LoyWl FkMPEGrmV4y6epLvG08tbkPEX796N4d0F+m+wZM1RKUwEdYPWEo5MLV5fQ6NlL0TlMyd CqT2hCuuojhAYyH/yqRrZvG1CuUzpAyGmZjt1RuDhviOtuwnzVyXUs7F3Xr3p3UemjCb 8aYQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u23si37835217pgb.66.2018.11.18.17.01.17; Sun, 18 Nov 2018 17:01:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728225AbeKSLW6 (ORCPT + 32 others); Mon, 19 Nov 2018 06:22:58 -0500 Received: from mx.socionext.com ([202.248.49.38]:40728 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727622AbeKSLW5 (ORCPT ); Mon, 19 Nov 2018 06:22:57 -0500 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 19 Nov 2018 10:00:59 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 7653E60062; Mon, 19 Nov 2018 10:00:59 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Mon, 19 Nov 2018 10:00:59 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id D6ABF40387; Mon, 19 Nov 2018 10:00:58 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id B3ABA120455; Mon, 19 Nov 2018 10:00:58 +0900 (JST) From: Sugaya Taichi To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Russell King , Jiri Slaby , Masami Hiramatsu , Jassi Brar , Sugaya Taichi Subject: [PATCH 12/14] ARM: dts: milbeaut: Add device tree set for the Milbeaut M10V board Date: Mon, 19 Nov 2018 10:02:14 +0900 Message-Id: <1542589336-13925-3-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1542589336-13925-1-git-send-email-sugaya.taichi@socionext.com> References: <1542589336-13925-1-git-send-email-sugaya.taichi@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add devicetree for Milbeaut M10V SoC and M10V Evaluation board. Signed-off-by: Sugaya Taichi --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/milbeaut-m10v-evb.dts | 35 +++ arch/arm/boot/dts/milbeaut-m10v-evb.dtsi | 17 ++ arch/arm/boot/dts/milbeaut-m10v.dtsi | 510 +++++++++++++++++++++++++++++++ 4 files changed, 563 insertions(+) create mode 100644 arch/arm/boot/dts/milbeaut-m10v-evb.dts create mode 100644 arch/arm/boot/dts/milbeaut-m10v-evb.dtsi create mode 100644 arch/arm/boot/dts/milbeaut-m10v.dtsi -- 1.9.1 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b0e966d..ee6220b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1207,6 +1207,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7623n-bananapi-bpi-r2.dtb \ mt8127-moose.dtb \ mt8135-evbp1.dtb +dtb-$(CONFIG_MACH_M10V_EVB) += milbeaut-m10v-evb.dtb dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-ast2500-evb.dtb \ diff --git a/arch/arm/boot/dts/milbeaut-m10v-evb.dts b/arch/arm/boot/dts/milbeaut-m10v-evb.dts new file mode 100644 index 0000000..af8d6e4 --- /dev/null +++ b/arch/arm/boot/dts/milbeaut-m10v-evb.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Socionext Milbeaut M10V Evaluation Board */ +/dts-v1/; +#include "milbeaut-m10v-evb.dtsi" + +/ { + cpus { + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf02>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf03>; + }; + + }; + trampoline: trampoline@0x0000F100 { + compatible = "socionext,smp-trampoline"; + reg = <0x0000F100 0x100>; + }; +}; diff --git a/arch/arm/boot/dts/milbeaut-m10v-evb.dtsi b/arch/arm/boot/dts/milbeaut-m10v-evb.dtsi new file mode 100644 index 0000000..fc35c0b --- /dev/null +++ b/arch/arm/boot/dts/milbeaut-m10v-evb.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "milbeaut-m10v.dtsi" + +/ { + model = "Socionext M10V EVB"; + compatible = "socionext,sc2000a", "socionext,milbeaut-m10v-evb"; + interrupt-parent = <&gic>; + chosen { + bootargs = "consoleblank=0 loglevel=8 init=/sbin/finit root=/dev/mmcblk0p2 rootwait ro console=ttyUSI0,115200n8 console=/dev/tty1 "; + linux,initrd-start = <0x4A000000>; + linux,initrd-end = <0x4BF00000>; + }; + memory { + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; +}; diff --git a/arch/arm/boot/dts/milbeaut-m10v.dtsi b/arch/arm/boot/dts/milbeaut-m10v.dtsi new file mode 100644 index 0000000..4745dc6 --- /dev/null +++ b/arch/arm/boot/dts/milbeaut-m10v.dtsi @@ -0,0 +1,510 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include +#include + +#include "skeleton.dtsi" + +/ { + compatible = "socionext,sc2000a"; + interrupt-parent = <&gic>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + }; + + + gic: interrupt-controller@1d000000 { + compatible = "arm,cortex-a7-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x1d001000 0x1000>, /* Distributer base and size */ + <0x1d002000 0x1000>; /* CPU I/f base and size */ + }; + + m10v-clk-tree@ { + compatible = "socionext,milbeaut-m10v-clk-regs"; + reg = <0x1d021000 0x4000>; + + clocks { + #address-cells = <0>; + #size-cells = <0>; + + uclk40xi: uclk40xi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + + aumclki: aumclki { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + + rtc32k: rtc32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + pxrefclk: pxrefclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pcisuppclk: pcisuppclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&uclk40xi>; + clock-div = <20>; + clock-mult = <1>; + }; + + usb2_clk: usb2_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&uclk40xi>; + clock-div = <2>; + clock-mult = <1>; + }; + + pll1: pll1 { + compatible = + "socionext,milbeaut-m10v-pll-fixed-factor"; + #clock-cells = <0>; + clocks = <&uclk40xi>; + offset = <1>; + clock-div = <1>; + clock-mult = <40>; + }; + + pll2: pll2 { + compatible = + "socionext,milbeaut-m10v-pll-fixed-factor"; + #clock-cells = <0>; + clocks = <&uclk40xi>; + offset = <2>; + clock-div = <1>; + clock-mult = <30>; + }; + + pll6: pll6 { /* CLK 6-1 */ + compatible = + "socionext,milbeaut-m10v-pll-fixed-factor"; + #clock-cells = <0>; + clocks = <&uclk40xi>; + offset = <7>; + clock-div = <1>; + clock-mult = <35>; + }; + + pll7: pll7 { /* CLK 7-1 */ + compatible = + "socionext,milbeaut-m10v-pll-fixed-factor"; + #clock-cells = <0>; + clocks = <&uclk40xi>; + offset = <8>; + clock-div = <1>; + clock-mult = <40>; + }; + + pll9: pll9 { /* CA7CLK, ATCLK */ + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&uclk40xi>; + clock-div = <1>; + clock-mult = <33>; + }; + + pll10: pll10 { + compatible = + "socionext,milbeaut-m10v-pll-fixed-factor"; + #clock-cells = <0>; + clocks = <&uclk40xi>; + offset = <10>; + clock-div = <5>; + clock-mult = <108>; + }; + + pll11: pll11 { /* CLK 11-1 */ + compatible = + "socionext,milbeaut-m10v-pll-fixed-factor"; + #clock-cells = <0>; + clocks = <&uclk40xi>; + offset = <12>; + clock-div = <2>; + clock-mult = <75>; + }; + + emmcclk: emmcclk { + compatible = "socionext,milbeaut-m10v-clk-div"; + #clock-cells = <0>; + clocks = <&pll11>; + offset = <28>; /* EMMCCLK */ + mask = <0x3>; + ratios = <15 0x7 10 0x6 9 0x5 8 0x4>; + }; + + pll1_div_1_2: pll1_div_1_2 { /* CLK 1-2 */ + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&pll1>; + clock-div = <2>; + clock-mult = <1>; + }; + + pll2_div_1_2: pll2_div_1_2 { /* CLK 2-2 */ + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&pll2>; + clock-div = <2>; + clock-mult = <1>; + }; + + pll6_div_1_2: pll6_div_1_2 { /* CLK 6-2 */ + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&pll6>; + clock-div = <2>; + clock-mult = <1>; + }; + + pll6_div_1_3: pll6_div_1_3 { /* CLK 6-3 */ + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&pll6>; + clock-div = <3>; + clock-mult = <1>; + }; + + pll7_div_1_2: pll7_div_1_2 { /* CLK 7-2 */ + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&pll7>; + clock-div = <2>; + clock-mult = <1>; + }; + + pll7_div_1_5: pll7_div_1_5 { /* CLK 7-5 */ + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&pll7>; + clock-div = <5>; + clock-mult = <1>; + }; + + pll10_div_1_2: pll10_div_1_2 { /* CLK 10-2 */ + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&pll10>; + clock-div = <2>; + clock-mult = <1>; + }; + + spiclk_mux_0: spiclk_mux_0 { + compatible = "socionext,milbeaut-m10v-clk-div"; + #clock-cells = <0>; + clocks = <&pll10_div_1_2>; + offset = <227>; /* SPICLK */ + mask = <0x3>; + ratios = <4 0x5 2 0x4>; + }; + + spiclk_mux_1: spiclk_mux_1 { + compatible = "socionext,milbeaut-m10v-clk-div"; + #clock-cells = <0>; + clocks = <&pll7_div_1_2>; + offset = <227>; /* SPICLK */ + mask = <0x3>; + ratios = <8 0x6>; + }; + + spiclk: spiclk { + compatible = "socionext,milbeaut-m10v-clk-mux"; + #clock-cells = <0>; + clocks = <&spiclk_mux_0>, <&spiclk_mux_1>; + }; + + ca7wdclk: ca7wdclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&pll2_div_1_2>; + clock-div = <12>; + clock-mult = <1>; + }; + + pll9_div_1_2: pll9_div_1_2 { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&pll9>; + clock-div = <2>; + clock-mult = <1>; + }; + + mclk400: mclk400 { + compatible = "socionext,milbeaut-m10v-clk-div"; + #clock-cells = <0>; + clocks = <&pll1_div_1_2>; + offset = <295>; /* MCLK400 */ + mask = <0x3>; + ratios = <4 0x7 2 0x5>; + }; + + mclk200: mclk200 { + compatible = "socionext,milbeaut-m10v-clk-div"; + #clock-cells = <0>; + clocks = <&pll1_div_1_2>; + offset = <291>; /* MCLK200 */ + mask = <0x7>; + ratios = <8 0xf 4 0xb>; + }; + + aclk400: aclk400 { + compatible = "socionext,milbeaut-m10v-clk-div"; + #clock-cells = <0>; + clocks = <&pll1_div_1_2>; + offset = <288>; /* ACLK400 */ + mask = <0x3>; + ratios = <4 0x7 2 0x5>; + }; + + aclk300: aclk300 { + compatible = "socionext,milbeaut-m10v-clk-div"; + #clock-cells = <0>; + clocks = <&pll2_div_1_2>; + offset = <352>; /* ACLK300 */ + mask = <0x1>; + ratios = <6 0x3 4 0x2>; + }; + + aclk: aclk { + compatible = "socionext,milbeaut-m10v-clk-div"; + #clock-cells = <0>; + clocks = <&pll1_div_1_2>; + offset = <276>; /* ACLK */ + mask = <0x7>; + ratios = <8 0xf 4 0xb>; + }; + + aclkexs: aclkexs { + compatible = "socionext,milbeaut-m10v-clk-div"; + #clock-cells = <0>; + clocks = <&pll1_div_1_2>; + offset = <272>; /* ACLKEXS */ + mask = <0x7>; + ratios = <8 0xf 6 0xd 5 0xc 4 0xb>; + }; + + hclk: hclk { + compatible = "socionext,milbeaut-m10v-clk-div"; + #clock-cells = <0>; + clocks = <&pll1_div_1_2>; + offset = <263>; /* HCLK */ + mask = <0xf>; + ratios = <16 0x1f 8 0x17>; + }; + + hclkbmh: hclkbmh { + compatible = "socionext,milbeaut-m10v-clk-div"; + #clock-cells = <0>; + clocks = <&pll1_div_1_2>; + offset = <268>; /* HCLKBMH */ + mask = <0x7>; + ratios = <8 0xf 4 0xb>; + }; + + pclk: pclk { + compatible = "socionext,milbeaut-m10v-clk-div"; + #clock-cells = <0>; + clocks = <&pll1_div_1_2>; + offset = <256>; /* PCLK */ + mask = <0x3f>; + ratios = <32 0x5f 16 0x4f>; + }; + + pclkca7wd: pclkca7wd { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&pll1_div_1_2>; + clock-div = <16>; + clock-mult = <1>; + }; + + rclk: rclk { + compatible = "socionext,milbeaut-m10v-clk-div"; + #clock-cells = <0>; + clocks = <&pll10_div_1_2>; + offset = <0>; /* RCLK */ + mask = <0x3>; + ratios = <64 0x7 48 0x6 32 0x5 16 0x4>; + }; + + uhs1clk0: uhs1clk0 { + compatible = "socionext,milbeaut-m10v-clk-div"; + #clock-cells = <0>; + clocks = <&pll7>; + offset = <3>; /* UHS1CLK0 */ + mask = <0xf>; + ratios = <16 0x14 8 0x13 4 0x12 3 0x11 2 0x10>; + }; + + uhs1clk1_div1: uhs1clk1_div1 { + compatible = "socionext,milbeaut-m10v-clk-div"; + #clock-cells = <0>; + clocks = <&pll7>; + offset = <8>; /* UHS1CLK1 */ + mask = <0xf>; + ratios = <16 0x14 8 0x13>; + }; + + uhs1clk1_div2: uhs1clk1_div2 { + compatible = "socionext,milbeaut-m10v-clk-div"; + #clock-cells = <0>; + clocks = <&pll6_div_1_2>; + offset = <8>; /* UHS1CLK1 */ + mask = <0xf>; + ratios = <1 0x18>; + }; + + uhs1clk1: uhs1clk1 { + compatible = "socionext,milbeaut-m10v-clk-mux"; + #clock-cells = <0>; + clocks = <&uhs1clk1_div1>, <&uhs1clk1_div2>; + }; + + uhs1clk2_div1: uhs1clk2_div1 { + compatible = "socionext,milbeaut-m10v-clk-div"; + #clock-cells = <0>; + clocks = <&pll7>; + offset = <13>; /* UHS1CLK2 */ + mask = <0xf>; + ratios = <16 0x14 8 0x13 4 0x12>; + }; + + uhs1clk2_div2: uhs1clk2_div2 { + compatible = "socionext,milbeaut-m10v-clk-div"; + #clock-cells = <0>; + clocks = <&pll6_div_1_2>; + offset = <13>; /* UHS1CLK2 */ + mask = <0xf>; + ratios = <1 0x18>; + }; + + uhs1clk2: uhs1clk2 { + compatible = "socionext,milbeaut-m10v-clk-mux"; + #clock-cells = <0>; + clocks = <&uhs1clk2_div1>, <&uhs1clk2_div2>; + }; + + uhs2clk: uhs2clk { + compatible = "socionext,milbeaut-m10v-clk-div"; + #clock-cells = <0>; + clocks = <&pll6_div_1_3>; + offset = <18>; /* UHS2CLK */ + mask = <0x7>; + ratios = <18 0xf 16 0xe 14 0xd 13 0xc + 12 0xb 11 0xa 10 0x9 9 0x8>; + }; + + nfclk_div1: nfclk_div1 { + compatible = "socionext,milbeaut-m10v-clk-div"; + #clock-cells = <0>; + clocks = <&pll7_div_1_2>; + offset = <22>; /* NFCLK */ + mask = <0x1f>; + ratios = <40 0x24 16 0x23 13 0x22 10 0x21 + 8 0x20>; + }; + + nfclk_div2: nfclk_div2 { + compatible = "socionext,milbeaut-m10v-clk-div"; + #clock-cells = <0>; + clocks = <&pll7_div_1_5>; + offset = <22>; /* NFCLK */ + mask = <0x1f>; + ratios = <10 0x28>; + }; + + nfclk: nfclk { + compatible = "socionext,milbeaut-m10v-clk-mux"; + #clock-cells = <0>; + clocks = <&nfclk_div1>, <&nfclk_div2>; + }; + + clk5: clk5 { + compatible = "socionext,milbeaut-m10v-clk-div"; + #clock-cells = <0>; + clocks = <&pll10_div_1_2>; + offset = <239>; /* NETAUSEL */ + mask = <0x3>; + ratios = <64 0x7 48 0x6 32 0x5 16 0x4>; + }; + }; + }; + + peri-timer@1e000000 { /* 32-bit Reload Timers */ + compatible = "socionext,milbeaut-m10v-timer"; + reg = <0x1e000050 0x10>, <0x1e000060 0x10>; + interrupts = <0 91 4>; + clocks = <&rclk>; + }; + + timer { /* The Generic Timer */ + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <40000000>;//40M + always-on; + arm,cpu-registers-not-fw-configured; + }; + + dummy_clk: dummy_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + pinctrl: pinctrl@1d022000 { + compatible = "socionext,milbeaut-m10v-pinctrl"; + reg = <0x1d022000 0x1000>, + <0x1c26f000 0x1000>; + reg-names = "pinctrl", "exiu"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&dummy_clk>; + interrupts = <0 54 4>, <0 55 4>, <0 56 4>, <0 57 4>, + <0 58 4>, <0 59 4>, <0 60 4>, <0 61 4>, + <0 62 4>, <0 63 4>, <0 64 4>, <0 65 4>, + <0 66 4>, <0 67 4>, <0 68 4>, <0 69 4>; + interrupt-names = "pin-48", "pin-49", "pin-50", "pin-51", + "pin-52", "pin-53", "pin-54", "pin-55", + "pin-56", "pin-57", "pin-58", "pin-59", + "pin-60", "pin-61", "pin-62", "pin-63"; + + usio1_pins: usio1_pins { + pins = "PE4", "PE5", "P87"; + function = "usio1"; + }; + }; + + usio1: usio_uart@1e700010 { /* PE4, PE5 */ + /* Enable this as ttyUSI0 */ + index = <0>; + compatible = "socionext,milbeaut-m10v-usio-uart"; + reg = <0x1e700010 0x10>; + interrupts = <0 141 0x4>, <0 149 0x4>; + interrupt-names = "rx", "tx"; + clocks = <&hclk>; + }; +}; From patchwork Mon Nov 19 01:02:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 151450 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2058100ljp; Sun, 18 Nov 2018 17:01:07 -0800 (PST) X-Google-Smtp-Source: AJdET5eIkPgFPn6jSrOt2g63HEMs7ptGUhp1QARX+QTGMkFQPXzziuG4QwB1z/vRgacvZP2mi6cJ X-Received: by 2002:a63:bc02:: with SMTP id q2mr18445866pge.116.1542589267207; Sun, 18 Nov 2018 17:01:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542589267; cv=none; d=google.com; s=arc-20160816; b=wtZC+y6P/tSaIOUjsw+I4TTwwQlZ//sONW3jL42HcuPwkXO52H7qJjKnEfRfFb363c HE8DTphedN62N3OJcInXXDgcnIb6963aP5MV6ekZuAJ6FWtC2yK/jdNVnVYA/H2K0FAM Z7f7sJUt3/sE0WcrVv393bfmT/7TZtdyuUr5V4632/uOf9O5OAxgFLbgRsA1T7Td7QA9 e1d1PvKHh0A3DtL+RiBrA34WnXy50uz8lRMWYMMGv3i3bzJXBPirVzaDXvGpc/Nwdm+G PB0ikUNEIMN34nDHEibw3jzigAS1s+5qXu8yorDTTD0QWuOyfxKt1iqQcGKoqQDYu+ND 4kOg== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id 131-v6si41220562pfx.213.2018.11.18.17.01.06; Sun, 18 Nov 2018 17:01:07 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728243AbeKSLW6 (ORCPT + 32 others); Mon, 19 Nov 2018 06:22:58 -0500 Received: from mx.socionext.com ([202.248.49.38]:40741 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728141AbeKSLW5 (ORCPT ); Mon, 19 Nov 2018 06:22:57 -0500 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 19 Nov 2018 10:01:01 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 07FA1180111; Mon, 19 Nov 2018 10:01:01 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Mon, 19 Nov 2018 10:01:00 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id 9DA0E40387; Mon, 19 Nov 2018 10:01:00 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 6B6EE120455; Mon, 19 Nov 2018 10:01:00 +0900 (JST) From: Sugaya Taichi To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Russell King , Jiri Slaby , Masami Hiramatsu , Jassi Brar , Sugaya Taichi Subject: [PATCH 13/14] ARM: configs: Add Milbeaut M10V defconfig Date: Mon, 19 Nov 2018 10:02:15 +0900 Message-Id: <1542589336-13925-4-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1542589336-13925-1-git-send-email-sugaya.taichi@socionext.com> References: <1542589336-13925-1-git-send-email-sugaya.taichi@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds the minimal defconfig for the Milbeaut M10V. Signed-off-by: Sugaya Taichi --- arch/arm/configs/milbeaut_m10v_defconfig | 364 +++++++++++++++++++++++++++++++ 1 file changed, 364 insertions(+) create mode 100644 arch/arm/configs/milbeaut_m10v_defconfig -- 1.9.1 diff --git a/arch/arm/configs/milbeaut_m10v_defconfig b/arch/arm/configs/milbeaut_m10v_defconfig new file mode 100644 index 0000000..90c22f8 --- /dev/null +++ b/arch/arm/configs/milbeaut_m10v_defconfig @@ -0,0 +1,364 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_DEFAULT_HOSTNAME="mlbel" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_FHANDLE=y +CONFIG_NO_HZ_FULL=y +CONFIG_NO_HZ_FULL_ALL=y +CONFIG_NO_HZ_FULL_SYSIDLE=y +CONFIG_NO_HZ_FULL_SYSIDLE_SMALL=4 +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +# CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=m +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_ARCH_MILBEAUT=y +CONFIG_ARCH_MILBEAUT_M10V=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_775420=y +# CONFIG_PCI is not set +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_HOST_GENERIC is not set +# CONFIG_PCIE_SN_DW_PLAT is not set +# CONFIG_PCI_MSI is not set +# CONFIG_PCIEPORTBUS is not set +# CONFIG_PCIEAER is not set +# CONFIG_PCIEASPM is not set +CONFIG_SMP=y +# CONFIG_ARM_CPU_TOPOLOGY is not set +CONFIG_HAVE_ARM_ARCH_TIMER=y +CONFIG_VMSPLIT_2G=y +CONFIG_PREEMPT=y +CONFIG_THUMB2_KERNEL=y +CONFIG_HIGHMEM=y +# CONFIG_COMPACTION is not set +CONFIG_CMA=y +# CONFIG_ATAGS is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_KEXEC=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_KERNEL_MODE_NEON=y +CONFIG_PM_RUNTIME=y +CONFIG_PM_DEBUG=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=m +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +CONFIG_INET_IPCOMP=y +CONFIG_INET_XFRM_MODE_TRANSPORT=m +CONFIG_INET_XFRM_MODE_TUNNEL=m +CONFIG_INET_XFRM_MODE_BEET=m +CONFIG_INET_UDP_DIAG=m +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_IP_SCTP=m +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_TIPC=y +CONFIG_L2TP=m +CONFIG_L2TP_DEBUGFS=m +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=y +CONFIG_L2TP_ETH=y +CONFIG_IPX=m +CONFIG_NETLINK_MMAP=y +CONFIG_NETLINK_DIAG=y +CONFIG_CFG80211=y +CONFIG_NL80211_TESTMODE=y +CONFIG_CFG80211_DEVELOPER_WARNINGS=y +CONFIG_CFG80211_REG_DEBUG=y +CONFIG_CFG80211_INTERNAL_REGDB=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=y +# CONFIG_MAC80211_RC_MINSTREL is not set +CONFIG_MAC80211_LEDS=y +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_REGULATOR=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=16 +CONFIG_MTD=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_CDN_HPNFC=y +CONFIG_MTD_NAND_CDN_HPNFC_DT=y +CONFIG_MTD_NAND_PLATFORM=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=3 +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=2 +CONFIG_BLK_DEV_RAM=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_NETDEVICES=y +CONFIG_MACVLAN=y +CONFIG_TUN=y +CONFIG_VETH=y +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +CONFIG_R8169=y +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_SOCIONEXT_OGMA=y +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_REALTEK_PHY=y +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_SERIO_LIBPS2=y +CONFIG_LEGACY_PTY_COUNT=4 +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_DMA is not set +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_M10V_USIO=y +CONFIG_SERIAL_M10V_USIO_CONSOLE=y +# CONFIG_HW_RANDOM is not set +# CONFIG_I2C is not set +# CONFIG_I2C_BOARDINFO is not set +# CONFIG_I2C_COMPAT is not set +# CONFIG_I2C_CHARDEV is not set +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_SNI_M10V is not set +CONFIG_SPI=y +# CONFIG_SPI_SN_USIO=y +#CONFIG_SPI_SNI is not set +#CONFIG_SPI_SPIDEV is not set +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCA953X_IRQ=y +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_SOFT_WATCHDOG=m +CONFIG_REGULATOR=y +CONFIG_REGULATOR_DEBUG=y +CONFIG_REGULATOR_S6AP412=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_VIDEO_ADV_DEBUG=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=y +# CONFIG_USB_GSPCA is not set +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_SOC_CAMERA=y +CONFIG_SOC_CAMERA_PLATFORM=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_V4L_TEST_DRIVERS=y +CONFIG_VIDEO_VIVID=m +CONFIG_VIDEO_VIVID_MAX_DEVS=64 +CONFIG_FB=y +# CONFIG_VGA_ARB is not set +# CONFIG_USB is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_XHCI_HCD is not set +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_OHCI_HCD_PCI is not set +# CONFIG_USB_OHCI_HCD_PLATFORM is not set +# CONFIG_USB_STORAGE is not set +# CONFIG_USB_SERIAL is not set +# CONFIG_USB_SERIAL_GENERIC is not set +# CONFIG_USB_SERIAL_CP210X is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_ULPI is not set +# CONFIG_USB_GADGET is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_DWC3_PCI is not set +# CONFIG_USB_DWC3_OTG is not set +# CONFIG_USB_DWC3_SN is not set +# CONFIG_USB_DWC3_OF_SIMPLE is not set +# CONFIG_USB_GADGET_SN_LAP is not set +# CONFIG_USB_CONFIGFS is not set +# CONFIG_USB_CONFIGFS_ACM is not set +# CONFIG_USB_CONFIGFS_MASS_STORAGE is not set +# CONFIG_USB_CONFIGFS_F_MTP is not set +# CONFIG_USB_CONFIGFS_F_UVC is not set +# CONFIG_USB_CONFIGFS_UEVENT is not set +# CONFIG_MMC is not set +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SDHCI_PLTFM is not set +# CONFIG_MMC_SDHCI_F_SDH30 is not set +# CONFIG_MMC_SDHCI_F_EMMC50 is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_HCTOSYS is not set +# CONFIG_RTC_SYSTOHC is not set +CONFIG_RTC_DEBUG=y +CONFIG_RTC_DRV_RX8025=y +CONFIG_DMADEVICES=y +CONFIG_MB86S7X_HDMAC=y +CONFIG_MB8AC0300_XDMAC=y +CONFIG_UIO=y +CONFIG_UIO_SNI=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_PWM=y +# CONFIG_PWM_SYSFS is not set +CONFIG_PWM_M10V=y +CONFIG_RESET_CONTROLLER=y +CONFIG_EXFAT=y +CONFIG_EXT4_FS=y +# CONFIG_EXT4_USE_FOR_EXT23 is not set +# CONFIG_XFS_FS is not set +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_QUOTA=y +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set +CONFIG_FSCACHE=y +CONFIG_FSCACHE_STATS=y +CONFIG_FSCACHE_HISTOGRAM=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=932 +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_ROMFS_FS=y +CONFIG_ROMFS_BACKED_BY_BOTH=y +CONFIG_NFS_FS=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=y +CONFIG_NLS_CODEPAGE_775=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_CODEPAGE_852=y +CONFIG_NLS_CODEPAGE_855=y +CONFIG_NLS_CODEPAGE_857=y +CONFIG_NLS_CODEPAGE_860=y +CONFIG_NLS_CODEPAGE_861=y +CONFIG_NLS_CODEPAGE_862=y +CONFIG_NLS_CODEPAGE_863=y +CONFIG_NLS_CODEPAGE_864=y +CONFIG_NLS_CODEPAGE_865=y +CONFIG_NLS_CODEPAGE_866=y +CONFIG_NLS_CODEPAGE_869=y +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_CODEPAGE_950=y +CONFIG_NLS_CODEPAGE_932=y +CONFIG_NLS_CODEPAGE_949=y +CONFIG_NLS_CODEPAGE_874=y +CONFIG_NLS_ISO8859_8=y +CONFIG_NLS_CODEPAGE_1250=y +CONFIG_NLS_CODEPAGE_1251=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_ISO8859_3=y +CONFIG_NLS_ISO8859_4=y +CONFIG_NLS_ISO8859_5=y +CONFIG_NLS_ISO8859_6=y +CONFIG_NLS_ISO8859_7=y +CONFIG_NLS_ISO8859_9=y +CONFIG_NLS_ISO8859_13=y +CONFIG_NLS_ISO8859_14=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_KOI8_R=y +CONFIG_NLS_KOI8_U=y +CONFIG_NLS_MAC_ROMAN=y +CONFIG_NLS_MAC_CELTIC=y +CONFIG_NLS_MAC_CENTEURO=y +CONFIG_NLS_MAC_CROATIAN=y +CONFIG_NLS_MAC_CYRILLIC=y +CONFIG_NLS_MAC_GAELIC=y +CONFIG_NLS_MAC_GREEK=y +CONFIG_NLS_MAC_ICELAND=y +CONFIG_NLS_MAC_INUIT=y +CONFIG_NLS_MAC_ROMANIAN=y +CONFIG_NLS_MAC_TURKISH=y +CONFIG_NLS_UTF8=y +CONFIG_IPCU_FS=y +# CONFIG_TEST_IPCU_FS is not set +CONFIG_PRINTK_TIME=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DEBUG_INFO=y +#CONFIG_DEBUG_INFO_REDUCED is not set +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_GIC_BL=y +CONFIG_HEADERS_CHECK=y +CONFIG_DEBUG_SECTION_MISMATCH=y +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_RCU_TORTURE_TEST=m +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_KGDB=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_LL_MILBEAUT_UART=y +CONFIG_EARLY_PRINTK=y +# CONFIG_EARLY_PRINTK_DIRECT is not set +CONFIG_KEYS=y +CONFIG_ENCRYPTED_KEYS=y +CONFIG_SECURITY=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +CONFIG_FONTS=y From patchwork Mon Nov 19 01:02:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 151451 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2058135ljp; Sun, 18 Nov 2018 17:01:08 -0800 (PST) X-Google-Smtp-Source: AJdET5elEdHqsYxjrfgzORtGbBm/7q/RrVG2CyZ6WXfOUde5Ex/J6WHashbpWDF3txt3rD+j6j7h X-Received: by 2002:a65:63d3:: with SMTP id n19mr18510005pgv.179.1542589268372; Sun, 18 Nov 2018 17:01:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542589268; cv=none; d=google.com; s=arc-20160816; b=EPv0wmWnyzlL0Xg1VrlqGN43oKQD69QaX6gB76Dc4LzTcpGQAu5YjDzGgd3fl9+rni FmxaXg6GYVibcSN9j0qSnUtO6yLYQ3xvaL8to5vaOy0PCwrw5nB66Ef2dUYlh+LUNrHr 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[209.132.180.67]) by mx.google.com with ESMTP id 131-v6si41220562pfx.213.2018.11.18.17.01.08; Sun, 18 Nov 2018 17:01:08 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728259AbeKSLW7 (ORCPT + 32 others); Mon, 19 Nov 2018 06:22:59 -0500 Received: from mx.socionext.com ([202.248.49.38]:40749 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728200AbeKSLW7 (ORCPT ); Mon, 19 Nov 2018 06:22:59 -0500 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 19 Nov 2018 10:01:03 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 8C25360062; Mon, 19 Nov 2018 10:01:03 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Mon, 19 Nov 2018 10:01:03 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id EBE1940387; Mon, 19 Nov 2018 10:01:02 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id CB13C120455; Mon, 19 Nov 2018 10:01:02 +0900 (JST) From: Sugaya Taichi To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Russell King , Jiri Slaby , Masami Hiramatsu , Jassi Brar , Sugaya Taichi Subject: [PATCH 14/14] MAINTAINERS: Add entry to MAINTAINERS for Milbeaut Date: Mon, 19 Nov 2018 10:02:16 +0900 Message-Id: <1542589336-13925-5-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1542589336-13925-1-git-send-email-sugaya.taichi@socionext.com> References: <1542589336-13925-1-git-send-email-sugaya.taichi@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add entry to MAINTAINERS for Milbeaut that supported minimal drivers. Signed-off-by: Sugaya Taichi --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) -- 1.9.1 diff --git a/MAINTAINERS b/MAINTAINERS index 0abecc5..31dd29f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1782,6 +1782,15 @@ F: drivers/watchdog/sama5d4_wdt.c X: drivers/input/touchscreen/atmel_mxt_ts.c X: drivers/net/wireless/atmel/ +ARM/MILBEAUT ARCHITECTURE +M: Taichi Sugaya +M: Takao Orito +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: arch/arm/boot/dts/milbeaut* +F: arch/arm/mach-milbeaut/ +N: milbeaut + ARM/MIOA701 MACHINE SUPPORT M: Robert Jarzmik L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)