From patchwork Tue Jan 18 00:44:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 532935 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00D4AC433F5 for ; Tue, 18 Jan 2022 01:01:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238678AbiARBBz (ORCPT ); Mon, 17 Jan 2022 20:01:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229836AbiARBBy (ORCPT ); Mon, 17 Jan 2022 20:01:54 -0500 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77987C06161C; Mon, 17 Jan 2022 17:01:54 -0800 (PST) Received: by mail-ed1-x52c.google.com with SMTP id j7so24188150edr.4; Mon, 17 Jan 2022 17:01:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=M1ATHqKukkS8wdcox6Oca6+wxzUoLyKhXdX3OudoHRM=; b=fFMoHeEPVOAEEVkE3CTtbtVkXhTTwrQeaKaYiBYD1+WStpoySc37Ht398xyrmfRLbN qLWTrLlnycDSayXUrxIgQ0roZpimVQtscWRWCkxEzPPD8u/k1oX1agrUL1KLD6TCWgzS RrQJ8pNUjmKoB9zBYIfHGw6PH86VF0R53MSJgiMB0H4KJBpgOryxZOT1nGAVzngWJ4kb srvzXnHQ8frt4xcXAMScrmlxUTqhHe8xvjSHwyz8IQzsPWl9b7+96sGZU3qMF8mj9Ev5 FG0La58RXiMaC2kzwMV03qok5Jh01n3s6mz4WAWhfzvJHeTMFmnQKakFW1vltp8hdG9Q kYog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M1ATHqKukkS8wdcox6Oca6+wxzUoLyKhXdX3OudoHRM=; b=FKSaz7mR9dXWRmp6eFgfxq0LoD3hBJN/NEJJwJO9SdPd4X/THxy900pRhEoHXOcVgY Gh6O6uYhIkhfSp/ex4YbLJKY1FxuFDcqGF+LG5/2Ob5OTpE3aRN6HrvHr1pxad7vRwq+ cpOdnSzqXiAEX6sU75bCaoaFKH6RszdkHen377AoKHDJZ9PUifp9jFBNSS7KMW80OQER Hkpb53N3ZeYXlMt9VftaW53MPJQXhisDJJe3iPR5H8J/kjXqPYBMbZsO9rjTmdjsPE+F vpnJWFbf4Vo69bjo5cjhY3ez+CXPLjDkqXoS6GyB3M4n7aMW6BgBfY/77zUuGutD0Idw ycjg== X-Gm-Message-State: AOAM5327kfM3YaAJ7ie+gMZU8PinwiSDScTMa/Z+iHCt6KG9bNS4JASt xCT9zQcVC/Sk2S7pX3yd4Ko= X-Google-Smtp-Source: ABdhPJxSJEsUeQTLwmAjMZUiRgjC3kNpj/Ok6kOddHIsMYUjHadf3yzQ/lLZBwOVNleYZFiFG8mlzg== X-Received: by 2002:a17:906:7044:: with SMTP id r4mr18735298ejj.351.1642467712903; Mon, 17 Jan 2022 17:01:52 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id 24sm4892127ejg.47.2022.01.17.17.01.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jan 2022 17:01:52 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/14] dt-bindings: clock: Document qcom,gcc-ipq8064 binding Date: Tue, 18 Jan 2022 01:44:21 +0100 Message-Id: <20220118004434.17095-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220118004434.17095-1-ansuelsmth@gmail.com> References: <20220118004434.17095-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document qcom,gcc-ipq8064 binding needed to declare pxo and cxo source clocks. The gcc node is also used by the tsens driver, already Documented, to get the calib nvmem cells and the base reg from gcc. Signed-off-by: Ansuel Smith --- .../bindings/clock/qcom,gcc-ipq8064.yaml | 67 +++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml new file mode 100644 index 000000000000..2dc254fdf161 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for IPQ8064 + +maintainers: + - Ansuel Smith + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on IPQ8064. + +properties: + compatible: + const: qcom,gcc-ipq8064 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + clocks: + items: + - description: PXO source + - description: CX0 source + + clock-names: + items: + - const: pxo + - const: cxo + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + - clocks + - clock-names + +additionalProperties: true + +examples: + - | + gcc: clock-controller@900000 { + compatible = "qcom,gcc-ipq8064", "syscon"; + reg = <0x00900000 0x4000>; + clocks = <&pxo_board>, <&cxo_board>; + clock-names = "pxo", "cxo"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + /* Tsens node definition */ + + }; +... From patchwork Tue Jan 18 00:44:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 532934 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A6C2C433F5 for ; Tue, 18 Jan 2022 01:02:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243885AbiARBCA (ORCPT ); Mon, 17 Jan 2022 20:02:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39062 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238683AbiARBBz (ORCPT ); Mon, 17 Jan 2022 20:01:55 -0500 Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68E36C061574; Mon, 17 Jan 2022 17:01:55 -0800 (PST) Received: by mail-ed1-x531.google.com with SMTP id q25so72652355edb.2; Mon, 17 Jan 2022 17:01:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=wlPGztyCglYvRuLUlqRz5tHJBkS2fLA0AOcHKOEzeZA=; b=Tg5/HL6RuF0u+pFSo8jDHr92zFaEckK5slFfbo/rjYssifQc4WCkWQAI74QeC3kyCJ tz7d2QiqQUYgJvP59Xn8s1+xp5N/iLyXZqLpqa5F//IwwElr5g3zunEK7VJio9kFc+aE q2s6HVdx0U8ouT7L/m8gWS36vQGMMPgIK7W7hVLCzJdZiFYoG3xHkI/sEajqtGUmxBUC 4USoyH6455GDleXLcnDRUyX+wBU/usE2sXynmAXmdBL3H2s/dXE4c77/QuBW7jdVeqCw OEwOIzvGgul71yQj7YH6JhM/DWnSLgzijr9kRBIYTCP/KRtmt14rRmCmCcPJVZHnfp71 Q+ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wlPGztyCglYvRuLUlqRz5tHJBkS2fLA0AOcHKOEzeZA=; b=GpbAaKOQdkw4sAQ0TF6RGZczeneIYbFgPGBaG9JBk99Ws/Wox3OeMFcJwYvYveXy61 yrr0EtdrAlYj5zuU7fuyHuNBgzAdQMtyuR3X2MhpEYZh2ym1Z84Ie2v+m0BFSgZS01tg WQ+riAVNA3XO34U+VdTx+TZYen4cx1LocbCc5JuU1e6NfSgHV/6dJ4sR6tCbVfzYwVu5 dhFuE4Pbk0HadluUTEZKDj/+hGY7YyYhEvT3UCT1LzQA9SkNICZ5VN4tC+M9nYhKPc0n OE9XMn7P+X2kLX4Klq2Qb4T0e1fard2NemDvgrn0huZR2hxf9RBMrPWIL2hCz0MgCe3U CxKg== X-Gm-Message-State: AOAM533F9BVLsZ9qMMCF8rzTfmpd5zxi0p0GLEsgGzZ2WisH84cutL0m B9dNvsYMmDYAG9ZsuOgAOVNM/EKVG0w= X-Google-Smtp-Source: ABdhPJwhHv1mJNexDLPa1Tz9S1m32K+gy7UG3OJlmciHbMZcUHiclw9c49rRU7mHOqe42QUcFJgrgg== X-Received: by 2002:a17:907:2da3:: with SMTP id gt35mr18833052ejc.493.1642467713880; Mon, 17 Jan 2022 17:01:53 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id 24sm4892127ejg.47.2022.01.17.17.01.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jan 2022 17:01:53 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/14] drivers: clk: qcom: gcc-ipq806x: fix wrong naming for gcc_pxo_pll8_pll0 Date: Tue, 18 Jan 2022 01:44:22 +0100 Message-Id: <20220118004434.17095-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220118004434.17095-1-ansuelsmth@gmail.com> References: <20220118004434.17095-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Parent gcc_pxo_pll8_pll0 had the parent definition and parent map swapped. Fix this naming error. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index d6b7adb4be38..34cddf461dba 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -291,13 +291,13 @@ static const char * const gcc_pxo_pll3[] = { "pll3", }; -static const struct parent_map gcc_pxo_pll8_pll0[] = { +static const struct parent_map gcc_pxo_pll8_pll0_map[] = { { P_PXO, 0 }, { P_PLL8, 3 }, { P_PLL0, 2 } }; -static const char * const gcc_pxo_pll8_pll0_map[] = { +static const char * const gcc_pxo_pll8_pll0[] = { "pxo", "pll8_vote", "pll0_vote", @@ -1993,7 +1993,7 @@ static struct clk_rcg usb30_master_clk_src = { }, .s = { .src_sel_shift = 0, - .parent_map = gcc_pxo_pll8_pll0, + .parent_map = gcc_pxo_pll8_pll0_map, }, .freq_tbl = clk_tbl_usb30_master, .clkr = { @@ -2001,7 +2001,7 @@ static struct clk_rcg usb30_master_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb30_master_ref_src", - .parent_names = gcc_pxo_pll8_pll0_map, + .parent_names = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2063,7 +2063,7 @@ static struct clk_rcg usb30_utmi_clk = { }, .s = { .src_sel_shift = 0, - .parent_map = gcc_pxo_pll8_pll0, + .parent_map = gcc_pxo_pll8_pll0_map, }, .freq_tbl = clk_tbl_usb30_utmi, .clkr = { @@ -2071,7 +2071,7 @@ static struct clk_rcg usb30_utmi_clk = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb30_utmi_clk", - .parent_names = gcc_pxo_pll8_pll0_map, + .parent_names = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2133,7 +2133,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { }, .s = { .src_sel_shift = 0, - .parent_map = gcc_pxo_pll8_pll0, + .parent_map = gcc_pxo_pll8_pll0_map, }, .freq_tbl = clk_tbl_usb, .clkr = { @@ -2141,7 +2141,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_src", - .parent_names = gcc_pxo_pll8_pll0_map, + .parent_names = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2197,7 +2197,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { }, .s = { .src_sel_shift = 0, - .parent_map = gcc_pxo_pll8_pll0, + .parent_map = gcc_pxo_pll8_pll0_map, }, .freq_tbl = clk_tbl_usb, .clkr = { @@ -2205,7 +2205,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_fs1_xcvr_src", - .parent_names = gcc_pxo_pll8_pll0_map, + .parent_names = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, From patchwork Tue Jan 18 00:44:23 2022 Content-Type: text/plain; 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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id 24sm4892127ejg.47.2022.01.17.17.01.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jan 2022 17:01:54 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/14] drivers: clk: qcom: gcc-ipq806x: convert parent_names to parent_data Date: Tue, 18 Jan 2022 01:44:23 +0100 Message-Id: <20220118004434.17095-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220118004434.17095-1-ansuelsmth@gmail.com> References: <20220118004434.17095-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert parent_names to parent_data to modernize the driver. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 300 ++++++++++++++++++++------------- 1 file changed, 187 insertions(+), 113 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 34cddf461dba..cbacd56f52d4 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -35,7 +35,9 @@ static struct clk_pll pll0 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll0", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pxo", + }, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -46,7 +48,9 @@ static struct clk_regmap pll0_vote = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "pll0_vote", - .parent_names = (const char *[]){ "pll0" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &pll0.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -62,7 +66,9 @@ static struct clk_pll pll3 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll3", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pxo", + }, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -89,7 +95,9 @@ static struct clk_pll pll8 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll8", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pxo", + }, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -100,7 +108,9 @@ static struct clk_regmap pll8_vote = { .enable_mask = BIT(8), .hw.init = &(struct clk_init_data){ .name = "pll8_vote", - .parent_names = (const char *[]){ "pll8" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &pll8.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -123,7 +133,9 @@ static struct hfpll_data hfpll0_data = { static struct clk_hfpll hfpll0 = { .d = &hfpll0_data, .clkr.hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "pxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pxo", + }, .num_parents = 1, .name = "hfpll0", .ops = &clk_ops_hfpll, @@ -149,7 +161,9 @@ static struct hfpll_data hfpll1_data = { static struct clk_hfpll hfpll1 = { .d = &hfpll1_data, .clkr.hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "pxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pxo", + }, .num_parents = 1, .name = "hfpll1", .ops = &clk_ops_hfpll, @@ -175,7 +189,9 @@ static struct hfpll_data hfpll_l2_data = { static struct clk_hfpll hfpll_l2 = { .d = &hfpll_l2_data, .clkr.hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "pxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pxo", + }, .num_parents = 1, .name = "hfpll_l2", .ops = &clk_ops_hfpll, @@ -194,7 +210,9 @@ static struct clk_pll pll14 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll14", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pxo", + }, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -205,7 +223,9 @@ static struct clk_regmap pll14_vote = { .enable_mask = BIT(14), .hw.init = &(struct clk_init_data){ .name = "pll14_vote", - .parent_names = (const char *[]){ "pll14" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &pll14.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -238,7 +258,9 @@ static struct clk_pll pll18 = { .freq_tbl = pll18_freq_tbl, .clkr.hw.init = &(struct clk_init_data){ .name = "pll18", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pxo", + }, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -259,9 +281,9 @@ static const struct parent_map gcc_pxo_pll8_map[] = { { P_PLL8, 3 } }; -static const char * const gcc_pxo_pll8[] = { - "pxo", - "pll8_vote", +static const struct clk_parent_data gcc_pxo_pll8[] = { + { .fw_name = "pxo" }, + { .hw = &pll8_vote.hw }, }; static const struct parent_map gcc_pxo_pll8_cxo_map[] = { @@ -270,10 +292,10 @@ static const struct parent_map gcc_pxo_pll8_cxo_map[] = { { P_CXO, 5 } }; -static const char * const gcc_pxo_pll8_cxo[] = { - "pxo", - "pll8_vote", - "cxo", +static const struct clk_parent_data gcc_pxo_pll8_cxo[] = { + { .fw_name = "pxo" }, + { .hw = &pll8_vote.hw }, + { .fw_name = "cxo" }, }; static const struct parent_map gcc_pxo_pll3_map[] = { @@ -286,9 +308,9 @@ static const struct parent_map gcc_pxo_pll3_sata_map[] = { { P_PLL3, 6 } }; -static const char * const gcc_pxo_pll3[] = { - "pxo", - "pll3", +static const struct clk_parent_data gcc_pxo_pll3[] = { + { .fw_name = "pxo" }, + { .hw = &pll3.clkr.hw }, }; static const struct parent_map gcc_pxo_pll8_pll0_map[] = { @@ -297,10 +319,10 @@ static const struct parent_map gcc_pxo_pll8_pll0_map[] = { { P_PLL0, 2 } }; -static const char * const gcc_pxo_pll8_pll0[] = { - "pxo", - "pll8_vote", - "pll0_vote", +static const struct clk_parent_data gcc_pxo_pll8_pll0[] = { + { .fw_name = "pxo" }, + { .hw = &pll8_vote.hw }, + { .hw = &pll0_vote.hw }, }; static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = { @@ -311,12 +333,12 @@ static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = { { P_PLL18, 1 } }; -static const char * const gcc_pxo_pll8_pll14_pll18_pll0[] = { - "pxo", - "pll8_vote", - "pll0_vote", - "pll14", - "pll18", +static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = { + { .fw_name = "pxo" }, + { .hw = &pll8_vote.hw }, + { .hw = &pll0_vote.hw }, + { .hw = &pll14.clkr.hw }, + { .hw = &pll18.clkr.hw }, }; static struct freq_tbl clk_tbl_gsbi_uart[] = { @@ -362,7 +384,7 @@ static struct clk_rcg gsbi1_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -378,8 +400,8 @@ static struct clk_branch gsbi1_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_clk", - .parent_names = (const char *[]){ - "gsbi1_uart_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gsbi1_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -413,7 +435,7 @@ static struct clk_rcg gsbi2_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -429,8 +451,8 @@ static struct clk_branch gsbi2_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_clk", - .parent_names = (const char *[]){ - "gsbi2_uart_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gsbi2_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -464,7 +486,7 @@ static struct clk_rcg gsbi4_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -480,8 +502,8 @@ static struct clk_branch gsbi4_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_clk", - .parent_names = (const char *[]){ - "gsbi4_uart_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gsbi4_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -515,7 +537,7 @@ static struct clk_rcg gsbi5_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -531,8 +553,8 @@ static struct clk_branch gsbi5_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_clk", - .parent_names = (const char *[]){ - "gsbi5_uart_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gsbi5_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -566,7 +588,7 @@ static struct clk_rcg gsbi6_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi6_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -582,8 +604,8 @@ static struct clk_branch gsbi6_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi6_uart_clk", - .parent_names = (const char *[]){ - "gsbi6_uart_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gsbi6_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -617,7 +639,7 @@ static struct clk_rcg gsbi7_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi7_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -633,8 +655,8 @@ static struct clk_branch gsbi7_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi7_uart_clk", - .parent_names = (const char *[]){ - "gsbi7_uart_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gsbi7_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -681,7 +703,7 @@ static struct clk_rcg gsbi1_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -697,7 +719,9 @@ static struct clk_branch gsbi1_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_clk", - .parent_names = (const char *[]){ "gsbi1_qup_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &gsbi1_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -730,7 +754,7 @@ static struct clk_rcg gsbi2_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -746,7 +770,9 @@ static struct clk_branch gsbi2_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_clk", - .parent_names = (const char *[]){ "gsbi2_qup_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &gsbi2_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -779,7 +805,7 @@ static struct clk_rcg gsbi4_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -795,7 +821,9 @@ static struct clk_branch gsbi4_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_clk", - .parent_names = (const char *[]){ "gsbi4_qup_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &gsbi4_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -828,7 +856,7 @@ static struct clk_rcg gsbi5_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -844,7 +872,9 @@ static struct clk_branch gsbi5_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_clk", - .parent_names = (const char *[]){ "gsbi5_qup_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &gsbi5_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -877,7 +907,7 @@ static struct clk_rcg gsbi6_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi6_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -893,7 +923,9 @@ static struct clk_branch gsbi6_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi6_qup_clk", - .parent_names = (const char *[]){ "gsbi6_qup_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &gsbi6_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -926,7 +958,7 @@ static struct clk_rcg gsbi7_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi7_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -942,7 +974,9 @@ static struct clk_branch gsbi7_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi7_qup_clk", - .parent_names = (const char *[]){ "gsbi7_qup_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &gsbi7_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1076,7 +1110,7 @@ static struct clk_rcg gp0_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gp0_src", - .parent_names = gcc_pxo_pll8_cxo, + .parent_data = gcc_pxo_pll8_cxo, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -1092,7 +1126,9 @@ static struct clk_branch gp0_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp0_clk", - .parent_names = (const char *[]){ "gp0_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &gp0_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1125,7 +1161,7 @@ static struct clk_rcg gp1_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gp1_src", - .parent_names = gcc_pxo_pll8_cxo, + .parent_data = gcc_pxo_pll8_cxo, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1141,7 +1177,9 @@ static struct clk_branch gp1_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp1_clk", - .parent_names = (const char *[]){ "gp1_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &gp1_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1174,7 +1212,7 @@ static struct clk_rcg gp2_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gp2_src", - .parent_names = gcc_pxo_pll8_cxo, + .parent_data = gcc_pxo_pll8_cxo, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1190,7 +1228,9 @@ static struct clk_branch gp2_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp2_clk", - .parent_names = (const char *[]){ "gp2_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &gp2_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1228,7 +1268,7 @@ static struct clk_rcg prng_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "prng_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, }, @@ -1244,7 +1284,9 @@ static struct clk_branch prng_clk = { .enable_mask = BIT(10), .hw.init = &(struct clk_init_data){ .name = "prng_clk", - .parent_names = (const char *[]){ "prng_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &prng_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, }, @@ -1290,7 +1332,7 @@ static struct clk_rcg sdc1_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "sdc1_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, }, @@ -1305,7 +1347,9 @@ static struct clk_branch sdc1_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "sdc1_clk", - .parent_names = (const char *[]){ "sdc1_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &sdc1_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1338,7 +1382,7 @@ static struct clk_rcg sdc3_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "sdc3_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, }, @@ -1353,7 +1397,9 @@ static struct clk_branch sdc3_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "sdc3_clk", - .parent_names = (const char *[]){ "sdc3_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &sdc3_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1421,7 +1467,7 @@ static struct clk_rcg tsif_ref_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "tsif_ref_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, }, @@ -1436,7 +1482,9 @@ static struct clk_branch tsif_ref_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "tsif_ref_clk", - .parent_names = (const char *[]){ "tsif_ref_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &tsif_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1583,7 +1631,7 @@ static struct clk_rcg pcie_ref_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "pcie_ref_src", - .parent_names = gcc_pxo_pll3, + .parent_data = gcc_pxo_pll3, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1599,7 +1647,9 @@ static struct clk_branch pcie_ref_src_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "pcie_ref_src_clk", - .parent_names = (const char *[]){ "pcie_ref_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &pcie_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1675,7 +1725,7 @@ static struct clk_rcg pcie1_ref_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "pcie1_ref_src", - .parent_names = gcc_pxo_pll3, + .parent_data = gcc_pxo_pll3, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1691,7 +1741,9 @@ static struct clk_branch pcie1_ref_src_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "pcie1_ref_src_clk", - .parent_names = (const char *[]){ "pcie1_ref_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &pcie1_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1767,7 +1819,7 @@ static struct clk_rcg pcie2_ref_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "pcie2_ref_src", - .parent_names = gcc_pxo_pll3, + .parent_data = gcc_pxo_pll3, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1783,7 +1835,9 @@ static struct clk_branch pcie2_ref_src_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "pcie2_ref_src_clk", - .parent_names = (const char *[]){ "pcie2_ref_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &pcie2_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1864,7 +1918,7 @@ static struct clk_rcg sata_ref_src = { .enable_mask = BIT(7), .hw.init = &(struct clk_init_data){ .name = "sata_ref_src", - .parent_names = gcc_pxo_pll3, + .parent_data = gcc_pxo_pll3, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1880,7 +1934,9 @@ static struct clk_branch sata_rxoob_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "sata_rxoob_clk", - .parent_names = (const char *[]){ "sata_ref_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &sata_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1896,7 +1952,9 @@ static struct clk_branch sata_pmalive_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "sata_pmalive_clk", - .parent_names = (const char *[]){ "sata_ref_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &sata_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1912,7 +1970,9 @@ static struct clk_branch sata_phy_ref_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "sata_phy_ref_clk", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pxo", + }, .num_parents = 1, .ops = &clk_branch_ops, }, @@ -2001,7 +2061,7 @@ static struct clk_rcg usb30_master_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb30_master_ref_src", - .parent_names = gcc_pxo_pll8_pll0, + .parent_data = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2017,7 +2077,9 @@ static struct clk_branch usb30_0_branch_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb30_0_branch_clk", - .parent_names = (const char *[]){ "usb30_master_ref_src", }, + .parent_data = &(const struct clk_parent_data){ + .hw = &usb30_master_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2033,7 +2095,9 @@ static struct clk_branch usb30_1_branch_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb30_1_branch_clk", - .parent_names = (const char *[]){ "usb30_master_ref_src", }, + .parent_data = &(const struct clk_parent_data){ + .hw = &usb30_master_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2071,7 +2135,7 @@ static struct clk_rcg usb30_utmi_clk = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb30_utmi_clk", - .parent_names = gcc_pxo_pll8_pll0, + .parent_data = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2087,7 +2151,9 @@ static struct clk_branch usb30_0_utmi_clk_ctl = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb30_0_utmi_clk_ctl", - .parent_names = (const char *[]){ "usb30_utmi_clk", }, + .parent_data = &(const struct clk_parent_data){ + .hw = &usb30_utmi_clk.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2103,7 +2169,9 @@ static struct clk_branch usb30_1_utmi_clk_ctl = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb30_1_utmi_clk_ctl", - .parent_names = (const char *[]){ "usb30_utmi_clk", }, + .parent_data = &(const struct clk_parent_data){ + .hw = &usb30_utmi_clk.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2141,7 +2209,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_src", - .parent_names = gcc_pxo_pll8_pll0, + .parent_data = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2157,7 +2225,9 @@ static struct clk_branch usb_hs1_xcvr_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_clk", - .parent_names = (const char *[]){ "usb_hs1_xcvr_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &usb_hs1_xcvr_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2205,7 +2275,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_fs1_xcvr_src", - .parent_names = gcc_pxo_pll8_pll0, + .parent_data = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2221,7 +2291,9 @@ static struct clk_branch usb_fs1_xcvr_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "usb_fs1_xcvr_clk", - .parent_names = (const char *[]){ "usb_fs1_xcvr_src", }, + .parent_data = &(const struct clk_parent_data){ + .hw = &usb_fs1_xcvr_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2237,7 +2309,9 @@ static struct clk_branch usb_fs1_sys_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb_fs1_sys_clk", - .parent_names = (const char *[]){ "usb_fs1_xcvr_src", }, + .parent_data = &(const struct clk_parent_data){ + .hw = &usb_fs1_xcvr_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2337,7 +2411,7 @@ static struct clk_dyn_rcg gmac_core1_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gmac_core1_src", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, }, @@ -2354,8 +2428,8 @@ static struct clk_branch gmac_core1_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gmac_core1_clk", - .parent_names = (const char *[]){ - "gmac_core1_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gmac_core1_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2409,7 +2483,7 @@ static struct clk_dyn_rcg gmac_core2_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gmac_core2_src", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, }, @@ -2426,8 +2500,8 @@ static struct clk_branch gmac_core2_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gmac_core2_clk", - .parent_names = (const char *[]){ - "gmac_core2_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gmac_core2_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2481,7 +2555,7 @@ static struct clk_dyn_rcg gmac_core3_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gmac_core3_src", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, }, @@ -2498,8 +2572,8 @@ static struct clk_branch gmac_core3_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gmac_core3_clk", - .parent_names = (const char *[]){ - "gmac_core3_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gmac_core3_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2553,7 +2627,7 @@ static struct clk_dyn_rcg gmac_core4_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gmac_core4_src", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, }, @@ -2570,8 +2644,8 @@ static struct clk_branch gmac_core4_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gmac_core4_clk", - .parent_names = (const char *[]){ - "gmac_core4_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gmac_core4_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2613,7 +2687,7 @@ static struct clk_dyn_rcg nss_tcm_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "nss_tcm_src", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, }, @@ -2628,8 +2702,8 @@ static struct clk_branch nss_tcm_clk = { .enable_mask = BIT(6) | BIT(4), .hw.init = &(struct clk_init_data){ .name = "nss_tcm_clk", - .parent_names = (const char *[]){ - "nss_tcm_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &nss_tcm_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2691,7 +2765,7 @@ static struct clk_dyn_rcg ubi32_core1_src_clk = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "ubi32_core1_src_clk", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, @@ -2744,7 +2818,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "ubi32_core2_src_clk", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, From patchwork Tue Jan 18 00:44:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 533686 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00F8CC43219 for ; Tue, 18 Jan 2022 01:02:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243941AbiARBCC (ORCPT ); Mon, 17 Jan 2022 20:02:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39072 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243872AbiARBB6 (ORCPT ); Mon, 17 Jan 2022 20:01:58 -0500 Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8AC86C061574; Mon, 17 Jan 2022 17:01:57 -0800 (PST) Received: by mail-ed1-x531.google.com with SMTP id z22so72642880edd.12; Mon, 17 Jan 2022 17:01:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=TmJxjyQbdETgs4yns2i+f8c1louW3ocpGtGrolnd4As=; b=UUKoYPEp0/3gidXvwZTyUsow4ZYvhJpsHNle8L21BPIW2LapS9al/QD6FBlJnUecYc hjlVI0A5XjIsk/iCrQbxYrva1YUbjGgWrVYS8ZZN7KbrcHYnUrNvLLQIN3JXjjcA3Dp6 PSF8+2nL59Dsy050DAiG8kypCZq/p+EfblA3Zyy7lj1/IIqP72bKAaeHa3OAsCBTUVPG XJmmRGADw7O4SzhWqyoEb/VObvOOeN3DRVBM8aKqdDpuWdR6d1x9Imo0ZPKC0InD1CvE ZU2YnixZd/0b5LpiEbtZiKdQZ58ROApQ6lqwU3wW3YU88BesDOYkAmy8iY7kG0wJ4uy6 WFLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TmJxjyQbdETgs4yns2i+f8c1louW3ocpGtGrolnd4As=; b=ox0QkNTdHnUKIRnhGvHKauUVUaEkN30lDz75Id8SZuLf+R3YoB6uqjrkMR6qbOvlXr RsfByp0aZYwxqaCXAHP1ZiCj1+k8oHw4/qT3iGY+OvSfnuDHj8TDjhkdQOkckKURlfas XW8es4/xtfsIYZI1Wx0Fk8P0os8lueYyWWpjGnXG3PP3AOkdZfeBrYxPI4m2qCyLen0w M4IiEmYMHcjboPLarq+OO2HSHRU4l4vTcqJHTqSssovX13EVxAVaYzlnb6FhoHNkHYNg sx03UJYbscOpuBns5HZvj7SIqUg32ILuCYrOERqgfNKxcqHWT+WUZLFPXxRkRbhZ8hfj YRxQ== X-Gm-Message-State: AOAM533EgXvluqtYQ4s/daoo+KzxvRG+Zl8wnb/A/6zPaKV07btNGksH cqd0HMcBG0vWg9RuH8MF0nSxMUl6uAI= X-Google-Smtp-Source: ABdhPJy5f5rLvfUTaUbsS3+CtIMri47cAtZl+y8SWGZVfVXVq4BZZJ854XmQCwiOy8pV02UmgRHzug== X-Received: by 2002:a17:906:1e4f:: with SMTP id i15mr19605736ejj.522.1642467716046; Mon, 17 Jan 2022 17:01:56 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id 24sm4892127ejg.47.2022.01.17.17.01.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jan 2022 17:01:55 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/14] drivers: clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents Date: Tue, 18 Jan 2022 01:44:24 +0100 Message-Id: <20220118004434.17095-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220118004434.17095-1-ansuelsmth@gmail.com> References: <20220118004434.17095-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use ARRAY_SIZE for num_parents instead of hardcoding the value. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 68 +++++++++++++++++----------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index cbacd56f52d4..17ce61f36b08 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -385,7 +385,7 @@ static struct clk_rcg gsbi1_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -436,7 +436,7 @@ static struct clk_rcg gsbi2_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -487,7 +487,7 @@ static struct clk_rcg gsbi4_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -538,7 +538,7 @@ static struct clk_rcg gsbi5_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -589,7 +589,7 @@ static struct clk_rcg gsbi6_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi6_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -640,7 +640,7 @@ static struct clk_rcg gsbi7_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi7_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -704,7 +704,7 @@ static struct clk_rcg gsbi1_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -755,7 +755,7 @@ static struct clk_rcg gsbi2_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -806,7 +806,7 @@ static struct clk_rcg gsbi4_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -857,7 +857,7 @@ static struct clk_rcg gsbi5_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -908,7 +908,7 @@ static struct clk_rcg gsbi6_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi6_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -959,7 +959,7 @@ static struct clk_rcg gsbi7_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi7_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1111,7 +1111,7 @@ static struct clk_rcg gp0_src = { .hw.init = &(struct clk_init_data){ .name = "gp0_src", .parent_data = gcc_pxo_pll8_cxo, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1162,7 +1162,7 @@ static struct clk_rcg gp1_src = { .hw.init = &(struct clk_init_data){ .name = "gp1_src", .parent_data = gcc_pxo_pll8_cxo, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1213,7 +1213,7 @@ static struct clk_rcg gp2_src = { .hw.init = &(struct clk_init_data){ .name = "gp2_src", .parent_data = gcc_pxo_pll8_cxo, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1269,7 +1269,7 @@ static struct clk_rcg prng_src = { .hw.init = &(struct clk_init_data){ .name = "prng_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, }, @@ -1333,7 +1333,7 @@ static struct clk_rcg sdc1_src = { .hw.init = &(struct clk_init_data){ .name = "sdc1_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, } @@ -1383,7 +1383,7 @@ static struct clk_rcg sdc3_src = { .hw.init = &(struct clk_init_data){ .name = "sdc3_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, } @@ -1468,7 +1468,7 @@ static struct clk_rcg tsif_ref_src = { .hw.init = &(struct clk_init_data){ .name = "tsif_ref_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, } @@ -1632,7 +1632,7 @@ static struct clk_rcg pcie_ref_src = { .hw.init = &(struct clk_init_data){ .name = "pcie_ref_src", .parent_data = gcc_pxo_pll3, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1726,7 +1726,7 @@ static struct clk_rcg pcie1_ref_src = { .hw.init = &(struct clk_init_data){ .name = "pcie1_ref_src", .parent_data = gcc_pxo_pll3, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1820,7 +1820,7 @@ static struct clk_rcg pcie2_ref_src = { .hw.init = &(struct clk_init_data){ .name = "pcie2_ref_src", .parent_data = gcc_pxo_pll3, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1919,7 +1919,7 @@ static struct clk_rcg sata_ref_src = { .hw.init = &(struct clk_init_data){ .name = "sata_ref_src", .parent_data = gcc_pxo_pll3, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2062,7 +2062,7 @@ static struct clk_rcg usb30_master_clk_src = { .hw.init = &(struct clk_init_data){ .name = "usb30_master_ref_src", .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2136,7 +2136,7 @@ static struct clk_rcg usb30_utmi_clk = { .hw.init = &(struct clk_init_data){ .name = "usb30_utmi_clk", .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2210,7 +2210,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_src", .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2276,7 +2276,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { .hw.init = &(struct clk_init_data){ .name = "usb_fs1_xcvr_src", .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2412,7 +2412,7 @@ static struct clk_dyn_rcg gmac_core1_src = { .hw.init = &(struct clk_init_data){ .name = "gmac_core1_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2484,7 +2484,7 @@ static struct clk_dyn_rcg gmac_core2_src = { .hw.init = &(struct clk_init_data){ .name = "gmac_core2_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2556,7 +2556,7 @@ static struct clk_dyn_rcg gmac_core3_src = { .hw.init = &(struct clk_init_data){ .name = "gmac_core3_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2628,7 +2628,7 @@ static struct clk_dyn_rcg gmac_core4_src = { .hw.init = &(struct clk_init_data){ .name = "gmac_core4_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2688,7 +2688,7 @@ static struct clk_dyn_rcg nss_tcm_src = { .hw.init = &(struct clk_init_data){ .name = "nss_tcm_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2766,7 +2766,7 @@ static struct clk_dyn_rcg ubi32_core1_src_clk = { .hw.init = &(struct clk_init_data){ .name = "ubi32_core1_src_clk", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, }, @@ -2819,7 +2819,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = { .hw.init = &(struct clk_init_data){ .name = "ubi32_core2_src_clk", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, }, From patchwork Tue Jan 18 00:44:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 533685 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AB5DC4167D for ; Tue, 18 Jan 2022 01:02:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243959AbiARBCD (ORCPT ); Mon, 17 Jan 2022 20:02:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243878AbiARBB7 (ORCPT ); Mon, 17 Jan 2022 20:01:59 -0500 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90C46C061574; Mon, 17 Jan 2022 17:01:58 -0800 (PST) Received: by mail-ed1-x52e.google.com with SMTP id u21so72585771edd.5; Mon, 17 Jan 2022 17:01:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ciuwc03q2BGkK4WAOq0QYpQJkVPGRMXxXF8I3KXs9ZY=; b=aO996fTOi8uCivGeZHAIolHhksWaqKkgdA1xdywUzF+1XQLlA7BBK0oRHPDySiIIkO ooa/KpAbFZay4dg9IRRJzZk/NrI272l1+GPRB52IK6E5/NkKD954Ey7iKtK3DnlBypC8 VpSuxP/UtDd7BwnANA8f0o97go8FVpY9IrQGoYXalEr4wgvk1ovvxe6pHaGkq4m8d1at wuEO5DT46aCumoW81LdJDG2vmf8WAxLAd6qhcw1rPwDnhF7BgFVrKGoytbEAfsdCUNUf d3C9IORC0op9XeUbZbvTBwbNKb4lu9kj61I7dqXp7mA//wfK3iMrRmg6k98dAS6wsPKb bsgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ciuwc03q2BGkK4WAOq0QYpQJkVPGRMXxXF8I3KXs9ZY=; b=w8JJgluc7+WPRBH7RHyWJa+nXZL91SmNrdTPx3ew27QXqZYO0FEif+ElpgFMgtw+zd KzcqyY8b3rZEHDdI3sdCxY9DCY5cKuSCFMmoJnt6uPgjkK7wuS101oIn5MCRdo1GfNkf Xoqh2b8FmS0q0qOmUiRZfEWHDKgza4+jfMu7CnxlY0zTQOwbqYd8nyu/DX2BN26QaSaL aWi6iTHrfTfP3YuaUqfdgRX+TozaO6W1Au1dWwmzkBPxcRrr6rUsdbQ52ZHiGuq7B3Yj rrT4NYwxnoa4kxIvt9o0R+wsmbNWU2SYNoBeC0hpWFIfcyxvnhVyRUWIotvEDnhlbdBE kP6g== X-Gm-Message-State: AOAM532K0Q3HC92r9u/N/dkvZphPJY7L08ih0VlqpQ98jUlWsLvbLrFc bMG/6VRij5OXcYMt6cn0zKQ= X-Google-Smtp-Source: ABdhPJwadbQQhQFwwou3GrAenFFGLoM7xgWnNr+7WUqN1Io6TuBfb+T9O36lvtsRgXoA1pnn36VmvQ== X-Received: by 2002:a17:906:5d0f:: with SMTP id g15mr5271614ejt.167.1642467717023; Mon, 17 Jan 2022 17:01:57 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id 24sm4892127ejg.47.2022.01.17.17.01.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jan 2022 17:01:56 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 05/14] drivers: clk: qcom: gcc-ipq806x: drop hardcoded pxo and cxo source clk Date: Tue, 18 Jan 2022 01:44:25 +0100 Message-Id: <20220118004434.17095-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220118004434.17095-1-ansuelsmth@gmail.com> References: <20220118004434.17095-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We now define these clk in dts. Drop pxo and cxo hardcoded in the gcc probe function. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 17ce61f36b08..383494280e3e 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -3133,23 +3133,14 @@ MODULE_DEVICE_TABLE(of, gcc_ipq806x_match_table); static int gcc_ipq806x_probe(struct platform_device *pdev) { - struct device *dev = &pdev->dev; struct regmap *regmap; int ret; - ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000); - if (ret) - return ret; - - ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000); - if (ret) - return ret; - ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc); if (ret) return ret; - regmap = dev_get_regmap(dev, NULL); + regmap = dev_get_regmap(&pdev->dev, NULL); if (!regmap) return -ENODEV; From patchwork Tue Jan 18 00:44:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 533684 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4047BC4321E for ; Tue, 18 Jan 2022 01:02:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244123AbiARBCO (ORCPT ); Mon, 17 Jan 2022 20:02:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229836AbiARBCA (ORCPT ); Mon, 17 Jan 2022 20:02:00 -0500 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3261C061574; Mon, 17 Jan 2022 17:01:59 -0800 (PST) Received: by mail-ed1-x52f.google.com with SMTP id b13so72861440edn.0; Mon, 17 Jan 2022 17:01:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=X3rbRq5KfKbeBC7Dkw4uo5NOk4Ukps/dmiHuiNy8NQc=; b=Sz/r6tel48hi+gCzCaVmU6ApnbpTRvGnhkCT3ijgn9gjmAj9dLy3C5/KvbN4/ImVlj oU4w/JYu7HgFQh6Jjy58QNX537t/7p7mvHF6oTyTHmaLiemuZYlJ/gYrXR7o4q4ShRrl 1rTxch2FKD1ahFrPNQszh5fMr/6jEHbmRAuJzbv1svQcLVmbYXAzEOp6gGIWX8+PQg+j J75U5KP9qculY8DLdCTYnKZRppSrdBEfs2e0iN3a+rky5+JKxE+Yz3EQLFjKEJpRx801 6EJ1+GNrCgiDLiq5Js61SiXk4YERnRhEzVNbBn7GXXgXV8mcqFLsSvRgVc+KR3g5JsCO 4i/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X3rbRq5KfKbeBC7Dkw4uo5NOk4Ukps/dmiHuiNy8NQc=; b=6H/VCnSQuSZnTqqx1DICpaq0qkTG5tVlJzrd8Oy+1xZckoYjxE6XCkWusqpcg6M56W bUlCd2IecAVciB6hBO9Lq9kuz8aTJgkHumLRMAOwF67hE6LhCO3HbMrelaauFzCu7dhE DFW509Cnas9+B0P6v0cThL37MFy2KoSFjv6rP58t1s2RIO00msOnl+gVIVJbYHT4spoq vjmQmBskCsE84fwOIZcmo6sz8AasoDRBNCD6W9cmChlK7A9nP/2WhMQ2mWV61avcMuWu w3uf3w90soDisr1+0z83DIBv/HbTUyNWJkEU1JIuKAtdJQdQqMmM55S5C0f9Phu6zsQf OYXA== X-Gm-Message-State: AOAM532dP1vPxEqnvcoblcS5LFPGdnVJ0fvaFl4z58EtSb1upQqvy6Jp 7zgsiAk0K74SWiXqOXDwYLc= X-Google-Smtp-Source: ABdhPJyAzXaFCJe40ztl7YCSxcfx3Fc8bwM/Ywi+aUpQDYUrDNaNxz7GVz+hdQQ4O21xOC/AI1W5rA== X-Received: by 2002:a17:906:e43:: with SMTP id q3mr12859971eji.92.1642467718082; Mon, 17 Jan 2022 17:01:58 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id 24sm4892127ejg.47.2022.01.17.17.01.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jan 2022 17:01:57 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 06/14] drivers: clk: qcom: gcc-ipq806x: use parent_hws where possible Date: Tue, 18 Jan 2022 01:44:26 +0100 Message-Id: <20220118004434.17095-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220118004434.17095-1-ansuelsmth@gmail.com> References: <20220118004434.17095-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use parent_hws instead of generic parent_data when parents all the parent are defined in the ipq806x gcc driver. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 156 ++++++++++++++++----------------- 1 file changed, 78 insertions(+), 78 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 383494280e3e..ce5654d3e937 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -48,8 +48,8 @@ static struct clk_regmap pll0_vote = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "pll0_vote", - .parent_data = &(const struct clk_parent_data){ - .hw = &pll0.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &pll0.clkr.hw, }, .num_parents = 1, .ops = &clk_pll_vote_ops, @@ -108,8 +108,8 @@ static struct clk_regmap pll8_vote = { .enable_mask = BIT(8), .hw.init = &(struct clk_init_data){ .name = "pll8_vote", - .parent_data = &(const struct clk_parent_data){ - .hw = &pll8.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &pll8.clkr.hw, }, .num_parents = 1, .ops = &clk_pll_vote_ops, @@ -223,8 +223,8 @@ static struct clk_regmap pll14_vote = { .enable_mask = BIT(14), .hw.init = &(struct clk_init_data){ .name = "pll14_vote", - .parent_data = &(const struct clk_parent_data){ - .hw = &pll14.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &pll14.clkr.hw, }, .num_parents = 1, .ops = &clk_pll_vote_ops, @@ -400,8 +400,8 @@ static struct clk_branch gsbi1_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gsbi1_uart_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gsbi1_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -451,8 +451,8 @@ static struct clk_branch gsbi2_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gsbi2_uart_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gsbi2_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -502,8 +502,8 @@ static struct clk_branch gsbi4_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gsbi4_uart_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gsbi4_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -553,8 +553,8 @@ static struct clk_branch gsbi5_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gsbi5_uart_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gsbi5_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -604,8 +604,8 @@ static struct clk_branch gsbi6_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi6_uart_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gsbi6_uart_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gsbi6_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -655,8 +655,8 @@ static struct clk_branch gsbi7_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi7_uart_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gsbi7_uart_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gsbi7_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -719,8 +719,8 @@ static struct clk_branch gsbi1_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gsbi1_qup_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gsbi1_qup_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -770,8 +770,8 @@ static struct clk_branch gsbi2_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gsbi2_qup_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gsbi2_qup_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -821,8 +821,8 @@ static struct clk_branch gsbi4_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gsbi4_qup_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gsbi4_qup_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -872,8 +872,8 @@ static struct clk_branch gsbi5_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gsbi5_qup_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gsbi5_qup_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -923,8 +923,8 @@ static struct clk_branch gsbi6_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi6_qup_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gsbi6_qup_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gsbi6_qup_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -974,8 +974,8 @@ static struct clk_branch gsbi7_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi7_qup_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gsbi7_qup_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gsbi7_qup_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -1126,8 +1126,8 @@ static struct clk_branch gp0_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gp0_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gp0_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -1177,8 +1177,8 @@ static struct clk_branch gp1_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gp1_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gp1_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -1228,8 +1228,8 @@ static struct clk_branch gp2_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gp2_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gp2_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -1284,8 +1284,8 @@ static struct clk_branch prng_clk = { .enable_mask = BIT(10), .hw.init = &(struct clk_init_data){ .name = "prng_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &prng_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &prng_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -1347,8 +1347,8 @@ static struct clk_branch sdc1_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "sdc1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &sdc1_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &sdc1_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -1397,8 +1397,8 @@ static struct clk_branch sdc3_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "sdc3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &sdc3_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &sdc3_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -1482,8 +1482,8 @@ static struct clk_branch tsif_ref_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "tsif_ref_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &tsif_ref_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &tsif_ref_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -1647,8 +1647,8 @@ static struct clk_branch pcie_ref_src_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "pcie_ref_src_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &pcie_ref_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &pcie_ref_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -1741,8 +1741,8 @@ static struct clk_branch pcie1_ref_src_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "pcie1_ref_src_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &pcie1_ref_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &pcie1_ref_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -1835,8 +1835,8 @@ static struct clk_branch pcie2_ref_src_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "pcie2_ref_src_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &pcie2_ref_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &pcie2_ref_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -1934,8 +1934,8 @@ static struct clk_branch sata_rxoob_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "sata_rxoob_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &sata_ref_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &sata_ref_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -1952,8 +1952,8 @@ static struct clk_branch sata_pmalive_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "sata_pmalive_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &sata_ref_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &sata_ref_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2077,8 +2077,8 @@ static struct clk_branch usb30_0_branch_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb30_0_branch_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &usb30_master_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &usb30_master_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2095,8 +2095,8 @@ static struct clk_branch usb30_1_branch_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb30_1_branch_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &usb30_master_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &usb30_master_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2151,8 +2151,8 @@ static struct clk_branch usb30_0_utmi_clk_ctl = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb30_0_utmi_clk_ctl", - .parent_data = &(const struct clk_parent_data){ - .hw = &usb30_utmi_clk.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &usb30_utmi_clk.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2169,8 +2169,8 @@ static struct clk_branch usb30_1_utmi_clk_ctl = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb30_1_utmi_clk_ctl", - .parent_data = &(const struct clk_parent_data){ - .hw = &usb30_utmi_clk.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &usb30_utmi_clk.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2225,8 +2225,8 @@ static struct clk_branch usb_hs1_xcvr_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &usb_hs1_xcvr_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &usb_hs1_xcvr_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2291,8 +2291,8 @@ static struct clk_branch usb_fs1_xcvr_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "usb_fs1_xcvr_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &usb_fs1_xcvr_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &usb_fs1_xcvr_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2309,8 +2309,8 @@ static struct clk_branch usb_fs1_sys_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb_fs1_sys_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &usb_fs1_xcvr_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &usb_fs1_xcvr_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2428,8 +2428,8 @@ static struct clk_branch gmac_core1_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gmac_core1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gmac_core1_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gmac_core1_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2500,8 +2500,8 @@ static struct clk_branch gmac_core2_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gmac_core2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gmac_core2_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gmac_core2_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2572,8 +2572,8 @@ static struct clk_branch gmac_core3_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gmac_core3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gmac_core3_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gmac_core3_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2644,8 +2644,8 @@ static struct clk_branch gmac_core4_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gmac_core4_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gmac_core4_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gmac_core4_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2702,8 +2702,8 @@ static struct clk_branch nss_tcm_clk = { .enable_mask = BIT(6) | BIT(4), .hw.init = &(struct clk_init_data){ .name = "nss_tcm_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &nss_tcm_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &nss_tcm_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, From patchwork Tue Jan 18 00:44:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 532932 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6351CC4167B for ; Tue, 18 Jan 2022 01:02:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244156AbiARBCQ (ORCPT ); Mon, 17 Jan 2022 20:02:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39092 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243896AbiARBCB (ORCPT ); Mon, 17 Jan 2022 20:02:01 -0500 Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 95C47C06161C; Mon, 17 Jan 2022 17:02:00 -0800 (PST) Received: by mail-ed1-x531.google.com with SMTP id 15so39406800edx.9; Mon, 17 Jan 2022 17:02:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=cf+P4bGd9tu17hA7rWQ2MKI9pQI9iWRAdtNFE5256nQ=; b=hNiKVFT6a1uEaLKDwH5eTkMXs+pdGmRvKQj7+xC5FNd5hyGW9eSBziEa/K9RYGIkG9 fMYMtUan3uXfBqvBNDsFC3/BmSYMxXSQcShsxHi/Q8UduFBrON7ipWdu6UnWbWoVxh8e nT7Xi3MsH+dHZ0l84/PfsYFLJUGXuFOLpsYQ9VnIPrB72ko5o0V2phWCWTHYXeM7i5Pt Qjo81SQ1iMcY1VGNfR5scll8qzRSE1gKV37qUHAIEp/mRFWVNCzjyhnXh7oY9k2eigUi qukMKG/plYe6jx4dTyvWKEI7qSVx/IRANqXyAHQRI7ugLr20hXAH0brnVvvIP3aarZhb GKVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cf+P4bGd9tu17hA7rWQ2MKI9pQI9iWRAdtNFE5256nQ=; b=Pfs41im4jckenrB5Au7CWp7tUKrn2dPxI7gM9c2lG+vh2GNI5BfqwGQwps2kKzQ4qN NK6sZZKjLwya0jsbzVfvcGjORYu1+ettcSeYvfXgeIf4vHTnBbQJoxGX8vwVRR9FsuOM +3rYyGwDXb4ra48IktiPKQOyqGS7oHDAuK5DzUJzual36SQxLBmXrzRZ+DZoTfoL0l7J YvCaqAoZpkhwO0GvBmR/NqMVk8iCd3O1nN4DEaXH/85TdqJhcU306JDxOM+0CbYTDcpw l4nAW1TA85fbB5BOIhf6gIFlV96i/0+ODBAI8xuUpiV39eETQ1EYP63N5PiLz2UqD5jz 1dGw== X-Gm-Message-State: AOAM532fJv5o5lSJxVHUTmsMnEqmNyWueJuhr0/fF0kW3rQenMWqrPk3 mE3WAKsInORCF1yAnvwlwx8= X-Google-Smtp-Source: ABdhPJyK3QyODMzR20rsrBpJ8qA/Jmi/N6HnkkXzEKhM0NWzz4+7/07L5SF8fohRNueWVgJpIxkEMQ== X-Received: by 2002:a17:907:1b21:: with SMTP id mp33mr18157651ejc.580.1642467719093; Mon, 17 Jan 2022 17:01:59 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id 24sm4892127ejg.47.2022.01.17.17.01.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jan 2022 17:01:58 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/14] drivers: clk: qcom: gcc-ipq806x: add additional freq nss cores Date: Tue, 18 Jan 2022 01:44:27 +0100 Message-Id: <20220118004434.17095-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220118004434.17095-1-ansuelsmth@gmail.com> References: <20220118004434.17095-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Ipq8065 SoC (an evolution of ipq8064 SoC) contains nss cores that can be clocked to 800MHz. Add these missing freq to the gcc driver. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index ce5654d3e937..d0c5441eb98e 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -242,7 +242,9 @@ static struct clk_regmap pll14_vote = { static struct pll_freq_tbl pll18_freq_tbl[] = { NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625), + NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625), NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625), + NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625), }; static struct clk_pll pll18 = { @@ -2716,7 +2718,9 @@ static const struct freq_tbl clk_tbl_nss[] = { { 110000000, P_PLL18, 1, 1, 5 }, { 275000000, P_PLL18, 2, 0, 0 }, { 550000000, P_PLL18, 1, 0, 0 }, + { 600000000, P_PLL18, 1, 0, 0 }, { 733000000, P_PLL18, 1, 0, 0 }, + { 800000000, P_PLL18, 1, 0, 0 }, { } }; From patchwork Tue Jan 18 00:44:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 533683 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AECBC4167E for ; Tue, 18 Jan 2022 01:02:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244070AbiARBCR (ORCPT ); Mon, 17 Jan 2022 20:02:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39106 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243960AbiARBCD (ORCPT ); Mon, 17 Jan 2022 20:02:03 -0500 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94ADBC061401; Mon, 17 Jan 2022 17:02:01 -0800 (PST) Received: by mail-ed1-x52b.google.com with SMTP id m4so72501351edb.10; Mon, 17 Jan 2022 17:02:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=rCx/NWCn5wFgUlCns4gxP47CTM6P+IWicMwkRv5E1+s=; b=W00CEX5U3ssKB+oc/8MFhXvIomGoLhGg7yCosvBcOD6Wuyo4FD2JPS2OPMhwVBPqRO gePd2zjbvbNwkfgLtBLtS429rXGK5LIY5nY0Ax6HuCWC1o3Nf35o+GPm8OwNuxLXNq32 MgbR2hd5EPAtykP3e+plOIXTy/o3AGhMEVMqDm5H08jht+FGdfrrpdvXl/lHiZKoE4kw HhudslCY/IFNB6hsXLj5X1OiHXBmrXYNxobEcxmLzBD6q19j364ZNODKpcXscSa2JPZQ bWknZLbHEzu4g12kIog01MKBgVa8gUcc2TRiMkiGLwMrpUUH9LwaFPs7Jj7yFs7/KtjU FZsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rCx/NWCn5wFgUlCns4gxP47CTM6P+IWicMwkRv5E1+s=; b=qqequIVvWRn0QXoXNhTMdIOV31zGzOS8XD8M8NhCvk1SEVXlOyG1Z4RRt/Dziktxm8 vXz6JM+OmwMVllq4roCwuinNCwFD8bqRFEquQE1bWG2m26yI0MGT97tOsg0IOKS1xjMM GpD9FnL+WrLmwsiGinE3tA2aJ8sdS4d/imYLqBcLSXITs4ZDZ8fh7FALmLJCNp6i+lzj zuZK2bz4EW1ByKnyLWInjbdQZifm2/SEw6QupJG9Gy27th7FVzqZVqDghwyTfFzVxwOE rPXzGQKnw4jkp5o2tQUn/s79aBhCRlqhZl4OOY14q+04u9cSNmUCL94FeK9nIaspFC3O YTHw== X-Gm-Message-State: AOAM532ICZk+gWzHNccYbCcoI55ZfB7BJwBPPxV/cAiBvkiMkY6HyKId zWEerB0yKYOZ9XYQf8rAXUU= X-Google-Smtp-Source: ABdhPJwaLjuiJXYwOM+CpUiffY2l13ni9Tf460XnssKQ2McotB+4RV+MocFyft2g6cZHVr6s0BkoPA== X-Received: by 2002:a17:906:5fc2:: with SMTP id k2mr12334612ejv.472.1642467720128; Mon, 17 Jan 2022 17:02:00 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id 24sm4892127ejg.47.2022.01.17.17.01.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jan 2022 17:01:59 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/14] drivers: clk: qcom: gcc-ipq806x: add unusued flag for critical clock Date: Tue, 18 Jan 2022 01:44:28 +0100 Message-Id: <20220118004434.17095-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220118004434.17095-1-ansuelsmth@gmail.com> References: <20220118004434.17095-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some clocks are used by other devices present on the SoC. For example the gsbi4_h_clk is used by RPM and is if disabled cause the RPM to reject any regulator change command. These clock should never be disabled. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index d0c5441eb98e..7d1ddbbbc8ec 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -810,7 +810,7 @@ static struct clk_rcg gsbi4_qup_src = { .parent_data = gcc_pxo_pll8, .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, + .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, }, }, }; @@ -828,7 +828,7 @@ static struct clk_branch gsbi4_qup_clk = { }, .num_parents = 1, .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, }, }, }; @@ -912,7 +912,7 @@ static struct clk_rcg gsbi6_qup_src = { .parent_data = gcc_pxo_pll8, .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, + .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, }, }, }; @@ -981,7 +981,7 @@ static struct clk_branch gsbi7_qup_clk = { }, .num_parents = 1, .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, }, }, }; @@ -1027,6 +1027,7 @@ static struct clk_branch gsbi4_h_clk = { .hw.init = &(struct clk_init_data){ .name = "gsbi4_h_clk", .ops = &clk_branch_ops, + .flags = CLK_IGNORE_UNUSED, }, }, }; From patchwork Tue Jan 18 00:44:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 532931 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BAB0C2BA4C for ; Tue, 18 Jan 2022 01:02:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244011AbiARBCS (ORCPT ); Mon, 17 Jan 2022 20:02:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39108 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243963AbiARBCD (ORCPT ); Mon, 17 Jan 2022 20:02:03 -0500 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FA01C061747; Mon, 17 Jan 2022 17:02:02 -0800 (PST) Received: by mail-ed1-x52c.google.com with SMTP id f21so15536288eds.11; Mon, 17 Jan 2022 17:02:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=lj9tyHKwn1pbX2A1jzsdupYAHEFENiH62KbSI1f1j2c=; b=bMr3MbKYmOjqfILlGPAynUEEC0XPgkyTNRhiWETQ7zHBC6yGjtIb5ptlFBJ/3U13Yi estKbbFawC+Fr23oxP7lxLCt8Cd7hIcjfMBo1cHZ3bNJXouk7wc9eUb3pR9rPcbu5BQk SSK0dSe2fWOwFe64WUD9BU0A3ZaXePA8gK+xX50IeZCrdu/i6wstB4UltEOZv6YHP12E seC6bG7DSQUV0hU+l/UgRf9jKGc5QGkYtXernKxDqaEYHBXpfeToGHk+wJkMgI1X/2HN Ln4eXG5Qq6hWFnOAoD9gJVLoHPtjslSz/jmuD10F/zDwiQwJPgE9w3UCHPdk7Mbxanje j46Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lj9tyHKwn1pbX2A1jzsdupYAHEFENiH62KbSI1f1j2c=; b=L+0aQ4L4huL3rWpg6G3tj2cBB1CpwTcSAgmyCoFSeg9iUl4K4daRvt/GFVC2anc0kP 5bSPXJB1V2+iDS2trklSdyucD25aVsym3bbtBUKN+wuR7cBWWKgLrMlnOcnik7RW2M9v LCiBLNiZ3wljE4CfJyRnKN0ynXTTccv8ighW3cmyB/BWJq9KRJE8dpU8fhrXN7eeLU0m DVrA17j30mFHYrkiBqxtGBvQlFPR756zv4geCBNUnRaFWVt1JvVT2JQUUYGb/uYZQ4nZ 0kjgCwmyNQfQOsfAdx+Zg4wzTfomh9r520kLMENLSCtESa4q61sxUZgDOWweLSIre263 TkZA== X-Gm-Message-State: AOAM532yNpUn1UpDOf3DMWNDvU2jyqpPqGm36EoaTDNMqi8qphfvz/HR 0sJ3nS9LxmEA1yPM4RxA7PQ= X-Google-Smtp-Source: ABdhPJy3IXye2zcrS9StAsu8r7oZBvJGEoTUKgACMf+lFQ+T07GUPm1rJQwRJIgqbkhDfkX5zrF6Xg== X-Received: by 2002:a17:907:a42a:: with SMTP id sg42mr18750849ejc.413.1642467721155; Mon, 17 Jan 2022 17:02:01 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id 24sm4892127ejg.47.2022.01.17.17.02.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jan 2022 17:02:00 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/14] drivers: clk: qcom: gcc-ipq806x: add additional freq for sdc table Date: Tue, 18 Jan 2022 01:44:29 +0100 Message-Id: <20220118004434.17095-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220118004434.17095-1-ansuelsmth@gmail.com> References: <20220118004434.17095-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add additional freq supported for the sdc table. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 7d1ddbbbc8ec..0923d7f79a1c 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -1304,6 +1304,7 @@ static const struct freq_tbl clk_tbl_sdc[] = { { 20210000, P_PLL8, 1, 1, 19 }, { 24000000, P_PLL8, 4, 1, 4 }, { 48000000, P_PLL8, 4, 1, 2 }, + { 52000000, P_PLL8, 1, 2, 15 }, /* 51.2 Mhz */ { 64000000, P_PLL8, 3, 1, 2 }, { 96000000, P_PLL8, 4, 0, 0 }, { 192000000, P_PLL8, 2, 0, 0 }, From patchwork Tue Jan 18 00:44:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 532930 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B75D0C3525B for ; Tue, 18 Jan 2022 01:02:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244002AbiARBCT (ORCPT ); Mon, 17 Jan 2022 20:02:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243993AbiARBCE (ORCPT ); Mon, 17 Jan 2022 20:02:04 -0500 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8BE0C061574; Mon, 17 Jan 2022 17:02:03 -0800 (PST) Received: by mail-ed1-x530.google.com with SMTP id 30so72680267edv.3; Mon, 17 Jan 2022 17:02:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=CXVZRlEKPP4hcCweUpH3JuNpFEE+gl2M3UXNpQ3IHj0=; b=ZKRD2QhSN8Ds7tSnS8enr3uAt/NjQva6NIkkOknlj5OszLfPQsZR/ijsyWJ9fc2WLk uplnrJY3ZAREamzZ4Dcwfkp7nNxQdNm6CKdDi7mZjTLcqkFQm3QiCmm1KhrMQpA7nRiU OOtbFGIMy0+EWerZrExY3I7HcDhaUx7WDkN26yqNipdBfkNFCGYOfNe5ZbGKa/W/ay8J rlICGXR0po/frBL7YyPIipvshTTZoULIqLgS+Yy5wCfWDywC4+Cvht4aXZIWTPcTI9Mq QR3TpOIQQue0Q3i0vlt7aYIne1HcDDFEtVoEabqfioezw65Zb2yWMOPJiePQB/S/uL1V s4aQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CXVZRlEKPP4hcCweUpH3JuNpFEE+gl2M3UXNpQ3IHj0=; b=A8V+3+XrX5rz8FVhzQVGw59aVK+ifYeNz4T9RN/V0yJnY3/pXmp32OdTFrcwukZcJ7 seFMgFQ3uAn5kGFNpD6oBv/zvzKBqStEdTlgNcNmsMwAKVsem4ohR11dHutcbeksdxTm dHN9vhYrHsFz1dunSrIo0/4L6FfaK5dh8W6/lkCTpFEYBzKjWiFFTXqMtm7fQDapSLUf ALgYBixGDKlAg2k3RVjACq7Eufm4NAUrP3UHhr3ugDLx29EI6vjyuCBH6x8qUaWgjW8U ObhIxEu0aBiSKWhpRCxBB2MGYJdFgXjMDWDhMKDxDE71xxb+zeZdIaJ9Eaz8ouQsgH6j sKuQ== X-Gm-Message-State: AOAM530JgfwsiYSFZyob/t6GHJ5Sc0pZGo3pADVmDmJDSOHIY8weTRYX URZU8qNO5R5I0NRcwcbHW0Y= X-Google-Smtp-Source: ABdhPJzmraW03nyXQa7eHj0BHSKZoBUEYfqBf7IaDSvinDs2ioZsDB8+ygHWlvmLbW3+6GhNAq4TQA== X-Received: by 2002:a05:6402:c12:: with SMTP id co18mr14364166edb.246.1642467722156; Mon, 17 Jan 2022 17:02:02 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id 24sm4892127ejg.47.2022.01.17.17.02.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jan 2022 17:02:01 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/14] dt-bindings: clock: add ipq8064 ce5 clk define Date: Tue, 18 Jan 2022 01:44:30 +0100 Message-Id: <20220118004434.17095-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220118004434.17095-1-ansuelsmth@gmail.com> References: <20220118004434.17095-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add ipq8064 ce5 clk define needed for CryptoEngine in gcc driver. Signed-off-by: Ansuel Smith --- include/dt-bindings/clock/qcom,gcc-ipq806x.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/include/dt-bindings/clock/qcom,gcc-ipq806x.h index 7deec14a6dee..02262d2ac899 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h @@ -240,7 +240,7 @@ #define PLL14 232 #define PLL14_VOTE 233 #define PLL18 234 -#define CE5_SRC 235 +#define CE5_A_CLK 235 #define CE5_H_CLK 236 #define CE5_CORE_CLK 237 #define CE3_SLEEP_CLK 238 @@ -283,5 +283,8 @@ #define EBI2_AON_CLK 281 #define NSSTCM_CLK_SRC 282 #define NSSTCM_CLK 283 +#define CE5_A_CLK_SRC 285 +#define CE5_H_CLK_SRC 286 +#define CE5_CORE_CLK_SRC 287 #endif From patchwork Tue Jan 18 00:44:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 532928 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C0EBC4167B for ; Tue, 18 Jan 2022 01:02:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244058AbiARBCd (ORCPT ); Mon, 17 Jan 2022 20:02:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244046AbiARBCF (ORCPT ); Mon, 17 Jan 2022 20:02:05 -0500 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE09DC06161C; Mon, 17 Jan 2022 17:02:04 -0800 (PST) Received: by mail-ed1-x535.google.com with SMTP id z22so72643838edd.12; Mon, 17 Jan 2022 17:02:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=cdRwCloUT8Thyo1nWTg/Cv6W0pfmm/eqyz83O1RekOs=; b=Ikm23nEs5gASUqJoTSmbWL5A2FTLi27PjBV534u7BNZ5fEjUiIShiC4jO2jf4FivbS Bgh2zciCPoK9XkO/daFf16ZpZxVhDdKOpHDmWCXUzK2yh7fOa/ZDJauvOK3hIi2ny2r8 TK5xKbAbNFVzkWEnfeTGUB1k1y43vvCz3sfJPYSnjSqgwuVFMDHQUErTt7XbUonN/n7q yF0HbupOZY3ChFqqB3pDr2L6XoSp4U8wejagNfTYYuPHZO16SEKjhzW2uVK8f1xXW22R 9PiMSJ+kVB+HJ6zZz/+0qS98B9j8uPC/o4QSlXSW/vfQT2F1E/dcNPhB/1wlnpMvDh/I lnrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cdRwCloUT8Thyo1nWTg/Cv6W0pfmm/eqyz83O1RekOs=; b=E/2MTPZD/VAGSof6yBjH8IgCrN9jl5O48Ewfu8TeQDFD9B3Geg6OpgdACo+h4WNiPw ccohEkT4j/mPdu9+CtLZAwVExZPTBywPJzDt7jXdf3w3k0PfsQm9tUnTNJf72LYANRDE Hn9AhBIhMauzyLIQRV8zzyVHnnnWH1K8GnY5Bxot2U1jtwoSZJ1e1X0GeRvHAFcwHg/8 3EskDJdhFxNL3G9H6aontdV4XqZp1TnTDLD+tAg60vZcTAnMCnXYQyoaXajBevBVp8Hf QVSDpMXCkSSV7cvKAsA86QeI1sAn3NW3vyDzEhWLtl1zxko+ilgLZk85CBfzO3xNDKKA BYNQ== X-Gm-Message-State: AOAM533VR4j/+gZJ3aOQ1OCe6L7t004tSymqoj3NXg0yf6J/hT7EikWm Z+iQBr77wYGvr2U5CYPaL7Q= X-Google-Smtp-Source: ABdhPJyilzrFW6mHgMehvlQefLz0cNTJZpr0b1ZUqbg7xJeAs9MSA/AuPRR70k2TnN7SSBpGzXo0BA== X-Received: by 2002:a17:907:6d8a:: with SMTP id sb10mr4773698ejc.86.1642467723283; Mon, 17 Jan 2022 17:02:03 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id 24sm4892127ejg.47.2022.01.17.17.02.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jan 2022 17:02:02 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 11/14] drivers: clk: qcom: gcc-ipq806x: add CryptoEngine clocks Date: Tue, 18 Jan 2022 01:44:31 +0100 Message-Id: <20220118004434.17095-12-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220118004434.17095-1-ansuelsmth@gmail.com> References: <20220118004434.17095-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add missing CryptoEngine clocks and pll11 required clock. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 244 +++++++++++++++++++++++++++++++++ 1 file changed, 244 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 0923d7f79a1c..46d0fe511868 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -268,6 +268,24 @@ static struct clk_pll pll18 = { }, }; +static struct clk_pll pll11 = { + .l_reg = 0x3184, + .m_reg = 0x3188, + .n_reg = 0x318c, + .config_reg = 0x3194, + .mode_reg = 0x3180, + .status_reg = 0x3198, + .status_bit = 16, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pll11", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pxo", + }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + enum { P_PXO, P_PLL8, @@ -276,6 +294,7 @@ enum { P_CXO, P_PLL14, P_PLL18, + P_PLL11, }; static const struct parent_map gcc_pxo_pll8_map[] = { @@ -343,6 +362,44 @@ static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = { { .hw = &pll18.clkr.hw }, }; +static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = { + { P_PXO, 0 }, + { P_PLL8, 4 }, + { P_PLL0, 2 }, + { P_PLL14, 5 }, + { P_PLL18, 1 }, + { P_PLL11, 3 }, +}; + +static const struct clk_parent_data gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = { + { .fw_name = "pxo" }, + { .hw = &pll8_vote.hw }, + { .hw = &pll0_vote.hw }, + { .hw = &pll14.clkr.hw }, + { .hw = &pll18.clkr.hw }, + { .hw = &pll11.clkr.hw }, + +}; + +static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = { + { P_PXO, 0 }, + { P_PLL3, 6 }, + { P_PLL0, 2 }, + { P_PLL14, 5 }, + { P_PLL18, 1 }, + { P_PLL11, 3 }, +}; + +static const struct clk_parent_data gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = { + { .fw_name = "pxo" }, + { .hw = &pll3.clkr.hw }, + { .hw = &pll0_vote.hw }, + { .hw = &pll14.clkr.hw }, + { .hw = &pll18.clkr.hw }, + { .hw = &pll11.clkr.hw }, + +}; + static struct freq_tbl clk_tbl_gsbi_uart[] = { { 1843200, P_PLL8, 2, 6, 625 }, { 3686400, P_PLL8, 2, 12, 625 }, @@ -2832,6 +2889,186 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = { }, }; +static const struct freq_tbl clk_tbl_ce5_core[] = { + { 150000000, P_PLL3, 8, 1, 1 }, + { 213200000, P_PLL11, 5, 1, 1 }, + { } +}; + +static struct clk_dyn_rcg ce5_core_src = { + .ns_reg[0] = 0x36C4, + .ns_reg[1] = 0x36C8, + .bank_reg = 0x36C0, + .s[0] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map, + }, + .s[1] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map, + }, + .p[0] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .p[1] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .mux_sel_bit = 0, + .freq_tbl = clk_tbl_ce5_core, + .clkr = { + .enable_reg = 0x36C0, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "ce5_core_src", + .parent_data = gcc_pxo_pll3_pll0_pll14_pll18_pll11, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3_pll0_pll14_pll18_pll11), + .ops = &clk_dyn_rcg_ops, + }, + }, +}; + +static struct clk_branch ce5_core_clk = { + .halt_reg = 0x2FDC, + .halt_bit = 5, + .hwcg_reg = 0x36CC, + .hwcg_bit = 6, + .clkr = { + .enable_reg = 0x36CC, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "ce5_core_clk", + .parent_hws = (const struct clk_hw*[]){ + &ce5_core_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static const struct freq_tbl clk_tbl_ce5_a_clk[] = { + { 160000000, P_PLL0, 5, 1, 1 }, + { 213200000, P_PLL11, 5, 1, 1 }, + { } +}; + +static struct clk_dyn_rcg ce5_a_clk_src = { + .ns_reg[0] = 0x3d84, + .ns_reg[1] = 0x3d88, + .bank_reg = 0x3d80, + .s[0] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, + }, + .s[1] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, + }, + .p[0] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .p[1] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .mux_sel_bit = 0, + .freq_tbl = clk_tbl_ce5_a_clk, + .clkr = { + .enable_reg = 0x3d80, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "ce5_a_clk_src", + .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11), + .ops = &clk_dyn_rcg_ops, + }, + }, +}; + +static struct clk_branch ce5_a_clk = { + .halt_reg = 0x3c20, + .halt_bit = 12, + .hwcg_reg = 0x3d8c, + .hwcg_bit = 6, + .clkr = { + .enable_reg = 0x3d8c, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "ce5_a_clk", + .parent_hws = (const struct clk_hw*[]){ + &ce5_a_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static const struct freq_tbl clk_tbl_ce5_h_clk[] = { + { 160000000, P_PLL0, 5, 1, 1 }, + { 213200000, P_PLL11, 5, 1, 1 }, + { } +}; + +static struct clk_dyn_rcg ce5_h_clk_src = { + .ns_reg[0] = 0x3c64, + .ns_reg[1] = 0x3c68, + .bank_reg = 0x3c60, + .s[0] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, + }, + .s[1] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, + }, + .p[0] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .p[1] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .mux_sel_bit = 0, + .freq_tbl = clk_tbl_ce5_h_clk, + .clkr = { + .enable_reg = 0x3c60, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "ce5_h_clk_src", + .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11), + .ops = &clk_dyn_rcg_ops, + }, + }, +}; + +static struct clk_branch ce5_h_clk = { + .halt_reg = 0x3c20, + .halt_bit = 11, + .hwcg_reg = 0x3c6c, + .hwcg_bit = 6, + .clkr = { + .enable_reg = 0x3c6c, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "ce5_h_clk", + .parent_hws = (const struct clk_hw*[]){ + &ce5_h_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + static struct clk_regmap *gcc_ipq806x_clks[] = { [PLL0] = &pll0.clkr, [PLL0_VOTE] = &pll0_vote, @@ -2839,6 +3076,7 @@ static struct clk_regmap *gcc_ipq806x_clks[] = { [PLL4_VOTE] = &pll4_vote, [PLL8] = &pll8.clkr, [PLL8_VOTE] = &pll8_vote, + [PLL11] = &pll11.clkr, [PLL14] = &pll14.clkr, [PLL14_VOTE] = &pll14_vote, [PLL18] = &pll18.clkr, @@ -2953,6 +3191,12 @@ static struct clk_regmap *gcc_ipq806x_clks[] = { [PLL9] = &hfpll0.clkr, [PLL10] = &hfpll1.clkr, [PLL12] = &hfpll_l2.clkr, + [CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr, + [CE5_A_CLK] = &ce5_a_clk.clkr, + [CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr, + [CE5_H_CLK] = &ce5_h_clk.clkr, + [CE5_CORE_CLK_SRC] = &ce5_core_src.clkr, + [CE5_CORE_CLK] = &ce5_core_clk.clkr, }; static const struct qcom_reset_map gcc_ipq806x_resets[] = { From patchwork Tue Jan 18 00:44:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 533682 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8C06C433FE for ; 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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id 24sm4892127ejg.47.2022.01.17.17.02.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jan 2022 17:02:03 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 12/14] dt-bindings: reset: add ipq8064 ce5 resets Date: Tue, 18 Jan 2022 01:44:32 +0100 Message-Id: <20220118004434.17095-13-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220118004434.17095-1-ansuelsmth@gmail.com> References: <20220118004434.17095-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add ipq8064 ce5 resets needed for CryptoEngine gcc driver. Signed-off-by: Ansuel Smith --- include/dt-bindings/reset/qcom,gcc-ipq806x.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/dt-bindings/reset/qcom,gcc-ipq806x.h b/include/dt-bindings/reset/qcom,gcc-ipq806x.h index 26b6f9200620..020c9cf18751 100644 --- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h +++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h @@ -163,5 +163,10 @@ #define NSS_CAL_PRBS_RST_N_RESET 154 #define NSS_LCKDT_RST_N_RESET 155 #define NSS_SRDS_N_RESET 156 +#define CRYPTO_ENG1_RESET 157 +#define CRYPTO_ENG2_RESET 158 +#define CRYPTO_ENG3_RESET 159 +#define CRYPTO_ENG4_RESET 160 +#define CRYPTO_AHB_RESET 161 #endif From patchwork Tue Jan 18 00:44:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 532929 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 158B0C433F5 for ; Tue, 18 Jan 2022 01:02:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244221AbiARBCU (ORCPT ); Mon, 17 Jan 2022 20:02:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244097AbiARBCH (ORCPT ); Mon, 17 Jan 2022 20:02:07 -0500 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C11CDC061574; Mon, 17 Jan 2022 17:02:06 -0800 (PST) Received: by mail-ed1-x530.google.com with SMTP id m4so72502025edb.10; Mon, 17 Jan 2022 17:02:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=wfWF7NDErASivxj8coRKrOvkTRbtA/JEwudCiRXB7sw=; b=gJeeDhfI9NgKF4swBHQ5YHzu4vJe66KrAxl7Ifoj3w9/bD3d/KOHwWjiBK2JXT/sB1 jZm9FDEeViMtHqh4XwVy2/MUb+jhcoA4ZkL8mINGaNfvNYhhJAxESHl+QdiHF4uN9EMD I31cM6BQDaVdTzfHwTrAMN+7ZPBx+F5aVkIYV2PPQzv8bkrk2jnjU19KgMCG7wuN9CcH foDBDiCz2g01H3W45j3yyJdZTPhWkQyjqYX8lT11+82wdQ7IPrUyEun+HEa0/UlhSPq8 Wh3bHb6oVkWo2u4THxLCbDTWRuOcRuUgPQ6sCPOeGi7U1cXOvgIIxa+9obaFZ4IfvPz8 ZUeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wfWF7NDErASivxj8coRKrOvkTRbtA/JEwudCiRXB7sw=; b=FL7Y8cFy2pFS7tcAPpwtoGAi3+meCHJBUeO6qB+YfM6+GxSCNwond4BMbUSQebb71n b6joMCZGnOMeAH2D1jNpO+8R2KtraDeDBK/OXPpTz5JjNqRzMck/Q1XAs/8fRkFLEGel gLXQ4AxzETHHQjgVYs0BfNdtHfQ4UO2+viEVsUvAHIV3nabHAGkxjuaATr+m9E8XaBv/ lr4jUHEqGvXDJIqJ/oZtthvxi344FWPVGVECvgKmFJlBO2o4Ip17sHT8TUscnDMcFfgw HaGh/iM8z43PFV56SH15A7feMJjksuZACo9aYqgA3mpp51Gk0JOaSsSaNJyCe5BDxDCp nnTQ== X-Gm-Message-State: AOAM530tBlT6ur4hLR6evp7+5R7Ixb5ME2ir0Q4Vph0DieE936Q9OTw1 lmS4T+CNb2+raIzUYkJkaww= X-Google-Smtp-Source: ABdhPJyvfKYO/3BoNpEfSP+7U1xiuEgEyE24wlSi8o03TL8IVJWsaGLTfrDpk3cAlV6hZr1u5ditgQ== X-Received: by 2002:a17:906:58cf:: with SMTP id e15mr90480ejs.439.1642467725281; Mon, 17 Jan 2022 17:02:05 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id 24sm4892127ejg.47.2022.01.17.17.02.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jan 2022 17:02:04 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 13/14] drivers: clk: qcom: gcc-ipq806x: add CryptoEngine resets Date: Tue, 18 Jan 2022 01:44:33 +0100 Message-Id: <20220118004434.17095-14-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220118004434.17095-1-ansuelsmth@gmail.com> References: <20220118004434.17095-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add missing CryptoEngine resets. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 46d0fe511868..201c967fc74d 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -3328,6 +3328,11 @@ static const struct qcom_reset_map gcc_ipq806x_resets[] = { [GMAC_CORE3_RESET] = { 0x3cfc, 0 }, [GMAC_CORE4_RESET] = { 0x3d1c, 0 }, [GMAC_AHB_RESET] = { 0x3e24, 0 }, + [CRYPTO_ENG1_RESET] = { 0x3e00, 0}, + [CRYPTO_ENG2_RESET] = { 0x3e04, 0}, + [CRYPTO_ENG3_RESET] = { 0x3e08, 0}, + [CRYPTO_ENG4_RESET] = { 0x3e0c, 0}, + [CRYPTO_AHB_RESET] = { 0x3e10, 0}, [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 }, [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 }, [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 }, From patchwork Tue Jan 18 00:44:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 533681 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88C34C4332F for ; Tue, 18 Jan 2022 01:02:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244263AbiARBCc (ORCPT ); Mon, 17 Jan 2022 20:02:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244112AbiARBCI (ORCPT ); Mon, 17 Jan 2022 20:02:08 -0500 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D54D1C06161C; Mon, 17 Jan 2022 17:02:07 -0800 (PST) Received: by mail-ed1-x52d.google.com with SMTP id c71so72639749edf.6; Mon, 17 Jan 2022 17:02:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=70y9nP+1TJuyoQVHWKHYrgk62/1kbAozVgHhQoGQnWU=; b=Ua355Juvb+5cWQs7Gu/XWJattoD8KtPGSZKPITsu8/pwo6tOdqGkRg78iwsyMaR/3Q 5Nl6JWabCVo4Ysyl4qcpLQddwq2FtSSNTl0IEWSKUUvxyCCU1LzPPFdMwEScczc0cTSx eLyThB2vMDUN+WPoE8SgUPs+Ni55KM+GYapZ7K3IptXwFqs6XYx0qxZCO1au/4ckOW0n ziUnL2ARYZyRDq/g1voz3IMBh3mHi7G1+xeK3Is0K96VpYeDq9Z6EC2lAXiWc/gIyD3c pWnd09mAyvDhmza6odhGBmhl9SJUovZXXAajqM0GQQSPNvFUgTjATRQvrVqIRjSBr5GT 8XnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=70y9nP+1TJuyoQVHWKHYrgk62/1kbAozVgHhQoGQnWU=; b=fpXvvVYjvLmG3CoWFQ5Mb7DRBEmKPvMJl+TMpqlmsDRrzN8yX848qH+W8qlpp4Q3r8 MYB2TdPcwKOrxvGCapFEmQOjQSsnk5MAkY1f3tWzE+g9PFy9Y1t2+MVvuCsn8oW43bMh bo5LafQlurhHiovmgDq7TIm21LZwMoK04EJZ2pSrBhSD5NUNud3u/QF00FgdS+kdxKM5 buwUCi8igHhq7Ota8nb6TnEQq7yqKVKSqhvglNH5wQt9IWC8awXgbiWMXsniwtbX/Gyb Rew1ozZnwiC3Tvwoi0Sd5sfEs5ZVL9A4eOd74LcACLFqYc/VizkwJAd6ajYYpn886fab mqYA== X-Gm-Message-State: AOAM531zAJGH8FJi/qr4UxEPV5zuKt23ckJIsmGeD/whOXLnwquZMjWr 1CC3eIHt5YVGv8WVDa88L8814WOCkyQ= X-Google-Smtp-Source: ABdhPJw587JtgnQlOOPt5ApE1N1/wBG4hMb2MOqEUk6zLxEKAgsPBKF5evubIxpeZlL3w/Qnn8/1CA== X-Received: by 2002:a05:6402:518d:: with SMTP id q13mr23364662edd.377.1642467726331; Mon, 17 Jan 2022 17:02:06 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id 24sm4892127ejg.47.2022.01.17.17.02.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jan 2022 17:02:06 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 14/14] ARM: dts: qcom: Add syscon and cxo/pxo clock to gcc node for ipq8064 Date: Tue, 18 Jan 2022 01:44:34 +0100 Message-Id: <20220118004434.17095-15-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220118004434.17095-1-ansuelsmth@gmail.com> References: <20220118004434.17095-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add syscon compatible required for tsens driver to correctly probe driver and access the reg. Also add cxo and pxo tag and declare them as gcc clock now requires them for the ipq8064 gcc driver that has now been modernized. Signed-off-by: Ansuel Smith --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 11481313bdb6..5524a68cf3d1 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -298,13 +298,13 @@ smem: smem@41000000 { }; clocks { - cxo_board { + cxo_board: cxo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; - pxo_board { + pxo_board: pxo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; @@ -736,7 +736,9 @@ tsens_calib_backup: calib_backup@410 { }; gcc: clock-controller@900000 { - compatible = "qcom,gcc-ipq8064"; + compatible = "qcom,gcc-ipq8064", "syscon"; + clocks = <&pxo_board>, <&cxo_board>; + clock-names = "pxo", "cxo"; reg = <0x00900000 0x4000>; #clock-cells = <1>; #reset-cells = <1>;