From patchwork Tue Jan 18 00:44:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 533010 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5721EC433EF for ; Tue, 18 Jan 2022 01:02:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243894AbiARBCA (ORCPT ); Mon, 17 Jan 2022 20:02:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39062 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238683AbiARBBz (ORCPT ); Mon, 17 Jan 2022 20:01:55 -0500 Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68E36C061574; Mon, 17 Jan 2022 17:01:55 -0800 (PST) Received: by mail-ed1-x531.google.com with SMTP id q25so72652355edb.2; Mon, 17 Jan 2022 17:01:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=wlPGztyCglYvRuLUlqRz5tHJBkS2fLA0AOcHKOEzeZA=; b=Tg5/HL6RuF0u+pFSo8jDHr92zFaEckK5slFfbo/rjYssifQc4WCkWQAI74QeC3kyCJ tz7d2QiqQUYgJvP59Xn8s1+xp5N/iLyXZqLpqa5F//IwwElr5g3zunEK7VJio9kFc+aE q2s6HVdx0U8ouT7L/m8gWS36vQGMMPgIK7W7hVLCzJdZiFYoG3xHkI/sEajqtGUmxBUC 4USoyH6455GDleXLcnDRUyX+wBU/usE2sXynmAXmdBL3H2s/dXE4c77/QuBW7jdVeqCw OEwOIzvGgul71yQj7YH6JhM/DWnSLgzijr9kRBIYTCP/KRtmt14rRmCmCcPJVZHnfp71 Q+ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wlPGztyCglYvRuLUlqRz5tHJBkS2fLA0AOcHKOEzeZA=; b=GpbAaKOQdkw4sAQ0TF6RGZczeneIYbFgPGBaG9JBk99Ws/Wox3OeMFcJwYvYveXy61 yrr0EtdrAlYj5zuU7fuyHuNBgzAdQMtyuR3X2MhpEYZh2ym1Z84Ie2v+m0BFSgZS01tg WQ+riAVNA3XO34U+VdTx+TZYen4cx1LocbCc5JuU1e6NfSgHV/6dJ4sR6tCbVfzYwVu5 dhFuE4Pbk0HadluUTEZKDj/+hGY7YyYhEvT3UCT1LzQA9SkNICZ5VN4tC+M9nYhKPc0n OE9XMn7P+X2kLX4Klq2Qb4T0e1fard2NemDvgrn0huZR2hxf9RBMrPWIL2hCz0MgCe3U CxKg== X-Gm-Message-State: AOAM533F9BVLsZ9qMMCF8rzTfmpd5zxi0p0GLEsgGzZ2WisH84cutL0m B9dNvsYMmDYAG9ZsuOgAOVNM/EKVG0w= X-Google-Smtp-Source: ABdhPJwhHv1mJNexDLPa1Tz9S1m32K+gy7UG3OJlmciHbMZcUHiclw9c49rRU7mHOqe42QUcFJgrgg== X-Received: by 2002:a17:907:2da3:: with SMTP id gt35mr18833052ejc.493.1642467713880; Mon, 17 Jan 2022 17:01:53 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id 24sm4892127ejg.47.2022.01.17.17.01.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jan 2022 17:01:53 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/14] drivers: clk: qcom: gcc-ipq806x: fix wrong naming for gcc_pxo_pll8_pll0 Date: Tue, 18 Jan 2022 01:44:22 +0100 Message-Id: <20220118004434.17095-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220118004434.17095-1-ansuelsmth@gmail.com> References: <20220118004434.17095-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Parent gcc_pxo_pll8_pll0 had the parent definition and parent map swapped. Fix this naming error. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index d6b7adb4be38..34cddf461dba 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -291,13 +291,13 @@ static const char * const gcc_pxo_pll3[] = { "pll3", }; -static const struct parent_map gcc_pxo_pll8_pll0[] = { +static const struct parent_map gcc_pxo_pll8_pll0_map[] = { { P_PXO, 0 }, { P_PLL8, 3 }, { P_PLL0, 2 } }; -static const char * const gcc_pxo_pll8_pll0_map[] = { +static const char * const gcc_pxo_pll8_pll0[] = { "pxo", "pll8_vote", "pll0_vote", @@ -1993,7 +1993,7 @@ static struct clk_rcg usb30_master_clk_src = { }, .s = { .src_sel_shift = 0, - .parent_map = gcc_pxo_pll8_pll0, + .parent_map = gcc_pxo_pll8_pll0_map, }, .freq_tbl = clk_tbl_usb30_master, .clkr = { @@ -2001,7 +2001,7 @@ static struct clk_rcg usb30_master_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb30_master_ref_src", - .parent_names = gcc_pxo_pll8_pll0_map, + .parent_names = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2063,7 +2063,7 @@ static struct clk_rcg usb30_utmi_clk = { }, .s = { .src_sel_shift = 0, - .parent_map = gcc_pxo_pll8_pll0, + .parent_map = gcc_pxo_pll8_pll0_map, }, .freq_tbl = clk_tbl_usb30_utmi, .clkr = { @@ -2071,7 +2071,7 @@ static struct clk_rcg usb30_utmi_clk = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb30_utmi_clk", - .parent_names = gcc_pxo_pll8_pll0_map, + .parent_names = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2133,7 +2133,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { }, .s = { .src_sel_shift = 0, - .parent_map = gcc_pxo_pll8_pll0, + .parent_map = gcc_pxo_pll8_pll0_map, }, .freq_tbl = clk_tbl_usb, .clkr = { @@ -2141,7 +2141,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_src", - .parent_names = gcc_pxo_pll8_pll0_map, + .parent_names = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2197,7 +2197,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { }, .s = { .src_sel_shift = 0, - .parent_map = gcc_pxo_pll8_pll0, + .parent_map = gcc_pxo_pll8_pll0_map, }, .freq_tbl = clk_tbl_usb, .clkr = { @@ -2205,7 +2205,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_fs1_xcvr_src", - .parent_names = gcc_pxo_pll8_pll0_map, + .parent_names = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, From patchwork Tue Jan 18 00:44:23 2022 Content-Type: text/plain; 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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id 24sm4892127ejg.47.2022.01.17.17.01.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jan 2022 17:01:54 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/14] drivers: clk: qcom: gcc-ipq806x: convert parent_names to parent_data Date: Tue, 18 Jan 2022 01:44:23 +0100 Message-Id: <20220118004434.17095-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220118004434.17095-1-ansuelsmth@gmail.com> References: <20220118004434.17095-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert parent_names to parent_data to modernize the driver. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 300 ++++++++++++++++++++------------- 1 file changed, 187 insertions(+), 113 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 34cddf461dba..cbacd56f52d4 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -35,7 +35,9 @@ static struct clk_pll pll0 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll0", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pxo", + }, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -46,7 +48,9 @@ static struct clk_regmap pll0_vote = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "pll0_vote", - .parent_names = (const char *[]){ "pll0" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &pll0.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -62,7 +66,9 @@ static struct clk_pll pll3 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll3", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pxo", + }, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -89,7 +95,9 @@ static struct clk_pll pll8 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll8", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pxo", + }, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -100,7 +108,9 @@ static struct clk_regmap pll8_vote = { .enable_mask = BIT(8), .hw.init = &(struct clk_init_data){ .name = "pll8_vote", - .parent_names = (const char *[]){ "pll8" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &pll8.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -123,7 +133,9 @@ static struct hfpll_data hfpll0_data = { static struct clk_hfpll hfpll0 = { .d = &hfpll0_data, .clkr.hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "pxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pxo", + }, .num_parents = 1, .name = "hfpll0", .ops = &clk_ops_hfpll, @@ -149,7 +161,9 @@ static struct hfpll_data hfpll1_data = { static struct clk_hfpll hfpll1 = { .d = &hfpll1_data, .clkr.hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "pxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pxo", + }, .num_parents = 1, .name = "hfpll1", .ops = &clk_ops_hfpll, @@ -175,7 +189,9 @@ static struct hfpll_data hfpll_l2_data = { static struct clk_hfpll hfpll_l2 = { .d = &hfpll_l2_data, .clkr.hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "pxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pxo", + }, .num_parents = 1, .name = "hfpll_l2", .ops = &clk_ops_hfpll, @@ -194,7 +210,9 @@ static struct clk_pll pll14 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll14", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pxo", + }, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -205,7 +223,9 @@ static struct clk_regmap pll14_vote = { .enable_mask = BIT(14), .hw.init = &(struct clk_init_data){ .name = "pll14_vote", - .parent_names = (const char *[]){ "pll14" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &pll14.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -238,7 +258,9 @@ static struct clk_pll pll18 = { .freq_tbl = pll18_freq_tbl, .clkr.hw.init = &(struct clk_init_data){ .name = "pll18", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pxo", + }, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -259,9 +281,9 @@ static const struct parent_map gcc_pxo_pll8_map[] = { { P_PLL8, 3 } }; -static const char * const gcc_pxo_pll8[] = { - "pxo", - "pll8_vote", +static const struct clk_parent_data gcc_pxo_pll8[] = { + { .fw_name = "pxo" }, + { .hw = &pll8_vote.hw }, }; static const struct parent_map gcc_pxo_pll8_cxo_map[] = { @@ -270,10 +292,10 @@ static const struct parent_map gcc_pxo_pll8_cxo_map[] = { { P_CXO, 5 } }; -static const char * const gcc_pxo_pll8_cxo[] = { - "pxo", - "pll8_vote", - "cxo", +static const struct clk_parent_data gcc_pxo_pll8_cxo[] = { + { .fw_name = "pxo" }, + { .hw = &pll8_vote.hw }, + { .fw_name = "cxo" }, }; static const struct parent_map gcc_pxo_pll3_map[] = { @@ -286,9 +308,9 @@ static const struct parent_map gcc_pxo_pll3_sata_map[] = { { P_PLL3, 6 } }; -static const char * const gcc_pxo_pll3[] = { - "pxo", - "pll3", +static const struct clk_parent_data gcc_pxo_pll3[] = { + { .fw_name = "pxo" }, + { .hw = &pll3.clkr.hw }, }; static const struct parent_map gcc_pxo_pll8_pll0_map[] = { @@ -297,10 +319,10 @@ static const struct parent_map gcc_pxo_pll8_pll0_map[] = { { P_PLL0, 2 } }; -static const char * const gcc_pxo_pll8_pll0[] = { - "pxo", - "pll8_vote", - "pll0_vote", +static const struct clk_parent_data gcc_pxo_pll8_pll0[] = { + { .fw_name = "pxo" }, + { .hw = &pll8_vote.hw }, + { .hw = &pll0_vote.hw }, }; static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = { @@ -311,12 +333,12 @@ static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = { { P_PLL18, 1 } }; -static const char * const gcc_pxo_pll8_pll14_pll18_pll0[] = { - "pxo", - "pll8_vote", - "pll0_vote", - "pll14", - "pll18", +static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = { + { .fw_name = "pxo" }, + { .hw = &pll8_vote.hw }, + { .hw = &pll0_vote.hw }, + { .hw = &pll14.clkr.hw }, + { .hw = &pll18.clkr.hw }, }; static struct freq_tbl clk_tbl_gsbi_uart[] = { @@ -362,7 +384,7 @@ static struct clk_rcg gsbi1_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -378,8 +400,8 @@ static struct clk_branch gsbi1_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_clk", - .parent_names = (const char *[]){ - "gsbi1_uart_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gsbi1_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -413,7 +435,7 @@ static struct clk_rcg gsbi2_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -429,8 +451,8 @@ static struct clk_branch gsbi2_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_clk", - .parent_names = (const char *[]){ - "gsbi2_uart_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gsbi2_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -464,7 +486,7 @@ static struct clk_rcg gsbi4_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -480,8 +502,8 @@ static struct clk_branch gsbi4_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_clk", - .parent_names = (const char *[]){ - "gsbi4_uart_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gsbi4_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -515,7 +537,7 @@ static struct clk_rcg gsbi5_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -531,8 +553,8 @@ static struct clk_branch gsbi5_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_clk", - .parent_names = (const char *[]){ - "gsbi5_uart_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gsbi5_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -566,7 +588,7 @@ static struct clk_rcg gsbi6_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi6_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -582,8 +604,8 @@ static struct clk_branch gsbi6_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi6_uart_clk", - .parent_names = (const char *[]){ - "gsbi6_uart_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gsbi6_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -617,7 +639,7 @@ static struct clk_rcg gsbi7_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi7_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -633,8 +655,8 @@ static struct clk_branch gsbi7_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi7_uart_clk", - .parent_names = (const char *[]){ - "gsbi7_uart_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gsbi7_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -681,7 +703,7 @@ static struct clk_rcg gsbi1_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -697,7 +719,9 @@ static struct clk_branch gsbi1_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_clk", - .parent_names = (const char *[]){ "gsbi1_qup_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &gsbi1_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -730,7 +754,7 @@ static struct clk_rcg gsbi2_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -746,7 +770,9 @@ static struct clk_branch gsbi2_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_clk", - .parent_names = (const char *[]){ "gsbi2_qup_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &gsbi2_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -779,7 +805,7 @@ static struct clk_rcg gsbi4_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -795,7 +821,9 @@ static struct clk_branch gsbi4_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_clk", - .parent_names = (const char *[]){ "gsbi4_qup_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &gsbi4_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -828,7 +856,7 @@ static struct clk_rcg gsbi5_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -844,7 +872,9 @@ static struct clk_branch gsbi5_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_clk", - .parent_names = (const char *[]){ "gsbi5_qup_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &gsbi5_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -877,7 +907,7 @@ static struct clk_rcg gsbi6_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi6_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -893,7 +923,9 @@ static struct clk_branch gsbi6_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi6_qup_clk", - .parent_names = (const char *[]){ "gsbi6_qup_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &gsbi6_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -926,7 +958,7 @@ static struct clk_rcg gsbi7_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi7_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -942,7 +974,9 @@ static struct clk_branch gsbi7_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi7_qup_clk", - .parent_names = (const char *[]){ "gsbi7_qup_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &gsbi7_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1076,7 +1110,7 @@ static struct clk_rcg gp0_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gp0_src", - .parent_names = gcc_pxo_pll8_cxo, + .parent_data = gcc_pxo_pll8_cxo, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -1092,7 +1126,9 @@ static struct clk_branch gp0_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp0_clk", - .parent_names = (const char *[]){ "gp0_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &gp0_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1125,7 +1161,7 @@ static struct clk_rcg gp1_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gp1_src", - .parent_names = gcc_pxo_pll8_cxo, + .parent_data = gcc_pxo_pll8_cxo, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1141,7 +1177,9 @@ static struct clk_branch gp1_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp1_clk", - .parent_names = (const char *[]){ "gp1_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &gp1_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1174,7 +1212,7 @@ static struct clk_rcg gp2_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gp2_src", - .parent_names = gcc_pxo_pll8_cxo, + .parent_data = gcc_pxo_pll8_cxo, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1190,7 +1228,9 @@ static struct clk_branch gp2_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp2_clk", - .parent_names = (const char *[]){ "gp2_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &gp2_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1228,7 +1268,7 @@ static struct clk_rcg prng_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "prng_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, }, @@ -1244,7 +1284,9 @@ static struct clk_branch prng_clk = { .enable_mask = BIT(10), .hw.init = &(struct clk_init_data){ .name = "prng_clk", - .parent_names = (const char *[]){ "prng_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &prng_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, }, @@ -1290,7 +1332,7 @@ static struct clk_rcg sdc1_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "sdc1_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, }, @@ -1305,7 +1347,9 @@ static struct clk_branch sdc1_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "sdc1_clk", - .parent_names = (const char *[]){ "sdc1_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &sdc1_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1338,7 +1382,7 @@ static struct clk_rcg sdc3_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "sdc3_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, }, @@ -1353,7 +1397,9 @@ static struct clk_branch sdc3_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "sdc3_clk", - .parent_names = (const char *[]){ "sdc3_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &sdc3_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1421,7 +1467,7 @@ static struct clk_rcg tsif_ref_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "tsif_ref_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, }, @@ -1436,7 +1482,9 @@ static struct clk_branch tsif_ref_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "tsif_ref_clk", - .parent_names = (const char *[]){ "tsif_ref_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &tsif_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1583,7 +1631,7 @@ static struct clk_rcg pcie_ref_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "pcie_ref_src", - .parent_names = gcc_pxo_pll3, + .parent_data = gcc_pxo_pll3, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1599,7 +1647,9 @@ static struct clk_branch pcie_ref_src_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "pcie_ref_src_clk", - .parent_names = (const char *[]){ "pcie_ref_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &pcie_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1675,7 +1725,7 @@ static struct clk_rcg pcie1_ref_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "pcie1_ref_src", - .parent_names = gcc_pxo_pll3, + .parent_data = gcc_pxo_pll3, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1691,7 +1741,9 @@ static struct clk_branch pcie1_ref_src_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "pcie1_ref_src_clk", - .parent_names = (const char *[]){ "pcie1_ref_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &pcie1_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1767,7 +1819,7 @@ static struct clk_rcg pcie2_ref_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "pcie2_ref_src", - .parent_names = gcc_pxo_pll3, + .parent_data = gcc_pxo_pll3, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1783,7 +1835,9 @@ static struct clk_branch pcie2_ref_src_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "pcie2_ref_src_clk", - .parent_names = (const char *[]){ "pcie2_ref_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &pcie2_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1864,7 +1918,7 @@ static struct clk_rcg sata_ref_src = { .enable_mask = BIT(7), .hw.init = &(struct clk_init_data){ .name = "sata_ref_src", - .parent_names = gcc_pxo_pll3, + .parent_data = gcc_pxo_pll3, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1880,7 +1934,9 @@ static struct clk_branch sata_rxoob_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "sata_rxoob_clk", - .parent_names = (const char *[]){ "sata_ref_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &sata_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1896,7 +1952,9 @@ static struct clk_branch sata_pmalive_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "sata_pmalive_clk", - .parent_names = (const char *[]){ "sata_ref_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &sata_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1912,7 +1970,9 @@ static struct clk_branch sata_phy_ref_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "sata_phy_ref_clk", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pxo", + }, .num_parents = 1, .ops = &clk_branch_ops, }, @@ -2001,7 +2061,7 @@ static struct clk_rcg usb30_master_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb30_master_ref_src", - .parent_names = gcc_pxo_pll8_pll0, + .parent_data = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2017,7 +2077,9 @@ static struct clk_branch usb30_0_branch_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb30_0_branch_clk", - .parent_names = (const char *[]){ "usb30_master_ref_src", }, + .parent_data = &(const struct clk_parent_data){ + .hw = &usb30_master_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2033,7 +2095,9 @@ static struct clk_branch usb30_1_branch_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb30_1_branch_clk", - .parent_names = (const char *[]){ "usb30_master_ref_src", }, + .parent_data = &(const struct clk_parent_data){ + .hw = &usb30_master_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2071,7 +2135,7 @@ static struct clk_rcg usb30_utmi_clk = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb30_utmi_clk", - .parent_names = gcc_pxo_pll8_pll0, + .parent_data = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2087,7 +2151,9 @@ static struct clk_branch usb30_0_utmi_clk_ctl = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb30_0_utmi_clk_ctl", - .parent_names = (const char *[]){ "usb30_utmi_clk", }, + .parent_data = &(const struct clk_parent_data){ + .hw = &usb30_utmi_clk.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2103,7 +2169,9 @@ static struct clk_branch usb30_1_utmi_clk_ctl = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb30_1_utmi_clk_ctl", - .parent_names = (const char *[]){ "usb30_utmi_clk", }, + .parent_data = &(const struct clk_parent_data){ + .hw = &usb30_utmi_clk.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2141,7 +2209,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_src", - .parent_names = gcc_pxo_pll8_pll0, + .parent_data = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2157,7 +2225,9 @@ static struct clk_branch usb_hs1_xcvr_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_clk", - .parent_names = (const char *[]){ "usb_hs1_xcvr_src" }, + .parent_data = &(const struct clk_parent_data){ + .hw = &usb_hs1_xcvr_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2205,7 +2275,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_fs1_xcvr_src", - .parent_names = gcc_pxo_pll8_pll0, + .parent_data = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2221,7 +2291,9 @@ static struct clk_branch usb_fs1_xcvr_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "usb_fs1_xcvr_clk", - .parent_names = (const char *[]){ "usb_fs1_xcvr_src", }, + .parent_data = &(const struct clk_parent_data){ + .hw = &usb_fs1_xcvr_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2237,7 +2309,9 @@ static struct clk_branch usb_fs1_sys_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb_fs1_sys_clk", - .parent_names = (const char *[]){ "usb_fs1_xcvr_src", }, + .parent_data = &(const struct clk_parent_data){ + .hw = &usb_fs1_xcvr_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2337,7 +2411,7 @@ static struct clk_dyn_rcg gmac_core1_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gmac_core1_src", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, }, @@ -2354,8 +2428,8 @@ static struct clk_branch gmac_core1_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gmac_core1_clk", - .parent_names = (const char *[]){ - "gmac_core1_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gmac_core1_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2409,7 +2483,7 @@ static struct clk_dyn_rcg gmac_core2_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gmac_core2_src", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, }, @@ -2426,8 +2500,8 @@ static struct clk_branch gmac_core2_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gmac_core2_clk", - .parent_names = (const char *[]){ - "gmac_core2_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gmac_core2_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2481,7 +2555,7 @@ static struct clk_dyn_rcg gmac_core3_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gmac_core3_src", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, }, @@ -2498,8 +2572,8 @@ static struct clk_branch gmac_core3_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gmac_core3_clk", - .parent_names = (const char *[]){ - "gmac_core3_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gmac_core3_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2553,7 +2627,7 @@ static struct clk_dyn_rcg gmac_core4_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gmac_core4_src", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, }, @@ -2570,8 +2644,8 @@ static struct clk_branch gmac_core4_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gmac_core4_clk", - .parent_names = (const char *[]){ - "gmac_core4_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gmac_core4_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2613,7 +2687,7 @@ static struct clk_dyn_rcg nss_tcm_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "nss_tcm_src", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, }, @@ -2628,8 +2702,8 @@ static struct clk_branch nss_tcm_clk = { .enable_mask = BIT(6) | BIT(4), .hw.init = &(struct clk_init_data){ .name = "nss_tcm_clk", - .parent_names = (const char *[]){ - "nss_tcm_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &nss_tcm_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2691,7 +2765,7 @@ static struct clk_dyn_rcg ubi32_core1_src_clk = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "ubi32_core1_src_clk", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, @@ -2744,7 +2818,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "ubi32_core2_src_clk", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, From patchwork Tue Jan 18 00:44:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 533005 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F40DEC4707F for ; Tue, 18 Jan 2022 01:02:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244162AbiARBCR (ORCPT ); Mon, 17 Jan 2022 20:02:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229836AbiARBCA (ORCPT ); Mon, 17 Jan 2022 20:02:00 -0500 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3261C061574; Mon, 17 Jan 2022 17:01:59 -0800 (PST) Received: by mail-ed1-x52f.google.com with SMTP id b13so72861440edn.0; Mon, 17 Jan 2022 17:01:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=X3rbRq5KfKbeBC7Dkw4uo5NOk4Ukps/dmiHuiNy8NQc=; b=Sz/r6tel48hi+gCzCaVmU6ApnbpTRvGnhkCT3ijgn9gjmAj9dLy3C5/KvbN4/ImVlj oU4w/JYu7HgFQh6Jjy58QNX537t/7p7mvHF6oTyTHmaLiemuZYlJ/gYrXR7o4q4ShRrl 1rTxch2FKD1ahFrPNQszh5fMr/6jEHbmRAuJzbv1svQcLVmbYXAzEOp6gGIWX8+PQg+j J75U5KP9qculY8DLdCTYnKZRppSrdBEfs2e0iN3a+rky5+JKxE+Yz3EQLFjKEJpRx801 6EJ1+GNrCgiDLiq5Js61SiXk4YERnRhEzVNbBn7GXXgXV8mcqFLsSvRgVc+KR3g5JsCO 4i/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X3rbRq5KfKbeBC7Dkw4uo5NOk4Ukps/dmiHuiNy8NQc=; b=6H/VCnSQuSZnTqqx1DICpaq0qkTG5tVlJzrd8Oy+1xZckoYjxE6XCkWusqpcg6M56W bUlCd2IecAVciB6hBO9Lq9kuz8aTJgkHumLRMAOwF67hE6LhCO3HbMrelaauFzCu7dhE DFW509Cnas9+B0P6v0cThL37MFy2KoSFjv6rP58t1s2RIO00msOnl+gVIVJbYHT4spoq vjmQmBskCsE84fwOIZcmo6sz8AasoDRBNCD6W9cmChlK7A9nP/2WhMQ2mWV61avcMuWu w3uf3w90soDisr1+0z83DIBv/HbTUyNWJkEU1JIuKAtdJQdQqMmM55S5C0f9Phu6zsQf OYXA== X-Gm-Message-State: AOAM532dP1vPxEqnvcoblcS5LFPGdnVJ0fvaFl4z58EtSb1upQqvy6Jp 7zgsiAk0K74SWiXqOXDwYLc= X-Google-Smtp-Source: ABdhPJyAzXaFCJe40ztl7YCSxcfx3Fc8bwM/Ywi+aUpQDYUrDNaNxz7GVz+hdQQ4O21xOC/AI1W5rA== X-Received: by 2002:a17:906:e43:: with SMTP id q3mr12859971eji.92.1642467718082; Mon, 17 Jan 2022 17:01:58 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id 24sm4892127ejg.47.2022.01.17.17.01.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jan 2022 17:01:57 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 06/14] drivers: clk: qcom: gcc-ipq806x: use parent_hws where possible Date: Tue, 18 Jan 2022 01:44:26 +0100 Message-Id: <20220118004434.17095-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220118004434.17095-1-ansuelsmth@gmail.com> References: <20220118004434.17095-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Use parent_hws instead of generic parent_data when parents all the parent are defined in the ipq806x gcc driver. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 156 ++++++++++++++++----------------- 1 file changed, 78 insertions(+), 78 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 383494280e3e..ce5654d3e937 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -48,8 +48,8 @@ static struct clk_regmap pll0_vote = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "pll0_vote", - .parent_data = &(const struct clk_parent_data){ - .hw = &pll0.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &pll0.clkr.hw, }, .num_parents = 1, .ops = &clk_pll_vote_ops, @@ -108,8 +108,8 @@ static struct clk_regmap pll8_vote = { .enable_mask = BIT(8), .hw.init = &(struct clk_init_data){ .name = "pll8_vote", - .parent_data = &(const struct clk_parent_data){ - .hw = &pll8.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &pll8.clkr.hw, }, .num_parents = 1, .ops = &clk_pll_vote_ops, @@ -223,8 +223,8 @@ static struct clk_regmap pll14_vote = { .enable_mask = BIT(14), .hw.init = &(struct clk_init_data){ .name = "pll14_vote", - .parent_data = &(const struct clk_parent_data){ - .hw = &pll14.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &pll14.clkr.hw, }, .num_parents = 1, .ops = &clk_pll_vote_ops, @@ -400,8 +400,8 @@ static struct clk_branch gsbi1_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gsbi1_uart_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gsbi1_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -451,8 +451,8 @@ static struct clk_branch gsbi2_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gsbi2_uart_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gsbi2_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -502,8 +502,8 @@ static struct clk_branch gsbi4_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gsbi4_uart_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gsbi4_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -553,8 +553,8 @@ static struct clk_branch gsbi5_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gsbi5_uart_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gsbi5_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -604,8 +604,8 @@ static struct clk_branch gsbi6_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi6_uart_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gsbi6_uart_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gsbi6_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -655,8 +655,8 @@ static struct clk_branch gsbi7_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi7_uart_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gsbi7_uart_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gsbi7_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -719,8 +719,8 @@ static struct clk_branch gsbi1_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gsbi1_qup_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gsbi1_qup_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -770,8 +770,8 @@ static struct clk_branch gsbi2_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gsbi2_qup_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gsbi2_qup_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -821,8 +821,8 @@ static struct clk_branch gsbi4_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gsbi4_qup_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gsbi4_qup_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -872,8 +872,8 @@ static struct clk_branch gsbi5_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gsbi5_qup_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gsbi5_qup_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -923,8 +923,8 @@ static struct clk_branch gsbi6_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi6_qup_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gsbi6_qup_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gsbi6_qup_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -974,8 +974,8 @@ static struct clk_branch gsbi7_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi7_qup_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gsbi7_qup_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gsbi7_qup_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -1126,8 +1126,8 @@ static struct clk_branch gp0_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gp0_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gp0_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -1177,8 +1177,8 @@ static struct clk_branch gp1_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gp1_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gp1_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -1228,8 +1228,8 @@ static struct clk_branch gp2_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gp2_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gp2_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -1284,8 +1284,8 @@ static struct clk_branch prng_clk = { .enable_mask = BIT(10), .hw.init = &(struct clk_init_data){ .name = "prng_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &prng_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &prng_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -1347,8 +1347,8 @@ static struct clk_branch sdc1_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "sdc1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &sdc1_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &sdc1_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -1397,8 +1397,8 @@ static struct clk_branch sdc3_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "sdc3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &sdc3_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &sdc3_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -1482,8 +1482,8 @@ static struct clk_branch tsif_ref_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "tsif_ref_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &tsif_ref_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &tsif_ref_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -1647,8 +1647,8 @@ static struct clk_branch pcie_ref_src_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "pcie_ref_src_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &pcie_ref_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &pcie_ref_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -1741,8 +1741,8 @@ static struct clk_branch pcie1_ref_src_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "pcie1_ref_src_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &pcie1_ref_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &pcie1_ref_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -1835,8 +1835,8 @@ static struct clk_branch pcie2_ref_src_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "pcie2_ref_src_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &pcie2_ref_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &pcie2_ref_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -1934,8 +1934,8 @@ static struct clk_branch sata_rxoob_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "sata_rxoob_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &sata_ref_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &sata_ref_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -1952,8 +1952,8 @@ static struct clk_branch sata_pmalive_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "sata_pmalive_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &sata_ref_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &sata_ref_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2077,8 +2077,8 @@ static struct clk_branch usb30_0_branch_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb30_0_branch_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &usb30_master_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &usb30_master_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2095,8 +2095,8 @@ static struct clk_branch usb30_1_branch_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb30_1_branch_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &usb30_master_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &usb30_master_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2151,8 +2151,8 @@ static struct clk_branch usb30_0_utmi_clk_ctl = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb30_0_utmi_clk_ctl", - .parent_data = &(const struct clk_parent_data){ - .hw = &usb30_utmi_clk.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &usb30_utmi_clk.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2169,8 +2169,8 @@ static struct clk_branch usb30_1_utmi_clk_ctl = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb30_1_utmi_clk_ctl", - .parent_data = &(const struct clk_parent_data){ - .hw = &usb30_utmi_clk.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &usb30_utmi_clk.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2225,8 +2225,8 @@ static struct clk_branch usb_hs1_xcvr_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &usb_hs1_xcvr_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &usb_hs1_xcvr_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2291,8 +2291,8 @@ static struct clk_branch usb_fs1_xcvr_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "usb_fs1_xcvr_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &usb_fs1_xcvr_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &usb_fs1_xcvr_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2309,8 +2309,8 @@ static struct clk_branch usb_fs1_sys_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb_fs1_sys_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &usb_fs1_xcvr_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &usb_fs1_xcvr_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2428,8 +2428,8 @@ static struct clk_branch gmac_core1_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gmac_core1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gmac_core1_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gmac_core1_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2500,8 +2500,8 @@ static struct clk_branch gmac_core2_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gmac_core2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gmac_core2_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gmac_core2_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2572,8 +2572,8 @@ static struct clk_branch gmac_core3_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gmac_core3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gmac_core3_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gmac_core3_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2644,8 +2644,8 @@ static struct clk_branch gmac_core4_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gmac_core4_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gmac_core4_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gmac_core4_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2702,8 +2702,8 @@ static struct clk_branch nss_tcm_clk = { .enable_mask = BIT(6) | BIT(4), .hw.init = &(struct clk_init_data){ .name = "nss_tcm_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &nss_tcm_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &nss_tcm_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, From patchwork Tue Jan 18 00:44:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 533007 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0139C4332F for ; Tue, 18 Jan 2022 01:02:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244126AbiARBCO (ORCPT ); Mon, 17 Jan 2022 20:02:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39106 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243960AbiARBCD (ORCPT ); Mon, 17 Jan 2022 20:02:03 -0500 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94ADBC061401; Mon, 17 Jan 2022 17:02:01 -0800 (PST) Received: by mail-ed1-x52b.google.com with SMTP id m4so72501351edb.10; Mon, 17 Jan 2022 17:02:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=rCx/NWCn5wFgUlCns4gxP47CTM6P+IWicMwkRv5E1+s=; b=W00CEX5U3ssKB+oc/8MFhXvIomGoLhGg7yCosvBcOD6Wuyo4FD2JPS2OPMhwVBPqRO gePd2zjbvbNwkfgLtBLtS429rXGK5LIY5nY0Ax6HuCWC1o3Nf35o+GPm8OwNuxLXNq32 MgbR2hd5EPAtykP3e+plOIXTy/o3AGhMEVMqDm5H08jht+FGdfrrpdvXl/lHiZKoE4kw HhudslCY/IFNB6hsXLj5X1OiHXBmrXYNxobEcxmLzBD6q19j364ZNODKpcXscSa2JPZQ bWknZLbHEzu4g12kIog01MKBgVa8gUcc2TRiMkiGLwMrpUUH9LwaFPs7Jj7yFs7/KtjU FZsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rCx/NWCn5wFgUlCns4gxP47CTM6P+IWicMwkRv5E1+s=; b=qqequIVvWRn0QXoXNhTMdIOV31zGzOS8XD8M8NhCvk1SEVXlOyG1Z4RRt/Dziktxm8 vXz6JM+OmwMVllq4roCwuinNCwFD8bqRFEquQE1bWG2m26yI0MGT97tOsg0IOKS1xjMM GpD9FnL+WrLmwsiGinE3tA2aJ8sdS4d/imYLqBcLSXITs4ZDZ8fh7FALmLJCNp6i+lzj zuZK2bz4EW1ByKnyLWInjbdQZifm2/SEw6QupJG9Gy27th7FVzqZVqDghwyTfFzVxwOE rPXzGQKnw4jkp5o2tQUn/s79aBhCRlqhZl4OOY14q+04u9cSNmUCL94FeK9nIaspFC3O YTHw== X-Gm-Message-State: AOAM532ICZk+gWzHNccYbCcoI55ZfB7BJwBPPxV/cAiBvkiMkY6HyKId zWEerB0yKYOZ9XYQf8rAXUU= X-Google-Smtp-Source: ABdhPJwaLjuiJXYwOM+CpUiffY2l13ni9Tf460XnssKQ2McotB+4RV+MocFyft2g6cZHVr6s0BkoPA== X-Received: by 2002:a17:906:5fc2:: with SMTP id k2mr12334612ejv.472.1642467720128; Mon, 17 Jan 2022 17:02:00 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id 24sm4892127ejg.47.2022.01.17.17.01.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jan 2022 17:01:59 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/14] drivers: clk: qcom: gcc-ipq806x: add unusued flag for critical clock Date: Tue, 18 Jan 2022 01:44:28 +0100 Message-Id: <20220118004434.17095-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220118004434.17095-1-ansuelsmth@gmail.com> References: <20220118004434.17095-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some clocks are used by other devices present on the SoC. For example the gsbi4_h_clk is used by RPM and is if disabled cause the RPM to reject any regulator change command. These clock should never be disabled. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index d0c5441eb98e..7d1ddbbbc8ec 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -810,7 +810,7 @@ static struct clk_rcg gsbi4_qup_src = { .parent_data = gcc_pxo_pll8, .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, + .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, }, }, }; @@ -828,7 +828,7 @@ static struct clk_branch gsbi4_qup_clk = { }, .num_parents = 1, .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, }, }, }; @@ -912,7 +912,7 @@ static struct clk_rcg gsbi6_qup_src = { .parent_data = gcc_pxo_pll8, .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, + .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, }, }, }; @@ -981,7 +981,7 @@ static struct clk_branch gsbi7_qup_clk = { }, .num_parents = 1, .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, }, }, }; @@ -1027,6 +1027,7 @@ static struct clk_branch gsbi4_h_clk = { .hw.init = &(struct clk_init_data){ .name = "gsbi4_h_clk", .ops = &clk_branch_ops, + .flags = CLK_IGNORE_UNUSED, }, }, }; From patchwork Tue Jan 18 00:44:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 533006 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2541AC4167D for ; Tue, 18 Jan 2022 01:02:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244134AbiARBCP (ORCPT ); Mon, 17 Jan 2022 20:02:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39108 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243963AbiARBCD (ORCPT ); Mon, 17 Jan 2022 20:02:03 -0500 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FA01C061747; Mon, 17 Jan 2022 17:02:02 -0800 (PST) Received: by mail-ed1-x52c.google.com with SMTP id f21so15536288eds.11; Mon, 17 Jan 2022 17:02:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=lj9tyHKwn1pbX2A1jzsdupYAHEFENiH62KbSI1f1j2c=; b=bMr3MbKYmOjqfILlGPAynUEEC0XPgkyTNRhiWETQ7zHBC6yGjtIb5ptlFBJ/3U13Yi estKbbFawC+Fr23oxP7lxLCt8Cd7hIcjfMBo1cHZ3bNJXouk7wc9eUb3pR9rPcbu5BQk SSK0dSe2fWOwFe64WUD9BU0A3ZaXePA8gK+xX50IeZCrdu/i6wstB4UltEOZv6YHP12E seC6bG7DSQUV0hU+l/UgRf9jKGc5QGkYtXernKxDqaEYHBXpfeToGHk+wJkMgI1X/2HN Ln4eXG5Qq6hWFnOAoD9gJVLoHPtjslSz/jmuD10F/zDwiQwJPgE9w3UCHPdk7Mbxanje j46Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lj9tyHKwn1pbX2A1jzsdupYAHEFENiH62KbSI1f1j2c=; b=L+0aQ4L4huL3rWpg6G3tj2cBB1CpwTcSAgmyCoFSeg9iUl4K4daRvt/GFVC2anc0kP 5bSPXJB1V2+iDS2trklSdyucD25aVsym3bbtBUKN+wuR7cBWWKgLrMlnOcnik7RW2M9v LCiBLNiZ3wljE4CfJyRnKN0ynXTTccv8ighW3cmyB/BWJq9KRJE8dpU8fhrXN7eeLU0m DVrA17j30mFHYrkiBqxtGBvQlFPR756zv4geCBNUnRaFWVt1JvVT2JQUUYGb/uYZQ4nZ 0kjgCwmyNQfQOsfAdx+Zg4wzTfomh9r520kLMENLSCtESa4q61sxUZgDOWweLSIre263 TkZA== X-Gm-Message-State: AOAM532yNpUn1UpDOf3DMWNDvU2jyqpPqGm36EoaTDNMqi8qphfvz/HR 0sJ3nS9LxmEA1yPM4RxA7PQ= X-Google-Smtp-Source: ABdhPJy3IXye2zcrS9StAsu8r7oZBvJGEoTUKgACMf+lFQ+T07GUPm1rJQwRJIgqbkhDfkX5zrF6Xg== X-Received: by 2002:a17:907:a42a:: with SMTP id sg42mr18750849ejc.413.1642467721155; Mon, 17 Jan 2022 17:02:01 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id 24sm4892127ejg.47.2022.01.17.17.02.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jan 2022 17:02:00 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/14] drivers: clk: qcom: gcc-ipq806x: add additional freq for sdc table Date: Tue, 18 Jan 2022 01:44:29 +0100 Message-Id: <20220118004434.17095-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220118004434.17095-1-ansuelsmth@gmail.com> References: <20220118004434.17095-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add additional freq supported for the sdc table. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 7d1ddbbbc8ec..0923d7f79a1c 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -1304,6 +1304,7 @@ static const struct freq_tbl clk_tbl_sdc[] = { { 20210000, P_PLL8, 1, 1, 19 }, { 24000000, P_PLL8, 4, 1, 4 }, { 48000000, P_PLL8, 4, 1, 2 }, + { 52000000, P_PLL8, 1, 2, 15 }, /* 51.2 Mhz */ { 64000000, P_PLL8, 3, 1, 2 }, { 96000000, P_PLL8, 4, 0, 0 }, { 192000000, P_PLL8, 2, 0, 0 }, From patchwork Tue Jan 18 00:44:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 533004 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A207C43217 for ; Tue, 18 Jan 2022 01:02:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244063AbiARBCd (ORCPT ); Mon, 17 Jan 2022 20:02:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244046AbiARBCF (ORCPT ); Mon, 17 Jan 2022 20:02:05 -0500 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE09DC06161C; Mon, 17 Jan 2022 17:02:04 -0800 (PST) Received: by mail-ed1-x535.google.com with SMTP id z22so72643838edd.12; Mon, 17 Jan 2022 17:02:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=cdRwCloUT8Thyo1nWTg/Cv6W0pfmm/eqyz83O1RekOs=; b=Ikm23nEs5gASUqJoTSmbWL5A2FTLi27PjBV534u7BNZ5fEjUiIShiC4jO2jf4FivbS Bgh2zciCPoK9XkO/daFf16ZpZxVhDdKOpHDmWCXUzK2yh7fOa/ZDJauvOK3hIi2ny2r8 TK5xKbAbNFVzkWEnfeTGUB1k1y43vvCz3sfJPYSnjSqgwuVFMDHQUErTt7XbUonN/n7q yF0HbupOZY3ChFqqB3pDr2L6XoSp4U8wejagNfTYYuPHZO16SEKjhzW2uVK8f1xXW22R 9PiMSJ+kVB+HJ6zZz/+0qS98B9j8uPC/o4QSlXSW/vfQT2F1E/dcNPhB/1wlnpMvDh/I lnrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cdRwCloUT8Thyo1nWTg/Cv6W0pfmm/eqyz83O1RekOs=; b=E/2MTPZD/VAGSof6yBjH8IgCrN9jl5O48Ewfu8TeQDFD9B3Geg6OpgdACo+h4WNiPw ccohEkT4j/mPdu9+CtLZAwVExZPTBywPJzDt7jXdf3w3k0PfsQm9tUnTNJf72LYANRDE Hn9AhBIhMauzyLIQRV8zzyVHnnnWH1K8GnY5Bxot2U1jtwoSZJ1e1X0GeRvHAFcwHg/8 3EskDJdhFxNL3G9H6aontdV4XqZp1TnTDLD+tAg60vZcTAnMCnXYQyoaXajBevBVp8Hf QVSDpMXCkSSV7cvKAsA86QeI1sAn3NW3vyDzEhWLtl1zxko+ilgLZk85CBfzO3xNDKKA BYNQ== X-Gm-Message-State: AOAM533VR4j/+gZJ3aOQ1OCe6L7t004tSymqoj3NXg0yf6J/hT7EikWm Z+iQBr77wYGvr2U5CYPaL7Q= X-Google-Smtp-Source: ABdhPJyilzrFW6mHgMehvlQefLz0cNTJZpr0b1ZUqbg7xJeAs9MSA/AuPRR70k2TnN7SSBpGzXo0BA== X-Received: by 2002:a17:907:6d8a:: with SMTP id sb10mr4773698ejc.86.1642467723283; Mon, 17 Jan 2022 17:02:03 -0800 (PST) Received: from localhost.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id 24sm4892127ejg.47.2022.01.17.17.02.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jan 2022 17:02:02 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 11/14] drivers: clk: qcom: gcc-ipq806x: add CryptoEngine clocks Date: Tue, 18 Jan 2022 01:44:31 +0100 Message-Id: <20220118004434.17095-12-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220118004434.17095-1-ansuelsmth@gmail.com> References: <20220118004434.17095-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add missing CryptoEngine clocks and pll11 required clock. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 244 +++++++++++++++++++++++++++++++++ 1 file changed, 244 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 0923d7f79a1c..46d0fe511868 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -268,6 +268,24 @@ static struct clk_pll pll18 = { }, }; +static struct clk_pll pll11 = { + .l_reg = 0x3184, + .m_reg = 0x3188, + .n_reg = 0x318c, + .config_reg = 0x3194, + .mode_reg = 0x3180, + .status_reg = 0x3198, + .status_bit = 16, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pll11", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pxo", + }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + enum { P_PXO, P_PLL8, @@ -276,6 +294,7 @@ enum { P_CXO, P_PLL14, P_PLL18, + P_PLL11, }; static const struct parent_map gcc_pxo_pll8_map[] = { @@ -343,6 +362,44 @@ static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = { { .hw = &pll18.clkr.hw }, }; +static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = { + { P_PXO, 0 }, + { P_PLL8, 4 }, + { P_PLL0, 2 }, + { P_PLL14, 5 }, + { P_PLL18, 1 }, + { P_PLL11, 3 }, +}; + +static const struct clk_parent_data gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = { + { .fw_name = "pxo" }, + { .hw = &pll8_vote.hw }, + { .hw = &pll0_vote.hw }, + { .hw = &pll14.clkr.hw }, + { .hw = &pll18.clkr.hw }, + { .hw = &pll11.clkr.hw }, + +}; + +static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = { + { P_PXO, 0 }, + { P_PLL3, 6 }, + { P_PLL0, 2 }, + { P_PLL14, 5 }, + { P_PLL18, 1 }, + { P_PLL11, 3 }, +}; + +static const struct clk_parent_data gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = { + { .fw_name = "pxo" }, + { .hw = &pll3.clkr.hw }, + { .hw = &pll0_vote.hw }, + { .hw = &pll14.clkr.hw }, + { .hw = &pll18.clkr.hw }, + { .hw = &pll11.clkr.hw }, + +}; + static struct freq_tbl clk_tbl_gsbi_uart[] = { { 1843200, P_PLL8, 2, 6, 625 }, { 3686400, P_PLL8, 2, 12, 625 }, @@ -2832,6 +2889,186 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = { }, }; +static const struct freq_tbl clk_tbl_ce5_core[] = { + { 150000000, P_PLL3, 8, 1, 1 }, + { 213200000, P_PLL11, 5, 1, 1 }, + { } +}; + +static struct clk_dyn_rcg ce5_core_src = { + .ns_reg[0] = 0x36C4, + .ns_reg[1] = 0x36C8, + .bank_reg = 0x36C0, + .s[0] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map, + }, + .s[1] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map, + }, + .p[0] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .p[1] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .mux_sel_bit = 0, + .freq_tbl = clk_tbl_ce5_core, + .clkr = { + .enable_reg = 0x36C0, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "ce5_core_src", + .parent_data = gcc_pxo_pll3_pll0_pll14_pll18_pll11, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3_pll0_pll14_pll18_pll11), + .ops = &clk_dyn_rcg_ops, + }, + }, +}; + +static struct clk_branch ce5_core_clk = { + .halt_reg = 0x2FDC, + .halt_bit = 5, + .hwcg_reg = 0x36CC, + .hwcg_bit = 6, + .clkr = { + .enable_reg = 0x36CC, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "ce5_core_clk", + .parent_hws = (const struct clk_hw*[]){ + &ce5_core_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static const struct freq_tbl clk_tbl_ce5_a_clk[] = { + { 160000000, P_PLL0, 5, 1, 1 }, + { 213200000, P_PLL11, 5, 1, 1 }, + { } +}; + +static struct clk_dyn_rcg ce5_a_clk_src = { + .ns_reg[0] = 0x3d84, + .ns_reg[1] = 0x3d88, + .bank_reg = 0x3d80, + .s[0] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, + }, + .s[1] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, + }, + .p[0] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .p[1] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .mux_sel_bit = 0, + .freq_tbl = clk_tbl_ce5_a_clk, + .clkr = { + .enable_reg = 0x3d80, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "ce5_a_clk_src", + .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11), + .ops = &clk_dyn_rcg_ops, + }, + }, +}; + +static struct clk_branch ce5_a_clk = { + .halt_reg = 0x3c20, + .halt_bit = 12, + .hwcg_reg = 0x3d8c, + .hwcg_bit = 6, + .clkr = { + .enable_reg = 0x3d8c, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "ce5_a_clk", + .parent_hws = (const struct clk_hw*[]){ + &ce5_a_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static const struct freq_tbl clk_tbl_ce5_h_clk[] = { + { 160000000, P_PLL0, 5, 1, 1 }, + { 213200000, P_PLL11, 5, 1, 1 }, + { } +}; + +static struct clk_dyn_rcg ce5_h_clk_src = { + .ns_reg[0] = 0x3c64, + .ns_reg[1] = 0x3c68, + .bank_reg = 0x3c60, + .s[0] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, + }, + .s[1] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, + }, + .p[0] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .p[1] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .mux_sel_bit = 0, + .freq_tbl = clk_tbl_ce5_h_clk, + .clkr = { + .enable_reg = 0x3c60, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "ce5_h_clk_src", + .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11), + .ops = &clk_dyn_rcg_ops, + }, + }, +}; + +static struct clk_branch ce5_h_clk = { + .halt_reg = 0x3c20, + .halt_bit = 11, + .hwcg_reg = 0x3c6c, + .hwcg_bit = 6, + .clkr = { + .enable_reg = 0x3c6c, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "ce5_h_clk", + .parent_hws = (const struct clk_hw*[]){ + &ce5_h_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + static struct clk_regmap *gcc_ipq806x_clks[] = { [PLL0] = &pll0.clkr, [PLL0_VOTE] = &pll0_vote, @@ -2839,6 +3076,7 @@ static struct clk_regmap *gcc_ipq806x_clks[] = { [PLL4_VOTE] = &pll4_vote, [PLL8] = &pll8.clkr, [PLL8_VOTE] = &pll8_vote, + [PLL11] = &pll11.clkr, [PLL14] = &pll14.clkr, [PLL14_VOTE] = &pll14_vote, [PLL18] = &pll18.clkr, @@ -2953,6 +3191,12 @@ static struct clk_regmap *gcc_ipq806x_clks[] = { [PLL9] = &hfpll0.clkr, [PLL10] = &hfpll1.clkr, [PLL12] = &hfpll_l2.clkr, + [CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr, + [CE5_A_CLK] = &ce5_a_clk.clkr, + [CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr, + [CE5_H_CLK] = &ce5_h_clk.clkr, + [CE5_CORE_CLK_SRC] = &ce5_core_src.clkr, + [CE5_CORE_CLK] = &ce5_core_clk.clkr, }; static const struct qcom_reset_map gcc_ipq806x_resets[] = { From patchwork Tue Jan 18 00:44:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 533008 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02097C46467 for ; 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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id 24sm4892127ejg.47.2022.01.17.17.02.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jan 2022 17:02:04 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 13/14] drivers: clk: qcom: gcc-ipq806x: add CryptoEngine resets Date: Tue, 18 Jan 2022 01:44:33 +0100 Message-Id: <20220118004434.17095-14-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220118004434.17095-1-ansuelsmth@gmail.com> References: <20220118004434.17095-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add missing CryptoEngine resets. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 46d0fe511868..201c967fc74d 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -3328,6 +3328,11 @@ static const struct qcom_reset_map gcc_ipq806x_resets[] = { [GMAC_CORE3_RESET] = { 0x3cfc, 0 }, [GMAC_CORE4_RESET] = { 0x3d1c, 0 }, [GMAC_AHB_RESET] = { 0x3e24, 0 }, + [CRYPTO_ENG1_RESET] = { 0x3e00, 0}, + [CRYPTO_ENG2_RESET] = { 0x3e04, 0}, + [CRYPTO_ENG3_RESET] = { 0x3e08, 0}, + [CRYPTO_ENG4_RESET] = { 0x3e0c, 0}, + [CRYPTO_AHB_RESET] = { 0x3e10, 0}, [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 }, [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 }, [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },