From patchwork Wed May 31 14:32:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 100787 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp353034qge; Wed, 31 May 2017 07:34:04 -0700 (PDT) X-Received: by 10.99.138.195 with SMTP id y186mr9953350pgd.42.1496241244788; Wed, 31 May 2017 07:34:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496241244; cv=none; d=google.com; s=arc-20160816; b=z9WEvOm34A1zBPqAneBZ3xkf8tJ1wOCHZSsopzFvu4GQMGVDmDcEFkoUoBhA4P2/b4 zTiFqraQSRt/moFMsEK9QhWY9bFAgfMI2GeypFOfjYIv8B0LtmfatoaGymmhuorZuTZK FzqzaXgJ+yuzB//YuvjbaBnIHboLEwqRhEPAAG3VUnWMIf5dE8xyckcs2e4xdb/PGb/v 8UbX6CLX74vXhmDx+lWiDi3b6aGN/KIJ7yi6O70m20qwCDL5NrQMPaBA+ooKjx2rFiNl IGZzJdMh0VHYAeej5Md6lQY+DeVWzQJbb+L1jqJ/vVWIZrXpCHkDNLcRQKLTZxMzEawt JakA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=VoZS05WSv6/piBNy7gcu0Yp5olsAuKep28ITAALV45s=; b=TdljNGoPDum9ShL+cWn/J6Lxuk59yaSCs7HJDTzJgx996do2tLpAxJh8O4p4v2yuOf 0EytUEQ/loDiQMKBD/1JPIuWjI1xtKlsTfrfheQVHJdvTke0m8LSd9sJWfHeRPHkUO1b OyIEkR3U9X75jiID5N1KWNreo9atnPP4pkYBPx7WuDV//jBVD7tAp1+ELNkYgp/cuxLs mj4OjNgLZju3Cc8I0lG1Q0rX7ClKI3L9pHaEZ2CfnClMWqXuIrM+CHwVJYVC1Wguebag p5GSxx5FcXsX/GQ8nyfKxAsRGUzv0tTMF3VUbTzrUZF1ptMtMhVdkugcjAGPb2kD7LFI 3m3w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f64si16579419pfg.362.2017.05.31.07.34.04; Wed, 31 May 2017 07:34:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751041AbdEaOeE (ORCPT + 8 others); Wed, 31 May 2017 10:34:04 -0400 Received: from szxga03-in.huawei.com ([45.249.212.189]:6928 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751011AbdEaOeD (ORCPT ); Wed, 31 May 2017 10:34:03 -0400 Received: from 172.30.72.54 (EHLO dggeml405-hub.china.huawei.com) ([172.30.72.54]) by dggrg03-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOP20883; Wed, 31 May 2017 22:34:00 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.203.177.212) by dggeml405-hub.china.huawei.com (10.3.17.49) with Microsoft SMTP Server id 14.3.301.0; Wed, 31 May 2017 22:33:49 +0800 From: shameer To: , , , , , CC: , , , , , , , , , shameer Subject: [RFCv2 1/2] acpi:iort: Add new helper function to retrieve ITS base addr from dev IORT node Date: Wed, 31 May 2017 15:32:12 +0100 Message-ID: <20170531143213.82100-2-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170531143213.82100-1-shameerali.kolothum.thodi@huawei.com> References: <20170531143213.82100-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020202.592ED458.0352, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: fff2de700e89d13ef1585dbe61daeb41 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org This provides a helper function to find and retrieve the ITS base address from the ID mappings array reference of a device IORT node(if any). This is used in the subsequent patch to retrieve the ITS base address associated with a pci dev IORT node. Signed-off-by: shameer --- drivers/acpi/arm64/iort.c | 47 +++++++++++++++++++++++++++++++++++++--- drivers/irqchip/irq-gic-v3-its.c | 3 ++- include/linux/acpi_iort.h | 8 ++++++- 3 files changed, 53 insertions(+), 5 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index c5fecf9..12d7347 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -34,6 +34,7 @@ struct iort_its_msi_chip { struct list_head list; struct fwnode_handle *fw_node; + u64 base_addr; u32 translation_id; }; @@ -132,13 +133,14 @@ typedef acpi_status (*iort_find_node_callback) /** * iort_register_domain_token() - register domain token and related ITS ID - * to the list from where we can get it back later on. + * and base address to the list from where we can get it back later on. * @trans_id: ITS ID. * @fw_node: Domain token. * * Returns: 0 on success, -ENOMEM if no memory when allocating list element */ -int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node) +int iort_register_domain_token(int trans_id, u64 base, + struct fwnode_handle *fw_node) { struct iort_its_msi_chip *its_msi_chip; @@ -148,6 +150,7 @@ int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node) its_msi_chip->fw_node = fw_node; its_msi_chip->translation_id = trans_id; + its_msi_chip->base_addr = base; spin_lock(&iort_msi_chip_lock); list_add(&its_msi_chip->list, &iort_msi_chip_list); @@ -370,7 +373,6 @@ static struct acpi_iort_node *iort_node_map_id(struct acpi_iort_node *node, if (!node->mapping_offset || !node->mapping_count) goto fail_map; - map = ACPI_ADD_PTR(struct acpi_iort_id_mapping, node, node->mapping_offset); @@ -491,6 +493,45 @@ int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id) return -ENODEV; } +int iort_dev_find_its_base(struct device *dev, u32 req_id, + unsigned int idx, u64 *its_base) +{ + struct acpi_iort_its_group *its; + struct acpi_iort_node *node; + struct iort_its_msi_chip *its_msi_chip; + u32 trans_id; + + node = iort_find_dev_node(dev); + if (!node) + return -ENXIO; + + node = iort_node_map_id(node, req_id, NULL, IORT_MSI_TYPE); + if (!node) + return -ENXIO; + + /* Move to ITS specific data */ + its = (struct acpi_iort_its_group *)node->node_data; + if (idx > its->its_count) { + dev_err(dev, "requested ITS ID index [%d] is greater than available [%d]\n", + idx, its->its_count); + return -ENXIO; + } + + trans_id = its->identifiers[idx]; + + spin_lock(&iort_msi_chip_lock); + list_for_each_entry(its_msi_chip, &iort_msi_chip_list, list) { + if (its_msi_chip->translation_id == trans_id) { + *its_base = its_msi_chip->base_addr; + spin_unlock(&iort_msi_chip_lock); + return 0; + } + } + spin_unlock(&iort_msi_chip_lock); + + return -ENXIO; +} + /** * iort_dev_find_its_id() - Find the ITS identifier for a device * @dev: The device. diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 45ea1933..c45a2ad 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -1854,7 +1854,8 @@ static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header, return -ENOMEM; } - err = iort_register_domain_token(its_entry->translation_id, dom_handle); + err = iort_register_domain_token(its_entry->translation_id, res.start, + dom_handle); if (err) { pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n", &res.start, its_entry->translation_id); diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h index 3ff9ace..bf7b53d 100644 --- a/include/linux/acpi_iort.h +++ b/include/linux/acpi_iort.h @@ -26,7 +26,8 @@ #define IORT_IRQ_MASK(irq) (irq & 0xffffffffULL) #define IORT_IRQ_TRIGGER_MASK(irq) ((irq >> 32) & 0xffffffffULL) -int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node); +int iort_register_domain_token(int trans_id, u64 base, + struct fwnode_handle *fw_node); void iort_deregister_domain_token(int trans_id); struct fwnode_handle *iort_find_domain_token(int trans_id); #ifdef CONFIG_ACPI_IORT @@ -36,6 +37,8 @@ struct irq_domain *iort_get_device_domain(struct device *dev, u32 req_id); void acpi_configure_pmsi_domain(struct device *dev); int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id); +int iort_dev_find_its_base(struct device *dev, u32 req_id, + unsigned int idx, u64 *its_base); /* IOMMU interface */ void iort_set_dma_mask(struct device *dev); const struct iommu_ops *iort_iommu_configure(struct device *dev); @@ -48,6 +51,9 @@ static inline struct irq_domain *iort_get_device_domain(struct device *dev, u32 req_id) { return NULL; } static inline void acpi_configure_pmsi_domain(struct device *dev) { } +int iort_dev_find_its_base(struct device *dev, u32 req_id, + unsigned int idx, u64 *its_base) +{ return -ENOSYS; } /* IOMMU interface */ static inline void iort_set_dma_mask(struct device *dev) { } static inline From patchwork Wed May 31 14:32:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 100788 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp353093qge; Wed, 31 May 2017 07:34:14 -0700 (PDT) X-Received: by 10.98.200.23 with SMTP id z23mr30956220pff.18.1496241253940; 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mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f64si16579419pfg.362.2017.05.31.07.34.13; Wed, 31 May 2017 07:34:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751067AbdEaOeM (ORCPT + 8 others); Wed, 31 May 2017 10:34:12 -0400 Received: from szxga03-in.huawei.com ([45.249.212.189]:6929 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751011AbdEaOeM (ORCPT ); Wed, 31 May 2017 10:34:12 -0400 Received: from 172.30.72.54 (EHLO dggeml405-hub.china.huawei.com) ([172.30.72.54]) by dggrg03-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOP20893; Wed, 31 May 2017 22:34:05 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.203.177.212) by dggeml405-hub.china.huawei.com (10.3.17.49) with Microsoft SMTP Server id 14.3.301.0; Wed, 31 May 2017 22:33:55 +0800 From: shameer To: , , , , , CC: , , , , , , , , , shameer Subject: [RFCv2 2/2] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801 Date: Wed, 31 May 2017 15:32:13 +0100 Message-ID: <20170531143213.82100-3-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170531143213.82100-1-shameerali.kolothum.thodi@huawei.com> References: <20170531143213.82100-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.592ED45E.001A, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 3353111ed35acc79e0a3f0c2ea9bec25 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms Hip06/Hip07 to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch implements a ACPI table based quirk to reserve the hw msi regions in the smmu-v3 driver which means these address regions will not be translated and will be excluded from iova allocations. The HW ITS address region associated with the dev is retrieved using a new helper function added in the IORT code. Signed-off-by: shameer --- drivers/iommu/arm-smmu-v3.c | 49 ++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 46 insertions(+), 3 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index abe4b88..3767526 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -597,6 +597,7 @@ struct arm_smmu_device { u32 features; #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) +#define ARM_SMMU_OPT_RESV_HW_MSI (1 << 1) u32 options; struct arm_smmu_cmdq cmdq; @@ -1755,6 +1756,38 @@ static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid) static struct iommu_ops arm_smmu_ops; +#ifdef CONFIG_ACPI +static struct iommu_resv_region *arm_smmu_acpi_alloc_hw_msi(struct device *dev) +{ + struct iommu_resv_region *region; + struct irq_domain *irq_dom; + int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; + u64 base; + + irq_dom = pci_msi_get_device_domain(to_pci_dev(dev)); + if (irq_dom) { + int ret; + u32 rid; + + rid = pci_msi_domain_get_msi_rid(irq_dom, to_pci_dev(dev)); + ret = iort_dev_find_its_base(dev, rid, 0, &base); + if (!ret) { + dev_info(dev, "SMMUv3:HW MSI resv addr 0x%pa\n", &base); + region = iommu_alloc_resv_region(base, SZ_128K, + prot, IOMMU_RESV_MSI); + return region; + } + } + + return NULL; +} +#else +static struct iommu_resv_region *arm_smmu_acpi_alloc_hw_msi(struct device *dev) +{ + return NULL; +} +#endif + static int arm_smmu_add_device(struct device *dev) { int i, ret; @@ -1903,11 +1936,20 @@ static int arm_smmu_of_xlate(struct device *dev, struct of_phandle_args *args) static void arm_smmu_get_resv_regions(struct device *dev, struct list_head *head) { - struct iommu_resv_region *region; + struct iommu_fwspec *fwspec = dev->iommu_fwspec; + struct iommu_resv_region *region = NULL; int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; + struct arm_smmu_device *smmu; + + smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode); - region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, - prot, IOMMU_RESV_SW_MSI); + if (smmu && (smmu->options & ARM_SMMU_OPT_RESV_HW_MSI) && + dev_is_pci(dev)) + region = arm_smmu_acpi_alloc_hw_msi(dev); + + if (!region) + region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, + prot, IOMMU_RESV_SW_MSI); if (!region) return; @@ -2611,6 +2653,7 @@ static void parse_driver_acpi_options(struct acpi_iort_smmu_v3 *iort_smmu, switch (iort_smmu->model) { case ACPI_IORT_SMMU_HISILICON_HI161X: smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH; + smmu->options |= ARM_SMMU_OPT_RESV_HW_MSI; break; default: break;