From patchwork Thu Jan 27 15:16:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 538090 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF358C433EF for ; Thu, 27 Jan 2022 15:17:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230228AbiA0PRA (ORCPT ); Thu, 27 Jan 2022 10:17:00 -0500 Received: from out28-221.mail.aliyun.com ([115.124.28.221]:49212 "EHLO out28-221.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242844AbiA0PRA (ORCPT ); Thu, 27 Jan 2022 10:17:00 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.847046|0.8261247; CH=green; DM=|SPAM|false|; DS=CONTINUE|ham_system_inform|0.0212515-0.000109326-0.978639; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047205; MF=icenowy@nucleisys.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.Mj85Oz4_1643296614; Received: from ice-e5v2.lan(mailfrom:icenowy@nucleisys.com fp:SMTPD_---.Mj85Oz4_1643296614) by smtp.aliyun-inc.com(33.45.46.134); Thu, 27 Jan 2022 23:16:56 +0800 From: Icenowy Zheng To: Rob Herring , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, Icenowy Zheng Subject: [PATCH 01/12] dt-bindings: vendor-prefixes: add Nuclei Date: Thu, 27 Jan 2022 23:16:36 +0800 Message-Id: <20220127151647.2375449-2-icenowy@nucleisys.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220127151647.2375449-1-icenowy@nucleisys.com> References: <20220127151647.2375449-1-icenowy@nucleisys.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Nuclei System Technology is a RISC-V CPU IP core vendor. Add vendor prefix for it. Signed-off-by: Icenowy Zheng --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 294093d45a23..8d786367b093 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -842,6 +842,8 @@ patternProperties: description: Nordic Semiconductor "^novtech,.*": description: NovTech, Inc. + "^nuclei,.*": + description: Nuclei System Technology "^nutsboard,.*": description: NutsBoard "^nuvoton,.*": From patchwork Thu Jan 27 15:16:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 537186 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82C7BC43217 for ; Thu, 27 Jan 2022 15:17:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242864AbiA0PRD (ORCPT ); Thu, 27 Jan 2022 10:17:03 -0500 Received: from out29-99.mail.aliyun.com ([115.124.29.99]:36760 "EHLO out29-99.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242847AbiA0PRC (ORCPT ); Thu, 27 Jan 2022 10:17:02 -0500 X-Alimail-AntiSpam: AC=SUSPECT; BC=0.6349558|-1; BR=01201311R141b1; CH=blue; DM=|SUSPECT|false|; DS=CONTINUE|ham_system_inform|0.0327302-0.00826224-0.959008; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047192; MF=icenowy@nucleisys.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.Mj85OzO_1643296617; Received: from ice-e5v2.lan(mailfrom:icenowy@nucleisys.com fp:SMTPD_---.Mj85OzO_1643296617) by smtp.aliyun-inc.com(33.45.46.134); Thu, 27 Jan 2022 23:16:58 +0800 From: Icenowy Zheng To: Rob Herring , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, Icenowy Zheng Subject: [PATCH 02/12] RISC-V: add Nuclei SoC Kconfig option Date: Thu, 27 Jan 2022 23:16:37 +0800 Message-Id: <20220127151647.2375449-3-icenowy@nucleisys.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220127151647.2375449-1-icenowy@nucleisys.com> References: <20220127151647.2375449-1-icenowy@nucleisys.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org As a CPU core vendor, Nuclei has some "DemoSoCs" that uses Nuclei CPU cores and modified peripherals from Hummingbird E203. Add a Kconfig option for this. Signed-off-by: Icenowy Zheng --- arch/riscv/Kconfig.socs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 6ec44a22278a..e4488ac8c72b 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -7,6 +7,12 @@ config SOC_MICROCHIP_POLARFIRE help This enables support for Microchip PolarFire SoC platforms. +config SOC_NUCLEI + bool "Nuclei SoCs" + select SIFIVE_PLIC + help + This enables support for Nuclei SoC platform hardware. + config SOC_SIFIVE bool "SiFive SoCs" select SERIAL_SIFIVE if TTY From patchwork Thu Jan 27 15:16:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 537185 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64C3CC43217 for ; Thu, 27 Jan 2022 15:17:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242877AbiA0PRG (ORCPT ); Thu, 27 Jan 2022 10:17:06 -0500 Received: from out28-121.mail.aliyun.com ([115.124.28.121]:35882 "EHLO out28-121.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242859AbiA0PRE (ORCPT ); Thu, 27 Jan 2022 10:17:04 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.4093572|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.096465-0.000677537-0.902857; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047211; MF=icenowy@nucleisys.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.Mj85Ozd_1643296619; Received: from ice-e5v2.lan(mailfrom:icenowy@nucleisys.com fp:SMTPD_---.Mj85Ozd_1643296619) by smtp.aliyun-inc.com(33.45.46.134); Thu, 27 Jan 2022 23:17:00 +0800 From: Icenowy Zheng To: Rob Herring , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, Icenowy Zheng Subject: [PATCH 03/12] dt-bindings: riscv: add compatible strings for Nuclei UX600 series Date: Thu, 27 Jan 2022 23:16:38 +0800 Message-Id: <20220127151647.2375449-4-icenowy@nucleisys.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220127151647.2375449-1-icenowy@nucleisys.com> References: <20220127151647.2375449-1-icenowy@nucleisys.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Nuclei UX600 series are 64-bit, MMU-equipped CPUs, which can run Linux. Add compatible strings for these CPU cores. Signed-off-by: Icenowy Zheng --- Documentation/devicetree/bindings/riscv/cpus.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index aa5fb64d57eb..f50f5c3dcc06 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -45,6 +45,13 @@ properties: - sifive,u54-mc - const: sifive,rocket0 - const: riscv + - items: + - enum: + - nuclei,ux605 + - nuclei,ux607 + - nuclei,ux608 + - const: nuclei,ux600 + - const: riscv - const: riscv # Simulator only description: Identifies that the hart uses the RISC-V instruction set From patchwork Thu Jan 27 15:16:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 538088 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7D16C433F5 for ; Thu, 27 Jan 2022 15:17:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242884AbiA0PRH (ORCPT ); Thu, 27 Jan 2022 10:17:07 -0500 Received: from out28-125.mail.aliyun.com ([115.124.28.125]:36216 "EHLO out28-125.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242874AbiA0PRG (ORCPT ); Thu, 27 Jan 2022 10:17:06 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.4156253|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0591787-0.000989701-0.939832; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047203; MF=icenowy@nucleisys.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.Mj85Ozx_1643296621; Received: from ice-e5v2.lan(mailfrom:icenowy@nucleisys.com fp:SMTPD_---.Mj85Ozx_1643296621) by smtp.aliyun-inc.com(33.45.46.134); Thu, 27 Jan 2022 23:17:02 +0800 From: Icenowy Zheng To: Rob Herring , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, Icenowy Zheng Subject: [PATCH 04/12] dt-bindings: timer: add compatible for Nuclei UX600 CLINT-compat timer Date: Thu, 27 Jan 2022 23:16:39 +0800 Message-Id: <20220127151647.2375449-5-icenowy@nucleisys.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220127151647.2375449-1-icenowy@nucleisys.com> References: <20220127151647.2375449-1-icenowy@nucleisys.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Nuclei UX600's timer has a part which is compatible with CLINT. Add a DT compatible string for it. Signed-off-by: Icenowy Zheng --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 8d5f4687add9..61a8bd8bde91 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -27,6 +27,7 @@ properties: - sifive,fu540-c000-clint - starfive,jh7100-clint - canaan,k210-clint + - nuclei,ux600-clint - const: sifive,clint0 description: From patchwork Thu Jan 27 15:16:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 537184 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A177C4321E for ; Thu, 27 Jan 2022 15:17:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242945AbiA0PRN (ORCPT ); Thu, 27 Jan 2022 10:17:13 -0500 Received: from out28-220.mail.aliyun.com ([115.124.28.220]:42813 "EHLO out28-220.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230336AbiA0PRI (ORCPT ); Thu, 27 Jan 2022 10:17:08 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.510604|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.191371-0.00178411-0.806845; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047187; MF=icenowy@nucleisys.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.Mj85P-L_1643296623; Received: from ice-e5v2.lan(mailfrom:icenowy@nucleisys.com fp:SMTPD_---.Mj85P-L_1643296623) by smtp.aliyun-inc.com(33.45.46.134); Thu, 27 Jan 2022 23:17:04 +0800 From: Icenowy Zheng To: Rob Herring , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, Icenowy Zheng Subject: [PATCH 05/12] dt-bindings: interrupt-controller: add compatible string for UX600 PLIC Date: Thu, 27 Jan 2022 23:16:40 +0800 Message-Id: <20220127151647.2375449-6-icenowy@nucleisys.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220127151647.2375449-1-icenowy@nucleisys.com> References: <20220127151647.2375449-1-icenowy@nucleisys.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Nuclei UX600 series CPU has an optional PLIC (recommended when running Linux). Add a compatible string for it. Signed-off-by: Icenowy Zheng --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 28b6b17fe4b2..70f5bd6cb879 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -47,6 +47,7 @@ properties: - sifive,fu540-c000-plic - starfive,jh7100-plic - canaan,k210-plic + - nuclei,ux600-plic - const: sifive,plic-1.0.0 reg: From patchwork Thu Jan 27 15:16:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 538087 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8B2CC433EF for ; Thu, 27 Jan 2022 15:17:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242965AbiA0PRO (ORCPT ); Thu, 27 Jan 2022 10:17:14 -0500 Received: from out28-169.mail.aliyun.com ([115.124.28.169]:54771 "EHLO out28-169.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242890AbiA0PRK (ORCPT ); Thu, 27 Jan 2022 10:17:10 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.5467414|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.023987-0.000137044-0.975876; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047209; MF=icenowy@nucleisys.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.Mj85P-f_1643296625; Received: from ice-e5v2.lan(mailfrom:icenowy@nucleisys.com fp:SMTPD_---.Mj85P-f_1643296625) by smtp.aliyun-inc.com(33.45.46.134); Thu, 27 Jan 2022 23:17:06 +0800 From: Icenowy Zheng To: Rob Herring , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, Icenowy Zheng Subject: [PATCH 06/12] dt-bindings: serial: add compatible string for Nuclei DemoSoC UART Date: Thu, 27 Jan 2022 23:16:41 +0800 Message-Id: <20220127151647.2375449-7-icenowy@nucleisys.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220127151647.2375449-1-icenowy@nucleisys.com> References: <20220127151647.2375449-1-icenowy@nucleisys.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Nuclei DemoSoC design integrates the UART controller from SiFive. Add a compatible string for it. Signed-off-by: Icenowy Zheng --- Documentation/devicetree/bindings/serial/sifive-serial.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/sifive-serial.yaml b/Documentation/devicetree/bindings/serial/sifive-serial.yaml index 09aae43f65a7..329341a3648f 100644 --- a/Documentation/devicetree/bindings/serial/sifive-serial.yaml +++ b/Documentation/devicetree/bindings/serial/sifive-serial.yaml @@ -21,6 +21,7 @@ properties: - sifive,fu540-c000-uart - sifive,fu740-c000-uart - canaan,k210-uarths + - nuclei,demosoc-uart - const: sifive,uart0 description: From patchwork Thu Jan 27 15:16:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 537183 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0830AC43219 for ; Thu, 27 Jan 2022 15:17:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242909AbiA0PRQ (ORCPT ); Thu, 27 Jan 2022 10:17:16 -0500 Received: from out28-52.mail.aliyun.com ([115.124.28.52]:56734 "EHLO out28-52.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242906AbiA0PRM (ORCPT ); Thu, 27 Jan 2022 10:17:12 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.512559|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0785358-0.00189877-0.919565; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047207; MF=icenowy@nucleisys.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.Mj85P.-_1643296627; Received: from ice-e5v2.lan(mailfrom:icenowy@nucleisys.com fp:SMTPD_---.Mj85P.-_1643296627) by smtp.aliyun-inc.com(33.45.46.134); Thu, 27 Jan 2022 23:17:08 +0800 From: Icenowy Zheng To: Rob Herring , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, Icenowy Zheng Subject: [PATCH 07/12] dt-bindings: spi: add compatible string for Nuclei DemoSoC SPI Date: Thu, 27 Jan 2022 23:16:42 +0800 Message-Id: <20220127151647.2375449-8-icenowy@nucleisys.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220127151647.2375449-1-icenowy@nucleisys.com> References: <20220127151647.2375449-1-icenowy@nucleisys.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Nuclei DemoSoC design integrates SPI controllers from SiFive. Add a compatible string for these SPI controllers. Signed-off-by: Icenowy Zheng --- Documentation/devicetree/bindings/spi/spi-sifive.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/spi-sifive.yaml b/Documentation/devicetree/bindings/spi/spi-sifive.yaml index 6e7e394fc1e4..60a24f31a928 100644 --- a/Documentation/devicetree/bindings/spi/spi-sifive.yaml +++ b/Documentation/devicetree/bindings/spi/spi-sifive.yaml @@ -20,6 +20,7 @@ properties: - enum: - sifive,fu540-c000-spi - sifive,fu740-c000-spi + - nuclei,demosoc-spi - const: sifive,spi0 description: From patchwork Thu Jan 27 15:16:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 538086 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51557C4321E for ; Thu, 27 Jan 2022 15:17:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243002AbiA0PRR (ORCPT ); Thu, 27 Jan 2022 10:17:17 -0500 Received: from out28-218.mail.aliyun.com ([115.124.28.218]:53184 "EHLO out28-218.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242915AbiA0PRN (ORCPT ); Thu, 27 Jan 2022 10:17:13 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.5576189|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0234192-0.00181788-0.974763; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047188; MF=icenowy@nucleisys.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.Mj85P.G_1643296629; Received: from ice-e5v2.lan(mailfrom:icenowy@nucleisys.com fp:SMTPD_---.Mj85P.G_1643296629) by smtp.aliyun-inc.com(33.45.46.134); Thu, 27 Jan 2022 23:17:10 +0800 From: Icenowy Zheng To: Rob Herring , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, Icenowy Zheng Subject: [PATCH 08/12] dt-bindings: riscv: add binding for Nuclei platform boards Date: Thu, 27 Jan 2022 23:16:43 +0800 Message-Id: <20220127151647.2375449-9-icenowy@nucleisys.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220127151647.2375449-1-icenowy@nucleisys.com> References: <20220127151647.2375449-1-icenowy@nucleisys.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org As we added support for RISC-V SoCs from Nuclei, add device tree binding for the currently supported board-bitstream combo (DemoSoC with UX600 on DDR200T board). Signed-off-by: Icenowy Zheng --- .../devicetree/bindings/riscv/nuclei.yaml | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/nuclei.yaml diff --git a/Documentation/devicetree/bindings/riscv/nuclei.yaml b/Documentation/devicetree/bindings/riscv/nuclei.yaml new file mode 100644 index 000000000000..4760568c7bde --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/nuclei.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/nuclei.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuclei SoC-based boards + +maintainers: + - Icenowy Zheng + +description: + Nuclei SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - const: nuclei,demosoc-ux600-ddr200t + - const: nuclei,demosoc-ux600 + - const: nuclei,demosoc + +additionalProperties: true + +... From patchwork Thu Jan 27 15:16:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 538085 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27056C433EF for ; Thu, 27 Jan 2022 15:17:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242974AbiA0PRV (ORCPT ); Thu, 27 Jan 2022 10:17:21 -0500 Received: from out28-149.mail.aliyun.com ([115.124.28.149]:49353 "EHLO out28-149.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242947AbiA0PRP (ORCPT ); Thu, 27 Jan 2022 10:17:15 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07451715|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.277158-0.000105434-0.722737; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047212; MF=icenowy@nucleisys.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.Mj85P.V_1643296630; Received: from ice-e5v2.lan(mailfrom:icenowy@nucleisys.com fp:SMTPD_---.Mj85P.V_1643296630) by smtp.aliyun-inc.com(33.45.46.134); Thu, 27 Jan 2022 23:17:12 +0800 From: Icenowy Zheng To: Rob Herring , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, Icenowy Zheng Subject: [PATCH 09/12] riscv: dts: add device tree for Nuclei DemoSoC w/ UX600 on DDR200T Date: Thu, 27 Jan 2022 23:16:44 +0800 Message-Id: <20220127151647.2375449-10-icenowy@nucleisys.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220127151647.2375449-1-icenowy@nucleisys.com> References: <20220127151647.2375449-1-icenowy@nucleisys.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org As we're supporting Nuclei DemoSoC for UX600 CPU cores on DDR200T FPGA prototyping board, add device tree files for it, including DTSI files for basic DemoSoC structure, DemoSoC with UX600 and DemoSoC running on DDR200T for further reusing. Signed-off-by: Icenowy Zheng --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/nuclei/Makefile | 2 + .../dts/nuclei/nuclei-demosoc-ddr200t.dtsi | 41 ++++++++++++ .../nuclei/nuclei-demosoc-ux600-ddr200t.dts | 13 ++++ .../boot/dts/nuclei/nuclei-demosoc-ux600.dtsi | 49 ++++++++++++++ .../riscv/boot/dts/nuclei/nuclei-demosoc.dtsi | 67 +++++++++++++++++++ 6 files changed, 173 insertions(+) create mode 100644 arch/riscv/boot/dts/nuclei/Makefile create mode 100644 arch/riscv/boot/dts/nuclei/nuclei-demosoc-ddr200t.dtsi create mode 100644 arch/riscv/boot/dts/nuclei/nuclei-demosoc-ux600-ddr200t.dts create mode 100644 arch/riscv/boot/dts/nuclei/nuclei-demosoc-ux600.dtsi create mode 100644 arch/riscv/boot/dts/nuclei/nuclei-demosoc.dtsi diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index ff174996cdfd..fd31084986da 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -3,5 +3,6 @@ subdir-y += sifive subdir-y += starfive subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan subdir-y += microchip +subdir-y += nuclei obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) diff --git a/arch/riscv/boot/dts/nuclei/Makefile b/arch/riscv/boot/dts/nuclei/Makefile new file mode 100644 index 000000000000..57970aabf01d --- /dev/null +++ b/arch/riscv/boot/dts/nuclei/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_SOC_NUCLEI) += nuclei-demosoc-ux600-ddr200t.dtb diff --git a/arch/riscv/boot/dts/nuclei/nuclei-demosoc-ddr200t.dtsi b/arch/riscv/boot/dts/nuclei/nuclei-demosoc-ddr200t.dtsi new file mode 100644 index 000000000000..4f44c6b564bb --- /dev/null +++ b/arch/riscv/boot/dts/nuclei/nuclei-demosoc-ddr200t.dtsi @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2022 Nuclei System Technology */ + +/ { + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@a0000000 { + device_type = "memory"; + reg = <0xa0000000 0xe000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&qspi0 { + status = "okay"; + + spi_nor: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <8000000>; + }; +}; + +&qspi2 { + status = "okay"; + + spi_mmc: mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <8000000>; + }; +}; diff --git a/arch/riscv/boot/dts/nuclei/nuclei-demosoc-ux600-ddr200t.dts b/arch/riscv/boot/dts/nuclei/nuclei-demosoc-ux600-ddr200t.dts new file mode 100644 index 000000000000..cd15ec2c1376 --- /dev/null +++ b/arch/riscv/boot/dts/nuclei/nuclei-demosoc-ux600-ddr200t.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2022 Nuclei System Technology */ + +/dts-v1/; + +#include "nuclei-demosoc-ux600.dtsi" +#include "nuclei-demosoc-ddr200t.dtsi" + +/ { + model = "Nuclei DemoSoC with UX600 on DDR200T"; + compatible = "nuclei,demosoc-ux600-ddr200t", + "nuclei,demosoc-ux600", "nuclei,demosoc"; +}; diff --git a/arch/riscv/boot/dts/nuclei/nuclei-demosoc-ux600.dtsi b/arch/riscv/boot/dts/nuclei/nuclei-demosoc-ux600.dtsi new file mode 100644 index 000000000000..f3588907ce3f --- /dev/null +++ b/arch/riscv/boot/dts/nuclei/nuclei-demosoc-ux600.dtsi @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2022 Nuclei System Technology */ + +#include "nuclei-demosoc.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + /* The counting clock of the timer is the LF clock */ + timebase-frequency = <32768>; + + cpu0: cpu@0 { + compatible = "nuclei,ux607", "nuclei,ux600", "riscv"; + device_type = "cpu"; + reg = <0>; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + clock-frequency = <16000000>; + + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + + clint: clint@2001000 { + compatible = "nuclei,ux600-clint", "sifive,clint0"; + reg = <0x02001000 0xc000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; + }; + + plic: plic@8000000 { + compatible = "nuclei,ux600-plic", "sifive,plic-1.0.0"; + reg = <0x08000000 0x4000000>; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + interrupts-extended = + <&cpu0_intc 11>, <&cpu0_intc 9>; + riscv,ndev = <52>; + }; +}; + +&ppi { + interrupt-parent = <&plic>; +}; diff --git a/arch/riscv/boot/dts/nuclei/nuclei-demosoc.dtsi b/arch/riscv/boot/dts/nuclei/nuclei-demosoc.dtsi new file mode 100644 index 000000000000..85a4f713d3d9 --- /dev/null +++ b/arch/riscv/boot/dts/nuclei/nuclei-demosoc.dtsi @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2022 Nuclei System Technology */ + +/ { + /* + * Nuclei DemoSoC is a 32-bit design even if 64-bit CPU core is + * integrated into it. + */ + #address-cells = <1>; + #size-cells = <1>; + + clocks { + /* For most of the SoC */ + hfclk: hfclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + }; + + /* For always-on zone */ + lfclk: lfclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + /* + * The interrupt controller and all peripherals' interrupt parent + * are to be defined in individual CPU cores' DemoSoC DT. + */ + ppi: ppi { + compatible = "simple-bus"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + uart0: serial@10010000 { + compatible = "nuclei,demosoc-uart", "sifive,uart0"; + reg = <0x10013000 0x1000>; + clocks = <&hfclk>; + interrupts = <33>; + status = "disabled"; + }; + + qspi0: spi@10014000 { + compatible = "nuclei,demosoc-spi", "sifive,spi0"; + reg = <0x10014000 0x1000>, + <0x20000000 0x20000000>; + interrupts = <35>; + clocks = <&hfclk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + qspi2: spi@10034000 { + compatible = "nuclei,demosoc-spi", "sifive,spi0"; + reg = <0x10034000 0x1000>; + interrupts = <37>; + clocks = <&hfclk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; +}; From patchwork Thu Jan 27 15:16:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 537182 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEB35C4167B for ; Thu, 27 Jan 2022 15:17:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242995AbiA0PRX (ORCPT ); Thu, 27 Jan 2022 10:17:23 -0500 Received: from out28-197.mail.aliyun.com ([115.124.28.197]:40751 "EHLO out28-197.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242976AbiA0PRR (ORCPT ); Thu, 27 Jan 2022 10:17:17 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.08545136|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_regular_dialog|0.0149326-0.000578924-0.984489; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047213; MF=icenowy@nucleisys.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.Mj85P.l_1643296632; Received: from ice-e5v2.lan(mailfrom:icenowy@nucleisys.com fp:SMTPD_---.Mj85P.l_1643296632) by smtp.aliyun-inc.com(33.45.46.134); Thu, 27 Jan 2022 23:17:14 +0800 From: Icenowy Zheng To: Rob Herring , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, Icenowy Zheng Subject: [PATCH 10/12] RISC-V: workaround Nuclei UX600 cores with broken SATP CSR Date: Thu, 27 Jan 2022 23:16:45 +0800 Message-Id: <20220127151647.2375449-11-icenowy@nucleisys.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220127151647.2375449-1-icenowy@nucleisys.com> References: <20220127151647.2375449-1-icenowy@nucleisys.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Current release of Nuclei UX600 CPU cores have two errata against RISC-V Privledged Specification 1.10: one is left over mvendorid value (not the JEDEC ID), the other, which is a more breaking one that needs to be workaround in software, is that satp will accept written value with MODE=9 (Sv48, which is not supported by UX600), and silently change it to MODE=8 (Sv39). As current kernel MMU initialization code relies on the behavior defined on the spec (reject write request with unsupported MODE value and do not change the CSR's value at all) to detect the existence of Sv48, the erratum breaks the Sv48 detection code. As both two errata are to be fixed in the next revision, use the first to detect the existence of the second at runtime, and force Sv39 when these errata are detected. Signed-off-by: Icenowy Zheng --- arch/riscv/include/asm/vendorid_list.h | 1 + arch/riscv/mm/init.c | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h index 9d934215b3c8..47ff43795d70 100644 --- a/arch/riscv/include/asm/vendorid_list.h +++ b/arch/riscv/include/asm/vendorid_list.h @@ -6,5 +6,6 @@ #define ASM_VENDOR_LIST_H #define SIFIVE_VENDOR_ID 0x489 +#define NUCLEI_OLD_VENDOR_ID 0x2d33 #endif diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index cf4d018b7d66..0085b14ae265 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -28,6 +28,8 @@ #include #include #include +#include +#include #include "../kernel/head.h" @@ -591,6 +593,21 @@ static __init void set_satp_mode(void) u64 identity_satp, hw_satp; uintptr_t set_satp_mode_pmd; + if (sbi_get_mvendorid() == NUCLEI_OLD_VENDOR_ID) { + /* + * Old Nuclei UX600 processor releases have broken + * implementation of SATP register which prevents + * proper runtime detection of Sv48 existence. In + * addition these processor releases have an old + * vendor id instead of proper JEDEC ID. + * + * As these releases do not support Sv48 at all, + * force Sv39 on them. + */ + disable_pgtable_l4(); + return; + } + set_satp_mode_pmd = ((unsigned long)set_satp_mode) & PMD_MASK; create_pgd_mapping(early_pg_dir, set_satp_mode_pmd, (uintptr_t)early_pud, From patchwork Thu Jan 27 15:16:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 537181 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C533AC43219 for ; Thu, 27 Jan 2022 15:17:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243247AbiA0PRh (ORCPT ); Thu, 27 Jan 2022 10:17:37 -0500 Received: from out28-51.mail.aliyun.com ([115.124.28.51]:46312 "EHLO out28-51.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243011AbiA0PRU (ORCPT ); Thu, 27 Jan 2022 10:17:20 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.6810555|0.5696508; CH=green; DM=|SPAM|false|; DS=CONTINUE|ham_regular_dialog|0.0726309-0.00131609-0.926053; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047199; MF=icenowy@nucleisys.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.Mj85P0-_1643296634; Received: from ice-e5v2.lan(mailfrom:icenowy@nucleisys.com fp:SMTPD_---.Mj85P0-_1643296634) by smtp.aliyun-inc.com(33.45.46.134); Thu, 27 Jan 2022 23:17:15 +0800 From: Icenowy Zheng To: Rob Herring , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, Icenowy Zheng Subject: [PATCH 11/12] MAINTAINERS: add myself as Nuclei SoCs/CPUs supporter Date: Thu, 27 Jan 2022 23:16:46 +0800 Message-Id: <20220127151647.2375449-12-icenowy@nucleisys.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220127151647.2375449-1-icenowy@nucleisys.com> References: <20220127151647.2375449-1-icenowy@nucleisys.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Currently I am working on mainlining Nuclei SoCs/CPUs Linux support. Add myself as a supporter of this. Signed-off-by: Icenowy Zheng --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index ea3e6c914384..499450d14625 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13733,6 +13733,13 @@ F: drivers/nubus/ F: include/linux/nubus.h F: include/uapi/linux/nubus.h +NUCLEI RISCV CORES AND SOCS +M: Icenowy Zheng +L: linux-riscv@lists.infradead.org +S: Supported +N: nuclei +K: [^@]nuclei + NVIDIA (rivafb and nvidiafb) FRAMEBUFFER DRIVER M: Antonino Daplas L: linux-fbdev@vger.kernel.org From patchwork Thu Jan 27 15:16:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 538084 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 827A1C433FE for ; Thu, 27 Jan 2022 15:17:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243037AbiA0PRg (ORCPT ); Thu, 27 Jan 2022 10:17:36 -0500 Received: from out28-194.mail.aliyun.com ([115.124.28.194]:56675 "EHLO out28-194.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243023AbiA0PRU (ORCPT ); Thu, 27 Jan 2022 10:17:20 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1905793|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0580845-0.00345395-0.938462; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047194; MF=icenowy@nucleisys.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.Mj85P0E_1643296636; Received: from ice-e5v2.lan(mailfrom:icenowy@nucleisys.com fp:SMTPD_---.Mj85P0E_1643296636) by smtp.aliyun-inc.com(33.45.46.134); Thu, 27 Jan 2022 23:17:17 +0800 From: Icenowy Zheng To: Rob Herring , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, Icenowy Zheng Subject: [PATCH 12/12] mailmap: add Icenowy Zheng's Nuclei mail addresses Date: Thu, 27 Jan 2022 23:16:47 +0800 Message-Id: <20220127151647.2375449-13-icenowy@nucleisys.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220127151647.2375449-1-icenowy@nucleisys.com> References: <20220127151647.2375449-1-icenowy@nucleisys.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org A mail address is assigned to Icenowy under @nucleisys.com for supporting Nuclei SoCs/CPUs in Linux (and other open source projects). Add it to the .mailmap file. Signed-off-by: Icenowy Zheng --- .mailmap | 1 + 1 file changed, 1 insertion(+) diff --git a/.mailmap b/.mailmap index b157f88ce26a..4bacaef7b06d 100644 --- a/.mailmap +++ b/.mailmap @@ -144,6 +144,7 @@ Henrik Rydberg Herbert Xu Huacai Chen Huacai Chen +Icenowy Zheng Jacob Shin Jaegeuk Kim Jaegeuk Kim