From patchwork Thu Nov 22 11:38:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 151751 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp627854ljp; Thu, 22 Nov 2018 03:39:32 -0800 (PST) X-Google-Smtp-Source: AJdET5dTSO04oJzjgM30J85k2dw6uMA3yJ3KXgfnUKJxbD3IMIhfeec5HOvTR0/5HAFb6zA679+w X-Received: by 2002:a62:cc4:: with SMTP id 65-v6mr11012788pfm.127.1542886772413; Thu, 22 Nov 2018 03:39:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542886772; cv=none; d=google.com; s=arc-20160816; b=lBdKaSxkR6G0whFQ3qnshBJ43P47UakX+5iIi9MjVQJJHT65KcFktWwj0/NWQq80wL gM7H/KwNjt2gpGXgAtoQ7LiZY2Z6xvL/tOEPHk44gNurve0htpA4Xyk3MS7YhxNMnyfC 40p4fBRPCQSsum6PQ9HUGnh6O8N7GeDQjXI4MvDJ+QLX4xmHCUz2wNeqfs+vEvVD0Pf8 8ga8DaC8pJuxbuqVK/B56hFGVJkzG2R81aolfRKL71/Q4HgF8lC60DGyJewDY6fvXbeo gKgBUNawdVRHhEFTsr3a+1cXcIaxkH/EGyfQ+p3TzxbA+V9pdYmRVqfqTvGQw437ldUc OUnQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=66hSt6aY4EgkJI+Da0DauljFqWsuYb3z1eFtSjgvNLY=; b=r5PCvEF4G+kr8QJfRe73GjXqGM0PGPujkjXQxevcK/+sVR2M8/fwobVJ/6hyLsBgT9 r+zcK8OAEwKgpdijwtQnreMFNasmIgr58nPed/2VbmDF9oQOMgkGeiUoO8zydlOmahcQ g7JPk0YYKdFtw3x0cCI+TxNECLm9+HujEvwX0gVXqioNU9/3nLrd6qns8Sj2D1aUMEj9 7QkZRZy/HKVqJ/clO0l1wGaRSOqGhJGdZr4+DloXTogeOC9GDgvvschQs7ezSnAPutKw 1PSosNRnN5dNlepe2V6y0YBoONWgOF0xGMFdFMPro3bgHhVUk1Fmw6Lr/IfyQqHsQT6t +lRQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=AI5ew8Tn; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g10si33829255plm.1.2018.11.22.03.39.32; Thu, 22 Nov 2018 03:39:32 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=AI5ew8Tn; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405539AbeKVWSb (ORCPT + 32 others); Thu, 22 Nov 2018 17:18:31 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:50370 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2403801AbeKVWSa (ORCPT ); Thu, 22 Nov 2018 17:18:30 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id wAMBdPIW075744; Thu, 22 Nov 2018 05:39:25 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1542886765; bh=66hSt6aY4EgkJI+Da0DauljFqWsuYb3z1eFtSjgvNLY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=AI5ew8Tn+I41/b+WIqD/GOO5+RVYN7stHGEIoKPMomqFQMhgu+Fw6kG99Nys0GNVO pRd3D3d610bPc3g9LHValFrTU0ZBJ3Kz5WTqlNIK+RJhFnyDYOpBcvrp93pVqMeeGL 1oyNSjTrsRTqC4+6Za3qxor7awMx+/TWP3FxWYKM= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wAMBdPqs129910 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 22 Nov 2018 05:39:25 -0600 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 22 Nov 2018 05:39:22 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 22 Nov 2018 05:39:22 -0600 Received: from dlelxv97.itg.ti.com (dlelxv97.itg.ti.com [172.17.2.193]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAMBdMZD011163; Thu, 22 Nov 2018 05:39:22 -0600 Received: from localhost.localdomain (vboxa0400828d.dhcp.ti.com [172.22.239.63]) by dlelxv97.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAMBdDf0013203; Thu, 22 Nov 2018 05:39:18 -0600 From: Roger Quadros To: CC: , , , , , , , , , , , , , , , , Subject: [PATCH 01/17] dt-bindings: remoteproc: Add TI PRUSS bindings Date: Thu, 22 Nov 2018 13:38:57 +0200 Message-ID: <1542886753-17625-2-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1542886753-17625-1-git-send-email-rogerq@ti.com> References: <1542886753-17625-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Suman Anna This patch adds the bindings for the Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS) present on various TI SoCs. The IP is present on multiple TI SoC architecture families including the OMAP architecture SoCs such as AM33xx, AM437x and AM57xx; and on a Keystone 2 architecture based 66AK2G SoC. It is also present on the Davinci based OMAPL138 SoCs and K3 architecture based AM65x SoCs as well (not covered for now). Details have been added to include bindings for various core sub-modules like the PRU Cores, the PRUSS Interrupt Controller, and other sub-modules used for Industrial Communication purposes, covering the MDIO, MII_RT and the IEP sub-modules. The binding mostly uses standard DT properties. Signed-off-by: Suman Anna Signed-off-by: Roger Quadros --- .../devicetree/bindings/soc/ti/ti,pruss.txt | 360 +++++++++++++++++++++ 1 file changed, 360 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/ti/ti,pruss.txt -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/Documentation/devicetree/bindings/soc/ti/ti,pruss.txt b/Documentation/devicetree/bindings/soc/ti/ti,pruss.txt new file mode 100644 index 0000000..24fedad --- /dev/null +++ b/Documentation/devicetree/bindings/soc/ti/ti,pruss.txt @@ -0,0 +1,360 @@ +PRU-ICSS on TI SoCs +=================== + +The Programmable Real-Time Unit and Industrial Communication Subsystem +(PRU-ICSS) is present on various TI SoCs such as AM335x or AM437x or a +Keystone 66AK2G. A PRUSS consists of dual 32-bit RISC cores (Programmable +Real-Time Units, or PRUs), shared RAM, data and instruction RAMs, some +internal peripheral modules to facilitate industrial communication, and +an interrupt controller. The programmable nature of the PRUs provide +flexibility to implement custom peripheral interfaces, fast real-time +responses, or specialized data handling. The common peripheral modules +include the following, + - an Ethernet MII_RT module with two MII ports + - an MDIO port to control external Ethernet PHYs + - an Industrial Ethernet Peripheral (IEP) to manage/generate Industrial + Ethernet functions + - an Enhanced Capture Module (eCAP) + - an Industrial Ethernet Timer with 7/9 capture and 16 compare events + - a 16550-compatible UART to support PROFIBUS + +A PRU-ICSS subsystem can have up to three shared data memories. A PRU core +acts on a primary Data RAM (there are usually 2 Data RAMs) at its address +0x0, but also has access to a secondary Data RAM (primary to the other PRU +core) at its address 0x2000. A shared Data RAM, if present, can be accessed +by both the PRU cores. The Interrupt Controller (INTC) and a CFG module are +common to both the PRU cores. Each PRU core also has a private instruction RAM, +and specific register spaces for Control and Debug functionalities. + +Various sub-modules within a PRU-ICSS subsystem are represented as individual +nodes and are defined using a parent-child hierarchy depending on their +integration within the IP and the SoC. These nodes are described in the +following sections. + + +PRU-ICSS SoC Bus Parent Node +============================= +This node represents the integration of the PRU-ICSS IP into a SoC, and is +required for all SoCs. The PRU-ICSS parent nodes need to be defined as child +nodes of this node. + +Required Properties: +-------------------- +- compatible : should be one of, + "ti,am3356-pruss-soc-bus" for AM335x family of SoCs + "ti,am4376-pruss-soc-bus" for AM437x family of SoCs + "ti,am5728-pruss-soc-bus" for AM57xx family of SoCs + "ti,k2g-pruss-soc-bus" for 66AK2G family of SoCs +- reg : address and size of the PRUSS CFG sub-module registers + dictating the interconnect configuration +- #address-cells : should be 1 +- #size-cells : should be 1 +- ranges : standard ranges definition + +SoC-specific Required properties: +--------------------------------- + +The following are mandatory properties for all OMAP-architecture based SoCs: +- ti,hwmods : name of the hwmod associated with the PRUSS instance + +The following properties are _required_ only for Keystone 2 66AK2G SoCs only: +- power-domains : Should contain a phandle to a PM domain provider node and an + args specifier containing the PRUSS SCI device id value. This + property is as per the binding, + Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt + + +PRU-ICSS Parent Node +===================== +Each PRU-ICSS subsystem instance is represented as a child node of +the PRUSS SoC bus node, with the individual PRU processor cores, a +memories node, an INTC node and an MDIO node represented as child nodes +within this parent PRUSS node. + +Required Properties: +-------------------- +- compatible : should be one of, + "ti,am3356-pruss" for AM335x family of SoCs + "ti,am4376-pruss" for AM437x family of SoCs + "ti,am5728-pruss" for AM57xx family of SoCs + "ti,k2g-pruss" for 66AK2G family of SoCs +- reg : base address and size of the entire PRU-ICSS space +- interrupts : all the interrupts generated towards the main host + processor in the SoC. The format depends on the + interrupt specifier for the particular SoC's MPU + parent interrupt controller +- interrupt-names: should use one of the following names for each interrupt, + the name should match the corresponding host interrupt + number, + "host2", "host3", "host4", "host5", "host6", + "host7", "host8" or "host9" + NOTE: AM437x and 66AK2G SoCs do not have "host7" interrupt + connected to MPU +- #address-cells : should be 1 +- #size-cells : should be 1 +- ranges : no specific range translations required, child nodes have the + same address view as the parent, so should be mentioned without + any value for the property + + +PRU-ICSS Memories Node +======================= +The various Data RAMs within a PRU-ICSS are represented as a single +node with the name 'memories'. + +Required Properties: +-------------------- +- reg : base address and size for each of the Data RAMs as + mentioned in reg-names, and in the same order as the + reg-names +- reg-names : should contain a string(s) from among the following names, + each representing a specific Data RAM region. A PRU-ICSS may + not have all of the Data RAMs. The binding is agnostic + of the order of these reg-names + "dram0" for Data RAM0, + "dram1" for Data RAM1, + "shrdram2" for Shared Data RAM, + + +PRU-ICSS SysCon Nodes +====================== +The individual sub-modules CFG, IEP and MII_RT are represented as a syscon +node each for now with specific node names as below: + "cfg" for CFG sub-module, + "iep" for IEP sub-module, + "mii_rt" for MII-RT sub-module, + + +PRUSS INTC Child Node +====================== +Each PRUSS has a single interrupt controller instance that is common to both +the PRU cores. Each interrupt controller can detect 64 input events which are +then mapped to 10 possible output interrupts through two levels of mapping. The +input events can be triggered by either the PRUs and/or various other PRUSS +internal and external peripherals. The first 2 output interrupts are fed +exclusively to the internal PRU cores, with the remaining 8 connected to +external interrupt controllers including the MPU. + +Required Properties: +-------------------- +- compatible : should be one of, + "ti,am3356-pruss-intc" for AM335x family of SoCs + "ti,am4376-pruss-intc" for AM437x family of SoCs + "ti,am5728-pruss-intc" for AM57xx family of SoCs + "ti,k2g-pruss-intc" for 66AK2G family of SoCs +- reg : base address and size for the PRUSS INTC sub-module +- reg-names : should contain the string "intc" +- interrupt-controller : mark this node as an interrupt controller +- #interrupt-cells : should be 1. Client users shall use the PRU System + event number (the interrupt source that the client + is interested in) as the value of the interrupts + property in their node + + +PRU Child Node +=============== +Each PRUSS has dual PRU cores, each represented by a PRU child node. Each node +can optionally be rendered inactive by using the standard DT string property, +"status". + +Required Properties: +-------------------- +- compatible : should be + "ti,am3356-pru" for AM335x family of SoCs + "ti,am4376-pru" for AM437x family of SoCs + "ti,am5728-pru" for AM57xx family of SoCs + "ti,k2g-pru" for 66AK2G family of SoCs +- reg : base address and size for each of the 3 sub-module address + spaces as mentioned in reg-names, and in the same order as + the reg-names +- reg-names : should contain each of the following 3 names, the binding is + agnostic of the order of these reg-names + "iram" for Instruction RAM, + "control" for the CTRL sub-module registers, + "debug" for the Debug sub-module registers, +- firmware-name : should contain the name of the default firmware image file + located on the firmware search path + + +MDIO Child Node +================ +Each PRUSS has an MDIO module that can be used to control external PHYs. The +MDIO module used within the PRU-ICSS is an instance of the MDIO Controller +used in TI Davinci SoCs. Please refer to the corresponding binding document, +Documentation/devicetree/bindings/net/davinci-mdio.txt for details. + + +Example: +======== +1. /* AM33xx PRU-ICSS */ + pruss_soc_bus: pruss_soc_bus@4a326004 { + compatible = "ti,am3356-pruss-soc-bus"; + ti,hwmods = "pruss"; + reg = <0x4a326004 0x4>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pruss: pruss@4a300000 { + compatible = "ti,am3356-pruss"; + reg = <0x4a300000 0x80000>; + interrupts = <20 21 22 23 24 25 26 27>; + interrupt-names = "host2", "host3", "host4", + "host5", "host6", "host7", + "host8", "host9"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pruss_mem: memories@4a300000 { + reg = <0x4a300000 0x2000>, + <0x4a302000 0x2000>, + <0x4a310000 0x3000>; + reg-names = "dram0", "dram1", "shrdram2"; + }; + + pruss_cfg: cfg@4a326000 { + compatible = "syscon"; + reg = <0x4a326000 0x2000>; + }; + + pruss_iep: iep@4a32e000 { + compatible = "syscon"; + reg = <0x4a32e000 0x31c>; + }; + + pruss_mii_rt: mii_rt@4a332000 { + compatible = "syscon"; + reg = <0x4a332000 0x58>; + }; + + pruss_intc: intc@4a320000 { + compatible = "ti,am3356-pruss-intc"; + reg = <0x4a320000 0x2000>; + reg-names = "intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + pru0: pru@4a334000 { + compatible = "ti,am3356-pru"; + reg = <0x4a334000 0x2000>, + <0x4a322000 0x400>, + <0x4a322400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am335x-pru0-fw"; + }; + + pru1: pru@4a338000 { + compatible = "ti,am3356-pru"; + reg = <0x4a338000 0x2000>, + <0x4a324000 0x400>, + <0x4a324400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am335x-pru1-fw"; + }; + + pruss_mdio: mdio@4a332400 { + compatible = "ti,davinci_mdio"; + reg = <0x4a332400 0x90>; + clocks = <&dpll_core_m4_ck>; + clock-names = "fck"; + bus_freq = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + +2. /* AM43xx PRU-ICSS with PRUSS1 node (PRUSS0 not shown completely) */ + pruss_soc_bus: pruss_soc_bus@54426004 { + compatible = "ti,am4376-pruss-soc-bus"; + reg = <0x54426004 0x4>; + ti,hwmods = "pruss"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pruss1: pruss@54400000 { + compatible = "ti,am4376-pruss"; + reg = <0x54400000 0x40000>; + interrupts = ; + interrupt-names = "host2", "host3", "host4", + "host5", "host6", "host8", + "host9"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pruss1_mem: memories@54400000 { + reg = <0x54400000 0x2000>, + <0x54402000 0x2000>, + <0x54410000 0x8000>; + reg-names = "dram0", "dram1", "shrdram2"; + }; + + pruss1_cfg: cfg@54426000 { + compatible = "syscon"; + reg = <0x54426000 0x2000>; + }; + + pruss1_iep: iep@5442e000 { + compatible = "syscon"; + reg = <0x5442e000 0x31c>; + }; + + pruss1_mii_rt: mii_rt@54432000 { + compatible = "syscon"; + reg = <0x54432000 0x58>; + }; + + pruss1_intc: intc@54420000 { + compatible = "ti,am4376-pruss-intc"; + reg = <0x54420000 0x2000>; + reg-names = "intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + pru1_0: pru@54434000 { + compatible = "ti,am4376-pru"; + reg = <0x54434000 0x3000>, + <0x54422000 0x400>, + <0x54422400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am437x-pru1_0-fw"; + }; + + pru1_1: pru@54438000 { + compatible = "ti,am4376-pru"; + reg = <0x54438000 0x3000>, + <0x54424000 0x400>, + <0x54424400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am437x-pru1_1-fw"; + }; + + pruss1_mdio: mdio@54432400 { + compatible = "ti,davinci_mdio"; + reg = <0x54432400 0x90>; + clocks = <&dpll_core_m4_ck>; + clock-names = "fck"; + bus_freq = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + pruss0: pruss@54440000 { + compatible = "ti,am4376-pruss"; + reg = <0x54440000 0x40000>; + ... + }; + }; From patchwork Thu Nov 22 11:38:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 151752 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp627920ljp; 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[209.132.180.67]) by mx.google.com with ESMTP id w7-v6si50040491pgh.131.2018.11.22.03.39.35; Thu, 22 Nov 2018 03:39:35 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=QUARANTINE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405555AbeKVWSe (ORCPT + 32 others); Thu, 22 Nov 2018 17:18:34 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:58390 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2405540AbeKVWSc (ORCPT ); Thu, 22 Nov 2018 17:18:32 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id wAMBdSe3008384; Thu, 22 Nov 2018 05:39:28 -0600 Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wAMBdSkq106871 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 22 Nov 2018 05:39:28 -0600 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 22 Nov 2018 05:39:26 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 22 Nov 2018 05:39:26 -0600 Received: from dlelxv97.itg.ti.com (dlelxv97.itg.ti.com [172.17.2.193]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAMBdQdb011201; Thu, 22 Nov 2018 05:39:26 -0600 Received: from localhost.localdomain (vboxa0400828d.dhcp.ti.com [172.22.239.63]) by dlelxv97.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAMBdDf1013203; Thu, 22 Nov 2018 05:39:22 -0600 From: Roger Quadros To: CC: , , , , , , , , , , , , , , , , Subject: [PATCH 02/17] soc: ti: pruss: Define platform data for PRUSS bus driver Date: Thu, 22 Nov 2018 13:38:58 +0200 Message-ID: <1542886753-17625-3-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1542886753-17625-1-git-send-email-rogerq@ti.com> References: <1542886753-17625-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Suman Anna The PRUSS can have a PRCM reset line associated with the IP on some OMAP architecture based SoCs. The reset needs to be programmed properly before accessing any of the internal registers in the PRUSS. This functionality is achieved through the omap_device layer, which is not exposed outside of mach-omap2 layer. Define a platform data structure for PRUSS so that this API can be invoked through platform data ops from the driver. Signed-off-by: Suman Anna --- include/linux/platform_data/ti-pruss.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 include/linux/platform_data/ti-pruss.h -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/include/linux/platform_data/ti-pruss.h b/include/linux/platform_data/ti-pruss.h new file mode 100644 index 0000000..96a66cc --- /dev/null +++ b/include/linux/platform_data/ti-pruss.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Platform data for PRUSS on TI SoCs + * + * Copyright (C) 2014-2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#ifndef _PLAT_TI_PRUSS_H +#define _PLAT_TI_PRUSS_H + +struct platform_device; + +/** + * struct pruss_platform_data - PRUSS platform data + * @reset_name: name of the reset + * @assert_reset: PRU-specific handler for putting the device in reset + * @deassert_reset: PRU-specific handler for releasing the device from reset + */ +struct pruss_platform_data { + const char *reset_name; + int (*assert_reset)(struct platform_device *pdev, const char *name); + int (*deassert_reset)(struct platform_device *pdev, const char *name); +}; + +#endif /* _PLAT_TI_PRUSS_H */ From patchwork Thu Nov 22 11:38:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 151753 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp627958ljp; Thu, 22 Nov 2018 03:39:37 -0800 (PST) X-Google-Smtp-Source: AFSGD/VlZ3dx3sluar7bxqYcV+64lf7+EN2mePt9Pm1xgcGq/6COp3K8NzxLvI6XYb/axfRKpn2i X-Received: by 2002:a17:902:c5:: with SMTP id a63mr10823503pla.267.1542886777563; Thu, 22 Nov 2018 03:39:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542886777; cv=none; d=google.com; s=arc-20160816; b=pJAJefaQivRtJyMH9j7P9EeiIDlORYAd9r1xst/3bf0eON5frPgyX9Lre5YEP2UgEA MJ8ObTvOL5ryWdJAkoEY+CBaYEH+Flxz22yUQU+P6eUFZdHEzbN16Z6GsW9KsA2dymOt l605B4x5iQkQWNQS88DxJivYy6F00RrQANBcILhwCV7VDCNmo5buEitogbTOKdVqR/ZZ 3ELYBev7mNNvZOdlQywWjGvO3E5faPMDMUyJOukD803vvjvNPysK4UKpZAtoFsaoMcId H/o5GCKT1Fq8yHusqYDa8jEYVpjEvQfH9faNEot8r4/0BHKApg8n69DE0WzvZVFUCBOM w6Mw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=l8EaJ/3pWE8PUD6eVg1qaCX+cy1kmh/AyeShSjrRSRw=; b=jrtjEPFQjMfSxX9fcjma96lvuh85COWrXWWooLBBUS08G/QP2YCWWP3vIosBvaZKOC YJ9F8JVsE//RuqwLzlYm59upvWq2wG52fae5+0NsludQughKcdiGQyWryncC37ppdAPr L43X/etYlj/6hPV8JcQXn9DAxE875rosOa8TO1i256f5HwFszBdOrKA2W76kpxOnWVgJ FrZVq/STMlZM4jXMkZ+EHhDyAG7eJ/q0nzr9a3CHjWtSdUwlAwE8Z5/p0VSlFx7XeXjF 5dJdkkJkD4o2DMBvPdUqYZD8iZzaRCwIvhDPnUL5Mq/r3mWYGX+2tjYBmMq6t+/ynLi3 7pkg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=rZjWOviQ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v16-v6si50201598plo.417.2018.11.22.03.39.37; Thu, 22 Nov 2018 03:39:37 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=rZjWOviQ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405569AbeKVWSf (ORCPT + 32 others); Thu, 22 Nov 2018 17:18:35 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:50380 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2405550AbeKVWSe (ORCPT ); Thu, 22 Nov 2018 17:18:34 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id wAMBdUt3075756; Thu, 22 Nov 2018 05:39:31 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1542886771; bh=l8EaJ/3pWE8PUD6eVg1qaCX+cy1kmh/AyeShSjrRSRw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=rZjWOviQifrFquBfPuMHTnLu5pSAlZGv7xJrKwgJ6EZTTtXXCPafD3bVWMaczi7Bx U1+3bls6I7y4dFuh6G0i1dLb785Oa5pzTuPRb3MJnHylIw61Kij3EE9pAQz1Ml9H6k wDsWYxubSWLsGLduFI5zOQVKXb4dSlsV+drKg4NM= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wAMBdU0R029349 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 22 Nov 2018 05:39:30 -0600 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 22 Nov 2018 05:39:30 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 22 Nov 2018 05:39:30 -0600 Received: from dlelxv97.itg.ti.com (dlelxv97.itg.ti.com [172.17.2.193]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAMBdUmR027293; Thu, 22 Nov 2018 05:39:30 -0600 Received: from localhost.localdomain (vboxa0400828d.dhcp.ti.com [172.22.239.63]) by dlelxv97.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAMBdDf2013203; Thu, 22 Nov 2018 05:39:26 -0600 From: Roger Quadros To: CC: , , , , , , , , , , , , , , , , Subject: [PATCH 03/17] soc: ti: pruss: Add pruss_soc_bus platform driver Date: Thu, 22 Nov 2018 13:38:59 +0200 Message-ID: <1542886753-17625-4-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1542886753-17625-1-git-send-email-rogerq@ti.com> References: <1542886753-17625-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Suman Anna The Programmable Real-Time Unit - Industrial Communication Subsystem (PRU-ICSS) is present of various TI SoCs such as AM335x or AM437x or the Keystone 66AK2G. Each SoC can have one or more PRUSS instances that may or may not be identical. For example, AM335x SoCs have a single PRUSS, while AM437x has two PRUSS instances PRUSS1 and PRUSS0, with the PRUSS0 being a cut-down version of the PRUSS1. The PRUSS consists of dual 32-bit RISC cores called the Programmable Real-Time Units (PRUs), some shared, data and instruction memories, some internal peripheral modules, and an interrupt controller. The programmable nature of the PRUs provide flexibility to implement custom peripheral interfaces, fast real-time responses, or specialized data handling. The PRU-ICSS functionality is achieved through four different modules, each implementing a platform driver addressing a specific portion of the PRUSS. Some sub-modules of the PRU-ICSS IP reuse some of the existing drivers (like davinci mdio driver or the generic syscon driver). The pruss_soc_bus driver deals with the SoC integration aspects of the PRUSS IP(s) and manages the common clock, reset and interconnect configuration and creates the child PRUSS devices. The second pruss driver is responsible for the creation and deletion of various platform devices for the child PRU device and other child devices. A third driver manages the PRUSS interrupt controller and implements an irqchip driver to provide a Linux standard way of interrupt management to PRU clients. The fourth platform driver is a remoteproc driver and performs the individual PRU RISC cores management. This design provides flexibility in representing the different modules of PRUSS accordingly. This patch introduces the first part i.e. pruss_soc_bus driver. The driver currently supports the AM335x SoC. Signed-off-by: Suman Anna Signed-off-by: Keerthy Signed-off-by: Roger Quadros --- drivers/soc/ti/Kconfig | 11 ++++ drivers/soc/ti/Makefile | 1 + drivers/soc/ti/pruss_soc_bus.c | 142 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 154 insertions(+) create mode 100644 drivers/soc/ti/pruss_soc_bus.c -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig index be4570b..d1ea6da 100644 --- a/drivers/soc/ti/Kconfig +++ b/drivers/soc/ti/Kconfig @@ -73,4 +73,15 @@ config TI_SCI_PM_DOMAINS called ti_sci_pm_domains. Note this is needed early in boot before rootfs may be available. +config TI_PRUSS + tristate "TI PRU-ICSS Subsystem Platform drivers" + depends on SOC_AM33XX + default n + help + TI PRU-ICSS Subsystem platform specific support. + + Say Y or M here to support the Programmable Realtime Unit (PRU) + processors on various TI SoCs. It's safe to say N here if you're + not interested in the PRU or if you are unsure. + endif # SOC_TI diff --git a/drivers/soc/ti/Makefile b/drivers/soc/ti/Makefile index a22edc0..ac6b695 100644 --- a/drivers/soc/ti/Makefile +++ b/drivers/soc/ti/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_KEYSTONE_NAVIGATOR_DMA) += knav_dma.o obj-$(CONFIG_AMX3_PM) += pm33xx.o obj-$(CONFIG_WKUP_M3_IPC) += wkup_m3_ipc.o obj-$(CONFIG_TI_SCI_PM_DOMAINS) += ti_sci_pm_domains.o +obj-$(CONFIG_TI_PRUSS) += pruss_soc_bus.o diff --git a/drivers/soc/ti/pruss_soc_bus.c b/drivers/soc/ti/pruss_soc_bus.c new file mode 100644 index 0000000..16b4802 --- /dev/null +++ b/drivers/soc/ti/pruss_soc_bus.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PRU-ICSS SoC bus driver for various TI SoCs + * + * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Suman Anna + * Keerthy + */ + +#include +#include +#include +#include +#include +#include + +#include + +/** + * struct pruss_soc_bus - PRUSS SoC bus structure + * @syscfg: kernel mapped address for SYSCFG register + * @has_reset: cached variable for storing global module reset flag + */ +struct pruss_soc_bus { + void __iomem *syscfg; + bool has_reset; +}; + +/** + * struct pruss_soc_bus_match_data - PRUSS SoC bus driver match data + * @has_reset: flag to indicate the presence of global module reset + */ +struct pruss_soc_bus_match_data { + bool has_reset; +}; + +static int pruss_soc_bus_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct pruss_platform_data *pdata = dev_get_platdata(dev); + struct pruss_soc_bus *psoc_bus; + const struct pruss_soc_bus_match_data *data; + int ret; + + psoc_bus = devm_kzalloc(dev, sizeof(*psoc_bus), GFP_KERNEL); + if (!psoc_bus) + return -ENOMEM; + + psoc_bus->syscfg = of_iomap(node, 0); + if (!psoc_bus->syscfg) + return -ENOMEM; + + data = of_device_get_match_data(dev); + if (!data) { + dev_err(dev, "missing match data\n"); + return -ENODEV; + } + + if (data->has_reset && (!pdata || !pdata->deassert_reset || + !pdata->assert_reset || !pdata->reset_name)) { + dev_err(dev, "platform data (reset configuration information) missing\n"); + return -ENODEV; + } + psoc_bus->has_reset = data->has_reset; + platform_set_drvdata(pdev, psoc_bus); + + if (psoc_bus->has_reset) { + ret = pdata->deassert_reset(pdev, pdata->reset_name); + if (ret) { + dev_err(dev, "deassert_reset failed: %d\n", ret); + goto fail_reset; + } + } + + pm_runtime_enable(dev); + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + pm_runtime_put_noidle(dev); + goto fail_clock; + } + + ret = of_platform_populate(node, NULL, NULL, dev); + if (ret) + goto fail_of; + + return 0; + +fail_of: + pm_runtime_put_sync(dev); +fail_clock: + pm_runtime_disable(dev); + if (psoc_bus->has_reset) + pdata->assert_reset(pdev, pdata->reset_name); +fail_reset: + iounmap(psoc_bus->syscfg); + return ret; +} + +static int pruss_soc_bus_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct pruss_platform_data *pdata = dev_get_platdata(dev); + struct pruss_soc_bus *psoc_bus = platform_get_drvdata(pdev); + + of_platform_depopulate(dev); + + pm_runtime_put_sync(dev); + pm_runtime_disable(dev); + + if (psoc_bus->has_reset) + pdata->assert_reset(pdev, pdata->reset_name); + iounmap(psoc_bus->syscfg); + + return 0; +} + +/* instance-specific driver private data */ +static const struct pruss_soc_bus_match_data am335x_data = { + .has_reset = true, +}; + +static const struct of_device_id pruss_soc_bus_of_match[] = { + { .compatible = "ti,am3356-pruss-soc-bus", .data = &am335x_data, }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, pruss_soc_bus_of_match); + +static struct platform_driver pruss_soc_bus_driver = { + .driver = { + .name = "pruss-soc-bus", + .of_match_table = pruss_soc_bus_of_match, + }, + .probe = pruss_soc_bus_probe, + .remove = pruss_soc_bus_remove, +}; +module_platform_driver(pruss_soc_bus_driver); + +MODULE_AUTHOR("Suman Anna "); +MODULE_AUTHOR("Keerthy "); +MODULE_DESCRIPTION("PRU-ICSS SoC Bus Driver for TI SoCs"); +MODULE_LICENSE("GPL v2"); From patchwork Thu Nov 22 11:39:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 151754 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp628043ljp; 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[209.132.180.67]) by mx.google.com with ESMTP id v5si36542340ply.74.2018.11.22.03.39.42; Thu, 22 Nov 2018 03:39:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=oP5igHjv; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2436487AbeKVWSl (ORCPT + 32 others); Thu, 22 Nov 2018 17:18:41 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:41972 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2405572AbeKVWSk (ORCPT ); Thu, 22 Nov 2018 17:18:40 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id wAMBdb9F022534; Thu, 22 Nov 2018 05:39:37 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1542886777; bh=wid2SPnwYAS8OrDuPNeFfDxOtgHDrKisgze3uUQ/47A=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=oP5igHjvdpz6N+rdhOf4a0gDZNlRzmFMOXngvZGz7sFwQpeIDPRjp5dEEsnhr9W2r sl0if1ofabNQnS+O0lSLhxxm98dNKWUWyrZ2gcbTPKH55q9EqzLhBwdFiRq9Ssqnvs gJvzHFJv6MYNv4y3N1ROb+17Lu9VZdiu78tm+bqI= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wAMBdb4q106946 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 22 Nov 2018 05:39:37 -0600 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 22 Nov 2018 05:39:34 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 22 Nov 2018 05:39:34 -0600 Received: from dlelxv97.itg.ti.com (dlelxv97.itg.ti.com [172.17.2.193]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAMBdYq9017630; Thu, 22 Nov 2018 05:39:34 -0600 Received: from localhost.localdomain (vboxa0400828d.dhcp.ti.com [172.22.239.63]) by dlelxv97.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAMBdDf3013203; Thu, 22 Nov 2018 05:39:30 -0600 From: Roger Quadros To: CC: , , , , , , , , , , , , , , , , Subject: [PATCH 04/17] soc: ti: pruss: Fix system suspend/MStandby config issues Date: Thu, 22 Nov 2018 13:39:00 +0200 Message-ID: <1542886753-17625-5-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1542886753-17625-1-git-send-email-rogerq@ti.com> References: <1542886753-17625-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Suman Anna The PRU-ICSS subsystem has a separate PRUSS_CFG module that contains various configuration registers. This includes a control bit STANDBY_INIT in PRUSS_CFG register to initiate a Standby sequence (when set) and trigger a MStandby request to the SoC's PRCM module. This same bit is also used to enable the OCP master ports (when cleared). The system suspend/resume functionality on AM33xx/AM437x/AM57xx SoCs requires all initiators to assert their MStandby signal properly inorder to successfully enter suspend, and resume on a wakeup event. Certain firmwares can enable the OCP master ports through the STANDBY_INIT programming on the firmware side in order to access peripherals or memories external to the PRUSS. This causes a hang in the resume sequence on AM33xx/AM437x boards and requires a board reset to come out of the hang. This patch adds the preliminary System PM callbacks in the PRUSS SoC bus driver, and fixes this system resume hang by setting the STANDBY_INIT in the PM system suspend callback and resetting it back in the PM system resume callback, if so configured. The clearing of the STANDBY_INIT during resume requires an acknowledgment from PRCM and is done through the monitoring of the PRUSS_SYSCFG.SUB_MWAIT bit. NOTE: 1. This patch only adds the PM callbacks with code to fix the System Suspend/Resume hang issue on AM33xx/AM437x SoCs, but does not implement the full context save and restore required for the PRUSS drivers to work across system suspend/resume when the power domain is switched off (L4PER domain is switched OFF on AM335x/AM437x during system suspend/resume, so PRUSS modules do lose context). 2. The PRUSS driver functionality on AM57xx SoCs is not affected that much because the PER power domain to which the PRUSS IPs belong is not switched OFF during suspend/resume. Signed-off-by: Suman Anna Signed-off-by: Roger Quadros --- drivers/soc/ti/pruss_soc_bus.c | 85 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/pruss_soc_bus.c b/drivers/soc/ti/pruss_soc_bus.c index 16b4802..d4da55d2 100644 --- a/drivers/soc/ti/pruss_soc_bus.c +++ b/drivers/soc/ti/pruss_soc_bus.c @@ -7,6 +7,7 @@ * Keerthy */ +#include #include #include #include @@ -16,13 +17,18 @@ #include +#define SYSCFG_STANDBY_INIT BIT(4) +#define SYSCFG_SUB_MWAIT_READY BIT(5) + /** * struct pruss_soc_bus - PRUSS SoC bus structure * @syscfg: kernel mapped address for SYSCFG register + * @in_standby: flag for storing standby status * @has_reset: cached variable for storing global module reset flag */ struct pruss_soc_bus { void __iomem *syscfg; + bool in_standby; bool has_reset; }; @@ -34,6 +40,81 @@ struct pruss_soc_bus_match_data { bool has_reset; }; +static inline void pruss_soc_bus_rmw(void __iomem *reg, u32 mask, u32 set) +{ + u32 val; + + val = readl_relaxed(reg); + val &= ~mask; + val |= (set & mask); + writel_relaxed(val, reg); +} + +/* + * This function programs the PRUSS_SYSCFG.STANDBY_INIT bit to achieve dual + * functionalities - one is to deassert the MStandby signal to the device + * PRCM, and the other is to enable OCP master ports to allow accesses + * outside of the PRU-ICSS. The function has to wait for the PRCM to + * acknowledge through the monitoring of the PRUSS_SYSCFG.SUB_MWAIT bit. + */ +static +int __maybe_unused pruss_soc_bus_enable_ocp_master_ports(struct device *dev) +{ + struct pruss_soc_bus *psoc_bus = dev_get_drvdata(dev); + u32 syscfg_val, i; + bool ready = false; + + pruss_soc_bus_rmw(psoc_bus->syscfg, SYSCFG_STANDBY_INIT, 0); + + /* wait till we are ready for transactions - delay is arbitrary */ + for (i = 0; i < 10; i++) { + syscfg_val = readl_relaxed(psoc_bus->syscfg); + ready = !(syscfg_val & SYSCFG_SUB_MWAIT_READY); + if (ready) + break; + udelay(5); + } + + if (!ready) { + dev_err(dev, "timeout waiting for SUB_MWAIT_READY\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static int __maybe_unused pruss_soc_bus_suspend(struct device *dev) +{ + struct pruss_soc_bus *psoc_bus = dev_get_drvdata(dev); + u32 syscfg_val; + + syscfg_val = readl_relaxed(psoc_bus->syscfg); + psoc_bus->in_standby = syscfg_val & SYSCFG_STANDBY_INIT; + + /* initiate MStandby, undo the MStandby config in probe */ + if (!psoc_bus->in_standby) { + pruss_soc_bus_rmw(psoc_bus->syscfg, SYSCFG_STANDBY_INIT, + SYSCFG_STANDBY_INIT); + } + + return 0; +} + +static int __maybe_unused pruss_soc_bus_resume(struct device *dev) +{ + struct pruss_soc_bus *psoc_bus = dev_get_drvdata(dev); + int ret = 0; + + /* re-enable OCP master ports/disable MStandby */ + if (!psoc_bus->in_standby) { + ret = pruss_soc_bus_enable_ocp_master_ports(dev); + if (ret) + dev_err(dev, "%s failed\n", __func__); + } + + return ret; +} + static int pruss_soc_bus_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -126,9 +207,13 @@ static const struct of_device_id pruss_soc_bus_of_match[] = { }; MODULE_DEVICE_TABLE(of, pruss_soc_bus_of_match); +static SIMPLE_DEV_PM_OPS(pruss_soc_bus_pm_ops, + pruss_soc_bus_suspend, pruss_soc_bus_resume); + static struct platform_driver pruss_soc_bus_driver = { .driver = { .name = "pruss-soc-bus", + .pm = &pruss_soc_bus_pm_ops, .of_match_table = pruss_soc_bus_of_match, }, .probe = pruss_soc_bus_probe, From patchwork Thu Nov 22 11:39:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 151755 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp628149ljp; Thu, 22 Nov 2018 03:39:48 -0800 (PST) X-Google-Smtp-Source: AFSGD/XjatzzBQAFbF50TVbXaicYXA0bzISfTXKa+0ondkNhYTDBcwsp9ahNX2Bpr1W7c06g5PHj X-Received: by 2002:a17:902:b104:: with SMTP id q4-v6mr11004776plr.5.1542886788045; Thu, 22 Nov 2018 03:39:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542886788; cv=none; d=google.com; s=arc-20160816; b=kgapO98CSuC4RnHJEFRqU5Ml7c2Tlwd/TIsKRVMfJ5xEOyiq0BBg5osTGXcULfenxY 2cZgt0oxmFROJADZcvez+PPCWS4HQCMyDxp4A2bpyEjJt/TAy+Nxu4T81e9YBvogcw97 8ahZeZ6i0LbKLdZ577flrPWvj319LVByPwcreXISuNM16DAIYF990fffJwbqHPZpdRt2 jjm3LcxKPWDfM2rfMv4e7P1cekAa+CIHCpAbtrxfgiTSM03/jC1Gke6wkl2OGFx4+GC3 MQ7gZXC8fDCTutDya6Lq3Wy5Xy6KA2JzGxwWGvP9hDrPJn/hMZ8DxXQo3yjY+V0YpTAk Ljbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=vxyCHXR1JMyg6Q9lFruUOMrUzaWNOqUp0GPab0Yz8Rk=; b=RDbDlilblxzyQLgMg1JsnCppudOyE6q7srl08VdiRtu26U8qWKPihQZipPvT/2CxiM SoOASCWPZ87pcukb0Qjd35xvLHgZNoY3E77ANhKI916ZA57xB1A2TXqQdD6tvUidkXhr 71eAbniutJ07w+y6otd07Lt+m/PWHmc/9cdahUd9j9Fd1fcZGRF7FI2TlokUR+BJ8TV3 DIMQRt9E9JNwUE6sp7wfDRbhv9HVlbei2Z0sTW/NKE7U6T/yMyFtFx2txuDiM/kd4p3V koap6j9qSY/guM1EdQlOsMVmsJglYhUK4jCJFDZ0UOPvHW7hEoYgJguBomxk3h18hdxG NYQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=J3bCFcup; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y6si32848306pll.384.2018.11.22.03.39.47; Thu, 22 Nov 2018 03:39:48 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=J3bCFcup; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2436498AbeKVWSq (ORCPT + 32 others); Thu, 22 Nov 2018 17:18:46 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:35414 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2405550AbeKVWSp (ORCPT ); Thu, 22 Nov 2018 17:18:45 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id wAMBdfrd078031; Thu, 22 Nov 2018 05:39:41 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1542886781; bh=vxyCHXR1JMyg6Q9lFruUOMrUzaWNOqUp0GPab0Yz8Rk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=J3bCFcupOggCja41aIAQA9OXTRiGuJ9Tojqb4NDru3MPPJoBTdDDoES+1lLAJT04Z uyDHabqPkP00Gkdt9++W0ha7etBV73on5LFk92CDg2Tizamv70o+bDtY5oSJcxLf1k krYRPv8NUj1+Iu7CVDu2ZJSqKnzu8hHqTzmQKRqw= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wAMBdfQQ076850 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 22 Nov 2018 05:39:41 -0600 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 22 Nov 2018 05:39:38 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 22 Nov 2018 05:39:38 -0600 Received: from dlelxv97.itg.ti.com (dlelxv97.itg.ti.com [172.17.2.193]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAMBdcj2024667; Thu, 22 Nov 2018 05:39:38 -0600 Received: from localhost.localdomain (vboxa0400828d.dhcp.ti.com [172.22.239.63]) by dlelxv97.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAMBdDf4013203; Thu, 22 Nov 2018 05:39:34 -0600 From: Roger Quadros To: CC: , , , , , , , , , , , , , , , , Subject: [PATCH 05/17] soc: ti: pruss: Configure SYSCFG properly during probe/remove Date: Thu, 22 Nov 2018 13:39:01 +0200 Message-ID: <1542886753-17625-6-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1542886753-17625-1-git-send-email-rogerq@ti.com> References: <1542886753-17625-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Suman Anna The PRUSS CFG module's SYSCFG register is used for managing the PRCM clock management settings at the PRU-ICSS subsystem level. Add two helper functions pruss_{enable/disable}_module() that programs this SYSCFG register during probe and remove. The register is currently programmed for the default Smart-Idle and Smart-Standby always during probe. The MStandby is enabled during remove to undo the settings in probe to properly configure the SYSCFG in the case that a firmware has disabled MStandby. This is needed on SoCs like AM57xx that do not have a reset line and so cannot reset the register properly. Signed-off-by: Suman Anna Signed-off-by: Roger Quadros --- drivers/soc/ti/pruss_soc_bus.c | 60 +++++++++++++++++++++++++++++++++++++----- 1 file changed, 54 insertions(+), 6 deletions(-) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/pruss_soc_bus.c b/drivers/soc/ti/pruss_soc_bus.c index d4da55d2..46dfb7a 100644 --- a/drivers/soc/ti/pruss_soc_bus.c +++ b/drivers/soc/ti/pruss_soc_bus.c @@ -20,6 +20,16 @@ #define SYSCFG_STANDBY_INIT BIT(4) #define SYSCFG_SUB_MWAIT_READY BIT(5) +#define SYSCFG_STANDBY_MODE_FORCE (0 << 2) +#define SYSCFG_STANDBY_MODE_NO (1 << 2) +#define SYSCFG_STANDBY_MODE_SMART (2 << 2) +#define SYSCFG_STANDBY_MODE_MASK (3 << 2) + +#define SYSCFG_IDLE_MODE_FORCE 0 +#define SYSCFG_IDLE_MODE_NO 1 +#define SYSCFG_IDLE_MODE_SMART 2 +#define SYSCFG_IDLE_MODE_MASK 3 + /** * struct pruss_soc_bus - PRUSS SoC bus structure * @syscfg: kernel mapped address for SYSCFG register @@ -115,6 +125,44 @@ static int __maybe_unused pruss_soc_bus_resume(struct device *dev) return ret; } +/* firmware must be idle when calling this function */ +static void pruss_disable_module(struct device *dev) +{ + struct pruss_soc_bus *psoc_bus = dev_get_drvdata(dev); + + /* configure Smart Standby */ + pruss_soc_bus_rmw(psoc_bus->syscfg, SYSCFG_STANDBY_MODE_MASK, + SYSCFG_STANDBY_MODE_SMART); + + /* initiate MStandby */ + pruss_soc_bus_rmw(psoc_bus->syscfg, SYSCFG_STANDBY_INIT, + SYSCFG_STANDBY_INIT); + + /* tell PRCM to initiate IDLE request */ + pm_runtime_put_sync(dev); +} + +static int pruss_enable_module(struct device *dev) +{ + struct pruss_soc_bus *psoc_bus = dev_get_drvdata(dev); + int ret; + + /* tell PRCM to de-assert IDLE request */ + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + pm_runtime_put_noidle(dev); + return ret; + } + + /* configure for Smart Idle & Smart Standby */ + pruss_soc_bus_rmw(psoc_bus->syscfg, SYSCFG_IDLE_MODE_MASK, + SYSCFG_IDLE_MODE_SMART); + pruss_soc_bus_rmw(psoc_bus->syscfg, SYSCFG_STANDBY_MODE_MASK, + SYSCFG_STANDBY_MODE_SMART); + + return ret; +} + static int pruss_soc_bus_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -155,10 +203,10 @@ static int pruss_soc_bus_probe(struct platform_device *pdev) } pm_runtime_enable(dev); - ret = pm_runtime_get_sync(dev); + ret = pruss_enable_module(dev); if (ret < 0) { - pm_runtime_put_noidle(dev); - goto fail_clock; + dev_err(dev, "couldn't enable module\n"); + goto fail_module; } ret = of_platform_populate(node, NULL, NULL, dev); @@ -168,8 +216,8 @@ static int pruss_soc_bus_probe(struct platform_device *pdev) return 0; fail_of: - pm_runtime_put_sync(dev); -fail_clock: + pruss_disable_module(dev); +fail_module: pm_runtime_disable(dev); if (psoc_bus->has_reset) pdata->assert_reset(pdev, pdata->reset_name); @@ -186,7 +234,7 @@ static int pruss_soc_bus_remove(struct platform_device *pdev) of_platform_depopulate(dev); - pm_runtime_put_sync(dev); + pruss_disable_module(dev); pm_runtime_disable(dev); if (psoc_bus->has_reset) From patchwork Thu Nov 22 11:39:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 151756 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp628198ljp; Thu, 22 Nov 2018 03:39:51 -0800 (PST) X-Google-Smtp-Source: AFSGD/Wy4E5IP1VmDTqw25mtLuFuBlp5wVVBaIfcjS5rfYa+3HXItrUejRxrU95nNwrhhEWuwwZg X-Received: by 2002:a63:9e58:: with SMTP id r24mr10033370pgo.264.1542886791324; Thu, 22 Nov 2018 03:39:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542886791; cv=none; d=google.com; s=arc-20160816; b=Ck+qx+w+QUMhb+fCWhgl1AqpF1u49WSGRmOPwJIYX6n7JacSP2+wPwh+8YIxi+kkJK KMepjY+ramLEd1Hf8dRnyZRI8A9bY0i6Ic8P7HR5vPkXaQnmMSX2gyWipAjGHONuQJvN KecxJUvLQYphJME76QqX/t9b7B+JppyekQ6lD/8PNtqxt3Fe1ddljfAwxUWakFC45HRk VBdnAtDV2s0izSwtNfLGA6e0TsvSE6o1eHQJNlzgob2p6QZG2LjP/tZPQ49xrauGTM/J qTuK8vbptIEk0A4ujjey1b/ZmvaIz5yg9AVKzgw0/MAp9KzHJL+zEzLrgJ5zG/hKsTWN fTFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=aaZ/jobFgzIocx05nqhftnRIG+zzXmeHGMAhQym+Kf0=; b=Txj5jbSskXln6Ag7RdTu6TY/g+wd29T8ADiQHutwemOX+oj94NJv5bKrB3NmRWWuaz TUCGWO7JCGHSCpN6jVRh20+DuTtucFROTgjzG7hJezWDoavsABi+QKLbU0Z16Ni2CNPs CfVNC8Pjxxa8m3HTkNuy49p6qfET3WlzhJ+kt9GBqHCTDbFyIl68QfgBrTaksCSoFvHc qZsSNFss+7o2K/WDYpcgPjBnVOZLUD3TDGIJCQ6QooBnsT08mfJJx7zd+wtCIYisPrK0 5BdWIjlfA9PSVLSr7nnZfYgn+IZVKTs0r/pxbhA0zJvL0Ya5UYvy7EFbQN+JC8VZacMt zzYg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=QUARANTINE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y6si32848306pll.384.2018.11.22.03.39.50; Thu, 22 Nov 2018 03:39:51 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=QUARANTINE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2436514AbeKVWSu (ORCPT + 32 others); Thu, 22 Nov 2018 17:18:50 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:58428 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2405550AbeKVWSt (ORCPT ); Thu, 22 Nov 2018 17:18:49 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id wAMBdj6h008444; Thu, 22 Nov 2018 05:39:45 -0600 Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wAMBdjP0076880 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 22 Nov 2018 05:39:45 -0600 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 22 Nov 2018 05:39:42 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 22 Nov 2018 05:39:42 -0600 Received: from dlelxv97.itg.ti.com (dlelxv97.itg.ti.com [172.17.2.193]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAMBdgdM024692; Thu, 22 Nov 2018 05:39:42 -0600 Received: from localhost.localdomain (vboxa0400828d.dhcp.ti.com [172.22.239.63]) by dlelxv97.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAMBdDf5013203; Thu, 22 Nov 2018 05:39:38 -0600 From: Roger Quadros To: CC: , , , , , , , , , , , , , , , , Subject: [PATCH 06/17] soc: ti: pruss: Add a platform driver for PRUSS in TI SoCs Date: Thu, 22 Nov 2018 13:39:02 +0200 Message-ID: <1542886753-17625-7-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1542886753-17625-1-git-send-email-rogerq@ti.com> References: <1542886753-17625-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Suman Anna The PRUSS platform driver deals with the overall PRUSS and is used for managing the subsystem level resources like various memories. It is responsible for the creation and deletion of the platform devices for the child PRU devices and other child devices (Interrupt Controller or MDIO node or some syscon nodes) so that they can be managed by specific platform drivers. This design provides flexibility in representing the different modules of PRUSS accordingly, and at the same time allowing the PRUSS driver to add some instance specific configuration within an SoC. The driver currently supports the AM335x SoC. Signed-off-by: Suman Anna Signed-off-by: Andrew F. Davis Signed-off-by: Roger Quadros --- drivers/soc/ti/Makefile | 2 +- drivers/soc/ti/pruss.c | 116 ++++++++++++++++++++++++++++++++++++++++++++++++ drivers/soc/ti/pruss.h | 44 ++++++++++++++++++ 3 files changed, 161 insertions(+), 1 deletion(-) create mode 100644 drivers/soc/ti/pruss.c create mode 100644 drivers/soc/ti/pruss.h -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/Makefile b/drivers/soc/ti/Makefile index ac6b695..5a0c89d 100644 --- a/drivers/soc/ti/Makefile +++ b/drivers/soc/ti/Makefile @@ -8,4 +8,4 @@ obj-$(CONFIG_KEYSTONE_NAVIGATOR_DMA) += knav_dma.o obj-$(CONFIG_AMX3_PM) += pm33xx.o obj-$(CONFIG_WKUP_M3_IPC) += wkup_m3_ipc.o obj-$(CONFIG_TI_SCI_PM_DOMAINS) += ti_sci_pm_domains.o -obj-$(CONFIG_TI_PRUSS) += pruss_soc_bus.o +obj-$(CONFIG_TI_PRUSS) += pruss_soc_bus.o pruss.o diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c new file mode 100644 index 0000000..0840b59 --- /dev/null +++ b/drivers/soc/ti/pruss.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PRU-ICSS platform driver for various TI SoCs + * + * Copyright (C) 2014-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Suman Anna + * Andrew F. Davis + */ + +#include +#include +#include +#include +#include + +#include "pruss.h" + +static int pruss_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct device_node *np; + struct pruss *pruss; + struct resource res; + int ret, i, index; + const char *mem_names[PRUSS_MEM_MAX] = { "dram0", "dram1", "shrdram2" }; + + if (!node) { + dev_err(dev, "Non-DT platform device not supported\n"); + return -ENODEV; + } + + ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); + if (ret) { + dev_err(dev, "dma_set_coherent_mask: %d\n", ret); + return ret; + } + + pruss = devm_kzalloc(dev, sizeof(*pruss), GFP_KERNEL); + if (!pruss) + return -ENOMEM; + + pruss->dev = dev; + + np = of_get_child_by_name(node, "memories"); + if (!np) + return -ENODEV; + + for (i = 0; i < ARRAY_SIZE(mem_names); i++) { + index = of_property_match_string(np, "reg-names", mem_names[i]); + if (index < 0) { + of_node_put(np); + return index; + } + + if (of_address_to_resource(np, index, &res)) { + of_node_put(np); + return -EINVAL; + } + + pruss->mem_regions[i].va = devm_ioremap(dev, res.start, + resource_size(&res)); + if (!pruss->mem_regions[i].va) { + dev_err(dev, "failed to parse and map memory resource %d %s\n", + i, mem_names[i]); + of_node_put(np); + return -ENOMEM; + } + pruss->mem_regions[i].pa = res.start; + pruss->mem_regions[i].size = resource_size(&res); + + dev_dbg(dev, "memory %8s: pa %pa size 0x%zx va %p\n", + mem_names[i], &pruss->mem_regions[i].pa, + pruss->mem_regions[i].size, pruss->mem_regions[i].va); + } + of_node_put(np); + + platform_set_drvdata(pdev, pruss); + + dev_info(&pdev->dev, "creating PRU cores and other child platform devices\n"); + ret = of_platform_populate(node, NULL, NULL, &pdev->dev); + if (ret) + dev_err(dev, "of_platform_populate failed\n"); + + return ret; +} + +static int pruss_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + + dev_info(dev, "remove PRU cores and other child platform devices\n"); + of_platform_depopulate(dev); + + return 0; +} + +static const struct of_device_id pruss_of_match[] = { + { .compatible = "ti,am3356-pruss", }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, pruss_of_match); + +static struct platform_driver pruss_driver = { + .driver = { + .name = "pruss", + .of_match_table = pruss_of_match, + }, + .probe = pruss_probe, + .remove = pruss_remove, +}; +module_platform_driver(pruss_driver); + +MODULE_AUTHOR("Suman Anna "); +MODULE_DESCRIPTION("PRU-ICSS Subsystem Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/soc/ti/pruss.h b/drivers/soc/ti/pruss.h new file mode 100644 index 0000000..dbdf475 --- /dev/null +++ b/drivers/soc/ti/pruss.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * PRU-ICSS sub-system specific definitions + * + * Copyright (C) 2014-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Suman Anna + */ + +#ifndef _PRUSS_H_ +#define _PRUSS_H_ + +/** + * enum pruss_mem - PRUSS memory range identifiers + */ +enum pruss_mem { + PRUSS_MEM_DRAM0 = 0, + PRUSS_MEM_DRAM1, + PRUSS_MEM_SHRD_RAM2, + PRUSS_MEM_MAX, +}; + +/** + * struct pruss_mem_region - PRUSS memory region structure + * @va: kernel virtual address of the PRUSS memory region + * @pa: physical (bus) address of the PRUSS memory region + * @size: size of the PRUSS memory region + */ +struct pruss_mem_region { + void __iomem *va; + phys_addr_t pa; + size_t size; +}; + +/** + * struct pruss - PRUSS parent structure + * @dev: pruss device pointer + * @mem_regions: data for each of the PRUSS memory regions + */ +struct pruss { + struct device *dev; + struct pruss_mem_region mem_regions[PRUSS_MEM_MAX]; +}; + +#endif /* _PRUSS_H_ */ From patchwork Thu Nov 22 11:39:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 151757 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp628335ljp; Thu, 22 Nov 2018 03:39:55 -0800 (PST) X-Google-Smtp-Source: AJdET5fzN6STvkllXwcN3oKUwclDUXKNR0170rq4Iln2agqAI3IrD51g0vMYBYvRhJoiCkACWuEE X-Received: by 2002:a62:1c7:: with SMTP id 190mr11154684pfb.46.1542886795216; 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[209.132.180.67]) by mx.google.com with ESMTP id 38si49041782pgx.460.2018.11.22.03.39.54; Thu, 22 Nov 2018 03:39:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=QUARANTINE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2436530AbeKVWSx (ORCPT + 32 others); Thu, 22 Nov 2018 17:18:53 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:58460 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2405550AbeKVWSv (ORCPT ); Thu, 22 Nov 2018 17:18:51 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id wAMBdlCC008454; Thu, 22 Nov 2018 05:39:47 -0600 Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wAMBdliA107021 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 22 Nov 2018 05:39:47 -0600 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 22 Nov 2018 05:39:46 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 22 Nov 2018 05:39:46 -0600 Received: from dlelxv97.itg.ti.com (dlelxv97.itg.ti.com [172.17.2.193]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAMBdkHK027423; Thu, 22 Nov 2018 05:39:46 -0600 Received: from localhost.localdomain (vboxa0400828d.dhcp.ti.com [172.22.239.63]) by dlelxv97.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAMBdDf6013203; Thu, 22 Nov 2018 05:39:42 -0600 From: Roger Quadros To: CC: , , , , , , , , , , , , , , , , Subject: [PATCH 07/17] soc: ti: pruss: enable OCP master ports in SYSCFG always Date: Thu, 22 Nov 2018 13:39:03 +0200 Message-ID: <1542886753-17625-8-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1542886753-17625-1-git-send-email-rogerq@ti.com> References: <1542886753-17625-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Suman Anna The PRUSS CFG module's SYSCFG register is used for managing the PRCM clock management settings at the PRU-ICSS subsystem level, and is being programmed for the PRCM Idle/Standby protocol properly during probe and remove. The register is also programmed to enable the OCP master ports (disable MStandby) by default during probe now to allow the PRUs access to on-chip memories and peripherals outside the PRUSS without having to do it in firmware (primarily for the PRU Ethernet usecase currently, the firmware is not programming this register). NOTE: 1. The AM57xx TRM suggests to enable "No Standby" during the Idle + Standby state to an Active/Normal state, but this sequence is not documented in either of AM33xx and AM437x SoCs. Furthermore, it did not have an impact on the working of Ethernet Rx, so is left out. 2. This has an impact on the PM suspend/resume operation usually (same bit is used to trigger PRU standby), and even when the PRU cores are in halted state. The STANDBY_INIT has to be re-programmed to initiate a standby sequence and have the PM suspend/resume functional when PRUs are halted. This is already handled in commit b7e68ab66385 ("remoteproc/pruss_soc: fix system suspend/MStandby config issues"). Signed-off-by: Suman Anna --- drivers/soc/ti/pruss_soc_bus.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/pruss_soc_bus.c b/drivers/soc/ti/pruss_soc_bus.c index 46dfb7a..f477168 100644 --- a/drivers/soc/ti/pruss_soc_bus.c +++ b/drivers/soc/ti/pruss_soc_bus.c @@ -67,8 +67,7 @@ static inline void pruss_soc_bus_rmw(void __iomem *reg, u32 mask, u32 set) * outside of the PRU-ICSS. The function has to wait for the PRCM to * acknowledge through the monitoring of the PRUSS_SYSCFG.SUB_MWAIT bit. */ -static -int __maybe_unused pruss_soc_bus_enable_ocp_master_ports(struct device *dev) +static int pruss_soc_bus_enable_ocp_master_ports(struct device *dev) { struct pruss_soc_bus *psoc_bus = dev_get_drvdata(dev); u32 syscfg_val, i; @@ -160,6 +159,11 @@ static int pruss_enable_module(struct device *dev) pruss_soc_bus_rmw(psoc_bus->syscfg, SYSCFG_STANDBY_MODE_MASK, SYSCFG_STANDBY_MODE_SMART); + /* enable OCP master ports/disable MStandby */ + ret = pruss_soc_bus_enable_ocp_master_ports(dev); + if (ret) + pruss_disable_module(dev); + return ret; } From patchwork Thu Nov 22 11:39:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 151758 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp628434ljp; Thu, 22 Nov 2018 03:40:00 -0800 (PST) X-Google-Smtp-Source: AFSGD/X9WB6vrchVpVM9Y8C55GsKp2Xzg9MLt6ahSvnyAz3XVAYeePybITsRlD8pMalcdPT7k+Jy X-Received: by 2002:a17:902:2f03:: with SMTP id s3mr10379010plb.277.1542886800796; Thu, 22 Nov 2018 03:40:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542886800; cv=none; d=google.com; s=arc-20160816; b=FWFiIszmtzHnvelodVq6bAYh9e50gRiObT8bPmfsuVFBqCeWOAN1jkSL9c4wtL1rje KAcSUrBBDMqgBUgIr06bR/D/GLuRfxHnJiP4CvSo2iYs58injb4Zy+ic+6KwvWHWu+8p Pqz9Z/w6sqKAZmY0xffLQlp7yLzPdG0h3y0aN5+cxgq4jdyIml2KDPbx65KJzmXfEesL oZpuwNO/qAJERUdj4NiWOdY5QgAenoMursUYcrWKq+LVO2sv7eddWLnzvBqE8oA8gfLd kUl97tUlC34td5MycNnqwC7+9+E6bYuN6NpGrgnbmq0/R1HjiUg2htqNt95QOKXlNXum dDXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=XNyoLGbN57o6AGKvIRzOoAPN9qwb4b9t2iJge+fmxDU=; b=v643tgq7FyZSrhnVV9mp2THlduyL1UW9PW7X65W8anspv5oOFQtdrLEPwFROFlUpku qM4MVA0CKs7gCcxliKnlHmA1dwmZ3PbIPcm0BfdI5jJSeCD8lHtHsnO0Iad5+JE428Ql aFU+9mHTANESFgrofoN+QumjDZHlWAux8vSSsGVPEa5EkL9kHJ+nXjzpIWXMjlIcXkpa wVEPTaUgO9ff5B8u0qU249FKPYd0QO8u+LWgNsvPLaMjLhmmPmuj1Ykiw/ARZrqg7aDY MgQfQugFYkWdYkDqBbqaZ9Y5gYiJccwrSlG7uHYvZ7BRBBf7CsCCDLaejVryhWH6DuKS DiBQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=rSEQTZtx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 38si49041782pgx.460.2018.11.22.03.40.00; Thu, 22 Nov 2018 03:40:00 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=rSEQTZtx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2436546AbeKVWS7 (ORCPT + 32 others); Thu, 22 Nov 2018 17:18:59 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:50426 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728274AbeKVWS6 (ORCPT ); Thu, 22 Nov 2018 17:18:58 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id wAMBdroR075844; Thu, 22 Nov 2018 05:39:53 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1542886793; bh=XNyoLGbN57o6AGKvIRzOoAPN9qwb4b9t2iJge+fmxDU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=rSEQTZtxQpX0REp2cxSbih7LqWL7F5ZfrxAABEX88hYhVazPWEpMPY2AUT/StN1NN GjPU1AzmD8/bwa5JnCLkFUtkyzBZuPfAvF144Wux2QQiyR2eXFW8MeYdnAAiGa5IPf XI1QFWvkTnm8e67mK/QGHZaqwU8qClHUd5ztygVk= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wAMBdr0W076956 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 22 Nov 2018 05:39:53 -0600 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 22 Nov 2018 05:39:50 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 22 Nov 2018 05:39:50 -0600 Received: from dlelxv97.itg.ti.com (dlelxv97.itg.ti.com [172.17.2.193]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAMBdoKC024743; Thu, 22 Nov 2018 05:39:50 -0600 Received: from localhost.localdomain (vboxa0400828d.dhcp.ti.com [172.22.239.63]) by dlelxv97.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAMBdDf7013203; Thu, 22 Nov 2018 05:39:47 -0600 From: Roger Quadros To: CC: , , , , , , , , , , , , , , , , Subject: [PATCH 08/17] soc: ti: pruss: Add a PRUSS irqchip driver for PRUSS interrupts Date: Thu, 22 Nov 2018 13:39:04 +0200 Message-ID: <1542886753-17625-9-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1542886753-17625-1-git-send-email-rogerq@ti.com> References: <1542886753-17625-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Suman Anna The Programmable Real-Time Unit Subsystem (PRUSS) contains an interrupt controller (INTC) that can handle various system input events and post interrupts back to the device-level initiators. The INTC can support upto 64 input events with individual control configuration and hardware prioritization. These events are mapped onto 10 interrupt signals through two levels of many-to-one mapping support. Different interrupt signals are routed to the individual PRU cores or to the host CPU. The PRUSS INTC platform driver manages this PRUSS interrupt controller and implements an irqchip driver to provide a Linux standard way for the PRU client users to enable/disable/ack/ re-trigger a PRUSS system event. The system events to interrupt channels and host interrupts relies on the mapping configuration provided through a firmware resource table for now. This will be revisited and enhanced in the future for a better interface. The mappings will currently be programmed during the boot/shutdown of the PRU. The PRUSS INTC module is reference counted during the interrupt setup phase through the irqchip's irq_request_resources() and irq_release_resources() ops. This restricts the module from being removed as long as there are active interrupt users. The driver currently supports the AM335x SoC. Signed-off-by: Suman Anna Signed-off-by: Andrew F. Davis Signed-off-by: Roger Quadros --- drivers/soc/ti/Makefile | 2 +- drivers/soc/ti/pruss.h | 29 +++ drivers/soc/ti/pruss_intc.c | 572 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 602 insertions(+), 1 deletion(-) create mode 100644 drivers/soc/ti/pruss_intc.c -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/Makefile b/drivers/soc/ti/Makefile index 5a0c89d..71626a0 100644 --- a/drivers/soc/ti/Makefile +++ b/drivers/soc/ti/Makefile @@ -8,4 +8,4 @@ obj-$(CONFIG_KEYSTONE_NAVIGATOR_DMA) += knav_dma.o obj-$(CONFIG_AMX3_PM) += pm33xx.o obj-$(CONFIG_WKUP_M3_IPC) += wkup_m3_ipc.o obj-$(CONFIG_TI_SCI_PM_DOMAINS) += ti_sci_pm_domains.o -obj-$(CONFIG_TI_PRUSS) += pruss_soc_bus.o pruss.o +obj-$(CONFIG_TI_PRUSS) += pruss_soc_bus.o pruss.o pruss_intc.o diff --git a/drivers/soc/ti/pruss.h b/drivers/soc/ti/pruss.h index dbdf475..a5a0667 100644 --- a/drivers/soc/ti/pruss.h +++ b/drivers/soc/ti/pruss.h @@ -9,6 +9,18 @@ #ifndef _PRUSS_H_ #define _PRUSS_H_ +/* maximum number of system events */ +#define MAX_PRU_SYS_EVENTS 64 + +/* maximum number of interrupt channels */ +#define MAX_PRU_CHANNELS 10 + +/* minimum starting host interrupt number for MPU */ +#define MIN_PRU_HOST_INT 2 + +/* maximum number of host interrupts */ +#define MAX_PRU_HOST_INT 10 + /** * enum pruss_mem - PRUSS memory range identifiers */ @@ -32,13 +44,30 @@ struct pruss_mem_region { }; /** + * struct pruss_intc_config - INTC configuration info + * @sysev_to_ch: system events to channel mapping information + * @ch_to_host: interrupt channel to host interrupt information + */ +struct pruss_intc_config { + s8 sysev_to_ch[MAX_PRU_SYS_EVENTS]; + s8 ch_to_host[MAX_PRU_CHANNELS]; +}; + +/** * struct pruss - PRUSS parent structure * @dev: pruss device pointer * @mem_regions: data for each of the PRUSS memory regions + * @host_mask: indicate which HOST IRQs are enabled */ struct pruss { struct device *dev; struct pruss_mem_region mem_regions[PRUSS_MEM_MAX]; + u32 host_mask; }; +int pruss_intc_configure(struct pruss *pruss, + struct pruss_intc_config *intc_config); +int pruss_intc_unconfigure(struct pruss *pruss, + struct pruss_intc_config *intc_config); + #endif /* _PRUSS_H_ */ diff --git a/drivers/soc/ti/pruss_intc.c b/drivers/soc/ti/pruss_intc.c new file mode 100644 index 0000000..dde054b --- /dev/null +++ b/drivers/soc/ti/pruss_intc.c @@ -0,0 +1,572 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PRU-ICSS INTC IRQChip driver for various TI SoCs + * + * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Andrew F. Davis + * Suman Anna + */ + +#include +#include +#include +#include +#include +#include + +#include "pruss.h" + +/* + * Number of host interrupts reaching the main MPU sub-system. Note that this + * is not the same as the total number of host interrupts supported by the PRUSS + * INTC instance + */ +#define MAX_HOST_NUM_IRQS 8 + +/* PRU_ICSS_INTC registers */ +#define PRU_INTC_REVID 0x0000 +#define PRU_INTC_CR 0x0004 +#define PRU_INTC_GER 0x0010 +#define PRU_INTC_GNLR 0x001C +#define PRU_INTC_SISR 0x0020 +#define PRU_INTC_SICR 0x0024 +#define PRU_INTC_EISR 0x0028 +#define PRU_INTC_EICR 0x002C +#define PRU_INTC_HIEISR 0x0034 +#define PRU_INTC_HIDISR 0x0038 +#define PRU_INTC_GPIR 0x0080 +#define PRU_INTC_SRSR0 0x0200 +#define PRU_INTC_SRSR1 0x0204 +#define PRU_INTC_SECR0 0x0280 +#define PRU_INTC_SECR1 0x0284 +#define PRU_INTC_ESR0 0x0300 +#define PRU_INTC_ESR1 0x0304 +#define PRU_INTC_ECR0 0x0380 +#define PRU_INTC_ECR1 0x0384 +#define PRU_INTC_CMR(x) (0x0400 + (x) * 4) +#define PRU_INTC_HMR(x) (0x0800 + (x) * 4) +#define PRU_INTC_HIPIR(x) (0x0900 + (x) * 4) +#define PRU_INTC_SIPR0 0x0D00 +#define PRU_INTC_SIPR1 0x0D04 +#define PRU_INTC_SITR0 0x0D80 +#define PRU_INTC_SITR1 0x0D84 +#define PRU_INTC_HINLR(x) (0x1100 + (x) * 4) +#define PRU_INTC_HIER 0x1500 + +/* HIPIR register bit-fields */ +#define INTC_HIPIR_NONE_HINT 0x80000000 + +static const char * const irq_names[] = { + "host2", "host3", "host4", "host5", "host6", "host7", "host8", "host9", +}; + +/** + * struct pruss_intc - PRUSS interrupt controller structure + * @pruss: back-reference to parent PRUSS structure + * @irqs: kernel irq numbers corresponding to PRUSS host interrupts + * @mem: kernel-mapping data for the INTC register space + * @irqchip: irq chip for this interrupt controller + * @domain: irq domain for this interrupt controller + * @config_map: stored INTC configuration mapping data + * @lock: mutex to serialize access to INTC + */ +struct pruss_intc { + struct pruss *pruss; + unsigned int irqs[MAX_HOST_NUM_IRQS]; + struct pruss_mem_region mem; + struct irq_chip *irqchip; + struct irq_domain *domain; + struct pruss_intc_config config_map; + struct mutex lock; /* PRUSS INTC lock */ +}; + +static inline u32 pruss_intc_read_reg(struct pruss_intc *intc, unsigned int reg) +{ + return readl_relaxed(intc->mem.va + reg); +} + +static inline void pruss_intc_write_reg(struct pruss_intc *intc, + unsigned int reg, u32 val) +{ + writel_relaxed(val, intc->mem.va + reg); +} + +static int pruss_intc_check_write(struct pruss_intc *intc, unsigned int reg, + unsigned int sysevent) +{ + if (!intc) + return -EINVAL; + + if (sysevent >= MAX_PRU_SYS_EVENTS) + return -EINVAL; + + pruss_intc_write_reg(intc, reg, sysevent); + + return 0; +} + +static struct pruss_intc *to_pruss_intc(struct pruss *pruss) +{ + struct device_node *parent = pruss->dev->of_node; + struct device_node *np; + struct platform_device *pdev; + struct pruss_intc *intc = NULL; + + np = of_get_child_by_name(parent, "intc"); + if (!np) { + dev_err(pruss->dev, "pruss does not have an intc node\n"); + return NULL; + } + + pdev = of_find_device_by_node(np); + if (!pdev) { + dev_err(pruss->dev, "no associated platform device\n"); + goto out; + } + + intc = platform_get_drvdata(pdev); +out: + of_node_put(np); + return intc; +} + +/** + * pruss_intc_configure() - configure the PRUSS INTC + * @pruss: the pruss instance + * @intc_config: PRU core-specific INTC configuration + * + * Configures the PRUSS INTC with the provided configuration from + * a PRU core. Any existing event to channel mappings or channel to + * host interrupt mappings are checked to make sure there are no + * conflicting configuration between both the PRU cores. The function + * is intended to be used only by the PRU remoteproc driver. + * + * Returns 0 on success, or a suitable error code otherwise + */ +int pruss_intc_configure(struct pruss *pruss, + struct pruss_intc_config *intc_config) +{ + struct device *dev = pruss->dev; + struct pruss_intc *intc = to_pruss_intc(pruss); + int i, idx, ret; + s8 ch, host; + u64 sysevt_mask = 0; + u32 ch_mask = 0; + u32 host_mask = 0; + u32 val; + + if (!intc) + return -EINVAL; + + mutex_lock(&intc->lock); + + /* + * configure channel map registers - each register holds map info + * for 4 events, with each event occupying the lower nibble in + * a register byte address in little-endian fashion + */ + for (i = 0; i < ARRAY_SIZE(intc_config->sysev_to_ch); i++) { + ch = intc_config->sysev_to_ch[i]; + if (ch < 0) + continue; + + /* check if sysevent already assigned */ + if (intc->config_map.sysev_to_ch[i] != -1) { + dev_err(dev, "event %d (req. channel %d) already assigned to channel %d\n", + i, ch, intc->config_map.sysev_to_ch[i]); + ret = -EEXIST; + goto unlock; + } + + intc->config_map.sysev_to_ch[i] = ch; + + idx = i / 4; + val = pruss_intc_read_reg(intc, PRU_INTC_CMR(idx)); + val |= ch << ((i & 3) * 8); + pruss_intc_write_reg(intc, PRU_INTC_CMR(idx), val); + sysevt_mask |= BIT_ULL(i); + ch_mask |= BIT(ch); + + dev_dbg(dev, "SYSEV%d -> CH%d (CMR%d 0x%08x)\n", i, ch, idx, + pruss_intc_read_reg(intc, PRU_INTC_CMR(idx))); + } + + /* + * set host map registers - each register holds map info for + * 4 channels, with each channel occupying the lower nibble in + * a register byte address in little-endian fashion + */ + for (i = 0; i < ARRAY_SIZE(intc_config->ch_to_host); i++) { + host = intc_config->ch_to_host[i]; + if (host < 0) + continue; + + /* check if channel already assigned */ + if (intc->config_map.ch_to_host[i] != -1) { + dev_err(dev, "channel %d (req. intr_no %d) already assigned to intr_no %d\n", + i, host, intc->config_map.ch_to_host[i]); + ret = -EEXIST; + goto unlock; + } + + /* check if host intr is already in use by other PRU */ + if (pruss->host_mask & (1U << host)) { + dev_err(dev, "%s: host intr %d already in use\n", + __func__, host); + ret = -EEXIST; + goto unlock; + } + + intc->config_map.ch_to_host[i] = host; + + idx = i / 4; + + val = pruss_intc_read_reg(intc, PRU_INTC_HMR(idx)); + val |= host << ((i & 3) * 8); + pruss_intc_write_reg(intc, PRU_INTC_HMR(idx), val); + + ch_mask |= BIT(i); + host_mask |= BIT(host); + + dev_dbg(dev, "CH%d -> HOST%d (HMR%d 0x%08x)\n", i, host, idx, + pruss_intc_read_reg(intc, PRU_INTC_HMR(idx))); + } + + dev_info(dev, "configured system_events = 0x%016llx intr_channels = 0x%08x host_intr = 0x%08x\n", + sysevt_mask, ch_mask, host_mask); + + /* enable system events, writing 0 has no-effect */ + pruss_intc_write_reg(intc, PRU_INTC_ESR0, lower_32_bits(sysevt_mask)); + pruss_intc_write_reg(intc, PRU_INTC_SECR0, lower_32_bits(sysevt_mask)); + pruss_intc_write_reg(intc, PRU_INTC_ESR1, upper_32_bits(sysevt_mask)); + pruss_intc_write_reg(intc, PRU_INTC_SECR1, upper_32_bits(sysevt_mask)); + + /* enable host interrupts */ + for (i = 0; i < MAX_PRU_HOST_INT; i++) { + if (host_mask & BIT(i)) + pruss_intc_write_reg(intc, PRU_INTC_HIEISR, i); + } + + /* global interrupt enable */ + pruss_intc_write_reg(intc, PRU_INTC_GER, 1); + + pruss->host_mask |= host_mask; + + mutex_unlock(&intc->lock); + return 0; + +unlock: + mutex_unlock(&intc->lock); + return ret; +} +EXPORT_SYMBOL_GPL(pruss_intc_configure); + +/** + * pruss_intc_unconfigure() - unconfigure the PRUSS INTC + * @pruss: the pruss instance + * @intc_config: PRU core specific INTC configuration + * + * Undo whatever was done in pruss_intc_configure() for a PRU core. + * It should be sufficient to just mark the resources free in the + * global map and disable the host interrupts and sysevents. + */ +int pruss_intc_unconfigure(struct pruss *pruss, + struct pruss_intc_config *intc_config) +{ + struct device *dev = pruss->dev; + struct pruss_intc *intc = to_pruss_intc(pruss); + int i; + s8 ch, host; + u64 sysevt_mask = 0; + u32 host_mask = 0; + + if (!intc) + return -EINVAL; + + mutex_lock(&intc->lock); + + for (i = 0; i < ARRAY_SIZE(intc_config->sysev_to_ch); i++) { + ch = intc_config->sysev_to_ch[i]; + if (ch < 0) + continue; + + /* mark sysevent free in global map */ + intc->config_map.sysev_to_ch[i] = -1; + sysevt_mask |= BIT_ULL(i); + } + + for (i = 0; i < ARRAY_SIZE(intc_config->ch_to_host); i++) { + host = intc_config->ch_to_host[i]; + if (host < 0) + continue; + + /* mark channel free in global map */ + intc->config_map.ch_to_host[i] = -1; + host_mask |= BIT(host); + } + + dev_info(dev, "unconfigured system_events = 0x%016llx host_intr = 0x%08x\n", + sysevt_mask, host_mask); + + /* disable system events, writing 0 has no-effect */ + pruss_intc_write_reg(intc, PRU_INTC_ECR0, lower_32_bits(sysevt_mask)); + pruss_intc_write_reg(intc, PRU_INTC_ECR1, upper_32_bits(sysevt_mask)); + /* clear any pending status */ + pruss_intc_write_reg(intc, PRU_INTC_SECR0, lower_32_bits(sysevt_mask)); + pruss_intc_write_reg(intc, PRU_INTC_SECR1, upper_32_bits(sysevt_mask)); + + /* disable host interrupts */ + for (i = 0; i < MAX_PRU_HOST_INT; i++) { + if (host_mask & BIT(i)) + pruss_intc_write_reg(intc, PRU_INTC_HIDISR, i); + } + + pruss->host_mask &= ~host_mask; + mutex_unlock(&intc->lock); + + return 0; +} +EXPORT_SYMBOL_GPL(pruss_intc_unconfigure); + +static void pruss_intc_init(struct pruss_intc *intc) +{ + int i; + + /* configure polarity to active high for all system interrupts */ + pruss_intc_write_reg(intc, PRU_INTC_SIPR0, 0xffffffff); + pruss_intc_write_reg(intc, PRU_INTC_SIPR1, 0xffffffff); + + /* configure type to pulse interrupt for all system interrupts */ + pruss_intc_write_reg(intc, PRU_INTC_SITR0, 0); + pruss_intc_write_reg(intc, PRU_INTC_SITR1, 0); + + /* clear all 16 interrupt channel map registers */ + for (i = 0; i < 16; i++) + pruss_intc_write_reg(intc, PRU_INTC_CMR(i), 0); + + /* clear all 3 host interrupt map registers */ + for (i = 0; i < 3; i++) + pruss_intc_write_reg(intc, PRU_INTC_HMR(i), 0); +} + +static void pruss_intc_irq_ack(struct irq_data *data) +{ + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); + unsigned int hwirq = data->hwirq; + + pruss_intc_check_write(intc, PRU_INTC_SICR, hwirq); +} + +static void pruss_intc_irq_mask(struct irq_data *data) +{ + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); + unsigned int hwirq = data->hwirq; + + pruss_intc_check_write(intc, PRU_INTC_EICR, hwirq); +} + +static void pruss_intc_irq_unmask(struct irq_data *data) +{ + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); + unsigned int hwirq = data->hwirq; + + pruss_intc_check_write(intc, PRU_INTC_EISR, hwirq); +} + +static int pruss_intc_irq_retrigger(struct irq_data *data) +{ + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); + unsigned int hwirq = data->hwirq; + + return pruss_intc_check_write(intc, PRU_INTC_SISR, hwirq); +} + +static int pruss_intc_irq_reqres(struct irq_data *data) +{ + if (!try_module_get(THIS_MODULE)) + return -ENODEV; + + return 0; +} + +static void pruss_intc_irq_relres(struct irq_data *data) +{ + module_put(THIS_MODULE); +} + +static int pruss_intc_irq_domain_map(struct irq_domain *d, unsigned int virq, + irq_hw_number_t hw) +{ + struct pruss_intc *intc = d->host_data; + + irq_set_chip_data(virq, intc); + irq_set_chip_and_handler(virq, intc->irqchip, handle_level_irq); + + return 0; +} + +static void pruss_intc_irq_domain_unmap(struct irq_domain *d, unsigned int virq) +{ + irq_set_chip_and_handler(virq, NULL, NULL); + irq_set_chip_data(virq, NULL); +} + +static const struct irq_domain_ops pruss_intc_irq_domain_ops = { + .xlate = irq_domain_xlate_onecell, + .map = pruss_intc_irq_domain_map, + .unmap = pruss_intc_irq_domain_unmap, +}; + +static void pruss_intc_irq_handler(struct irq_desc *desc) +{ + unsigned int irq = irq_desc_get_irq(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct pruss_intc *intc = irq_get_handler_data(irq); + u32 hipir; + unsigned int virq; + int i, hwirq; + + chained_irq_enter(chip, desc); + + /* find our host irq number */ + for (i = 0; i < MAX_HOST_NUM_IRQS; i++) + if (intc->irqs[i] == irq) + break; + if (i == MAX_HOST_NUM_IRQS) + goto err; + + i += MIN_PRU_HOST_INT; + + /* get highest priority pending PRUSS system event */ + hipir = pruss_intc_read_reg(intc, PRU_INTC_HIPIR(i)); + while (!(hipir & BIT(31))) { + hwirq = hipir & GENMASK(9, 0); + virq = irq_linear_revmap(intc->domain, hwirq); + + /* + * XXX: manually ACK any system events that do not have a + * handler mapped yet + */ + if (unlikely(!virq)) + pruss_intc_check_write(intc, PRU_INTC_SICR, hwirq); + else + generic_handle_irq(virq); + + /* get next system event */ + hipir = pruss_intc_read_reg(intc, PRU_INTC_HIPIR(i)); + } +err: + chained_irq_exit(chip, desc); +} + +static int pruss_intc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct platform_device *ppdev = to_platform_device(dev->parent); + struct pruss_intc *intc; + struct resource *res; + struct irq_chip *irqchip; + int i, irq; + + intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL); + if (!intc) + return -ENOMEM; + platform_set_drvdata(pdev, intc); + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intc"); + intc->mem.va = devm_ioremap_resource(dev, res); + if (IS_ERR(intc->mem.va)) { + dev_err(dev, "failed to parse and map intc memory resource\n"); + return PTR_ERR(intc->mem.va); + } + intc->mem.pa = res->start; + intc->mem.size = resource_size(res); + + dev_dbg(dev, "intc memory: pa %pa size 0x%zx va %p\n", &intc->mem.pa, + intc->mem.size, intc->mem.va); + + mutex_init(&intc->lock); + + for (i = 0; i < ARRAY_SIZE(intc->config_map.sysev_to_ch); i++) + intc->config_map.sysev_to_ch[i] = -1; + + for (i = 0; i < ARRAY_SIZE(intc->config_map.ch_to_host); i++) + intc->config_map.ch_to_host[i] = -1; + + intc->pruss = platform_get_drvdata(ppdev); + pruss_intc_init(intc); + + irqchip = devm_kzalloc(dev, sizeof(*irqchip), GFP_KERNEL); + if (!irqchip) + return -ENOMEM; + + irqchip->irq_ack = pruss_intc_irq_ack; + irqchip->irq_mask = pruss_intc_irq_mask; + irqchip->irq_unmask = pruss_intc_irq_unmask; + irqchip->irq_retrigger = pruss_intc_irq_retrigger; + irqchip->irq_request_resources = pruss_intc_irq_reqres; + irqchip->irq_release_resources = pruss_intc_irq_relres; + irqchip->name = dev_name(dev); + intc->irqchip = irqchip; + + /* always 64 events */ + intc->domain = irq_domain_add_linear(dev->of_node, MAX_PRU_SYS_EVENTS, + &pruss_intc_irq_domain_ops, intc); + if (!intc->domain) + return -ENOMEM; + + for (i = 0; i < MAX_HOST_NUM_IRQS; i++) { + irq = platform_get_irq_byname(ppdev, irq_names[i]); + if (irq < 0) { + dev_err(dev->parent, "platform_get_irq_byname failed for %s : %d\n", + irq_names[i], irq); + goto fail_irq; + } + + intc->irqs[i] = irq; + irq_set_handler_data(irq, intc); + irq_set_chained_handler(irq, pruss_intc_irq_handler); + } + + return 0; + +fail_irq: + irq_domain_remove(intc->domain); + return irq; +} + +static int pruss_intc_remove(struct platform_device *pdev) +{ + struct pruss_intc *intc = platform_get_drvdata(pdev); + unsigned int hwirq; + + if (intc->domain) { + for (hwirq = 0; hwirq < MAX_PRU_SYS_EVENTS; hwirq++) + irq_dispose_mapping(irq_find_mapping(intc->domain, + hwirq)); + irq_domain_remove(intc->domain); + } + + return 0; +} + +static const struct of_device_id pruss_intc_of_match[] = { + { .compatible = "ti,am3356-pruss-intc", }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, pruss_intc_of_match); + +static struct platform_driver pruss_intc_driver = { + .driver = { + .name = "pruss-intc", + .of_match_table = pruss_intc_of_match, + }, + .probe = pruss_intc_probe, + .remove = pruss_intc_remove, +}; +module_platform_driver(pruss_intc_driver); + +MODULE_AUTHOR("Andrew F. Davis "); +MODULE_AUTHOR("Suman Anna "); +MODULE_DESCRIPTION("PRU-ICSS INTC Driver"); +MODULE_LICENSE("GPL v2"); From patchwork Thu Nov 22 11:39:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 151759 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp628491ljp; Thu, 22 Nov 2018 03:40:04 -0800 (PST) X-Google-Smtp-Source: AFSGD/VcLnsIlRv3GeH2Gzheg3ye3OvP//icCKD90O/uNUxj7rBrzHe+QvcBNRasSnYFP/58t1M3 X-Received: by 2002:a65:57cb:: with SMTP id q11mr9739872pgr.60.1542886804008; Thu, 22 Nov 2018 03:40:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542886804; cv=none; d=google.com; s=arc-20160816; b=TZ4IZui1o5V6Edc3ZLOjTlX864pvez6gKPAEB/HE4P1yeUPJDYUAykrIGM7lLoWwLl Lpo4CtGwEddrcVsAuQSsD+vJLUai0uG72aV0fZQ56pssX/x12rdE7oTdKFMhICMd1EyA EKz0pJBj1r1yrli+HGHFpdbWPEgf16IcsxIndB2rR31YuRgW3W17dqOsPZna+Q0FXfUf klmdWPFTNruyOYjiAMpUK9aWcdhw90AbClpJ6dmBdUb4g+S1L++Uw6D1jUVoOYSOThxl 1J83WzVord3NdVfy9SMf16sXB8nczWz3vG+Oy68Ylb+mqU9SgPlf9sgCdecrCQtzg6XM mzIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=L1g+cFlZbK2jqch2VzZJr2MhbexCzsfb03CSRdvV3hI=; b=KR+kS2WObPRNMfxL0rq3Yvhx6or48DQLahXZtq7G7znYHryQjxYkYwy++i0Q+y56hw sv0gQD9IFHZLi46rzNh03XGAKBOvQ2yxzfGcW6bGI2k2CrOLlxcplT7DwjL25tvFZftX BdOvMj+89iZKgDNSfTipE0zA1oekzEVpmxipUgdl4qmRzN9ibdVl7ncQ0RiV3LaDe5fk ONjP+Ntqh+fsTV6V/t78It7ux0B4JE/X1BpT9NB7XBTzsKzDysgrbzJKRDs0XvV+O4CQ 8+PMCSL10O5TNlRSCq+eDvYbV6sG2tjHALftl3fVWaxG+ihm7Y214jkhkj/xwiBB2cNY 1Gcw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=sCndE0Tb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h70si46107070pge.221.2018.11.22.03.40.03; Thu, 22 Nov 2018 03:40:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=sCndE0Tb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2394866AbeKVWTC (ORCPT + 32 others); Thu, 22 Nov 2018 17:19:02 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:50436 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2436532AbeKVWS7 (ORCPT ); Thu, 22 Nov 2018 17:18:59 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id wAMBdt1M075858; Thu, 22 Nov 2018 05:39:55 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1542886795; bh=L1g+cFlZbK2jqch2VzZJr2MhbexCzsfb03CSRdvV3hI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=sCndE0TbRh5Su6X70iJvaFz6E7tyNNpNDqWHA3Lz/TcaHOcB1ECElYImB27t0wgvP ILHJQMUw5BaGD2MONhVRO3NfERMyTCeDx382yKcEjcW/cTWwp1ze4Zpv7hIa6aHGBu RD5xopx89K1NHNhB61PRd773jQpVXUPU3QgVmfFU= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wAMBdteB076979 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 22 Nov 2018 05:39:55 -0600 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 22 Nov 2018 05:39:55 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 22 Nov 2018 05:39:54 -0600 Received: from dlelxv97.itg.ti.com (dlelxv97.itg.ti.com [172.17.2.193]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAMBdsV1017780; Thu, 22 Nov 2018 05:39:54 -0600 Received: from localhost.localdomain (vboxa0400828d.dhcp.ti.com [172.22.239.63]) by dlelxv97.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAMBdDf8013203; Thu, 22 Nov 2018 05:39:51 -0600 From: Roger Quadros To: CC: , , , , , , , , , , , , , , , , Subject: [PATCH 09/17] soc: ti: pruss: add pruss_{request, release}_mem_region() API Date: Thu, 22 Nov 2018 13:39:05 +0200 Message-ID: <1542886753-17625-10-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1542886753-17625-1-git-send-email-rogerq@ti.com> References: <1542886753-17625-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: "Andrew F. Davis" Add two new API - pruss_request_mem_region() & pruss_release_mem_region(), to the PRUSS platform driver to allow client drivers to acquire and release the common memory resources present within a PRU-ICSS subsystem. This allows the client drivers to directly manipulate the respective memories, as per their design contract with the associated firmware. Signed-off-by: Andrew F. Davis [s-anna@ti.com: rename functions, add error checking, comments] Signed-off-by: Suman Anna Signed-off-by: Roger Quadros --- drivers/soc/ti/pruss.c | 81 +++++++++++++++++++++++++++++++++++++++++++++ drivers/soc/ti/pruss.h | 26 +++------------ drivers/soc/ti/pruss_intc.c | 1 + include/linux/pruss.h | 61 ++++++++++++++++++++++++++++++++++ 4 files changed, 147 insertions(+), 22 deletions(-) create mode 100644 include/linux/pruss.h -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c index 0840b59..c2271c4 100644 --- a/drivers/soc/ti/pruss.c +++ b/drivers/soc/ti/pruss.c @@ -12,9 +12,89 @@ #include #include #include +#include #include "pruss.h" +/** + * pruss_request_mem_region() - request a memory resource + * @pruss: the pruss instance + * @mem_id: the memory resource id + * @region: pointer to memory region structure to be filled in + * + * This function allows a client driver to request a memory resource, + * and if successful, will let the client driver own the particular + * memory region until released using the pruss_release_mem_region() + * API. + * + * Returns the memory region if requested resource is available, an + * error otherwise + */ +int pruss_request_mem_region(struct pruss *pruss, enum pruss_mem mem_id, + struct pruss_mem_region *region) +{ + if (!pruss || !region) + return -EINVAL; + + if (mem_id >= PRUSS_MEM_MAX) + return -EINVAL; + + mutex_lock(&pruss->lock); + + if (pruss->mem_in_use[mem_id]) { + mutex_unlock(&pruss->lock); + return -EBUSY; + } + + *region = pruss->mem_regions[mem_id]; + pruss->mem_in_use[mem_id] = region; + + mutex_unlock(&pruss->lock); + + return 0; +} +EXPORT_SYMBOL_GPL(pruss_request_mem_region); + +/** + * pruss_release_mem_region() - release a memory resource + * @pruss: the pruss instance + * @region: the memory region to release + * + * This function is the complimentary function to + * pruss_request_mem_region(), and allows the client drivers to + * release back a memory resource. + * + * Returns 0 on success, an error code otherwise + */ +int pruss_release_mem_region(struct pruss *pruss, + struct pruss_mem_region *region) +{ + int id; + + if (!pruss || !region) + return -EINVAL; + + mutex_lock(&pruss->lock); + + /* find out the memory region being released */ + for (id = 0; id < PRUSS_MEM_MAX; id++) { + if (pruss->mem_in_use[id] == region) + break; + } + + if (id == PRUSS_MEM_MAX) { + mutex_unlock(&pruss->lock); + return -EINVAL; + } + + pruss->mem_in_use[id] = NULL; + + mutex_unlock(&pruss->lock); + + return 0; +} +EXPORT_SYMBOL_GPL(pruss_release_mem_region); + static int pruss_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -41,6 +121,7 @@ static int pruss_probe(struct platform_device *pdev) return -ENOMEM; pruss->dev = dev; + mutex_init(&pruss->lock); np = of_get_child_by_name(node, "memories"); if (!np) diff --git a/drivers/soc/ti/pruss.h b/drivers/soc/ti/pruss.h index a5a0667..f8878c2 100644 --- a/drivers/soc/ti/pruss.h +++ b/drivers/soc/ti/pruss.h @@ -22,28 +22,6 @@ #define MAX_PRU_HOST_INT 10 /** - * enum pruss_mem - PRUSS memory range identifiers - */ -enum pruss_mem { - PRUSS_MEM_DRAM0 = 0, - PRUSS_MEM_DRAM1, - PRUSS_MEM_SHRD_RAM2, - PRUSS_MEM_MAX, -}; - -/** - * struct pruss_mem_region - PRUSS memory region structure - * @va: kernel virtual address of the PRUSS memory region - * @pa: physical (bus) address of the PRUSS memory region - * @size: size of the PRUSS memory region - */ -struct pruss_mem_region { - void __iomem *va; - phys_addr_t pa; - size_t size; -}; - -/** * struct pruss_intc_config - INTC configuration info * @sysev_to_ch: system events to channel mapping information * @ch_to_host: interrupt channel to host interrupt information @@ -57,12 +35,16 @@ struct pruss_intc_config { * struct pruss - PRUSS parent structure * @dev: pruss device pointer * @mem_regions: data for each of the PRUSS memory regions + * @mem_in_use: to indicate if memory resource is in use * @host_mask: indicate which HOST IRQs are enabled + * @lock: mutex to serialize access to resources */ struct pruss { struct device *dev; struct pruss_mem_region mem_regions[PRUSS_MEM_MAX]; + struct pruss_mem_region *mem_in_use[PRUSS_MEM_MAX]; u32 host_mask; + struct mutex lock; /* PRU resource lock */ }; int pruss_intc_configure(struct pruss *pruss, diff --git a/drivers/soc/ti/pruss_intc.c b/drivers/soc/ti/pruss_intc.c index dde054b..df6b83b 100644 --- a/drivers/soc/ti/pruss_intc.c +++ b/drivers/soc/ti/pruss_intc.c @@ -13,6 +13,7 @@ #include #include #include +#include #include "pruss.h" diff --git a/include/linux/pruss.h b/include/linux/pruss.h new file mode 100644 index 0000000..198ae25 --- /dev/null +++ b/include/linux/pruss.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/** + * PRU-ICSS Subsystem user interfaces + * + * Copyright (C) 2015-2018 Texas Instruments Incorporated - http://www.ti.com + * Suman Anna + * Tero Kristo + */ + +#ifndef __LINUX_PRUSS_H +#define __LINUX_PRUSS_H + +/** + * enum pruss_mem - PRUSS memory range identifiers + */ +enum pruss_mem { + PRUSS_MEM_DRAM0 = 0, + PRUSS_MEM_DRAM1, + PRUSS_MEM_SHRD_RAM2, + PRUSS_MEM_MAX, +}; + +/** + * struct pruss_mem_region - PRUSS memory region structure + * @va: kernel virtual address of the PRUSS memory region + * @pa: physical (bus) address of the PRUSS memory region + * @size: size of the PRUSS memory region + */ +struct pruss_mem_region { + void __iomem *va; + phys_addr_t pa; + size_t size; +}; + +struct pruss; + +#if IS_ENABLED(CONFIG_TI_PRUSS) + +int pruss_request_mem_region(struct pruss *pruss, enum pruss_mem mem_id, + struct pruss_mem_region *region); +int pruss_release_mem_region(struct pruss *pruss, + struct pruss_mem_region *region); + +#else + +static inline int pruss_request_mem_region(struct pruss *pruss, + enum pruss_mem mem_id, + struct pruss_mem_region *region) +{ + return -ENOTSUPP; +} + +static inline int pruss_release_mem_region(struct pruss *pruss, + struct pruss_mem_region *region) +{ + return -ENOTSUPP; +} + +#endif /* CONFIG_TI_PRUSS */ + +#endif /* __LINUX_PRUSS_H */ From patchwork Thu Nov 22 11:39:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 151760 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp628529ljp; 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These system events can be used by PRU client drivers or applications for event notifications/signalling between PRUs and MPU or other processors. A new API, pruss_intc_trigger() is provided to MPU-side PRU client drivers/applications to be able to trigger an event/interrupt using IRQ numbers provided by the PRUSS-INTC irqdomain chip. Signed-off-by: Andrew F. Davis Signed-off-by: Suman Anna --- drivers/soc/ti/pruss_intc.c | 31 +++++++++++++++++++++++++++++++ include/linux/pruss.h | 7 +++++++ 2 files changed, 38 insertions(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/pruss_intc.c b/drivers/soc/ti/pruss_intc.c index df6b83b..6158b63 100644 --- a/drivers/soc/ti/pruss_intc.c +++ b/drivers/soc/ti/pruss_intc.c @@ -395,6 +395,37 @@ static void pruss_intc_irq_relres(struct irq_data *data) module_put(THIS_MODULE); } +/** + * pruss_intc_trigger() - trigger a PRU system event + * @irq: linux IRQ number associated with a PRU system event + * + * Trigger an interrupt by signalling a specific PRU system event. + * This can be used by PRUSS client users to raise/send an event to + * a PRU or any other core that is listening on the host interrupt + * mapped to that specific PRU system event. The @irq variable is the + * Linux IRQ number associated with a specific PRU system event that + * a client user/application uses. The interrupt mappings for this is + * provided by the PRUSS INTC irqchip instance. + * + * Returns 0 on success, or an error value upon failure. + */ +int pruss_intc_trigger(unsigned int irq) +{ + struct irq_desc *desc; + + if (irq <= 0) + return -EINVAL; + + desc = irq_to_desc(irq); + if (!desc) + return -EINVAL; + + pruss_intc_irq_retrigger(&desc->irq_data); + + return 0; +} +EXPORT_SYMBOL_GPL(pruss_intc_trigger); + static int pruss_intc_irq_domain_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hw) { diff --git a/include/linux/pruss.h b/include/linux/pruss.h index 198ae25..768b698 100644 --- a/include/linux/pruss.h +++ b/include/linux/pruss.h @@ -41,6 +41,8 @@ int pruss_request_mem_region(struct pruss *pruss, enum pruss_mem mem_id, int pruss_release_mem_region(struct pruss *pruss, struct pruss_mem_region *region); +int pruss_intc_trigger(unsigned int irq); + #else static inline int pruss_request_mem_region(struct pruss *pruss, @@ -56,6 +58,11 @@ static inline int pruss_release_mem_region(struct pruss *pruss, return -ENOTSUPP; } +static inline int pruss_intc_trigger(unsigned int irq) +{ + return -ENOTSUPP; +} + #endif /* CONFIG_TI_PRUSS */ #endif /* __LINUX_PRUSS_H */ From patchwork Thu Nov 22 11:39:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 151761 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp628565ljp; Thu, 22 Nov 2018 03:40:09 -0800 (PST) X-Google-Smtp-Source: AJdET5c0Rhr+enPLerWtQinDqrEgMsgbCC9dXu5BJZ5zQfv8IS6NwZJqXxGnwlZh7/buaankCAIJ X-Received: by 2002:a62:e201:: with SMTP id a1mr10839732pfi.75.1542886808965; Thu, 22 Nov 2018 03:40:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542886808; cv=none; d=google.com; s=arc-20160816; b=dQ0dO51FZWd9NGPswmNCp/QrQf65lVH+qtilGoav82oFcI3oNeFkHOSRwQqNqWcaPb jmT35jJk4m6gbdjezACzWi+pXHXVjFS370T42H9YAb0NZFnCi7szQlui3SlNo0J23Ngc y28IDQvGfZ1ndyJQ087ffNlQ5JT6XaaJ6hGyz2Q2K0pNr8ygnsBqTWcQJYPdJBJEnWZ+ n4+gqdVdE8bcpHahKasj0XbRGGW3AeasmDTmPovaDu4KlCEq7yUxovlrELUAYex2JjQG Yzvyq+32WCzNopfABvepnwZGzyWeQGBP4yQzqxZlPgJ0mF+9PAbhXEXfYum7zVVb4C4k GTgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=kOyCfU8xu52K1rFh2Alr7YiAlWDJE4ZlzFpySZgmULM=; b=PLa179U9uamAKLdn1Y26OQ68GScJxleqpN7NXVbkawvJGBx9+2XBN2JEnFSVBEgSPk 0a3dPM+g1KpAmDCLu65PRZgIfjlFmk8AuDM7Xn2A6ikLkbnGw0GY4RpjIwVB4s/7o8Yh qqYIjwcI2aAmFg+tzW98YHufIPtbCxCeXIzCDYVPjmiV7XB3hefVrUBlbDkhwMnIeROp UtmFwN+bi0pHw03C6yi9tOzfJ7IeR7PIE2xSZEq5TZYF3SR6pI0kZXxmumFl18ik00na U1CQ4YfvtdkT4GrKqQ9URTU76XsAzr5TZ/jioVjG0djFlJCSPh9YA1n0Ck0baSJ+VKAu Nc6w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=eidyErn7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i39si22778481plb.256.2018.11.22.03.40.08; Thu, 22 Nov 2018 03:40:08 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=eidyErn7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2394896AbeKVWTH (ORCPT + 32 others); Thu, 22 Nov 2018 17:19:07 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:35462 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391015AbeKVWTG (ORCPT ); Thu, 22 Nov 2018 17:19:06 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id wAMBe34r078110; Thu, 22 Nov 2018 05:40:03 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1542886803; bh=kOyCfU8xu52K1rFh2Alr7YiAlWDJE4ZlzFpySZgmULM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=eidyErn7rx/OG4khofgNFVKPvQnlm7kLiFRt2TkuXTmIjRgXe+mOshcfc8/wMYTae DyyTeVBmJEulL5JY8Q4W1a6zuvPtDQx6D4jbn49r2MMhLJrDL+mb05Rz6lDDu+A43F YHGBRLyFjiwVF88FvvAI9kRGFpJP3DSwwIJ+98Cg= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wAMBe3Z9029729 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 22 Nov 2018 05:40:03 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 22 Nov 2018 05:40:03 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 22 Nov 2018 05:40:02 -0600 Received: from dlelxv97.itg.ti.com (dlelxv97.itg.ti.com [172.17.2.193]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAMBe2rf018071; Thu, 22 Nov 2018 05:40:02 -0600 Received: from localhost.localdomain (vboxa0400828d.dhcp.ti.com [172.22.239.63]) by dlelxv97.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAMBdDfA013203; Thu, 22 Nov 2018 05:39:59 -0600 From: Roger Quadros To: CC: , , , , , , , , , , , , , , , , Subject: [PATCH 11/17] soc: ti: pruss: add pruss_get()/put() API Date: Thu, 22 Nov 2018 13:39:07 +0200 Message-ID: <1542886753-17625-12-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1542886753-17625-1-git-send-email-rogerq@ti.com> References: <1542886753-17625-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tero Kristo Add two new get and put API, pruss_get() and pruss_put(), to the PRUSS platform driver to allow client drivers to request a handle to a PRUSS device. This handle will be used by client drivers to request various operations of the PRUSS platform driver through additional API that will be added in the following patches. The pruss_get() function returns the pruss handle corresponding to a PRUSS device referenced by a PRU remoteproc instance. The pruss_put() is the complimentary function to pruss_get(). Signed-off-by: Tero Kristo [s-anna@ti.com: various fixups and cleanups] Signed-off-by: Suman Anna --- drivers/soc/ti/pruss.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++++++ include/linux/pruss.h | 10 +++++++++ 2 files changed, 67 insertions(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c index c2271c4..90ee5b9 100644 --- a/drivers/soc/ti/pruss.c +++ b/drivers/soc/ti/pruss.c @@ -13,10 +13,67 @@ #include #include #include +#include #include "pruss.h" /** + * pruss_get() - get the pruss for a given PRU remoteproc + * @rproc: remoteproc handle of a PRU instance + * + * Finds the parent pruss device for a PRU given the @rproc handle of the + * PRU remote processor. This function increments the pruss device's refcount, + * so always use pruss_put() to decrement it back once pruss isn't needed + * anymore. + * + * Returns the pruss handle on success, and an ERR_PTR on failure using one + * of the following error values + * -EINVAL if invalid parameter + * -ENODEV if PRU device or PRUSS device is not found + */ +struct pruss *pruss_get(struct rproc *rproc) +{ + struct pruss *pruss; + struct device *dev; + struct platform_device *ppdev; + + if (IS_ERR_OR_NULL(rproc)) + return ERR_PTR(-EINVAL); + + dev = &rproc->dev; + if (!dev->parent) + return ERR_PTR(-ENODEV); + + /* rudimentary check to make sure rproc handle is for a PRU */ + if (!strstr(dev_name(dev->parent), "pru")) + return ERR_PTR(-ENODEV); + + ppdev = to_platform_device(dev->parent->parent); + pruss = platform_get_drvdata(ppdev); + if (pruss) + get_device(pruss->dev); + + return pruss ? pruss : ERR_PTR(-ENODEV); +} +EXPORT_SYMBOL_GPL(pruss_get); + +/** + * pruss_put() - decrement pruss device's usecount + * @pruss: pruss handle + * + * Complimentary function for pruss_get(). Needs to be called + * after the PRUSS is used, and only if the pruss_get() succeeds. + */ +void pruss_put(struct pruss *pruss) +{ + if (IS_ERR_OR_NULL(pruss)) + return; + + put_device(pruss->dev); +} +EXPORT_SYMBOL_GPL(pruss_put); + +/** * pruss_request_mem_region() - request a memory resource * @pruss: the pruss instance * @mem_id: the memory resource id diff --git a/include/linux/pruss.h b/include/linux/pruss.h index 768b698..b9135d6 100644 --- a/include/linux/pruss.h +++ b/include/linux/pruss.h @@ -36,6 +36,9 @@ struct pruss; #if IS_ENABLED(CONFIG_TI_PRUSS) +struct pruss *pruss_get(struct rproc *rproc); +void pruss_put(struct pruss *pruss); + int pruss_request_mem_region(struct pruss *pruss, enum pruss_mem mem_id, struct pruss_mem_region *region); int pruss_release_mem_region(struct pruss *pruss, @@ -45,6 +48,13 @@ int pruss_intc_trigger(unsigned int irq); #else +static inline struct pruss *pruss_get(struct rproc *rproc) +{ + return ERR_PTR(-ENOTSUPP); +} + +static inline void pruss_put(struct pruss *pruss) { } + static inline int pruss_request_mem_region(struct pruss *pruss, enum pruss_mem mem_id, struct pruss_mem_region *region) From patchwork Thu Nov 22 11:39:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 151762 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp628639ljp; Thu, 22 Nov 2018 03:40:13 -0800 (PST) X-Google-Smtp-Source: AFSGD/WS/A5w4UkcnwhK0zdpxSMFuKpXBLJkxI8zfIMH3x9DiZZXw3Xz5ZxiWvpaxWmQwapazkQi X-Received: by 2002:a63:e001:: with SMTP id e1mr9832371pgh.39.1542886813017; Thu, 22 Nov 2018 03:40:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542886813; cv=none; d=google.com; s=arc-20160816; b=mtdptG9GvDmoQYnGF/LBnCyMylsfXbWFtOOLnBy29or+rAcguAANcqimxQMD5aj/hw QDPH7kLHr9M4sBg1AyLizRSGFx5ED0KDN7PSDvJKJlTw7VVRAOadUz5VctZK+exOtmnl 7f1LVJWWchQPhHoW1S+VDGZoQjMkrG2PgKQstvpFt86awz4CgyUY2U32lvK5GZ6DJYoc ecRhw0Kjj3HLOtGYpD6g52SZvU6tCpAqwX9USDB9Ti3Y2Ez2ffPj1h6ZLHd8pDGH1j8X Bes9qjfZdVRAD35EIDk8lFqwgt9b7mMo5al/XjD1Q6JQV8XHysoWmfXFN+ZHZzGX/6t9 qq2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=f5QWpg9K78nrvKyK44+R/q5gP4r0NZpzVIuRi3xm0hs=; b=GaAdCGVTekCCUZOG8P26ukzdgdpw3jquVb46pdpZR/MwWPfmQd1dQkueemjukcq8g2 worNKI+CFDFSjOO1oKoJg6PPZK1CLnM8BiKs/plJBKZnCOxIaduHcP5U7m03Laemo6x6 p3z2dSy/1gz+ct2ZJgq/nexQlr17vK4jEKf+el3w7jw66kscjn4COt1HIND0OsB4BDca WbtlDBVW+HgG/3pkIhYq9NkKHzhP29yfxBgXSMeXSxfCulwKo/SdZpfd2rSSP3XzqDxM Q8bNbZO8PsCDHlAfLBoqNGYp3nbwzemVqUMHjkjFMxjktaOAVWRiwAu+xdOOUxeofokV sp7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=FcqJGu17; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This interface provides a simple way for client drivers without having them to include and parse these syscon nodes within their respective device nodes. The register definitions for the CFG registors have also been added. Signed-off-by: Roger Quadros --- drivers/soc/ti/Kconfig | 1 + drivers/soc/ti/pruss.c | 52 +++++++++++++++++++++++++ drivers/soc/ti/pruss.h | 2 + include/linux/pruss.h | 101 +++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 156 insertions(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig index d1ea6da..d239996 100644 --- a/drivers/soc/ti/Kconfig +++ b/drivers/soc/ti/Kconfig @@ -76,6 +76,7 @@ config TI_SCI_PM_DOMAINS config TI_PRUSS tristate "TI PRU-ICSS Subsystem Platform drivers" depends on SOC_AM33XX + select MFD_SYSCON default n help TI PRU-ICSS Subsystem platform specific support. diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c index 90ee5b9..63c7d8c 100644 --- a/drivers/soc/ti/pruss.c +++ b/drivers/soc/ti/pruss.c @@ -10,9 +10,11 @@ #include #include #include +#include #include #include #include +#include #include #include "pruss.h" @@ -152,6 +154,47 @@ int pruss_release_mem_region(struct pruss *pruss, } EXPORT_SYMBOL_GPL(pruss_release_mem_region); +/** + * pruss_cfg_read() - read a PRUSS CFG register + * @pruss: the pruss instance handle + * @reg: register offset within the CFG sub-module + * @val: pointer to return the value in + * + * Reads a given register within CFG module of PRUSS + * and returns it through the passed-in @val pointer + * + * Returns 0 on success, or an error code otherwise + */ +int pruss_cfg_read(struct pruss *pruss, unsigned int reg, unsigned int *val) +{ + if (IS_ERR_OR_NULL(pruss)) + return -EINVAL; + + return regmap_read(pruss->cfg, reg, val); +} +EXPORT_SYMBOL_GPL(pruss_cfg_read); + +/** + * pruss_cfg_update() - update a PRUSS CFG register + * @pruss: the pruss instance handle + * @reg: register offset within the CFG sub-module + * @mask: bit mask to use for programming the @val + * @val: value to write + * + * Updates a given register within CFG sub-module of PRUSS + * + * Returns 0 on success, or an error code otherwise + */ +int pruss_cfg_update(struct pruss *pruss, unsigned int reg, + unsigned int mask, unsigned int val) +{ + if (IS_ERR_OR_NULL(pruss)) + return -EINVAL; + + return regmap_update_bits(pruss->cfg, reg, mask, val); +} +EXPORT_SYMBOL_GPL(pruss_cfg_update); + static int pruss_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -180,6 +223,15 @@ static int pruss_probe(struct platform_device *pdev) pruss->dev = dev; mutex_init(&pruss->lock); + np = of_get_child_by_name(node, "cfg"); + if (!np) + return -ENODEV; + + pruss->cfg = syscon_node_to_regmap(np); + of_node_put(np); + if (IS_ERR(pruss->cfg)) + return -ENODEV; + np = of_get_child_by_name(node, "memories"); if (!np) return -ENODEV; diff --git a/drivers/soc/ti/pruss.h b/drivers/soc/ti/pruss.h index f8878c2..45de1be 100644 --- a/drivers/soc/ti/pruss.h +++ b/drivers/soc/ti/pruss.h @@ -34,6 +34,7 @@ struct pruss_intc_config { /** * struct pruss - PRUSS parent structure * @dev: pruss device pointer + * @cfg: regmap for config region * @mem_regions: data for each of the PRUSS memory regions * @mem_in_use: to indicate if memory resource is in use * @host_mask: indicate which HOST IRQs are enabled @@ -41,6 +42,7 @@ struct pruss_intc_config { */ struct pruss { struct device *dev; + struct regmap *cfg; struct pruss_mem_region mem_regions[PRUSS_MEM_MAX]; struct pruss_mem_region *mem_in_use[PRUSS_MEM_MAX]; u32 host_mask; diff --git a/include/linux/pruss.h b/include/linux/pruss.h index b9135d6..3ed175a 100644 --- a/include/linux/pruss.h +++ b/include/linux/pruss.h @@ -10,6 +10,92 @@ #ifndef __LINUX_PRUSS_H #define __LINUX_PRUSS_H +/* + * PRU_ICSS_CFG registers + * SYSCFG, ISRP, ISP, IESP, IECP, SCRP applicable on AMxxxx devices only + */ +#define PRUSS_CFG_REVID 0x00 +#define PRUSS_CFG_SYSCFG 0x04 +#define PRUSS_CFG_GPCFG(x) (0x08 + (x) * 4) +#define PRUSS_CFG_CGR 0x10 +#define PRUSS_CFG_ISRP 0x14 +#define PRUSS_CFG_ISP 0x18 +#define PRUSS_CFG_IESP 0x1C +#define PRUSS_CFG_IECP 0x20 +#define PRUSS_CFG_SCRP 0x24 +#define PRUSS_CFG_PMAO 0x28 +#define PRUSS_CFG_MII_RT 0x2C +#define PRUSS_CFG_IEPCLK 0x30 +#define PRUSS_CFG_SPP 0x34 +#define PRUSS_CFG_PIN_MX 0x40 + +/* PRUSS_GPCFG register bits */ +#define PRUSS_GPCFG_PRU_GPO_SH_SEL BIT(25) + +#define PRUSS_GPCFG_PRU_DIV1_SHIFT 20 +#define PRUSS_GPCFG_PRU_DIV1_MASK GENMASK(24, 20) + +#define PRUSS_GPCFG_PRU_DIV0_SHIFT 15 +#define PRUSS_GPCFG_PRU_DIV0_MASK GENMASK(15, 19) + +#define PRUSS_GPCFG_PRU_GPO_MODE BIT(14) +#define PRUSS_GPCFG_PRU_GPO_MODE_DIRECT 0 +#define PRUSS_GPCFG_PRU_GPO_MODE_SERIAL BIT(14) + +#define PRUSS_GPCFG_PRU_GPI_SB BIT(13) + +#define PRUSS_GPCFG_PRU_GPI_DIV1_SHIFT 8 +#define PRUSS_GPCFG_PRU_GPI_DIV1_MASK GENMASK(12, 8) + +#define PRUSS_GPCFG_PRU_GPI_DIV0_SHIFT 3 +#define PRUSS_GPCFG_PRU_GPI_DIV0_MASK GENMASK(7, 3) + +#define PRUSS_GPCFG_PRU_GPI_CLK_MODE_POSITIVE 0 +#define PRUSS_GPCFG_PRU_GPI_CLK_MODE_NEGATIVE BIT(2) +#define PRUSS_GPCFG_PRU_GPI_CLK_MODE BIT(2) + +#define PRUSS_GPCFG_PRU_GPI_MODE_MASK GENMASK(1, 0) +#define PRUSS_GPCFG_PRU_GPI_MODE_SHIFT 0 + +#define PRUSS_GPCFG_PRU_MUX_SEL_SHIFT 26 +#define PRUSS_GPCFG_PRU_MUX_SEL_MASK GENMASK(29, 26) + +/* PRUSS_MII_RT register bits */ +#define PRUSS_MII_RT_EVENT_EN BIT(0) + +/* PRUSS_SPP register bits */ +#define PRUSS_SPP_XFER_SHIFT_EN BIT(1) +#define PRUSS_SPP_PRU1_PAD_HP_EN BIT(0) + +/** + * enum pruss_gp_mux_sel - PRUSS GPI/O Mux modes for the + * PRUSS_GPCFG0/1 registers + * + * NOTE: The below defines are the most common values, but there + * are some exceptions like on 66AK2G, where the RESERVED and MII2 + * values are interchanged. Also, this bit-field does not exist on + * AM335x SoCs + */ +enum pruss_gp_mux_sel { + PRUSS_GP_MUX_SEL_GP = 0, + PRUSS_GP_MUX_SEL_ENDAT, + PRUSS_GP_MUX_SEL_RESERVED, + PRUSS_GP_MUX_SEL_SD, + PRUSS_GP_MUX_SEL_MII2, + PRUSS_GP_MUX_SEL_MAX, +}; + +/** + * enum pruss_gpi_mode - PRUSS GPI configuration modes, used + * to program the PRUSS_GPCFG0/1 registers + */ +enum pruss_gpi_mode { + PRUSS_GPI_MODE_DIRECT = 0, + PRUSS_GPI_MODE_PARALLEL, + PRUSS_GPI_MODE_28BIT_SHIFT, + PRUSS_GPI_MODE_MII, +}; + /** * enum pruss_mem - PRUSS memory range identifiers */ @@ -46,6 +132,10 @@ int pruss_release_mem_region(struct pruss *pruss, int pruss_intc_trigger(unsigned int irq); +int pruss_cfg_read(struct pruss *pruss, unsigned int reg, unsigned int *val); +int pruss_cfg_update(struct pruss *pruss, unsigned int reg, + unsigned int mask, unsigned int val); + #else static inline struct pruss *pruss_get(struct rproc *rproc) @@ -73,6 +163,17 @@ static inline int pruss_intc_trigger(unsigned int irq) return -ENOTSUPP; } +int pruss_cfg_read(struct pruss *pruss, unsigned int reg, unsigned int *val) +{ + return -ENOTSUPP; +} + +int pruss_cfg_update(struct pruss *pruss, unsigned int reg, + unsigned int mask, unsigned int val) +{ + return -ENOTSUPP; +} + #endif /* CONFIG_TI_PRUSS */ #endif /* __LINUX_PRUSS_H */ From patchwork Thu Nov 22 11:39:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 151763 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp628741ljp; Thu, 22 Nov 2018 03:40:18 -0800 (PST) X-Google-Smtp-Source: AFSGD/VREiueywEv1c8zAFhIQzfoVpbpGit4pduq971q0ZomRgbh0ja8QElWUxGULYCvjnqs3Qk+ X-Received: by 2002:a17:902:784d:: with SMTP id e13mr11123643pln.188.1542886818751; Thu, 22 Nov 2018 03:40:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542886818; cv=none; d=google.com; s=arc-20160816; b=lGQ6tJGLntq2eq7uloY5Bw/iU9ZwEYgV9MpgAXQqhNtfxGe+zlTqcuf3jGniwlJITX 1DRFOCfvsdqHfbLvp8FV9xA3J6x0Ed28PDEuJLLU7e7pwnelDwMaHyBgaRgUt6df1OfC 8EK5gkuw9aNMaemarGEIT2px4bwLVcoTKKdkqk7CTqCfzjVSVTa6CuW7V3fVdwIyBEqH MRdgTnAeTDB3wVB/cSAQmBmzgfEUel2jV+TL46v63Lm4KN1rjh1zBRCMqyIylbh6+5tr XVm848YlQtJV2V2ZPdpRMg+tytXILWWtbunUeBOcdHsxTwoBFiMbE2TZYkKNQDrcheaq dJvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Ln0fJdBQ/2H23W8baBsSHB73EdERozHgYF1vFWlnGT8=; b=BfWiM2JtwC/xTcJpQE9iBtPynfwgq3GOrMrQAUectqGr6n8Islzy0MK+EAJz+5T7ZE sxmMAP3flkb/yLsfJJRcwH2Ut28ju145NiecvB9np0UXGdQxzZD9a7ccrVKjVn82J60/ T2BxTZit6J6F9YfS5igOGVi8exXzPr80gWV5Egn9P6ilZOJ0iBH0/RLeweLxnO9ikz2C IcFzu1PK8EEsHlxzFNSWiwIZeScT/G2RyuYO99b2bw9zvtGZ4kP8IkNQGnJ0CoxwmDIX 1habKJGZiZWvm9n54XcqYV0lYcOyYIKnuh6rGP2rfMhZR22ycpzYa9le1U4FzJD6U4Qh zuRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=gjH5dsPE; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 1-v6si51805960plw.81.2018.11.22.03.40.18; Thu, 22 Nov 2018 03:40:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=gjH5dsPE; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2394926AbeKVWTQ (ORCPT + 32 others); Thu, 22 Nov 2018 17:19:16 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:42074 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391015AbeKVWTP (ORCPT ); Thu, 22 Nov 2018 17:19:15 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id wAMBeBfs022738; Thu, 22 Nov 2018 05:40:11 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1542886811; bh=Ln0fJdBQ/2H23W8baBsSHB73EdERozHgYF1vFWlnGT8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=gjH5dsPEGR1IDE8HFHmkS1ZA/BQknSLubXStXPdyyquP8VpgrAZNdt8MetKdY8O7o vGXB9M5R7Ev/2z25ORuhNYpGzYvPTu6LEEh1oXmu9fvG5t3elbFGI42P9VmvaOg149 ey0a7880VlEV4Bv6qqROjXfnuugHIdpdT06Avkps= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wAMBeBJw107692 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 22 Nov 2018 05:40:11 -0600 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 22 Nov 2018 05:40:11 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 22 Nov 2018 05:40:11 -0600 Received: from dlelxv97.itg.ti.com (dlelxv97.itg.ti.com [172.17.2.193]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAMBeBWc018314; Thu, 22 Nov 2018 05:40:11 -0600 Received: from localhost.localdomain (vboxa0400828d.dhcp.ti.com [172.22.239.63]) by dlelxv97.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAMBdDfC013203; Thu, 22 Nov 2018 05:40:07 -0600 From: Roger Quadros To: CC: , , , , , , , , , , , , , , , , Subject: [PATCH 13/17] soc: ti: pruss: export pruss_intc_configure/unconfigure APIs Date: Thu, 22 Nov 2018 13:39:09 +0200 Message-ID: <1542886753-17625-14-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1542886753-17625-1-git-send-email-rogerq@ti.com> References: <1542886753-17625-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The PRU remoteproc driver will need to configure the Interrupt controller based on the application specific interrupt map. Export pruss_intc_configure() and pruss_intc_unconfigure() to linux/pruss.h Signed-off-by: Roger Quadros --- drivers/soc/ti/pruss.h | 21 ------------------- include/linux/pruss.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+), 21 deletions(-) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/pruss.h b/drivers/soc/ti/pruss.h index 45de1be..ce3f96a 100644 --- a/drivers/soc/ti/pruss.h +++ b/drivers/soc/ti/pruss.h @@ -9,12 +9,6 @@ #ifndef _PRUSS_H_ #define _PRUSS_H_ -/* maximum number of system events */ -#define MAX_PRU_SYS_EVENTS 64 - -/* maximum number of interrupt channels */ -#define MAX_PRU_CHANNELS 10 - /* minimum starting host interrupt number for MPU */ #define MIN_PRU_HOST_INT 2 @@ -22,16 +16,6 @@ #define MAX_PRU_HOST_INT 10 /** - * struct pruss_intc_config - INTC configuration info - * @sysev_to_ch: system events to channel mapping information - * @ch_to_host: interrupt channel to host interrupt information - */ -struct pruss_intc_config { - s8 sysev_to_ch[MAX_PRU_SYS_EVENTS]; - s8 ch_to_host[MAX_PRU_CHANNELS]; -}; - -/** * struct pruss - PRUSS parent structure * @dev: pruss device pointer * @cfg: regmap for config region @@ -49,9 +33,4 @@ struct pruss { struct mutex lock; /* PRU resource lock */ }; -int pruss_intc_configure(struct pruss *pruss, - struct pruss_intc_config *intc_config); -int pruss_intc_unconfigure(struct pruss *pruss, - struct pruss_intc_config *intc_config); - #endif /* _PRUSS_H_ */ diff --git a/include/linux/pruss.h b/include/linux/pruss.h index 3ed175a..c797fb1 100644 --- a/include/linux/pruss.h +++ b/include/linux/pruss.h @@ -118,6 +118,22 @@ struct pruss_mem_region { size_t size; }; +/* maximum number of system events */ +#define MAX_PRU_SYS_EVENTS 64 + +/* maximum number of interrupt channels */ +#define MAX_PRU_CHANNELS 10 + +/** + * struct pruss_intc_config - INTC configuration info + * @sysev_to_ch: system events to channel mapping information + * @ch_to_host: interrupt channel to host interrupt information + */ +struct pruss_intc_config { + s8 sysev_to_ch[MAX_PRU_SYS_EVENTS]; + s8 ch_to_host[MAX_PRU_CHANNELS]; +}; + struct pruss; #if IS_ENABLED(CONFIG_TI_PRUSS) @@ -136,6 +152,34 @@ int pruss_cfg_read(struct pruss *pruss, unsigned int reg, unsigned int *val); int pruss_cfg_update(struct pruss *pruss, unsigned int reg, unsigned int mask, unsigned int val); +/** + * pruss_intc_configure() - configure the PRUSS INTC + * @pruss: the pruss instance + * @intc_config: PRU core-specific INTC configuration + * + * Configures the PRUSS INTC with the provided configuration from + * a PRU core. Any existing event to channel mappings or channel to + * host interrupt mappings are checked to make sure there are no + * conflicting configuration between both the PRU cores. The function + * is intended to be used only by the PRU remoteproc driver. + * + * Returns 0 on success, or a suitable error code otherwise + */ +int pruss_intc_configure(struct pruss *pruss, + struct pruss_intc_config *intc_config); + +/** + * pruss_intc_unconfigure() - unconfigure the PRUSS INTC + * @pruss: the pruss instance + * @intc_config: PRU core specific INTC configuration + * + * Undo whatever was done in pruss_intc_configure() for a PRU core. + * It should be sufficient to just mark the resources free in the + * global map and disable the host interrupts and sysevents. + */ +int pruss_intc_unconfigure(struct pruss *pruss, + struct pruss_intc_config *intc_config); + #else static inline struct pruss *pruss_get(struct rproc *rproc) @@ -174,6 +218,18 @@ int pruss_cfg_update(struct pruss *pruss, unsigned int reg, return -ENOTSUPP; } +int pruss_intc_configure(struct pruss *pruss, + struct pruss_intc_config *intc_config) +{ + return -ENOTSUPP; +} + +int pruss_intc_unconfigure(struct pruss *pruss, + struct pruss_intc_config *intc_config) +{ + return -ENOTSUPP; +} + #endif /* CONFIG_TI_PRUSS */ #endif /* __LINUX_PRUSS_H */ From patchwork Thu Nov 22 11:39:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 151764 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp628778ljp; Thu, 22 Nov 2018 03:40:21 -0800 (PST) X-Google-Smtp-Source: AJdET5eqZKRzWEmRo0mhhdkPRNc3itOUeu1ytzjCn3WiFQn8lkMj2KHrwVpCtS/Z8YZaLQE2MON4 X-Received: by 2002:a62:868b:: with SMTP id x133mr11650351pfd.252.1542886821101; Thu, 22 Nov 2018 03:40:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542886821; cv=none; d=google.com; s=arc-20160816; b=T3v5IKWi/oY40FKPwxS9ngHdNYMifvHyfFBHG0FSCRbernXZazNn2xFiNNhpWDc2ET +/dgCx7JlfxwIbC8M4Obk5djKzJ7/AtcreW5SD2zGHyvIMG+ZuXbDmV4aAiJ2n5XSu2y owV0i5So4x016TlYmoTmkRL/KP+VVizdbHRmyIm7soSFmeP6/x37B8baEgen5WzQaaSm gvExbMIDSgjOQ2mmEFM8e7o0f3UOLtcLGoitSTX1uM7Q8Nw8Gpe/AexvPE57dXIco9AK mfPoskpOeNnsY7OraH/HhKY5n/NrY7iQWDqblKwCmqIIa6Dy7l+thFyJ4F0VdYWIASuj YQKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=UH9ZtOEAkM8LjqcjlORrkmUpFi0EsfdDpou6SyOEwFc=; b=rPIQmmAmJzCHQChISXDz1iZiMCxTaFRuwizRe6T17QiCNWcfV8AyOSnLJDPn+ZCfjU g5tLwlH1obLMp845u8yLYDOVhnxaihERz74GeGMuXxYqZlOyFZaPvcVhjrwpu936MCEL QjjUVsn4BabXD6s8glxPTxolnZk3mJlKe7TyN4jtMaE5qPc5VcM+1r9A0rqazIAr9EgE AI22T/5SdDS11cB65LHnqmCmpI9LkO/kQAOVYT5azlpEfE++lgf850dqu3OLXaIEdf0I AC92XbWCR2XfJK/zIzC2TyLsEnDDO4X2ibaE2FtT+gDRYOBPO3mGKpC4u44j2fqmSflA vgmA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=QUARANTINE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 1-v6si51805960plw.81.2018.11.22.03.40.20; Thu, 22 Nov 2018 03:40:21 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=QUARANTINE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2394942AbeKVWTT (ORCPT + 32 others); Thu, 22 Nov 2018 17:19:19 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:58510 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391015AbeKVWTS (ORCPT ); Thu, 22 Nov 2018 17:19:18 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id wAMBeFN6008575; Thu, 22 Nov 2018 05:40:15 -0600 Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wAMBeFVn130530 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 22 Nov 2018 05:40:15 -0600 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 22 Nov 2018 05:40:15 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 22 Nov 2018 05:40:15 -0600 Received: from dlelxv97.itg.ti.com (dlelxv97.itg.ti.com [172.17.2.193]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAMBeFfn025374; Thu, 22 Nov 2018 05:40:15 -0600 Received: from localhost.localdomain (vboxa0400828d.dhcp.ti.com [172.22.239.63]) by dlelxv97.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAMBdDfD013203; Thu, 22 Nov 2018 05:40:11 -0600 From: Roger Quadros To: CC: , , , , , , , , , , , , , , , , Subject: [PATCH 14/17] ARM: OMAP2+: use pdata quirks for PRUSS reset lines on AM335x Date: Thu, 22 Nov 2018 13:39:10 +0200 Message-ID: <1542886753-17625-15-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1542886753-17625-1-git-send-email-rogerq@ti.com> References: <1542886753-17625-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Suman Anna The omap_device API is needed to perform the reset management for any IP instances with PRCM RSTCTRL registers (hard reset lines). This API is limited to the mach-omap2 layer, and cannot be exposed to drivers layer directly. So use platform data ops and pdata quirks for the PRUSS IP in AM335x SoCs to plumb the required omap_device API. The PRUSS SoC bus driver can then use these pdata ops to achieve the required reset functionality. This is being implemented this way as there is no separate reset driver at the moment. Signed-off-by: Suman Anna Signed-off-by: Keerthy --- arch/arm/mach-omap2/pdata-quirks.c | 11 +++++++++++ 1 file changed, 11 insertions(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 9fec5f8..97fc5a2 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -438,6 +439,14 @@ static struct wkup_m3_platform_data wkup_m3_data = { }; #endif +#ifdef CONFIG_SOC_AM33XX +static struct pruss_platform_data pruss_pdata = { + .reset_name = "pruss", + .assert_reset = omap_device_assert_hardreset, + .deassert_reset = omap_device_deassert_hardreset, +}; +#endif + #ifdef CONFIG_SOC_OMAP5 static void __init omap5_uevm_legacy_init(void) { @@ -580,6 +589,8 @@ static struct of_dev_auxdata omap_auxdata_lookup[] = { #ifdef CONFIG_SOC_AM33XX OF_DEV_AUXDATA("ti,am3352-wkup-m3", 0x44d00000, "44d00000.wkup_m3", &wkup_m3_data), + OF_DEV_AUXDATA("ti,am3356-pruss-soc-bus", 0x4a326004, + "4a326004.pruss-soc-bus", &pruss_pdata), #endif #ifdef CONFIG_SOC_AM43XX OF_DEV_AUXDATA("ti,am4372-wkup-m3", 0x44d00000, "44d00000.wkup_m3", From patchwork Thu Nov 22 11:39:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 151765 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp628848ljp; Thu, 22 Nov 2018 03:40:24 -0800 (PST) X-Google-Smtp-Source: AFSGD/WTJy9zcoEE5ZQhYgwyoitYSB9MiZeJn2I3jvJ3P34Pucc4hXdOsCefauT4i+ITRrg7U/7l X-Received: by 2002:a17:902:850c:: with SMTP id bj12mr10733180plb.46.1542886824830; Thu, 22 Nov 2018 03:40:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542886824; cv=none; d=google.com; s=arc-20160816; b=MJLg5YbqS4aMxkGHHANwUGu7fml/RblYyMLkd8p6bzOQWhB7ZVgjw/rmJpTgifi5cg mAonBzQ5N7WaDRWDUwV2rG9sPUDSiH3Ea6Gor829NGswHzj+osbWibW6M4Ch3+Y0YhoV B+wJi2EfwwZehxTRRAeNwbPi3eXTT77TTzlzjA89icKPXvM4T+ova7BGb96+E7YsBNJ2 IVK3VN1wBwVj6rOVOT9ewcIRjjnRaY1w/QTr5iNdQpUI7ZlbmGJoNgZ21GsBtDnFZsyY egUG68z4ox8NGE5e2Z9QbNzU07k9dMgNnQBH+EbC7P7X/sGLhvE/Q7PVcx5jCztPG9XF bJAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=+7/cMm9B5ZwcvkaBZi3/Dsf+EeZ6IItk2wxzfBZ9GO0=; b=ZI09mbhxQgtxus1EIsPjypaMQgAbISswhM6HpxZ0/ZuYEximR8nJ88wNTkOCBSt0oN DrTR0+0lfK3OehK+IipYYiiiAfIUm9Q5IVW2MLAFxNj66evOcZeAyZk1GeTHAjGXlqM3 6p5yFTW1J6RRfXith5oT7lnQL7rT9RFeBK0B4uEjmL+hXQyhtiw1yKFmP9EVmTecAfHI edaru3ZeedyTw8dlwP7DB7PORGDylLa4LdQA7WpNhrkvVPm9kHLYYMAi5R+CEanbu7St SOLbYZ4ZxXCEompTx0JYgT0cvifVL/pVQfvLwGPwSJg6B95F6KS2iU4BhJ6mJBbVhBlm rgjw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=auFUCrtN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 1-v6si51805960plw.81.2018.11.22.03.40.24; Thu, 22 Nov 2018 03:40:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=auFUCrtN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2394956AbeKVWTX (ORCPT + 32 others); Thu, 22 Nov 2018 17:19:23 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:50472 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391015AbeKVWTX (ORCPT ); Thu, 22 Nov 2018 17:19:23 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id wAMBeJ3C075929; Thu, 22 Nov 2018 05:40:19 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1542886819; bh=+7/cMm9B5ZwcvkaBZi3/Dsf+EeZ6IItk2wxzfBZ9GO0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=auFUCrtNiJFuygz9/nuuq6oVApTCrT5o6tuHCFsemqDpc2t9buPLciBMeOMHHg3Ec qIkVWo/4vqdbW+PpUZTQrKj1+G7/Zr+BMkin/S70YmkFt9mxXm4EpPq+zHKLdlnAsm 1FNXb1vqKOj9DOIJ/OwgmXPdAxzALvOw/Pmabvw0= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wAMBeJ1s077516 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 22 Nov 2018 05:40:19 -0600 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 22 Nov 2018 05:40:19 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 22 Nov 2018 05:40:19 -0600 Received: from dlelxv97.itg.ti.com (dlelxv97.itg.ti.com [172.17.2.193]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAMBeJG2012012; Thu, 22 Nov 2018 05:40:19 -0600 Received: from localhost.localdomain (vboxa0400828d.dhcp.ti.com [172.22.239.63]) by dlelxv97.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAMBdDfE013203; Thu, 22 Nov 2018 05:40:15 -0600 From: Roger Quadros To: CC: , , , , , , , , , , , , , , , , Subject: [PATCH 15/17] ARM: dts: AM33xx: Add the PRU-ICSS DT nodes Date: Thu, 22 Nov 2018 13:39:11 +0200 Message-ID: <1542886753-17625-16-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1542886753-17625-1-git-send-email-rogerq@ti.com> References: <1542886753-17625-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Suman Anna Add the DT nodes for the PRU-ICSS on AM33xx family of SoCs. The AM33xx SoCs contain a single PRU-ICSS instance and is represented by the pruss-soc-bus node and a child PRUSS node. PRU-ICSS is not supported on AM3352 SoC though in the AM33xx family, so the nodes are added in disabled state to the common am33xx dtsi file. They should be enabled in only those derivative board files that use a SoC containing PRU-ICSS. The PRUSS subsystem node contains the entire address space and the various interrupts generated towards the main MPU. The various sub-modules of the PRU-ICSS are represented as individual child nodes (so platform devices themselves) of the PRUSS subsystem node. These include the two PRU cores and the interrupt controller. The Industrial Ethernet Peripheral (IEP), the Real Time Media Independent Interface controller (MII_RT), and the CFG sub-module are represented as syscon nodes. All the Data RAMs are represented within a child node of its own named 'memories' without any compatible. The DT nodes use all standard properties. The regs property in the PRU nodes define the addresses for the Instruction RAM, the Debug and Control sub-modules for that PRU core. The firmware for each PRU core is defined through a 'firmware-name' property. The default names for the firmware images for each PRU core are defined as follows (these can be adjusted either in derivative board dts files or through sysfs at runtime if required): PRU-ICSS PRU0 Core: am335x-pru1_0-fw PRU-ICSS PRU1 Core: am335x-pru1_1-fw Signed-off-by: Suman Anna --- arch/arm/boot/dts/am33xx.dtsi | 72 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index d3dd6a1..ce42cd9 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -924,6 +924,78 @@ }; }; + pruss_soc_bus: pruss_soc_bus@4a326004 { + compatible = "ti,am3356-pruss-soc-bus"; + reg = <0x4a326004 0x4>; + ti,hwmods = "pruss"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + pruss: pruss@4a300000 { + compatible = "ti,am3356-pruss"; + reg = <0x4a300000 0x80000>; + interrupts = <20 21 22 23 24 25 26 27>; + interrupt-names = "host2", "host3", "host4", + "host5", "host6", "host7", + "host8", "host9"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + pruss_mem: memories@4a300000 { + reg = <0x4a300000 0x2000>, + <0x4a302000 0x2000>, + <0x4a310000 0x3000>; + reg-names = "dram0", "dram1", + "shrdram2"; + }; + + pruss_cfg: cfg@4a326000 { + compatible = "syscon"; + reg = <0x4a326000 0x2000>; + }; + + pruss_iep: iep@4a32e000 { + compatible = "syscon"; + reg = <0x4a32e000 0x31c>; + }; + + pruss_mii_rt: mii_rt@4a332000 { + compatible = "syscon"; + reg = <0x4a332000 0x58>; + }; + + pruss_intc: intc@4a320000 { + compatible = "ti,am3356-pruss-intc"; + reg = <0x4a320000 0x2000>; + reg-names = "intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + pru0: pru@4a334000 { + compatible = "ti,am3356-pru"; + reg = <0x4a334000 0x2000>, + <0x4a322000 0x400>, + <0x4a322400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am335x-pru0-fw"; + }; + + pru1: pru@4a338000 { + compatible = "ti,am3356-pru"; + reg = <0x4a338000 0x2000>, + <0x4a324000 0x400>, + <0x4a324400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am335x-pru1-fw"; + }; + }; + }; + elm: elm@48080000 { compatible = "ti,am3352-elm"; reg = <0x48080000 0x2000>; From patchwork Thu Nov 22 11:39:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 151766 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp628924ljp; Thu, 22 Nov 2018 03:40:29 -0800 (PST) X-Google-Smtp-Source: AFSGD/UF9gO7MvnJh7AzBaWRhKwB6LsJBMhQI2TtHs6/M+xjAveWTBKZ1khnrTp94QiGjiIi6OoA X-Received: by 2002:a63:2222:: with SMTP id i34mr8972833pgi.83.1542886829464; Thu, 22 Nov 2018 03:40:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542886829; cv=none; d=google.com; s=arc-20160816; b=tdcn6H03y+H0JRddSuJgX+xpDdeIjbL2SRp5BfornAblIfbRSDIa99bgBMGZr+h62S B6kcuymS1yE7+EuS2Tuk0IFA23nSYx6h1DOSzBOTk4KPqkdy1j+goyQeVHIVMK6Ko4y5 j3sXFHvtENdhjEJyPzK1AIMIvbW9oJzjdD3dvRqjIoCqo7lEZ4DXrJKHbvOL9cmCab3R mGuhNuEnbr1oBhkLdIHiH6XV14CXPpBFjr7qFfSojoPB7IZlCN8C9ul1BBBBCfucJ/mY 5Ei9MOO4dgwLARFizH1yxs3dHAOGcHSt/iNBdLmOF4q27y96RpR546I9ezlX2d2K+hIX O+sg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=Ng5z4dagtHX8lvj6nUscX5CiLZR34B+6mpicKjwn6Pg=; b=VWFPU6rcCiuZTLHbqTC0TlmY9Xa1Ri1F7Z8MsIiJngbl04mo/+YxTeGSW+2DsnvFfF dJfHpzAizyf/5ryLii9ZegX/9zVDQgwcm5K+5YKxkmMlVZ2mPtOzFT7OA1Fw8wOdyOSG erwPdcrD1urMxdzompVLtzx/6kY1j9A3YLeRhTXoBeMHA+YM2mzXLPwTJ2dqL6V0Feu6 jV0i6TNUBfN0kzoazMYET6VSV1eMD+Okm21IXRyOE1PMIdW4umsX/dlB/oK3oHZ8H5wl GxEWakO1TlxCgw+1jZjkc+q2oCEPkUNXcJWIw4iB8Qz49xjwvpVDw2SUF+ah8LFENZFB P47w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=QUARANTINE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x124-v6si54430682pfb.154.2018.11.22.03.40.29; Thu, 22 Nov 2018 03:40:29 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=QUARANTINE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2394975AbeKVWT1 (ORCPT + 32 others); Thu, 22 Nov 2018 17:19:27 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:58524 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2394958AbeKVWT1 (ORCPT ); Thu, 22 Nov 2018 17:19:27 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id wAMBeNQX008613; Thu, 22 Nov 2018 05:40:23 -0600 Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wAMBeNYY130688 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 22 Nov 2018 05:40:23 -0600 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 22 Nov 2018 05:40:23 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 22 Nov 2018 05:40:23 -0600 Received: from dlelxv97.itg.ti.com (dlelxv97.itg.ti.com [172.17.2.193]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAMBeNSb028209; Thu, 22 Nov 2018 05:40:23 -0600 Received: from localhost.localdomain (vboxa0400828d.dhcp.ti.com [172.22.239.63]) by dlelxv97.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAMBdDfF013203; Thu, 22 Nov 2018 05:40:19 -0600 From: Roger Quadros To: CC: , , , , , , , , , , , , , , , , Subject: [PATCH 16/17] ARM: dts: AM33xx: Add PRU system events for virtio Date: Thu, 22 Nov 2018 13:39:12 +0200 Message-ID: <1542886753-17625-17-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1542886753-17625-1-git-send-email-rogerq@ti.com> References: <1542886753-17625-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Suman Anna Two PRU system events "vring" and "kick" have been added to each of the PRU nodes in the PRU-ICSS remote processor subsystem to enable the virtio/rpmsg communication between MPU and that PRU core. The additions are done in the base am33xx.dtsi file, and so are inherited by all the AM33xx boards. Do note that PRUSS is not available on all AM335x SoCs. The PRU system events is the preferred approach over using OMAP mailboxes, as it eliminates an external peripheral access from the PRU-side, and keeps the interrupt generation internal to the PRUSS. The difference from MPU would be minimal in using one versus the other. Mailboxes can still be used if desired. Either approach would require that an appropriate firmware image is loaded/booted on the PRU. Signed-off-by: Suman Anna --- arch/arm/boot/dts/am33xx.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index ce42cd9..b7e3f69 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -983,6 +983,9 @@ <0x4a322400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am335x-pru0-fw"; + interrupt-parent = <&pruss_intc>; + interrupts = <16>, <17>; + interrupt-names = "vring", "kick"; }; pru1: pru@4a338000 { @@ -992,6 +995,9 @@ <0x4a324400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am335x-pru1-fw"; + interrupt-parent = <&pruss_intc>; + interrupts = <18>, <19>; + interrupt-names = "vring", "kick"; }; }; }; From patchwork Thu Nov 22 11:39:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 151767 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp629035ljp; Thu, 22 Nov 2018 03:40:35 -0800 (PST) X-Google-Smtp-Source: AJdET5efod6Vt3SI1eH5R9aKExVKGdRgG0q9aE6Vae3NPymNr+hNeN/sOGqlsRE23tILmkePCUHn X-Received: by 2002:a62:8915:: with SMTP id v21-v6mr11260700pfd.137.1542886835204; Thu, 22 Nov 2018 03:40:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542886835; cv=none; d=google.com; s=arc-20160816; b=WO5XgDy+mcDeOAQewlCwtuJVTozyre7z6B9mmXAF4/nL6xf6Vzrw9i9qyLljVufj0d s07QMnQ+smIkB9gGmC2O9/2pgZ745ZEmwxurmcs9B7xwoeteLPCL3/jfInnUQpxJhaR0 8BGFxWiIObDtZbq+PDLs+9prfn5+v6PPEjzAJDRyHgBY/+me3VGtKzkEyQcnWANQI2Po LQ4kVKTzjGphvZoLHVhddyNiciuD3GfLe/XRU1X6CLtZJMiTnaN+HT8SG4VkqRrGVQKD 0gFv858oR1IPxw4opAtXTBUy8o4F/64IAbr8ad/GwtzAgw2LfW6f8ClImrbK7W0GkrfO sWzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=ftWSvjI7qlQpDwhFOSUwMXmg9aHPDUkp4ZjQ1EVmo1M=; b=IXdAIhnEWfXMj10CkrQa7wigDRLPY210dnxGx+67b7Axs1vRz62OUZ2OsQQgge818r PSX7JiIwHq9C5wzfytzj04ZUU+iOVFkjMqyYZ0cJcrmcy6//sUc3Mp18OGOhBvzkxlcs terHz8LAm/3sY5PW+Ye+n+6TEmLfW10ZG8B8tv7Seu2D9lRJVSpv+DaB9LW8hj1eRBNw 1kP+Q9n942DBrTaGNzM6wsv7eY5WXCsYW1+hjtBNs8Bx0xJTAFO6LpUTO6JEFORIwhI/ 31u1oyliBdtTUrgncdurCKzvKY6q0z4fy794AWOGkxpW8well7d4/CwJ0KfL/T435oZO k9BA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=AECXo4KT; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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PRU-ICSS is supported on these AM335x boards so enable the PRUSS node. Signed-off-by: Suman Anna Signed-off-by: Roger Quadros --- arch/arm/boot/dts/am335x-bone-common.dtsi | 8 ++++++++ arch/arm/boot/dts/am335x-evm.dts | 8 ++++++++ arch/arm/boot/dts/am335x-evmsk.dts | 8 ++++++++ arch/arm/boot/dts/am335x-icev2.dts | 8 ++++++++ 4 files changed, 32 insertions(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 9e5e75e..ea0e869 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -422,3 +422,11 @@ clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; }; + +&pruss_soc_bus { + status = "okay"; + + pruss: pruss@4a300000 { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 98ec9c3..0e07160 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -800,3 +800,11 @@ clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; }; + +&pruss_soc_bus { + status = "okay"; + + pruss: pruss@4a300000 { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 245868f..f152c15 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -741,3 +741,11 @@ clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; }; + +&pruss_soc_bus { + status = "okay"; + + pruss: pruss@4a300000 { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts index f2005ec..7d2fff2e 100644 --- a/arch/arm/boot/dts/am335x-icev2.dts +++ b/arch/arm/boot/dts/am335x-icev2.dts @@ -504,3 +504,11 @@ reg = <3>; }; }; + +&pruss_soc_bus { + status = "okay"; + + pruss: pruss@4a300000 { + status = "okay"; + }; +};