From patchwork Wed Feb 16 09:32:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: xinlei.lee@mediatek.com X-Patchwork-Id: 543126 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27E1FC433F5 for ; Wed, 16 Feb 2022 09:33:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232273AbiBPJdU (ORCPT ); Wed, 16 Feb 2022 04:33:20 -0500 Received: from gmail-smtp-in.l.google.com ([23.128.96.19]:57938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232286AbiBPJdT (ORCPT ); Wed, 16 Feb 2022 04:33:19 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8ECDEAC99; Wed, 16 Feb 2022 01:33:05 -0800 (PST) X-UUID: d8344ab55d6a460098bcb3ebe48bf921-20220216 X-UUID: d8344ab55d6a460098bcb3ebe48bf921-20220216 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 302646374; Wed, 16 Feb 2022 17:33:02 +0800 Received: from MTKMBS34N1.mediatek.inc (172.27.4.172) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Feb 2022 17:33:00 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS34N1.mediatek.inc (172.27.4.172) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Feb 2022 17:32:59 +0800 Received: from mszsdaap41.gcn.mediatek.inc (10.16.6.141) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Feb 2022 17:32:58 +0800 From: To: , , , , , CC: , , , , , , , Xinlei Lee Subject: [v2,1/4] dt-bindings: pwm: Convert pwm-mtk-disp.txt to mediatek,pwm-disp.yaml format Date: Wed, 16 Feb 2022 17:32:48 +0800 Message-ID: <1645003971-16908-2-git-send-email-xinlei.lee@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1645003971-16908-1-git-send-email-xinlei.lee@mediatek.com> References: <1645003971-16908-1-git-send-email-xinlei.lee@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Xinlei Lee Convert pwm-mtk-disp.txt to mediatek,pwm-disp.yaml format as suggested by maintainer Signed-off-by: Xinlei Lee --- .../bindings/pwm/mediatek,pwm-disp.yaml | 71 +++++++++++++++++++ .../devicetree/bindings/pwm/pwm-mtk-disp.txt | 44 ------------ 2 files changed, 71 insertions(+), 44 deletions(-) create mode 100755 Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml delete mode 100644 Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml new file mode 100755 index 000000000000..edf2a2e9ea72 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/mediatek,pwm-disp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek PWM Controller Device Tree Bindings + +maintainers: + - Jitao Shi + - Xinlei Lee + +properties: + compatible: + enum: + - mediatek,mt2701-disp-pwm + - mediatek,mt6595-disp-pwm + - mediatek,mt8173-disp-pwm + - mediatek,mt8183-disp-pwm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + "#pwm-cells": + description: + Number of cells in a PWM specifier. + + clocks: + items: + - description: Main Clock + - description: Mm Clock + + clock-names: + items: + - const: main + - const: mm + +required: + - compatible + - reg + - interrupts + - power-domains + - "#pwm-cells" + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + pwm: pwm@1100e000 { + compatible = "mediatek,mt8183-disp-pwm"; + reg = <0x1100e000 0x1000>; + interrupts = ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + #pwm-cells = <2>; + clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>, + <&infracfg CLK_INFRA_DISP_PWM>; + clock-names = "main", "mm"; + }; diff --git a/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt deleted file mode 100644 index 902b271891ae..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt +++ /dev/null @@ -1,44 +0,0 @@ -MediaTek display PWM controller - -Required properties: - - compatible: should be "mediatek,-disp-pwm": - - "mediatek,mt2701-disp-pwm": found on mt2701 SoC. - - "mediatek,mt6595-disp-pwm": found on mt6595 SoC. - - "mediatek,mt8167-disp-pwm", "mediatek,mt8173-disp-pwm": found on mt8167 SoC. - - "mediatek,mt8173-disp-pwm": found on mt8173 SoC. - - reg: physical base address and length of the controller's registers. - - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of - the cell format. - - clocks: phandle and clock specifier of the PWM reference clock. - - clock-names: must contain the following: - - "main": clock used to generate PWM signals. - - "mm": sync signals from the modules of mmsys. - - pinctrl-names: Must contain a "default" entry. - - pinctrl-0: One property must exist for each entry in pinctrl-names. - See pinctrl/pinctrl-bindings.txt for details of the property values. - -Example: - pwm0: pwm@1401e000 { - compatible = "mediatek,mt8173-disp-pwm", - "mediatek,mt6595-disp-pwm"; - reg = <0 0x1401e000 0 0x1000>; - #pwm-cells = <2>; - clocks = <&mmsys CLK_MM_DISP_PWM026M>, - <&mmsys CLK_MM_DISP_PWM0MM>; - clock-names = "main", "mm"; - pinctrl-names = "default"; - pinctrl-0 = <&disp_pwm0_pins>; - }; - - backlight_lcd: backlight_lcd { - compatible = "pwm-backlight"; - pwms = <&pwm0 0 1000000>; - brightness-levels = < - 0 16 32 48 64 80 96 112 - 128 144 160 176 192 208 224 240 - 255 - >; - default-brightness-level = <9>; - power-supply = <&mt6397_vio18_reg>; - enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>; - }; From patchwork Wed Feb 16 09:32:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: xinlei.lee@mediatek.com X-Patchwork-Id: 543125 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7FACBC433F5 for ; Wed, 16 Feb 2022 09:33:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232308AbiBPJdc (ORCPT ); Wed, 16 Feb 2022 04:33:32 -0500 Received: from gmail-smtp-in.l.google.com ([23.128.96.19]:59526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232328AbiBPJda (ORCPT ); Wed, 16 Feb 2022 04:33:30 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1C580EDF04; Wed, 16 Feb 2022 01:33:13 -0800 (PST) X-UUID: 60dc1293a867486e8c80387f5f1569fd-20220216 X-UUID: 60dc1293a867486e8c80387f5f1569fd-20220216 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1718772956; Wed, 16 Feb 2022 17:33:09 +0800 Received: from MTKMBS34N1.mediatek.inc (172.27.4.172) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 16 Feb 2022 17:33:07 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS34N1.mediatek.inc (172.27.4.172) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Feb 2022 17:33:06 +0800 Received: from mszsdaap41.gcn.mediatek.inc (10.16.6.141) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Feb 2022 17:33:05 +0800 From: To: , , , , , CC: , , , , , , , Xinlei Lee Subject: [v2,3/4] dt-bindings: pwm: Add compatible for MediaTek MT8195 Date: Wed, 16 Feb 2022 17:32:50 +0800 Message-ID: <1645003971-16908-4-git-send-email-xinlei.lee@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1645003971-16908-1-git-send-email-xinlei.lee@mediatek.com> References: <1645003971-16908-1-git-send-email-xinlei.lee@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Xinlei Lee Add dt-binding documentation of pwm for MediaTek MT8195 SoC. Signed-off-by: Xinlei Lee --- Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml index 825cad513309..768ab04d3764 100755 --- a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml +++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml @@ -18,6 +18,7 @@ properties: - mediatek,mt8173-disp-pwm - mediatek,mt8183-disp-pwm - mediatek,mt8192-disp-pwm + - mediatek,mt8195-disp-pwm reg: maxItems: 1