From patchwork Thu Jun 1 17:10:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 100963 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp861318obc; Thu, 1 Jun 2017 10:21:37 -0700 (PDT) X-Received: by 10.55.141.133 with SMTP id p127mr3108112qkd.216.1496337697616; Thu, 01 Jun 2017 10:21:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496337697; cv=none; d=google.com; s=arc-20160816; b=K5CSx881xy6mjlj0J2T5zlHZtWXwx5HWgtTyhc5TY4CIz8t5n1UrDkoScwOMQYKOBJ YVIwf88mi2HzwOj91zqXDkGcfczSoJJZP2+rDRxvKA1RHnuc914WpxPOFU3m7ZPJ8lov GIAEkzKme2sRiC4k+8pmGwVH0/juzNd/dRlabh0d6lP/2F+pW39CY7U4H3XkF6kn2DMc PR+jCz9r/AKcS0FUrTTLy5BOAyRsJXGkjhNocakg/KekDmwDOzx6QJNMwBZ1Ymv/g++v 3ARNq2uOOFrFGidYWlm49gyqNHLTZs9dH+T2cfYq2wAsR0yRnCIoImbvzwjyZEa5iETh gfvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=kQOep00xmqAgWUdGX5HwrPnqVXm48ZatfuPvhLTJD5Y=; b=Asbv2AuJNIflZeCreLKdnMtaiOvasvcbC0JhiIPyG7bAeBbGNuT14YdIzSZ56fYtj+ tyUjMYG8O/Alo+JQHyuRHfRubIeHzUjjvLJ1lULf9kYXAIwPOGw+k4R8eDwcfI0aL68H Ei5y7keHsjShVkEsCsDBwwaM1JoM17Gm1C4Ab4CJIZRenvOV97ype4qe4IdN790BtaLD FglffRZXPb2HPlMi7rWoGWMZccKVIIy8t7P0NEoxtrGlu9JZzPb3w0SpQX+LJ//Zc76R 7mfgi8iO+c0wsNyZTap/vtwKMEc0Z7zr1DFpZptBzo8rUO7fjQb4eCJ15N9ratxk6EEq P7Tw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id u65si19906304qkf.84.2017.06.01.10.21.37 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Jun 2017 10:21:37 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45846 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTmw-0002F6-Ti for patch@linaro.org; Thu, 01 Jun 2017 13:21:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35251) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTcZ-00017H-Fe for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGTcY-0006Cc-9s for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:51 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37145) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTcY-00067A-07 for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:50 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTcL-0007NC-3T for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:37 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:09 +0100 Message-Id: <1496337035-30213-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 01/27] libvixl: Correct build failures on NetBSD X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Kamil Rytarowski Ensure that C99 macros are defined regardless of the inclusion order of headers in vixl. This is required at least on NetBSD. The vixl/globals.h headers defines __STDC_CONSTANT_MACROS and must be included before other system headers. This file defines unconditionally the following macros, without altering the original sources: - __STDC_CONSTANT_MACROS - __STDC_LIMIT_MACROS - __STDC_FORMAT_MACROS Signed-off-by: Kamil Rytarowski Reviewed-by: Philippe Mathieu-Daudé Message-id: 20170514051820.15985-1-n54@gmx.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- disas/libvixl/Makefile.objs | 3 +++ 1 file changed, 3 insertions(+) -- 2.7.4 diff --git a/disas/libvixl/Makefile.objs b/disas/libvixl/Makefile.objs index bbe7695..860fb7f 100644 --- a/disas/libvixl/Makefile.objs +++ b/disas/libvixl/Makefile.objs @@ -7,5 +7,8 @@ libvixl_OBJS = vixl/utils.o \ # The -Wno-sign-compare is needed only for gcc 4.6, which complains about # some signed-unsigned equality comparisons which later gcc versions do not. $(addprefix $(obj)/,$(libvixl_OBJS)): QEMU_CFLAGS := -I$(SRC_PATH)/disas/libvixl $(QEMU_CFLAGS) -Wno-sign-compare +# Ensure that C99 macros are defined regardless of the inclusion order of +# headers in vixl. This is required at least on NetBSD. +$(addprefix $(obj)/,$(libvixl_OBJS)): QEMU_CFLAGS += -D__STDC_CONSTANT_MACROS -D__STDC_LIMIT_MACROS -D__STDC_FORMAT_MACROS common-obj-$(CONFIG_ARM_A64_DIS) += $(libvixl_OBJS) From patchwork Thu Jun 1 17:10:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 100962 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp861153obc; Thu, 1 Jun 2017 10:21:14 -0700 (PDT) X-Received: by 10.200.36.162 with SMTP id s31mr3480580qts.224.1496337674026; Thu, 01 Jun 2017 10:21:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496337674; cv=none; d=google.com; s=arc-20160816; b=nMJVQKUOZLYC1XA+PNrOJKWXGggVyOi/mvKJtuPMP7blRxubTFQ9G7JrdXyogxgw5S iz5DhV3e0mdqNIEGnZtUs8maBHmWkVTgJk7huXVhD38dfulT26KLBNZBkCP6QizLEqji uLCm0RLKjQnbymyCbuhGOoI4lEZCdG22hZLIb88SXEL72Ak1bKocAgXW9g/oGvCCM9z/ HJlJxW1MJvlJotJ7CNIEUc9X+lymdUmOVjeeGMIGQdX/PibIaCcn8kuOQkKoP+5hx0sV oJaaIOfw5DmeY/DRUidIIHjbLO3VopjNKlcZvhdTKIUkRiLcfHgkYbhI6jRiJylca8Yg zcvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=8zAyDdOR6dqaRkLTaaTImB1wtcyGXzElc1oGtEawhbw=; b=Fi+IpQD+qwP76QST5ra5TsuTcMneMIF9DNehI7x0xPXpcUrmw6zec/gxo+1IcvR3Rm tc4y3zaF8gLWjBCxhotahiFk3t9jrGxNn3vzr4JKJxUJS8l+/2u45fBs/N5/HLOGRVH3 mc+N/DxLw3HoBgKjh8lwRYqS5vrSM0iG16w+iNGZmxUXZ2vxxXjaTZTk2yXgoowj8zmk tzm6aBObGajDwULkEDGQbQDWuaA9YhN/9gxGjRqHm5FjDnsaTvqrsuuLvOeD/3o0SgdG 44QCtD5dpV03NT+L4GnFp+b5VzRe2c+Xw24rv7OMA9pZd0PvhVCyk2yTp7zD/bdZieK0 AZeQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id m12si14490415qki.192.2017.06.01.10.21.13 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Jun 2017 10:21:14 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45843 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTmZ-0001wT-F3 for patch@linaro.org; Thu, 01 Jun 2017 13:21:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35246) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTcZ-00017F-B8 for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGTcY-0006Bx-0V for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:51 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37147) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTcX-0006AO-Oh for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:49 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTcL-0007NZ-NO for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:37 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:10 +0100 Message-Id: <1496337035-30213-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 02/27] load_uboot_image: don't assume a full header read X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Andrew Jones Don't allow load_uboot_image() to proceed when less bytes than header-size was read. Signed-off-by: Andrew Jones Message-id: 20170524091315.20284-1-drjones@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/core/loader.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/hw/core/loader.c b/hw/core/loader.c index bf17b42..f72930c 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -611,8 +611,9 @@ static int load_uboot_image(const char *filename, hwaddr *ep, hwaddr *loadaddr, return -1; size = read(fd, hdr, sizeof(uboot_image_header_t)); - if (size < 0) + if (size < sizeof(uboot_image_header_t)) { goto out; + } bswap_uboot_header(hdr); From patchwork Thu Jun 1 17:10:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 100970 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp863444obc; Thu, 1 Jun 2017 10:26:46 -0700 (PDT) X-Received: by 10.55.137.7 with SMTP id l7mr3330170qkd.122.1496338006200; Thu, 01 Jun 2017 10:26:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496338006; cv=none; d=google.com; s=arc-20160816; b=jqVOgnwHaz/mFW8rYfNDczjNcwNZkJCKcM9a/AYEEP8l7egyCOVFWkj5QZBiO7XYyJ 9bLltiH+4E7samSXszdcw6Jb30JIHHF4Embggn1g8h5OYuhX5/1A9L3ggC+xyX/pPyFe VUGun5HQiLgctvWUu4x1sCpOrS1BTYk4lOagDCeY3Vf/sRHrFLxT58LF6rCpXPZrnBeL clQPWr9wrzv+Nb/4PuCO/qS6fjgZOoH9O/zZrR/aIc7uK0/2ihN3dCyp96AS4xTm4Ajb soyBrOrFLqyTQg3rU2iGXILtYIgszkzxNBWUyBuEC2dW7lPyf3q10s54QW4Vq3ncTYQ2 OJNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=HlBb3GoPUxY7aNVT2X8zRlMw5mPQeMPaYmGqPcsWPlw=; b=CKQgeKQNp+YHrq9U9YWUHYpuOBXsLYonkilBuSZ+EPpVBXGLReiiXS6MzHXFJwOinE K5YY+bGCrrevn9NsS0e5XQmTORQg7kUgIzULWodA+ujaigmYsAb8IdRr5OGyDIT0Eoyb M50oqE2xn9d+rIWE6OLRv6kCZKC7+ARkorCEO6CrBw+K0bPRB7RDfuPBhqfccB8bYObo Jf1RoZ2kJDZt/ryzOmEnrgLlyi/EGhO2A5DlhspTv6nAgwXiiESIi+2mzfme5xq+Lqa/ H2XmSNjfOBINzoEFYG9vi538HIY4OCJ6oeDEDJhfO6SotzlATfYFa6FHHbdeqLf86XXG ASsw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id t11si20258389qth.148.2017.06.01.10.26.45 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Jun 2017 10:26:46 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45869 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTrv-00070p-Em for patch@linaro.org; Thu, 01 Jun 2017 13:26:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35343) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTcb-0001Ac-W9 for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGTcX-0006Bi-RW for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:53 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37144) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTcX-00064g-Ix for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:49 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTcM-0007Nx-Cw for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:38 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:11 +0100 Message-Id: <1496337035-30213-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 03/27] hw/intc/arm_gicv3_cpuif: Fix reset value for VMCR_EL2.VBPR1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We were setting the VBPR1 field of VMCR_EL2 to icv_min_vbpr() on reset, but this is not correct. The field should reset to the minimum value of ICV_BPR0_EL1 plus one. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 1493226792-3237-2-git-send-email-peter.maydell@linaro.org --- hw/intc/arm_gicv3_cpuif.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 0b20856..d31eba0 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -2014,7 +2014,7 @@ static void icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) cs->ich_hcr_el2 = 0; memset(cs->ich_lr_el2, 0, sizeof(cs->ich_lr_el2)); cs->ich_vmcr_el2 = ICH_VMCR_EL2_VFIQEN | - (icv_min_vbpr(cs) << ICH_VMCR_EL2_VBPR1_SHIFT) | + ((icv_min_vbpr(cs) + 1) << ICH_VMCR_EL2_VBPR1_SHIFT) | (icv_min_vbpr(cs) << ICH_VMCR_EL2_VBPR0_SHIFT); } From patchwork Thu Jun 1 17:10:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 100959 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp860264obc; Thu, 1 Jun 2017 10:19:01 -0700 (PDT) X-Received: by 10.200.36.108 with SMTP id d41mr3307365qtd.42.1496337541062; Thu, 01 Jun 2017 10:19:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496337541; cv=none; d=google.com; s=arc-20160816; b=kd8xayjhQe26oQaVhqbvOCpXK3tjTdfj3Y4/JfDm2gYLw3ZgKENynfYrBI4zzrU2zU WLVbpR1YXFvJCb4I7wZUpwY9/AwjmDfJIZTWsXYJo0XQVDs2/5oV7DzIHj+o8qmf4XCn Ryn+QnLRkv5tUhACD4Z3vUtIn/2v9XFzK6uByl2wAY3VPmpjJAQVUL/7EW+CbzYOhWEH fbOgtPATSN0xuHzNLdeu5Gjm7JQDc+G6KY/exS+lJ+h//eUR+N/F71sOfff37odpTP5U MR/6q2zM+sw0Lizxpdb9W4Xsk6qifY81Jsg2GeEPwTugPHgo8AgK0OzkxNgyTmJC12B4 COnQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=Kb2+yIv84DB/diH76qHAinbkVr/3lMk2L6Ie2RDagPA=; b=n4UtoM6imQnglaF55Y42hdN/BNUP1QfnBtwF5xKFMwo13oXmy0XIhF83zJ9f0VXa8A HHG9Q3/dDuHe3wl+oEwopUK94plB86jBM9AGCaaQfR/9JDMhwgCjNBDxVWSIQmDLKn0U UR7jpiDfFxqDgi3kiLymG2rV5y8Jc5EGs4ri0cipbXihpduk0PRcTy5l4gCyq/R+3UX+ meO8GW69k45zEOCQOL697OuYFs207QgrkPXRp3j3QlVkg0XaqCk0tjzBAg2gfBoQf3f7 cnwnF8VR/SX8EEXsQssIStj35gRPBdj/v3XNEaVZaPB5Q7YQJ1xZaXHru+cAuQ0cj6/W kkew== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id g2si20178689qte.191.2017.06.01.10.19.00 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Jun 2017 10:19:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45832 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTkQ-0008UP-CH for patch@linaro.org; Thu, 01 Jun 2017 13:18:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35203) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTcY-00017C-DH for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGTcX-0006BU-AW for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:50 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37145) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTcX-00067A-1b for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:49 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTcN-0007OB-00 for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:39 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:12 +0100 Message-Id: <1496337035-30213-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 04/27] hw/intc/arm_gicv3_cpuif: Don't let BPR be set below its minimum X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" icc_bpr_write() was not enforcing that writing a value below the minimum for the BPR should behave as if the BPR was set to the minimum value. This doesn't make a difference for the secure BPRs (since we define the minimum for the QEMU implementation as zero) but did mean we were allowing the NS BPR1 to be set to 0 when 1 should be the lowest value. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 1493226792-3237-3-git-send-email-peter.maydell@linaro.org --- hw/intc/arm_gicv3_cpuif.c | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.7.4 diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index d31eba0..e660b3f 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -1388,6 +1388,7 @@ static void icc_bpr_write(CPUARMState *env, const ARMCPRegInfo *ri, { GICv3CPUState *cs = icc_cs_from_env(env); int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1; + uint64_t minval; if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) { icv_bpr_write(env, ri, value); @@ -1415,6 +1416,11 @@ static void icc_bpr_write(CPUARMState *env, const ARMCPRegInfo *ri, return; } + minval = (grp == GICV3_G1NS) ? GIC_MIN_BPR_NS : GIC_MIN_BPR; + if (value < minval) { + value = minval; + } + cs->icc_bpr[grp] = value & 7; gicv3_cpuif_update(cs); } From patchwork Thu Jun 1 17:10:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 100960 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp860769obc; Thu, 1 Jun 2017 10:20:14 -0700 (PDT) X-Received: by 10.237.62.136 with SMTP id n8mr3529682qtf.0.1496337614049; Thu, 01 Jun 2017 10:20:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496337614; cv=none; d=google.com; s=arc-20160816; b=a9tMVsti8dFMymuXhRtJEgPKPRDovIN9RavlbLsOfa9ZodU8vjhxlCUY/CeQd6a9q1 pS8VoSWDeyg0McBiIzL6l3Xyg/4LlKA9EK5Ks5LIhDKL4iqYtAoA6VhpDobStr8peCGL dJfgPPoYAdd+BGXLCM+mAXUQfJaueoG0Evw/Fq+ubk4CJhrS0CdCSqG9pX4jKl5ONrBN 9f7RtWfr7qwqU1oUg3Oliz4bSZbok7HNTHYLqBxtaIbH5GQWAQ5FLPyl80rbKJu5BH+y FvDCYi7l654fZU0iTJbPPvCtqb1SpknkfgEkX1OnPBrCZjLetVDj9HpJBQ7Kjd+3gfBd qqTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=XhUPosrKYZNPjxh112WF1BbnFZpacucs78fdvM1M318=; b=ieEDncH9TFih+C8nTELEAhwo8ovDvOKOkiPGb40oauqeCXSpGUF24wNfVG61gP6fUS /a6PnGayG8/iy/dkNAdyG7MNPqtnl5bqHzwRJJ3zao2TD2BV8sxC43D92cdgmvLy86+Z JFY1ZklXuEZv8viGef2JXcwggkKOmbAorwB3ICgu2iRpMCEvkYqkO5JF6lhvFlJCzu+Z 0OsrWrNfBUhWJyDrs0gAYW3njkaqV20vSWPihBL2cLMJGcsdrUToAzBbOXxsovmkYAaV mn+AX4Qr6WdZ8aJ9RkdMTtc+P6O9Z1TSKmaEGMZOA5UxROIY6/mOqE0B2ha3pfjOjj/q tJNg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id u18si19683061qka.46.2017.06.01.10.20.13 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Jun 2017 10:20:14 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45833 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTlb-0000qn-Am for patch@linaro.org; Thu, 01 Jun 2017 13:20:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35192) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTcY-000170-3Z for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGTcW-0006B4-T6 for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:50 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37144) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTcW-00064g-Ki for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:48 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTcN-0007OP-II for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:39 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:13 +0100 Message-Id: <1496337035-30213-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 05/27] hw/intc/arm_gicv3_cpuif: Fix priority masking for NS BPR1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When we calculate the mask to use to get the group priority from an interrupt priority, the way that NS BPR1 is handled differs from how BPR0 and S BPR1 work -- a BPR1 value of 1 means the group priority is in bits [7:1], whereas for BPR0 and S BPR1 this is indicated by a 0 BPR value. Subtract 1 from the BPR value before creating the mask if we're using the NS BPR value, for both hardware and virtual interrupts, as the GICv3 pseudocode does, and fix the comments accordingly. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 1493226792-3237-4-git-send-email-peter.maydell@linaro.org --- hw/intc/arm_gicv3_cpuif.c | 42 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 38 insertions(+), 4 deletions(-) -- 2.7.4 diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index e660b3f..09d8ba0 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -216,18 +216,35 @@ static uint32_t icv_gprio_mask(GICv3CPUState *cs, int group) { /* Return a mask word which clears the subpriority bits from * a priority value for a virtual interrupt in the specified group. - * This depends on the VBPR value: + * This depends on the VBPR value. + * If using VBPR0 then: * a BPR of 0 means the group priority bits are [7:1]; * a BPR of 1 means they are [7:2], and so on down to * a BPR of 7 meaning no group priority bits at all. + * If using VBPR1 then: + * a BPR of 0 is impossible (the minimum value is 1) + * a BPR of 1 means the group priority bits are [7:1]; + * a BPR of 2 means they are [7:2], and so on down to + * a BPR of 7 meaning the group priority is [7]. + * * Which BPR to use depends on the group of the interrupt and * the current ICH_VMCR_EL2.VCBPR settings. + * + * This corresponds to the VGroupBits() pseudocode. */ + int bpr; + if (group == GICV3_G1NS && cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR) { group = GICV3_G0; } - return ~0U << (read_vbpr(cs, group) + 1); + bpr = read_vbpr(cs, group); + if (group == GICV3_G1NS) { + assert(bpr > 0); + bpr--; + } + + return ~0U << (bpr + 1); } static bool icv_hppi_can_preempt(GICv3CPUState *cs, uint64_t lr) @@ -674,20 +691,37 @@ static uint32_t icc_gprio_mask(GICv3CPUState *cs, int group) { /* Return a mask word which clears the subpriority bits from * a priority value for an interrupt in the specified group. - * This depends on the BPR value: + * This depends on the BPR value. For CBPR0 (S or NS): * a BPR of 0 means the group priority bits are [7:1]; * a BPR of 1 means they are [7:2], and so on down to * a BPR of 7 meaning no group priority bits at all. + * For CBPR1 NS: + * a BPR of 0 is impossible (the minimum value is 1) + * a BPR of 1 means the group priority bits are [7:1]; + * a BPR of 2 means they are [7:2], and so on down to + * a BPR of 7 meaning the group priority is [7]. + * * Which BPR to use depends on the group of the interrupt and * the current ICC_CTLR.CBPR settings. + * + * This corresponds to the GroupBits() pseudocode. */ + int bpr; + if ((group == GICV3_G1 && cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_CBPR) || (group == GICV3_G1NS && cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR)) { group = GICV3_G0; } - return ~0U << ((cs->icc_bpr[group] & 7) + 1); + bpr = cs->icc_bpr[group] & 7; + + if (group == GICV3_G1NS) { + assert(bpr > 0); + bpr--; + } + + return ~0U << (bpr + 1); } static bool icc_no_enabled_hppi(GICv3CPUState *cs) From patchwork Thu Jun 1 17:10:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 100966 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp861900obc; Thu, 1 Jun 2017 10:23:08 -0700 (PDT) X-Received: by 10.237.41.97 with SMTP id s88mr3271139qtd.8.1496337787984; Thu, 01 Jun 2017 10:23:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496337787; cv=none; d=google.com; s=arc-20160816; b=FEmRTc8CsFhLXsCkNjJ5L7vL0J4+tWlATELQUllkdmzClMM5e9t1Y2PWiTW2CAyWXw sklYdLLczjO4T23F8V13mgEXar8W4OPQLKRTSoX0GyUQ9FPT+0cyuMhsfRX9lKO1OVA7 HnT9vjK8zuBE37M/2u5/SojnhfrHjLxm03yZL7YApK4gpoum18dg7Uvsvu0eNvO8Solk MwLv+iXSQ4NNxC3n0UlEMNtxAkj6Ey7fQMHiYjIf3hNZblsIGSnsxJsXFu5SsRWZ2Iy1 cVUcAElBv+xMpysMEEJkKAlF41UXJiKasPAcrPh1XBZZIVD6at22036KABn44TuhPbmh OZ/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=3IN1Dc9ilWIp5YmcPcKsTC9gzn7OoEFuqCOmFmGPjXQ=; b=ChATMW4CaarSBPuDAA/C01KGsq7vYGSxUlFHVdqwxgFUXRqPK/wMgRR1akCB3PqL19 BAw08sZbbTlDxB642ox+7ncZx49xCcyrk3Ilj363LVJfgtR68fDKzlHVVfDRNX0gCBPk bLx0tN41TxIKGKqwybNhFiJNIz1uFryiS0YbDYLaF0aiGS86VLTPJNMElgWX0CFAnoT5 2ldNjOw4JHicGongrD5eF8hw9ROsVc5WvzHZX0bs8rPxBhospew/v8rR7blCCTZoshl+ ijTVvT1if2+rrfeoD+g9dyIe3yHu+sTh42eSar1t/lyraaIKHZaKbM7mayQ1CQsTmCkT qvkg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id y73si20109365qka.32.2017.06.01.10.23.07 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Jun 2017 10:23:07 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45850 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGToP-0003YN-8y for patch@linaro.org; Thu, 01 Jun 2017 13:23:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35193) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTcY-000171-3g for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGTcW-0006Av-Rn for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:50 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37146) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTcW-00068M-Ka for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:48 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTcO-0007Om-Az for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:40 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:14 +0100 Message-Id: <1496337035-30213-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 06/27] target/arm: clear PMUVER field of AA64DFR0 when vPMU=off X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Wei Huang The PMUv3 driver of linux kernel (in arch/arm64/kernel/perf_event.c) relies on the PMUVER field of id_aa64dfr0_el1 to decide if PMU support is present or not. This patch clears the PMUVER field under TCG mode when vPMU=off. Without it, PMUv3 will init insider guest VMs even with vPMU=off. This patch also removes a redundant line inside the if-statement. Signed-off-by: Wei Huang Message-id: 1495123889-32301-1-git-send-email-wei@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c185eb1..4e8fe1c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -750,8 +750,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) } if (!cpu->has_pmu) { - cpu->has_pmu = false; unset_feature(env, ARM_FEATURE_PMU); + cpu->id_aa64dfr0 &= ~0xf00; } if (!arm_feature(env, ARM_FEATURE_EL2)) { From patchwork Thu Jun 1 17:10:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 100952 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp858735obc; Thu, 1 Jun 2017 10:14:56 -0700 (PDT) X-Received: by 10.55.144.5 with SMTP id s5mr2976511qkd.39.1496337296266; Thu, 01 Jun 2017 10:14:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496337296; cv=none; d=google.com; s=arc-20160816; b=ERuzDTn7IPRl26qgWqSLiMGKD1RyLsbNgr7g9r9weZyrvusPpGlCkoCPbStOE2YHFX p3ulOFMftEP46rrki4MVRaAfkQ3oJsxjPdxnlJ8WSxuCAjd78B53wOGLdxGZ9rUUif5N s4HmRzsTtt7ar4shOzr6xsGZ4woXdDbcv9HWfVgj6DpZPnrI3yUBH9eW5I7U1lAHOCyS q4/8OnXfd8gydAHfSquLHlBaWtdyIVWOWkNdP6XbVaLer4pqYVIW4rabB6mgjt6hnSnG KNp3JNKjtLrF+TuFTXUsvTsW1Mwe5llZHPV2NUG39rJ4k1RR5Gd/n/KyrobE81IwbCQc LqBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=nkbJmjhXWH8XyJFuKdzgSJhRLmuWR8K4x9BV5A+R3I8=; b=sTREZ44TN7jZS6Tz+VsGjYUP1hK2FFIXOwEOk5oqC2QDGTt1nDSeCmQhqQBPZjbkji uPYxXgj7RrCz5oob2Vw92mC1lNoDiEM60wDzkvU9hNlD92oBV8U7HI/KGtDIyEq0sa8f EJrnsp62112DcrbeL6WPD0ZMkq2Nev11GclzJE5EFQRnfbeavAKTbNbUC5dgq2kVeQCC bTufvrr2AWaNkfOwc5+QdpPwn11cTbQPZ+YPkqounHpkQpmkL8QCwyfdsPkyanbSRCOR P1GMxi7sWCnQlApy0TU7zSYbIMqSMVXOcH/V7CILt9NW3KgM2BPFwgLrPQLyiHvsZTpQ sLzA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id e125si20004588qkc.177.2017.06.01.10.14.55 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Jun 2017 10:14:56 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45813 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTgT-0004dQ-EZ for patch@linaro.org; Thu, 01 Jun 2017 13:14:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35142) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTcW-00015j-Px for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGTcV-0006AI-Uq for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:48 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37146) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTcV-00068M-Lh for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:47 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTcO-0007P9-UQ for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:40 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:15 +0100 Message-Id: <1496337035-30213-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 07/27] arm: Use the mmu_idx we're passed in arm_cpu_do_unaligned_access() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When identifying the DFSR format for an alignment fault, use the mmu index that we are passed, rather than calling cpu_mmu_index() to get the mmu index for the current CPU state. This doesn't actually make any difference since the only cases where the current MMU index differs from the index used for the load are the "unprivileged load/store" instructions, and in that case the mmu index may differ but the translation regime is the same (apart from the "use from Hyp mode" case which is UNPREDICTABLE). However it's the more logical thing to do. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-id: 1493122030-32191-2-git-send-email-peter.maydell@linaro.org --- target/arm/op_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 156b825..de24815 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -208,7 +208,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, /* the DFSR for an alignment fault depends on whether we're using * the LPAE long descriptor format, or the short descriptor format */ - if (arm_s1_regime_using_lpae_format(env, cpu_mmu_index(env, false))) { + if (arm_s1_regime_using_lpae_format(env, mmu_idx)) { env->exception.fsr = (1 << 9) | 0x21; } else { env->exception.fsr = 0x1; From patchwork Thu Jun 1 17:10:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 100969 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp863096obc; Thu, 1 Jun 2017 10:25:52 -0700 (PDT) X-Received: by 10.237.61.39 with SMTP id g36mr3224459qtf.60.1496337952677; Thu, 01 Jun 2017 10:25:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496337952; cv=none; d=google.com; s=arc-20160816; b=UlQKuDuSIHylMB01SzUJyQamnSwTyUZGmUyVweCn+1V85sMxmOHkwlyyOcKMOf1fnW 7fN5loAiElvwWfvHrkPpIGhLV90K4pt6PuAh0ngSOaGf4aXabmya5YoqNn92DqbsHhMU ttAtw8mWZI1qND1xD0QsHa+Ze4yCyRfdQoVCGdSR9b/1o94RFQCUrwQ/yyQnNe0DQfHZ RZjjClpibW6MH2WK2VZ2Q1dAVeYrapi9geOaPKuPha/kQE/86E7hEwGlrYPijC2wWFXn rU69mWX8GTlCjLP77frHuahszuS23UVWutH4wKuCV59UbL1pgPjIDbBSB6vCYmXxIZw0 ntvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=w7+Z4hG3djWuL2pDSob8PLbBBImQiW9udVkB/bxUQ+8=; b=CtUyrDagkGTgI7VN/7XB4LEYD9IIpWhaUd2/pJ046lsGL2RLNOm6QF+dxvlF29Ehzd Yt1FJnjb0F4DQ2nYfUdODMe1DcKwFT/XNF7wM9BT3P1PvWa+JcGBuv8rnOq/74Onf3vr PgfcnIu2A0oHOIv2ltrjL664hfnXdD/zjQYIOOtkbN1lrYP/+6Enqto3N1Uaj8g0J0Qt OHV9l7PSRs8hnkLIJeboiqwq9UNGVON2VWWyDzBbHwbx7WWa9UQBVNaghs6KcUVxv8Iv LNT2OqMjrOjJ1pE3nqObDHwX9f50c2gwF83UGxBqG+TEagOqhQK+Mq1EytplSscnv49i f7BQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id i2si2071654qtc.253.2017.06.01.10.25.51 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Jun 2017 10:25:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45866 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTr3-00065B-TG for patch@linaro.org; Thu, 01 Jun 2017 13:25:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35240) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTcZ-00017E-5M for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGTcW-0006AU-0S for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:51 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37144) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTcV-00064g-EC for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:47 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTcP-0007PN-Hp for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:41 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:16 +0100 Message-Id: <1496337035-30213-9-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 08/27] arm: Add support for M profile CPUs having different MMU index semantics X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The M profile CPU's MPU has an awkward corner case which we would like to implement with a different MMU index. We can avoid having to bump the number of MMU modes ARM uses, because some of our existing MMU indexes are only used by non-M-profile CPUs, so we can borrow one. To avoid that getting too confusing, clean up the code to try to keep the two meanings of the index separate. Instead of ARMMMUIdx enum values being identical to core QEMU MMU index values, they are now the core index values with some high bits set. Any particular CPU always uses the same high bits (so eventually A profile cores and M profile cores will use different bits). New functions arm_to_core_mmu_idx() and core_to_arm_mmu_idx() convert between the two. In general core index values are stored in 'int' types, and ARM values are stored in ARMMMUIdx types. Signed-off-by: Peter Maydell Message-id: 1493122030-32191-3-git-send-email-peter.maydell@linaro.org --- target/arm/cpu.h | 71 ++++++++++++++++----- target/arm/translate.h | 2 +- target/arm/helper.c | 151 ++++++++++++++++++++++++--------------------- target/arm/op_helper.c | 3 +- target/arm/translate-a64.c | 18 ++++-- target/arm/translate.c | 10 +-- 6 files changed, 156 insertions(+), 99 deletions(-) -- 2.7.4 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 048faed..4b1e982 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2039,6 +2039,16 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, * for the accesses done as part of a stage 1 page table walk, rather than * having to walk the stage 2 page table over and over.) * + * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code + * are not quite the same -- different CPU types (most notably M profile + * vs A/R profile) would like to use MMU indexes with different semantics, + * but since we don't ever need to use all of those in a single CPU we + * can avoid setting NB_MMU_MODES to more than 8. The lower bits of + * ARMMMUIdx are the core TLB mmu index, and the higher bits are always + * the same for any particular CPU. + * Variables of type ARMMUIdx are always full values, and the core + * index values are in variables of type 'int'. + * * Our enumeration includes at the end some entries which are not "true" * mmu_idx values in that they don't have corresponding TLBs and are only * valid for doing slow path page table walks. @@ -2047,28 +2057,61 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, * of the AT/ATS operations. * The values used are carefully arranged to make mmu_idx => EL lookup easy. */ +#define ARM_MMU_IDX_A 0x10 /* A profile (and M profile, for the moment) */ +#define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ + +#define ARM_MMU_IDX_TYPE_MASK (~0x7) +#define ARM_MMU_IDX_COREIDX_MASK 0x7 + typedef enum ARMMMUIdx { - ARMMMUIdx_S12NSE0 = 0, - ARMMMUIdx_S12NSE1 = 1, - ARMMMUIdx_S1E2 = 2, - ARMMMUIdx_S1E3 = 3, - ARMMMUIdx_S1SE0 = 4, - ARMMMUIdx_S1SE1 = 5, - ARMMMUIdx_S2NS = 6, + ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A, + ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A, + ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, + ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, + ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, + ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, + ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, /* Indexes below here don't have TLBs and are used only for AT system * instructions or for the first stage of an S12 page table walk. */ - ARMMMUIdx_S1NSE0 = 7, - ARMMMUIdx_S1NSE1 = 8, + ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB, } ARMMMUIdx; +/* Bit macros for the core-mmu-index values for each index, + * for use when calling tlb_flush_by_mmuidx() and friends. + */ +typedef enum ARMMMUIdxBit { + ARMMMUIdxBit_S12NSE0 = 1 << 0, + ARMMMUIdxBit_S12NSE1 = 1 << 1, + ARMMMUIdxBit_S1E2 = 1 << 2, + ARMMMUIdxBit_S1E3 = 1 << 3, + ARMMMUIdxBit_S1SE0 = 1 << 4, + ARMMMUIdxBit_S1SE1 = 1 << 5, + ARMMMUIdxBit_S2NS = 1 << 6, +} ARMMMUIdxBit; + #define MMU_USER_IDX 0 +static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) +{ + return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; +} + +static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) +{ + return mmu_idx | ARM_MMU_IDX_A; +} + /* Return the exception level we're running at if this is our mmu_idx */ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) { - assert(mmu_idx < ARMMMUIdx_S2NS); - return mmu_idx & 3; + switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { + case ARM_MMU_IDX_A: + return mmu_idx & 3; + default: + g_assert_not_reached(); + } } /* Determine the current mmu_idx to use for normal loads/stores */ @@ -2077,7 +2120,7 @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) int el = arm_current_el(env); if (el < 2 && arm_is_secure_below_el3(env)) { - return ARMMMUIdx_S1SE0 + el; + return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); } return el; } @@ -2473,7 +2516,7 @@ static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) { - ARMMMUIdx mmu_idx = cpu_mmu_index(env, false); + ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); if (is_a64(env)) { *pc = env->pc; *flags = ARM_TBFLAG_AARCH64_STATE_MASK; @@ -2498,7 +2541,7 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, << ARM_TBFLAG_XSCALE_CPAR_SHIFT); } - *flags |= (mmu_idx << ARM_TBFLAG_MMUIDX_SHIFT); + *flags |= (arm_to_core_mmu_idx(mmu_idx) << ARM_TBFLAG_MMUIDX_SHIFT); /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine * states defined in the ARM ARM for software singlestep: diff --git a/target/arm/translate.h b/target/arm/translate.h index 629dab9..6b2cc34 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -88,7 +88,7 @@ static inline int arm_dc_feature(DisasContext *dc, int feature) static inline int get_mem_index(DisasContext *s) { - return s->mmu_idx; + return arm_to_core_mmu_idx(s->mmu_idx); } /* Function used to determine the target exception EL when otherwise not known diff --git a/target/arm/helper.c b/target/arm/helper.c index 8a3e448..520adcc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -571,9 +571,9 @@ static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, CPUState *cs = ENV_GET_CPU(env); tlb_flush_by_mmuidx(cs, - (1 << ARMMMUIdx_S12NSE1) | - (1 << ARMMMUIdx_S12NSE0) | - (1 << ARMMMUIdx_S2NS)); + ARMMMUIdxBit_S12NSE1 | + ARMMMUIdxBit_S12NSE0 | + ARMMMUIdxBit_S2NS); } static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -582,9 +582,9 @@ static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, CPUState *cs = ENV_GET_CPU(env); tlb_flush_by_mmuidx_all_cpus_synced(cs, - (1 << ARMMMUIdx_S12NSE1) | - (1 << ARMMMUIdx_S12NSE0) | - (1 << ARMMMUIdx_S2NS)); + ARMMMUIdxBit_S12NSE1 | + ARMMMUIdxBit_S12NSE0 | + ARMMMUIdxBit_S2NS); } static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -605,7 +605,7 @@ static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri, pageaddr = sextract64(value << 12, 0, 40); - tlb_flush_page_by_mmuidx(cs, pageaddr, (1 << ARMMMUIdx_S2NS)); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS); } static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -621,7 +621,7 @@ static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri, pageaddr = sextract64(value << 12, 0, 40); tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - (1 << ARMMMUIdx_S2NS)); + ARMMMUIdxBit_S2NS); } static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -629,7 +629,7 @@ static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, { CPUState *cs = ENV_GET_CPU(env); - tlb_flush_by_mmuidx(cs, (1 << ARMMMUIdx_S1E2)); + tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); } static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -637,7 +637,7 @@ static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, { CPUState *cs = ENV_GET_CPU(env); - tlb_flush_by_mmuidx_all_cpus_synced(cs, (1 << ARMMMUIdx_S1E2)); + tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); } static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -646,7 +646,7 @@ static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, CPUState *cs = ENV_GET_CPU(env); uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); - tlb_flush_page_by_mmuidx(cs, pageaddr, (1 << ARMMMUIdx_S1E2)); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); } static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -656,7 +656,7 @@ static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - (1 << ARMMMUIdx_S1E2)); + ARMMMUIdxBit_S1E2); } static const ARMCPRegInfo cp_reginfo[] = { @@ -2596,9 +2596,9 @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, /* Accesses to VTTBR may change the VMID so we must flush the TLB. */ if (raw_read(env, ri) != value) { tlb_flush_by_mmuidx(cs, - (1 << ARMMMUIdx_S12NSE1) | - (1 << ARMMMUIdx_S12NSE0) | - (1 << ARMMMUIdx_S2NS)); + ARMMMUIdxBit_S12NSE1 | + ARMMMUIdxBit_S12NSE0 | + ARMMMUIdxBit_S2NS); raw_write(env, ri, value); } } @@ -2957,12 +2957,12 @@ static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri, if (arm_is_secure_below_el3(env)) { tlb_flush_by_mmuidx(cs, - (1 << ARMMMUIdx_S1SE1) | - (1 << ARMMMUIdx_S1SE0)); + ARMMMUIdxBit_S1SE1 | + ARMMMUIdxBit_S1SE0); } else { tlb_flush_by_mmuidx(cs, - (1 << ARMMMUIdx_S12NSE1) | - (1 << ARMMMUIdx_S12NSE0)); + ARMMMUIdxBit_S12NSE1 | + ARMMMUIdxBit_S12NSE0); } } @@ -2974,12 +2974,12 @@ static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, if (sec) { tlb_flush_by_mmuidx_all_cpus_synced(cs, - (1 << ARMMMUIdx_S1SE1) | - (1 << ARMMMUIdx_S1SE0)); + ARMMMUIdxBit_S1SE1 | + ARMMMUIdxBit_S1SE0); } else { tlb_flush_by_mmuidx_all_cpus_synced(cs, - (1 << ARMMMUIdx_S12NSE1) | - (1 << ARMMMUIdx_S12NSE0)); + ARMMMUIdxBit_S12NSE1 | + ARMMMUIdxBit_S12NSE0); } } @@ -2995,18 +2995,18 @@ static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, if (arm_is_secure_below_el3(env)) { tlb_flush_by_mmuidx(cs, - (1 << ARMMMUIdx_S1SE1) | - (1 << ARMMMUIdx_S1SE0)); + ARMMMUIdxBit_S1SE1 | + ARMMMUIdxBit_S1SE0); } else { if (arm_feature(env, ARM_FEATURE_EL2)) { tlb_flush_by_mmuidx(cs, - (1 << ARMMMUIdx_S12NSE1) | - (1 << ARMMMUIdx_S12NSE0) | - (1 << ARMMMUIdx_S2NS)); + ARMMMUIdxBit_S12NSE1 | + ARMMMUIdxBit_S12NSE0 | + ARMMMUIdxBit_S2NS); } else { tlb_flush_by_mmuidx(cs, - (1 << ARMMMUIdx_S12NSE1) | - (1 << ARMMMUIdx_S12NSE0)); + ARMMMUIdxBit_S12NSE1 | + ARMMMUIdxBit_S12NSE0); } } } @@ -3017,7 +3017,7 @@ static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, ARMCPU *cpu = arm_env_get_cpu(env); CPUState *cs = CPU(cpu); - tlb_flush_by_mmuidx(cs, (1 << ARMMMUIdx_S1E2)); + tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); } static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3026,7 +3026,7 @@ static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, ARMCPU *cpu = arm_env_get_cpu(env); CPUState *cs = CPU(cpu); - tlb_flush_by_mmuidx(cs, (1 << ARMMMUIdx_S1E3)); + tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E3); } static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3042,17 +3042,17 @@ static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, if (sec) { tlb_flush_by_mmuidx_all_cpus_synced(cs, - (1 << ARMMMUIdx_S1SE1) | - (1 << ARMMMUIdx_S1SE0)); + ARMMMUIdxBit_S1SE1 | + ARMMMUIdxBit_S1SE0); } else if (has_el2) { tlb_flush_by_mmuidx_all_cpus_synced(cs, - (1 << ARMMMUIdx_S12NSE1) | - (1 << ARMMMUIdx_S12NSE0) | - (1 << ARMMMUIdx_S2NS)); + ARMMMUIdxBit_S12NSE1 | + ARMMMUIdxBit_S12NSE0 | + ARMMMUIdxBit_S2NS); } else { tlb_flush_by_mmuidx_all_cpus_synced(cs, - (1 << ARMMMUIdx_S12NSE1) | - (1 << ARMMMUIdx_S12NSE0)); + ARMMMUIdxBit_S12NSE1 | + ARMMMUIdxBit_S12NSE0); } } @@ -3061,7 +3061,7 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, { CPUState *cs = ENV_GET_CPU(env); - tlb_flush_by_mmuidx_all_cpus_synced(cs, (1 << ARMMMUIdx_S1E2)); + tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); } static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3069,7 +3069,7 @@ static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri, { CPUState *cs = ENV_GET_CPU(env); - tlb_flush_by_mmuidx_all_cpus_synced(cs, (1 << ARMMMUIdx_S1E3)); + tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E3); } static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3086,12 +3086,12 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, if (arm_is_secure_below_el3(env)) { tlb_flush_page_by_mmuidx(cs, pageaddr, - (1 << ARMMMUIdx_S1SE1) | - (1 << ARMMMUIdx_S1SE0)); + ARMMMUIdxBit_S1SE1 | + ARMMMUIdxBit_S1SE0); } else { tlb_flush_page_by_mmuidx(cs, pageaddr, - (1 << ARMMMUIdx_S12NSE1) | - (1 << ARMMMUIdx_S12NSE0)); + ARMMMUIdxBit_S12NSE1 | + ARMMMUIdxBit_S12NSE0); } } @@ -3106,7 +3106,7 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, CPUState *cs = CPU(cpu); uint64_t pageaddr = sextract64(value << 12, 0, 56); - tlb_flush_page_by_mmuidx(cs, pageaddr, (1 << ARMMMUIdx_S1E2)); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); } static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3120,7 +3120,7 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, CPUState *cs = CPU(cpu); uint64_t pageaddr = sextract64(value << 12, 0, 56); - tlb_flush_page_by_mmuidx(cs, pageaddr, (1 << ARMMMUIdx_S1E3)); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E3); } static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3133,12 +3133,12 @@ static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, if (sec) { tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - (1 << ARMMMUIdx_S1SE1) | - (1 << ARMMMUIdx_S1SE0)); + ARMMMUIdxBit_S1SE1 | + ARMMMUIdxBit_S1SE0); } else { tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - (1 << ARMMMUIdx_S12NSE1) | - (1 << ARMMMUIdx_S12NSE0)); + ARMMMUIdxBit_S12NSE1 | + ARMMMUIdxBit_S12NSE0); } } @@ -3149,7 +3149,7 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t pageaddr = sextract64(value << 12, 0, 56); tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - (1 << ARMMMUIdx_S1E2)); + ARMMMUIdxBit_S1E2); } static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3159,7 +3159,7 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t pageaddr = sextract64(value << 12, 0, 56); tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - (1 << ARMMMUIdx_S1E3)); + ARMMMUIdxBit_S1E3); } static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3181,7 +3181,7 @@ static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri, pageaddr = sextract64(value << 12, 0, 48); - tlb_flush_page_by_mmuidx(cs, pageaddr, (1 << ARMMMUIdx_S2NS)); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS); } static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3197,7 +3197,7 @@ static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri, pageaddr = sextract64(value << 12, 0, 48); tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - (1 << ARMMMUIdx_S2NS)); + ARMMMUIdxBit_S2NS); } static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri, @@ -7049,6 +7049,17 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; } +/* Convert a possible stage1+2 MMU index into the appropriate + * stage 1 MMU index + */ +static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) +{ + if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { + mmu_idx += (ARMMMUIdx_S1NSE0 - ARMMMUIdx_S12NSE0); + } + return mmu_idx; +} + /* Returns TBI0 value for current regime el */ uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) { @@ -7056,11 +7067,9 @@ uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) uint32_t el; /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert - * a stage 1+2 mmu index into the appropriate stage 1 mmu index. - */ - if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { - mmu_idx += ARMMMUIdx_S1NSE0; - } + * a stage 1+2 mmu index into the appropriate stage 1 mmu index. + */ + mmu_idx = stage_1_mmu_idx(mmu_idx); tcr = regime_tcr(env, mmu_idx); el = regime_el(env, mmu_idx); @@ -7079,11 +7088,9 @@ uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) uint32_t el; /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert - * a stage 1+2 mmu index into the appropriate stage 1 mmu index. - */ - if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { - mmu_idx += ARMMMUIdx_S1NSE0; - } + * a stage 1+2 mmu index into the appropriate stage 1 mmu index. + */ + mmu_idx = stage_1_mmu_idx(mmu_idx); tcr = regime_tcr(env, mmu_idx); el = regime_el(env, mmu_idx); @@ -7129,9 +7136,7 @@ static inline bool regime_using_lpae_format(CPUARMState *env, * on whether the long or short descriptor format is in use. */ bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) { - if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { - mmu_idx += ARMMMUIdx_S1NSE0; - } + mmu_idx = stage_1_mmu_idx(mmu_idx); return regime_using_lpae_format(env, mmu_idx); } @@ -8385,7 +8390,7 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, int ret; ret = get_phys_addr(env, address, access_type, - mmu_idx + ARMMMUIdx_S1NSE0, &ipa, attrs, + stage_1_mmu_idx(mmu_idx), &ipa, attrs, prot, page_size, fsr, fi); /* If S1 fails or S2 is disabled, return early. */ @@ -8406,7 +8411,7 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, /* * For non-EL2 CPUs a stage1+stage2 translation is just stage 1. */ - mmu_idx += ARMMMUIdx_S1NSE0; + mmu_idx = stage_1_mmu_idx(mmu_idx); } } @@ -8482,7 +8487,8 @@ bool arm_tlb_fill(CPUState *cs, vaddr address, int ret; MemTxAttrs attrs = {}; - ret = get_phys_addr(env, address, access_type, mmu_idx, &phys_addr, + ret = get_phys_addr(env, address, access_type, + core_to_arm_mmu_idx(env, mmu_idx), &phys_addr, &attrs, &prot, &page_size, fsr, fi); if (!ret) { /* Map a single [sub]page. */ @@ -8507,10 +8513,11 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, bool ret; uint32_t fsr; ARMMMUFaultInfo fi = {}; + ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); *attrs = (MemTxAttrs) {}; - ret = get_phys_addr(env, addr, 0, cpu_mmu_index(env, false), &phys_addr, + ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr, attrs, &prot, &page_size, &fsr, &fi); if (ret) { diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index de24815..2a85666 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -194,6 +194,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int target_el; bool same_el; uint32_t syn; + ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx); if (retaddr) { /* now we have a real cpu fault */ @@ -208,7 +209,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, /* the DFSR for an alignment fault depends on whether we're using * the LPAE long descriptor format, or the short descriptor format */ - if (arm_s1_regime_using_lpae_format(env, mmu_idx)) { + if (arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) { env->exception.fsr = (1 << 9) | 0x21; } else { env->exception.fsr = 0x1; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 24de30d..a82ab49 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -101,21 +101,27 @@ void a64_translate_init(void) offsetof(CPUARMState, exclusive_high), "exclusive_high"); } -static inline ARMMMUIdx get_a64_user_mem_index(DisasContext *s) +static inline int get_a64_user_mem_index(DisasContext *s) { - /* Return the mmu_idx to use for A64 "unprivileged load/store" insns: + /* Return the core mmu_idx to use for A64 "unprivileged load/store" insns: * if EL1, access as if EL0; otherwise access at current EL */ + ARMMMUIdx useridx; + switch (s->mmu_idx) { case ARMMMUIdx_S12NSE1: - return ARMMMUIdx_S12NSE0; + useridx = ARMMMUIdx_S12NSE0; + break; case ARMMMUIdx_S1SE1: - return ARMMMUIdx_S1SE0; + useridx = ARMMMUIdx_S1SE0; + break; case ARMMMUIdx_S2NS: g_assert_not_reached(); default: - return s->mmu_idx; + useridx = s->mmu_idx; + break; } + return arm_to_core_mmu_idx(useridx); } void aarch64_cpu_dump_state(CPUState *cs, FILE *f, @@ -11212,7 +11218,7 @@ void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb) dc->be_data = ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE; dc->condexec_mask = 0; dc->condexec_cond = 0; - dc->mmu_idx = ARM_TBFLAG_MMUIDX(tb->flags); + dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(tb->flags)); dc->tbi0 = ARM_TBFLAG_TBI0(tb->flags); dc->tbi1 = ARM_TBFLAG_TBI1(tb->flags); dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); diff --git a/target/arm/translate.c b/target/arm/translate.c index 0b5a0bc..8d509a2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -145,9 +145,9 @@ static void disas_set_da_iss(DisasContext *s, TCGMemOp memop, ISSInfo issinfo) disas_set_insn_syndrome(s, syn); } -static inline ARMMMUIdx get_a32_user_mem_index(DisasContext *s) +static inline int get_a32_user_mem_index(DisasContext *s) { - /* Return the mmu_idx to use for A32/T32 "unprivileged load/store" + /* Return the core mmu_idx to use for A32/T32 "unprivileged load/store" * insns: * if PL2, UNPREDICTABLE (we choose to implement as if PL0) * otherwise, access as if at PL0. @@ -156,11 +156,11 @@ static inline ARMMMUIdx get_a32_user_mem_index(DisasContext *s) case ARMMMUIdx_S1E2: /* this one is UNPREDICTABLE */ case ARMMMUIdx_S12NSE0: case ARMMMUIdx_S12NSE1: - return ARMMMUIdx_S12NSE0; + return arm_to_core_mmu_idx(ARMMMUIdx_S12NSE0); case ARMMMUIdx_S1E3: case ARMMMUIdx_S1SE0: case ARMMMUIdx_S1SE1: - return ARMMMUIdx_S1SE0; + return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0); case ARMMMUIdx_S2NS: default: g_assert_not_reached(); @@ -11816,7 +11816,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb) dc->be_data = ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE; dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1; dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4; - dc->mmu_idx = ARM_TBFLAG_MMUIDX(tb->flags); + dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(tb->flags)); dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user = (dc->current_el == 0); From patchwork Thu Jun 1 17:10:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 100955 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp859226obc; Thu, 1 Jun 2017 10:16:16 -0700 (PDT) X-Received: by 10.237.53.205 with SMTP id d13mr2780248qte.46.1496337376633; Thu, 01 Jun 2017 10:16:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496337376; cv=none; d=google.com; s=arc-20160816; b=DsH3HgCtTwg94lxle4/Lnh3mEVdp3+/PHhTvlNlfEyIPS0E2HSyKmT1B5FdNUT6Vc3 A7ziX/4HULSzqQWhZLGdB/l/Vimtur4+kA5tPdy38d8e9l7NMUCm0DEjcHsf79n8WvD6 o5vuyZ/ei8FxVgLhGEN6lj48j5lm2jAppkeGjwrzZROGsx7kvKT5Z6wuhVsbwwUDRpOR obweDe2F7Ot7c+/m40Lw30119t36zWDdIKNRFPa43AdaUKAR49GTDUetqHSGb1Lmrg4T WiJwzqY4m0auh6S2znYRC7UwscvnM7vaa4+uUEQKFHdaoItOFmBuIY3S8RLVoUO5kS7R DG1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=/a7FRICu6Pm7wcC+R+ZzbFcQzp/hMYtV5NZ8IeexTKw=; b=CQt6xP08mK0dv4pxgd4r620YT0k4w9lfckEhuGlZLmg/PQCzTyZuI7hlsY7S3D+sEY 1cG/1aqPjCMZAa1X7UnueE//cKZqQaRcWZIbZBn6lT3oWEDuM+AIPxF3qivxJ0WGPWJO ob0kOneVfey5H2vzVYP5HbFLJLMzvypPB9phwlSF6lc/CrLSqXLbJ+lcZEqPemttyfv1 Q30pgnyylRarCXqri2cp51yuK9EC542UQz9ETkWuMUKiYl1Tz25t1mSVejo63Uh/4qzt pZ4vDfoiWbbtNWzIJ6bWOraozpXxhpKNV/bMkqGBJwx8xcC/vxKCNT7MH3/Alnz97XCb NMCA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id f95si19750410qtb.88.2017.06.01.10.16.16 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Jun 2017 10:16:16 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45823 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGThl-0005qc-Tl for patch@linaro.org; Thu, 01 Jun 2017 13:16:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35116) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTcV-00014m-V9 for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGTcU-00068v-P4 for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:47 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37144) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTcU-00064g-Gg for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:46 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTcQ-0007Pb-7d for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:42 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:17 +0100 Message-Id: <1496337035-30213-10-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 09/27] arm: Use different ARMMMUIdx values for M profile X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Make M profile use completely separate ARMMMUIdx values from those that A profile CPUs use. This is a prelude to adding support for the MPU and for v8M, which together will require 6 MMU indexes which don't map cleanly onto the A profile uses: non secure User non secure Privileged non secure Privileged, execution priority < 0 secure User secure Privileged secure Privileged, execution priority < 0 Signed-off-by: Peter Maydell Message-id: 1493122030-32191-4-git-send-email-peter.maydell@linaro.org --- target/arm/cpu.h | 21 +++++++++++++++++++-- target/arm/helper.c | 5 +++++ target/arm/translate.c | 3 +++ 3 files changed, 27 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4b1e982..cadec09 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2057,8 +2057,9 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, * of the AT/ATS operations. * The values used are carefully arranged to make mmu_idx => EL lookup easy. */ -#define ARM_MMU_IDX_A 0x10 /* A profile (and M profile, for the moment) */ +#define ARM_MMU_IDX_A 0x10 /* A profile */ #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ +#define ARM_MMU_IDX_M 0x40 /* M profile */ #define ARM_MMU_IDX_TYPE_MASK (~0x7) #define ARM_MMU_IDX_COREIDX_MASK 0x7 @@ -2071,6 +2072,8 @@ typedef enum ARMMMUIdx { ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, + ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, + ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, /* Indexes below here don't have TLBs and are used only for AT system * instructions or for the first stage of an S12 page table walk. */ @@ -2089,6 +2092,8 @@ typedef enum ARMMMUIdxBit { ARMMMUIdxBit_S1SE0 = 1 << 4, ARMMMUIdxBit_S1SE1 = 1 << 5, ARMMMUIdxBit_S2NS = 1 << 6, + ARMMMUIdxBit_MUser = 1 << 0, + ARMMMUIdxBit_MPriv = 1 << 1, } ARMMMUIdxBit; #define MMU_USER_IDX 0 @@ -2100,7 +2105,11 @@ static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) { - return mmu_idx | ARM_MMU_IDX_A; + if (arm_feature(env, ARM_FEATURE_M)) { + return mmu_idx | ARM_MMU_IDX_M; + } else { + return mmu_idx | ARM_MMU_IDX_A; + } } /* Return the exception level we're running at if this is our mmu_idx */ @@ -2109,6 +2118,8 @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { case ARM_MMU_IDX_A: return mmu_idx & 3; + case ARM_MMU_IDX_M: + return mmu_idx & 1; default: g_assert_not_reached(); } @@ -2119,6 +2130,12 @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) { int el = arm_current_el(env); + if (arm_feature(env, ARM_FEATURE_M)) { + ARMMMUIdx mmu_idx = el == 0 ? ARMMMUIdx_MUser : ARMMMUIdx_MPriv; + + return arm_to_core_mmu_idx(mmu_idx); + } + if (el < 2 && arm_is_secure_below_el3(env)) { return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); } diff --git a/target/arm/helper.c b/target/arm/helper.c index 520adcc..791332c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6992,6 +6992,8 @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) case ARMMMUIdx_S1SE1: case ARMMMUIdx_S1NSE0: case ARMMMUIdx_S1NSE1: + case ARMMMUIdx_MPriv: + case ARMMMUIdx_MUser: return 1; default: g_assert_not_reached(); @@ -7008,6 +7010,8 @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) case ARMMMUIdx_S1NSE1: case ARMMMUIdx_S1E2: case ARMMMUIdx_S2NS: + case ARMMMUIdx_MPriv: + case ARMMMUIdx_MUser: return false; case ARMMMUIdx_S1E3: case ARMMMUIdx_S1SE0: @@ -7146,6 +7150,7 @@ static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) switch (mmu_idx) { case ARMMMUIdx_S1SE0: case ARMMMUIdx_S1NSE0: + case ARMMMUIdx_MUser: return true; default: return false; diff --git a/target/arm/translate.c b/target/arm/translate.c index 8d509a2..ac905dd 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -161,6 +161,9 @@ static inline int get_a32_user_mem_index(DisasContext *s) case ARMMMUIdx_S1SE0: case ARMMMUIdx_S1SE1: return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0); + case ARMMMUIdx_MUser: + case ARMMMUIdx_MPriv: + return arm_to_core_mmu_idx(ARMMMUIdx_MUser); case ARMMMUIdx_S2NS: default: g_assert_not_reached(); From patchwork Thu Jun 1 17:10:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 100956 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp859257obc; Thu, 1 Jun 2017 10:16:21 -0700 (PDT) X-Received: by 10.55.68.81 with SMTP id r78mr3173994qka.102.1496337381170; Thu, 01 Jun 2017 10:16:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496337381; cv=none; d=google.com; s=arc-20160816; b=gbooPvipxsBvPfLd+9UciYPrlTcW8zdEfwp8v3fOPu09Iq7VJt+Jqs9COI5e0q1X/5 DiZkKO2NDNdvSoQIg4PlVUg3iXrpqpRfO+Tou2gX7MFAa1Mp4ju37++Ilwou0Q1sPGe5 Uo/RQQLEX0EMGB75pfnfTzNpOETq3h4P3mGJB9dAsmCmvBc8DJYP+0njbxRORH0+XOrd C6TV7oxrw5/D1om/G20HiQq9+MTh2XJ4lN5CVvQZL/RIphXfmpTRWbHdBl/4+qjmdWfG vU31A5njbojlkzWc83rgVsYqOi3bhwoC1fu8QxAyWTKV8y2QgNqAeaus22hftCbyGUBl U6AQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=oHFs9RfriLotcTTyn7OGTLs1DKIjU6LW6+KC14thr5M=; b=uWkZnjUhB41bTRlwhx1gCegUNCOKF7hj2BhkPSma/f1jsY03B7MtZMlEJTeRMOGFE2 95BMLXKJwkpuh5W5/NzkgwyDhFmU6trjQIdQ+ze7Cymam159NIxau/d/CFa+O66Gzt85 7smpzXvwneAFZBgjVNCdt/RAri45IEzqpTzhPt16hGOHC2iEibwAS0yOVt0xuG6pdfQz zta1neIFNafFUccvxpHpgt5fLfWmfFLMfSLjFpH4ySaTsrFDH1VLYsjC/pEccPLvTc9h Ze+BypzxYS+hC10vba4o746G4/z4mi8d7us/QHO3TEEr2n6xo2XKeV2dtAnQ4NyDyCd8 i71Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id r2si20547546qtc.37.2017.06.01.10.16.20 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Jun 2017 10:16:21 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45824 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGThq-0005uC-Fy for patch@linaro.org; Thu, 01 Jun 2017 13:16:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35107) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTcV-00014Y-Ln for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGTcU-00068X-An for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:47 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37145) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTcU-00067A-2G for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:46 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTcQ-0007Pp-Qw for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:42 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:18 +0100 Message-Id: <1496337035-30213-11-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 10/27] arm: Clean up handling of no-MPU PMSA CPUs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" ARM CPUs come in two flavours: * proper MMU ("VMSA") * only an MPU ("PMSA") For PMSA, the MPU may be implemented, or not (in which case there is default "always acts the same" behaviour, but it isn't guest programmable). QEMU is a bit confused about how we indicate this: we have an ARM_FEATURE_MPU, but it's not clear whether this indicates "PMSA, not VMSA" or "PMSA and MPU present" , and sometimes we use it for one purpose and sometimes the other. Currently trying to implement a PMSA-without-MPU core won't work correctly because we turn off the ARM_FEATURE_MPU bit and then a lot of things which should still exist get turned off too. As the first step in cleaning this up, rename the feature bit to ARM_FEATURE_PMSA, which indicates a PMSA CPU (with or without MPU). Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-id: 1493122030-32191-5-git-send-email-peter.maydell@linaro.org --- target/arm/cpu.h | 2 +- target/arm/cpu.c | 12 ++++++------ target/arm/helper.c | 12 ++++++------ target/arm/machine.c | 2 +- 4 files changed, 14 insertions(+), 14 deletions(-) -- 2.7.4 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cadec09..cb1d696 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1181,7 +1181,7 @@ enum arm_features { ARM_FEATURE_V6K, ARM_FEATURE_V7, ARM_FEATURE_THUMB2, - ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */ + ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ ARM_FEATURE_VFP3, ARM_FEATURE_VFP_FP16, ARM_FEATURE_NEON, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4e8fe1c..f844af5 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -593,7 +593,7 @@ static void arm_cpu_post_init(Object *obj) &error_abort); } - if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) { + if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, &error_abort); if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { @@ -689,7 +689,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) if (arm_feature(env, ARM_FEATURE_V7) && !arm_feature(env, ARM_FEATURE_M) && - !arm_feature(env, ARM_FEATURE_MPU)) { + !arm_feature(env, ARM_FEATURE_PMSA)) { /* v7VMSA drops support for the old ARMv5 tiny pages, so we * can use 4K pages. */ @@ -764,10 +764,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) } if (!cpu->has_mpu) { - unset_feature(env, ARM_FEATURE_MPU); + unset_feature(env, ARM_FEATURE_PMSA); } - if (arm_feature(env, ARM_FEATURE_MPU) && + if (arm_feature(env, ARM_FEATURE_PMSA) && arm_feature(env, ARM_FEATURE_V7)) { uint32_t nr = cpu->pmsav7_dregion; @@ -867,7 +867,7 @@ static void arm946_initfn(Object *obj) cpu->dtb_compatible = "arm,arm946"; set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_MPU); + set_feature(&cpu->env, ARM_FEATURE_PMSA); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); cpu->midr = 0x41059461; cpu->ctr = 0x0f004006; @@ -1079,7 +1079,7 @@ static void cortex_r5_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); set_feature(&cpu->env, ARM_FEATURE_V7MP); - set_feature(&cpu->env, ARM_FEATURE_MPU); + set_feature(&cpu->env, ARM_FEATURE_PMSA); cpu->midr = 0x411fc153; /* r1p3 */ cpu->id_pfr0 = 0x0131; cpu->id_pfr1 = 0x001; diff --git a/target/arm/helper.c b/target/arm/helper.c index 791332c..404bfdb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -485,7 +485,7 @@ static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, { ARMCPU *cpu = arm_env_get_cpu(env); - if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU) + if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA) && !extended_addresses_enabled(env)) { /* For VMSA (when not using the LPAE long descriptor page table * format) this register includes the ASID, so do a TLB flush. @@ -4615,7 +4615,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, v6k_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_V7MP) && - !arm_feature(env, ARM_FEATURE_MPU)) { + !arm_feature(env, ARM_FEATURE_PMSA)) { define_arm_cp_regs(cpu, v7mp_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_V7)) { @@ -4969,7 +4969,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) } } - if (arm_feature(env, ARM_FEATURE_MPU)) { + if (arm_feature(env, ARM_FEATURE_PMSA)) { if (arm_feature(env, ARM_FEATURE_V6)) { /* PMSAv6 not implemented */ assert(arm_feature(env, ARM_FEATURE_V7)); @@ -5131,7 +5131,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); } define_arm_cp_regs(cpu, id_cp_reginfo); - if (!arm_feature(env, ARM_FEATURE_MPU)) { + if (!arm_feature(env, ARM_FEATURE_PMSA)) { define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); } else if (arm_feature(env, ARM_FEATURE_V7)) { define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); @@ -8442,7 +8442,7 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, /* pmsav7 has special handling for when MPU is disabled so call it before * the common MMU/MPU disabled check below. */ - if (arm_feature(env, ARM_FEATURE_MPU) && + if (arm_feature(env, ARM_FEATURE_PMSA) && arm_feature(env, ARM_FEATURE_V7)) { *page_size = TARGET_PAGE_SIZE; return get_phys_addr_pmsav7(env, address, access_type, mmu_idx, @@ -8457,7 +8457,7 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, return 0; } - if (arm_feature(env, ARM_FEATURE_MPU)) { + if (arm_feature(env, ARM_FEATURE_PMSA)) { /* Pre-v7 MPU */ *page_size = TARGET_PAGE_SIZE; return get_phys_addr_pmsav5(env, address, access_type, mmu_idx, diff --git a/target/arm/machine.c b/target/arm/machine.c index d8094a8..ac6b758 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -142,7 +142,7 @@ static bool pmsav7_needed(void *opaque) ARMCPU *cpu = opaque; CPUARMState *env = &cpu->env; - return arm_feature(env, ARM_FEATURE_MPU) && + return arm_feature(env, ARM_FEATURE_PMSA) && arm_feature(env, ARM_FEATURE_V7); } From patchwork Thu Jun 1 17:10:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 100948 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp857259obc; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id p43si20187228qte.133.2017.06.01.10.11.13 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Jun 2017 10:11:13 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45799 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTcs-00014t-PY for patch@linaro.org; Thu, 01 Jun 2017 13:11:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35063) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTcT-00012u-Pl for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGTcS-00067g-Uv for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:45 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37144) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTcS-00064g-Ne for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:44 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTcR-0007Q3-Jm for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:43 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:19 +0100 Message-Id: <1496337035-30213-12-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 11/27] arm: Don't clear ARM_FEATURE_PMSA for no-mpu configs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Fix the handling of QOM properties for PMSA CPUs with no MPU: Allow no-MPU to be specified by either: * has-mpu = false * pmsav7_dregion = 0 and make setting one imply the other. Don't clear the PMSA feature bit in this situation. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-id: 1493122030-32191-6-git-send-email-peter.maydell@linaro.org --- target/arm/cpu.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f844af5..76a5e20 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -763,8 +763,14 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) cpu->id_pfr1 &= ~0xf000; } + /* MPU can be configured out of a PMSA CPU either by setting has-mpu + * to false or by setting pmsav7-dregion to 0. + */ if (!cpu->has_mpu) { - unset_feature(env, ARM_FEATURE_PMSA); + cpu->pmsav7_dregion = 0; + } + if (cpu->pmsav7_dregion == 0) { + cpu->has_mpu = false; } if (arm_feature(env, ARM_FEATURE_PMSA) && From patchwork Thu Jun 1 17:10:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 100951 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp858331obc; Thu, 1 Jun 2017 10:14:00 -0700 (PDT) X-Received: by 10.237.37.100 with SMTP id w33mr3443733qtc.14.1496337239973; Thu, 01 Jun 2017 10:13:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496337239; cv=none; d=google.com; s=arc-20160816; b=HHKEjIiL9fzIKE+3EpVeaWWmQMIUR6gYq8W7sKCnT7WXJJOKyOHxEyesSrkpEplOJ6 7EJvf4Q1qcfF7S+wSAafYzf3Ob/AwxnAJ6yxiBnlv5laeac47yS2H+KonQwXuovnphNv IWDJmCuUkbJDkNAEs0oV27lZOm/fjkkr7DpqqDWy4Voz9UGSypUHUDLfpr3hX4cwzhv4 v7UqumiwklcrBuOxU0MpGFIYm/w63jpUPt7t5qr4QOJYFOByiAu3zBrD/qxWWBTnDyml kK9O2bsN3KPwkSsx1Pd1J6BIba9tc7ID13CrmsxOBGrp9fCFXlpsa6r+p/RHoB5dUG/k f8CQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=f0D+qYvn348QkfpMFfZJSvg1AhvLdHWBeY2lqC+QHCo=; b=E9FGhn+yRTVnIwpKvQxH0o1+FnWhuyb2zvbzPiHGthueFHg8SwzsxoTnkbTfu7/M3W se31ZLKWnooKgalulndZviyEpR0SaRN5LDpof3CHiH3aWFeqOhSC2/xIIYGfq1ei9hbE 6oiJYRAICz+tY0Thjggv+DACytoDCEusYDmA763diNil3gMaWvgSORWKi/stO8/z8hA8 2L4XxOyKSyx+GOwu6N7T3tInWYjhow883CJRYmSFYAmegfe1HiELvQOua7a4iEvmpO2o YKhy7N6obtCMBDj1tBmsCpMogrQ6lVveJ485+yqOuAjPdzNbRdt3nFBgMe2a6KuUNzNk UVWQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 85si10390409qkz.146.2017.06.01.10.13.59 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Jun 2017 10:13:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45807 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTfZ-0003fY-Dp for patch@linaro.org; Thu, 01 Jun 2017 13:13:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35072) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTcU-00013I-9J for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGTcT-000684-D0 for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:46 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37145) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTcT-00067A-5D for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:45 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTcS-0007QJ-85 for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:44 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:20 +0100 Message-Id: <1496337035-30213-13-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 12/27] arm: Don't let no-MPU PMSA cores write to SCTLR.M X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" If the CPU is a PMSA config with no MPU implemented, then the SCTLR.M bit should be RAZ/WI, so that the guest can never turn on the non-existent MPU. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-id: 1493122030-32191-7-git-send-email-peter.maydell@linaro.org --- target/arm/helper.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.7.4 diff --git a/target/arm/helper.c b/target/arm/helper.c index 404bfdb..f0f25c8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3258,6 +3258,11 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, return; } + if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { + /* M bit is RAZ/WI for PMSA with no MPU implemented */ + value &= ~SCTLR_M; + } + raw_write(env, ri, value); /* ??? Lots of these bits are not implemented. */ /* This may enable/disable the MMU, so do a TLB flush. */ From patchwork Thu Jun 1 17:10:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 100949 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp857273obc; Thu, 1 Jun 2017 10:11:14 -0700 (PDT) X-Received: by 10.237.55.193 with SMTP id j59mr3317487qtb.238.1496337074285; Thu, 01 Jun 2017 10:11:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496337074; cv=none; d=google.com; s=arc-20160816; b=DJhBLzqWKblp7ZGHISP1W36cwanDDbHXWtzNaEQYQIX77wjxMhKLtR6uYFvGOLuqub nm6Qkb9s8veuGIvAyPIH1hUxY+i8Y3EQ7I98q6x4lysiePiO0x5c+6Olp3toC5M0OJYC s43suTBLHMMQRTkK00OLC9IqoDyEZpfDZLcc7WspcEjyI29m3pODYRE+M9ybZS0WifBw BkgNCEv8XyMOlcN4eIP/BJJd7em9JwkI7gq3wLBBusqUYqSO9JZMEf/Qvczld7oKEnBH AjYQNGj4XCFHnoO9P6RDahoqLLh8ix6cKleip3aA9JoOICRuO8zR93N1J6DV4r5nyY2H 0F/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=bhwzZmJ7y2ZBCa4hZV1FPrSfotsOTy+t1xZNXh4pINM=; b=dBJ1Vwm23qBYEzbzCZFtKHokmeXO6dLViBvlJH1TfNhzYDO1YP9WGFWBCP6QGIOp2l WxUZJh1W9F0261zkrZOrpD+oXOaa2HAW9NBSE1FUzSG4NPSpyEOEuwdQ70q+fwnlJaE8 njZ3iTscx9Lho2iVrqNMjoIQFypgXawco6WynfpK6Obfzo/B8DoF2BAZSgDzFWiLPwtF U3iOzQnGvFplxuHkOfoUxdC72a5/d/8D74LTc4li0FosrrNmiwGfbfvpk5Dxflgm7JPN TD1ML3u10cRH/fiIvq0X3f37VRLtULYujWyRgAcypH8xZorg8AhcDE5RDSg9LZB5J5yC eMpA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id k62si2209183qke.89.2017.06.01.10.11.13 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Jun 2017 10:11:14 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45800 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTct-000160-Ky for patch@linaro.org; Thu, 01 Jun 2017 13:11:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35081) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTcU-00013Z-LK for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGTcT-00068F-RQ for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:46 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37144) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTcT-00064g-KB for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:45 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTcS-0007QX-Rb for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:44 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:21 +0100 Message-Id: <1496337035-30213-14-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 13/27] arm: Remove unnecessary check on cpu->pmsav7_dregion X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that we enforce both: * pmsav7_dregion == 0 implies has_mpu == false * PMSA with has_mpu == false means SCTLR.M cannot be set we can remove a check on pmsav7_dregion from get_phys_addr_pmsav7(), because we can only reach this code path if the MPU is enabled (and so region_translation_disabled() returned false). Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 1493122030-32191-8-git-send-email-peter.maydell@linaro.org --- target/arm/helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) -- 2.7.4 diff --git a/target/arm/helper.c b/target/arm/helper.c index f0f25c8..5c044d0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8227,8 +8227,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, } if (n == -1) { /* no hits */ - if (cpu->pmsav7_dregion && - (is_user || !(regime_sctlr(env, mmu_idx) & SCTLR_BR))) { + if (is_user || !(regime_sctlr(env, mmu_idx) & SCTLR_BR)) { /* background fault */ *fsr = 0; return true; From patchwork Thu Jun 1 17:10:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 100954 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp858909obc; Thu, 1 Jun 2017 10:15:23 -0700 (PDT) X-Received: by 10.55.129.195 with SMTP id c186mr3427301qkd.255.1496337323345; Thu, 01 Jun 2017 10:15:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496337323; cv=none; d=google.com; s=arc-20160816; b=f1fdOxnIxwVtq+hMPf4M+hZCAvAcW4NEcYgcXB58Broq6jW5XKDT0GLeaco7RkxKOY AF2SuzFy0+BylVus2ZgYs+jqB8KbPzPVE+HKE7qXgLJ39xi41JzbfpikUFDucmD+ToJi GzhB0JZ4sUGDQSIO4dIDHlXEDVZmi3Z4xlTztGb7P6EMqu0Rf3Z1kbEBU4wyIgblCvMq WdPPECXG2odhJqRz5YDgz3y+mYPxa7/dBkH/85gvsP6KgmunTYsPVWoSe6xUSSDPQud6 CUSIE+yZTdVqbqRgppki2AvUCry1Burr7GTSIMW4s9X3AHDBByyAqp4R+97cgQcvh/eU bQBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=0S1Sh+A+IiP2EoLVLISgh7o252gAb8sxfcC/Q5DEBds=; b=vwgbNcWcVXYDg+/mIakNYoQGGzw6d8YrTEmHQ3GYQd/uZBJXc6G3QgPwCGf/ldJc++ 6Yg9c1EDO61ygqyIu0ud6EhjCQkomrpsLRNJnLtaAQ2b9/wth71sl/2YcxwhNTjH2K3v 0wOjmE/SGVqaba4uH24iVK844Lx7TOKnL/53NZ53cTrU8UlcrxabuyiWly/xETZeQOc8 cxIBDZqSA43pYdnpRuFtY75WMVCZ5OsaNu8pyf8YXpjXdblbfhoZDZClfjcLJhT8R/cb nDFDq7+F9JKnsJzCPSTShw2ZvRsryxIvozkhTvEqJveg+LIxkhsLD+wIptYqPRNyTvjn DeUQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id m3si20120052qkd.257.2017.06.01.10.15.22 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Jun 2017 10:15:23 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45815 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTgu-0004pW-Kj for patch@linaro.org; Thu, 01 Jun 2017 13:15:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35114) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTcV-00014j-UF for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGTcU-000694-Re for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:47 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37146) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTcU-00068M-K1 for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:46 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTcT-0007Qt-Ki for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:45 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:22 +0100 Message-Id: <1496337035-30213-15-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 14/27] armv7m: Improve "-d mmu" tracing for PMSAv7 MPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Michael Davidsaver Improve the "-d mmu" tracing for the PMSAv7 MPU translation process as an aid in debugging guest MPU configurations: * fix a missing newline for a guest-error log * report the region number with guest-error or unimp logs of bad region register values * add a log message for the overall result of the lookup * print "0x" prefix for hex values Signed-off-by: Michael Davidsaver Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-id: 1493122030-32191-9-git-send-email-peter.maydell@linaro.org [PMM: a little tidyup, report region number in all messages rather than just one] Signed-off-by: Peter Maydell --- target/arm/helper.c | 39 +++++++++++++++++++++++++++------------ 1 file changed, 27 insertions(+), 12 deletions(-) -- 2.7.4 diff --git a/target/arm/helper.c b/target/arm/helper.c index 5c044d0..9e1ed1c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8169,16 +8169,18 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, } if (!rsize) { - qemu_log_mask(LOG_GUEST_ERROR, "DRSR.Rsize field can not be 0"); + qemu_log_mask(LOG_GUEST_ERROR, + "DRSR[%d]: Rsize field cannot be 0\n", n); continue; } rsize++; rmask = (1ull << rsize) - 1; if (base & rmask) { - qemu_log_mask(LOG_GUEST_ERROR, "DRBAR %" PRIx32 " misaligned " - "to DRSR region size, mask = %" PRIx32, - base, rmask); + qemu_log_mask(LOG_GUEST_ERROR, + "DRBAR[%d]: 0x%" PRIx32 " misaligned " + "to DRSR region size, mask = 0x%" PRIx32 "\n", + n, base, rmask); continue; } @@ -8215,9 +8217,10 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, } } if (rsize < TARGET_PAGE_BITS) { - qemu_log_mask(LOG_UNIMP, "No support for MPU (sub)region" + qemu_log_mask(LOG_UNIMP, + "DRSR[%d]: No support for MPU (sub)region " "alignment of %" PRIu32 " bits. Minimum is %d\n", - rsize, TARGET_PAGE_BITS); + n, rsize, TARGET_PAGE_BITS); continue; } if (srdis) { @@ -8251,8 +8254,8 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, break; default: qemu_log_mask(LOG_GUEST_ERROR, - "Bad value for AP bits in DRACR %" - PRIx32 "\n", ap); + "DRACR[%d]: Bad value for AP bits: 0x%" + PRIx32 "\n", n, ap); } } else { /* Priv. mode AP bits decoding */ switch (ap) { @@ -8269,8 +8272,8 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, break; default: qemu_log_mask(LOG_GUEST_ERROR, - "Bad value for AP bits in DRACR %" - PRIx32 "\n", ap); + "DRACR[%d]: Bad value for AP bits: 0x%" + PRIx32 "\n", n, ap); } } @@ -8448,9 +8451,21 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, */ if (arm_feature(env, ARM_FEATURE_PMSA) && arm_feature(env, ARM_FEATURE_V7)) { + bool ret; *page_size = TARGET_PAGE_SIZE; - return get_phys_addr_pmsav7(env, address, access_type, mmu_idx, - phys_ptr, prot, fsr); + ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, + phys_ptr, prot, fsr); + qemu_log_mask(CPU_LOG_MMU, "PMSAv7 MPU lookup for %s at 0x%08" PRIx32 + " mmu_idx %u -> %s (prot %c%c%c)\n", + access_type == 1 ? "reading" : + (access_type == 2 ? "writing" : "execute"), + (uint32_t)address, mmu_idx, + ret ? "Miss" : "Hit", + *prot & PAGE_READ ? 'r' : '-', + *prot & PAGE_WRITE ? 'w' : '-', + *prot & PAGE_EXEC ? 'x' : '-'); + + return ret; } if (regime_translation_disabled(env, mmu_idx)) { From patchwork Thu Jun 1 17:10:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 100953 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp858881obc; Thu, 1 Jun 2017 10:15:19 -0700 (PDT) X-Received: by 10.55.27.97 with SMTP id b94mr3071464qkb.169.1496337319765; Thu, 01 Jun 2017 10:15:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496337319; cv=none; d=google.com; s=arc-20160816; b=zLJSP1UsNJRko0e4QabD5ckmRtcBnklnLfE/5AzbY6QhGRDyoNtrxEuhbEhvUhbYQC pco10cpwpvzNhpKWFq22KeUUtZFSETiGDwZtwJdBhhFZMgkRqnGc8BAvkzIMYMLSqugL 4n4ksDN8OpE+NiS7CBDJQaH7LCYrv3iGy362eNdQGkXgz1TtQ5XUlB0tQANq06dclXN9 KN121XhiLCYMrHu1r8rpwp/60fJ3Dh6mkq8VwJrnCWwWOQ60aTYS6DoOmKw+C50K1byK heMa6tbBf5gXgaPslcI89WAsv+dTtxyhaGXcycvGJ9VSDgHYXvmqBze7V2f6YFoiuHKS Thtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=zMum8BDrQaAagQX8e9bJOPIYUX+fHth6I1SOVOLIoh4=; b=D0tRqukYkmUjjYkvPpwVHgSWFKREVZImHf1guR2HNX7520dOtPZM0YXNsd4eoHkb9A U7CXg5pk3Goin3XQDF9Qv/dNixRZEWRMfl576CL+td1FWMjNH72MZPtUYYLYTF1DIh/l 7hSHLWopq/735R1EqzwpNzZZvx73ehIpL5bu1wRnP1GveNPhNTzaBwMrzWSYae4cVsTQ qES70Ck7CBbK14Z5+o8I4pLaWHpxRbrltu33RXp3haUVfVriYahomI5M0CxdePrCtkgO j6tyNmQQdKcVFu3Hf34zgCLn+NxEyJlOyEVzOBtwASEIkSKUWwsGYGk3hFrmclZxhnsQ c1eQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id i125si20392296qkd.61.2017.06.01.10.15.19 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Jun 2017 10:15:19 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45814 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTgr-0004nR-3l for patch@linaro.org; Thu, 01 Jun 2017 13:15:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35122) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTcW-000159-7j for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGTcV-00069I-8t for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:48 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37145) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTcV-00067A-1N for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:47 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTcU-0007R9-AP for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:46 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:23 +0100 Message-Id: <1496337035-30213-16-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 15/27] armv7m: Implement M profile default memory map X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Michael Davidsaver Add support for the M profile default memory map which is used if the MPU is not present or disabled. The main differences in behaviour from implementing this correctly are that we set the PAGE_EXEC attribute on the right regions of memory, such that device regions are not executable. Signed-off-by: Michael Davidsaver Message-id: 1493122030-32191-10-git-send-email-peter.maydell@linaro.org [PMM: rephrased comment and commit message; don't mark the flash memory region as not-writable; list all the cases in the default map explicitly rather than using a 'default' case for the non-executable regions] Signed-off-by: Peter Maydell --- target/arm/helper.c | 41 ++++++++++++++++++++++++++++++++--------- 1 file changed, 32 insertions(+), 9 deletions(-) -- 2.7.4 diff --git a/target/arm/helper.c b/target/arm/helper.c index 9e1ed1c..180b490 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8129,18 +8129,41 @@ static inline void get_phys_addr_pmsav7_default(CPUARMState *env, ARMMMUIdx mmu_idx, int32_t address, int *prot) { - *prot = PAGE_READ | PAGE_WRITE; - switch (address) { - case 0xF0000000 ... 0xFFFFFFFF: - if (regime_sctlr(env, mmu_idx) & SCTLR_V) { /* hivecs execing is ok */ + if (!arm_feature(env, ARM_FEATURE_M)) { + *prot = PAGE_READ | PAGE_WRITE; + switch (address) { + case 0xF0000000 ... 0xFFFFFFFF: + if (regime_sctlr(env, mmu_idx) & SCTLR_V) { + /* hivecs execing is ok */ + *prot |= PAGE_EXEC; + } + break; + case 0x00000000 ... 0x7FFFFFFF: *prot |= PAGE_EXEC; + break; + } + } else { + /* Default system address map for M profile cores. + * The architecture specifies which regions are execute-never; + * at the MPU level no other checks are defined. + */ + switch (address) { + case 0x00000000 ... 0x1fffffff: /* ROM */ + case 0x20000000 ... 0x3fffffff: /* SRAM */ + case 0x60000000 ... 0x7fffffff: /* RAM */ + case 0x80000000 ... 0x9fffffff: /* RAM */ + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + break; + case 0x40000000 ... 0x5fffffff: /* Peripheral */ + case 0xa0000000 ... 0xbfffffff: /* Device */ + case 0xc0000000 ... 0xdfffffff: /* Device */ + case 0xe0000000 ... 0xffffffff: /* System */ + *prot = PAGE_READ | PAGE_WRITE; + break; + default: + g_assert_not_reached(); } - break; - case 0x00000000 ... 0x7FFFFFFF: - *prot |= PAGE_EXEC; - break; } - } static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, From patchwork Thu Jun 1 17:10:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 100958 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp859732obc; Thu, 1 Jun 2017 10:17:36 -0700 (PDT) X-Received: by 10.200.40.46 with SMTP id 43mr3244458qtq.132.1496337456789; Thu, 01 Jun 2017 10:17:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496337456; cv=none; d=google.com; s=arc-20160816; b=Dvka5n8iYkkjGA9ITpSd5kkh+ptXBAIH2Aw3uG5gOqv6HjNRLvYTqaKq0ESViGNPmB jNSissST3azZOYcko/ThOxymjN+Lib4BNUuJU+XL5J+1F8WVc9CuLobytCw16rinSQRd +qXimQf/fzxgRqoccac3LMdNEPrZpcdu0gDvjzanVFY8tA5RcBHlRby6oO1iB/qop2U2 UNpNs6rY7rGG5zT82BJ5zdf449BEiRcw0JmbQh3a3nGq2VDhTvIxWCD3sZ8tIyA2bH3P RLy81QfiUIDaYpW89KnwzozT4lL1a85SOao0uU5FsddLtksZTzS7RJFjqRBZqOZ9R1iv Gljw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=7I+cCeqRQOKZ+Adfidop6cUI+wtw3Z7jO330IBkKUI8=; b=kXVq/Z6nm3JlBANFftZiTB91JylC4VzR9Z0qPIRInYcY1dO8mYuBdwXPDtBUiEf13A zP6M8bFXVUU84TPEqdwSQskQPbej7j1AgonIiPY+KHJTuqf0SpKSAJvg+nZMPulHeuPP Y2zwaq4zdBiyuv7oOSIMAsmH8MVoP4Tn+9qvAygS5tg449c8zktwRWBy6kWfKf71okIC ldhKFR0NrN3E3dc2IdMNHan2elPuk6w9FXjLqVht57nDbnAMMhndQGseQX6846HFMIPz DujtV0lRF2H6XCQ/5Q/fKkoc4NLu4FQJsLGKcXiw5UnOyRh+7IoarB/FIasf/hOx+mH5 l53w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id g65si19244730qke.238.2017.06.01.10.17.36 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Jun 2017 10:17:36 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45825 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTj4-0006gx-8Q for patch@linaro.org; Thu, 01 Jun 2017 13:17:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35161) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTcX-00016S-H8 for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGTcW-0006Ai-AK for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:49 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37145) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTcW-00067A-2w for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:48 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTcU-0007Ra-UL for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:46 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:24 +0100 Message-Id: <1496337035-30213-17-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 16/27] arm: All M profile cores are PMSA X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" All M profile CPUs are PMSA, so set the feature bit. (We haven't actually implemented the M profile MPU register interface yet, but setting this feature bit gives us closer to correct behaviour for the MPU-disabled case.) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 1493122030-32191-11-git-send-email-peter.maydell@linaro.org --- target/arm/cpu.c | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.7.4 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 76a5e20..e748097 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -550,6 +550,14 @@ static void arm_cpu_post_init(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + /* M profile implies PMSA. We have to do this here rather than + * in realize with the other feature-implication checks because + * we look at the PMSA bit to see if we should add some properties. + */ + if (arm_feature(&cpu->env, ARM_FEATURE_M)) { + set_feature(&cpu->env, ARM_FEATURE_PMSA); + } + if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, From patchwork Thu Jun 1 17:10:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 100961 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp860870obc; Thu, 1 Jun 2017 10:20:31 -0700 (PDT) X-Received: by 10.200.34.229 with SMTP id g34mr3266278qta.65.1496337631738; Thu, 01 Jun 2017 10:20:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496337631; cv=none; d=google.com; s=arc-20160816; b=GsncHeneUNO0eHG56qXwz+kfNlV8fd1UwtwOIH46rqIDYCgbTLTawzQdF6LhdPzRVc HtSOj12q0ritiid+o4aFAt52bruI9jlpWEzuHGoI5b6T9KfyAz+8SPvKVxXLMtddCPJs u8Vs9gkvuVDCcwx3S6CpnhZRSegaqJuTgmkWWABBdn3BIudG2J7WTWggXVn8UGoUcRBP IStYDmUAZQzUCOTssmb43CqEaJdrTDZW9e2Bif888mNtq8HoJvhH+IKPrmvZ/NgP+c2E GutJufhSCgR/dDYJpmwKFBSozHBCdH19xwt84bdr5ZTq1wr11DBp9sooJGnNqTxOupN4 GgIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=KXZHwvtfqFJEFmuIQUU+PO2WwNcrLem9zQqKtT632vM=; b=irz+02hL/ie5+Q9NSXBXaFJ6nOy0NXBHWY1c7HAb4xytzmDvPiEEDRaG1em4PwExli vGVxcTxJjLgrdVCEXALmq64CKBpKhmueQ1mLSW3wYKDDVwP2WVyT4A18Sy74Uuk5Q6af DFrnE6XCfRdLwJUUdCU+eL2lng6i9l6OiV+H0a8ArCJ3VcWmC8mrxkuSDynGXdbCGQ2+ wbaaWRoc+HjNODvXS/+EYoshmXN/ke0S4qUOJqarRpHaF4qhpWL0LL6/XSGgH5k9w/rE 5NYDBaY3lODW37YeapZjLSgj3nDmKGuq5WrL86BlFzBbMK+BWKpzf0gKqATwQrjvvGhh nIrQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id p188si134113qkd.25.2017.06.01.10.20.31 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Jun 2017 10:20:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45836 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTlt-000160-1b for patch@linaro.org; Thu, 01 Jun 2017 13:20:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35204) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTcY-00017D-EQ for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGTcW-0006BC-Uw for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:50 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37147) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTcW-0006AO-OC for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:48 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTcV-0007S0-I1 for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:47 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:25 +0100 Message-Id: <1496337035-30213-18-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 17/27] armv7m: Classify faults as MemManage or BusFault X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Michael Davidsaver General logic is that operations stopped by the MPU are MemManage, and those which go through the MPU and are caught by the unassigned handle are BusFault. Distinguish these by looking at the exception.fsr values, and set the CFSR bits and (if appropriate) fill in the BFAR or MMFAR with the exception address. Signed-off-by: Michael Davidsaver Message-id: 1493122030-32191-12-git-send-email-peter.maydell@linaro.org [PMM: i-side faults do not set BFAR/MMFAR, only d-side; added some CPU_LOG_INT logging] Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- target/arm/helper.c | 45 ++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 42 insertions(+), 3 deletions(-) -- 2.7.4 diff --git a/target/arm/helper.c b/target/arm/helper.c index 180b490..c9d94c5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6342,10 +6342,49 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: - /* TODO: if we implemented the MPU registers, this is where we - * should set the MMFAR, etc from exception.fsr and exception.vaddress. + /* Note that for M profile we don't have a guest facing FSR, but + * the env->exception.fsr will be populated by the code that + * raises the fault, in the A profile short-descriptor format. */ - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM); + switch (env->exception.fsr & 0xf) { + case 0x8: /* External Abort */ + switch (cs->exception_index) { + case EXCP_PREFETCH_ABORT: + env->v7m.cfsr |= R_V7M_CFSR_PRECISERR_MASK; + qemu_log_mask(CPU_LOG_INT, "...with CFSR.PRECISERR\n"); + break; + case EXCP_DATA_ABORT: + env->v7m.cfsr |= + (R_V7M_CFSR_IBUSERR_MASK | R_V7M_CFSR_BFARVALID_MASK); + env->v7m.bfar = env->exception.vaddress; + qemu_log_mask(CPU_LOG_INT, + "...with CFSR.IBUSERR and BFAR 0x%x\n", + env->v7m.bfar); + break; + } + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS); + break; + default: + /* All other FSR values are either MPU faults or "can't happen + * for M profile" cases. + */ + switch (cs->exception_index) { + case EXCP_PREFETCH_ABORT: + env->v7m.cfsr |= R_V7M_CFSR_IACCVIOL_MASK; + qemu_log_mask(CPU_LOG_INT, "...with CFSR.IACCVIOL\n"); + break; + case EXCP_DATA_ABORT: + env->v7m.cfsr |= + (R_V7M_CFSR_DACCVIOL_MASK | R_V7M_CFSR_MMARVALID_MASK); + env->v7m.mmfar = env->exception.vaddress; + qemu_log_mask(CPU_LOG_INT, + "...with CFSR.DACCVIOL and MMFAR 0x%x\n", + env->v7m.mmfar); + break; + } + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM); + break; + } break; case EXCP_BKPT: if (semihosting_enabled()) { From patchwork Thu Jun 1 17:10:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 100971 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp863857obc; Thu, 1 Jun 2017 10:27:57 -0700 (PDT) X-Received: by 10.55.38.2 with SMTP id y2mr3095709qkg.188.1496338077733; Thu, 01 Jun 2017 10:27:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496338077; cv=none; d=google.com; s=arc-20160816; b=WyL/4XnJE6RPQOnwC0HUcXFP010vkbC/O5WayZo2XiZGEY1wg7juhmu0W1THt0gJLC KKi+uY/if0XNLUdGHdEvQMq4ndjtsjK8LgTbVkChgjfR1dZP+DHpFeb/qvZEVqQLfyQj Jx7KdrD+8rb0YcNUunGtscbC05TV/mZ6rXffGf6fMsPoCjJEqkMONAkVWC6wjTyMf5wZ 3EObUiK+OMQuukUcHA+FMRoDdgaXmGyc8pC++IJzI8VaoWMoqBZzw7mdNlhu76ZBjatv XsWh7/zGGqC+sq5kfSBJhiWgfmhQTYJ9/mPq1v5U418//vMPmOD9un9zDJMYb2HOlg7G Ra/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=AxhH3wl34jVPdiH5pquReSmFxWuId0OTui9zp0ahQ9I=; b=N2cUo98NeKzjRxQ0DT//YKsE4VusHWCtmX/rwhGD5QZ4EEP7FVS2cSMQ3u7Hy3uVnR vDMfrtaXShtFStDV0sBMqXhRm/sgxXtHSARtEVwvCWAPHukIYg0GlMhAvOX4oeGPBeYQ m3FleNAqqdqmXTWt6mZDoanY5MyczaJ/vxWs9oPNJl2zucjeSkgJiW97avVy3av0KExy AcZa6v1iIVVL6Qx6RVpxJbjcMK05FGQ1KpFhJL81cZXqS3jvP9Xard24SlccRjjrzhZ1 U+GWpMtwFB8PLYfzVo8ET1GrDf23vAtPOriInbzxkDIud1968FQLTR9j9a4QFmDJ34Pe RORA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 31si20102643qtn.87.2017.06.01.10.27.57 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Jun 2017 10:27:57 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45871 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTt4-0007nT-Rn for patch@linaro.org; Thu, 01 Jun 2017 13:27:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35263) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTcZ-00017I-OA for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGTcX-0006Bo-Rn for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:51 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37146) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTcX-00068M-Hu for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:49 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTcW-0007SM-Gj for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:48 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:26 +0100 Message-Id: <1496337035-30213-19-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 18/27] arm: add MPU support to M profile CPUs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Michael Davidsaver The M series MPU is almost the same as the already implemented R profile MPU (v7 PMSA). So all we need to implement here is the MPU register interface in the system register space. This implementation has the same restriction as the R profile MPU that it doesn't permit regions to be sized down smaller than 1K. We also do not yet implement support for MPU_CTRL.HFNMIENA; this bit should if zero disable use of the MPU when running HardFault, NMI or with FAULTMASK set to 1 (ie at an execution priority of less than zero) -- if the MPU is enabled we don't treat these cases any differently. Signed-off-by: Michael Davidsaver Message-id: 1493122030-32191-13-git-send-email-peter.maydell@linaro.org [PMM: Keep all the bits in mpu_ctrl field, rather than using SCTLR bits for them; drop broken HFNMIENA support; various cleanup] Signed-off-by: Peter Maydell --- target/arm/cpu.h | 6 +++ hw/intc/armv7m_nvic.c | 104 ++++++++++++++++++++++++++++++++++++++++++++++++++ target/arm/helper.c | 25 +++++++++++- target/arm/machine.c | 5 ++- 4 files changed, 137 insertions(+), 3 deletions(-) -- 2.7.4 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cb1d696..5c46c48 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -418,6 +418,7 @@ typedef struct CPUARMState { uint32_t dfsr; /* Debug Fault Status Register */ uint32_t mmfar; /* MemManage Fault Address */ uint32_t bfar; /* BusFault Address */ + unsigned mpu_ctrl; /* MPU_CTRL (some bits kept in sctlr_el[1]) */ int exception; } v7m; @@ -1168,6 +1169,11 @@ FIELD(V7M_DFSR, DWTTRAP, 2, 1) FIELD(V7M_DFSR, VCATCH, 3, 1) FIELD(V7M_DFSR, EXTERNAL, 4, 1) +/* v7M MPU_CTRL bits */ +FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) +FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) +FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) + /* If adding a feature bit which corresponds to a Linux ELF * HWCAP bit, remember to update the feature-bit-to-hwcap * mapping in linux-user/elfload.c:get_elf_hwcap(). diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 32ffa0b..26a4b2d 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -19,6 +19,7 @@ #include "hw/arm/arm.h" #include "hw/arm/armv7m_nvic.h" #include "target/arm/cpu.h" +#include "exec/exec-all.h" #include "qemu/log.h" #include "trace.h" @@ -528,6 +529,39 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset) case 0xd70: /* ISAR4. */ return 0x01310102; /* TODO: Implement debug registers. */ + case 0xd90: /* MPU_TYPE */ + /* Unified MPU; if the MPU is not present this value is zero */ + return cpu->pmsav7_dregion << 8; + break; + case 0xd94: /* MPU_CTRL */ + return cpu->env.v7m.mpu_ctrl; + case 0xd98: /* MPU_RNR */ + return cpu->env.cp15.c6_rgnr; + case 0xd9c: /* MPU_RBAR */ + case 0xda4: /* MPU_RBAR_A1 */ + case 0xdac: /* MPU_RBAR_A2 */ + case 0xdb4: /* MPU_RBAR_A3 */ + { + int region = cpu->env.cp15.c6_rgnr; + + if (region >= cpu->pmsav7_dregion) { + return 0; + } + return (cpu->env.pmsav7.drbar[region] & 0x1f) | (region & 0xf); + } + case 0xda0: /* MPU_RASR */ + case 0xda8: /* MPU_RASR_A1 */ + case 0xdb0: /* MPU_RASR_A2 */ + case 0xdb8: /* MPU_RASR_A3 */ + { + int region = cpu->env.cp15.c6_rgnr; + + if (region >= cpu->pmsav7_dregion) { + return 0; + } + return ((cpu->env.pmsav7.dracr[region] & 0xffff) << 16) | + (cpu->env.pmsav7.drsr[region] & 0xffff); + } default: qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset); return 0; @@ -627,6 +661,76 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) qemu_log_mask(LOG_UNIMP, "NVIC: Aux fault status registers unimplemented\n"); break; + case 0xd90: /* MPU_TYPE */ + return; /* RO */ + case 0xd94: /* MPU_CTRL */ + if ((value & + (R_V7M_MPU_CTRL_HFNMIENA_MASK | R_V7M_MPU_CTRL_ENABLE_MASK)) + == R_V7M_MPU_CTRL_HFNMIENA_MASK) { + qemu_log_mask(LOG_GUEST_ERROR, "MPU_CTRL: HFNMIENA and !ENABLE is " + "UNPREDICTABLE\n"); + } + cpu->env.v7m.mpu_ctrl = value & (R_V7M_MPU_CTRL_ENABLE_MASK | + R_V7M_MPU_CTRL_HFNMIENA_MASK | + R_V7M_MPU_CTRL_PRIVDEFENA_MASK); + tlb_flush(CPU(cpu)); + break; + case 0xd98: /* MPU_RNR */ + if (value >= cpu->pmsav7_dregion) { + qemu_log_mask(LOG_GUEST_ERROR, "MPU region out of range %" + PRIu32 "/%" PRIu32 "\n", + value, cpu->pmsav7_dregion); + } else { + cpu->env.cp15.c6_rgnr = value; + } + break; + case 0xd9c: /* MPU_RBAR */ + case 0xda4: /* MPU_RBAR_A1 */ + case 0xdac: /* MPU_RBAR_A2 */ + case 0xdb4: /* MPU_RBAR_A3 */ + { + int region; + + if (value & (1 << 4)) { + /* VALID bit means use the region number specified in this + * value and also update MPU_RNR.REGION with that value. + */ + region = extract32(value, 0, 4); + if (region >= cpu->pmsav7_dregion) { + qemu_log_mask(LOG_GUEST_ERROR, + "MPU region out of range %u/%" PRIu32 "\n", + region, cpu->pmsav7_dregion); + return; + } + cpu->env.cp15.c6_rgnr = region; + } else { + region = cpu->env.cp15.c6_rgnr; + } + + if (region >= cpu->pmsav7_dregion) { + return; + } + + cpu->env.pmsav7.drbar[region] = value & ~0x1f; + tlb_flush(CPU(cpu)); + break; + } + case 0xda0: /* MPU_RASR */ + case 0xda8: /* MPU_RASR_A1 */ + case 0xdb0: /* MPU_RASR_A2 */ + case 0xdb8: /* MPU_RASR_A3 */ + { + int region = cpu->env.cp15.c6_rgnr; + + if (region >= cpu->pmsav7_dregion) { + return; + } + + cpu->env.pmsav7.drsr[region] = value & 0xff3f; + cpu->env.pmsav7.dracr[region] = (value >> 16) & 0x173f; + tlb_flush(CPU(cpu)); + break; + } case 0xf00: /* Software Triggered Interrupt Register */ { /* user mode can only write to STIR if CCR.USERSETMPEND permits it */ diff --git a/target/arm/helper.c b/target/arm/helper.c index c9d94c5..674b52d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7076,6 +7076,10 @@ static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) static inline bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx) { + if (arm_feature(env, ARM_FEATURE_M)) { + return !(env->v7m.mpu_ctrl & R_V7M_MPU_CTRL_ENABLE_MASK); + } + if (mmu_idx == ARMMMUIdx_S2NS) { return (env->cp15.hcr_el2 & HCR_VM) == 0; } @@ -8205,6 +8209,25 @@ static inline void get_phys_addr_pmsav7_default(CPUARMState *env, } } +static bool pmsav7_use_background_region(ARMCPU *cpu, + ARMMMUIdx mmu_idx, bool is_user) +{ + /* Return true if we should use the default memory map as a + * "background" region if there are no hits against any MPU regions. + */ + CPUARMState *env = &cpu->env; + + if (is_user) { + return false; + } + + if (arm_feature(env, ARM_FEATURE_M)) { + return env->v7m.mpu_ctrl & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; + } else { + return regime_sctlr(env, mmu_idx) & SCTLR_BR; + } +} + static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, int access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, int *prot, uint32_t *fsr) @@ -8292,7 +8315,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, } if (n == -1) { /* no hits */ - if (is_user || !(regime_sctlr(env, mmu_idx) & SCTLR_BR)) { + if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) { /* background fault */ *fsr = 0; return true; diff --git a/target/arm/machine.c b/target/arm/machine.c index ac6b758..1a40469 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -99,8 +99,8 @@ static bool m_needed(void *opaque) static const VMStateDescription vmstate_m = { .name = "cpu/m", - .version_id = 3, - .minimum_version_id = 3, + .version_id = 4, + .minimum_version_id = 4, .needed = m_needed, .fields = (VMStateField[]) { VMSTATE_UINT32(env.v7m.vecbase, ARMCPU), @@ -112,6 +112,7 @@ static const VMStateDescription vmstate_m = { VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), VMSTATE_UINT32(env.v7m.mmfar, ARMCPU), VMSTATE_UINT32(env.v7m.bfar, ARMCPU), + VMSTATE_UINT32(env.v7m.mpu_ctrl, ARMCPU), VMSTATE_INT32(env.v7m.exception, ARMCPU), VMSTATE_END_OF_LIST() } From patchwork Thu Jun 1 17:10:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 100957 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp859712obc; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id 56si20487324qtq.75.2017.06.01.10.17.33 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Jun 2017 10:17:33 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45826 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTj1-0006pC-DW for patch@linaro.org; Thu, 01 Jun 2017 13:17:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35283) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTca-00017g-27 for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGTcY-0006D6-Gt for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:52 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37148) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTcY-0006BY-8H for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:50 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTcX-0007Sx-8C for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:49 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:27 +0100 Message-Id: <1496337035-30213-20-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 19/27] arm: Implement HFNMIENA support for M profile MPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Implement HFNMIENA support for the M profile MPU. This bit controls whether the MPU is treated as enabled when executing at execution priorities of less than zero (in NMI, HardFault or with the FAULTMASK bit set). Doing this requires us to use a different MMU index for "running at execution priority < 0", because we will have different access permissions for that case versus the normal case. Signed-off-by: Peter Maydell Message-id: 1493122030-32191-14-git-send-email-peter.maydell@linaro.org --- target/arm/cpu.h | 24 +++++++++++++++++++++++- target/arm/helper.c | 18 +++++++++++++++++- target/arm/translate.c | 1 + 3 files changed, 41 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5c46c48..13da503 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2045,6 +2045,18 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, * for the accesses done as part of a stage 1 page table walk, rather than * having to walk the stage 2 page table over and over.) * + * R profile CPUs have an MPU, but can use the same set of MMU indexes + * as A profile. They only need to distinguish NS EL0 and NS EL1 (and + * NS EL2 if we ever model a Cortex-R52). + * + * M profile CPUs are rather different as they do not have a true MMU. + * They have the following different MMU indexes: + * User + * Privileged + * Execution priority negative (this is like privileged, but the + * MPU HFNMIENA bit means that it may have different access permission + * check results to normal privileged code, so can't share a TLB). + * * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code * are not quite the same -- different CPU types (most notably M profile * vs A/R profile) would like to use MMU indexes with different semantics, @@ -2080,6 +2092,7 @@ typedef enum ARMMMUIdx { ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, + ARMMMUIdx_MNegPri = 2 | ARM_MMU_IDX_M, /* Indexes below here don't have TLBs and are used only for AT system * instructions or for the first stage of an S12 page table walk. */ @@ -2100,6 +2113,7 @@ typedef enum ARMMMUIdxBit { ARMMMUIdxBit_S2NS = 1 << 6, ARMMMUIdxBit_MUser = 1 << 0, ARMMMUIdxBit_MPriv = 1 << 1, + ARMMMUIdxBit_MNegPri = 1 << 2, } ARMMMUIdxBit; #define MMU_USER_IDX 0 @@ -2125,7 +2139,7 @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) case ARM_MMU_IDX_A: return mmu_idx & 3; case ARM_MMU_IDX_M: - return mmu_idx & 1; + return mmu_idx == ARMMMUIdx_MUser ? 0 : 1; default: g_assert_not_reached(); } @@ -2139,6 +2153,14 @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) if (arm_feature(env, ARM_FEATURE_M)) { ARMMMUIdx mmu_idx = el == 0 ? ARMMMUIdx_MUser : ARMMMUIdx_MPriv; + /* Execution priority is negative if FAULTMASK is set or + * we're in a HardFault or NMI handler. + */ + if ((env->v7m.exception > 0 && env->v7m.exception <= 3) + || env->daif & PSTATE_F) { + return arm_to_core_mmu_idx(ARMMMUIdx_MNegPri); + } + return arm_to_core_mmu_idx(mmu_idx); } diff --git a/target/arm/helper.c b/target/arm/helper.c index 674b52d..2594faa 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7037,6 +7037,7 @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) case ARMMMUIdx_S1NSE0: case ARMMMUIdx_S1NSE1: case ARMMMUIdx_MPriv: + case ARMMMUIdx_MNegPri: case ARMMMUIdx_MUser: return 1; default: @@ -7055,6 +7056,7 @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) case ARMMMUIdx_S1E2: case ARMMMUIdx_S2NS: case ARMMMUIdx_MPriv: + case ARMMMUIdx_MNegPri: case ARMMMUIdx_MUser: return false; case ARMMMUIdx_S1E3: @@ -7077,7 +7079,21 @@ static inline bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx) { if (arm_feature(env, ARM_FEATURE_M)) { - return !(env->v7m.mpu_ctrl & R_V7M_MPU_CTRL_ENABLE_MASK); + switch (env->v7m.mpu_ctrl & + (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { + case R_V7M_MPU_CTRL_ENABLE_MASK: + /* Enabled, but not for HardFault and NMI */ + return mmu_idx == ARMMMUIdx_MNegPri; + case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK: + /* Enabled for all cases */ + return false; + case 0: + default: + /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but + * we warned about that in armv7m_nvic.c when the guest set it. + */ + return true; + } } if (mmu_idx == ARMMMUIdx_S2NS) { diff --git a/target/arm/translate.c b/target/arm/translate.c index ac905dd..ae6646c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -163,6 +163,7 @@ static inline int get_a32_user_mem_index(DisasContext *s) return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0); case ARMMMUIdx_MUser: case ARMMMUIdx_MPriv: + case ARMMMUIdx_MNegPri: return arm_to_core_mmu_idx(ARMMMUIdx_MUser); case ARMMMUIdx_S2NS: default: From patchwork Thu Jun 1 17:10:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 100967 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp862238obc; Thu, 1 Jun 2017 10:23:53 -0700 (PDT) X-Received: by 10.200.43.178 with SMTP id m47mr3252817qtm.228.1496337833316; Thu, 01 Jun 2017 10:23:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496337833; cv=none; d=google.com; s=arc-20160816; b=fEVb57TbBPsK/B6rabHY2Sm7Z+Ztum3wKnTgKMU4/P8p+Iia089aOnU2CdgJCKSKLh 9VR5ORFCiWTLK35m593X7KN+f16pVCQ1SEmY1zS38sOv5X96ASLRg7NwzdXH+KR76z/7 qLixv4/zr78tQD+YtDn5n33MlcS0hg6lHx8Vz+2AaCDkImRp7F9nTYWgQivuOP6DPFUF 4ONiUfOG8AIcx/QRUNjxS5iDTxr556VnVEbB9goMzDYFSwQbHgd4vJcS0P4NTY76Avoo g187mnZUCgWMLBgDjpmrz4vZuB474g4PrM8LA1Nq4x8jUDF0xVjVs55oNsJTmjrNB7wI VkXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=zPuvI1cW96PLt8qadeqJjzLb0rSRRokpvgn8w3Mw0mk=; b=0iQ2NdVynswjlDCYBTwD18Bnwm291lTTQay2JXMGyHkPV+N3Bt2Tpm05OtO2PfK/0N DsJOxPHu+aGrHsthqNF3iEBVGU4UyoeuYt3VWEEftJ1ekqy+YuPwWQ8hZnzx32tW1+pX CEhU+ZZ1+nyFaX/topQrhR3AhjLV8W80vKfXq90AEaD0cQy+2lSAs9nP67Om+FOQ2J3A AbYJq/hiJuGLKUFtCQnPJYtor0TZ//vAF/3/2y3PPljpG6B+2Uno6H/jQlKQmMkYovCB rZ52hAfmdGE+HbUNd8qvGkIYi9ZtITp+TDNmh9NszvSvCXBxCPNd+fClnd8P6n2oz5m2 7A8w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id h134si15722325qke.194.2017.06.01.10.23.52 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Jun 2017 10:23:53 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45853 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTp8-0004Vu-QW for patch@linaro.org; Thu, 01 Jun 2017 13:23:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35296) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTca-00018A-B4 for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGTcZ-0006EG-61 for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:52 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37145) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTcY-00067A-Tv for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:51 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTcX-0007TI-VJ for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:49 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:28 +0100 Message-Id: <1496337035-30213-21-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 20/27] aspeed/i2c: improve command handling X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater Multiple I2C commands can be fired simultaneously and the controller execute the commands following these priorities: (1) Master Start Command (2) Master Transmit Command (3) Slave Transmit Command or Master Receive Command (4) Master Stop Command The current code is incorrect with respect to the above sequence and needs to be reworked to handle each individual command. Signed-off-by: Cédric Le Goater Message-id: 1494827476-1487-2-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell --- hw/i2c/aspeed_i2c.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) -- 2.7.4 diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index ce5b1f0..56a4fdf 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -171,6 +171,7 @@ static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset, static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) { + bus->cmd &= ~0xFFFF; bus->cmd |= value & 0xFFFF; bus->intr_status = 0; @@ -182,15 +183,27 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) bus->intr_status |= I2CD_INTR_TX_ACK; } - } else if (bus->cmd & I2CD_M_TX_CMD) { + /* START command is also a TX command, as the slave address is + * sent on the bus */ + bus->cmd &= ~(I2CD_M_START_CMD | I2CD_M_TX_CMD); + + /* No slave found */ + if (!i2c_bus_busy(bus->bus)) { + return; + } + } + + if (bus->cmd & I2CD_M_TX_CMD) { if (i2c_send(bus->bus, bus->buf)) { bus->intr_status |= (I2CD_INTR_TX_NAK | I2CD_INTR_ABNORMAL); i2c_end_transfer(bus->bus); } else { bus->intr_status |= I2CD_INTR_TX_ACK; } + bus->cmd &= ~I2CD_M_TX_CMD; + } - } else if (bus->cmd & I2CD_M_RX_CMD) { + if (bus->cmd & I2CD_M_RX_CMD) { int ret = i2c_recv(bus->bus); if (ret < 0) { qemu_log_mask(LOG_GUEST_ERROR, "%s: read failed\n", __func__); @@ -199,6 +212,7 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) bus->intr_status |= I2CD_INTR_RX_DONE; } bus->buf = (ret & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT; + bus->cmd &= ~I2CD_M_RX_CMD; } if (bus->cmd & (I2CD_M_STOP_CMD | I2CD_M_S_RX_CMD_LAST)) { @@ -208,11 +222,8 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) i2c_end_transfer(bus->bus); bus->intr_status |= I2CD_INTR_NORMAL_STOP; } + bus->cmd &= ~I2CD_M_STOP_CMD; } - - /* command is handled, reset it and check for interrupts */ - bus->cmd &= ~0xFFFF; - aspeed_i2c_bus_raise_interrupt(bus); } static void aspeed_i2c_bus_write(void *opaque, hwaddr offset, @@ -262,6 +273,7 @@ static void aspeed_i2c_bus_write(void *opaque, hwaddr offset, } aspeed_i2c_bus_handle_cmd(bus, value); + aspeed_i2c_bus_raise_interrupt(bus); break; default: From patchwork Thu Jun 1 17:10:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 100968 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp863082obc; Thu, 1 Jun 2017 10:25:49 -0700 (PDT) X-Received: by 10.237.37.154 with SMTP id x26mr3455153qtc.133.1496337949877; Thu, 01 Jun 2017 10:25:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496337949; cv=none; d=google.com; s=arc-20160816; b=Y/XVuLi5R+gDmIvOUD0bsy78cJto1BNnmYqp6Old4JNbV+JhN86cJtXWEtHbfSDeMZ JK9H8vb9T7BEtq6eUsouVTo7On7XWOddi9EZ/UF++PgRT4Ma3aJNwuuKgKUqQDMObyXt KNM+RCCJjMwcDajCsYEp/6r6TkoRNAku74GF2f0JRdwEna77AtmOixrgr9bo0HY/50DJ WI4TyuhILEqdfZuOTcyyTI9CoGn4wqAT9cV9ntCUGZY8O5BYGHO31diQnAKrm8cQ/XOA 6821n2HrJuz+LsJxIjak/VwoxsYhmCtGaKMCaqdKS2zChAadA/QhuHZbjYbTeDDzY0yo Wz7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=eFTYRxpHhl8j5V220QQEPJbcZhu0Beh/1v5CI/z7VK8=; b=E7QFrRIrcARUPmeb9gMPVyxBz4pNvNuX5e5kBZB1VKStpwc5a0uvvv6IU3A8cCios5 UMiLXfPe7LgcZTeyw0vwINtXpAhFd/75FhhoOHLa0hDk/slHc7PR4scW22bCz3fP1KqA zvJnvMmBVhW5zJ0jFBRMhiSEZUF3RENmQw8n2TQv/hI4i3BMsp9+uxKWMwg7Q2JBszqi 2S7ztVFx4EnonZVL7fYofUvLkh9QgO14wQpHLHJlPvT99P5tMNGIwB4okch/TDxDItCp fDK71tRHQk1MnM5G+WfVyAw5T1PyXER7ULMjlTOL8Sp4in8Hup3fDG0O5akMmgrIdksx RaKg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id r21si20238159qtb.114.2017.06.01.10.25.49 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Jun 2017 10:25:49 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45865 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTr1-00064T-0t for patch@linaro.org; Thu, 01 Jun 2017 13:25:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35304) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTca-00018e-NJ for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGTcZ-0006Eu-OT for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:52 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37149) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTcZ-0006DU-Hr for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:51 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTcY-0007UB-Jr for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:50 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:29 +0100 Message-Id: <1496337035-30213-22-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 21/27] aspeed/i2c: handle LAST command under the RX command X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater Today, the LAST command is handled with the STOP command but this is incorrect. Also nack the I2C bus when a LAST is issued. Signed-off-by: Cédric Le Goater Message-id: 1494827476-1487-3-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell --- hw/i2c/aspeed_i2c.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) -- 2.7.4 diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index 56a4fdf..67004c6 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -203,7 +203,7 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) bus->cmd &= ~I2CD_M_TX_CMD; } - if (bus->cmd & I2CD_M_RX_CMD) { + if (bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST)) { int ret = i2c_recv(bus->bus); if (ret < 0) { qemu_log_mask(LOG_GUEST_ERROR, "%s: read failed\n", __func__); @@ -212,10 +212,13 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) bus->intr_status |= I2CD_INTR_RX_DONE; } bus->buf = (ret & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT; - bus->cmd &= ~I2CD_M_RX_CMD; + if (bus->cmd & I2CD_M_S_RX_CMD_LAST) { + i2c_nack(bus->bus); + } + bus->cmd &= ~(I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST); } - if (bus->cmd & (I2CD_M_STOP_CMD | I2CD_M_S_RX_CMD_LAST)) { + if (bus->cmd & I2CD_M_STOP_CMD) { if (!i2c_bus_busy(bus->bus)) { bus->intr_status |= I2CD_INTR_ABNORMAL; } else { From patchwork Thu Jun 1 17:10:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 100975 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp864917obc; Thu, 1 Jun 2017 10:30:32 -0700 (PDT) X-Received: by 10.55.69.72 with SMTP id s69mr3191566qka.175.1496338232623; Thu, 01 Jun 2017 10:30:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496338232; cv=none; d=google.com; s=arc-20160816; b=ICaabA/72yEJnlL2PnKmhv+CNN9vQDQacVJXU+Xuk8kyh2LSV4LpshjGBPqEoSZOWj i/esPbMbXmUCkMkHV7vMgSQV/zjW6rmDSYQfHAa9vpmanS4zwfNN/BzMOFYXmH4curKz TPBgMiBkbuCJgNpQRtlAH1IWGtM4m3x3azKDuKNBYGQRRRCmztcUutzzZfNS2go8yH+0 17tDtfRiR+o4XaCNiSkBwN84Qrd6TmN3shRRMyX7oFVkzd8C7B+LdZ/oGxx1FubTYtPb nEtoaRZevf2WZIgctU8/cA1yrj5jQgRSQq1Kjr7sh/uGiCdQ6A760wl/CXYosJO2oe5k 4xSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=QbFijTpPk6a+TYPzS7Ej7dgMn2yS6FJoK1L2zQWcvn4=; b=bEupFVDk3PhRej1m8HQzI1XTfmfKvdvDYdWQ+8qUMwLchGNKL5WB9xCxjqM4od+eW4 YYiDpd9m+ydFimfQs0F6Lp87NDbnUEvyL+pLUEdqPNr8E8bqIcLqlzHM19cKAIJxU8lB 3/wAaJpecYWlm+qV4Ahr6rzinhY0h2E+etmQjZf4dZzatT0B+0WkhQ6fVvDZvxuj6S4Z FbmKhRZZPvUf1cp4/us01UU8Lc57hk8bHv0lQwgwbHHGQ/UlaDgkNV1+hBNHlxkvDLDw rRHs3WSnyg4MjwzHGhDVhGCNKID45k4QnLLcJmYPi/wGNQa+mj4n4zT8k/vPsukPjTXb /Jew== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 15si6297835qku.15.2017.06.01.10.30.32 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Jun 2017 10:30:32 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45888 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTvZ-0002Pj-TC for patch@linaro.org; Thu, 01 Jun 2017 13:30:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35346) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTcc-0001Af-2D for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGTca-0006Fc-Ng for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:53 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37149) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTca-0006DU-E9 for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:52 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTcZ-0007UQ-9E for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:51 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:30 +0100 Message-Id: <1496337035-30213-23-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 22/27] aspeed/i2c: introduce a state machine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater The Aspeed I2C controller maintains a state machine in the command register, which is mostly used for debug. Let's start adding a few states to handle abnormal STOP commands. Today, the model uses the busy status of the bus as a condition to do so but it is not precise enough. Also remove the ABNORMAL bit for failing TX commands. This is incorrect with respect to the specs. Signed-off-by: Cédric Le Goater Message-id: 1494827476-1487-4-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell --- hw/i2c/aspeed_i2c.c | 36 +++++++++++++++++++++++++++++++++--- 1 file changed, 33 insertions(+), 3 deletions(-) -- 2.7.4 diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index 67004c6..c762c73 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -169,6 +169,21 @@ static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset, } } +static void aspeed_i2c_set_state(AspeedI2CBus *bus, uint8_t state) +{ + bus->cmd &= ~(I2CD_TX_STATE_MASK << I2CD_TX_STATE_SHIFT); + bus->cmd |= (state & I2CD_TX_STATE_MASK) << I2CD_TX_STATE_SHIFT; +} + +static uint8_t aspeed_i2c_get_state(AspeedI2CBus *bus) +{ + return (bus->cmd >> I2CD_TX_STATE_SHIFT) & I2CD_TX_STATE_MASK; +} + +/* + * The state machine needs some refinement. It is only used to track + * invalid STOP commands for the moment. + */ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) { bus->cmd &= ~0xFFFF; @@ -176,6 +191,11 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) bus->intr_status = 0; if (bus->cmd & I2CD_M_START_CMD) { + uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ? + I2CD_MSTARTR : I2CD_MSTART; + + aspeed_i2c_set_state(bus, state); + if (i2c_start_transfer(bus->bus, extract32(bus->buf, 1, 7), extract32(bus->buf, 0, 1))) { bus->intr_status |= I2CD_INTR_TX_NAK; @@ -191,20 +211,26 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) if (!i2c_bus_busy(bus->bus)) { return; } + aspeed_i2c_set_state(bus, I2CD_MACTIVE); } if (bus->cmd & I2CD_M_TX_CMD) { + aspeed_i2c_set_state(bus, I2CD_MTXD); if (i2c_send(bus->bus, bus->buf)) { - bus->intr_status |= (I2CD_INTR_TX_NAK | I2CD_INTR_ABNORMAL); + bus->intr_status |= (I2CD_INTR_TX_NAK); i2c_end_transfer(bus->bus); } else { bus->intr_status |= I2CD_INTR_TX_ACK; } bus->cmd &= ~I2CD_M_TX_CMD; + aspeed_i2c_set_state(bus, I2CD_MACTIVE); } if (bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST)) { - int ret = i2c_recv(bus->bus); + int ret; + + aspeed_i2c_set_state(bus, I2CD_MRXD); + ret = i2c_recv(bus->bus); if (ret < 0) { qemu_log_mask(LOG_GUEST_ERROR, "%s: read failed\n", __func__); ret = 0xff; @@ -216,16 +242,20 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) i2c_nack(bus->bus); } bus->cmd &= ~(I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST); + aspeed_i2c_set_state(bus, I2CD_MACTIVE); } if (bus->cmd & I2CD_M_STOP_CMD) { - if (!i2c_bus_busy(bus->bus)) { + if (!(aspeed_i2c_get_state(bus) & I2CD_MACTIVE)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: abnormal stop\n", __func__); bus->intr_status |= I2CD_INTR_ABNORMAL; } else { + aspeed_i2c_set_state(bus, I2CD_MSTOP); i2c_end_transfer(bus->bus); bus->intr_status |= I2CD_INTR_NORMAL_STOP; } bus->cmd &= ~I2CD_M_STOP_CMD; + aspeed_i2c_set_state(bus, I2CD_IDLE); } } From patchwork Thu Jun 1 17:10:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 100964 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp861405obc; Thu, 1 Jun 2017 10:21:49 -0700 (PDT) X-Received: by 10.200.58.130 with SMTP id x2mr3302441qte.110.1496337709860; Thu, 01 Jun 2017 10:21:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496337709; cv=none; d=google.com; s=arc-20160816; b=0kB6sijmrexlAuVnvpWUcwBFR758TpAmqgB1wvEytoDc/wer2CvUSNIIdr4ZroEYUG oGAgntTqTu7Km+wKurEWSwsShD8uPkaQ3rq5Whd9qS/5pjtyHj5X5kBaX+iAO6kuKh5p 0125AKCGL7akzS93JvJRJLUwl06gn4op2WajHpifUlc3c7zndayfxYApEATCtG26QAzc qx/QGV1U1fXYJzYTx/Yd0xjBX2UsHWDPGKi02LLqt8KdwpqwtiRlysegfa0dq6UthTCk ibFyKASoJq0E//rUbIMW21uADlAczBcQT+ZKrD8Ncd2FgUo8qQ74luiHgfQstnZR5Mtq 3tEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=N39leYXVFaTQkXPWSdl+OUj0DLKoCy+XkRR/dpHgseE=; b=mmnRxXuxXiCZpORGlMq6ErJMrCdirVqkA93rn4VU3DD47iKwsupnDgmNHAE1Klon2w YpUUAQzWw4UQEuSMUhxU5qqJAu6zeFySN2e/+7sxXtGpZxbcijfAIpXn8lFfxd+BxG2N SJqFZE8rSFAaCe2Saxr29xUjCsbARR5GVvNuRZ9Pj/fUNpItYejIeiZ5JmnJcLnb8/3p FpUBPH0MQyUZ/AerFW8LRPRH91t8a4WBqGxY1diHKTbT1WW8w1Sa3we1V352tYM+4mwu /rdiJF75AIJH3Fxq95C3sa89t1XBML5H4lX5rzt5Qx5PO5sIvFyngNFmmcGl5Gt3mp0p P5bA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id b205si3933758qkg.149.2017.06.01.10.21.49 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Jun 2017 10:21:49 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45847 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTn9-0002GA-7K for patch@linaro.org; Thu, 01 Jun 2017 13:21:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35354) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTcc-0001B8-CI for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGTcb-0006Fq-2L for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:54 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37150) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTca-0006F8-RW for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:53 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTcZ-0007Up-SW for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:51 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:31 +0100 Message-Id: <1496337035-30213-24-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 23/27] aspeed: add some I2C devices to the Aspeed machines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater Let's add an RTC to the palmetto BMC and a LM75 temperature sensor to the AST2500 EVB to start with. Signed-off-by: Cédric Le Goater Message-id: 1494827476-1487-5-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell Reviewed-by: Peter Maydell --- hw/arm/aspeed.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) -- 2.7.4 diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 283c038..e824ea8 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -39,6 +39,7 @@ typedef struct AspeedBoardConfig { const char *fmc_model; const char *spi_model; uint32_t num_cs; + void (*i2c_init)(AspeedBoardState *bmc); } AspeedBoardConfig; enum { @@ -82,6 +83,9 @@ enum { SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) +static void palmetto_bmc_i2c_init(AspeedBoardState *bmc); +static void ast2500_evb_i2c_init(AspeedBoardState *bmc); + static const AspeedBoardConfig aspeed_boards[] = { [PALMETTO_BMC] = { .soc_name = "ast2400-a1", @@ -89,6 +93,7 @@ static const AspeedBoardConfig aspeed_boards[] = { .fmc_model = "n25q256a", .spi_model = "mx25l25635e", .num_cs = 1, + .i2c_init = palmetto_bmc_i2c_init, }, [AST2500_EVB] = { .soc_name = "ast2500-a1", @@ -96,6 +101,7 @@ static const AspeedBoardConfig aspeed_boards[] = { .fmc_model = "n25q256a", .spi_model = "mx25l25635e", .num_cs = 1, + .i2c_init = ast2500_evb_i2c_init, }, [ROMULUS_BMC] = { .soc_name = "ast2500-a1", @@ -223,9 +229,22 @@ static void aspeed_board_init(MachineState *machine, aspeed_board_binfo.ram_size = ram_size; aspeed_board_binfo.loader_start = sc->info->sdram_base; + if (cfg->i2c_init) { + cfg->i2c_init(bmc); + } + arm_load_kernel(ARM_CPU(first_cpu), &aspeed_board_binfo); } +static void palmetto_bmc_i2c_init(AspeedBoardState *bmc) +{ + AspeedSoCState *soc = &bmc->soc; + + /* The palmetto platform expects a ds3231 RTC but a ds1338 is + * enough to provide basic RTC features. Alarms will be missing */ + i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68); +} + static void palmetto_bmc_init(MachineState *machine) { aspeed_board_init(machine, &aspeed_boards[PALMETTO_BMC]); @@ -250,6 +269,14 @@ static const TypeInfo palmetto_bmc_type = { .class_init = palmetto_bmc_class_init, }; +static void ast2500_evb_i2c_init(AspeedBoardState *bmc) +{ + AspeedSoCState *soc = &bmc->soc; + + /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ + i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "tmp105", 0x4d); +} + static void ast2500_evb_init(MachineState *machine) { aspeed_board_init(machine, &aspeed_boards[AST2500_EVB]); From patchwork Thu Jun 1 17:10:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 100973 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp864440obc; Thu, 1 Jun 2017 10:29:32 -0700 (PDT) X-Received: by 10.200.54.188 with SMTP id a57mr3540325qtc.66.1496338172234; Thu, 01 Jun 2017 10:29:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496338172; cv=none; d=google.com; s=arc-20160816; b=gxAtcQcuInyhH7FsdjahiQpU5FS2z46sD8VgKcIbS7IHxFcOTAugDkApzh85V9R+U2 7FYyL34fGDkfE+tDilOf5HAv11wSQGpu2H3fzSEe0TMxI4ZCdTfecLkbC/N8M3P4EvVj MIsgVVc5nfmeeZbJpB3AwaCCexXabyYmE3UQDWiWRb8tL2nmbYweZCq+fPPOMXcs/geF 2ATO7I4+611uZ/TgY0qskCIT/if1GkCu5gFK7rtT9/U4NiWt5BSr91s109TcSCgqgw+x 1UoWg1kl4FE4sHF73/Np/gxbCYM/w35A3B7aQvJ3Z4olomVh00SUfEqqAV+9ak+W4PlA BIXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=set+hx0TJmW6VqTSSTGezGVoVM5y6vvHHnupPUWCHuw=; b=Auuagqvm1GgiakiACg8MYdHNFDz3EVwvflzHdm6KivWu3sLA8ibuvSWpe3RdwrNprS yKFTpv0wHc5AfXcwvoUM6BXf1/4RYOs/rGz5NOUGfhT3AaDqSlbkAby2ZD1A35QBRjdy teSNlDyaqqfF17yuOTiWIGukRdkvg89TZNL1mCwneSLId7X+nvBJm/mECH47gpt6TUQF HP+PbE6mgBBYAqN+GhXTIjEcwzYX6oE3YlcUpPY28em2JuOU17nJjkqsq9vsJsBC7pVZ za+F9fKo659KMeL9sgbUDx/9yJEvyuXOz/GwmoM4v1a27wG70XWvb6a/fG0TRFOIcgkU IBXA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id o191si14829819qke.59.2017.06.01.10.29.31 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Jun 2017 10:29:32 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45879 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTua-0001CA-TO for patch@linaro.org; Thu, 01 Jun 2017 13:29:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35398) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTce-0001Dl-NY for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGTcc-0006Hc-H0 for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:56 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37150) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTcb-0006F8-VK for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:54 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTca-0007V5-LX for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:52 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:32 +0100 Message-Id: <1496337035-30213-25-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 24/27] hw/misc: add a TMP42{1, 2, 3} device model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater Largely inspired by the TMP105 temperature sensor, here is a model for the TMP42{1,2,3} temperature sensors. Specs can be found here : http://www.ti.com/lit/gpn/tmp421 Signed-off-by: Cédric Le Goater Message-id: 1494827476-1487-6-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell Reviewed-by: Peter Maydell --- hw/misc/Makefile.objs | 1 + hw/misc/tmp421.c | 401 ++++++++++++++++++++++++++++++++++++++++ default-configs/arm-softmmu.mak | 1 + 3 files changed, 403 insertions(+) create mode 100644 hw/misc/tmp421.c -- 2.7.4 diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index c8b4893..2019846 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -1,6 +1,7 @@ common-obj-$(CONFIG_APPLESMC) += applesmc.o common-obj-$(CONFIG_MAX111X) += max111x.o common-obj-$(CONFIG_TMP105) += tmp105.o +common-obj-$(CONFIG_TMP421) += tmp421.o common-obj-$(CONFIG_ISA_DEBUG) += debugexit.o common-obj-$(CONFIG_SGA) += sga.o common-obj-$(CONFIG_ISA_TESTDEV) += pc-testdev.o diff --git a/hw/misc/tmp421.c b/hw/misc/tmp421.c new file mode 100644 index 0000000..a57cf93 --- /dev/null +++ b/hw/misc/tmp421.c @@ -0,0 +1,401 @@ +/* + * Texas Instruments TMP421 temperature sensor. + * + * Copyright (c) 2016 IBM Corporation. + * + * Largely inspired by : + * + * Texas Instruments TMP105 temperature sensor. + * + * Copyright (C) 2008 Nokia Corporation + * Written by Andrzej Zaborowski + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 or + * (at your option) version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "hw/hw.h" +#include "hw/i2c/i2c.h" +#include "qapi/error.h" +#include "qapi/visitor.h" + +/* Manufacturer / Device ID's */ +#define TMP421_MANUFACTURER_ID 0x55 +#define TMP421_DEVICE_ID 0x21 +#define TMP422_DEVICE_ID 0x22 +#define TMP423_DEVICE_ID 0x23 + +typedef struct DeviceInfo { + int model; + const char *name; +} DeviceInfo; + +static const DeviceInfo devices[] = { + { TMP421_DEVICE_ID, "tmp421" }, + { TMP422_DEVICE_ID, "tmp422" }, + { TMP423_DEVICE_ID, "tmp423" }, +}; + +typedef struct TMP421State { + /*< private >*/ + I2CSlave i2c; + /*< public >*/ + + int16_t temperature[4]; + + uint8_t status; + uint8_t config[2]; + uint8_t rate; + + uint8_t len; + uint8_t buf[2]; + uint8_t pointer; + +} TMP421State; + +typedef struct TMP421Class { + I2CSlaveClass parent_class; + DeviceInfo *dev; +} TMP421Class; + +#define TYPE_TMP421 "tmp421-generic" +#define TMP421(obj) OBJECT_CHECK(TMP421State, (obj), TYPE_TMP421) + +#define TMP421_CLASS(klass) \ + OBJECT_CLASS_CHECK(TMP421Class, (klass), TYPE_TMP421) +#define TMP421_GET_CLASS(obj) \ + OBJECT_GET_CLASS(TMP421Class, (obj), TYPE_TMP421) + +/* the TMP421 registers */ +#define TMP421_STATUS_REG 0x08 +#define TMP421_STATUS_BUSY (1 << 7) +#define TMP421_CONFIG_REG_1 0x09 +#define TMP421_CONFIG_RANGE (1 << 2) +#define TMP421_CONFIG_SHUTDOWN (1 << 6) +#define TMP421_CONFIG_REG_2 0x0A +#define TMP421_CONFIG_RC (1 << 2) +#define TMP421_CONFIG_LEN (1 << 3) +#define TMP421_CONFIG_REN (1 << 4) +#define TMP421_CONFIG_REN2 (1 << 5) +#define TMP421_CONFIG_REN3 (1 << 6) + +#define TMP421_CONVERSION_RATE_REG 0x0B +#define TMP421_ONE_SHOT 0x0F + +#define TMP421_RESET 0xFC +#define TMP421_MANUFACTURER_ID_REG 0xFE +#define TMP421_DEVICE_ID_REG 0xFF + +#define TMP421_TEMP_MSB0 0x00 +#define TMP421_TEMP_MSB1 0x01 +#define TMP421_TEMP_MSB2 0x02 +#define TMP421_TEMP_MSB3 0x03 +#define TMP421_TEMP_LSB0 0x10 +#define TMP421_TEMP_LSB1 0x11 +#define TMP421_TEMP_LSB2 0x12 +#define TMP421_TEMP_LSB3 0x13 + +static const int32_t mins[2] = { -40000, -55000 }; +static const int32_t maxs[2] = { 127000, 150000 }; + +static void tmp421_get_temperature(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + TMP421State *s = TMP421(obj); + bool ext_range = (s->config[0] & TMP421_CONFIG_RANGE); + int offset = ext_range * 64 * 256; + int64_t value; + int tempid; + + if (sscanf(name, "temperature%d", &tempid) != 1) { + error_setg(errp, "error reading %s: %m", name); + return; + } + + if (tempid >= 4 || tempid < 0) { + error_setg(errp, "error reading %s", name); + return; + } + + value = ((s->temperature[tempid] - offset) * 1000 + 128) / 256; + + visit_type_int(v, name, &value, errp); +} + +/* Units are 0.001 centigrades relative to 0 C. s->temperature is 8.8 + * fixed point, so units are 1/256 centigrades. A simple ratio will do. + */ +static void tmp421_set_temperature(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + TMP421State *s = TMP421(obj); + Error *local_err = NULL; + int64_t temp; + bool ext_range = (s->config[0] & TMP421_CONFIG_RANGE); + int offset = ext_range * 64 * 256; + int tempid; + + visit_type_int(v, name, &temp, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + if (temp >= maxs[ext_range] || temp < mins[ext_range]) { + error_setg(errp, "value %" PRId64 ".%03" PRIu64 " °C is out of range", + temp / 1000, temp % 1000); + return; + } + + if (sscanf(name, "temperature%d", &tempid) != 1) { + error_setg(errp, "error reading %s: %m", name); + return; + } + + if (tempid >= 4 || tempid < 0) { + error_setg(errp, "error reading %s", name); + return; + } + + s->temperature[tempid] = (int16_t) ((temp * 256 - 128) / 1000) + offset; +} + +static void tmp421_read(TMP421State *s) +{ + TMP421Class *sc = TMP421_GET_CLASS(s); + + s->len = 0; + + switch (s->pointer) { + case TMP421_MANUFACTURER_ID_REG: + s->buf[s->len++] = TMP421_MANUFACTURER_ID; + break; + case TMP421_DEVICE_ID_REG: + s->buf[s->len++] = sc->dev->model; + break; + case TMP421_CONFIG_REG_1: + s->buf[s->len++] = s->config[0]; + break; + case TMP421_CONFIG_REG_2: + s->buf[s->len++] = s->config[1]; + break; + case TMP421_CONVERSION_RATE_REG: + s->buf[s->len++] = s->rate; + break; + case TMP421_STATUS_REG: + s->buf[s->len++] = s->status; + break; + + /* FIXME: check for channel enablement in config registers */ + case TMP421_TEMP_MSB0: + s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 8); + s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 0) & 0xf0; + break; + case TMP421_TEMP_MSB1: + s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 8); + s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 0) & 0xf0; + break; + case TMP421_TEMP_MSB2: + s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 8); + s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 0) & 0xf0; + break; + case TMP421_TEMP_MSB3: + s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 8); + s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 0) & 0xf0; + break; + case TMP421_TEMP_LSB0: + s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 0) & 0xf0; + break; + case TMP421_TEMP_LSB1: + s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 0) & 0xf0; + break; + case TMP421_TEMP_LSB2: + s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 0) & 0xf0; + break; + case TMP421_TEMP_LSB3: + s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 0) & 0xf0; + break; + } +} + +static void tmp421_reset(I2CSlave *i2c); + +static void tmp421_write(TMP421State *s) +{ + switch (s->pointer) { + case TMP421_CONVERSION_RATE_REG: + s->rate = s->buf[0]; + break; + case TMP421_CONFIG_REG_1: + s->config[0] = s->buf[0]; + break; + case TMP421_CONFIG_REG_2: + s->config[1] = s->buf[0]; + break; + case TMP421_RESET: + tmp421_reset(I2C_SLAVE(s)); + break; + } +} + +static int tmp421_rx(I2CSlave *i2c) +{ + TMP421State *s = TMP421(i2c); + + if (s->len < 2) { + return s->buf[s->len++]; + } else { + return 0xff; + } +} + +static int tmp421_tx(I2CSlave *i2c, uint8_t data) +{ + TMP421State *s = TMP421(i2c); + + if (s->len == 0) { + /* first byte is the register pointer for a read or write + * operation */ + s->pointer = data; + s->len++; + } else if (s->len == 1) { + /* second byte is the data to write. The device only supports + * one byte writes */ + s->buf[0] = data; + tmp421_write(s); + } + + return 0; +} + +static int tmp421_event(I2CSlave *i2c, enum i2c_event event) +{ + TMP421State *s = TMP421(i2c); + + if (event == I2C_START_RECV) { + tmp421_read(s); + } + + s->len = 0; + return 0; +} + +static const VMStateDescription vmstate_tmp421 = { + .name = "TMP421", + .version_id = 0, + .minimum_version_id = 0, + .fields = (VMStateField[]) { + VMSTATE_UINT8(len, TMP421State), + VMSTATE_UINT8_ARRAY(buf, TMP421State, 2), + VMSTATE_UINT8(pointer, TMP421State), + VMSTATE_UINT8_ARRAY(config, TMP421State, 2), + VMSTATE_UINT8(status, TMP421State), + VMSTATE_UINT8(rate, TMP421State), + VMSTATE_INT16_ARRAY(temperature, TMP421State, 4), + VMSTATE_I2C_SLAVE(i2c, TMP421State), + VMSTATE_END_OF_LIST() + } +}; + +static void tmp421_reset(I2CSlave *i2c) +{ + TMP421State *s = TMP421(i2c); + TMP421Class *sc = TMP421_GET_CLASS(s); + + memset(s->temperature, 0, sizeof(s->temperature)); + s->pointer = 0; + + s->config[0] = 0; /* TMP421_CONFIG_RANGE */ + + /* resistance correction and channel enablement */ + switch (sc->dev->model) { + case TMP421_DEVICE_ID: + s->config[1] = 0x1c; + break; + case TMP422_DEVICE_ID: + s->config[1] = 0x3c; + break; + case TMP423_DEVICE_ID: + s->config[1] = 0x7c; + break; + } + + s->rate = 0x7; /* 8Hz */ + s->status = 0; +} + +static int tmp421_init(I2CSlave *i2c) +{ + TMP421State *s = TMP421(i2c); + + tmp421_reset(&s->i2c); + + return 0; +} + +static void tmp421_initfn(Object *obj) +{ + object_property_add(obj, "temperature0", "int", + tmp421_get_temperature, + tmp421_set_temperature, NULL, NULL, NULL); + object_property_add(obj, "temperature1", "int", + tmp421_get_temperature, + tmp421_set_temperature, NULL, NULL, NULL); + object_property_add(obj, "temperature2", "int", + tmp421_get_temperature, + tmp421_set_temperature, NULL, NULL, NULL); + object_property_add(obj, "temperature3", "int", + tmp421_get_temperature, + tmp421_set_temperature, NULL, NULL, NULL); +} + +static void tmp421_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); + TMP421Class *sc = TMP421_CLASS(klass); + + k->init = tmp421_init; + k->event = tmp421_event; + k->recv = tmp421_rx; + k->send = tmp421_tx; + dc->vmsd = &vmstate_tmp421; + sc->dev = (DeviceInfo *) data; +} + +static const TypeInfo tmp421_info = { + .name = TYPE_TMP421, + .parent = TYPE_I2C_SLAVE, + .instance_size = sizeof(TMP421State), + .instance_init = tmp421_initfn, + .class_init = tmp421_class_init, +}; + +static void tmp421_register_types(void) +{ + int i; + + type_register_static(&tmp421_info); + for (i = 0; i < ARRAY_SIZE(devices); ++i) { + TypeInfo ti = { + .name = devices[i].name, + .parent = TYPE_TMP421, + .class_init = tmp421_class_init, + .class_data = (void *) &devices[i], + }; + type_register(&ti); + } +} + +type_init(tmp421_register_types) diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index 78d7af0..93e995d 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -15,6 +15,7 @@ CONFIG_TWL92230=y CONFIG_TSC2005=y CONFIG_LM832X=y CONFIG_TMP105=y +CONFIG_TMP421=y CONFIG_STELLARIS=y CONFIG_STELLARIS_INPUT=y CONFIG_STELLARIS_ENET=y From patchwork Thu Jun 1 17:10:33 2017 Content-Type: text/plain; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id b126si18539018qkf.16.2017.06.01.10.29.19 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Jun 2017 10:29:19 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45880 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTuP-0001Cl-5N for patch@linaro.org; Thu, 01 Jun 2017 13:29:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35371) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTcd-0001CI-Af for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGTcc-0006Hn-Ji for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:55 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37151) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTcc-0006Gg-C5 for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:54 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTcb-0007VY-Au for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:53 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:33 +0100 Message-Id: <1496337035-30213-26-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 25/27] aspeed: add a temp sensor device on I2C bus 3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater Temperatures can be changed from the monitor with : (qemu) qom-set /machine/unattached/device[2] temperature0 12000 Signed-off-by: Cédric Le Goater Message-id: 1494827476-1487-7-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell Reviewed-by: Peter Maydell --- hw/arm/aspeed.c | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.7.4 diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index e824ea8..155eeb2 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -239,10 +239,19 @@ static void aspeed_board_init(MachineState *machine, static void palmetto_bmc_i2c_init(AspeedBoardState *bmc) { AspeedSoCState *soc = &bmc->soc; + DeviceState *dev; /* The palmetto platform expects a ds3231 RTC but a ds1338 is * enough to provide basic RTC features. Alarms will be missing */ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68); + + /* add a TMP423 temperature sensor */ + dev = i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2), + "tmp423", 0x4c); + object_property_set_int(OBJECT(dev), 31000, "temperature0", &error_abort); + object_property_set_int(OBJECT(dev), 28000, "temperature1", &error_abort); + object_property_set_int(OBJECT(dev), 20000, "temperature2", &error_abort); + object_property_set_int(OBJECT(dev), 110000, "temperature3", &error_abort); } static void palmetto_bmc_init(MachineState *machine) From patchwork Thu Jun 1 17:10:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 100974 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp864900obc; Thu, 1 Jun 2017 10:30:31 -0700 (PDT) X-Received: by 10.237.54.10 with SMTP id e10mr3531000qtb.51.1496338231078; Thu, 01 Jun 2017 10:30:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496338230; cv=none; d=google.com; s=arc-20160816; b=sNQ7ffJHxInMpjRNUgfY187ivg70rPGUTTM0vKWgtXCl/89CaHlDo3hYdMWlrTWPoL 9QO3J4cFpQj5BD3iesZlh4AEfWZRdIhM6fBnzQp38gl7jABPOR1JTsATEwTe4WSJFBhB 0YFoJDNoSPyoDXZnewN/Gm38xWE58LxvrJVIG4XhAd6k3S5nLOHNYBkI1gVC4dZqFvCW 4gSl5+Jz14gIXuKuk+UfBw9dykppEhnhUEV2uYsFcUVzuVcuy8QyN4yYb5vaO/ME5PxE WFdFuLNolqLhxzNjq7KEw498GkqDHJI6Q9ABlWqgr/6qTCK3ZHHU2lJmQBAG8y9mtQ4R EGwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=9W/yajrQ/dDPDt5Ore5N/MmWlZ8/MZQJcycyuoGDk0Q=; b=Ib0of0qLI+HXBR+3MF5/o/56oHO92BYTgbTIRUTCiRvoSGn5Er+LzBu4ew7v9x3v7q eZ+HPo8//JXMGEuFAgiW6CyUYYnEwLNNty07C4ZCsyTXnEtqelfgCPhc3NGxlv9iH+CZ AsqhkQjbvKZFVwwaOu6beveuU1LDeh6HIf8SEePLEkCnqZEjkEvF7YFyEBtsA15ltOA3 jWgRHd6uZ47K+08Q0WWkfc9bNGjlxKqb6c38bPEzYozxStdhjeug2wMjrhmQdXTSqTyp 5Cj7WesnVQn4zxBl931uVfTkiQyE6/lmRNtGHTjWJVzMeTyNBYpF6cdScgypjGmmNPXk aftA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Thu, 01 Jun 2017 13:10:57 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37150) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTcd-0006F8-8k for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:55 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTcb-0007Vk-UI for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:53 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:34 +0100 Message-Id: <1496337035-30213-27-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 26/27] hw/arm/virt-acpi-build: build SLIT when needed X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Andrew Jones Cc: Shannon Zhao Signed-off-by: Andrew Jones Reviewed-by: Igor Mammedov Reviewed-by: Shannon Zhao Message-id: 20170529173751.3443-2-drjones@redhat.com Signed-off-by: Peter Maydell --- hw/arm/virt-acpi-build.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.7.4 diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index e585206..2079828 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -776,6 +776,10 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) if (nb_numa_nodes > 0) { acpi_add_table(table_offsets, tables_blob); build_srat(tables_blob, tables->linker, vms); + if (have_numa_distance) { + acpi_add_table(table_offsets, tables_blob); + build_slit(tables_blob, tables->linker); + } } if (its_class_name() && !vmc->no_its) { From patchwork Thu Jun 1 17:10:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 100965 Delivered-To: patch@linaro.org Received: by 10.182.202.35 with SMTP id kf3csp861800obc; Thu, 1 Jun 2017 10:22:51 -0700 (PDT) X-Received: by 10.55.143.198 with SMTP id r189mr3041263qkd.150.1496337771915; Thu, 01 Jun 2017 10:22:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496337771; cv=none; d=google.com; s=arc-20160816; b=NPczsua+QfiM16m++T6DG7kTpj2nT5VwkceHfR6FrYin9jJoaThYWOsWwTIvjQZoSV qUYSLkevjeg2lWUEF0LiaN2N4H98ONTpFsaoR7S0rWhEJJAzI3IVnkVaLCfRcMbY3Uqm IO9rSFtoO0tKNFacwu+nSyxnhTm75TfoEsjnuyPGs+kkFyS7ks7tRqbUiNuj3c/ZM3jy w1K8lugXfXt3wlfG7lmMRkher5iNRvaTs0GSYbdpi3RtxY6C/3RVKm6jNJPld5hdPT1+ Q/b4vFBbjN/qNfDwbctOqUkwPcbjJ4wkj3LR35YPQTlPXVy9IAKU7DDtTfE56048zB2i 0IYQ== ARC-Message-Signature: i=1; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id 10si17269415qku.154.2017.06.01.10.22.51 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Jun 2017 10:22:51 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45849 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTo9-0003OS-5a for patch@linaro.org; Thu, 01 Jun 2017 13:22:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35410) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGTcf-0001Ef-FO for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGTce-0006II-Fz for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:57 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37152) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dGTcd-0006Hr-L4 for qemu-devel@nongnu.org; Thu, 01 Jun 2017 13:10:55 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dGTcc-0007W7-KK for qemu-devel@nongnu.org; Thu, 01 Jun 2017 18:10:54 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 18:10:35 +0100 Message-Id: <1496337035-30213-28-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> References: <1496337035-30213-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 27/27] hw/arm/virt: fdt: generate distance-map when needed X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Andrew Jones This is based on patch Shannon Zhao originally posted. Cc: Shannon Zhao Signed-off-by: Andrew Jones Reviewed-by: Shannon Zhao Message-id: 20170529173751.3443-3-drjones@redhat.com Signed-off-by: Peter Maydell --- hw/arm/virt.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) -- 2.7.4 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index c7c8159..4db2d42 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -219,6 +219,27 @@ static void create_fdt(VirtMachineState *vms) "clk24mhz"); qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); + if (have_numa_distance) { + int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); + uint32_t *matrix = g_malloc0(size); + int idx, i, j; + + for (i = 0; i < nb_numa_nodes; i++) { + for (j = 0; j < nb_numa_nodes; j++) { + idx = (i * nb_numa_nodes + j) * 3; + matrix[idx + 0] = cpu_to_be32(i); + matrix[idx + 1] = cpu_to_be32(j); + matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]); + } + } + + qemu_fdt_add_subnode(fdt, "/distance-map"); + qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", + "numa-distance-map-v1"); + qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", + matrix, size); + g_free(matrix); + } } static void fdt_add_psci_node(const VirtMachineState *vms)