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[2603:800c:1201:c600:119c:490c:a4ee:8e8]) by smtp.gmail.com with ESMTPSA id u25-20020a62ed19000000b004f140515d56sm3318043pfh.46.2022.03.03.11.15.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 11:15:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 1/9] tcg: Add TCG_TARGET_SIGNED_ADDR32 Date: Thu, 3 Mar 2022 09:15:43 -1000 Message-Id: <20220303191551.466631-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303191551.466631-1-richard.henderson@linaro.org> References: <20220303191551.466631-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::533 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui , Alistair Francis , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Define as 0 for all tcg hosts. Put this in a separate header, because we'll want this in places that do not ordinarily have access to all of tcg/tcg.h. Reviewed-by: WANG Xuerui Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-sa32.h | 1 + tcg/arm/tcg-target-sa32.h | 1 + tcg/i386/tcg-target-sa32.h | 1 + tcg/loongarch64/tcg-target-sa32.h | 1 + tcg/mips/tcg-target-sa32.h | 1 + tcg/ppc/tcg-target-sa32.h | 1 + tcg/riscv/tcg-target-sa32.h | 1 + tcg/s390x/tcg-target-sa32.h | 1 + tcg/sparc/tcg-target-sa32.h | 1 + tcg/tci/tcg-target-sa32.h | 1 + tcg/tcg.c | 4 ++++ 11 files changed, 14 insertions(+) create mode 100644 tcg/aarch64/tcg-target-sa32.h create mode 100644 tcg/arm/tcg-target-sa32.h create mode 100644 tcg/i386/tcg-target-sa32.h create mode 100644 tcg/loongarch64/tcg-target-sa32.h create mode 100644 tcg/mips/tcg-target-sa32.h create mode 100644 tcg/ppc/tcg-target-sa32.h create mode 100644 tcg/riscv/tcg-target-sa32.h create mode 100644 tcg/s390x/tcg-target-sa32.h create mode 100644 tcg/sparc/tcg-target-sa32.h create mode 100644 tcg/tci/tcg-target-sa32.h diff --git a/tcg/aarch64/tcg-target-sa32.h b/tcg/aarch64/tcg-target-sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/aarch64/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 diff --git a/tcg/arm/tcg-target-sa32.h b/tcg/arm/tcg-target-sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/arm/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 diff --git a/tcg/i386/tcg-target-sa32.h b/tcg/i386/tcg-target-sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/i386/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 diff --git a/tcg/loongarch64/tcg-target-sa32.h b/tcg/loongarch64/tcg-target-sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/loongarch64/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 diff --git a/tcg/mips/tcg-target-sa32.h b/tcg/mips/tcg-target-sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/mips/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 diff --git a/tcg/ppc/tcg-target-sa32.h b/tcg/ppc/tcg-target-sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/ppc/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 diff --git a/tcg/riscv/tcg-target-sa32.h b/tcg/riscv/tcg-target-sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/riscv/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 diff --git a/tcg/s390x/tcg-target-sa32.h b/tcg/s390x/tcg-target-sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/s390x/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 diff --git a/tcg/sparc/tcg-target-sa32.h b/tcg/sparc/tcg-target-sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/sparc/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 diff --git a/tcg/tci/tcg-target-sa32.h b/tcg/tci/tcg-target-sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/tci/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 diff --git a/tcg/tcg.c b/tcg/tcg.c index 33a97eabdb..8c131293fe 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -61,6 +61,10 @@ #include "exec/log.h" #include "tcg/tcg-ldst.h" #include "tcg-internal.h" +#include "tcg-target-sa32.h" + +/* Sanity check for TCG_TARGET_SIGNED_ADDR32. */ +QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS == 32 && TCG_TARGET_SIGNED_ADDR32); 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[2603:800c:1201:c600:119c:490c:a4ee:8e8]) by smtp.gmail.com with ESMTPSA id u25-20020a62ed19000000b004f140515d56sm3318043pfh.46.2022.03.03.11.15.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 11:15:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 2/9] accel/tcg: Split out g2h_tlbe Date: Thu, 3 Mar 2022 09:15:44 -1000 Message-Id: <20220303191551.466631-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303191551.466631-1-richard.henderson@linaro.org> References: <20220303191551.466631-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::52b (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui , Alistair Francis , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a new function to combine a CPUTLBEntry addend with the guest address to form a host address. Reviewed-by: WANG Xuerui Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 3b918fe018..0e62aa5d7c 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -91,6 +91,11 @@ static inline size_t sizeof_tlb(CPUTLBDescFast *fast) return fast->mask + (1 << CPU_TLB_ENTRY_BITS); } +static inline uintptr_t g2h_tlbe(const CPUTLBEntry *tlb, target_ulong gaddr) +{ + return tlb->addend + (uintptr_t)gaddr; +} + static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns, size_t max_entries) { @@ -986,8 +991,7 @@ static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry, if ((addr & (TLB_INVALID_MASK | TLB_MMIO | TLB_DISCARD_WRITE | TLB_NOTDIRTY)) == 0) { - addr &= TARGET_PAGE_MASK; - addr += tlb_entry->addend; + addr = g2h_tlbe(tlb_entry, addr & TARGET_PAGE_MASK); if ((addr - start) < length) { #if TCG_OVERSIZED_GUEST tlb_entry->addr_write |= TLB_NOTDIRTY; @@ -1537,7 +1541,7 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr, return -1; } - p = (void *)((uintptr_t)addr + entry->addend); + p = (void *)g2h_tlbe(entry, addr); if (hostp) { *hostp = p; } @@ -1629,7 +1633,7 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr, } /* Everything else is RAM. */ - *phost = (void *)((uintptr_t)addr + entry->addend); + *phost = (void *)g2h_tlbe(entry, addr); return flags; } @@ -1737,7 +1741,7 @@ bool tlb_plugin_lookup(CPUState *cpu, target_ulong addr, int mmu_idx, data->v.io.offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; } else { data->is_io = false; - data->v.ram.hostaddr = (void *)((uintptr_t)addr + tlbe->addend); + data->v.ram.hostaddr = (void *)g2h_tlbe(tlbe, addr); } return true; } else { @@ -1836,7 +1840,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, goto stop_the_world; } - hostaddr = (void *)((uintptr_t)addr + tlbe->addend); + hostaddr = (void *)g2h_tlbe(tlbe, addr); if (unlikely(tlb_addr & TLB_NOTDIRTY)) { notdirty_write(env_cpu(env), addr, size, @@ -1967,7 +1971,7 @@ load_helper(CPUArchState *env, target_ulong addr, MemOpIdx oi, access_type, op ^ (need_swap * MO_BSWAP)); } - haddr = (void *)((uintptr_t)addr + entry->addend); + haddr = (void *)g2h_tlbe(entry, addr); /* * Keep these two load_memop separate to ensure that the compiler @@ -2004,7 +2008,7 @@ load_helper(CPUArchState *env, target_ulong addr, MemOpIdx oi, return res & MAKE_64BIT_MASK(0, size * 8); } - haddr = (void *)((uintptr_t)addr + entry->addend); + haddr = (void *)g2h_tlbe(entry, addr); return load_memop(haddr, op); } @@ -2375,7 +2379,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, notdirty_write(env_cpu(env), addr, size, iotlbentry, retaddr); } - haddr = (void *)((uintptr_t)addr + entry->addend); + haddr = (void *)g2h_tlbe(entry, addr); /* * Keep these two store_memop separate to ensure that the compiler @@ -2400,7 +2404,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, return; } - haddr = (void *)((uintptr_t)addr + entry->addend); + haddr = (void *)g2h_tlbe(entry, addr); store_memop(haddr, val, op); } From patchwork Thu Mar 3 19:15:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 547799 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:3c7:0:0:0:0 with SMTP id b7csp1181847wrg; Thu, 3 Mar 2022 11:26:13 -0800 (PST) X-Google-Smtp-Source: ABdhPJwCNSIlmRjLo2NJkZC0+0if0UUZaZzHF8Lwc+ZpxcZkqv0WbUNCNTElyAe89867+o3oy7Qr X-Received: by 2002:a81:660a:0:b0:2db:c36a:31a5 with SMTP id a10-20020a81660a000000b002dbc36a31a5mr17508563ywc.470.1646335573200; Thu, 03 Mar 2022 11:26:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646335573; cv=none; d=google.com; s=arc-20160816; b=hED1p4qeZ96oFiDqUNzurGIOhylVUOefHH5TxpAeFAsG+/TH1DYXKahKH/sppohfZy M+TvHnXBLDsnsb4tzlkMLEMaXyRWPv1wCIwDqTBCz7Ih/fL82VFxPbsCpWIeM0oyiZg8 WiVD4T8wRikqJx6z4OiHtrVLw8OtQzIFI9FAeKCt1rdN/0O157P5c4Mhd40KwwMmUNG1 N/w4zToKl/nOoMU9209vkMpolVWXslgcP0WMcJvXZlwqcZ9RhJu225za0arunrH2YeIB aisKbsIhJAwpQ2peAyKbfu4B7uQgYp/eKDFE/+bypKMf5Ws4kUC+HM9Z01Ym5d6j7iC3 PB8Q== ARC-Message-Signature: i=1; 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[2603:800c:1201:c600:119c:490c:a4ee:8e8]) by smtp.gmail.com with ESMTPSA id u25-20020a62ed19000000b004f140515d56sm3318043pfh.46.2022.03.03.11.15.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 11:15:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 3/9] accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu Date: Thu, 3 Mar 2022 09:15:45 -1000 Message-Id: <20220303191551.466631-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303191551.466631-1-richard.henderson@linaro.org> References: <20220303191551.466631-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42b (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When TCG_TARGET_SIGNED_ADDR32 is set, adjust the tlb addend to allow the 32-bit guest address to be sign extended within the 64-bit host register instead of zero extended. This will simplify tcg hosts like MIPS, RISC-V, and LoongArch, which naturally sign-extend 32-bit values, in contrast to x86_64 and AArch64 which zero-extend them. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 0e62aa5d7c..0dbc3efbc7 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -40,6 +40,7 @@ #include "qemu/plugin-memory.h" #endif #include "tcg/tcg-ldst.h" +#include "tcg-target-sa32.h" /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ /* #define DEBUG_TLB */ @@ -93,6 +94,9 @@ static inline size_t sizeof_tlb(CPUTLBDescFast *fast) static inline uintptr_t g2h_tlbe(const CPUTLBEntry *tlb, target_ulong gaddr) { + if (TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS == 32) { + return tlb->addend + (int32_t)gaddr; + } return tlb->addend + (uintptr_t)gaddr; } @@ -1244,7 +1248,13 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, desc->iotlb[index].attrs = attrs; /* Now calculate the new entry */ - tn.addend = addend - vaddr_page; + + if (TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS == 32) { + tn.addend = addend - (int32_t)vaddr_page; + } else { + tn.addend = addend - vaddr_page; + } + if (prot & PAGE_READ) { tn.addr_read = address; if (wp_flags & BP_MEM_READ) { From patchwork Thu Mar 3 19:15:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 547796 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:3c7:0:0:0:0 with SMTP id b7csp1180185wrg; Thu, 3 Mar 2022 11:23:02 -0800 (PST) X-Google-Smtp-Source: ABdhPJySagcjHot6oaKxXPJq0ZZYacleI4Zaz4P4H7rtZKgi78XzubTBzaSvNHoq+V8MkV2OLdtS X-Received: by 2002:a81:f611:0:b0:2cf:aa3c:ab17 with SMTP id w17-20020a81f611000000b002cfaa3cab17mr36446758ywm.410.1646335381925; Thu, 03 Mar 2022 11:23:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646335381; cv=none; d=google.com; s=arc-20160816; b=kG3Vke2o8uiEF7cit3l/yxng0OZPpyV7DTY9Pa+FWR/BRF2m2CCI2VnIrZunsJhmmj 3NlnkP2La72FSa/7Qtfc+lDhwJIjCVROWR/OpnS32iLYW5oRzRJ8f5UTKAXKXcbrUnpU RB8wQMn/0kRrAVP7i6/m2WLjs11dUvfwJtsSubm0sYSDJNNBKT2mKDOg/wXvhs9QCW64 eo0gGHa2B8DlUEmNHNJUFKC6y8lyANUPCUsE63dDw6IOg7M3fqINqJc3UdflbHF8Idig 5WfERJhN8KXvUmzewgmZTeKvJa4rQ+bF+VMCwNfB4P9vPGGqZnNIohjrsc5nmmiaf5pv kMYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vyU1dEICQtRQByu98DNY2ApCIAVgpQWfK9xFqkqxnVc=; b=yOkTuKYrww7pssYN+Ryabt9tIF2CiTR30qTfhihL2yvgkWIJT2XaO1pesnsNEg0WaC 61uEiF2BktHyJY7nQMZoCT+ExutaaRPhYM52ndkncMikyQ3tLOxSeO02GOwTXCELumpy IrSdU7ylFh4TjZZPn9ibCY15mgT7hsXZ9HKCHuVwMTJfPDqGNeC6xhtkD234ZEsjzRhm 5viKgAso0QLuWxduYDE4MLYpJHHp3/CntBHTeAnmNf4i7ejOK/6VhH69S16+QqQOERXN HGCpC9xE8+MgZ8EcrpTN88GUKNtUbQjQrWSXar+TwFpU5lmed8QhTLDniz5W8BgJHnBk DeBw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DJ2qjQDs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2603:800c:1201:c600:119c:490c:a4ee:8e8]) by smtp.gmail.com with ESMTPSA id u25-20020a62ed19000000b004f140515d56sm3318043pfh.46.2022.03.03.11.15.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 11:15:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 4/9] accel/tcg: Add guest_base_signed_addr32 for user-only Date: Thu, 3 Mar 2022 09:15:46 -1000 Message-Id: <20220303191551.466631-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303191551.466631-1-richard.henderson@linaro.org> References: <20220303191551.466631-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::532 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" While the host may prefer to treat 32-bit addresses as signed, there are edge cases of guests that cannot be implemented with addresses 0x7fff_ffff and 0x8000_0000 being non-consecutive. Therefore, default to guest_base_signed_addr32 false, and allow probe_guest_base to determine whether it is possible to set it to true. A tcg backend which sets TCG_TARGET_SIGNED_ADDR32 will have to cope with either setting for user-only. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 16 ++++++++++++++++ include/exec/cpu_ldst.h | 3 ++- bsd-user/main.c | 4 ++++ linux-user/main.c | 3 +++ 4 files changed, 25 insertions(+), 1 deletion(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 84caf5c3d9..26ecd3c886 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -146,6 +146,7 @@ static inline void tswap64s(uint64_t *s) #if defined(CONFIG_USER_ONLY) #include "exec/user/abitypes.h" +#include "tcg-target-sa32.h" /* On some host systems the guest address space is reserved on the host. * This allows the guest address space to be offset to a convenient location. @@ -154,6 +155,21 @@ extern uintptr_t guest_base; extern bool have_guest_base; extern unsigned long reserved_va; +#if TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS == 32 +extern bool guest_base_signed_addr32; +#else +#define guest_base_signed_addr32 false +#endif + +static inline void set_guest_base_signed_addr32(void) +{ +#ifdef guest_base_signed_addr32 + qemu_build_not_reached(); +#else + guest_base_signed_addr32 = true; +#endif +} + /* * Limit the guest addresses as best we can. * diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index da987fe8ad..add45499ee 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -87,7 +87,8 @@ static inline abi_ptr cpu_untagged_addr(CPUState *cs, abi_ptr x) /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ static inline void *g2h_untagged(abi_ptr x) { - return (void *)((uintptr_t)(x) + guest_base); + uintptr_t hx = guest_base_signed_addr32 ? (int32_t)x : (uintptr_t)x; + return (void *)(guest_base + hx); } static inline void *g2h(CPUState *cs, abi_ptr x) diff --git a/bsd-user/main.c b/bsd-user/main.c index 88d347d05e..c181e54495 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -54,6 +54,10 @@ int singlestep; uintptr_t guest_base; bool have_guest_base; +#ifndef guest_base_signed_addr32 +bool guest_base_signed_addr32; +#endif + /* * When running 32-on-64 we should make sure we can fit all of the possible * guest address space into a contiguous chunk of virtual host memory. diff --git a/linux-user/main.c b/linux-user/main.c index fbc9bcfd5f..5d963ddb64 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -72,6 +72,9 @@ static const char *seed_optarg; unsigned long mmap_min_addr; uintptr_t guest_base; bool have_guest_base; +#ifndef guest_base_signed_addr32 +bool guest_base_signed_addr32; +#endif /* * Used to implement backwards-compatibility for the `-strace`, and From patchwork Thu Mar 3 19:15:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 547801 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:3c7:0:0:0:0 with SMTP id b7csp1182250wrg; Thu, 3 Mar 2022 11:26:57 -0800 (PST) X-Google-Smtp-Source: ABdhPJxgRs7rx2NBPjhwJZt7E/L/B/tPPMqAiCfrK0wUS8o8HWe/3l5v2xva7MfU/ofoNXuDl/tb X-Received: by 2002:a81:1d51:0:b0:2ca:73e5:9bd6 with SMTP id d78-20020a811d51000000b002ca73e59bd6mr37579575ywd.490.1646335617688; Thu, 03 Mar 2022 11:26:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646335617; cv=none; d=google.com; s=arc-20160816; b=pB3N5ah2e3daBH4FbtVp5RGYz7Ljru1t1P3E0pu42c767RACj+ff8k1qSFS1QBNPtn wZfzAZBj4r6diFL/lxyr9Z+cdyVaVbabbjq/XBxGdlLQrM/gCo9/+2cz3u2PlGz+hzyW N8gFcOZzWmQq5LUfNgJ8QvqbJ4wGZsS9PTGG7WtbyXbPLnXleN1y1SUA87NjhLnBm1Oq sHB1pUHeAgYuhjNXpRai0cFphtwPZ6ObA7PFpQDvxLIDUH28BhUpuVthYGlxkMeF1zwk 5TQONZlJJoAH64Yb1rMMpuwglUVXauxZfpBFdY4QQDiaobkrca21wybd3E1zhWobzzdY y1fQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=F2bsGcziKKgWIATQyKoWzWtQMllrUtNMWOT4PiIDWxo=; b=Arun3s1q8lBTXHCFKUOOWmQEfsBnmr4zxyqryEalvPo01s4yzMthAtYtpH2/hokk/f nLcvphASpQGVMflCa1QMYgWn7cvai0u43vz3lg/2I4akjAZFI0EGwTcd8ZUMATgAXYgO lOCxHPAIAcrnH7TMdlVqn73atYt7Ucm8KOwwN4XDGjCFJpmURSDl92rVrD5b6lYp4B1q SwaCyV/hkP5DARoAehGJA6R6Yu6BNTWrbYcztj+IO1XQWbqJaOzrlRn/irYTQ2dslsqA yz4zY+p7AUCXmgX6OASSxyXkdp6Wq1aMBKI+V9FgIUYbsj/xCQP3O5t0CwN+dxEo2aU+ aAXg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=La+UZkFG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2603:800c:1201:c600:119c:490c:a4ee:8e8]) by smtp.gmail.com with ESMTPSA id u25-20020a62ed19000000b004f140515d56sm3318043pfh.46.2022.03.03.11.16.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 11:16:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 5/9] linux-user: Support TCG_TARGET_SIGNED_ADDR32 Date: Thu, 3 Mar 2022 09:15:47 -1000 Message-Id: <20220303191551.466631-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303191551.466631-1-richard.henderson@linaro.org> References: <20220303191551.466631-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62b (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When using reserved_va, which is the default for a 64-bit host and a 32-bit guest, set guest_base_signed_addr32 if requested by TCG_TARGET_SIGNED_ADDR32, and the executable layout allows. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 4 --- linux-user/elfload.c | 62 ++++++++++++++++++++++++++++++++++-------- 2 files changed, 50 insertions(+), 16 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 26ecd3c886..8bea0e069e 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -269,11 +269,7 @@ extern const TargetPageBits target_page; #define PAGE_RESET 0x0040 /* For linux-user, indicates that the page is MAP_ANON. */ #define PAGE_ANON 0x0080 - -#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) -/* FIXME: Code that sets/uses this is broken and needs to go away. */ #define PAGE_RESERVED 0x0100 -#endif /* Target-specific bits that will be used via page_get_flags(). */ #define PAGE_TARGET_1 0x0200 #define PAGE_TARGET_2 0x0400 diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 9628a38361..5522f9e721 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -2482,34 +2482,72 @@ static void pgb_dynamic(const char *image_name, long align) static void pgb_reserved_va(const char *image_name, abi_ulong guest_loaddr, abi_ulong guest_hiaddr, long align) { - int flags = MAP_ANONYMOUS | MAP_PRIVATE | MAP_NORESERVE; + int flags = (MAP_ANONYMOUS | MAP_PRIVATE | + MAP_NORESERVE | MAP_FIXED_NOREPLACE); + unsigned long local_rva = reserved_va; + bool protect_wrap = false; void *addr, *test; - if (guest_hiaddr > reserved_va) { + if (guest_hiaddr > local_rva) { error_report("%s: requires more than reserved virtual " "address space (0x%" PRIx64 " > 0x%lx)", - image_name, (uint64_t)guest_hiaddr, reserved_va); + image_name, (uint64_t)guest_hiaddr, local_rva); exit(EXIT_FAILURE); } - /* Widen the "image" to the entire reserved address space. */ - pgb_static(image_name, 0, reserved_va, align); + if (TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS == 32) { + if (guest_loaddr < 0x80000000u && guest_hiaddr > 0x80000000u) { + /* + * The executable itself wraps on signed addresses. + * Without per-page translation, we must keep the + * guest address 0x7fff_ffff adjacent to 0x8000_0000 + * consecutive in host memory: unsigned addresses. + */ + } else { + set_guest_base_signed_addr32(); + if (local_rva <= 0x80000000u) { + /* No guest addresses are "negative": win! */ + } else { + /* Begin by allocating the entire address space. */ + local_rva = 0xfffffffful + 1; + protect_wrap = true; + } + } + } - /* osdep.h defines this as 0 if it's missing */ - flags |= MAP_FIXED_NOREPLACE; + /* Widen the "image" to the entire reserved address space. */ + pgb_static(image_name, 0, local_rva, align); + assert(guest_base != 0); /* Reserve the memory on the host. */ - assert(guest_base != 0); test = g2h_untagged(0); - addr = mmap(test, reserved_va, PROT_NONE, flags, -1, 0); + addr = mmap(test, local_rva, PROT_NONE, flags, -1, 0); if (addr == MAP_FAILED || addr != test) { + /* + * If protect_wrap, we could try again with the original reserved_va + * setting, but the edge case of low ulimit vm setting on a 64-bit + * host is probably useless. + */ error_report("Unable to reserve 0x%lx bytes of virtual address " - "space at %p (%s) for use as guest address space (check your" - "virtual memory ulimit setting, min_mmap_addr or reserve less " - "using -R option)", reserved_va, test, strerror(errno)); + "space at %p (%s) for use as guest address space " + "(check your virtual memory ulimit setting, " + "min_mmap_addr or reserve less using -R option)", + local_rva, test, strerror(errno)); exit(EXIT_FAILURE); } + if (protect_wrap) { + /* + * Prevent the page just before 0x80000000 from being allocated. + * This prevents a single guest object/allocation from crossing + * the signed wrap, and thus being discontiguous in host memory. + */ + page_set_flags(0x7fffffff & TARGET_PAGE_MASK, 0x80000000u, + PAGE_RESERVED); + /* Adjust guest_base so that 0 is in the middle of the reservation. */ + guest_base += 0x80000000ul; + } + qemu_log_mask(CPU_LOG_PAGE, "%s: base @ %p for %lu bytes\n", __func__, addr, reserved_va); } From patchwork Thu Mar 3 19:15:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 547800 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:3c7:0:0:0:0 with SMTP id b7csp1182230wrg; Thu, 3 Mar 2022 11:26:55 -0800 (PST) X-Google-Smtp-Source: ABdhPJzFa2XsDpdwc031Br2511tteW/Ey3X3MiNje192+eWESUl/3xJmC84pPPrbQaTRZFJ4rt1S X-Received: by 2002:a25:2403:0:b0:628:bf37:b517 with SMTP id k3-20020a252403000000b00628bf37b517mr4650205ybk.121.1646335615369; Thu, 03 Mar 2022 11:26:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646335615; cv=none; d=google.com; s=arc-20160816; b=s7WBINBN+AT8pFTfWt2hJG9M5gDIgc3JgPCzrb2RUhJFabAX6EULWlAuMCOMdDQ5Uc tjEbEIjQZs0MZyGPso6HOWFEbSoeEdt9UDHfV3rU4aj/3gT2VfAVQpnXhcw0QPIpScn8 +YvrGTmav9l2iE1326aDCcMHhm83h1CCEBIHPuyO0tb0wh9z88BN4HTJeqKbT6ClO0zY kekmK8PN3RxoGauLUsKhZS6DKk6BZnEavkDixQW5QA6Mv0J+RKOJ0GSoNOFn/k9+Bgqn eZefNV4/3m51PEzwc3F5HFqM0Mwwu34Iv5eAPpJDtRgJSc1RcZ3LRmsetLfw/jxpJyQU QaqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=pw9Lr6A1xqwAKDrOkoPeST8MZRplOG8Yhjei+xoRZSc=; b=kPfswIG4aYi/rKMaSlt3en4KP57kYi4yL0zBCs2fij5VOsSC4ekftCl8xEx/eF+fU2 MSTUZqDi10H1VMJlRvoUKXE0DPEKDpUMoa7OkdwIBTwDhrK3QxqqYNsPNuUqhJsiqTTs E0HGjrQ87w5rKDxdbKyQYaJv57HJH3aunwXEctudK45cL0W/4U3IQRSi4Pewt1UsQJY/ 65tYwp9J/vXkKnAbTU/74zjbFdBVry3p0L6mVJH6gSMjaq7IwK7FwD6DmHkq5UrDrwBV 7K/I09Tg6HKHIlwnL7Dleqk5pwpkbIsIB2/3v9kjuGVD25IRTgs3ZBTusU228l8YngEd Uu7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=T8uFcHJV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2603:800c:1201:c600:119c:490c:a4ee:8e8]) by smtp.gmail.com with ESMTPSA id u25-20020a62ed19000000b004f140515d56sm3318043pfh.46.2022.03.03.11.16.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 11:16:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 6/9] tcg/aarch64: Support TCG_TARGET_SIGNED_ADDR32 Date: Thu, 3 Mar 2022 09:15:48 -1000 Message-Id: <20220303191551.466631-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303191551.466631-1-richard.henderson@linaro.org> References: <20220303191551.466631-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1035 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" AArch64 has both sign and zero-extending addressing modes, which means that either treatment of guest addresses is equally efficient. Enabling this for AArch64 gives us testing of the feature in CI. Cc: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/aarch64/tcg-target-sa32.h | 8 +++- tcg/aarch64/tcg-target.c.inc | 81 ++++++++++++++++++++++++----------- 2 files changed, 64 insertions(+), 25 deletions(-) diff --git a/tcg/aarch64/tcg-target-sa32.h b/tcg/aarch64/tcg-target-sa32.h index cb185b1526..c99e502e4c 100644 --- a/tcg/aarch64/tcg-target-sa32.h +++ b/tcg/aarch64/tcg-target-sa32.h @@ -1 +1,7 @@ -#define TCG_TARGET_SIGNED_ADDR32 0 +/* + * AArch64 has both SXTW and UXTW addressing modes, which means that + * it is agnostic to how guest addresses should be represented. + * Because aarch64 is more common than the other hosts that will + * want to use this feature, enable it for continuous testing. + */ +#define TCG_TARGET_SIGNED_ADDR32 1 diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 077fc51401..4a3edd6963 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -361,6 +361,16 @@ typedef enum { LDST_LD_S_W = 3, /* load and sign-extend into Wt */ } AArch64LdstType; +/* + * See aarch64/instrs/extendreg/DecodeRegExtend + * But note that option<1> == 0 is UNDEFINED for LDR/STR. + */ +typedef enum { + LDST_EXT_UXTW = 2, /* zero-extend from uint32_t */ + LDST_EXT_UXTX = 3, /* zero-extend from uint64_t (i.e. no extension) */ + LDST_EXT_SXTW = 6, /* sign-extend from int32_t */ +} AArch64LdstExt; + /* We encode the format of the insn into the beginning of the name, so that we can have the preprocessor help "typecheck" the insn vs the output function. Arm didn't provide us with nice names for the formats, so we @@ -806,12 +816,12 @@ static void tcg_out_insn_3617(TCGContext *s, AArch64Insn insn, bool q, } static void tcg_out_insn_3310(TCGContext *s, AArch64Insn insn, - TCGReg rd, TCGReg base, TCGType ext, + TCGReg rd, TCGReg base, AArch64LdstExt option, TCGReg regoff) { /* Note the AArch64Insn constants above are for C3.3.12. Adjust. */ tcg_out32(s, insn | I3312_TO_I3310 | regoff << 16 | - 0x4000 | ext << 13 | base << 5 | (rd & 0x1f)); + option << 13 | base << 5 | (rd & 0x1f)); } static void tcg_out_insn_3312(TCGContext *s, AArch64Insn insn, @@ -1126,7 +1136,7 @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn insn, TCGReg rd, /* Worst-case scenario, move offset to temp register, use reg offset. */ tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, offset); - tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP); + tcg_out_ldst_r(s, insn, rd, rn, LDST_EXT_UXTX, TCG_REG_TMP); } static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) @@ -1765,31 +1775,31 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext, TCGReg data_r, TCGReg addr_r, - TCGType otype, TCGReg off_r) + AArch64LdstExt option, TCGReg off_r) { switch (memop & MO_SSIZE) { case MO_UB: - tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, option, off_r); break; case MO_SB: tcg_out_ldst_r(s, ext ? I3312_LDRSBX : I3312_LDRSBW, - data_r, addr_r, otype, off_r); + data_r, addr_r, option, off_r); break; case MO_UW: - tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, option, off_r); break; case MO_SW: tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW), - data_r, addr_r, otype, off_r); + data_r, addr_r, option, off_r); break; case MO_UL: - tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, option, off_r); break; case MO_SL: - tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, option, off_r); break; case MO_UQ: - tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, option, off_r); break; default: tcg_abort(); @@ -1798,31 +1808,52 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext, static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop, TCGReg data_r, TCGReg addr_r, - TCGType otype, TCGReg off_r) + AArch64LdstExt option, TCGReg off_r) { switch (memop & MO_SIZE) { case MO_8: - tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, option, off_r); break; case MO_16: - tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, option, off_r); break; case MO_32: - tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, option, off_r); break; case MO_64: - tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, option, off_r); break; default: tcg_abort(); } } +/* + * Bits for the option field of LDR/STR (register), + * for application to a guest address. + */ +static AArch64LdstExt ldst_ext_option(void) +{ +#ifdef CONFIG_USER_ONLY + bool signed_addr32 = guest_base_signed_addr32; +#else + bool signed_addr32 = TCG_TARGET_SIGNED_ADDR32; +#endif + + if (TARGET_LONG_BITS == 64) { + return LDST_EXT_UXTX; + } else if (signed_addr32) { + return LDST_EXT_SXTW; + } else { + return LDST_EXT_UXTW; + } +} + static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, MemOpIdx oi, TCGType ext) { MemOp memop = get_memop(oi); - const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32; + AArch64LdstExt option = ldst_ext_option(); /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((memop & MO_BSWAP) == 0); @@ -1833,7 +1864,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 1); tcg_out_qemu_ld_direct(s, memop, ext, data_reg, - TCG_REG_X1, otype, addr_reg); + TCG_REG_X1, option, addr_reg); add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ @@ -1843,10 +1874,11 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, } if (USE_GUEST_BASE) { tcg_out_qemu_ld_direct(s, memop, ext, data_reg, - TCG_REG_GUEST_BASE, otype, addr_reg); + TCG_REG_GUEST_BASE, option, addr_reg); } else { + /* This case is always a 64-bit guest with no extension. */ tcg_out_qemu_ld_direct(s, memop, ext, data_reg, - addr_reg, TCG_TYPE_I64, TCG_REG_XZR); + addr_reg, LDST_EXT_UXTX, TCG_REG_XZR); } #endif /* CONFIG_SOFTMMU */ } @@ -1855,7 +1887,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, MemOpIdx oi) { MemOp memop = get_memop(oi); - const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32; + AArch64LdstExt option = ldst_ext_option(); /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((memop & MO_BSWAP) == 0); @@ -1866,7 +1898,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 0); tcg_out_qemu_st_direct(s, memop, data_reg, - TCG_REG_X1, otype, addr_reg); + TCG_REG_X1, option, addr_reg); add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)== MO_64, data_reg, addr_reg, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ @@ -1876,10 +1908,11 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, } if (USE_GUEST_BASE) { tcg_out_qemu_st_direct(s, memop, data_reg, - TCG_REG_GUEST_BASE, otype, addr_reg); + TCG_REG_GUEST_BASE, option, addr_reg); } else { + /* This case is always a 64-bit guest with no extension. */ tcg_out_qemu_st_direct(s, memop, data_reg, - addr_reg, TCG_TYPE_I64, TCG_REG_XZR); + addr_reg, LDST_EXT_UXTX, TCG_REG_XZR); } #endif /* CONFIG_SOFTMMU */ } From patchwork Thu Mar 3 19:15:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 547797 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:3c7:0:0:0:0 with SMTP id b7csp1180359wrg; Thu, 3 Mar 2022 11:23:24 -0800 (PST) X-Google-Smtp-Source: ABdhPJxkFDhG6Icp04Bfa6fXxkfK50IQQYZyr9XD2ZaFPfth0YMBcPZM1ZVuS0LwuVNt3ZrkRJB8 X-Received: by 2002:a81:998c:0:b0:2d7:7e7d:877d with SMTP id q134-20020a81998c000000b002d77e7d877dmr36865443ywg.78.1646335403914; Thu, 03 Mar 2022 11:23:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646335403; cv=none; d=google.com; s=arc-20160816; b=kMjLB2GgMwn0Mg4epkrpUoeTsYXM4TbR6WH8qvARxk6zQdn6g9e4YtPzitRntsvhN3 OEhBxz2h1jDzZGGMl+S/u3KFxjAqJ8u3rz/QFnHrmk8lBsYaa76PtFqf1cR5xMq/5W7Z ZuAMC/6Qi3gsvvgOJX4TsJc2M2oroXKR/Hhakv1YpVZUuhzf4tZu9LtVZ0gL10VOHEgt JL1danevaPYOKfmDAd1FgttY+RmeuESci3hLLgDUcBPso4u+hSVgGNSbtbLQgG8yJfuP dlXe/yWC6SSGjFSl4UpN/8PuXckZhMrXKfUuRAtUGXA8zv+9URleL5uYgEm8Jl4Dcill ANKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+BD96XfV2twTSXl72v5Agr1at/ZBm5w6SA0tYUmlFcg=; b=TNyWrTRlPU+WZNH6xTKZzLW2LaIplbHmRSxR6Pd+Ila1I5wRFkWxVtMwXKF/zB5f80 zGdZd8+EESg2ymWNWQuhx5O3Rza7Tc35VwgwLDVenURo0VC4608qRSBPa1A4JjyTOAvW 1iwxyZdYIllIeelCCHtjD0bYEqd0HUp+NOChRSqhpzHnb8NSqsIsTmYQ3d/Road1oDvu LhaJMGpV5KjbemKN+i0I7HJA3zYuvM3zf7mJ9dPAAA9T/Jm5K/2E9CQ1jhHhI9CRxr8H fseR9EPmHbMuzUg/df0H+DLgjD2q9rLkHuIL7UNAfNv+AAC0pi01/y+oFrTdNkOgkyZQ tCAg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OkqH6XdZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2603:800c:1201:c600:119c:490c:a4ee:8e8]) by smtp.gmail.com with ESMTPSA id u25-20020a62ed19000000b004f140515d56sm3318043pfh.46.2022.03.03.11.16.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 11:16:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 7/9] tcg/mips: Support TCG_TARGET_SIGNED_ADDR32 Date: Thu, 3 Mar 2022 09:15:49 -1000 Message-Id: <20220303191551.466631-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303191551.466631-1-richard.henderson@linaro.org> References: <20220303191551.466631-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62b (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" All 32-bit mips operations sign-extend the output, so we are easily able to keep TCG_TYPE_I32 values sign-extended in host registers. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-sa32.h | 8 ++++++++ tcg/mips/tcg-target.c.inc | 10 ++-------- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/tcg/mips/tcg-target-sa32.h b/tcg/mips/tcg-target-sa32.h index cb185b1526..51255e7cba 100644 --- a/tcg/mips/tcg-target-sa32.h +++ b/tcg/mips/tcg-target-sa32.h @@ -1 +1,9 @@ +/* + * Do not set TCG_TARGET_SIGNED_ADDR32 for mips32; + * TCG expects this to only be set for 64-bit hosts. + */ +#ifdef __mips64 +#define TCG_TARGET_SIGNED_ADDR32 1 +#else #define TCG_TARGET_SIGNED_ADDR32 0 +#endif diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 993149d18a..b97c032ded 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1168,12 +1168,6 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl, TCG_TMP0, TCG_TMP3, cmp_off); } - /* Zero extend a 32-bit guest address for a 64-bit host. */ - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addrl); - addrl = base; - } - /* * Mask the page bits, keeping the alignment bits to compare against. * For unaligned accesses, compare against the end of the access to @@ -1679,7 +1673,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) data_regl, data_regh, addr_regl, addr_regh, s->code_ptr, label_ptr); #else - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr32) { tcg_out_ext32u(s, base, addr_regl); addr_regl = base; } @@ -1878,7 +1872,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) data_regl, data_regh, addr_regl, addr_regh, s->code_ptr, label_ptr); #else - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr32) { tcg_out_ext32u(s, base, addr_regl); addr_regl = base; } From patchwork Thu Mar 3 19:15:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 547802 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:3c7:0:0:0:0 with SMTP id b7csp1184853wrg; Thu, 3 Mar 2022 11:31:48 -0800 (PST) X-Google-Smtp-Source: ABdhPJx4TouCMHdsp9/jNVro+5kgViow1KbTnwyCKc3N7LMcQiBFszGvyo27EuDrOT0q2W4Rxoun X-Received: by 2002:a05:6902:1c9:b0:614:4645:8816 with SMTP id u9-20020a05690201c900b0061446458816mr34929545ybh.469.1646335908032; Thu, 03 Mar 2022 11:31:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646335908; cv=none; d=google.com; s=arc-20160816; b=mLedKqvA7ZuTTyud9vv7gymrVZibFdiwvqzLFwkGPaiPNnGdErnKBpQT3aHo7YP/dA x4/ljYSaUCI1BRI/DvX9Qo4nXXN/76qY581asaNSAXGjNu4XwkEZ69onKhULXYUX8LqE qE5UBXwYIeiw8yGObITceWRqC2JwVexvEqxQe+qacUEEWb1ME1wV1XJHa2lD8Hhc4aRF X9VASWnNekUtpVrL/HBB1J1i9C1se7IGRCo5zNjw8lRWw7EuysjZl0B0KfF3AtWapoTQ 8epbxGbex+CisZJAZasjF0dwdUQS07+ol+WNc4/46/tQw4USPEwS/n8blSIknpwUXyWm Np2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Ho2jnp9wAsj5SBP8tX6ESXDweHDs0USlRJ9dHfy8f/A=; b=HxmSHKdiCYB9whr3ViIhFYVfbMWF8iPEf79nRPRJZSd96jICtrvrGwDdY2DhaKjWxc vi12zk3gGnCeWNcdGFuj/L0UKUauloIiBjMXLDWNWWr0soIh5gvgrILsEp22xhnlEehx 1n3Em1yokKmt1PxgvCd3pOvJcSSMEsSV1oMSNmKCelSPSsc+fmYugRRZk8KSAPg5ACYb nr2Hg4T+biGsUjVxLeuYAUajpMOoHl1vX6aMCn6qZJmRcEYhDBEy17d85HEJS1Lm74aT LzU8x+UqpN8yXnQP40di+pK8kAyiv4UZ1jfZdWVv2rxYO/NMufagV4c67iHGlbjLeRbi dHpw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CTNxQqXt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2603:800c:1201:c600:119c:490c:a4ee:8e8]) by smtp.gmail.com with ESMTPSA id u25-20020a62ed19000000b004f140515d56sm3318043pfh.46.2022.03.03.11.16.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 11:16:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 8/9] tcg/riscv: Support TCG_TARGET_SIGNED_ADDR32 Date: Thu, 3 Mar 2022 09:15:50 -1000 Message-Id: <20220303191551.466631-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303191551.466631-1-richard.henderson@linaro.org> References: <20220303191551.466631-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::434 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" All RV64 32-bit operations sign-extend the output, so we are easily able to keep TCG_TYPE_I32 values sign-extended in host registers. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-sa32.h | 6 +++++- tcg/riscv/tcg-target.c.inc | 8 ++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/tcg/riscv/tcg-target-sa32.h b/tcg/riscv/tcg-target-sa32.h index cb185b1526..703467b37a 100644 --- a/tcg/riscv/tcg-target-sa32.h +++ b/tcg/riscv/tcg-target-sa32.h @@ -1 +1,5 @@ -#define TCG_TARGET_SIGNED_ADDR32 0 +/* + * Do not set TCG_TARGET_SIGNED_ADDR32 for RV32; + * TCG expects this to only be set for 64-bit hosts. + */ +#define TCG_TARGET_SIGNED_ADDR32 (__riscv_xlen == 64) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 6409d9c3d5..c999711494 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -951,10 +951,6 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0); /* TLB Hit - translate address using addend. */ - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, TCG_REG_TMP0, addrl); - addrl = TCG_REG_TMP0; - } tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl); } @@ -1175,7 +1171,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) data_regl, data_regh, addr_regl, addr_regh, s->code_ptr, label_ptr); #else - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr32) { tcg_out_ext32u(s, base, addr_regl); addr_regl = base; } @@ -1247,7 +1243,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) data_regl, data_regh, addr_regl, addr_regh, s->code_ptr, label_ptr); #else - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr32) { tcg_out_ext32u(s, base, addr_regl); addr_regl = base; } From patchwork Thu Mar 3 19:15:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 547793 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:3c7:0:0:0:0 with SMTP id b7csp1177548wrg; Thu, 3 Mar 2022 11:18:09 -0800 (PST) X-Google-Smtp-Source: ABdhPJx8AcUNOANakUNPfR8BJdrw0W1RI8fXpMZCPB+LetaZS7YL8A4eWxzOSXH+/8qLaFY24GT8 X-Received: by 2002:a81:346:0:b0:2dc:5363:ed9c with SMTP id 67-20020a810346000000b002dc5363ed9cmr2143271ywd.378.1646335089178; Thu, 03 Mar 2022 11:18:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1646335089; cv=none; d=google.com; s=arc-20160816; b=eTAZu4k36U7vqLgtiH/eigRjRsZ7Zzt+w98myvoVXPVijouIqObVVFWICLVcHTDm2M 38XWWFpAXiK6azLNVOLQ4Ct6LuZb37eJRtryKDyAHSDP5ydSSdms8QjuOARu2GnCgWNO xknZXK6eb18UFzfQZfyGS8HtFkLJX91NJHpiKj1+M5FvEwmRw1oKuVpWJl21ldZElf2J RitSCAc7jLLhjUdYLuFGDCY4BXlGTkbBLEGGD04EE+Vjnguo3SoGadF+He+PVdtZE/O9 MsGz8TQeoWaHcldCAOlIj/41av9Pa+ap+RfjyGRtR5UhWxVxKN5a9RVsHWpgWYn4UMVb BLkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=KnojlxdJvLZ10xztEz7NOsevcqMVQEVsVSU9aLxpzTg=; b=K9uZe4WXJ1AveuW82BoBRP+PhSik2ANRcqPE4gP0S1UvT9HnG+sTJbIgmFofZcMrVn tXNO4X5Oa9gD4HYm2vTmd0XgrDE4Qw69DIwRw4CohMLPX549NRuD2r8lOkd1h6RBnwMD 0dTSekxBsNNs9zg1Aa/xQJPfH+brzlqU2KAtSpWXKMqnEMreLCSvOfqWoeP4HkOUcqAH zLfHJizilR7rFIUZucpw82bXd718lvNBq9R2/Osl/WcHoJLOd3/vJL36H0noI715Uf+o vYPUAbtzUJ9Ne9ykFdogRdzYnW/ULWe7vNhJZSShqBo+uz3QSDXf0ZbZt6bwHS0Gl46L IRlg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qz6RvfJF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2603:800c:1201:c600:119c:490c:a4ee:8e8]) by smtp.gmail.com with ESMTPSA id u25-20020a62ed19000000b004f140515d56sm3318043pfh.46.2022.03.03.11.16.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 11:16:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 9/9] tcg/loongarch64: Support TCG_TARGET_SIGNED_ADDR32 Date: Thu, 3 Mar 2022 09:15:51 -1000 Message-Id: <20220303191551.466631-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303191551.466631-1-richard.henderson@linaro.org> References: <20220303191551.466631-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1035 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" All 32-bit LoongArch operations sign-extend the output, so we are easily able to keep TCG_TYPE_I32 values sign-extended in host registers. Cc: WANG Xuerui Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target-sa32.h | 2 +- tcg/loongarch64/tcg-target.c.inc | 15 ++++++--------- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/tcg/loongarch64/tcg-target-sa32.h b/tcg/loongarch64/tcg-target-sa32.h index cb185b1526..aaffd777bf 100644 --- a/tcg/loongarch64/tcg-target-sa32.h +++ b/tcg/loongarch64/tcg-target-sa32.h @@ -1 +1 @@ -#define TCG_TARGET_SIGNED_ADDR32 0 +#define TCG_TARGET_SIGNED_ADDR32 1 diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index a3debf6da7..425f6629ca 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -880,8 +880,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) return tcg_out_fail_alignment(s, l); } -#endif /* CONFIG_SOFTMMU */ - /* * `ext32u` the address register into the temp register given, * if target is 32-bit, no-op otherwise. @@ -891,12 +889,13 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) static TCGReg tcg_out_zext_addr_if_32_bit(TCGContext *s, TCGReg addr, TCGReg tmp) { - if (TARGET_LONG_BITS == 32) { + if (TARGET_LONG_BITS == 32 && !guest_base_signed_addr32) { tcg_out_ext32u(s, tmp, addr); return tmp; } return addr; } +#endif /* CONFIG_SOFTMMU */ static void tcg_out_qemu_ld_indexed(TCGContext *s, TCGReg rd, TCGReg rj, TCGReg rk, MemOp opc, TCGType type) @@ -944,8 +943,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGType type) tcg_insn_unit *label_ptr[1]; #else unsigned a_bits; -#endif TCGReg base; +#endif data_regl = *args++; addr_regl = *args++; @@ -954,8 +953,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGType type) #if defined(CONFIG_SOFTMMU) tcg_out_tlb_load(s, addr_regl, oi, label_ptr, 1); - base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0); - tcg_out_qemu_ld_indexed(s, data_regl, base, TCG_REG_TMP2, opc, type); + tcg_out_qemu_ld_indexed(s, data_regl, addr_regl, TCG_REG_TMP2, opc, type); add_qemu_ldst_label(s, 1, oi, type, data_regl, addr_regl, s->code_ptr, label_ptr); @@ -1004,8 +1002,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args) tcg_insn_unit *label_ptr[1]; #else unsigned a_bits; -#endif TCGReg base; +#endif data_regl = *args++; addr_regl = *args++; @@ -1014,8 +1012,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args) #if defined(CONFIG_SOFTMMU) tcg_out_tlb_load(s, addr_regl, oi, label_ptr, 0); - base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0); - tcg_out_qemu_st_indexed(s, data_regl, base, TCG_REG_TMP2, opc); + tcg_out_qemu_st_indexed(s, data_regl, addr_regl, TCG_REG_TMP2, opc); add_qemu_ldst_label(s, 0, oi, 0, /* type param is unused for stores */ data_regl, addr_regl,