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[188.155.181.108]) by smtp.gmail.com with ESMTPSA id r23-20020aa7da17000000b00415a1431488sm2047368eds.4.2022.03.04.04.25.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Mar 2022 04:25:00 -0800 (PST) From: Krzysztof Kozlowski To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v2 1/4] dt-bindings: timer: exynos4210-mct: describe known hardware and its interrupts Date: Fri, 4 Mar 2022 13:24:21 +0100 Message-Id: <20220304122424.307885-2-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220304122424.307885-1-krzysztof.kozlowski@canonical.com> References: <20220304122424.307885-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Most of the Samsung Exynos SoCs use almost the same Multi-Core Timer block, so only two compatibles were used so far (for Exynos4210 and Exynos4412 flavors) with Exynos4210-one being used in most of the SoCs. However the Exynos4210 flavor actually differs by number of interrupts. Add new compatibles, maintaining backward compatibility with Exynos4210, and constraints for number of interrupts. This allows to exactly match the Exynos MCT hardware. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar Reviewed-by: Rob Herring --- .../timer/samsung,exynos4210-mct.yaml | 67 ++++++++++++++++++- 1 file changed, 64 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml index f11cbc7ccc14..1584944c7ac4 100644 --- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml @@ -19,9 +19,20 @@ description: |+ properties: compatible: - enum: - - samsung,exynos4210-mct - - samsung,exynos4412-mct + oneOf: + - enum: + - samsung,exynos4210-mct + - samsung,exynos4412-mct + - items: + - enum: + - samsung,exynos3250-mct + - samsung,exynos5250-mct + - samsung,exynos5260-mct + - samsung,exynos5420-mct + - samsung,exynos5433-mct + - samsung,exynos850-mct + - tesla,fsd-mct + - const: samsung,exynos4210-mct clocks: minItems: 2 @@ -63,6 +74,56 @@ required: - interrupts - reg +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos3250-mct + then: + properties: + interrupts: + minItems: 8 + maxItems: 8 + + - if: + properties: + compatible: + contains: + const: samsung,exynos5250-mct + then: + properties: + interrupts: + minItems: 6 + maxItems: 6 + + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos5260-mct + - samsung,exynos5420-mct + - samsung,exynos5433-mct + - samsung,exynos850-mct + then: + properties: + interrupts: + minItems: 12 + maxItems: 12 + + - if: + properties: + compatible: + contains: + enum: + - tesla,fsd-mct + then: + properties: + interrupts: + minItems: 16 + maxItems: 16 + additionalProperties: false examples: From patchwork Fri Mar 4 12:24:22 2022 Content-Type: text/plain; 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[188.155.181.108]) by smtp.gmail.com with ESMTPSA id r23-20020aa7da17000000b00415a1431488sm2047368eds.4.2022.03.04.04.25.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Mar 2022 04:25:02 -0800 (PST) From: Krzysztof Kozlowski To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v2 2/4] ARM: dts: exynos: add a specific compatible to MCT Date: Fri, 4 Mar 2022 13:24:22 +0100 Message-Id: <20220304122424.307885-3-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220304122424.307885-1-krzysztof.kozlowski@canonical.com> References: <20220304122424.307885-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org One compatible is used for the Multi-Core Timer on most of the Samsung Exynos SoCs, which is correct but not specific enough. These MCT blocks have different number of interrupts, so add a second specific compatible to Exynos3250 and all Exynos5 SoCs. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar --- arch/arm/boot/dts/exynos3250.dtsi | 3 ++- arch/arm/boot/dts/exynos5250.dtsi | 3 ++- arch/arm/boot/dts/exynos5260.dtsi | 3 ++- arch/arm/boot/dts/exynos54xx.dtsi | 3 ++- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index ae644315855d..41bb421e67c2 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -269,7 +269,8 @@ gic: interrupt-controller@10481000 { }; timer@10050000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos3250-mct", + "samsung,exynos4210-mct"; reg = <0x10050000 0x800>; interrupts = , , diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 5baaa7eb71a4..63d1dcf2c55c 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -245,7 +245,8 @@ clock_audss: audss-clock-controller@3810000 { }; timer@101c0000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos5250-mct", + "samsung,exynos4210-mct"; reg = <0x101C0000 0x800>; clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; clock-names = "fin_pll", "mct"; diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index 56271e7c4587..ff1ee409eff3 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -333,7 +333,8 @@ chipid: chipid@10000000 { }; mct: timer@100b0000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos5260-mct", + "samsung,exynos4210-mct"; reg = <0x100B0000 0x1000>; clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>; clock-names = "fin_pll", "mct"; diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index 2ddb7a5f12b3..3ec43761d8b9 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -74,7 +74,8 @@ smp-sram@53000 { }; mct: timer@101c0000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos5420-mct", + "samsung,exynos4210-mct"; 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[188.155.181.108]) by smtp.gmail.com with ESMTPSA id r23-20020aa7da17000000b00415a1431488sm2047368eds.4.2022.03.04.04.25.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Mar 2022 04:25:03 -0800 (PST) From: Krzysztof Kozlowski To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v2 3/4] arm64: dts: exynos: add a specific compatible to MCT Date: Fri, 4 Mar 2022 13:24:23 +0100 Message-Id: <20220304122424.307885-4-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220304122424.307885-1-krzysztof.kozlowski@canonical.com> References: <20220304122424.307885-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org One compatible is used for the Multi-Core Timer on most of the Samsung Exynos SoCs, which is correct but not specific enough. These MCT blocks have different number of interrupts, so add a second specific compatible to Exynos5433 and Exynos850. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 3 ++- arch/arm64/boot/dts/exynos/exynos850.dtsi | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 661567d2dd7a..017ccc2f4650 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -806,7 +806,8 @@ tmu_isp: tmu@1007c000 { }; timer@101c0000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos5433-mct", + "samsung,exynos4210-mct"; reg = <0x101c0000 0x800>; interrupts = , , diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index d1700e96fee2..12f7ddc6fd0a 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -181,7 +181,8 @@ chipid@10000000 { }; timer@10040000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos850-mct", + "samsung,exynos4210-mct"; reg = <0x10040000 0x800>; interrupts = , , From patchwork Fri Mar 4 12:24:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 548814 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A04F6C4332F for ; Fri, 4 Mar 2022 12:25:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239714AbiCDM0B (ORCPT ); Fri, 4 Mar 2022 07:26:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60134 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238800AbiCDMZ7 (ORCPT ); Fri, 4 Mar 2022 07:25:59 -0500 Received: from smtp-relay-internal-0.canonical.com (smtp-relay-internal-0.canonical.com [185.125.188.122]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 630091B0BCE for ; Fri, 4 Mar 2022 04:25:07 -0800 (PST) Received: from mail-ej1-f72.google.com (mail-ej1-f72.google.com [209.85.218.72]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-0.canonical.com (Postfix) with ESMTPS id 388753F621 for ; Fri, 4 Mar 2022 12:25:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1646396706; bh=sMfVOQVh3QDv09HKuf77ip6IaDuNbDVh/tnxPccjD3M=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=OSiNLVksYhv5BFZYyWz7Z0kz/NKn/mboV6ONJF/avttnv/LglB34ywPTh/xlOuCA1 zXQNGtB6dlkV7ovP8rmL+8ono9GJ4sQTfrbtGZne7WpZEGYcsjcGNMn2+TxXi4JlHK 8rA61suFkKRiZkgewlCQ+8ORtdatiVZ0TLdxBfsRNSOVz73kOSPSqqlr+gd+mpwcVh IhaEXsgJ34l5Ms5YxxZkdzw4YY47w/rHqLwpN7+OsYZVO0NzDql0ZZzwLm6YzfhVCE en3IY63jKPoGsr8U3JkycQmDWNMWW5KrYmQ0PvtULLHt57ibEwKxFmfrKcvrGZw+x2 q+j83C6TgpSYQ== Received: by mail-ej1-f72.google.com with SMTP id la22-20020a170907781600b006a7884de505so4330998ejc.7 for ; Fri, 04 Mar 2022 04:25:06 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sMfVOQVh3QDv09HKuf77ip6IaDuNbDVh/tnxPccjD3M=; b=6lWMkpzhOQTmG41PzFALaVj4N0mJgUwsmXcT7kpTDUEyswtZzSSG2JEjRx577+ayu/ ARRISmOgWWHJlo6lRgcOsgYOvyhBrBR3C5WbX5pTTTlwI6qEvjiGQpfguqbO2Yp8kMJh pqUaxYbi1tNOz8sshng2jlWQaq7frhpCJRjC9012TfS3SAai81GEFDcMFXCEpL6OWQAx DmfnYLWrBhjYBfj0JXRFotAt58vRXJBfhv9YpWbmyIus54r1frAy1GCfp1twg8dROovj ey2y6vzwb9SOWJ5eqxhKC17zcqDIP0++lP9XKtvVAZpnpPf2aaejBm3xx/xTcEbmuPtw 56WQ== X-Gm-Message-State: AOAM530CKDpTsZ/JtkXJdi8Wum7UplLrwoxLd6i2Uq3FnkZWyL8Sd1vH 3D70lcEYPSyOkbHS7tQW9LDb/nLW9aBZp9E1l0FyqIsi7QsK/dXJCzggTHvjDykDoUlwrBvQN/R 7WRXZXBV7jF98qb6A40SbK0cdYJ1gRZnRoHy7sbkelmYkM98X X-Received: by 2002:aa7:d14f:0:b0:415:cf37:324b with SMTP id r15-20020aa7d14f000000b00415cf37324bmr9098551edo.263.1646396705938; Fri, 04 Mar 2022 04:25:05 -0800 (PST) X-Google-Smtp-Source: ABdhPJzKMSVDmEk/neqIWD4dYZYTA7KTOdHcqfRP178ukkaNKBBjSxa1rHQ9JAwE06E9Efaict8Eiw== X-Received: by 2002:aa7:d14f:0:b0:415:cf37:324b with SMTP id r15-20020aa7d14f000000b00415cf37324bmr9098533edo.263.1646396705766; Fri, 04 Mar 2022 04:25:05 -0800 (PST) Received: from localhost.localdomain (xdsl-188-155-181-108.adslplus.ch. [188.155.181.108]) by smtp.gmail.com with ESMTPSA id r23-20020aa7da17000000b00415a1431488sm2047368eds.4.2022.03.04.04.25.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Mar 2022 04:25:05 -0800 (PST) From: Krzysztof Kozlowski To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v2 4/4] arm64: dts: tesla: add a specific compatible to MCT on FSD Date: Fri, 4 Mar 2022 13:24:24 +0100 Message-Id: <20220304122424.307885-5-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220304122424.307885-1-krzysztof.kozlowski@canonical.com> References: <20220304122424.307885-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org One compatible is used for the Multi-Core Timer on Tesla FSD SoC, which is correct but not specific enough. The MCT blocks have different number of interrupts, so add a second specific compatible to Tesla FSD. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar --- arch/arm64/boot/dts/tesla/fsd.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index 9a652abcbcac..10c217a57a7d 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -727,7 +727,7 @@ spi_2: spi@14160000 { }; timer@10040000 { - compatible = "samsung,exynos4210-mct"; + compatible = "tesla,fsd-mct", "samsung,exynos4210-mct"; reg = <0x0 0x10040000 0x0 0x800>; interrupts = , ,