From patchwork Wed Mar 16 16:17:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivasa Rao Mandadapu X-Patchwork-Id: 551951 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ACB5BC433FE for ; Wed, 16 Mar 2022 16:17:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356229AbiCPQTD (ORCPT ); Wed, 16 Mar 2022 12:19:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51286 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357407AbiCPQTB (ORCPT ); Wed, 16 Mar 2022 12:19:01 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 47AA62A6; Wed, 16 Mar 2022 09:17:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647447467; x=1678983467; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=rKR8R2xrvVMhCLJudTmph3ry8li11n/7voUDkq7zraY=; b=u+yIJ0OmQPVzLOw+RH2hzOy2jz3Gs71vTR1zlRMlW6KZpB4ELUXZsgzQ BLmw8uYLMXw/W83jN2+T/o8gNi5ZODW1BqZ2yxL4Nh6bJhTCbhpUkEt6X lFr4KnXmJ3adRqzuJ4ilWQTmG9y4xgSIM7rtpqeHqpuKH48/tfuQjrT/C M=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-02.qualcomm.com with ESMTP; 16 Mar 2022 09:17:47 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2022 09:17:46 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 09:17:46 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 09:17:39 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , , , , , , , , Linus Walleij , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v12 1/7] dt-bindings: pinctrl: qcom: Update lpass lpi file name to SoC specific Date: Wed, 16 Mar 2022 21:47:00 +0530 Message-ID: <1647447426-23425-2-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647447426-23425-1-git-send-email-quic_srivasam@quicinc.com> References: <1647447426-23425-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Change generic lpass lpi pincotrol bindings file to SoC specific file, to distinguish and accomadate other SoC specific dt bindings. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu Acked-by: Rob Herring Reviewed-by: Stephen Boyd --- .../bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml | 133 --------------------- .../pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml | 133 +++++++++++++++++++++ 2 files changed, 133 insertions(+), 133 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml deleted file mode 100644 index 5c5542f..0000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml +++ /dev/null @@ -1,133 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS) - Low Power Island (LPI) TLMM block - -maintainers: - - Srinivas Kandagatla - -description: | - This binding describes the Top Level Mode Multiplexer block found in the - LPASS LPI IP on most Qualcomm SoCs - -properties: - compatible: - const: qcom,sm8250-lpass-lpi-pinctrl - - reg: - minItems: 2 - maxItems: 2 - - clocks: - items: - - description: LPASS Core voting clock - - description: LPASS Audio voting clock - - clock-names: - items: - - const: core - - const: audio - - gpio-controller: true - - '#gpio-cells': - description: Specifying the pin number and flags, as defined in - include/dt-bindings/gpio/gpio.h - const: 2 - - gpio-ranges: - maxItems: 1 - -#PIN CONFIGURATION NODES -patternProperties: - '-pins$': - type: object - description: - Pinctrl node's client devices use subnodes for desired pin configuration. - Client device subnodes use below standard properties. - $ref: "/schemas/pinctrl/pincfg-node.yaml" - - properties: - pins: - description: - List of gpio pins affected by the properties specified in this - subnode. - items: - oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9])$" - minItems: 1 - maxItems: 14 - - function: - enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws, - qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk, - dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data, - i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk, - dmic3_data, i2s2_data ] - description: - Specify the alternative function to be configured for the specified - pins. - - drive-strength: - enum: [2, 4, 6, 8, 10, 12, 14, 16] - default: 2 - description: - Selects the drive strength for the specified pins, in mA. - - slew-rate: - enum: [0, 1, 2, 3] - default: 0 - description: | - 0: No adjustments - 1: Higher Slew rate (faster edges) - 2: Lower Slew rate (slower edges) - 3: Reserved (No adjustments) - - bias-pull-down: true - - bias-pull-up: true - - bias-disable: true - - output-high: true - - output-low: true - - required: - - pins - - function - - additionalProperties: false - -allOf: - - $ref: "pinctrl.yaml#" - -required: - - compatible - - reg - - clocks - - clock-names - - gpio-controller - - '#gpio-cells' - - gpio-ranges - -additionalProperties: false - -examples: - - | - #include - lpi_tlmm: pinctrl@33c0000 { - compatible = "qcom,sm8250-lpass-lpi-pinctrl"; - reg = <0x33c0000 0x20000>, - <0x3550000 0x10000>; - clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; - clock-names = "core", "audio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&lpi_tlmm 0 0 14>; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml new file mode 100644 index 0000000..06efb13 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS) + Low Power Island (LPI) TLMM block + +maintainers: + - Srinivas Kandagatla + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + LPASS LPI IP on most Qualcomm SoCs + +properties: + compatible: + const: qcom,sm8250-lpass-lpi-pinctrl + + reg: + minItems: 2 + maxItems: 2 + + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: core + - const: audio + + gpio-controller: true + + '#gpio-cells': + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: "/schemas/pinctrl/pincfg-node.yaml" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9])$" + minItems: 1 + maxItems: 14 + + function: + enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws, + qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk, + dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data, + i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk, + dmic3_data, i2s2_data ] + description: + Specify the alternative function to be configured for the specified + pins. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + slew-rate: + enum: [0, 1, 2, 3] + default: 0 + description: | + 0: No adjustments + 1: Higher Slew rate (faster edges) + 2: Lower Slew rate (slower edges) + 3: Reserved (No adjustments) + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + required: + - pins + - function + + additionalProperties: false + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + - reg + - clocks + - clock-names + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + lpi_tlmm: pinctrl@33c0000 { + compatible = "qcom,sm8250-lpass-lpi-pinctrl"; + reg = <0x33c0000 0x20000>, + <0x3550000 0x10000>; + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpi_tlmm 0 0 14>; + }; From patchwork Wed Mar 16 16:17:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivasa Rao Mandadapu X-Patchwork-Id: 552812 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B872EC4332F for ; Wed, 16 Mar 2022 16:18:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357436AbiCPQTQ (ORCPT ); Wed, 16 Mar 2022 12:19:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52158 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357424AbiCPQTO (ORCPT ); Wed, 16 Mar 2022 12:19:14 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F26FAE7B; Wed, 16 Mar 2022 09:17:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647447475; x=1678983475; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=As1X0P/G4QwXKGqgTUAbh2m46WDe6bYCw7umSlOuyHc=; b=YvRuOxead8pm0QUHsuSPZrGbwINRZIH+AtqioSQwDSVugfIXRzSibBO3 ZhI4UnM+EvYi4gWAGUa+medBaGusVPYU9NS3GNVbWOSysnsxZGNNkTeOm s7alGt6E1i4yq8STbfGjBN/TTbe5QkBykyQF2ipkhgBkUdNIiklVnC/Cx k=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 16 Mar 2022 09:17:54 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2022 09:17:53 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 09:17:52 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 09:17:46 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , , , , , , , , Linus Walleij , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v12 2/7] dt-bindings: pinctrl: qcom: Add sc7280 lpass lpi pinctrl bindings Date: Wed, 16 Mar 2022 21:47:01 +0530 Message-ID: <1647447426-23425-3-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647447426-23425-1-git-send-email-quic_srivasam@quicinc.com> References: <1647447426-23425-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device tree binding Documentation details for Qualcomm SC7280 LPASS LPI pinctrl driver. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu Reviewed-by: Rob Herring Reviewed-by: Stephen Boyd --- .../pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml | 115 +++++++++++++++++++++ 1 file changed, 115 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml new file mode 100644 index 0000000..d32ee32 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS) + Low Power Island (LPI) TLMM block + +maintainers: + - Srinivasa Rao Mandadapu + - Srinivas Kandagatla + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + LPASS LPI IP on most Qualcomm SoCs + +properties: + compatible: + const: qcom,sc7280-lpass-lpi-pinctrl + + reg: + minItems: 2 + maxItems: 2 + + gpio-controller: true + + '#gpio-cells': + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: "/schemas/pinctrl/pincfg-node.yaml" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9])$" + minItems: 1 + maxItems: 15 + + function: + enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws, + qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk, + dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data, + i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk, + dmic3_data, i2s2_data ] + description: + Specify the alternative function to be configured for the specified + pins. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + slew-rate: + enum: [0, 1, 2, 3] + default: 0 + description: | + 0: No adjustments + 1: Higher Slew rate (faster edges) + 2: Lower Slew rate (slower edges) + 3: Reserved (No adjustments) + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + required: + - pins + - function + + additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + lpass_tlmm: pinctrl@33c0000 { + compatible = "qcom,sc7280-lpass-lpi-pinctrl"; + reg = <0x33c0000 0x20000>, + <0x3550000 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 15>; + }; From patchwork Wed Mar 16 16:17:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivasa Rao Mandadapu X-Patchwork-Id: 551950 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A0D3C433EF for ; Wed, 16 Mar 2022 16:18:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357443AbiCPQTR (ORCPT ); Wed, 16 Mar 2022 12:19:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52254 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357441AbiCPQTQ (ORCPT ); Wed, 16 Mar 2022 12:19:16 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9374A12AFE; Wed, 16 Mar 2022 09:18:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647447481; x=1678983481; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=oc3o9zAraAEr29frHp+Jyf45oT9tTWsAvE/U0IEHF24=; b=O3qauNGYJOZg9rXslifNTtbK0ZmlumTNWtbpFY7GnfailPOpQJWx10Db CRIAEi6/Rr4RbebMaVzpvINPcVmR3TaMcGQTwvnaZvyzb8/sGBcejWZJ2 tyzgcEqshkC2dJblLObJB79gTD+O3tPr2e8lbVOc9b6I42E6VHYm/RNIM s=; Received: from unknown (HELO ironmsg03-sd.qualcomm.com) ([10.53.140.143]) by alexa-out-sd-01.qualcomm.com with ESMTP; 16 Mar 2022 09:18:00 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg03-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2022 09:17:59 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 09:17:59 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 09:17:52 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , , , , , , , , Linus Walleij , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v12 3/7] pinctrl: qcom: Update macro name to LPI specific Date: Wed, 16 Mar 2022 21:47:02 +0530 Message-ID: <1647447426-23425-4-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647447426-23425-1-git-send-email-quic_srivasam@quicinc.com> References: <1647447426-23425-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Update NO_SLEW macro to LPI_NO_SLEW macro as this driver lpi specific. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu Reviewed-by: Stephen Boyd Reviewed-by: Bjorn Andersson --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index 2f19ab4..3c15f80 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -40,7 +40,7 @@ #define LPI_GPIO_KEEPER 0x2 #define LPI_GPIO_PULL_UP 0x3 #define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1) -#define NO_SLEW -1 +#define LPI_NO_SLEW -1 #define LPI_FUNCTION(fname) \ [LPI_MUX_##fname] = { \ @@ -193,14 +193,14 @@ static const struct lpi_pingroup sm8250_groups[] = { LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _), - LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _), - LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _), - LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _), - LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, _, _), LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _), LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _), - LPI_PINGROUP(12, NO_SLEW, dmic3_clk, i2s2_data, _, _), - LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, _, _), }; static const struct lpi_function sm8250_functions[] = { @@ -435,7 +435,7 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group, } slew_offset = g->slew_offset; - if (slew_offset == NO_SLEW) + if (slew_offset == LPI_NO_SLEW) break; mutex_lock(&pctrl->slew_access_lock); From patchwork Wed Mar 16 16:17:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivasa Rao Mandadapu X-Patchwork-Id: 552811 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EE34C433FE for ; Wed, 16 Mar 2022 16:18:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357435AbiCPQT3 (ORCPT ); Wed, 16 Mar 2022 12:19:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52620 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357447AbiCPQTW (ORCPT ); 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Wed, 16 Mar 2022 09:18:06 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 09:17:59 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , , , , , , , , Linus Walleij , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v12 4/7] pinctrl: qcom: Update lpi pin group custiom functions with framework generic functions Date: Wed, 16 Mar 2022 21:47:03 +0530 Message-ID: <1647447426-23425-5-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647447426-23425-1-git-send-email-quic_srivasam@quicinc.com> References: <1647447426-23425-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Update custom pin group structure members with framework generic group_desc structure and replace the driver's custom pinctrl_ops with framework provided generic pin control group functions to avoid redundant code written in lpass lpi driver. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu --- drivers/pinctrl/qcom/Kconfig | 1 + drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 102 +++++++++++++++---------------- 2 files changed, 52 insertions(+), 51 deletions(-) diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index ca6f68a..31c4aa6 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -351,6 +351,7 @@ config PINCTRL_LPASS_LPI select PINMUX select PINCONF select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS depends on GPIOLIB help This is the pinctrl, pinmux, pinconf and gpiolib driver for the diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index 3c15f80..3228c45 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -51,11 +51,11 @@ #define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \ { \ - .name = "gpio" #id, \ - .pins = gpio##id##_pins, \ + .group.name = "gpio" #id, \ + .group.pins = gpio##id##_pins, \ .pin = id, \ .slew_offset = soff, \ - .npins = ARRAY_SIZE(gpio##id##_pins), \ + .group.num_pins = ARRAY_SIZE(gpio##id##_pins), \ .funcs = (int[]){ \ LPI_MUX_gpio, \ LPI_MUX_##f1, \ @@ -67,9 +67,7 @@ } struct lpi_pingroup { - const char *name; - const unsigned int *pins; - unsigned int npins; + struct group_desc group; unsigned int pin; /* Bit offset in slew register for SoundWire pins only */ int slew_offset; @@ -150,20 +148,20 @@ enum sm8250_lpi_functions { LPI_MUX__, }; -static const unsigned int gpio0_pins[] = { 0 }; -static const unsigned int gpio1_pins[] = { 1 }; -static const unsigned int gpio2_pins[] = { 2 }; -static const unsigned int gpio3_pins[] = { 3 }; -static const unsigned int gpio4_pins[] = { 4 }; -static const unsigned int gpio5_pins[] = { 5 }; -static const unsigned int gpio6_pins[] = { 6 }; -static const unsigned int gpio7_pins[] = { 7 }; -static const unsigned int gpio8_pins[] = { 8 }; -static const unsigned int gpio9_pins[] = { 9 }; -static const unsigned int gpio10_pins[] = { 10 }; -static const unsigned int gpio11_pins[] = { 11 }; -static const unsigned int gpio12_pins[] = { 12 }; -static const unsigned int gpio13_pins[] = { 13 }; +static int gpio0_pins[] = { 0 }; +static int gpio1_pins[] = { 1 }; +static int gpio2_pins[] = { 2 }; +static int gpio3_pins[] = { 3 }; +static int gpio4_pins[] = { 4 }; +static int gpio5_pins[] = { 5 }; +static int gpio6_pins[] = { 6 }; +static int gpio7_pins[] = { 7 }; +static int gpio8_pins[] = { 8 }; +static int gpio9_pins[] = { 9 }; +static int gpio10_pins[] = { 10 }; +static int gpio11_pins[] = { 11 }; +static int gpio12_pins[] = { 12 }; +static int gpio13_pins[] = { 13 }; static const char * const swr_tx_clk_groups[] = { "gpio0" }; static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" }; static const char * const swr_rx_clk_groups[] = { "gpio3" }; @@ -250,38 +248,10 @@ static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin, return 0; } -static int lpi_gpio_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - return pctrl->data->ngroups; -} - -static const char *lpi_gpio_get_group_name(struct pinctrl_dev *pctldev, - unsigned int group) -{ - struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - return pctrl->data->groups[group].name; -} - -static int lpi_gpio_get_group_pins(struct pinctrl_dev *pctldev, - unsigned int group, - const unsigned int **pins, - unsigned int *num_pins) -{ - struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - *pins = pctrl->data->groups[group].pins; - *num_pins = pctrl->data->groups[group].npins; - - return 0; -} - static const struct pinctrl_ops lpi_gpio_pinctrl_ops = { - .get_groups_count = lpi_gpio_get_groups_count, - .get_group_name = lpi_gpio_get_group_name, - .get_group_pins = lpi_gpio_get_group_pins, + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, .dt_node_to_map = pinconf_generic_dt_node_to_map_group, .dt_free_map = pinctrl_utils_free_map, }; @@ -582,6 +552,28 @@ static const struct gpio_chip lpi_gpio_template = { .dbg_show = lpi_gpio_dbg_show, }; +static int lpi_build_pin_desc_groups(struct lpi_pinctrl *pctrl) +{ + int i, ret; + + for (i = 0; i < pctrl->data->npins; i++) { + const struct pinctrl_pin_desc *pin_info = pctrl->desc.pins + i; + + ret = pinctrl_generic_add_group(pctrl->ctrl, pin_info->name, + (int *)&pin_info->number, 1, NULL); + if (ret < 0) + goto err_pinctrl; + } + + return 0; + +err_pinctrl: + for (; i > 0; i--) + pinctrl_generic_remove_group(pctrl->ctrl, i - 1); + + return ret; +} + static int lpi_pinctrl_probe(struct platform_device *pdev) { const struct lpi_pinctrl_variant_data *data; @@ -647,6 +639,10 @@ static int lpi_pinctrl_probe(struct platform_device *pdev) goto err_pinctrl; } + ret = lpi_build_pin_desc_groups(pctrl); + if (ret) + goto err_pinctrl; + ret = devm_gpiochip_add_data(dev, &pctrl->chip, pctrl); if (ret) { dev_err(pctrl->dev, "can't add gpio chip\n"); @@ -665,10 +661,14 @@ static int lpi_pinctrl_probe(struct platform_device *pdev) static int lpi_pinctrl_remove(struct platform_device *pdev) { struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev); + int i; mutex_destroy(&pctrl->slew_access_lock); clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks); + for (i = 0; i < pctrl->data->npins; i++) + pinctrl_generic_remove_group(pctrl->ctrl, i); + return 0; } From patchwork Wed Mar 16 16:17:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivasa Rao Mandadapu X-Patchwork-Id: 551949 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 129BCC43217 for ; Wed, 16 Mar 2022 16:18:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357442AbiCPQTa (ORCPT ); Wed, 16 Mar 2022 12:19:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357449AbiCPQT3 (ORCPT ); Wed, 16 Mar 2022 12:19:29 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5CE68DEB6; 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Wed, 16 Mar 2022 09:18:06 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , , , , , , , , Linus Walleij , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v12 5/7] pinctrl: qcom: Extract chip specific LPASS LPI code Date: Wed, 16 Mar 2022 21:47:04 +0530 Message-ID: <1647447426-23425-6-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647447426-23425-1-git-send-email-quic_srivasam@quicinc.com> References: <1647447426-23425-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Extract the chip specific SM8250 data from the LPASS LPI pinctrl driver to allow reusing the common code in the addition of subsequent platforms. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu --- drivers/pinctrl/qcom/Kconfig | 9 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 233 +----------------------- drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 85 +++++++++ drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c | 164 +++++++++++++++++ 5 files changed, 264 insertions(+), 228 deletions(-) create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.h create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 31c4aa6..486a1b5 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -329,6 +329,15 @@ config PINCTRL_SM8250 Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM8250 platform. +config PINCTRL_SM8250_LPASS_LPI + tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver" + depends on GPIOLIB + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SM8250 platform. + config PINCTRL_SM8350 tristate "Qualcomm Technologies Inc SM8350 pin controller driver" depends on PINCTRL_MSM diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 709882f..39650d6 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_PINCTRL_SM6350) += pinctrl-sm6350.o obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o +obj-$(CONFIG_PINCTRL_SM8250_LPASS_LPI) += pinctrl-sm8250-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o obj-$(CONFIG_PINCTRL_SM8450) += pinctrl-sm8450.o obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index 3228c45..717e937 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -4,91 +4,15 @@ * Copyright (c) 2020 Linaro Ltd. */ -#include -#include #include #include -#include #include #include -#include #include #include #include -#include -#include -#include -#include "../core.h" #include "../pinctrl-utils.h" - -#define LPI_SLEW_RATE_CTL_REG 0xa000 -#define LPI_TLMM_REG_OFFSET 0x1000 -#define LPI_SLEW_RATE_MAX 0x03 -#define LPI_SLEW_BITS_SIZE 0x02 -#define LPI_SLEW_RATE_MASK GENMASK(1, 0) -#define LPI_GPIO_CFG_REG 0x00 -#define LPI_GPIO_PULL_MASK GENMASK(1, 0) -#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2) -#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6) -#define LPI_GPIO_OE_MASK BIT(9) -#define LPI_GPIO_VALUE_REG 0x04 -#define LPI_GPIO_VALUE_IN_MASK BIT(0) -#define LPI_GPIO_VALUE_OUT_MASK BIT(1) - -#define LPI_GPIO_BIAS_DISABLE 0x0 -#define LPI_GPIO_PULL_DOWN 0x1 -#define LPI_GPIO_KEEPER 0x2 -#define LPI_GPIO_PULL_UP 0x3 -#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1) -#define LPI_NO_SLEW -1 - -#define LPI_FUNCTION(fname) \ - [LPI_MUX_##fname] = { \ - .name = #fname, \ - .groups = fname##_groups, \ - .ngroups = ARRAY_SIZE(fname##_groups), \ - } - -#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \ - { \ - .group.name = "gpio" #id, \ - .group.pins = gpio##id##_pins, \ - .pin = id, \ - .slew_offset = soff, \ - .group.num_pins = ARRAY_SIZE(gpio##id##_pins), \ - .funcs = (int[]){ \ - LPI_MUX_gpio, \ - LPI_MUX_##f1, \ - LPI_MUX_##f2, \ - LPI_MUX_##f3, \ - LPI_MUX_##f4, \ - }, \ - .nfuncs = 5, \ - } - -struct lpi_pingroup { - struct group_desc group; - unsigned int pin; - /* Bit offset in slew register for SoundWire pins only */ - int slew_offset; - unsigned int *funcs; - unsigned int nfuncs; -}; - -struct lpi_function { - const char *name; - const char * const *groups; - unsigned int ngroups; -}; - -struct lpi_pinctrl_variant_data { - const struct pinctrl_pin_desc *pins; - int npins; - const struct lpi_pingroup *groups; - int ngroups; - const struct lpi_function *functions; - int nfunctions; -}; +#include "pinctrl-lpass-lpi.h" #define MAX_LPI_NUM_CLKS 2 @@ -104,136 +28,6 @@ struct lpi_pinctrl { const struct lpi_pinctrl_variant_data *data; }; -/* sm8250 variant specific data */ -static const struct pinctrl_pin_desc sm8250_lpi_pins[] = { - PINCTRL_PIN(0, "gpio0"), - PINCTRL_PIN(1, "gpio1"), - PINCTRL_PIN(2, "gpio2"), - PINCTRL_PIN(3, "gpio3"), - PINCTRL_PIN(4, "gpio4"), - PINCTRL_PIN(5, "gpio5"), - PINCTRL_PIN(6, "gpio6"), - PINCTRL_PIN(7, "gpio7"), - PINCTRL_PIN(8, "gpio8"), - PINCTRL_PIN(9, "gpio9"), - PINCTRL_PIN(10, "gpio10"), - PINCTRL_PIN(11, "gpio11"), - PINCTRL_PIN(12, "gpio12"), - PINCTRL_PIN(13, "gpio13"), -}; - -enum sm8250_lpi_functions { - LPI_MUX_dmic1_clk, - LPI_MUX_dmic1_data, - LPI_MUX_dmic2_clk, - LPI_MUX_dmic2_data, - LPI_MUX_dmic3_clk, - LPI_MUX_dmic3_data, - LPI_MUX_i2s1_clk, - LPI_MUX_i2s1_data, - LPI_MUX_i2s1_ws, - LPI_MUX_i2s2_clk, - LPI_MUX_i2s2_data, - LPI_MUX_i2s2_ws, - LPI_MUX_qua_mi2s_data, - LPI_MUX_qua_mi2s_sclk, - LPI_MUX_qua_mi2s_ws, - LPI_MUX_swr_rx_clk, - LPI_MUX_swr_rx_data, - LPI_MUX_swr_tx_clk, - LPI_MUX_swr_tx_data, - LPI_MUX_wsa_swr_clk, - LPI_MUX_wsa_swr_data, - LPI_MUX_gpio, - LPI_MUX__, -}; - -static int gpio0_pins[] = { 0 }; -static int gpio1_pins[] = { 1 }; -static int gpio2_pins[] = { 2 }; -static int gpio3_pins[] = { 3 }; -static int gpio4_pins[] = { 4 }; -static int gpio5_pins[] = { 5 }; -static int gpio6_pins[] = { 6 }; -static int gpio7_pins[] = { 7 }; -static int gpio8_pins[] = { 8 }; -static int gpio9_pins[] = { 9 }; -static int gpio10_pins[] = { 10 }; -static int gpio11_pins[] = { 11 }; -static int gpio12_pins[] = { 12 }; -static int gpio13_pins[] = { 13 }; -static const char * const swr_tx_clk_groups[] = { "gpio0" }; -static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" }; -static const char * const swr_rx_clk_groups[] = { "gpio3" }; -static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; -static const char * const dmic1_clk_groups[] = { "gpio6" }; -static const char * const dmic1_data_groups[] = { "gpio7" }; -static const char * const dmic2_clk_groups[] = { "gpio8" }; -static const char * const dmic2_data_groups[] = { "gpio9" }; -static const char * const i2s2_clk_groups[] = { "gpio10" }; -static const char * const i2s2_ws_groups[] = { "gpio11" }; -static const char * const dmic3_clk_groups[] = { "gpio12" }; -static const char * const dmic3_data_groups[] = { "gpio13" }; -static const char * const qua_mi2s_sclk_groups[] = { "gpio0" }; -static const char * const qua_mi2s_ws_groups[] = { "gpio1" }; -static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" }; -static const char * const i2s1_clk_groups[] = { "gpio6" }; -static const char * const i2s1_ws_groups[] = { "gpio7" }; -static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" }; -static const char * const wsa_swr_clk_groups[] = { "gpio10" }; -static const char * const wsa_swr_data_groups[] = { "gpio11" }; -static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" }; - -static const struct lpi_pingroup sm8250_groups[] = { - LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), - LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), - LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), - LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), - LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), - LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _), - LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _), - LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _), - LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _), - LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, _, _), - LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _), - LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _), - LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _), - LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, _, _), -}; - -static const struct lpi_function sm8250_functions[] = { - LPI_FUNCTION(dmic1_clk), - LPI_FUNCTION(dmic1_data), - LPI_FUNCTION(dmic2_clk), - LPI_FUNCTION(dmic2_data), - LPI_FUNCTION(dmic3_clk), - LPI_FUNCTION(dmic3_data), - LPI_FUNCTION(i2s1_clk), - LPI_FUNCTION(i2s1_data), - LPI_FUNCTION(i2s1_ws), - LPI_FUNCTION(i2s2_clk), - LPI_FUNCTION(i2s2_data), - LPI_FUNCTION(i2s2_ws), - LPI_FUNCTION(qua_mi2s_data), - LPI_FUNCTION(qua_mi2s_sclk), - LPI_FUNCTION(qua_mi2s_ws), - LPI_FUNCTION(swr_rx_clk), - LPI_FUNCTION(swr_rx_data), - LPI_FUNCTION(swr_tx_clk), - LPI_FUNCTION(swr_tx_data), - LPI_FUNCTION(wsa_swr_clk), - LPI_FUNCTION(wsa_swr_data), -}; - -static struct lpi_pinctrl_variant_data sm8250_lpi_data = { - .pins = sm8250_lpi_pins, - .npins = ARRAY_SIZE(sm8250_lpi_pins), - .groups = sm8250_groups, - .ngroups = ARRAY_SIZE(sm8250_groups), - .functions = sm8250_functions, - .nfunctions = ARRAY_SIZE(sm8250_functions), -}; - static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, unsigned int addr) { @@ -574,7 +368,7 @@ static int lpi_build_pin_desc_groups(struct lpi_pinctrl *pctrl) return ret; } -static int lpi_pinctrl_probe(struct platform_device *pdev) +int lpi_pinctrl_probe(struct platform_device *pdev) { const struct lpi_pinctrl_variant_data *data; struct device *dev = &pdev->dev; @@ -657,8 +451,9 @@ static int lpi_pinctrl_probe(struct platform_device *pdev) return ret; } +EXPORT_SYMBOL_GPL(lpi_pinctrl_probe); -static int lpi_pinctrl_remove(struct platform_device *pdev) +int lpi_pinctrl_remove(struct platform_device *pdev) { struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev); int i; @@ -671,25 +466,7 @@ static int lpi_pinctrl_remove(struct platform_device *pdev) return 0; } +EXPORT_SYMBOL_GPL(lpi_pinctrl_remove); -static const struct of_device_id lpi_pinctrl_of_match[] = { - { - .compatible = "qcom,sm8250-lpass-lpi-pinctrl", - .data = &sm8250_lpi_data, - }, - { } -}; -MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); - -static struct platform_driver lpi_pinctrl_driver = { - .driver = { - .name = "qcom-lpass-lpi-pinctrl", - .of_match_table = lpi_pinctrl_of_match, - }, - .probe = lpi_pinctrl_probe, - .remove = lpi_pinctrl_remove, -}; - -module_platform_driver(lpi_pinctrl_driver); MODULE_DESCRIPTION("QTI LPI GPIO pin control driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h new file mode 100644 index 0000000..afbac2a --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020 Linaro Ltd. + */ +#ifndef __PINCTRL_LPASS_LPI_H__ +#define __PINCTRL_LPASS_LPI_H__ + +#include +#include +#include "../core.h" + +#define LPI_SLEW_RATE_CTL_REG 0xa000 +#define LPI_TLMM_REG_OFFSET 0x1000 +#define LPI_SLEW_RATE_MAX 0x03 +#define LPI_SLEW_BITS_SIZE 0x02 +#define LPI_SLEW_RATE_MASK GENMASK(1, 0) +#define LPI_GPIO_CFG_REG 0x00 +#define LPI_GPIO_PULL_MASK GENMASK(1, 0) +#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2) +#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6) +#define LPI_GPIO_OE_MASK BIT(9) +#define LPI_GPIO_VALUE_REG 0x04 +#define LPI_GPIO_VALUE_IN_MASK BIT(0) +#define LPI_GPIO_VALUE_OUT_MASK BIT(1) + +#define LPI_GPIO_BIAS_DISABLE 0x0 +#define LPI_GPIO_PULL_DOWN 0x1 +#define LPI_GPIO_KEEPER 0x2 +#define LPI_GPIO_PULL_UP 0x3 +#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1) +#define LPI_NO_SLEW -1 + +#define LPI_FUNCTION(fname) \ + [LPI_MUX_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \ + { \ + .group.name = "gpio" #id, \ + .group.pins = gpio##id##_pins, \ + .pin = id, \ + .slew_offset = soff, \ + .group.num_pins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + LPI_MUX_gpio, \ + LPI_MUX_##f1, \ + LPI_MUX_##f2, \ + LPI_MUX_##f3, \ + LPI_MUX_##f4, \ + }, \ + .nfuncs = 5, \ + } + +struct lpi_pingroup { + struct group_desc group; + unsigned int pin; + /* Bit offset in slew register for SoundWire pins only */ + int slew_offset; + unsigned int *funcs; + unsigned int nfuncs; +}; + +struct lpi_function { + const char *name; + const char * const *groups; + unsigned int ngroups; +}; + +struct lpi_pinctrl_variant_data { + const struct pinctrl_pin_desc *pins; + int npins; + const struct lpi_pingroup *groups; + int ngroups; + const struct lpi_function *functions; + int nfunctions; +}; + +int lpi_pinctrl_probe(struct platform_device *pdev); +int lpi_pinctrl_remove(struct platform_device *pdev); + +#endif /*__PINCTRL_LPASS_LPI_H__*/ diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c new file mode 100644 index 0000000..8c95d0f --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020 Linaro Ltd. + */ + +#include +#include +#include + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic1_clk, + LPI_MUX_dmic1_data, + LPI_MUX_dmic2_clk, + LPI_MUX_dmic2_data, + LPI_MUX_dmic3_clk, + LPI_MUX_dmic3_data, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_qua_mi2s_data, + LPI_MUX_qua_mi2s_sclk, + LPI_MUX_qua_mi2s_ws, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_data, + LPI_MUX_wsa_swr_clk, + LPI_MUX_wsa_swr_data, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static int gpio0_pins[] = { 0 }; +static int gpio1_pins[] = { 1 }; +static int gpio2_pins[] = { 2 }; +static int gpio3_pins[] = { 3 }; +static int gpio4_pins[] = { 4 }; +static int gpio5_pins[] = { 5 }; +static int gpio6_pins[] = { 6 }; +static int gpio7_pins[] = { 7 }; +static int gpio8_pins[] = { 8 }; +static int gpio9_pins[] = { 9 }; +static int gpio10_pins[] = { 10 }; +static int gpio11_pins[] = { 11 }; +static int gpio12_pins[] = { 12 }; +static int gpio13_pins[] = { 13 }; + +/* sm8250 variant specific data */ +static const struct pinctrl_pin_desc sm8250_lpi_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), +}; + +static const char * const swr_tx_clk_groups[] = { "gpio0" }; +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" }; +static const char * const swr_rx_clk_groups[] = { "gpio3" }; +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; +static const char * const dmic1_clk_groups[] = { "gpio6" }; +static const char * const dmic1_data_groups[] = { "gpio7" }; +static const char * const dmic2_clk_groups[] = { "gpio8" }; +static const char * const dmic2_data_groups[] = { "gpio9" }; +static const char * const i2s2_clk_groups[] = { "gpio10" }; +static const char * const i2s2_ws_groups[] = { "gpio11" }; +static const char * const dmic3_clk_groups[] = { "gpio12" }; +static const char * const dmic3_data_groups[] = { "gpio13" }; +static const char * const qua_mi2s_sclk_groups[] = { "gpio0" }; +static const char * const qua_mi2s_ws_groups[] = { "gpio1" }; +static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" }; +static const char * const i2s1_clk_groups[] = { "gpio6" }; +static const char * const i2s1_ws_groups[] = { "gpio7" }; +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" }; +static const char * const wsa_swr_clk_groups[] = { "gpio10" }; +static const char * const wsa_swr_data_groups[] = { "gpio11" }; +static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" }; + +static const struct lpi_pingroup sm8250_groups[] = { + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, _, _), + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _), + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, _, _), +}; + +static const struct lpi_function sm8250_functions[] = { + LPI_FUNCTION(dmic1_clk), + LPI_FUNCTION(dmic1_data), + LPI_FUNCTION(dmic2_clk), + LPI_FUNCTION(dmic2_data), + LPI_FUNCTION(dmic3_clk), + LPI_FUNCTION(dmic3_data), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(qua_mi2s_data), + LPI_FUNCTION(qua_mi2s_sclk), + LPI_FUNCTION(qua_mi2s_ws), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(wsa_swr_clk), + LPI_FUNCTION(wsa_swr_data), +}; + +static const struct lpi_pinctrl_variant_data sm8250_lpi_data = { + .pins = sm8250_lpi_pins, + .npins = ARRAY_SIZE(sm8250_lpi_pins), + .groups = sm8250_groups, + .ngroups = ARRAY_SIZE(sm8250_groups), + .functions = sm8250_functions, + .nfunctions = ARRAY_SIZE(sm8250_functions), +}; + +static const struct of_device_id lpi_pinctrl_of_match[] = { + { + .compatible = "qcom,sm8250-lpass-lpi-pinctrl", + .data = &sm8250_lpi_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static struct platform_driver lpi_pinctrl_driver = { + .driver = { + .name = "qcom-sm8250-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + }, + .probe = lpi_pinctrl_probe, + .remove = lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("QTI SM8250 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); From patchwork Wed Mar 16 16:17:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivasa Rao Mandadapu X-Patchwork-Id: 552810 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF9BDC4332F for ; Wed, 16 Mar 2022 16:18:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244259AbiCPQTm (ORCPT ); Wed, 16 Mar 2022 12:19:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357476AbiCPQTl (ORCPT ); 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Wed, 16 Mar 2022 09:18:19 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 09:18:13 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , , , , , , , , Linus Walleij , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v12 6/7] pinctrl: qcom: Add SC7280 lpass pin configuration Date: Wed, 16 Mar 2022 21:47:05 +0530 Message-ID: <1647447426-23425-7-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647447426-23425-1-git-send-email-quic_srivasam@quicinc.com> References: <1647447426-23425-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add pin control support for SC7280 LPASS LPI. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu --- drivers/pinctrl/qcom/Kconfig | 9 ++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 167 ++++++++++++++++++++++++ 3 files changed, 177 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 486a1b5..6c3657e 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -239,6 +239,15 @@ config PINCTRL_SC7280 Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SC7280 platform. +config PINCTRL_SC7280_LPASS_LPI + tristate "Qualcomm Technologies Inc SC7280 LPASS LPI pin controller driver" + depends on GPIOLIB + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SC7280 platform. + config PINCTRL_SC8180X tristate "Qualcomm Technologies Inc SC8180x pin controller driver" depends on (OF || ACPI) diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 39650d6..573e741 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o obj-$(CONFIG_PINCTRL_SC7280) += pinctrl-sc7280.o +obj-$(CONFIG_PINCTRL_SC7280_LPASS_LPI) += pinctrl-sc7280-lpass-lpi.o obj-$(CONFIG_PINCTRL_SC8180X) += pinctrl-sc8180x.o obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c new file mode 100644 index 0000000..d67ff25 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + * ALSA SoC platform-machine driver for QTi LPASS + */ + +#include +#include +#include + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic1_clk, + LPI_MUX_dmic1_data, + LPI_MUX_dmic2_clk, + LPI_MUX_dmic2_data, + LPI_MUX_dmic3_clk, + LPI_MUX_dmic3_data, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_qua_mi2s_data, + LPI_MUX_qua_mi2s_sclk, + LPI_MUX_qua_mi2s_ws, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_data, + LPI_MUX_wsa_swr_clk, + LPI_MUX_wsa_swr_data, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static int gpio0_pins[] = { 0 }; +static int gpio1_pins[] = { 1 }; +static int gpio2_pins[] = { 2 }; +static int gpio3_pins[] = { 3 }; +static int gpio4_pins[] = { 4 }; +static int gpio5_pins[] = { 5 }; +static int gpio6_pins[] = { 6 }; +static int gpio7_pins[] = { 7 }; +static int gpio8_pins[] = { 8 }; +static int gpio9_pins[] = { 9 }; +static int gpio10_pins[] = { 10 }; +static int gpio11_pins[] = { 11 }; +static int gpio12_pins[] = { 12 }; +static int gpio13_pins[] = { 13 }; +static int gpio14_pins[] = { 14 }; + +/* sc7280 variant specific data */ +static const struct pinctrl_pin_desc sc7280_lpi_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), +}; + +static const char * const swr_tx_clk_groups[] = { "gpio0" }; +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" }; +static const char * const swr_rx_clk_groups[] = { "gpio3" }; +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; +static const char * const dmic1_clk_groups[] = { "gpio6" }; +static const char * const dmic1_data_groups[] = { "gpio7" }; +static const char * const dmic2_clk_groups[] = { "gpio8" }; +static const char * const dmic2_data_groups[] = { "gpio9" }; +static const char * const i2s2_clk_groups[] = { "gpio10" }; +static const char * const i2s2_ws_groups[] = { "gpio11" }; +static const char * const dmic3_clk_groups[] = { "gpio12" }; +static const char * const dmic3_data_groups[] = { "gpio13" }; +static const char * const qua_mi2s_sclk_groups[] = { "gpio0" }; +static const char * const qua_mi2s_ws_groups[] = { "gpio1" }; +static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" }; +static const char * const i2s1_clk_groups[] = { "gpio6" }; +static const char * const i2s1_ws_groups[] = { "gpio7" }; +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" }; +static const char * const wsa_swr_clk_groups[] = { "gpio10" }; +static const char * const wsa_swr_data_groups[] = { "gpio11" }; +static const char * const i2s2_data_groups[] = { "gpio12", "gpio13" }; + +static const struct lpi_pingroup sc7280_groups[] = { + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(5, 12, swr_rx_data, _, _, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, _, _), + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _), + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, _, _), + LPI_PINGROUP(14, 6, swr_tx_data, _, _, _), +}; + +static const struct lpi_function sc7280_functions[] = { + LPI_FUNCTION(dmic1_clk), + LPI_FUNCTION(dmic1_data), + LPI_FUNCTION(dmic2_clk), + LPI_FUNCTION(dmic2_data), + LPI_FUNCTION(dmic3_clk), + LPI_FUNCTION(dmic3_data), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(qua_mi2s_data), + LPI_FUNCTION(qua_mi2s_sclk), + LPI_FUNCTION(qua_mi2s_ws), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(wsa_swr_clk), + LPI_FUNCTION(wsa_swr_data), +}; + +static const struct lpi_pinctrl_variant_data sc7280_lpi_data = { + .pins = sc7280_lpi_pins, + .npins = ARRAY_SIZE(sc7280_lpi_pins), + .groups = sc7280_groups, + .ngroups = ARRAY_SIZE(sc7280_groups), + .functions = sc7280_functions, + .nfunctions = ARRAY_SIZE(sc7280_functions), +}; + +static const struct of_device_id lpi_pinctrl_of_match[] = { + { + .compatible = "qcom,sc7280-lpass-lpi-pinctrl", + .data = &sc7280_lpi_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static struct platform_driver lpi_pinctrl_driver = { + .driver = { + .name = "qcom-sc7280-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + }, + .probe = lpi_pinctrl_probe, + .remove = lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("QTI SC7280 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); From patchwork Wed Mar 16 16:17:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivasa Rao Mandadapu X-Patchwork-Id: 551948 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0C54C433F5 for ; Wed, 16 Mar 2022 16:18:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357460AbiCPQTv (ORCPT ); Wed, 16 Mar 2022 12:19:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357483AbiCPQTu (ORCPT ); Wed, 16 Mar 2022 12:19:50 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EBE072A730; Wed, 16 Mar 2022 09:18:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647447507; x=1678983507; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=P09KFJBhosL0gRzmWoJn0ZVYvPQeqeJkftNXKvDXo3Q=; b=Gpi2kGv/3tvNjzkvLQvCDw0lSSFy123VHOaO31UN+UjFh0CNrru+x5cP Af2tr+kQc4rHpykua2n6w/TI5z4Fq3JVGbaFog0Q5t0EL3i3pEROYC2qp mnlQqz20YIBSFWDIS24h5OPJJHsh4DNvumA4kzZOOuKdxECCBg2O296f2 8=; Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-02.qualcomm.com with ESMTP; 16 Mar 2022 09:18:27 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg02-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2022 09:18:26 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 09:18:26 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 09:18:19 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , , , , , , , , Linus Walleij , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v12 7/7] pinctrl: qcom: Update clock voting as optional Date: Wed, 16 Mar 2022 21:47:06 +0530 Message-ID: <1647447426-23425-8-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647447426-23425-1-git-send-email-quic_srivasam@quicinc.com> References: <1647447426-23425-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Update bulk clock voting to optional voting as ADSP bypass platform doesn't need macro and decodec clocks, as these macro and dcodec GDSC switches are maintained as power domains and operated from lpass clock drivers. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu Reviewed-by: Matthias Kaehlcke --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 8 ++++++-- drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 1 + drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 1 + 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index 717e937..74810ec 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -401,9 +401,13 @@ int lpi_pinctrl_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(pctrl->slew_base), "Slew resource not provided\n"); - ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks); + if (data->is_clk_optional) + ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks); + else + ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks); + if (ret) - return dev_err_probe(dev, ret, "Can't get clocks\n"); + return ret; ret = clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks); if (ret) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h index afbac2a..759d5d8 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h @@ -77,6 +77,7 @@ struct lpi_pinctrl_variant_data { int ngroups; const struct lpi_function *functions; int nfunctions; + bool is_clk_optional; }; int lpi_pinctrl_probe(struct platform_device *pdev); diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c index d67ff25..97a653c 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c @@ -142,6 +142,7 @@ static const struct lpi_pinctrl_variant_data sc7280_lpi_data = { .ngroups = ARRAY_SIZE(sc7280_groups), .functions = sc7280_functions, .nfunctions = ARRAY_SIZE(sc7280_functions), + .is_clk_optional = true, }; static const struct of_device_id lpi_pinctrl_of_match[] = {