From patchwork Thu Mar 17 22:35:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alvin_=C5=A0ipraga?= X-Patchwork-Id: 552733 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9861C433EF for ; Thu, 17 Mar 2022 22:36:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229441AbiCQWhX (ORCPT ); Thu, 17 Mar 2022 18:37:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229706AbiCQWhW (ORCPT ); Thu, 17 Mar 2022 18:37:22 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ECCE1262401 for ; Thu, 17 Mar 2022 15:36:04 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id ja24so8257361ejc.11 for ; Thu, 17 Mar 2022 15:36:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pqrs.dk; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=4wQ3zFfpd7aREXFgNk3LcUxheQc887/bs/gFwojIv5w=; b=bbmP/CH9YWdv5RN9DFGh3+DhWMX5vZKzWLaRzuRD69bBJbMDfp3A5+DuNauUlcKFN2 xkDNTW2xf0JiXSzNzquWotsdP8NztbCh2MNuzkvg/ldIla36tA4Fhlk1dicLucSMoggz fhhxLvFurR5XjwRk+ZEYOxN3DdaI1BBOxsJ88= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=4wQ3zFfpd7aREXFgNk3LcUxheQc887/bs/gFwojIv5w=; b=5SEwUIx6v6JAQrGxyvy6Ak9p3xO7Nuf7RweC7plAtFVagxlmYVTRfdpwRDLhUU/m2X dv4f/m9oR6rW1Kj0XSTnTvQX5aL440LGeAn9Bql35X6cSSp+c0uTz/+RnzT3O5ZRiOJ5 y53FeTJ/JuraXqQ98Kwbv/OdfS8Je7FFySNehkdMxf2nGE/WHfQEEm1ytoKG/SkkNl6B s1ToXMrQ+Q3AP6E00PWOvxNldGbMXx3zx51yOgLoQET3UfIxgUqjj1IemCWz3oD/wH7T vYS8UqvT4jTsjFwgBm6x3XwZfLUUOBTJ5PTgrq1K4gH/ImhWfTAu1U05g9AGrkYJZwfH Zk8g== X-Gm-Message-State: AOAM5318xT1XrFMoRe5DkxzQ4vahW3jqeP7IrfvWnO4/hWdHVWK3JJ0F zHFMiPft88EEuNk2vRFGG2JaWw== X-Google-Smtp-Source: ABdhPJwvcUtOkBafEEKnF/3EG0RSqIIckpy4W7SlIRZOyBnbssw7to5m/58/k2mkz+ZAdb5WP6KPNQ== X-Received: by 2002:a17:907:2d10:b0:6db:e3f7:2cb2 with SMTP id gs16-20020a1709072d1000b006dbe3f72cb2mr6473181ejc.491.1647556563328; Thu, 17 Mar 2022 15:36:03 -0700 (PDT) Received: from capella.. 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[80.71.142.18]) by smtp.gmail.com with ESMTPSA id ec21-20020a170906b6d500b006d170a3444csm2893669ejb.164.2022.03.17.15.36.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Mar 2022 15:36:02 -0700 (PDT) From: =?utf-8?q?Alvin_=C5=A0ipraga?= To: Abel Vesa , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Rob Herring Cc: =?utf-8?q?Alvin_=C5=A0ipraga?= , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 1/2] dt-bindings: imx: add clock bindings for i.MX8MN GPT Date: Thu, 17 Mar 2022 23:35:58 +0100 Message-Id: <20220317223600.175894-1-alvin@pqrs.dk> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Alvin Šipraga The i.MX8MN has a General Purpose Timer (GPT) just like the i.MX8MM, which already has such bindings. Add the relevant bindings for the Nano SoC too. Signed-off-by: Alvin Šipraga Acked-by: Krzysztof Kozlowski --- v1->v2: no changes --- include/dt-bindings/clock/imx8mn-clock.h | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h index 01e8bab1d767..07b8a282c268 100644 --- a/include/dt-bindings/clock/imx8mn-clock.h +++ b/include/dt-bindings/clock/imx8mn-clock.h @@ -243,6 +243,20 @@ #define IMX8MN_CLK_M7_CORE 221 -#define IMX8MN_CLK_END 222 +#define IMX8MN_CLK_GPT_3M 222 +#define IMX8MN_CLK_GPT1 223 +#define IMX8MN_CLK_GPT1_ROOT 224 +#define IMX8MN_CLK_GPT2 225 +#define IMX8MN_CLK_GPT2_ROOT 226 +#define IMX8MN_CLK_GPT3 227 +#define IMX8MN_CLK_GPT3_ROOT 228 +#define IMX8MN_CLK_GPT4 229 +#define IMX8MN_CLK_GPT4_ROOT 230 +#define IMX8MN_CLK_GPT5 231 +#define IMX8MN_CLK_GPT5_ROOT 232 +#define IMX8MN_CLK_GPT6 233 +#define IMX8MN_CLK_GPT6_ROOT 234 + +#define IMX8MN_CLK_END 235 #endif From patchwork Thu Mar 17 22:35:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alvin_=C5=A0ipraga?= X-Patchwork-Id: 552301 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DF74C433FE for ; Thu, 17 Mar 2022 22:36:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229803AbiCQWhY (ORCPT ); Thu, 17 Mar 2022 18:37:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229744AbiCQWhX (ORCPT ); Thu, 17 Mar 2022 18:37:23 -0400 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C62C26243B for ; Thu, 17 Mar 2022 15:36:06 -0700 (PDT) Received: by mail-ed1-x534.google.com with SMTP id m12so8251910edc.12 for ; Thu, 17 Mar 2022 15:36:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pqrs.dk; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HUL7G4oOlZT6ZcSm0IypZD6C9fq3wHaBrHnjH9uPtcY=; b=bOpNBvfhoMLPtp0GDUuHsUff1/qKx7bzkXyoF5Zx6VrrBO7q8B/4cX0+mN+37dIlox YDHDC3DUdzKD6KtoOLORcZI+L02IV30xfDP2fyJVAOFAvwEAfRdeBB0SLBTxlgcLr9SP 8GPEgGFswgaPIY1nVGh1/EI3Z6p8SGhW3wnGU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HUL7G4oOlZT6ZcSm0IypZD6C9fq3wHaBrHnjH9uPtcY=; b=H9cMiEGE0669t9+z6Rn75TYIwnZdJd0Vz8EwCdsXhm4u1RDD3ZEoe0df92qOegh6rD eDGrVMbLNKivBBk51ux+bhvGs31vo02HAE3WhWBKvWLLraIAMvYCQ/u3sSgPfyv9XrQ+ zxllzttMSYTSlKHqx9AIrlQUjYwRehglkT4SpnUdG918tq7q66FPbyBynr4ankp1sp1R tUEQIGXJWAefksyhGBAN62vBCOlN28Yk5KpbVtg4jzWl100E4x5HvyFz0HqBVy4Xf0cw F9IJ4Woyc8YfwYeUq1z3SgLo2L+3dYOd8FX6nnOUn134wmDexQW72lKsS1wA4csAZf/d 3Miw== X-Gm-Message-State: AOAM5331QR4Wx2r9rE7+9570nMeiAhCpV3CZMnTa/uFfAUR4zPIfZY6l pMuZOfot2Hry9L6/VJGGRLdnAw== X-Google-Smtp-Source: ABdhPJydOD9qsL8/+g218ELmo+ZGkUSYcQYHwl3QeH92QppgAMEA4so62K4IOG1KKTFJ4W9Zx4CqFw== X-Received: by 2002:aa7:cb0f:0:b0:416:201f:c64d with SMTP id s15-20020aa7cb0f000000b00416201fc64dmr6798503edt.48.1647556565058; Thu, 17 Mar 2022 15:36:05 -0700 (PDT) Received: from capella.. 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[80.71.142.18]) by smtp.gmail.com with ESMTPSA id ec21-20020a170906b6d500b006d170a3444csm2893669ejb.164.2022.03.17.15.36.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Mar 2022 15:36:04 -0700 (PDT) From: =?utf-8?q?Alvin_=C5=A0ipraga?= To: Abel Vesa , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Rob Herring Cc: =?utf-8?q?Alvin_=C5=A0ipraga?= , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 2/2] clk: imx8mn: add GPT support Date: Thu, 17 Mar 2022 23:35:59 +0100 Message-Id: <20220317223600.175894-2-alvin@pqrs.dk> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220317223600.175894-1-alvin@pqrs.dk> References: <20220317223600.175894-1-alvin@pqrs.dk> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Alvin Šipraga Add support for the General Purpose Timer (GPT) clocks on the i.MX8MN. The i.MX8MN GPT IP block is the same as on the i.MX8MM, on which this patch is based. Signed-off-by: Alvin Šipraga --- v1->v2: for reasons of consistency, change lines of the form: static const char *const imx8mn_gpt... to static const char * const imx8mn_gpt... and adjust the indentation accordingly. --- drivers/clk/imx/clk-imx8mn.c | 38 ++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 92fcbab4f5be..fb058cb38c27 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -227,6 +227,30 @@ static const char * const imx8mn_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys "sys_pll1_40m", "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", }; +static const char * const imx8mn_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", + "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "audio_pll1_out", "clk_ext1", }; + +static const char * const imx8mn_gpt2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", + "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "audio_pll1_out", "clk_ext1", }; + +static const char * const imx8mn_gpt3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", + "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "audio_pll1_out", "clk_ext1", }; + +static const char * const imx8mn_gpt4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", + "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "audio_pll1_out", "clk_ext1", }; + +static const char * const imx8mn_gpt5_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", + "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "audio_pll1_out", "clk_ext1", }; + +static const char * const imx8mn_gpt6_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", + "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "audio_pll1_out", "clk_ext1", }; + static const char * const imx8mn_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", }; @@ -476,6 +500,12 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) hws[IMX8MN_CLK_PWM2] = imx8m_clk_hw_composite("pwm2", imx8mn_pwm2_sels, base + 0xb400); hws[IMX8MN_CLK_PWM3] = imx8m_clk_hw_composite("pwm3", imx8mn_pwm3_sels, base + 0xb480); hws[IMX8MN_CLK_PWM4] = imx8m_clk_hw_composite("pwm4", imx8mn_pwm4_sels, base + 0xb500); + hws[IMX8MN_CLK_GPT1] = imx8m_clk_hw_composite("gpt1", imx8mn_gpt1_sels, base + 0xb580); + hws[IMX8MN_CLK_GPT2] = imx8m_clk_hw_composite("gpt2", imx8mn_gpt2_sels, base + 0xb600); + hws[IMX8MN_CLK_GPT3] = imx8m_clk_hw_composite("gpt3", imx8mn_gpt3_sels, base + 0xb680); + hws[IMX8MN_CLK_GPT4] = imx8m_clk_hw_composite("gpt4", imx8mn_gpt4_sels, base + 0xb700); + hws[IMX8MN_CLK_GPT5] = imx8m_clk_hw_composite("gpt5", imx8mn_gpt5_sels, base + 0xb780); + hws[IMX8MN_CLK_GPT6] = imx8m_clk_hw_composite("gpt6", imx8mn_gpt6_sels, base + 0xb800); hws[IMX8MN_CLK_WDOG] = imx8m_clk_hw_composite("wdog", imx8mn_wdog_sels, base + 0xb900); hws[IMX8MN_CLK_WRCLK] = imx8m_clk_hw_composite("wrclk", imx8mn_wrclk_sels, base + 0xb980); hws[IMX8MN_CLK_CLKO1] = imx8m_clk_hw_composite("clko1", imx8mn_clko1_sels, base + 0xba00); @@ -501,6 +531,12 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) hws[IMX8MN_CLK_GPIO3_ROOT] = imx_clk_hw_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0); hws[IMX8MN_CLK_GPIO4_ROOT] = imx_clk_hw_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0); hws[IMX8MN_CLK_GPIO5_ROOT] = imx_clk_hw_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0); + hws[IMX8MN_CLK_GPT1_ROOT] = imx_clk_hw_gate4("gpt1_root_clk", "gpt1", base + 0x4100, 0); + hws[IMX8MN_CLK_GPT2_ROOT] = imx_clk_hw_gate4("gpt2_root_clk", "gpt2", base + 0x4110, 0); + hws[IMX8MN_CLK_GPT3_ROOT] = imx_clk_hw_gate4("gpt3_root_clk", "gpt3", base + 0x4120, 0); + hws[IMX8MN_CLK_GPT4_ROOT] = imx_clk_hw_gate4("gpt4_root_clk", "gpt4", base + 0x4130, 0); + hws[IMX8MN_CLK_GPT5_ROOT] = imx_clk_hw_gate4("gpt5_root_clk", "gpt5", base + 0x4140, 0); + hws[IMX8MN_CLK_GPT6_ROOT] = imx_clk_hw_gate4("gpt6_root_clk", "gpt6", base + 0x4150, 0); hws[IMX8MN_CLK_I2C1_ROOT] = imx_clk_hw_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0); hws[IMX8MN_CLK_I2C2_ROOT] = imx_clk_hw_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0); hws[IMX8MN_CLK_I2C3_ROOT] = imx_clk_hw_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0); @@ -549,6 +585,8 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) hws[IMX8MN_CLK_SDMA3_ROOT] = imx_clk_hw_gate4("sdma3_clk", "ipg_audio_root", base + 0x45f0, 0); hws[IMX8MN_CLK_SAI7_ROOT] = imx_clk_hw_gate2_shared2("sai7_root_clk", "sai7", base + 0x4650, 0, &share_count_sai7); + hws[IMX8MN_CLK_GPT_3M] = imx_clk_hw_fixed_factor("gpt_3m", "osc_24m", 1, 8); + hws[IMX8MN_CLK_DRAM_ALT_ROOT] = imx_clk_hw_fixed_factor("dram_alt_root", "dram_alt", 1, 4); hws[IMX8MN_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core",