From patchwork Fri Dec 7 10:36:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153115 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp339065ljp; Fri, 7 Dec 2018 02:42:27 -0800 (PST) X-Google-Smtp-Source: AFSGD/V2rxpurbMYCp9BEJfYP9GmVa0NWMpQpMmNuQIXCPShOJWunGGllXwkMTRWm14MPwYVe/j0 X-Received: by 2002:ae9:dc43:: with SMTP id q64mr1263091qkf.223.1544179347270; Fri, 07 Dec 2018 02:42:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544179347; cv=none; d=google.com; s=arc-20160816; b=K9luNUkQ0sjn/eDgyu0/M0yPua2exYgLkb4FHKLzC8tnRprVAJWk3rHF/ukAmDvF6g l7jF92qppqZlF1WW8B91LKZu52EyM2Ww2dvekXFJfwRAZuKPHx57NQBYDCNsTz+cbCRB yjneTa31jQtZeU8eKcS4r3tx3TiJFkoWAWBB0grC5mjEwEtyMjfpIs81W0TqNlHXgaQP mJkRS8KO52W1vo2MagDFlzokt7lp8Yp41dOpPK6d2frOwt2oZMeZ4WZi0tH13/WI4cqF J8DAw6iri/VDHOCAszS0+Zp4JSmw2c5zsOBK/jBBeGFWxfPNbmWyqeR3sBtJKjd4Mhis /f/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=HgpwYWOjnTKJPAwYxN7qb31pNdMDM+2fBnsO5Kh5Myc=; b=Srrly7VA3PmYVZr669BeojiZpVom0XxMqMXor//Aoa8IngJLf0ldQ8NcKMOSBfbch2 mj/neendI8MB5g4iXJzY59Hg+rpmO0rUvCPnSD+BihdKoihdK/y+3O1s18JGIYKDHsjt Bc+ZWTgaIh1XdvY97oaD08okNP+xAJCmai7Holgw+zMDw7MM+Y+sdoazpm8M2YXox2Nh E7O7uJySgJWDPszpv9FAhdgF14Voc6BRLzmzprfaefCR759zw278diLM8FMyFEhDBPBs WCyVCwuKRg1TuORaCQOUcBKU/qufWdFLh9UVlz3hmkjpFd7RTbEgyf4qdS202hNiX2pJ eZew== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="Bfd5FKR/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id p68si1938967qkc.74.2018.12.07.02.42.27 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 07 Dec 2018 02:42:27 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="Bfd5FKR/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45275 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDaU-000622-KH for patch@linaro.org; Fri, 07 Dec 2018 05:42:26 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58998) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDUv-0007xn-Qo for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVDUt-0007C8-63 for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:41 -0500 Received: from mail-ot1-x343.google.com ([2607:f8b0:4864:20::343]:44469) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gVDUt-0007BU-0I for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:39 -0500 Received: by mail-ot1-x343.google.com with SMTP id f18so3327754otl.11 for ; Fri, 07 Dec 2018 02:36:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HgpwYWOjnTKJPAwYxN7qb31pNdMDM+2fBnsO5Kh5Myc=; b=Bfd5FKR/Dser8u9KpcJkcdczXE4MeN4y63yADm37Y2Xv0s6rQW8j5UDE44FFjfw0ve 8GuwMvHNz7H8HexAvqY2BGucJ7VfO9KwjPFL3DU/CF63uJqn8Gsj20or2WfkJpuvjcOt 0jmJPcu9U4TyPTZywzpnnRn9Oejh/0UhKFJgI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HgpwYWOjnTKJPAwYxN7qb31pNdMDM+2fBnsO5Kh5Myc=; b=dcvSZgyXICdfgxPo3xzkbHPSPRTtGGzpYNTWZelralX+ZjRnlMv4Q1u+cZVl5LbzJX wqOdme7q03n3Mau5qlD3zLwoU/QvsoY57DHBIOD/7p8nmkv3zAmY1RHLbHzYSmsYPiGw LMhV3EvQEJTz8MbSWr06B7jd4ma2lPrTN8UZs8Kio2+Jr9mt6VHuaTgBr/Bwl4ldN0yi LnXzGJ9EG7aVjohLEB7u4tXaViHFhkkB4I/nK2L7QvuOh3DHPeeDj6lEqDSw1KpO0jBf +gTpf/5y7jaRHgyddEqreVmD+6PBKLDt+95Dg+M9cgSQguzCwlxE7xvFeQ3BWT7eIJvb yd8A== X-Gm-Message-State: AA+aEWZW66bRuCIAXYGF6v1EYMSUVJKmhhsmEDhOLL4e/M5os6SvAGBp b4hn9eC1c5JSba5R0cdAf0yDLsr65MA= X-Received: by 2002:a9d:5549:: with SMTP id h9mr998378oti.83.1544178997922; Fri, 07 Dec 2018 02:36:37 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.36.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:36:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:06 -0600 Message-Id: <20181207103631.28193-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org> References: <20181207103631.28193-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::343 Subject: [Qemu-devel] [PATCH 01/26] target/arm: Add state for the ARMv8.3-PAuth extension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add storage space for the 5 encryption keys. Migrate them when the extension is enabled. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 23 +++++++++++++++++++++++ target/arm/machine.c | 23 +++++++++++++++++++++++ 2 files changed, 46 insertions(+) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c943f35dd9..0766e32a1b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -605,6 +605,14 @@ typedef struct CPUARMState { uint32_t cregs[16]; } iwmmxt; +#ifdef TARGET_AARCH64 + uint64_t apia_key[2]; + uint64_t apib_key[2]; + uint64_t apda_key[2]; + uint64_t apdb_key[2]; + uint64_t apga_key[2]; +#endif + #if defined(CONFIG_USER_ONLY) /* For usermode syscall translation. */ int eabi; @@ -3324,6 +3332,21 @@ static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; } +static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) +{ + /* + * Note that while QEMU will only implement the architected algorithm + * QARMA, and thus APA+GPA, the host cpu for kvm may use implementation + * defined algorithms, and thus API+GPI, and this predicate controls + * migration of the 128-bit keys. + */ + return (id->id_aa64isar1 & + (FIELD_DP64(0, ID_AA64ISAR1, APA, -1) | + FIELD_DP64(0, ID_AA64ISAR1, API, -1) | + FIELD_DP64(0, ID_AA64ISAR1, GPA, -1) | + FIELD_DP64(0, ID_AA64ISAR1, GPI, -1))) != 0; +} + static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically wrt FP16. */ diff --git a/target/arm/machine.c b/target/arm/machine.c index 7a22ebc209..340b36084c 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -169,6 +169,28 @@ static const VMStateDescription vmstate_sve = { VMSTATE_END_OF_LIST() } }; + +static bool pauth_needed(void *opaque) +{ + ARMCPU *cpu = opaque; + + return cpu_isar_feature(aa64_pauth, cpu); +} + +static const VMStateDescription vmstate_pauth = { + .name = "cpu/pauth", + .version_id = 1, + .minimum_version_id = 1, + .needed = pauth_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT64_ARRAY(env.apia_key, ARMCPU, 2), + VMSTATE_UINT64_ARRAY(env.apib_key, ARMCPU, 2), + VMSTATE_UINT64_ARRAY(env.apda_key, ARMCPU, 2), + VMSTATE_UINT64_ARRAY(env.apdb_key, ARMCPU, 2), + VMSTATE_UINT64_ARRAY(env.apga_key, ARMCPU, 2), + VMSTATE_END_OF_LIST() + } +}; #endif /* AARCH64 */ static bool serror_needed(void *opaque) @@ -795,6 +817,7 @@ const VMStateDescription vmstate_arm_cpu = { &vmstate_m_security, #ifdef TARGET_AARCH64 &vmstate_sve, + &vmstate_pauth, #endif &vmstate_serror, &vmstate_irq_line_state, From patchwork Fri Dec 7 10:36:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153110 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp336933ljp; Fri, 7 Dec 2018 02:39:39 -0800 (PST) X-Google-Smtp-Source: AFSGD/U+j34unCootQjYBjdF5Oirfwf6dMeOWuvsz6J849iwZ1WJE+d1z+eMpvSkt8zsD4nNRwHs X-Received: by 2002:a37:11dd:: with SMTP id 90mr1292764qkr.212.1544179179602; Fri, 07 Dec 2018 02:39:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544179179; cv=none; d=google.com; s=arc-20160816; b=IglOeEPFV5FXBh5K3VKnTDDsA7Z/xJ2z/KLMqsgofE896HXQogZvD5gwdbcoJepmU7 FBGJf9wVEAE9bYsL3un7XwlKLB/KZOlrklMw5/L9/A2xfBYfyuMmdruonEvL6BhFOzvl ryLIgdcgtQZ1EA95y6lD/dtp80XiEq3W/w5B9wp1OEus7duDkrnTMqmrj4r16Kk0R6Rf OUToTycVbQunFfjT/mJhF/kKWVRQq/t+8xstm/vL0cPz4MxZN51o0TNvjAAuZ/Ka57hA qV22cix0tvQcazxSk1rNznAYwXgT0II2Jp3h9Ie8sSfUHFDAyUdfqm+E9XCMcFcXImXW gktA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=1zHtqPqQuOVDqUCs4QxzsY6N+zhmBLTZdXVbBYN1Xvk=; b=Ld7hwMPSm7zN+hEioXVV7HgU5z87k1rblpJsVEgaH5U2cZtCzNqhALylDpJ7Z/4SG+ u3nRq6Q9IQw479RpOawx4gjRv9lRJM2r2skH8WqKaZztRiZHYmmEx9VPaLZ6sQCLw1UU 840oVvqW6UmVi4kdoOXNtGZeox+99sC9uAtsP0HoZEji0O3OTVYU1IN75er4e9Oqrmaw AA43JC+HAzBPttz4J+ijy4dwTzBybEasXZn0FtbF8JQBkrr+wE7agEKPJUG2Cmcj3kxz WVCEP9pseGaEwrbG1eLpK1cOyvraNLT+Og8KRi5XCuxUzWtSEDUr6koczP9UfjyW0KDF l/Kw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="L+I/Y/lH"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id z63si1571732qkc.262.2018.12.07.02.39.39 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 07 Dec 2018 02:39:39 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="L+I/Y/lH"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45257 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDXm-0003bV-UD for patch@linaro.org; Fri, 07 Dec 2018 05:39:38 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58996) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDUv-0007xm-Pw for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVDUu-0007DG-Gc for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:41 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:40167) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gVDUu-0007Cr-Bi for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:40 -0500 Received: by mail-oi1-x241.google.com with SMTP id t204so2988754oie.7 for ; Fri, 07 Dec 2018 02:36:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1zHtqPqQuOVDqUCs4QxzsY6N+zhmBLTZdXVbBYN1Xvk=; b=L+I/Y/lHiCMpqsGSRj7LuBUKiWWLolBC0Lloy5Bl/MlAwHj4hrXlasCJh1ogY+xjBq 8t9NmbHZLAjSrPUQrtGBnGGrjK8PC0hTj9VTaNzazesyrQTzKN29A31DqXoA6A3v5tkp /R9UPxttkzGs00ZwiTEH7ok2+w6ab2GMcq+QQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1zHtqPqQuOVDqUCs4QxzsY6N+zhmBLTZdXVbBYN1Xvk=; b=YkuVGP5aJVwZsBiBRkLUfs6k+DbzTVydTv/CarSkVUGDeE5QajjgQsaCEx5iq7O3uW sHtMTTYIKSVART/QCBy5/NZNOuLNT/nMvXlSZ8t1PX8KKMoHNHTxZJPIJqFzSknvo7Dw 9Tm04HHPa0DBhnz7LmQjAfegBvfh0nfQ4cp+LLtykDgViSZMz4U2AWwuTuzousZeppaB ymtJfSC6eZTcF9hnHUZdm0Ou/HdaoglpjUoDuPQzC6RgSVD5eCCcr1EQIvTqf9PrB9lA MAPQz/OWzmPIZZ5avygbXpCjDolLqm8BnAhFP+5VpqoUT+V4gAXRu8KAJG+Wp0dkWpMm 16qg== X-Gm-Message-State: AA+aEWYHE3rrV9MvDI2oBBQXOBoVLFDc7aorlfPy5N2rk1oFA8XFyX6X vsdGTbVPfHdiOXeFeNc26w2HGF+FPio= X-Received: by 2002:aca:5406:: with SMTP id i6mr948508oib.344.1544178999338; Fri, 07 Dec 2018 02:36:39 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.36.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:36:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:07 -0600 Message-Id: <20181207103631.28193-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org> References: <20181207103631.28193-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 Subject: [Qemu-devel] [PATCH 02/26] target/arm: Add SCTLR bits through ARMv8.5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Post v8.4 bits taken from SysReg_v85_xml-00bet8. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 40 +++++++++++++++++++++++++++++----------- 1 file changed, 29 insertions(+), 11 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0766e32a1b..80d65866c6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -984,12 +984,14 @@ void pmccntr_sync(CPUARMState *env); #define SCTLR_A (1U << 1) #define SCTLR_C (1U << 2) #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ -#define SCTLR_SA (1U << 3) +#define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ +#define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ +#define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ #define SCTLR_ITD (1U << 7) /* v8 onward */ #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ @@ -997,35 +999,51 @@ void pmccntr_sync(CPUARMState *env); #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ #define SCTLR_F (1U << 10) /* up to v6 */ -#define SCTLR_SW (1U << 10) /* v7 onward */ -#define SCTLR_Z (1U << 11) +#define SCTLR_SW (1U << 10) /* v7, RES0 in v8 */ +#define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ #define SCTLR_I (1U << 12) -#define SCTLR_V (1U << 13) +#define SCTLR_V (1U << 13) /* AArch32 only */ +#define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ #define SCTLR_RR (1U << 14) /* up to v7 */ #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ #define SCTLR_nTWI (1U << 16) /* v8 onward */ -#define SCTLR_HA (1U << 17) +#define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ #define SCTLR_BR (1U << 17) /* PMSA only */ #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ #define SCTLR_nTWE (1U << 18) /* v8 onward */ #define SCTLR_WXN (1U << 19) #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ -#define SCTLR_UWXN (1U << 20) /* v7 onward */ -#define SCTLR_FI (1U << 21) -#define SCTLR_U (1U << 22) +#define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ +#define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ +#define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ +#define SCTLR_U (1U << 22) /* up to ??, v8 RES1 */ #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ +#define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ #define SCTLR_VE (1U << 24) /* up to v7 */ #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ #define SCTLR_EE (1U << 25) #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ #define SCTLR_NMFI (1U << 27) -#define SCTLR_TRE (1U << 28) -#define SCTLR_AFE (1U << 29) -#define SCTLR_TE (1U << 30) +#define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ +#define SCTLR_TRE (1U << 28) /* AArch32 only */ +#define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ +#define SCTLR_AFE (1U << 29) /* AArch32 only */ +#define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ +#define SCTLR_TE (1U << 30) /* AArch32 only */ +#define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ +#define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ +#define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ +#define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ +#define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ +#define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ +#define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ +#define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ +#define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ +#define SCTLR_DSSBS (1ULL << 44) /* v8.5 */ #define CPTR_TCPAC (1U << 31) #define CPTR_TTA (1U << 20) From patchwork Fri Dec 7 10:36:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153112 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp337288ljp; Fri, 7 Dec 2018 02:40:07 -0800 (PST) X-Google-Smtp-Source: AFSGD/V73oQmJZnNAuxYG/Rujrs56d78kroFu/icitozvZAFPi/8pKUtwvytug7a/6enUchT1oXm X-Received: by 2002:a37:ea0a:: with SMTP id t10mr1233366qkj.273.1544179207027; Fri, 07 Dec 2018 02:40:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544179207; cv=none; d=google.com; s=arc-20160816; b=00ndvBMhCpXiRngAtPVMpqzF3ZFzEOdjRoSwDxHfjImyU1n8mut2uhnAS58oqAQgk2 lc/WhaqCuy00vn5B7kZcBXk+MEhUH+vYYQve9MiE4mHasxHkuTrLBBRlF1BjZJooUI04 VTv1a2rqXoY6u9KZQHf00IdMi9ytvXiobVeDFs303OShmRmaAiD1cz1THWCgsKGtLcoF KwYuJDXIMb1ZrkgYnfLeQRBxBELXeOxjI4HCaU7zUW6crnHYeBBqOlRBZadS+ePqqX4/ rK9YUiVNZXFqJ7E/A/QfAO4FQ227K/3jW29Nq7PYUNeiqZdpAnR2eB2tgBxdw5phKgWe uWVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=JFdWs6eYKiJMy9nZV/6pMCAE27SKK+ui75wieoQo31U=; b=MXbI6qkJbL1rP404AfHGt2eqiAUQBVfhLU62Icj2NunHOfFfqSFPJBs8rRrx8wS62e WwDgvcXdXcexEWNuC4ilXzSE3f0Xa8xpl2PqyLfNcFfduGIJU9b8iz3m9jTP9XLi7QX7 Km0ME5YErt3xkpIcCboOCnBpaDpDQYOM+4eYXZGN74hBC6rySB4CWHoLHGfntMr6BuYG YyP+1ifDFDgd6Ojw8kX7GpiVQdF9Ym5AU/MtXxZ1KjT9l5DmUElW02C+cu7bYoLoBk43 NO/kGwNhvH1W6CIrtjaU450GLYXnPIkKtWEY+8Mb2wSASUf4iWje6d8WNbNVI8h5Gns4 J9Bg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=isNywPv3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id v19si322681qvk.110.2018.12.07.02.40.06 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 07 Dec 2018 02:40:07 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=isNywPv3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45260 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDYE-0003gC-ED for patch@linaro.org; Fri, 07 Dec 2018 05:40:06 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59023) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDUx-0007y2-0a for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVDUw-0007Em-0A for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:42 -0500 Received: from mail-ot1-x343.google.com ([2607:f8b0:4864:20::343]:36576) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gVDUv-0007E0-Ow for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:41 -0500 Received: by mail-ot1-x343.google.com with SMTP id k98so3365220otk.3 for ; Fri, 07 Dec 2018 02:36:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JFdWs6eYKiJMy9nZV/6pMCAE27SKK+ui75wieoQo31U=; b=isNywPv33US7PbuZGMdmSg9V+arzUH6Bmlj/9fFMuTEXRv3qWu7MsY3/VtYmNDeaWF 1zoLZJeU1iX+UGjUYFUqDMws61g3AMfLSZX0p2/u08mcLl9c9cSz1nJCkeSht0jOa8ZZ 0aoQ9UeHxdeRXZ5mMibUxryUhf5yRvC4xNys8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JFdWs6eYKiJMy9nZV/6pMCAE27SKK+ui75wieoQo31U=; b=dOcTQXsh2zYTI3nMX7XkfRh2mPrFenAS0QMXcXx8ySNylce6BACUdmCFJngzf0sPV4 nJ1bkBL8dXw5lCe0gNIAQs7bY2LYXBxuvw+tIx7pk24FPZfBhxW50+pAbwJl3BBdY/c9 troFoPUSrVJssl+IOmb8jV9OgSscJBFHz9Pcms9r/XAnAcEBd9CqgfR1vxH/w+o+DN1+ 6qDtO9o5fwTksJHghA3qPzGa4uNVUCGw1XyUrT/CprRz5TC6nhcXHTIlTt/7C+q7cQQj 0lvg127dIVXR3kMoy/8sxRF17r7brGXAeRY4EhX+ocqICMfOw1vC5+13isMQmPySMjNe 1q9Q== X-Gm-Message-State: AA+aEWYRoLn7j9r9+Q7J1Q3OnWYiFy/K1KNZt2Vr4YdAV5lbMSAH/JS/ 0yVFDlro92ynZdTUzgI2r9Re+eRGl3g= X-Received: by 2002:a9d:620f:: with SMTP id g15mr1010638otj.296.1544179000741; Fri, 07 Dec 2018 02:36:40 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.36.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:36:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:08 -0600 Message-Id: <20181207103631.28193-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org> References: <20181207103631.28193-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::343 Subject: [Qemu-devel] [PATCH 03/26] target/arm: Add PAuth active bit to tbflags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There are 5 bits of state that could be added, but to save space within tbflags, add only a single enable bit. Helpers will determine the rest of the state at runtime. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 4 ++++ target/arm/translate.h | 2 ++ target/arm/helper.c | 19 +++++++++++++++++++ target/arm/translate-a64.c | 1 + 4 files changed, 26 insertions(+) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 80d65866c6..f70eff8bcf 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3024,6 +3024,8 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) #define ARM_TBFLAG_SVEEXC_EL_MASK (0x3 << ARM_TBFLAG_SVEEXC_EL_SHIFT) #define ARM_TBFLAG_ZCR_LEN_SHIFT 4 #define ARM_TBFLAG_ZCR_LEN_MASK (0xf << ARM_TBFLAG_ZCR_LEN_SHIFT) +#define ARM_TBFLAG_PAUTH_ACTIVE_SHIFT 8 +#define ARM_TBFLAG_PAUTH_ACTIVE_MASK (1ull << ARM_TBFLAG_PAUTH_ACTIVE_SHIFT) /* some convenience accessor macros */ #define ARM_TBFLAG_AARCH64_STATE(F) \ @@ -3066,6 +3068,8 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) (((F) & ARM_TBFLAG_SVEEXC_EL_MASK) >> ARM_TBFLAG_SVEEXC_EL_SHIFT) #define ARM_TBFLAG_ZCR_LEN(F) \ (((F) & ARM_TBFLAG_ZCR_LEN_MASK) >> ARM_TBFLAG_ZCR_LEN_SHIFT) +#define ARM_TBFLAG_PAUTH_ACTIVE(F) \ + (((F) & ARM_TBFLAG_PAUTH_ACTIVE_MASK) >> ARM_TBFLAG_PAUTH_ACTIVE_SHIFT) static inline bool bswap_code(bool sctlr_b) { diff --git a/target/arm/translate.h b/target/arm/translate.h index 1550aa8bc7..d8a8bb4e9c 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -68,6 +68,8 @@ typedef struct DisasContext { bool is_ldex; /* True if a single-step exception will be taken to the current EL */ bool ss_same_el; + /* True if v8.3-PAuth is active. */ + bool pauth_active; /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ int c15_cpar; /* TCG op of the current insn_start. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 1e20956376..158c550fab 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12991,6 +12991,25 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags |= sve_el << ARM_TBFLAG_SVEEXC_EL_SHIFT; flags |= zcr_len << ARM_TBFLAG_ZCR_LEN_SHIFT; } + + if (cpu_isar_feature(aa64_pauth, cpu)) { + /* + * In order to save space in flags, we record only whether + * pauth is "inactive", meaning the insns are implemented as + * a nop, or "active" when some action must be performed. + * The decision of which action to take is left to a helper. + */ + uint64_t sctlr; + if (current_el == 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + sctlr = env->cp15.sctlr_el[1]; + } else { + sctlr = env->cp15.sctlr_el[current_el]; + } + if (sctlr & (SCTLR_EnIA |SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { + flags |= ARM_TBFLAG_PAUTH_ACTIVE_MASK; + } + } } else { *pc = env->regs[15]; flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e1da1e4d6f..7c1cc1ce8e 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13407,6 +13407,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); dc->sve_excp_el = ARM_TBFLAG_SVEEXC_EL(dc->base.tb->flags); dc->sve_len = (ARM_TBFLAG_ZCR_LEN(dc->base.tb->flags) + 1) * 16; + dc->pauth_active = ARM_TBFLAG_PAUTH_ACTIVE(dc->base.tb->flags); dc->vec_len = 0; dc->vec_stride = 0; dc->cp_regs = arm_cpu->cp_regs; From patchwork Fri Dec 7 10:36:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153113 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp337359ljp; Fri, 7 Dec 2018 02:40:13 -0800 (PST) X-Google-Smtp-Source: AFSGD/WGq7QEFOaOisdQu3VENeUrVcJ8q8kRdeXQFuzjUxz40OR46Tqmr17ponIn/0cvOeAcjx/y X-Received: by 2002:ac8:4141:: with SMTP id e1mr1379904qtm.96.1544179212949; Fri, 07 Dec 2018 02:40:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544179212; cv=none; d=google.com; s=arc-20160816; b=eOrIw8JtLmVgHHi8/Xst68OvM7aDRnuSd7Aic/003FFS2d5EQkmmkryDYOd6KUvJpi c7gSYxnQkhXJy28fpD3CMDR1Ntbn2clzku9Mzh9Tck08FeBFc1nUqHgH4bRczCznaM44 nbQ2FCXp/GIISpbYlVNgfErj/namv4x8kbKrMNSDrl1R84YDvFyFM+GzceKxNGhQHRpJ PJPADzs7aD5LyFShgRXSKCy+6znaofniWYmpoxuM9XyqbSvSkQ1uZswzPzJSod546UhQ dKJC9RedEopqWJ/L1EeNdinLQ1HV7NjTE03eTaSICJM6xoWNIWacN++E6jSNdB7Q6lEV 2Edw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=JKCkWa5pkvyszalAQzzATBEqwgOub7oUfr3wWefDEc0=; b=QBAZuRJ2egrN0dDArlHNNebO3CCvAM9D25H/K1H6UI/bd24A4b+/U0R2oW6susTsYJ CO3A3jnXgAvyWhRBYE2St1QoZIh6LgIS41erjImn2SwqFm2ESkTrR+HrKuQda6oLLiyv F89PYQikdQiXxoXytB1QWSKsGmxL/+Cjvn/XtJmu+Em+SGIPra98C9DOGMRgs6IcJF9J s5bBiQE5moxbRZ7BP92AkDogBK5vBLN++p/VsoH3MUsK+zfXSchwUhj4adDX1Kq1Jpyt TOma0PPmniuUPBc0uz00jN+pz3u9QLecN0Hna6QkjCfvEQAsfw1aRwkytmfkggW4l04T UAHg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=iMZfC3nZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id k60si1880147qtd.396.2018.12.07.02.40.12 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 07 Dec 2018 02:40:12 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=iMZfC3nZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45262 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDYK-0003kd-7O for patch@linaro.org; Fri, 07 Dec 2018 05:40:12 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59039) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDUy-0007yn-KW for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVDUx-0007Fn-AG for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:44 -0500 Received: from mail-oi1-x242.google.com ([2607:f8b0:4864:20::242]:36760) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gVDUx-0007FK-3M for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:43 -0500 Received: by mail-oi1-x242.google.com with SMTP id x23so3004975oix.3 for ; Fri, 07 Dec 2018 02:36:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JKCkWa5pkvyszalAQzzATBEqwgOub7oUfr3wWefDEc0=; b=iMZfC3nZdIPWDHhlDpg9C5cxvUZnwpdnXume724cRyKre8zGnbD/wk+AaHXhVzNiAN tvb0qfEu6inQiwXB1t/FZiZ0LjHqWl9DtYYcSc4U9TKrvZpadfFzMtJ8wJ9JFE18lCWN RV4R9Cvsrh1UOcrkvkpvG3TtwUKguUkYRNwYs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JKCkWa5pkvyszalAQzzATBEqwgOub7oUfr3wWefDEc0=; b=JJWLObrgCFjB816Oqf26UeywVx3pOJhq+fg+vbcwxRUbgVC+GkMn+cQOAYlv7kNNz7 6HINcZgIlT/chnHxxM/B0mKrpN2IL96y3HCNqC3tphjhItBilDht323j9JhDY6eScIlU D2xrw6N259q2HjU3NQhKylUvnwTtYP2ZMa9O09UUnZoHlgtlaklkfKai28rFFxrAyMH2 j4c8r+ids9ftVFoY77e7k4+zzrx5wPgaQgFOY5nvzkPo6g+yEWbujWhKhRqRPUN8Vsdw a+hu/HpJooslXLhrKKpxwypUzjAHm6F9mI6l2CNXCjEhD24tFOjzQ090H7sRQDJz+3gV rBag== X-Gm-Message-State: AA+aEWYXtzYncBpLtSeSxvNtOb4iYE7K2UrZkWd4n8tFub9Erjds6H84 sDazTtqPg2gNgay5PaqYyzafqp4sp88= X-Received: by 2002:aca:b05:: with SMTP id 5mr959349oil.258.1544179002111; Fri, 07 Dec 2018 02:36:42 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.36.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:36:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:09 -0600 Message-Id: <20181207103631.28193-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org> References: <20181207103631.28193-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::242 Subject: [Qemu-devel] [PATCH 04/26] target/arm: Add PAuth helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The cryptographic internals are stubbed out for now, but the enable and trap bits are checked. Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 12 +++ target/arm/internals.h | 6 ++ target/arm/helper-a64.c | 169 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 187 insertions(+) -- 2.17.2 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 9d3a907049..70f6145b11 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -85,3 +85,15 @@ DEF_HELPER_2(advsimd_rinth, f16, f16, ptr) DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr) DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr) DEF_HELPER_2(sqrt_f16, f16, f16, ptr) + +DEF_HELPER_FLAGS_3(pacia, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(pacib, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(pacda, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(pacdb, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(pacga, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(autia, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(autib, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(autda, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(autdb, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_WG, i64, env, i64) diff --git a/target/arm/internals.h b/target/arm/internals.h index 78e026d6e9..6bc0daf560 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -259,6 +259,7 @@ enum arm_exception_class { EC_CP14DTTRAP = 0x06, EC_ADVSIMDFPACCESSTRAP = 0x07, EC_FPIDTRAP = 0x08, + EC_PACTRAP = 0x09, EC_CP14RRTTRAP = 0x0c, EC_ILLEGALSTATE = 0x0e, EC_AA32_SVC = 0x11, @@ -426,6 +427,11 @@ static inline uint32_t syn_sve_access_trap(void) return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; } +static inline uint32_t syn_pactrap(void) +{ + return EC_PACTRAP << ARM_EL_EC_SHIFT; +} + static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) { return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 61799d20e1..4aa34d4a3a 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -898,4 +898,173 @@ uint32_t HELPER(sqrt_f16)(uint32_t a, void *fpstp) return float16_sqrt(a, s); } +/* + * Helpers for ARMv8.3-PAuth. + */ +static uint64_t pauth_computepac(uint64_t data, uint64_t modifier, + uint64_t key0, uint64_t key1) +{ + g_assert_not_reached(); /* FIXME */ +} + +static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, + uint64_t *key, bool data) +{ + g_assert_not_reached(); /* FIXME */ +} + +static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, + uint64_t *key, bool data, int keynumber) +{ + g_assert_not_reached(); /* FIXME */ +} + +static uint64_t pauth_strip(CPUARMState *env, uint64_t a, bool data) +{ + g_assert_not_reached(); /* FIXME */ +} + +static void QEMU_NORETURN pauth_trap(CPUARMState *env, int target_el, + uintptr_t ra) +{ + CPUState *cs = ENV_GET_CPU(env); + + cs->exception_index = EXCP_UDEF; + env->exception.syndrome = syn_pactrap(); + env->exception.target_el = target_el; + cpu_loop_exit_restore(cs, ra); +} + +static void pauth_check_trap(CPUARMState *env, int el, uintptr_t ra) +{ + if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) { + uint64_t hcr = arm_hcr_el2_eff(env); + bool trap = !(hcr & HCR_API); + /* FIXME: ARMv8.1-VHE: trap only applies to EL1&0 regime. */ + /* FIXME: ARMv8.3-NV: HCR_NV trap takes precedence for ERETA[AB]. */ + /* FIXME: PMM mentioned a "late breaking spec change" here. */ + if (trap) { + pauth_trap(env, 2, ra); + } + } + if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) { + if (!(env->cp15.scr_el3 & SCR_API)) { + pauth_trap(env, 3, ra); + } + } +} + +static bool pauth_key_enabled(CPUARMState *env, int el, uint32_t bit) +{ + uint32_t sctlr; + if (el == 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + sctlr = env->cp15.sctlr_el[1]; + } else { + sctlr = env->cp15.sctlr_el[el]; + } + return (sctlr & bit) != 0; +} + +uint64_t HELPER(pacia)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el = arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnIA)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_addpac(env, x, y, env->apia_key, false); +} + +uint64_t HELPER(pacib)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el = arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnIB)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_addpac(env, x, y, env->apib_key, false); +} + +uint64_t HELPER(pacda)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el = arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnDA)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_addpac(env, x, y, env->apda_key, true); +} + +uint64_t HELPER(pacdb)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el = arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnDB)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_addpac(env, x, y, env->apdb_key, true); +} + +uint64_t HELPER(pacga)(CPUARMState *env, uint64_t x, uint64_t y) +{ + uint64_t pac; + + pauth_check_trap(env, arm_current_el(env), GETPC()); + pac = pauth_computepac(x, y, env->apga_key[1], env->apga_key[0]); + + return pac & 0xffffffff00000000ull; +} + +uint64_t HELPER(autia)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el = arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnIA)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_auth(env, x, y, env->apia_key, false, 0); +} + +uint64_t HELPER(autib)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el = arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnIB)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_auth(env, x, y, env->apib_key, false, 1); +} + +uint64_t HELPER(autda)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el = arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnDA)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_auth(env, x, y, env->apda_key, true, 0); +} + +uint64_t HELPER(autdb)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el = arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnDB)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_auth(env, x, y, env->apdb_key, true, 1); +} + +uint64_t HELPER(xpaci)(CPUARMState *env, uint64_t a) +{ + pauth_check_trap(env, arm_current_el(env), GETPC()); + return pauth_strip(env, a, false); +} + +uint64_t HELPER(xpacd)(CPUARMState *env, uint64_t a) +{ + pauth_check_trap(env, arm_current_el(env), GETPC()); + return pauth_strip(env, a, true); +} From patchwork Fri Dec 7 10:36:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153109 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp335203ljp; Fri, 7 Dec 2018 02:37:17 -0800 (PST) X-Google-Smtp-Source: AFSGD/WoFVXpYWu0x4+ke8+6S7hTpa6KvO3YUitUd4VgW7WQB+QJqImABEJdaPjjkv6aP8bAMfZ/ X-Received: by 2002:ac8:6b18:: with SMTP id w24mr1460569qts.144.1544179036949; Fri, 07 Dec 2018 02:37:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544179036; cv=none; d=google.com; s=arc-20160816; b=zfnbs345PUd8aeTtM4MfxA9U5Z+JcctJOmpPiE8cPQ8pQN19dPohIxvG+8KTvr1rBZ 06WaE1llkfX6A05S7Gm1yDTXUq2mYXh6/NlShTX2OVLNdP5f0X6aoWwejOa8m9l8vD09 tG32GqMON97lyxqwtdZKqTFn068B/pomrB84EQz7vT99AhlZ30hvYTMl2uLUTC/df01Y D+TQSR4ahJc2VDeJ5R/SNOB0A+T3Ghr4ZeRFdiZImNgEAZKzHAJgKTWvbkqLIS3T7MoS L3rjghl6zbIqkQvXu3A8S9qCo8jslqsmxIsL/btI8gmC1ACj3uWxImX73kK36rA4EgGA Ng0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=BBGH46DSzj6YIrBp1pSAJv0X2g3wgK77Rkp3YAo8k6I=; b=DMP9DfnUgIMSZm+NzPnub0TEjs5wdo8Fwn/QZ9bAiPjyTpj/LN1Kkyp5snilGFKz0r 00SOY2CiDyfJIaZizBeCMulIeeUu1ZuIDkDxQRdfBjvRBsWjMG7occsdMTb7S+cqvHzd oO0OMqUSMEAh7KrdA23S2mcTILvAdXXHt+qHenk1MuQ5HNd5GUmMfR5PEcVGwEoCiRoj XgvXvYPyjx1h7SaZyg/I/4WABi8KO4Rb2yDK8zBtB+fb0XprWDyK8L/GcE17y+wDdkgi N3xLAjxgPEGICv6tS8KNMw2nuHYbWTJSFawfESsT/qYYgFOItTAA5CL5kD5+g8pMvHgg ig8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gjSQqh82; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 63si784321qkr.108.2018.12.07.02.37.16 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 07 Dec 2018 02:37:16 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gjSQqh82; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45251 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDVU-000836-Cg for patch@linaro.org; Fri, 07 Dec 2018 05:37:16 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59050) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDUz-000802-ME for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVDUy-0007KT-OO for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:45 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:45291) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gVDUy-0007I5-FP for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:44 -0500 Received: by mail-oi1-x241.google.com with SMTP id y1so1218143oie.12 for ; Fri, 07 Dec 2018 02:36:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BBGH46DSzj6YIrBp1pSAJv0X2g3wgK77Rkp3YAo8k6I=; b=gjSQqh82xRUUx27Sw7M3eUZfBYbMNtfsuqzwmCBZ/1daWZxrhnWzcVJqJWxMFDsDr9 UCa96TyDacYx9MJrByfmDQ2fKEWeNYfoDaz0FMnuKeYMVxFbo98ER4J8yc8eVj9hpLEF jN/ogFCi3g+TA70MZrmPmyqyDKHO6Mi9gMm48= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BBGH46DSzj6YIrBp1pSAJv0X2g3wgK77Rkp3YAo8k6I=; b=tT4atfceP0tDncF1J/+UDFbcaPyXqYbhvt1czaY9x/dka34iB2Y+rXNR0bzORr4uiI HuhVkcVAYtTkB/BOqv9cQrsLfTlzJquuauy/+OaRbkl3LndU96Rv7ztFwvjNVtaJWSId 8u0hKOrViZ4R3uMcx+M/636KSkRF/sI4aHZQG67ouOGoxw3nZ5/eAGQEfrhVJldPJtLH 9VHEvp4396IwSuUXQHEDVKPUgn7Sr9ajX6v7afuZZPZLn1vWPtVgb25Do43vvhXAapSY PSaVlJZ9fKxu6Js/AeImFG2s2jRROh08GxVYJKfGvQ42qIHSLVA1RvAfAXPtbkBOjMfK hzYg== X-Gm-Message-State: AA+aEWZKSYlJ+9312BT1d63D5oaMcOuABQ+81bhDAHOXJVCSJ4dSedkk SfN6mTdCoz/wHE9HUfijypKRujL54xY= X-Received: by 2002:aca:6155:: with SMTP id v82mr952901oib.259.1544179003477; Fri, 07 Dec 2018 02:36:43 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.36.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:36:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:10 -0600 Message-Id: <20181207103631.28193-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org> References: <20181207103631.28193-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 Subject: [Qemu-devel] [PATCH 05/26] target/arm: Decode PAuth within system hint space X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 93 +++++++++++++++++++++++++++++++++----- 1 file changed, 81 insertions(+), 12 deletions(-) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7c1cc1ce8e..0df344f9e8 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1471,33 +1471,102 @@ static void handle_hint(DisasContext *s, uint32_t insn, } switch (selector) { - case 0: /* NOP */ - return; - case 3: /* WFI */ + case 000: /* NOP */ + break; + case 003: /* WFI */ s->base.is_jmp = DISAS_WFI; - return; + break; + case 001: /* YIELD */ /* When running in MTTCG we don't generate jumps to the yield and * WFE helpers as it won't affect the scheduling of other vCPUs. * If we wanted to more completely model WFE/SEV so we don't busy * spin unnecessarily we would need to do something more involved. */ - case 1: /* YIELD */ if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { s->base.is_jmp = DISAS_YIELD; } - return; - case 2: /* WFE */ + break; + case 002: /* WFE */ if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { s->base.is_jmp = DISAS_WFE; } - return; - case 4: /* SEV */ - case 5: /* SEVL */ + break; + case 004: /* SEV */ + case 005: /* SEVL */ /* we treat all as NOP at least for now */ - return; + break; + case 007: /* XPACLRI */ + if (s->pauth_active) { + gen_helper_xpaci(cpu_X[30], cpu_env, cpu_X[30]); + } + break; + case 010: /* PACIA1716 */ + if (s->pauth_active) { + gen_helper_pacia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + } + break; + case 012: /* PACIB1716 */ + if (s->pauth_active) { + gen_helper_pacib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + } + break; + case 014: /* AUTIA1716 */ + if (s->pauth_active) { + gen_helper_autia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + } + break; + case 016: /* AUTIB1716 */ + if (s->pauth_active) { + gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + } + break; + case 030: /* PACIAZ */ + if (s->pauth_active) { + gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], + new_tmp_a64_zero(s)); + } + break; + case 031: /* PACIASP */ + if (s->pauth_active) { + gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + } + break; + case 032: /* PACIBZ */ + if (s->pauth_active) { + gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], + new_tmp_a64_zero(s)); + } + break; + case 033: /* PACIBSP */ + if (s->pauth_active) { + gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + } + break; + case 034: /* AUTIAZ */ + if (s->pauth_active) { + gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], + new_tmp_a64_zero(s)); + } + break; + case 035: /* AUTIASP */ + if (s->pauth_active) { + gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + } + break; + case 036: /* AUTIBZ */ + if (s->pauth_active) { + gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], + new_tmp_a64_zero(s)); + } + break; + case 037: /* AUTIBSP */ + if (s->pauth_active) { + gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + } + break; default: /* default specified as NOP equivalent */ - return; + break; } } From patchwork Fri Dec 7 10:36:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153117 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp341098ljp; Fri, 7 Dec 2018 02:45:11 -0800 (PST) X-Google-Smtp-Source: AFSGD/VXiZTD8YnRIvr7r0J2on5wPGdP75x58BSt8o5V/bpmxHbRDpdMYcSi3aj8FF0giCHQ9TZW X-Received: by 2002:ac8:2a81:: with SMTP id b1mr1478819qta.110.1544179511568; Fri, 07 Dec 2018 02:45:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544179511; cv=none; d=google.com; s=arc-20160816; b=Uy+jWboWmj08leCcGPL8qeDggZcNiyr02FINpDGmn+/vChRJ1cZLJ4N9B0mzFKQzut z/8JXzN6fRLeKZM6KC2m63mhYcYHQBv22voxfQ1o3zuH29URemOq9pL2m8WiqlWxIdBp RM6BqG0hC7rzRK/r8GfcxbnlJagj20BOpfLLuqVdsorFOztXNtYRMq0EqnmyiI06V+mw W6xJwExw6LPhqqokiPq0YNQIn07twUI2EMvaAcGMoEI/Y4tHhXH21Zx8OkQIJfsSlX6v MdCzsk/upozCcgmnxcWgG8vuiV1BmE+wQQ8x7/MBSt3r0Nb0+9HA6NJoUGxgMk+Cv2JX 8oWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=IZN/zm+Sbr0VZp5LeMSCa70GLuCTR8dRmQr/tO3QM7I=; b=ySZqn4QLJZCExgm9XAPNiAS0yqgEROc/X8YmcE6R6oWyu4eNaj3EpBi84S6fCxsi2p uNXaRrYNkaAlnZVaqguKiuW/iEDhgd1fw3SXGvBgwoslNmPpdTvmWiUasHj4781kgcQS WuWFKyErmlKah8MJaZE7ciI7H4r0iP3WAzO9cvHNpqTN55ww/mBodUxIj/fMR8YueFaa 0jDXNkmRKjge6s1fHgcWeH5zfMvFIM5zrViiNsr5SBeQ/taod4C9G9hjWNfRt/LHxyRy UgVOLTtkA8Ub5KlKd3b2kbIvhPJ/I0RM6HEBYYFa2Wj74+RMYFM36J1rhAPX7Cr89uzQ BkRw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Neo3MWAr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id g14si2013546qti.392.2018.12.07.02.45.11 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 07 Dec 2018 02:45:11 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Neo3MWAr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45296 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDd8-0002DE-Ub for patch@linaro.org; Fri, 07 Dec 2018 05:45:11 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59066) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDV0-00081c-SG for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVDV0-0007OP-3p for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:46 -0500 Received: from mail-oi1-x244.google.com ([2607:f8b0:4864:20::244]:38515) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gVDUz-0007NZ-V5 for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:46 -0500 Received: by mail-oi1-x244.google.com with SMTP id a77so2999998oii.5 for ; Fri, 07 Dec 2018 02:36:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IZN/zm+Sbr0VZp5LeMSCa70GLuCTR8dRmQr/tO3QM7I=; b=Neo3MWArIUBVEwl/WomgFSwjO2fkJZAjK/sos2W34bVy5XTs50x0B5JRWYm2N0BR6n 1jWN/YypIPNgzCvMz6RRPob0hfgd9htIIQpfj5mF2vJHuBlYy074OhkrcDoU+QTkOjS/ sJfy5dM6vC5QoCcSdhO5vt6+TUiv1b/HzhnmU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IZN/zm+Sbr0VZp5LeMSCa70GLuCTR8dRmQr/tO3QM7I=; b=jVlkZlNvOJ0X9P8kea4ZqpTPAonHEN4d6zqQBcSHjeriunjvYRyChe+PtqMt4JnsN4 VlGccM180Frvvaba3USph0wbZXWI6bSvc2Mfgi4BOPp5wd9Bp6VI2YpW03Nz06KB1CyE w6SreJnMQBcHptHJKdSiOy6lLrQ5KWyOLA4I2z/Zq2UtRyXVupO8wZr1rDLYT8Pk5o+B jDpbgHN4OtAw3fFJaodRuQVDInOJhQbttHlX1yGOsl2TCBXfdc9JRzYHxHOoBm5hwRLW NWzjyUTiAu4CG4ZzrgYbgMDk2e0qNCFN9NIs4adSAxGqUj7/tp3zQ6yadPcWInKAQTrO h/sA== X-Gm-Message-State: AA+aEWbRGy7BbU9IgcrQCPwBtOQBEL2emRvZNKm4GbnoxXBCasW3Qbqi XbBJ67vCTo+0VtVWaE52A509qpjw82g= X-Received: by 2002:a54:440d:: with SMTP id k13mr966207oiw.263.1544179004988; Fri, 07 Dec 2018 02:36:44 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.36.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:36:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:11 -0600 Message-Id: <20181207103631.28193-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org> References: <20181207103631.28193-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::244 Subject: [Qemu-devel] [PATCH 06/26] target/arm: Rearrange decode in disas_data_proc_1src X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now properly signals unallocated for REV64 with SF=0. Allows for the opcode2 field to be decoded shortly. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 31 ++++++++++++++++++++++--------- 1 file changed, 22 insertions(+), 9 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 0df344f9e8..c5ec430b42 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4563,38 +4563,51 @@ static void handle_rev16(DisasContext *s, unsigned int sf, */ static void disas_data_proc_1src(DisasContext *s, uint32_t insn) { - unsigned int sf, opcode, rn, rd; + unsigned int sf, opcode, opcode2, rn, rd; - if (extract32(insn, 29, 1) || extract32(insn, 16, 5)) { + if (extract32(insn, 29, 1)) { unallocated_encoding(s); return; } sf = extract32(insn, 31, 1); opcode = extract32(insn, 10, 6); + opcode2 = extract32(insn, 16, 5); rn = extract32(insn, 5, 5); rd = extract32(insn, 0, 5); - switch (opcode) { - case 0: /* RBIT */ +#define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7)) + + switch (MAP(sf, opcode2, opcode)) { + case MAP(0, 0x00, 0x00): /* RBIT */ + case MAP(1, 0x00, 0x00): handle_rbit(s, sf, rn, rd); break; - case 1: /* REV16 */ + case MAP(0, 0x00, 0x01): /* REV16 */ + case MAP(1, 0x00, 0x01): handle_rev16(s, sf, rn, rd); break; - case 2: /* REV32 */ + case MAP(0, 0x00, 0x02): /* REV/REV32 */ + case MAP(1, 0x00, 0x02): handle_rev32(s, sf, rn, rd); break; - case 3: /* REV64 */ + case MAP(1, 0x00, 0x03): /* REV64 */ handle_rev64(s, sf, rn, rd); break; - case 4: /* CLZ */ + case MAP(0, 0x00, 0x04): /* CLZ */ + case MAP(1, 0x00, 0x04): handle_clz(s, sf, rn, rd); break; - case 5: /* CLS */ + case MAP(0, 0x00, 0x05): /* CLS */ + case MAP(1, 0x00, 0x05): handle_cls(s, sf, rn, rd); break; + default: + unallocated_encoding(s); + break; } + +#undef MAP } static void handle_div(DisasContext *s, bool is_signed, unsigned int sf, From patchwork Fri Dec 7 10:36:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153120 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp341508ljp; Fri, 7 Dec 2018 02:45:43 -0800 (PST) X-Google-Smtp-Source: AFSGD/WrmmmHu+insKrI3PHXYEPY1DWJiNFEsCLjZ1MaukKIxJvAW/OwPnpihfpQtSnOUh/U/Bjw X-Received: by 2002:ac8:6784:: with SMTP id b4mr1473197qtp.103.1544179543271; Fri, 07 Dec 2018 02:45:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544179543; cv=none; d=google.com; s=arc-20160816; b=GBXrP8tABOW8I+Xh4dpHjqTy3nqiWpp7S4cXRaV45CFKmbojyJ3+BHuCtopfq5+ZsY Zm0zkIPXenZMg04wQPwQE83DkJo2feEVqMD8JvZ/xcwH0y4Wkk9Qagto8zJCpRdP3pIX Jtm7q9ZO8FXTs35P/pixun5ELTLR+Q7FT0vhBt9P9hSmsvQl0QMavVPToBeuNVH1RkP/ JlPf2yC0V53EeI7IUC3xyVhfd2p024vgz/CPF160emEwIWRm62wzh3cZhvUIVXM8dP7Y o8q5NMs27PQ0JnnBVxzUToLBHXAytB2NaIKj5QZiUnabgGKe3hUe1JFM/RdRGc/ZSUzm QVLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=qQ2kBkEIooqXMwtWosEViqdXhdu/HbTiJ7UnjMq3Or0=; b=sHQGpJ8cs9sUjB71C6r44y6fM2wzRvvlRlQCoXhEULIosRQTN9bbqSDvLsrEbENCQb DBlOWom25soQT4ioSHzcXeYQ7Nr9S5mJ33ObiCszsXRbOnvf7eWMpyOLhzCxNUG0pn38 ZA2YpJ5YBbVm1CRhqXKRjIKC3IetilnRZeork0IUdylKNaDRQKs9aNam+5Ys7KoHOy0F URKTY0Vxfin1PnyxQfSTBAPLGb4VcX0Lu11LDBMkKCNT3clfpcbu1P3aSlPed2rx2aLg c1RlGhsnkPqi2tCjBrYJj06xZRgaJSjOxBBGtH5opyCIqfX3QPYz3lHoAFaCbodFEBU9 dyIg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GqYlaOaH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id g5si2286300qka.50.2018.12.07.02.45.43 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 07 Dec 2018 02:45:43 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GqYlaOaH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45298 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDde-0002fM-Ag for patch@linaro.org; Fri, 07 Dec 2018 05:45:42 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59106) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDV5-000843-07 for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVDV1-0007RE-NF for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:50 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:41413) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gVDV1-0007QO-GX for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:47 -0500 Received: by mail-oi1-x241.google.com with SMTP id j21so2984619oii.8 for ; Fri, 07 Dec 2018 02:36:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qQ2kBkEIooqXMwtWosEViqdXhdu/HbTiJ7UnjMq3Or0=; b=GqYlaOaH9dYfmlqLyIxWtDl+FfQRaf6cuclwaC6f/Odf/ZmJ+IrN4AJdRdSIlg2Cti H4EgXeYOg3ngsSUjqUqXbxg1DYVofp8uxKVA/QWxJhtonHTHlUj8gMdBq4Piqx3GgUbw IpYPq+LrmBbMmt9OPTxASsjq/Wj325ZbGCPrQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qQ2kBkEIooqXMwtWosEViqdXhdu/HbTiJ7UnjMq3Or0=; b=Qqz601gAxDU8VaWLVXhdeLRHzRAy11cBfXLVINjsD7zeQvccJ8BAVSqXUIHx9CVz+V xuG7XUphqlIGzV0EZvXSv4VIOdRdMt2yEEe2mq3Gfj5ZvMcbuere+dmEICsDBhOdM0B2 ukio5DzQw/1/CSsQrKDzghaE53hwfI0FEGebG71iaikjxD9gE+1tXLmkE4JEkbL8/XXZ 8tzrIWL5Z5oCYDgoRB3SEcNnqN56tjQ9Mu5NfezvP+vwPgwArB+3PhBY1a4Ir/kc6izY XRg+IvLIhKuRLA4VepFe6o6Ar2fRO0vhrDQQ98jmHPRl/myAfi5TGVcRcwesmBLAVIxu 0y7g== X-Gm-Message-State: AA+aEWYw7HLJNH+a4y4AaoPFjcJR0NBBXY9VF8CKxmM3vOQkoN3HS2Te l80k4Xhdxx3mKJEJEv/IAk0JPeBzlEU= X-Received: by 2002:aca:3011:: with SMTP id w17mr963475oiw.342.1544179006485; Fri, 07 Dec 2018 02:36:46 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.36.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:36:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:12 -0600 Message-Id: <20181207103631.28193-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org> References: <20181207103631.28193-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 Subject: [Qemu-devel] [PATCH 07/26] target/arm: Decode PAuth within disas_data_proc_1src X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 146 +++++++++++++++++++++++++++++++++++++ 1 file changed, 146 insertions(+) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c5ec430b42..7ba4c996cf 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4564,6 +4564,7 @@ static void handle_rev16(DisasContext *s, unsigned int sf, static void disas_data_proc_1src(DisasContext *s, uint32_t insn) { unsigned int sf, opcode, opcode2, rn, rd; + TCGv_i64 tcg_rd; if (extract32(insn, 29, 1)) { unallocated_encoding(s); @@ -4602,7 +4603,152 @@ static void disas_data_proc_1src(DisasContext *s, uint32_t insn) case MAP(1, 0x00, 0x05): handle_cls(s, sf, rn, rd); break; + case MAP(1, 0x01, 0x00): /* PACIA */ + if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_pacia(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x01): /* PACIB */ + if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_pacib(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x02): /* PACDA */ + if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_pacda(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x03): /* PACDB */ + if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_pacdb(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x04): /* AUTIA */ + if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_autia(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x05): /* AUTIB */ + if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_autib(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x06): /* AUTDA */ + if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_autda(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x07): /* AUTDB */ + if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_autdb(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x08): /* PACIZA */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_pacia(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x09): /* PACIZB */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_pacib(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x0a): /* PACDZA */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_pacda(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x0b): /* PACDZB */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_pacdb(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x0c): /* AUTIZA */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_autia(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x0d): /* AUTIZB */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_autib(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x0e): /* AUTDZA */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_autda(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x0f): /* AUTDZB */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_autdb(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x10): /* XPACI */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_xpaci(tcg_rd, cpu_env, tcg_rd); + } + break; + case MAP(1, 0x01, 0x11): /* XPACD */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_xpacd(tcg_rd, cpu_env, tcg_rd); + } + break; default: + do_unallocated: unallocated_encoding(s); break; } From patchwork Fri Dec 7 10:36:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153111 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp337066ljp; Fri, 7 Dec 2018 02:39:49 -0800 (PST) X-Google-Smtp-Source: AFSGD/WkfDbdNXVu6Si0uXkIRYKHC9K9D/hZqXTv+OuaC7grc0wqoe5D7pKypk04kHjLfYU/5FBl X-Received: by 2002:ac8:3181:: with SMTP id h1mr1494781qte.14.1544179189711; Fri, 07 Dec 2018 02:39:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544179189; cv=none; d=google.com; s=arc-20160816; b=RM6++s8Kl5t7fBpm7HdLwdI+3XvCLT/bhf4tvfQvs4bTIKMJ9Ahb/6VMM12FS2y5R2 chM8jnwEGQlymPLglt3NrLNsPYpJATR3qighnJhMhu2bvAl0cghFv9CSpnFjEzxWCD9B r6gQGi8YjCWHCVilZXgW3eDL6FkM6qdijW5xdT0pbZg418SSDwQYo3ew68GR99qrb25D P6XBE+i9LvM+RyRLmDTCxk1GEAtY9fuXQqfG0/RFqcfWhV7XHT/oqx7KWTz9TYyNcH0L QQd0+wM7+9HvIkLmanFo4NrArkIfo472+KHYPSUhxke2SUMnG8nBOMUQFgvv1dWPimas t0gA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=EoYoD6oIbPQGvsMFdoZaRrFdYbqAdTr3zU+lFQH+BQ8=; b=AS0drdmFgYhTDDfm5ZZotlPFD9R2wzlbvM/Je1fPGEjvBYOSBDpFiYOVhhLUynhhQF wI3onLL/1UtHiez7Gp5HCo2LLXkSyk/4KhaiNKdcZhYL+KGck/DweZb1qEsmLU/Oynen 12AL+v5XP4CkRI5ssxI0B/LMvPe+HuoprAibCi/UfPDHU0mySWEFYq0amyubACRTVyn1 G6NxaqSHauxqfFM/yF87aY7X1pgYcmfp2FNI7dNSCo2HEDO30SP9Ja3GK3ZhJnKG0Ih1 VbfFIHBYVyLZWs1uXzJEMQecPFtWnUkhNdDFhxTciYn+4KjkPiXCQzm6+5FQ1QH0uoVu GbAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=KRaZjYfL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id x14si1820556qts.71.2018.12.07.02.39.49 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 07 Dec 2018 02:39:49 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=KRaZjYfL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45263 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDXx-0003og-31 for patch@linaro.org; Fri, 07 Dec 2018 05:39:49 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59104) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDV4-000842-Vl for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVDV3-0007TY-BN for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:50 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:42314) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gVDV3-0007Sz-6L for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:49 -0500 Received: by mail-oi1-x241.google.com with SMTP id w13so2985710oiw.9 for ; Fri, 07 Dec 2018 02:36:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EoYoD6oIbPQGvsMFdoZaRrFdYbqAdTr3zU+lFQH+BQ8=; b=KRaZjYfLRM9+XlhL42QgyYxRmiYcZ7iYVF6KLlx4wX+1cQXYe4FE2Qbt32VaA4hG67 0xtPRsMEAGzRtNanCZr0DYdAF7KFH1DTa/ILewW1ntNglRZ/Uw6Ugd5l/P7lAzrFt/sg 6i8Nube4U8PttcmU8vcDK9ChJ4XCbuQYJrNuo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EoYoD6oIbPQGvsMFdoZaRrFdYbqAdTr3zU+lFQH+BQ8=; b=cOy0vphezjKaFH9YKQN7qhm7g9nxZbNWo6H2wGzFu6Q0waiYKD1ENf5McQaAmnnjp/ BzpsmH9yDf7mIwCqusHE44hfKGVhi5lkO4DCdLjM3n8my5/cHjQMEVejdAbU6BXwUeUr JYHinXtOasfyylfluOTHsTslbceTY/QBxc8BzA7kESBrjErS5wBPYMHhtD5bPaCDsK90 G6n4391e3Znqy6NKo+PiL1sMYg4dfO4RXAwzlLOVAmxnskCVAXSiWI7ZSEr7uS3tE5QH jYjjKi4i5XxbqnBU+39REDdML4nH0OqxdAnAR2DvEiOvefiYSSPTmLP28N9PJoBTrlK/ ZWFg== X-Gm-Message-State: AA+aEWa6p3YvwBH56hkIL5og4rzeXa5UxXZcG1/tmDF85QtZ5dODIaBZ l1ZTitehqru3qI0X0puzNWvg3bUnFGQ= X-Received: by 2002:aca:48d1:: with SMTP id v200mr960604oia.69.1544179008188; Fri, 07 Dec 2018 02:36:48 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.36.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:36:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:13 -0600 Message-Id: <20181207103631.28193-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org> References: <20181207103631.28193-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 Subject: [Qemu-devel] [PATCH 08/26] target/arm: Decode PAuth within disas_data_proc_2src X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7ba4c996cf..d034a5edf3 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4884,6 +4884,13 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) case 11: /* RORV */ handle_shift_reg(s, A64_SHIFT_TYPE_ROR, sf, rm, rn, rd); break; + case 12: /* PACGA */ + if (sf == 0 || !dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + gen_helper_pacga(cpu_reg(s, rd), cpu_env, + cpu_reg(s, rn), cpu_reg_sp(s, rm)); + break; case 16: case 17: case 18: @@ -4899,6 +4906,7 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) break; } default: + do_unallocated: unallocated_encoding(s); break; } From patchwork Fri Dec 7 10:36:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153114 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp337429ljp; Fri, 7 Dec 2018 02:40:20 -0800 (PST) X-Google-Smtp-Source: AFSGD/UyC8GEMj6fgc6IFJEPlLhiXrbvNHxSQdszWjvPSrJhOhWqcE2eMJhd/Vc+OlxlwYm51YBQ X-Received: by 2002:ac8:354e:: with SMTP id z14mr1456790qtb.272.1544179219960; Fri, 07 Dec 2018 02:40:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544179219; cv=none; d=google.com; s=arc-20160816; b=Vr1M25aO7EflZImRV59HccO/fncwlWd5ehRESSyRtKn6e+rmv0ehw5+YZtE7D4KvAS S50QTzE9BOs0KvJPeHra4CaIuLTJ4PEzpbx6/h/B5cVtQWukAyP3qQIgOb+9TSjbsl0G pWY3vq0RmEC2Wdl76cagJvbMypnA3rJONGxJjuncOCvyTdhe8IgCuNIU4XL0vYKCVpv7 TLGqcu2F95/7ejd+71LgqtspmeqkCLr/A4iJmGY2YlVG3gOb2ZdxOw73xxMk2PiFtFS9 7TpvgxWy+GN3Y4s50TOQyCXZeb3qihTPo7V7WyLrEdKdqiApzyWpmZdbc0ABcgsHMTdZ qIng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=PdZmYpa4j0jfsmJZR25EQHlHUcOzabDirddGYeF02Ns=; b=zLz6q6W6NWKFxD5PQOnlVDAbRdI63IOiCF4hGUV2hrNNpFyameoNFnWP2loWBwf5EN dEaLZ82aP6iK80MBwFwp8O0D9C6akgkprKMIaWvDrSj29I/0sIPShlx1AdTje8zD4mtZ cTPzpH8husrcn4f9NCh74eMhfxEjqJzypKaobYk8QA42fkHb341tRa5g/5xyhI9GkUeY EhWgWgCVgi+MlNHWpwIQSsyMZGJunn032m1Z/YgF/cbg+HMaDA0+y5DMXcnJoRYnGabV Xsgc1oY6shrk1fQObH7n3SYKctLTxU8gm7nADN7TMNll/NATtiwP0bEmKnMG01Ct1hDF zAuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PEyHRhax; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id u4si1928719qkc.197.2018.12.07.02.40.19 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 07 Dec 2018 02:40:19 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PEyHRhax; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45264 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDYR-0003st-97 for patch@linaro.org; Fri, 07 Dec 2018 05:40:19 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59134) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDV6-000866-LZ for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVDV5-0007Ye-1h for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:52 -0500 Received: from mail-oi1-x232.google.com ([2607:f8b0:4864:20::232]:35675) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gVDV4-0007XO-P4 for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:50 -0500 Received: by mail-oi1-x232.google.com with SMTP id v6so3020412oif.2 for ; Fri, 07 Dec 2018 02:36:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PdZmYpa4j0jfsmJZR25EQHlHUcOzabDirddGYeF02Ns=; b=PEyHRhaxxCGr+Tu26SiI77AAhhw6zRVczVeesqCfqShmAluojD0I3VqHXHH5nqzzU/ DzBap+HifTI+dmGh8t/GCOywceSZ+X983PAELQYl8xyQ9iiP3dJCbxqsT/0MimzdJAVY IciSf45NkT2dhp9xpev7yog7vFTGDKdRx5Yog= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PdZmYpa4j0jfsmJZR25EQHlHUcOzabDirddGYeF02Ns=; b=KX/qHOq1TJEoXEENavmSI6MBnG0zrTYzr2qLCvqr+uFffUHiCU3Q03mkwjJ+BWrpV7 Y26RfUtPEEW6FNNswMAN3mcK1YHWHXMGyF5mV2r6JzsG1/jWyhfyaW+x6Bc2hV7wWZJ2 pFx5uGHFCSx5HtncJjqAq3SJSFOsIHnz2SYsuLlHvn+L8e/yD9bciMdLAU/A1Db3wzO+ WKIjwO3HEIzS5BP10EzazhX4Caggm8KoidL+GBKRUcDO/DX32S4bODnuWbPkbGBvW2Jo 9fPdj2Z8+GkqRQQgi7M+VwurRLgN34pHuiWRwiL3aoDIQGa5yMdYUAe/kvL3yCJHCP+W SwUA== X-Gm-Message-State: AA+aEWZ+FGoPPHDqsdOEWtqLU1/FqKnJHpRDWpyfHy2nfYwyR04kwcUL V2IadMoh9UGCkzRQzQ1rjPAjAxuzPnE= X-Received: by 2002:aca:4ed8:: with SMTP id c207mr971138oib.276.1544179009717; Fri, 07 Dec 2018 02:36:49 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.36.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:36:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:14 -0600 Message-Id: <20181207103631.28193-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org> References: <20181207103631.28193-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::232 Subject: [Qemu-devel] [PATCH 09/26] target/arm: Move helper_exception_return to helper-a64.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This function is only used by AArch64. Code movement only. Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 2 + target/arm/helper.h | 1 - target/arm/helper-a64.c | 155 ++++++++++++++++++++++++++++++++++++++++ target/arm/op_helper.c | 155 ---------------------------------------- 4 files changed, 157 insertions(+), 156 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 70f6145b11..cb7209eb31 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -86,6 +86,8 @@ DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr) DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr) DEF_HELPER_2(sqrt_f16, f16, f16, ptr) +DEF_HELPER_1(exception_return, void, env) + DEF_HELPER_FLAGS_3(pacia, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(pacib, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(pacda, TCG_CALL_NO_WG, i64, env, i64, i64) diff --git a/target/arm/helper.h b/target/arm/helper.h index 8c9590091b..53a38188c6 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -79,7 +79,6 @@ DEF_HELPER_2(get_cp_reg64, i64, env, ptr) DEF_HELPER_3(msr_i_pstate, void, env, i32, i32) DEF_HELPER_1(clear_pstate_ss, void, env) -DEF_HELPER_1(exception_return, void, env) DEF_HELPER_2(get_r13_banked, i32, env, i32) DEF_HELPER_3(set_r13_banked, void, env, i32, i32) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 4aa34d4a3a..92e751fa07 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -887,6 +887,161 @@ uint32_t HELPER(advsimd_f16touinth)(uint32_t a, void *fpstp) return float16_to_uint16(a, fpst); } +static int el_from_spsr(uint32_t spsr) +{ + /* Return the exception level that this SPSR is requesting a return to, + * or -1 if it is invalid (an illegal return) + */ + if (spsr & PSTATE_nRW) { + switch (spsr & CPSR_M) { + case ARM_CPU_MODE_USR: + return 0; + case ARM_CPU_MODE_HYP: + return 2; + case ARM_CPU_MODE_FIQ: + case ARM_CPU_MODE_IRQ: + case ARM_CPU_MODE_SVC: + case ARM_CPU_MODE_ABT: + case ARM_CPU_MODE_UND: + case ARM_CPU_MODE_SYS: + return 1; + case ARM_CPU_MODE_MON: + /* Returning to Mon from AArch64 is never possible, + * so this is an illegal return. + */ + default: + return -1; + } + } else { + if (extract32(spsr, 1, 1)) { + /* Return with reserved M[1] bit set */ + return -1; + } + if (extract32(spsr, 0, 4) == 1) { + /* return to EL0 with M[0] bit set */ + return -1; + } + return extract32(spsr, 2, 2); + } +} + +void HELPER(exception_return)(CPUARMState *env) +{ + int cur_el = arm_current_el(env); + unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el); + uint32_t spsr = env->banked_spsr[spsr_idx]; + int new_el; + bool return_to_aa64 = (spsr & PSTATE_nRW) == 0; + + aarch64_save_sp(env, cur_el); + + arm_clear_exclusive(env); + + /* We must squash the PSTATE.SS bit to zero unless both of the + * following hold: + * 1. debug exceptions are currently disabled + * 2. singlestep will be active in the EL we return to + * We check 1 here and 2 after we've done the pstate/cpsr write() to + * transition to the EL we're going to. + */ + if (arm_generate_debug_exceptions(env)) { + spsr &= ~PSTATE_SS; + } + + new_el = el_from_spsr(spsr); + if (new_el == -1) { + goto illegal_return; + } + if (new_el > cur_el + || (new_el == 2 && !arm_feature(env, ARM_FEATURE_EL2))) { + /* Disallow return to an EL which is unimplemented or higher + * than the current one. + */ + goto illegal_return; + } + + if (new_el != 0 && arm_el_is_aa64(env, new_el) != return_to_aa64) { + /* Return to an EL which is configured for a different register width */ + goto illegal_return; + } + + if (new_el == 2 && arm_is_secure_below_el3(env)) { + /* Return to the non-existent secure-EL2 */ + goto illegal_return; + } + + if (new_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { + goto illegal_return; + } + + qemu_mutex_lock_iothread(); + arm_call_pre_el_change_hook(arm_env_get_cpu(env)); + qemu_mutex_unlock_iothread(); + + if (!return_to_aa64) { + env->aarch64 = 0; + /* We do a raw CPSR write because aarch64_sync_64_to_32() + * will sort the register banks out for us, and we've already + * caught all the bad-mode cases in el_from_spsr(). + */ + cpsr_write(env, spsr, ~0, CPSRWriteRaw); + if (!arm_singlestep_active(env)) { + env->uncached_cpsr &= ~PSTATE_SS; + } + aarch64_sync_64_to_32(env); + + if (spsr & CPSR_T) { + env->regs[15] = env->elr_el[cur_el] & ~0x1; + } else { + env->regs[15] = env->elr_el[cur_el] & ~0x3; + } + qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " + "AArch32 EL%d PC 0x%" PRIx32 "\n", + cur_el, new_el, env->regs[15]); + } else { + env->aarch64 = 1; + pstate_write(env, spsr); + if (!arm_singlestep_active(env)) { + env->pstate &= ~PSTATE_SS; + } + aarch64_restore_sp(env, new_el); + env->pc = env->elr_el[cur_el]; + qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " + "AArch64 EL%d PC 0x%" PRIx64 "\n", + cur_el, new_el, env->pc); + } + /* + * Note that cur_el can never be 0. If new_el is 0, then + * el0_a64 is return_to_aa64, else el0_a64 is ignored. + */ + aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64); + + qemu_mutex_lock_iothread(); + arm_call_el_change_hook(arm_env_get_cpu(env)); + qemu_mutex_unlock_iothread(); + + return; + +illegal_return: + /* Illegal return events of various kinds have architecturally + * mandated behaviour: + * restore NZCV and DAIF from SPSR_ELx + * set PSTATE.IL + * restore PC from ELR_ELx + * no change to exception level, execution state or stack pointer + */ + env->pstate |= PSTATE_IL; + env->pc = env->elr_el[cur_el]; + spsr &= PSTATE_NZCV | PSTATE_DAIF; + spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF); + pstate_write(env, spsr); + if (!arm_singlestep_active(env)) { + env->pstate &= ~PSTATE_SS; + } + qemu_log_mask(LOG_GUEST_ERROR, "Illegal exception return at EL%d: " + "resuming execution at 0x%" PRIx64 "\n", cur_el, env->pc); +} + /* * Square Root and Reciprocal square root */ diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index ef72361a36..24229981cd 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -1014,161 +1014,6 @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome) } } -static int el_from_spsr(uint32_t spsr) -{ - /* Return the exception level that this SPSR is requesting a return to, - * or -1 if it is invalid (an illegal return) - */ - if (spsr & PSTATE_nRW) { - switch (spsr & CPSR_M) { - case ARM_CPU_MODE_USR: - return 0; - case ARM_CPU_MODE_HYP: - return 2; - case ARM_CPU_MODE_FIQ: - case ARM_CPU_MODE_IRQ: - case ARM_CPU_MODE_SVC: - case ARM_CPU_MODE_ABT: - case ARM_CPU_MODE_UND: - case ARM_CPU_MODE_SYS: - return 1; - case ARM_CPU_MODE_MON: - /* Returning to Mon from AArch64 is never possible, - * so this is an illegal return. - */ - default: - return -1; - } - } else { - if (extract32(spsr, 1, 1)) { - /* Return with reserved M[1] bit set */ - return -1; - } - if (extract32(spsr, 0, 4) == 1) { - /* return to EL0 with M[0] bit set */ - return -1; - } - return extract32(spsr, 2, 2); - } -} - -void HELPER(exception_return)(CPUARMState *env) -{ - int cur_el = arm_current_el(env); - unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el); - uint32_t spsr = env->banked_spsr[spsr_idx]; - int new_el; - bool return_to_aa64 = (spsr & PSTATE_nRW) == 0; - - aarch64_save_sp(env, cur_el); - - arm_clear_exclusive(env); - - /* We must squash the PSTATE.SS bit to zero unless both of the - * following hold: - * 1. debug exceptions are currently disabled - * 2. singlestep will be active in the EL we return to - * We check 1 here and 2 after we've done the pstate/cpsr write() to - * transition to the EL we're going to. - */ - if (arm_generate_debug_exceptions(env)) { - spsr &= ~PSTATE_SS; - } - - new_el = el_from_spsr(spsr); - if (new_el == -1) { - goto illegal_return; - } - if (new_el > cur_el - || (new_el == 2 && !arm_feature(env, ARM_FEATURE_EL2))) { - /* Disallow return to an EL which is unimplemented or higher - * than the current one. - */ - goto illegal_return; - } - - if (new_el != 0 && arm_el_is_aa64(env, new_el) != return_to_aa64) { - /* Return to an EL which is configured for a different register width */ - goto illegal_return; - } - - if (new_el == 2 && arm_is_secure_below_el3(env)) { - /* Return to the non-existent secure-EL2 */ - goto illegal_return; - } - - if (new_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { - goto illegal_return; - } - - qemu_mutex_lock_iothread(); - arm_call_pre_el_change_hook(arm_env_get_cpu(env)); - qemu_mutex_unlock_iothread(); - - if (!return_to_aa64) { - env->aarch64 = 0; - /* We do a raw CPSR write because aarch64_sync_64_to_32() - * will sort the register banks out for us, and we've already - * caught all the bad-mode cases in el_from_spsr(). - */ - cpsr_write(env, spsr, ~0, CPSRWriteRaw); - if (!arm_singlestep_active(env)) { - env->uncached_cpsr &= ~PSTATE_SS; - } - aarch64_sync_64_to_32(env); - - if (spsr & CPSR_T) { - env->regs[15] = env->elr_el[cur_el] & ~0x1; - } else { - env->regs[15] = env->elr_el[cur_el] & ~0x3; - } - qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " - "AArch32 EL%d PC 0x%" PRIx32 "\n", - cur_el, new_el, env->regs[15]); - } else { - env->aarch64 = 1; - pstate_write(env, spsr); - if (!arm_singlestep_active(env)) { - env->pstate &= ~PSTATE_SS; - } - aarch64_restore_sp(env, new_el); - env->pc = env->elr_el[cur_el]; - qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " - "AArch64 EL%d PC 0x%" PRIx64 "\n", - cur_el, new_el, env->pc); - } - /* - * Note that cur_el can never be 0. If new_el is 0, then - * el0_a64 is return_to_aa64, else el0_a64 is ignored. - */ - aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64); - - qemu_mutex_lock_iothread(); - arm_call_el_change_hook(arm_env_get_cpu(env)); - qemu_mutex_unlock_iothread(); - - return; - -illegal_return: - /* Illegal return events of various kinds have architecturally - * mandated behaviour: - * restore NZCV and DAIF from SPSR_ELx - * set PSTATE.IL - * restore PC from ELR_ELx - * no change to exception level, execution state or stack pointer - */ - env->pstate |= PSTATE_IL; - env->pc = env->elr_el[cur_el]; - spsr &= PSTATE_NZCV | PSTATE_DAIF; - spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF); - pstate_write(env, spsr); - if (!arm_singlestep_active(env)) { - env->pstate &= ~PSTATE_SS; - } - qemu_log_mask(LOG_GUEST_ERROR, "Illegal exception return at EL%d: " - "resuming execution at 0x%" PRIx64 "\n", cur_el, env->pc); -} - /* Return true if the linked breakpoint entry lbn passes its checks */ static bool linked_bp_matches(ARMCPU *cpu, int lbn) { From patchwork Fri Dec 7 10:36:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153124 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp343852ljp; Fri, 7 Dec 2018 02:48:47 -0800 (PST) X-Google-Smtp-Source: AFSGD/WbgY2B906fc5I33RkbnAxujR7GboWN8y1vpUX1b/ouee1aJA2JFC8usbc6p7itDPdZgWef X-Received: by 2002:a37:bb82:: with SMTP id l124mr1292791qkf.188.1544179727051; Fri, 07 Dec 2018 02:48:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544179727; cv=none; d=google.com; s=arc-20160816; b=H6RF4Z8ZITyI4D9Ra8EZIzOOdEEfFtjPK4mEa8DAjZjtKeAuWxFsTDigomTQQ7LDaf gx7whbd/p3FO5bC6fXwbZtqXNgA5aHAGk/HZC5yPh6ck00MQjzwmX1m7L4MktXthDWGe 6aFruWbM/2iSe6n3bJDYtR18IfCEMQ7VCiNrvERAGLcUgkKLdmLI39Pn1WchxTJNQDU0 I3yitC0DJMkCOh2TPwgFx17tOREWMuU6a9ikVw3/2Tyf9fVr+sDg68aX9SDWX1WyVzZw 1FHLTh1skKSEdL300C9q2KUxZyxa9JfXg0OibHVJwTr8CYE+b4z/28w0Qu0I26qow6qA ha4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ZD9KhKx3yNscJBn17/oGmZfC0wUnvUG9NK9ZtliH2Gk=; b=f88og5lY8ZvaC8s6yslXVrwPdtXgWdA6PHbbBcrpOpz3D62yTuh4UoGK+R7GohgqzG 6xxTuhZkpjcheXgVxnN6aYJ8Xh0pXQQsmwm0w4swfb1EuPLuIhu831gJAI3/5ct1F5Xz ghs6WNA3imc5cLgz4bUA+tEbnKaGRER6G9i8uuWK/fURzIRrKdFHXbZjmk7liIqrnESb gEIPd8RyYRSXwFRvIjaWcLdgiVFNODRu/vtVHHyTaQXF4jhPNBJaThZ2DlRYmyBMjsv/ NcY6n5xQyQ9YxycbeSy9S52qQtkNE142mxdOKsMGFMTBRCC/SkFT2XwyP+8Dr1s9FHKJ Wrig== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dqP6wre9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 25si905196qkz.65.2018.12.07.02.48.46 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 07 Dec 2018 02:48:47 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dqP6wre9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45312 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDgc-0005Qb-Gg for patch@linaro.org; Fri, 07 Dec 2018 05:48:46 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59141) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDV7-000872-Fa for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVDV6-0007aT-LJ for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:53 -0500 Received: from mail-ot1-x32c.google.com ([2607:f8b0:4864:20::32c]:46420) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gVDV6-0007ZM-AK for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:52 -0500 Received: by mail-ot1-x32c.google.com with SMTP id w25so3309511otm.13 for ; Fri, 07 Dec 2018 02:36:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZD9KhKx3yNscJBn17/oGmZfC0wUnvUG9NK9ZtliH2Gk=; b=dqP6wre9sLtxPn49hSZrgbjxiJO+A0+TCeZ8viQgRUYjNc5Wom11Zye5FfwDx2BBwz mdcUFMuS04+dMRocZlB91reUVTj4mK/GGzsqBq8omjWhIOOMuQ3k/w4Ou3sXD+fTULXt y5YYGkADfj3+b6tFxSAU32/afRVicnRyeSYHc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZD9KhKx3yNscJBn17/oGmZfC0wUnvUG9NK9ZtliH2Gk=; b=qG9xeo1Vq//t3mnmzZLxfXAiuOOH5aZ4ifW2QgZVrnt8lmvLlI5Pnb4ZUeDrVjjKkr u72x5Juf9ARXPL1zhD+PQA5nG7XOGfxMJa+hi2Ctwdl/uMJDZcwUHN+Vjt2TKVRbYHBA U5NBniJPcN3zQsekv8PClJPZu+XwOwcA/4TNxDxtEpBgjzj94Oic1RCBsJTk9rc7JJtD TbCirXDPsYCIgH9ttFkDS71OiNSVhspVyp/gcLjF3xewSUrU17cARR/Rps67WYohGiZp BJz1YoPEvDBp0Ucnr418wDEwolCuptemJhDlHHQEW/nOGaYnvelmFkyHBMyr9Kq+cb5D NB/A== X-Gm-Message-State: AA+aEWZGbStdDP11eC48e29y7puoAtipPJh3Jlge87BTW7vr4BWgrcBC mOzmZoVs+PFCLeL4GK2V1glXCpNCaEQ= X-Received: by 2002:a05:6830:110f:: with SMTP id w15mr1049230otq.222.1544179011183; Fri, 07 Dec 2018 02:36:51 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.36.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:36:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:15 -0600 Message-Id: <20181207103631.28193-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org> References: <20181207103631.28193-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::32c Subject: [Qemu-devel] [PATCH 10/26] target/arm: Add new_pc argument to helper_exception_return X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 2 +- target/arm/helper-a64.c | 10 +++++----- target/arm/translate-a64.c | 7 ++++++- 3 files changed, 12 insertions(+), 7 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index cb7209eb31..b54ce59c48 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -86,7 +86,7 @@ DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr) DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr) DEF_HELPER_2(sqrt_f16, f16, f16, ptr) -DEF_HELPER_1(exception_return, void, env) +DEF_HELPER_2(exception_return, void, env, i64) DEF_HELPER_FLAGS_3(pacia, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(pacib, TCG_CALL_NO_WG, i64, env, i64, i64) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 92e751fa07..0818fd5451 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -925,7 +925,7 @@ static int el_from_spsr(uint32_t spsr) } } -void HELPER(exception_return)(CPUARMState *env) +void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) { int cur_el = arm_current_el(env); unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el); @@ -991,9 +991,9 @@ void HELPER(exception_return)(CPUARMState *env) aarch64_sync_64_to_32(env); if (spsr & CPSR_T) { - env->regs[15] = env->elr_el[cur_el] & ~0x1; + env->regs[15] = new_pc & ~0x1; } else { - env->regs[15] = env->elr_el[cur_el] & ~0x3; + env->regs[15] = new_pc & ~0x3; } qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " "AArch32 EL%d PC 0x%" PRIx32 "\n", @@ -1005,7 +1005,7 @@ void HELPER(exception_return)(CPUARMState *env) env->pstate &= ~PSTATE_SS; } aarch64_restore_sp(env, new_el); - env->pc = env->elr_el[cur_el]; + env->pc = new_pc; qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " "AArch64 EL%d PC 0x%" PRIx64 "\n", cur_el, new_el, env->pc); @@ -1031,7 +1031,7 @@ illegal_return: * no change to exception level, execution state or stack pointer */ env->pstate |= PSTATE_IL; - env->pc = env->elr_el[cur_el]; + env->pc = new_pc; spsr &= PSTATE_NZCV | PSTATE_DAIF; spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF); pstate_write(env, spsr); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d034a5edf3..c84c2dbb66 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1981,6 +1981,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) { unsigned int opc, op2, op3, rn, op4; + TCGv_i64 dst; opc = extract32(insn, 21, 4); op2 = extract32(insn, 16, 5); @@ -2011,7 +2012,11 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } - gen_helper_exception_return(cpu_env); + dst = tcg_temp_new_i64(); + tcg_gen_ld_i64(dst, cpu_env, + offsetof(CPUARMState, elr_el[s->current_el])); + gen_helper_exception_return(cpu_env, dst); + tcg_temp_free_i64(dst); if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_end(); } From patchwork Fri Dec 7 10:36:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153116 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp339380ljp; Fri, 7 Dec 2018 02:42:52 -0800 (PST) X-Google-Smtp-Source: AFSGD/U7ABnc5g0002L+pzlCVo4l+hYWtAMpMM6NIcENObLXkXzUa34ML/Seb/IBAPrFeuq8WROf X-Received: by 2002:aed:2185:: with SMTP id l5mr1461341qtc.276.1544179372075; Fri, 07 Dec 2018 02:42:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544179372; cv=none; d=google.com; s=arc-20160816; b=PeVlX3mo/R5s233cpxgpsq6aeO+HC5swX1yIECdGR5LQdkxlnCzpLkm7pRMVyJ1YFV D+Z2Bnrnb8mmDsKSjSNyqaexAllHUkyi6fi2mgDAcAhGsLJ6UEsBHxyx4MVaM4MrkC+H Jcx930VaqLnZNPF85KdVC/nspIL6/4f+HtJi908Qm1YttdxQ1d/KSsuWBGEke5eCLQsA bHswm6w7V7/OnND8FAkFF0MGXeKlW9hYCzgp3lf/Oyd8UY9evVp93uFYBOioHubA91CS 44o39rWhtp2VPx8YjOtJNPxAhpMcRBxr/EOR0aRTOs/I3n8kc+Of3jmtjKiVeAfaCED8 RNkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=k5sDymu3uuB9SOwgtcpUYLC0YD1LcUNwV8vq2tUCxfs=; b=K6yK7Lh8TFOuuJM3HWH/HM6c1yR/C621cQx6F8cnX4mzA3WZ5xurCpktHH14+MAfsi uN0rpCbAYZis6kfEdv3eSwZHdF8ZC91ApeJzDBCAmVYHLzmFkOn/Ce0Zn/j/m7P+/Y6A fIHmLoWnknClQEkfTHzHxUc2dvHdCd8lKpsg8WKb9r8J4SOGS64+j8w3I090O2avhFNh kbMJD1udzXXxRQ+++twKTufHxjIaP3PQoNgJ1s0uYzxgopsylwOoRO5Twt1B3TxoxpSt 48NfKlEDnO2XSTKg04YjEXicZD0YDxdMwdERh/kbCsoMaaQARtY8MB7PE9suuVfLhb/V Khsg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZuCwHbtV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id o5si1922651qtg.188.2018.12.07.02.42.51 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 07 Dec 2018 02:42:52 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZuCwHbtV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45276 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDat-00064P-IP for patch@linaro.org; Fri, 07 Dec 2018 05:42:51 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59162) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDV8-00088E-JB for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVDV7-0007bP-Oe for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:54 -0500 Received: from mail-oi1-x22b.google.com ([2607:f8b0:4864:20::22b]:39031) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gVDV7-0007av-Je for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:53 -0500 Received: by mail-oi1-x22b.google.com with SMTP id i6so2995443oia.6 for ; Fri, 07 Dec 2018 02:36:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=k5sDymu3uuB9SOwgtcpUYLC0YD1LcUNwV8vq2tUCxfs=; b=ZuCwHbtVq0PyGrvklNr0lST9iCpbOHeKTMvER1S4B1UPx9b1Knv9GY3hacOCmlDR9u 2WRL0YPkY+tqmRvME7xp+jm/urLql1VRx9IgLtTXCQhtC1YiiENgO/LmHATbw5Sz6M+L PzWdHoC5bw8pq3/eVM6HkLnQc8RAoTm1bqvDY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=k5sDymu3uuB9SOwgtcpUYLC0YD1LcUNwV8vq2tUCxfs=; b=BN9tmg4hS6hlhia64i0a7729irZjWfOit/PT687MXf5xoNZlr4PH5ujPV7U0T8tz7V sLRuNwScnNid2E+LldNrM4F1KFmgkEy5IRg4wLwBt/bLuMzi2u7E4gpgDxZWRTgCaqni 0Lp8KvJGemtLXRlwOoIo2Vt9nxunuyvMCjO7t6Q35odEQMw9/WCZvDbkkV/6h4J2aYpp AIUZ38tr2MtjWpV5SsqJMVVltUrPjjCoiwMg1ba6aJtzNSZNh3gekN9hIx4xTgeKjMfG j6M+Sw9yoBmvvU0xe7jtMvV4a47gWuT5X0WcBnzkfFYQpEajmJ9a/3GH4TBWQq9a86NN FrRQ== X-Gm-Message-State: AA+aEWZFkv6UYBQDiRHlR5RfDEaqmRL0q6e7Mml6f9swIzde4nJnsBr7 qj1qw2sZIG54KRYLbWFauxiO1S12PiI= X-Received: by 2002:aca:fd4a:: with SMTP id b71mr961016oii.221.1544179012616; Fri, 07 Dec 2018 02:36:52 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.36.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:36:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:16 -0600 Message-Id: <20181207103631.28193-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org> References: <20181207103631.28193-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::22b Subject: [Qemu-devel] [PATCH 11/26] target/arm: Rearrange decode in disas_uncond_b_reg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This will enable PAuth decode in a subsequent patch. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 34 +++++++++++++++++++++++----------- 1 file changed, 23 insertions(+), 11 deletions(-) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c84c2dbb66..5fa2647771 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1989,32 +1989,41 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) rn = extract32(insn, 5, 5); op4 = extract32(insn, 0, 5); - if (op4 != 0x0 || op3 != 0x0 || op2 != 0x1f) { - unallocated_encoding(s); - return; + if (op2 != 0x1f) { + goto do_unallocated; } switch (opc) { case 0: /* BR */ case 1: /* BLR */ case 2: /* RET */ - gen_a64_set_pc(s, cpu_reg(s, rn)); + if (op3 == 0 && op4 == 0) { + dst = cpu_reg(s, rn); + } else { + goto do_unallocated; + } + gen_a64_set_pc(s, dst); /* BLR also needs to load return address */ if (opc == 1) { tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); } break; + case 4: /* ERET */ if (s->current_el == 0) { - unallocated_encoding(s); - return; - } - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); + goto do_unallocated; } dst = tcg_temp_new_i64(); tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUARMState, elr_el[s->current_el])); + if (op3 == 0 && op4 == 0) { + ; + } else { + goto do_unallocated; + } + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_exception_return(cpu_env, dst); tcg_temp_free_i64(dst); if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { @@ -2023,14 +2032,17 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) /* Must exit loop to check un-masked IRQs */ s->base.is_jmp = DISAS_EXIT; return; + case 5: /* DRPS */ - if (rn != 0x1f) { - unallocated_encoding(s); + if (op3 != 0 || op4 != 0 || rn != 0x1f) { + goto do_unallocated; } else { unsupported_encoding(s, insn); } return; + default: + do_unallocated: unallocated_encoding(s); return; } From patchwork Fri Dec 7 10:36:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153118 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp341201ljp; Fri, 7 Dec 2018 02:45:18 -0800 (PST) X-Google-Smtp-Source: AFSGD/XtiYc1T+yqwJO7RJ7LBRt988VSD3QHVe1BWUJfXX2ml6CRWfcN3qR8TqF7+iQuAwwQUxN+ X-Received: by 2002:ac8:748:: with SMTP id k8mr1425830qth.235.1544179518026; Fri, 07 Dec 2018 02:45:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544179518; cv=none; d=google.com; s=arc-20160816; b=AhryUIazVPqtB4nDAehEaFS02V247S+S8BK1uo1zYNjY//TrZm7CcY11w/EKHBQf+G 5SVW8FkmSN5YttoHlEOrwQHCZX254K1wUtnrhp7JFZ+DtgeZ9l/Mpy8VIhi+3CVDXICY vXq5hZYBrW05SX0wbK9LAPilMfv2fHm5eRTSTCv2TxKNJqCkx4YqZ8YUioWG29wOM5ma yBHs1L4vMLtiaxWGoivSKcFoxub1svbJ8j2TNB+kQ2BUTrz4TBhvTflhezsUMKFABiOR 29ducTIqgqUslUYQPEIaEtZSKoolFcsYEfEbB/okOzXUhS/8rUy6D2MMySu1hwZT4UeJ gstw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=AfTh8gW2nEerFBptIiL2FcF2skV4dBXghfB4MT/cLMY=; b=JDWLvVTk8wy22gbUwAuiCIiRThtkf/STa9HOvuX+oMcN4QcprxigIpLrxvtaLNKfmz 95Qt4QtT/A6spS1TCeUuizQOX+LbePMOKmLnCmcDepT8LtfIIM8rLGllzSCu4ZJrHr0U pd5Z8nleFY/hhj0i7ZIhn0Y9RQhFqcErDsz/1L4JHiCmfxFlSSKpfaPb2qAo0+ALvvFI 9sV+1sB89CRt9PRLCVWUe1bDXu01xvlu0lEToSUZfN4GOYjGYOORqDfHC1Ty9S3RCUxt ZL2XZIUtklIAsIfHNPqG/v6QScMFaDPYqkZ8Nc+1w2qJLiyTnwnpevXqx/OVC0gTPhJ3 1zvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=eeF41a+6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id x2si2018418qta.285.2018.12.07.02.45.17 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 07 Dec 2018 02:45:18 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=eeF41a+6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45299 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDdF-0002qs-D1 for patch@linaro.org; Fri, 07 Dec 2018 05:45:17 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59174) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDVA-00089n-16 for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVDV9-0007ci-5Z for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:55 -0500 Received: from mail-ot1-x32d.google.com ([2607:f8b0:4864:20::32d]:43461) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gVDV9-0007c4-0b for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:55 -0500 Received: by mail-ot1-x32d.google.com with SMTP id a11so3336493otr.10 for ; Fri, 07 Dec 2018 02:36:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AfTh8gW2nEerFBptIiL2FcF2skV4dBXghfB4MT/cLMY=; b=eeF41a+6TXDKzbtjI9TvMb/eMa7mRxLAQE2lvo9CoOTktVDEHn5H+mDl89OfgWotxU b5SSLmrW/QoZgF8owQLl/qFq/V8IN+VbF2EP12HZsK7/Taru6jzS5KOSzcF6j+KzrEE7 S3NdyEiVkff0W3gUz0cazfQabfgIQKBcvp5fE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AfTh8gW2nEerFBptIiL2FcF2skV4dBXghfB4MT/cLMY=; b=U7IXaJ90SkUxGZtF91rh+yPrpB7BWvXqpknm9Nl+D+gUUrleboucfyjOABxb4vc2Nf IVXHzEYZBgU4Wp1IAOHTIU9NOcM5dqFC6WY2erfdPKghXd+vmpHjF4SB4vi1urH1GYxK wEFVZZ7kQSiESBq9J0X+Sfawdr1rsWD9gx5Pkk/5N7vq7BqoCGYX8J+3Mo4cHgfboxtr JVfM6z975bMf5cR75r0duB6BpFf1FdSzXI5y6vAyXBgdfNiMORmSC6Rca0je5WwhoFJJ 3usRrR9Xyk41rGeT+5sd8DLP3b0u4AdO9QmX+FFeGql1co9mNv9uZOdNaqkeIDCZWm0+ CRng== X-Gm-Message-State: AA+aEWZx6rmJjOCRxjfZPvikz4+2xV4gw6EAFn6Kr3okCrq51NmNSi+L fZLHYtnHLoFV/hHeUgbylyQ/JSzMzs8= X-Received: by 2002:a9d:88d:: with SMTP id 13mr976787otf.269.1544179014040; Fri, 07 Dec 2018 02:36:54 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.36.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:36:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:17 -0600 Message-Id: <20181207103631.28193-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org> References: <20181207103631.28193-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::32d Subject: [Qemu-devel] [PATCH 12/26] target/arm: Decode PAuth within disas_uncond_b_reg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 100 +++++++++++++++++++++++++++++++++++-- 1 file changed, 95 insertions(+), 5 deletions(-) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 5fa2647771..d4df2b48b1 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1982,6 +1982,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) { unsigned int opc, op2, op3, rn, op4; TCGv_i64 dst; + TCGv_i64 modifier; opc = extract32(insn, 21, 4); op2 = extract32(insn, 16, 5); @@ -1997,9 +1998,47 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) case 0: /* BR */ case 1: /* BLR */ case 2: /* RET */ - if (op3 == 0 && op4 == 0) { + switch (op3) { + case 0: + /* BR, BLR, RET */ + if (op4 != 0) { + goto do_unallocated; + } dst = cpu_reg(s, rn); - } else { + break; + + case 2: + case 3: + if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + if (opc == 2) { + /* RETAA, RETAB */ + if (rn != 0x1f || op4 != 0x1f) { + goto do_unallocated; + } + rn = 30; + modifier = cpu_X[31]; + } else { + /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */ + if (op4 != 0x1f) { + goto do_unallocated; + } + modifier = new_tmp_a64_zero(s); + } + if (s->pauth_active) { + dst = new_tmp_a64(s); + if (op3 == 2) { + gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier); + } else { + gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier); + } + } else { + dst = cpu_reg(s, rn); + } + break; + + default: goto do_unallocated; } gen_a64_set_pc(s, dst); @@ -2009,6 +2048,32 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) } break; + case 8: /* BRAA */ + case 9: /* BLRAA */ + if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + if (op3 != 2 || op3 != 3) { + goto do_unallocated; + } + if (s->pauth_active) { + dst = new_tmp_a64(s); + modifier = cpu_reg_sp(s, op4); + if (op3 == 2) { + gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier); + } else { + gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier); + } + } else { + dst = cpu_reg(s, rn); + } + gen_a64_set_pc(s, dst); + /* BLRAA also needs to load return address */ + if (opc == 9) { + tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); + } + break; + case 4: /* ERET */ if (s->current_el == 0) { goto do_unallocated; @@ -2016,11 +2081,36 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) dst = tcg_temp_new_i64(); tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUARMState, elr_el[s->current_el])); - if (op3 == 0 && op4 == 0) { - ; - } else { + + switch (op3) { + case 0: /* ERET */ + if (op4 != 0) { + goto do_unallocated; + } + break; + + case 2: /* ERETAA */ + case 3: /* ERETAB */ + if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + if (rn != 0x1f || op4 != 0x1f) { + goto do_unallocated; + } + if (s->pauth_active) { + modifier = cpu_X[31]; + if (op3 == 2) { + gen_helper_autia(dst, cpu_env, dst, modifier); + } else { + gen_helper_autib(dst, cpu_env, dst, modifier); + } + } + break; + + default: goto do_unallocated; } + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } From patchwork Fri Dec 7 10:36:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153121 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp341979ljp; Fri, 7 Dec 2018 02:46:20 -0800 (PST) X-Google-Smtp-Source: AFSGD/XohqFUouDETlfkEp1Zd0VkCV2szjDNiM+H2niFtEq56UiQPb/IbwVgB9s4A/S+widUir8l X-Received: by 2002:a37:5e42:: with SMTP id s63mr1262823qkb.220.1544179580168; Fri, 07 Dec 2018 02:46:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544179580; cv=none; d=google.com; s=arc-20160816; b=Yn2W58874pVe55XtuSoC3cBkzEZBtvoTZaaoDDtgP1oJVOlwV8H2TK0XDjM9rQdSzM Z8bVz8BVOtpvY20RQ64JxYTiE3Cn5R8MkZppDjpIrNfuO8+ZX/5HZgrKsuDfjd5Z9239 kmBztzzmw701AyxatQVHEmMqCFpCfhgtzV8XDVFIR/ri1hUaZdqLGsm5dzLz+/20iAdY wNDJn33Uonb8eV4K6qmTD6/n6xxkez4fqiZojuoQUOiYu4BiQZmI4PuDHyGhAsOcRTWV pLaljCjKGKoZcgC45o3y373ZTCqlXhq95WM6JcxLoF35QYo49vQSkEaDgEpPNY3ksJb3 Elsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=d5zvLHHmmieVOeK6cFWeR4Z+Tq48WSwNOYxULraeDqw=; b=Q+HxfgkNALAL24jwnE4DkhhdGIlCf8G+4wzCX0HxvmquF3vjl9kAySQQFADqdBpgEf CSQ9XA66k/ID1wmW6QryANK9E2mniKdf+7wIE1waXR4cSW0wJxtlBXa9Hl1ieUvn+oLs W59UTTs0atwaWt4b2voEeNNCb7tFcFtttQxgYHAEcFC00HBuhX1a/D1g2gbwF6Gn4GHF 3l+Ew2t2/BXmLMAErq1doGxqcs3IZsFZhSqfffAshf7dG41qPsjVEjZqVLrE6F4E8TWZ 5QN3WPFoCBKKWLwBBdALjp01ipjFh7ZudbSM2CU2gAcJ613OvKCb3Kq3vSt6b5nPpdY6 3b/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=KeEfUEFq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id q20si172487qkl.95.2018.12.07.02.46.19 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 07 Dec 2018 02:46:20 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=KeEfUEFq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45302 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDeC-0003Zu-T8 for patch@linaro.org; Fri, 07 Dec 2018 05:46:16 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59201) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDVD-0008Bt-6k for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVDVA-0007fW-Jf for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:59 -0500 Received: from mail-ot1-x334.google.com ([2607:f8b0:4864:20::334]:37925) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gVDVA-0007fD-E7 for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:56 -0500 Received: by mail-ot1-x334.google.com with SMTP id e12so3351119otl.5 for ; Fri, 07 Dec 2018 02:36:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=d5zvLHHmmieVOeK6cFWeR4Z+Tq48WSwNOYxULraeDqw=; b=KeEfUEFq6wteONVxWTamhTFy/yoDzR5/kiODiiIDAl2fmLR3Vc+YvZ4me36oW+yNzW 7vi6Pu0Ot1USTFgjAYJB2qa6JJn7Jdjaq+H7jxUrhZirwLpLM6V3fx/r21TVJqVQsLfY 22tiXeG7689ubn60mukqScvtPBbjs+dGIhc8w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=d5zvLHHmmieVOeK6cFWeR4Z+Tq48WSwNOYxULraeDqw=; b=Vi0PFIxsWw0XRXrTze0DovR+znOqCyEpQ1RSNyCUifDWfnB4UzLqgMFnffn+AIXPWG F1ov6fcyN7dk3h8HqloOhvPqHg89V4BMYKKFoUWvmFhY4jUZSIIepl0Ot3aposZPWxKQ gEGNkOAsw5tEgUEL7yd3ZTfcVZRkmIQffFo1PKU15wf/oRUrWVm/uFp4aa+VxH6dMO9e 4KfXloL91QOPBngHpcAO197jqvfzHLsbbHI8ed6B3MAp5LHe49tdNPvsmA96VokcbJcE vWASZyjXeGe63qEFAGE9ATfGaN7aEIc1wfvJtcvs+ODjfMn3rVopnsmnv8zkU88y3rIB blmw== X-Gm-Message-State: AA+aEWZc6352Rjb8aZYfc3N0x8saWSly3EKbytcDbPsnTXHf7/9NPM0F W6s/ECy7PxXyFrazEXJTGdxqaEU8RBQ= X-Received: by 2002:a9d:66f:: with SMTP id 102mr1128628otn.293.1544179015375; Fri, 07 Dec 2018 02:36:55 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.36.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:36:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:18 -0600 Message-Id: <20181207103631.28193-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org> References: <20181207103631.28193-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::334 Subject: [Qemu-devel] [PATCH 13/26] target/arm: Decode Load/store register (pac) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Not that there are any stores involved, but why argue with ARM's naming convention. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 62 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d4df2b48b1..99e1405dff 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3143,6 +3143,65 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, s->be_data | size | MO_ALIGN); } +/* PAC memory operations + * + * 31 30 27 26 24 22 21 12 11 10 5 0 + * +------+-------+---+-----+-----+---+--------+---+---+----+-----+ + * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt | + * +------+-------+---+-----+-----+------------+---+---+----+-----+ + * + * Rt: the result register + * Rn: base address or SP + * Rs: the source register for the operation + * V: vector flag (always 0 as of v8.3) + * M: clear for key DA, set for key DB + * W: pre-indexing flag + * S: sign for imm9. + */ +static void disas_ldst_pac(DisasContext *s, uint32_t insn, + int size, int rt, bool is_vector) +{ + int rn = extract32(insn, 5, 5); + bool is_wback = extract32(insn, 11, 1); + bool use_key_a = !extract32(insn, 23, 1); + int offset, memidx; + TCGv_i64 tcg_addr, tcg_rt; + + if (size != 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) { + unallocated_encoding(s); + return; + } + + if (rn == 31) { + gen_check_sp_alignment(s); + } + tcg_addr = read_cpu_reg_sp(s, rn, 1); + + if (s->pauth_active) { + if (use_key_a) { + gen_helper_autda(tcg_addr, cpu_env, tcg_addr, cpu_X[31]); + } else { + gen_helper_autdb(tcg_addr, cpu_env, tcg_addr, cpu_X[31]); + } + } + + /* Form the 10-bit signed, scaled offset. */ + offset = (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9); + offset = sextract32(offset << size, 10 + size, 0); + tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); + + tcg_rt = cpu_reg(s, rt); + memidx = get_mem_index(s); + do_gpr_ld_memidx(s, tcg_rt, tcg_addr, size, + /* is_signed */ false, /* extend */ false, memidx, + /* iss_valid */ true, /* iss_srt */ rt, + /* iss_sf */ true, /* iss_ar */ false); + + if (is_wback) { + tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr); + } +} + /* Load/store register (all forms) */ static void disas_ldst_reg(DisasContext *s, uint32_t insn) { @@ -3168,6 +3227,9 @@ static void disas_ldst_reg(DisasContext *s, uint32_t insn) case 2: disas_ldst_reg_roffset(s, insn, opc, size, rt, is_vector); return; + default: + disas_ldst_pac(s, insn, size, rt, is_vector); + return; } break; case 1: From patchwork Fri Dec 7 10:36:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153130 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp347564ljp; Fri, 7 Dec 2018 02:53:38 -0800 (PST) X-Google-Smtp-Source: AFSGD/XffR2GzZ6+RY0/X6QatMb9qjoUQLtgQfhXHaG4iuHFZhxP7cYx7p96TiRq2KGrU73I4KCB X-Received: by 2002:a37:d10:: with SMTP id 16mr1336968qkn.39.1544180018358; Fri, 07 Dec 2018 02:53:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544180018; cv=none; d=google.com; s=arc-20160816; b=p0xaSBvL54gOvoqyZPYgELL4yjVG/zoStPLCFs3wkDyou7AXeLImHkNO0cQ66+xtdE 0cfVnjmcKtDNzMLgRJfYcE2imhgcHfNomctWykWab03qXDFzox7OIBNrX+cRJDQjrRnz 02M7NjwvdAYVrilCnmg6BePBBiOzu+vFXp10rTV8m3+LRdq8c4D0Kcs0/dVuDKmRRj0y e+G8qw5n8tulfFcpaCl3yGTCRIZh9bs0jxZTkl2W3BjdRFiG1/B1lLSyqQ/4cJqRfbnh xl+5cadzqMc7yMI3oVGwu/FxaEO27ddrjMGP9IZpNQWq6f2PZez6RwXYX7AfmqjayhQg 7qBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=XvZTGTYjUe/CqE8goYOLGOvh/OEaS2UEgrpCkPuGHNk=; b=hAocMBxl1e6nT4Eu5WixMJ2f7pXTGxp7FEC0l/sH6Gavplg0P7sdIE6CFT88SDdVVx voXog9+JVB+oOkXpI77Wo2RZCZHDhug6gKSGL2FMLdbJSh+DCXHL8vpm3RA9JJN6BAUs nBr9KgP7RSAcxtBr+sqo5TBqlOLM+gldSbm012arzvTwhGgcg/iGihJFVdG9LIcTp7nD KH2BIriHiU17XeEKWoeGyg/DiVp4M9ySEfF2rhCRDcQjDv82kcgoek4hvbtdrosClVFV 3cfW8sIE+TS8BGN7buG3g0RGTZkSMpMRa/kFIxYOA7jS/OKEjObUCNFiExONgYrwzijy GZxg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AZNsB+iB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id i17si1234283qte.298.2018.12.07.02.53.38 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 07 Dec 2018 02:53:38 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AZNsB+iB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45335 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDlJ-0002mr-QM for patch@linaro.org; Fri, 07 Dec 2018 05:53:37 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59203) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDVD-0008Bu-7N for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVDVC-0007kc-0c for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:59 -0500 Received: from mail-ot1-x341.google.com ([2607:f8b0:4864:20::341]:46154) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gVDVB-0007ht-Qj for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:57 -0500 Received: by mail-ot1-x341.google.com with SMTP id w25so3309703otm.13 for ; Fri, 07 Dec 2018 02:36:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XvZTGTYjUe/CqE8goYOLGOvh/OEaS2UEgrpCkPuGHNk=; b=AZNsB+iBtTqQReyBoRZmZT1kvswobHBVscI1PbpxKdjp/gPSj1DjtFi5/03aGCewiU aOGOvuKCle72NTvgYSD1R5lT7vI+C2WuFASnMNh4If9e+oCTBK49Ky3LnLs3STgprCc+ 4jKeS0m1AHE4Zxkzszt9vjRasNQCyFScuaBpA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XvZTGTYjUe/CqE8goYOLGOvh/OEaS2UEgrpCkPuGHNk=; b=AdoFc6+0ttAZ9mgMc5y55DO+7agL0oSSv2dRBzIAl5qAUY6EiGRMihT24KbVI8I8IA yXKzKH/cmq0eTMHwoUHGTpbbDjZWCBSfjJX+p2hhE9osiN5gYNkNFIKB8HHVphtEY+3z azRylQxPM8QMonIaq5c1QRvL39rVXuny39DhaHoQR33V5tu6/Kjx2NGFL90NyhEhiuR4 eFfK737nd3YGPPbr0K5nLrYx7Ed+n4w8VXZ28Zc6WQA++7ZzeknZZysmqfztMGdFUa2m NxE3rEPyG+BuJPpno14LnuMwc2X3sY739erZKC46/QPQSCuo15kQKQa/eWvCF9fN1eDU Pn9Q== X-Gm-Message-State: AA+aEWakFA/iwy1708uU9kNATUvlUSMfqa05GEkCiPy0MSqlIRnWkJnk mzpNhEDtq6RJ4CSu1pj+1OeKRQsZ318= X-Received: by 2002:a9d:1b0:: with SMTP id e45mr1182823ote.16.1544179016818; Fri, 07 Dec 2018 02:36:56 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.36.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:36:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:19 -0600 Message-Id: <20181207103631.28193-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org> References: <20181207103631.28193-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::341 Subject: [Qemu-devel] [PATCH 14/26] target/arm: Move cpu_mmu_index out of line X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This function is, or will shortly become, too big to inline. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 48 +++++---------------------------------------- target/arm/helper.c | 44 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+), 43 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f70eff8bcf..18f2378b87 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2731,54 +2731,16 @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) } /* Return the MMU index for a v7M CPU in the specified security and - * privilege state + * privilege state. */ -static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, - bool secstate, - bool priv) -{ - ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; - - if (priv) { - mmu_idx |= ARM_MMU_IDX_M_PRIV; - } - - if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) { - mmu_idx |= ARM_MMU_IDX_M_NEGPRI; - } - - if (secstate) { - mmu_idx |= ARM_MMU_IDX_M_S; - } - - return mmu_idx; -} +ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, + bool secstate, bool priv); /* Return the MMU index for a v7M CPU in the specified security state */ -static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, - bool secstate) -{ - bool priv = arm_current_el(env) != 0; - - return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); -} +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); /* Determine the current mmu_idx to use for normal loads/stores */ -static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) -{ - int el = arm_current_el(env); - - if (arm_feature(env, ARM_FEATURE_M)) { - ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); - - return arm_to_core_mmu_idx(mmu_idx); - } - - if (el < 2 && arm_is_secure_below_el3(env)) { - return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); - } - return el; -} +int cpu_mmu_index(CPUARMState *env, bool ifetch); /* Indexes used when registering address spaces with cpu_address_space_init */ typedef enum ARMASIdx { diff --git a/target/arm/helper.c b/target/arm/helper.c index 158c550fab..eaa9e60e7b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12959,6 +12959,50 @@ int fp_exception_el(CPUARMState *env, int cur_el) return 0; } +ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, + bool secstate, bool priv) +{ + ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; + + if (priv) { + mmu_idx |= ARM_MMU_IDX_M_PRIV; + } + + if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) { + mmu_idx |= ARM_MMU_IDX_M_NEGPRI; + } + + if (secstate) { + mmu_idx |= ARM_MMU_IDX_M_S; + } + + return mmu_idx; +} + +/* Return the MMU index for a v7M CPU in the specified security state */ +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) +{ + bool priv = arm_current_el(env) != 0; + + return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); +} + +int cpu_mmu_index(CPUARMState *env, bool ifetch) +{ + int el = arm_current_el(env); + + if (arm_feature(env, ARM_FEATURE_M)) { + ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); + + return arm_to_core_mmu_idx(mmu_idx); + } + + if (el < 2 && arm_is_secure_below_el3(env)) { + return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); + } + return el; +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { From patchwork Fri Dec 7 10:36:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153127 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp345823ljp; Fri, 7 Dec 2018 02:51:16 -0800 (PST) X-Google-Smtp-Source: AFSGD/WI7Z0nMoAbf7X2/aw8YYMvn8K+nYJurtD5laxdNGAJ5eI6dNyZKRX5+Kq/e+BPJ6S/BpyT X-Received: by 2002:ac8:2d53:: with SMTP id o19mr1389464qta.21.1544179876140; Fri, 07 Dec 2018 02:51:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544179876; cv=none; d=google.com; s=arc-20160816; b=0gPjRPkV1XImwEmwe+iuTmQk1F+PjQeCsmOZxcbUt00GS+uy4+p4oDCXGtLCVTBciU IqCGjYykFAE1NDEwtLA0Odcom9pGjGIQic2j8Ja3jbMY8qVcY9RTqiQPjjpX1zPGLDQh EwoZECT62goq1F9TMvy8QPqYmJN//urufCDtgfwT3ll+LeCS9lEK/FAaWs7krHckR+Q1 xKtp1Ce2hpKBMX5vjNE/sHeOv3/29DDgcW2+I4yTWjAUMUIUEDPqd0weQnAH4wb7pKTK yytTqf1Whd/E4BzfbPsDeanBJaEpHEKWH1ZzUQEyMdfc37GVgW99FgdaFufXzGMzdpiP 6MbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=T1SS/p3u3YFxLhpOZRgkkQVS3ysBHfzBcMQrZhMcKSE=; b=hEqiRLZbwitJw7CtZrP+dl+/pBHvQO76L5u44duno+Z5co6ghBXYlvJ9XyRCxv+Dxb jtXNNOjqKBWQA0aWlZMg0gNLXpQd1wRgkRpxcn6mB4hleIxLLGFhe0ZM2+++BEmOjRcJ u+Xabd5i9B6U6PbS4w1lGtm53EObJRJ0HJf4exjObQNpIM81dvwCCuLkDBCyKAcXylDu UiypgFHMdpnlw11yNE/3eqIyxNY4EGs4talBeo/nJevK87DiE1Th82VM+ZCHYgtps2vr mOobM8mGUIAE1xtu3ad83FTt9lpwIYNxAO0Xl8AfLe21g8cWrZJl8ScPk/+j8iAlePiX rhTg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XTRxTSsC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id r15si588411qtj.56.2018.12.07.02.51.15 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 07 Dec 2018 02:51:16 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XTRxTSsC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45326 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDj1-0000TL-KV for patch@linaro.org; Fri, 07 Dec 2018 05:51:15 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59220) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDVE-0008Bv-7h for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVDVD-0007mx-Aa for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:00 -0500 Received: from mail-ot1-x342.google.com ([2607:f8b0:4864:20::342]:34822) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gVDVD-0007md-5M for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:59 -0500 Received: by mail-ot1-x342.google.com with SMTP id 81so3373723otj.2 for ; Fri, 07 Dec 2018 02:36:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=T1SS/p3u3YFxLhpOZRgkkQVS3ysBHfzBcMQrZhMcKSE=; b=XTRxTSsCpeoNHUVhe4ZTrnayE45G5urfFF6IDnP/asd84o/3oc972xs6i5dq86Cv56 ncfynJu7PAOzEfEbI/X28CznHN7Ca8Ddj6/E4a43VM7FgR/bJuRLO52REOc9fnj6oqs7 GU17nWdjOIwRtE/Zvt/OPZZ/RKn9VRSC/CT4U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=T1SS/p3u3YFxLhpOZRgkkQVS3ysBHfzBcMQrZhMcKSE=; b=Trep5BnUvBC9+fjKplEmxIgDlP7iLjZQ56F4A02iVbox1ZrvTabFiflyOxLXVfHRhQ 1003yYogjO1BL9Xxe+6VSWZV0vjy9LDEGiWfhWWF3s+IKOy3p/rowP8BOmz4KsWEjKMh tS0LXX8I5V6A6MyQmqSaeVVcTtCKNnlIOk9Fabl0PRPLyAV5YSZl6pSr9dyDtW12eb84 xeMg1GOF3pCHFpl1EjxW48pG1NqgdpkRH78UL4zfw5SPxj3Rf18gh7QxNefxxLXo1sUD 0T8OCiAdRkpsagGp0Ns04Q00gO43wZRmyU6he1+ovmqbHyXj8Z9Lpe1jRskrcVou81Sx 1Kog== X-Gm-Message-State: AA+aEWZfEaRP9DM1a5CFSFvqnHPObq0LGBU8J++CCljSuw4efnKln8yF Wwn+utz9oCAEOGzTnfMbJcRtep2Vxqc= X-Received: by 2002:a9d:7097:: with SMTP id l23mr1025680otj.49.1544179018142; Fri, 07 Dec 2018 02:36:58 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.36.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:36:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:20 -0600 Message-Id: <20181207103631.28193-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org> References: <20181207103631.28193-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 Subject: [Qemu-devel] [PATCH 15/26] target/arm: Introduce arm_mmu_idx X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The pattern ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); is computing the full ARMMMUIdx, stripping off the ARM bits, and then putting them back. Avoid the extra two steps with the appropriate helper function. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/helper.c | 27 ++++++++++++++++----------- 2 files changed, 17 insertions(+), 11 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 18f2378b87..6bac5c18d0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2740,6 +2740,7 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); /* Determine the current mmu_idx to use for normal loads/stores */ +ARMMMUIdx arm_mmu_idx(CPUARMState *env); int cpu_mmu_index(CPUARMState *env, bool ifetch); /* Indexes used when registering address spaces with cpu_address_space_init */ diff --git a/target/arm/helper.c b/target/arm/helper.c index eaa9e60e7b..be8daefc46 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7127,7 +7127,7 @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain, limit = env->v7m.msplim[M_REG_S]; } } else { - mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); + mmu_idx = arm_mmu_idx(env); frame_sp_p = &env->regs[13]; limit = v7m_sp_limit(env); } @@ -7308,7 +7308,7 @@ static bool v7m_push_stack(ARMCPU *cpu) CPUARMState *env = &cpu->env; uint32_t xpsr = xpsr_read(env); uint32_t frameptr = env->regs[13]; - ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); + ARMMMUIdx mmu_idx = arm_mmu_idx(env); /* Align stack pointer if the guest wants that */ if ((frameptr & 4) && @@ -11083,7 +11083,7 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, int prot; bool ret; ARMMMUFaultInfo fi = {}; - ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); + ARMMMUIdx mmu_idx = arm_mmu_idx(env); *attrs = (MemTxAttrs) {}; @@ -12987,26 +12987,31 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); } -int cpu_mmu_index(CPUARMState *env, bool ifetch) +ARMMMUIdx arm_mmu_idx(CPUARMState *env) { - int el = arm_current_el(env); + int el; if (arm_feature(env, ARM_FEATURE_M)) { - ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); - - return arm_to_core_mmu_idx(mmu_idx); + return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); } + el = arm_current_el(env); if (el < 2 && arm_is_secure_below_el3(env)) { - return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); + return ARMMMUIdx_S1SE0 + el; + } else { + return ARMMMUIdx_S12NSE0 + el; } - return el; +} + +int cpu_mmu_index(CPUARMState *env, bool ifetch) +{ + return arm_to_core_mmu_idx(arm_mmu_idx(env)); } void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { - ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); + ARMMMUIdx mmu_idx = arm_mmu_idx(env); int current_el = arm_current_el(env); int fp_el = fp_exception_el(env, current_el); uint32_t flags; From patchwork Fri Dec 7 10:36:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153132 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp350190ljp; Fri, 7 Dec 2018 02:57:13 -0800 (PST) X-Google-Smtp-Source: AFSGD/X9m9idcJhrNdVAGbMvzcxaAZkyI848Bowg/D7cQUHNtt1tXUV0BJBfq8OYKqvcfUVX6sh+ X-Received: by 2002:aed:384a:: with SMTP id j68mr1446429qte.171.1544180233432; Fri, 07 Dec 2018 02:57:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544180233; cv=none; d=google.com; s=arc-20160816; b=NHQi+RsD0k/50n/LaHVaFM6Vd56ckb7y4o5pbD8xD/majtAZsIbBBSKd7SusFUdY5e hTKBFtuiN9lA4oDwN48r97UjAaGfDbI1plysS2M5m6iPJMrXkbOguQdy3woeVj7fe50M tJSpo67Kg/b3FAQZbsR0c+6XORb4JckjPw34DthpVFYurSKh/G4ID1YSu2dNaJiY1zW6 SlC+OL2NK7PhHNnk7twN8DLwCSGOtKOKCuc0UoFtkScoouZorQ/2VmucXkmaaG31B4bl jkh6Q3ZPjzrhfuiCMY8KhBoHPtgOaRYUPd5zJGaqZ23hm/nHdIGWYl2piHSBAglKakTM aHuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=Ag0EZzZ3WpRd/Hxbj0lEjyeFRHKa0HzeOupdSh0X4QE=; b=jt0yYOt9PpCKweoo4zSKZPsg4vP5igSOiJEFQMCogByH/yF0MOzCGYHW2t+172NzuL 9T89c6z5QTplqH2T756qNToNU+NqsGkE1PaGFsghfIVmoeE5DGAmiEk7DtOf1UqhHrGk mOXvlcbRosr6H35QQtlDVhdpG5RQTZUXTSzCWxagzpi7/158BDIWohtwxA3XXLQLbWY7 ocT1AKCOvlFvWWZQN8r7qi4j98qOBjCWfirl5wH/3TtvrD2zcboynNxKxDsuhVLu1qSv 29TDnmW4yTUAswQp2dY61d9wsBwpD5DnT8bLe2WTv5gbKLeGe0luMqwoj9D8dd++uxH3 O+RQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=I0TudThN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id m17si2155661qkm.146.2018.12.07.02.57.13 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 07 Dec 2018 02:57:13 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=I0TudThN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45359 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDom-0006D1-V7 for patch@linaro.org; Fri, 07 Dec 2018 05:57:13 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59276) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDVL-0008Id-Sk for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVDVF-0007qR-93 for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:07 -0500 Received: from mail-ot1-x344.google.com ([2607:f8b0:4864:20::344]:46157) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gVDVE-0007pc-VN for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:01 -0500 Received: by mail-ot1-x344.google.com with SMTP id w25so3309820otm.13 for ; Fri, 07 Dec 2018 02:37:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ag0EZzZ3WpRd/Hxbj0lEjyeFRHKa0HzeOupdSh0X4QE=; b=I0TudThNGbqb0o8ZX3Y9osHtqMm7mepZpn410Zi/Zx5ed4Unzvw35awbKMyy1E1BOT A0PjRaQxKNrMsBynbo8PuPHu5JLlcQ9wxYKIU7OQ3dx6YDqARJCYwbOVlC1/ExVS8gg3 Yx9wMFgUk4tOvICsgfzcPGRpm4g0WhxLqdbkE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ag0EZzZ3WpRd/Hxbj0lEjyeFRHKa0HzeOupdSh0X4QE=; b=G/LnsfsJOynMrqMX0LJ9ORpPFwxFvuTjM0uHTuWn2+OgCMFYF12ajh5SI3QPkLAkwY I6RGNHnmLMvalVsHcpfUClUD22Guq6WlYQhOAgXp306vlhqwJ9lkKoql89gQWRnXyLcS IU9xtkce8PvfsQlXKlgIbWlclB7dFrTghYfWmbl5OnpXzNNcNtrTgbITLjD8h7viht89 Xk1Iw/MJl9TVTNOlUcfrW1I40cv/srCBnZv7jxxu3e8YIPuLGSYKqc0N7hS/XWLFPVU1 Tx9dUFngtdf/GbNkPcE9Y0Imw/vNBKYGq2tIYYmNDZvX/Xi+Wi4meLWi6RqTpMtg8Imv h67g== X-Gm-Message-State: AA+aEWakmXf1e6TXy7cyZL+BZcYaXFGNL6xPXFeYpVZJOvAILyU/iyqL 57EnA+KGyWYzZIzVE1DTDaOCyb578QQ= X-Received: by 2002:a9d:4:: with SMTP id 4mr1155661ota.174.1544179019746; Fri, 07 Dec 2018 02:36:59 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.36.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:36:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:21 -0600 Message-Id: <20181207103631.28193-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org> References: <20181207103631.28193-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 Subject: [Qemu-devel] [PATCH 16/26] target/arm: Create ARMVAParameters and helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split out functions to extract the virtual address parameters. Let the functions choose T0 or T1 address space half, if present. Extract (most of) the control bits that vary between EL or Tx. Signed-off-by: Richard Henderson --- target/arm/helper.c | 274 ++++++++++++++++++++++++-------------------- 1 file changed, 147 insertions(+), 127 deletions(-) -- 2.17.2 diff --git a/target/arm/helper.c b/target/arm/helper.c index be8daefc46..99ceed2cab 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9754,6 +9754,123 @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; } +typedef struct ARMVAParameters { + unsigned tsz : 8; + unsigned select : 1; + bool tbi : 1; + bool epd : 1; + bool hpd : 1; + bool ha : 1; + bool hd : 1; + bool using16k : 1; + bool using64k : 1; +} ARMVAParameters; + +static ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, + ARMMMUIdx mmu_idx, bool data) +{ + uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; + uint32_t el = regime_el(env, mmu_idx); + bool tbi, tbid, epd, hpd, ha, hd, using16k, using64k; + int select, tsz; + + /* Bit 55 is always between the two regions, and is canonical for + * determining if address tagging is enabled. + */ + select = extract64(va, 55, 1); + + if (el > 1) { + tsz = extract32(tcr, 0, 6); + using64k = extract32(tcr, 14, 1); + using16k = extract32(tcr, 15, 1); + tbi = extract32(tcr, 20, 1); + ha = extract32(tcr, 21, 1); + hd = extract32(tcr, 22, 1); + hpd = extract32(tcr, 24, 1); + tbid = extract32(tcr, 29, 1); + epd = false; + } else if (!select) { + tsz = extract32(tcr, 0, 6); + epd = extract32(tcr, 7, 1); + using64k = extract32(tcr, 14, 1); + using16k = extract32(tcr, 15, 1); + tbi = extract64(tcr, 37, 1); + ha = extract64(tcr, 39, 1); + hd = extract64(tcr, 40, 1); + hpd = extract64(tcr, 41, 1); + tbid = extract64(tcr, 51, 1); + } else { + int tg = extract32(tcr, 30, 2); + using16k = tg == 1; + using64k = tg == 3; + tsz = extract32(tcr, 16, 6); + epd = extract32(tcr, 23, 1); + tbi = extract64(tcr, 38, 1); + ha = extract64(tcr, 39, 1); + hd = extract64(tcr, 40, 1); + hpd = extract64(tcr, 42, 1); + tbid = extract64(tcr, 52, 1); + } + tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ + tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ + + return (ARMVAParameters) { + .tsz = tsz, + .select = select, + .tbi = tbi & (data | !tbid), + .epd = epd, + .hpd = hpd, + .ha = ha, + .hd = hd, + .using16k = using16k, + .using64k = using64k, + }; +} + +static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, + ARMMMUIdx mmu_idx) +{ + uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; + int select, tsz; + bool epd, hpd; + + if (mmu_idx == ARMMMUIdx_S2NS) { + tsz = sextract32(tcr, 0, 4) + 8; + select = 0; + hpd = false; + epd = false; + } else { + int t0sz = extract32(tcr, 0, 3); + int t1sz = extract32(tcr, 16, 3); + + if (t1sz == 0) { + select = va > (0xffffffffu >> t0sz); + } else { + /* Note that we will detect errors later. */ + select = va >= ~(0xffffffffu >> t1sz); + } + + if (!select) { + tsz = t0sz; + epd = extract32(tcr, 7, 1); + hpd = extract64(tcr, 41, 1); + } else { + tsz = t1sz; + epd = extract32(tcr, 23, 1); + hpd = extract64(tcr, 42, 1); + } + /* For aarch32, hpd0 is not enabled without t2e as well. */ + hpd &= extract32(tcr, 6, 1); + } + + return (ARMVAParameters) { + .tsz = tsz, + .select = select, + .epd = epd, + .hpd = hpd, + }; +} + static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, @@ -9765,26 +9882,20 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, /* Read an LPAE long-descriptor translation table. */ ARMFaultType fault_type = ARMFault_Translation; uint32_t level; - uint32_t epd = 0; - int32_t t0sz, t1sz; - uint32_t tg; + ARMVAParameters param; uint64_t ttbr; - int ttbr_select; hwaddr descaddr, indexmask, indexmask_grainsize; uint32_t tableattrs; target_ulong page_size; uint32_t attrs; - int32_t stride = 9; - int32_t addrsize; - int inputsize; - int32_t tbi = 0; + int32_t stride; + int top_bit, inputsize; TCR *tcr = regime_tcr(env, mmu_idx); int ap, ns, xn, pxn; uint32_t el = regime_el(env, mmu_idx); - bool ttbr1_valid = true; + bool ttbr1_valid; uint64_t descaddrmask; bool aarch64 = arm_el_is_aa64(env, el); - bool hpd = false; /* TODO: * This code does not handle the different format TCR for VTCR_EL2. @@ -9793,91 +9904,43 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, * support for those page table walks. */ if (aarch64) { + param = aa64_va_parameters(env, address, mmu_idx, + access_type != MMU_INST_FETCH); level = 0; - addrsize = 64; - if (el > 1) { - if (mmu_idx != ARMMMUIdx_S2NS) { - tbi = extract64(tcr->raw_tcr, 20, 1); - } - } else { - if (extract64(address, 55, 1)) { - tbi = extract64(tcr->raw_tcr, 38, 1); - } else { - tbi = extract64(tcr->raw_tcr, 37, 1); - } - } - tbi *= 8; - /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it * invalid. */ - if (el > 1) { - ttbr1_valid = false; - } + ttbr1_valid = (el < 1); } else { + param = aa32_va_parameters(env, address, mmu_idx); level = 1; - addrsize = 32; /* There is no TTBR1 for EL2 */ - if (el == 2) { - ttbr1_valid = false; - } + ttbr1_valid = (el != 2); } - /* Determine whether this address is in the region controlled by - * TTBR0 or TTBR1 (or if it is in neither region and should fault). - * This is a Non-secure PL0/1 stage 1 translation, so controlled by - * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32: + top_bit = (aarch64 ? 64 : 32); + inputsize = top_bit - param.tsz; + top_bit -= 8 * param.tbi; + + /* We determined the region when collecting the parameters, but we + * have not yet validated that the address is valid for the region. */ - if (aarch64) { - /* AArch64 translation. */ - t0sz = extract32(tcr->raw_tcr, 0, 6); - t0sz = MIN(t0sz, 39); - t0sz = MAX(t0sz, 16); - } else if (mmu_idx != ARMMMUIdx_S2NS) { - /* AArch32 stage 1 translation. */ - t0sz = extract32(tcr->raw_tcr, 0, 3); - } else { - /* AArch32 stage 2 translation. */ - bool sext = extract32(tcr->raw_tcr, 4, 1); - bool sign = extract32(tcr->raw_tcr, 3, 1); - /* Address size is 40-bit for a stage 2 translation, - * and t0sz can be negative (from -8 to 7), - * so we need to adjust it to use the TTBR selecting logic below. - */ - addrsize = 40; - t0sz = sextract32(tcr->raw_tcr, 0, 4) + 8; - - /* If the sign-extend bit is not the same as t0sz[3], the result - * is unpredictable. Flag this as a guest error. */ - if (sign != sext) { - qemu_log_mask(LOG_GUEST_ERROR, - "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n"); - } - } - t1sz = extract32(tcr->raw_tcr, 16, 6); - if (aarch64) { - t1sz = MIN(t1sz, 39); - t1sz = MAX(t1sz, 16); - } - if (t0sz && !extract64(address, addrsize - t0sz, t0sz - tbi)) { - /* there is a ttbr0 region and we are in it (high bits all zero) */ - ttbr_select = 0; - } else if (ttbr1_valid && t1sz && - !extract64(~address, addrsize - t1sz, t1sz - tbi)) { - /* there is a ttbr1 region and we are in it (high bits all one) */ - ttbr_select = 1; - } else if (!t0sz) { - /* ttbr0 region is "everything not in the ttbr1 region" */ - ttbr_select = 0; - } else if (!t1sz && ttbr1_valid) { - /* ttbr1 region is "everything not in the ttbr0 region" */ - ttbr_select = 1; - } else { - /* in the gap between the two regions, this is a Translation fault */ + if (param.select + ? extract64(~address, inputsize, top_bit - inputsize) || !ttbr1_valid + : extract64(address, inputsize, top_bit - inputsize)) { + /* In the gap between the two regions, this is a Translation fault */ fault_type = ARMFault_Translation; goto do_fault; } + if (param.using64k) { + stride = 13; + } else if (param.using16k) { + stride = 11; + } else { + stride = 9; + } + /* Note that QEMU ignores shareability and cacheability attributes, * so we don't need to do anything with the SH, ORGN, IRGN fields * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the @@ -9885,56 +9948,13 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, * implement any ASID-like capability so we can ignore it (instead * we will always flush the TLB any time the ASID is changed). */ - if (ttbr_select == 0) { - ttbr = regime_ttbr(env, mmu_idx, 0); - if (el < 2) { - epd = extract32(tcr->raw_tcr, 7, 1); - } - inputsize = addrsize - t0sz; - - tg = extract32(tcr->raw_tcr, 14, 2); - if (tg == 1) { /* 64KB pages */ - stride = 13; - } - if (tg == 2) { /* 16KB pages */ - stride = 11; - } - if (aarch64 && el > 1) { - hpd = extract64(tcr->raw_tcr, 24, 1); - } else { - hpd = extract64(tcr->raw_tcr, 41, 1); - } - if (!aarch64) { - /* For aarch32, hpd0 is not enabled without t2e as well. */ - hpd &= extract64(tcr->raw_tcr, 6, 1); - } - } else { - /* We should only be here if TTBR1 is valid */ - assert(ttbr1_valid); - - ttbr = regime_ttbr(env, mmu_idx, 1); - epd = extract32(tcr->raw_tcr, 23, 1); - inputsize = addrsize - t1sz; - - tg = extract32(tcr->raw_tcr, 30, 2); - if (tg == 3) { /* 64KB pages */ - stride = 13; - } - if (tg == 1) { /* 16KB pages */ - stride = 11; - } - hpd = extract64(tcr->raw_tcr, 42, 1); - if (!aarch64) { - /* For aarch32, hpd1 is not enabled without t2e as well. */ - hpd &= extract64(tcr->raw_tcr, 6, 1); - } - } + ttbr = regime_ttbr(env, mmu_idx, param.select); /* Here we should have set up all the parameters for the translation: * inputsize, ttbr, epd, stride, tbi */ - if (epd) { + if (param.epd) { /* Translation table walk disabled => Translation fault on TLB miss * Note: This is always 0 on 64-bit EL2 and EL3. */ @@ -10047,7 +10067,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, } /* Merge in attributes from table descriptors */ attrs |= nstable << 3; /* NS */ - if (hpd) { + if (param.hpd) { /* HPD disables all the table attributes except NSTable. */ break; } From patchwork Fri Dec 7 10:36:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153119 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp341422ljp; Fri, 7 Dec 2018 02:45:37 -0800 (PST) X-Google-Smtp-Source: AFSGD/VvK2ixskjcEngpvykxeiZBv3BssYOpJAG68nF18zjRurCR85J0ywz6IizoRIUukwkGpRsz X-Received: by 2002:ac8:2eb8:: with SMTP id h53mr1427910qta.18.1544179537489; Fri, 07 Dec 2018 02:45:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544179537; cv=none; d=google.com; s=arc-20160816; b=pdBD+cn/zKb7zhyKJ0HNkNlnuUmBrEuNzImu6GAn58nqsK+rYl/0nNxbuXgQt6craq MtYahwjcnqsl4C0XdaHO6Fwh2/TJ40KZmqaoLZr46jnvVCgBAOXWm7ErhOKo7Qf7T9hB vqq85C7QYizkafiO7dY8JBeFnO38MjSBMkcNAXeKwhxZUHmh34ucPhHgulxC+ZvdalIU Y6x9G4d6kB5ZasR4q6qGwa0jAJzQh7A93w5kV0SZUbOplZhf0yvQSzlxpEWTHwVijrKr iYSt65GioZ7uGFQBYfMKPw+KvnlQroMi01TbAvfCprZ6vJ3EMvb6DM280lQFyhn3fP+z mqqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=wX3ccSw4O9RNkScWYoSfbfKoW98SciKAV8QH4pR1k8Q=; b=l6v55xTuPV4L+wjmzqBgYkTdp9lzfTQa9+NSHFBoykUpipAk3l1LTc+4N83WzVDgTh rJNw/WBi0+05OZ9TF/Y09yM+hXH2ahQkyscIAh+L9qVv4tzNBqGo3SRuA9wswDe/Wn+g JMB54Mw2AdLaXphnV/DQ742zgl8O6iFArOsjWPN85KnwDE61gUCD425RG+bzfirkXNIE Hj9oE+C7J8PjejbaIvpxa3bHJHVYMFcaj2LgaJ0qCEyoELaObl8y8Gf7fOFQZ6w47eL5 8+9R8uBJwJykyBQSJvc68K21dg/37d+0wYVCVTq39Wq3cK8vcMCWhqkLtFpltnDu7E2P vpuw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Vebv5Rq3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id p58si1707040qtb.253.2018.12.07.02.45.37 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 07 Dec 2018 02:45:37 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Vebv5Rq3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45294 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDdW-0002BZ-Kt for patch@linaro.org; Fri, 07 Dec 2018 05:45:36 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59246) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDVH-0008EA-4y for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVDVG-0007sD-7A for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:03 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:33509) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gVDVG-0007qb-1T for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:02 -0500 Received: by mail-oi1-x241.google.com with SMTP id c206so3018048oib.0 for ; Fri, 07 Dec 2018 02:37:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wX3ccSw4O9RNkScWYoSfbfKoW98SciKAV8QH4pR1k8Q=; b=Vebv5Rq3Dzk+fSwWHmLbBlHmg2aJbaiuMZMwNCcrgpvCMFcBFxT4XdnONJnJR+3A7W z/nXIo+2NJx342Y3McEVqSrR7h6dn40+I7smPjUONXT7BghFzsAdU7T1GdtIuVyntTY9 zpQBDaUa4hCy1XOGS+Htw85XLR66minkgT1+E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wX3ccSw4O9RNkScWYoSfbfKoW98SciKAV8QH4pR1k8Q=; b=jYRydcytMy1I6hWChTfFxeQRKxfVpXdR0u5fSUnjFMDcHpHW26cCFJRjZEeymvhx32 OcpUgkKy08nDKNhwMLO5eRha3EURWeUFNIG9AxH578dT2MaeU168cBmQCkoYqRT/txV5 vGgInM2bVAfUtw6tvS5mSovkru2d2KY6y0Cpg8O0uPh/2nPSTHqjiyb0xfAzaAMhbqKE YOcpFC98EDYMaGYbTdxnE75OfdVPxi6Hy9ot+8UsCLSztn++e6AD/DSTztIM+TnROB9p gGZ5KYvqpX8fSjD8WfUXESAhJcK4ZhLAe4SDLDFm9jyCIDoWyGqoxt8G7DSqXUy4r6uI s8TQ== X-Gm-Message-State: AA+aEWZMcHFLFPpsnAHj4xAoJfYH6kciEJffhGwIpPlq05Ws2Y6mDROx RyvwjeIXXQa5OIljY4ThGGDZYqFdF/Q= X-Received: by 2002:aca:a60d:: with SMTP id p13mr979833oie.2.1544179021126; Fri, 07 Dec 2018 02:37:01 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.36.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:37:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:22 -0600 Message-Id: <20181207103631.28193-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org> References: <20181207103631.28193-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 Subject: [Qemu-devel] [PATCH 17/26] target/arm: Reuse aa64_va_parameters for setting tbflags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The arm_regime_tbi{0,1} functions are replacable with the new function by giving the lowest and highest address. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 35 ----------------------------- target/arm/helper.c | 55 +++++++++------------------------------------ 2 files changed, 10 insertions(+), 80 deletions(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6bac5c18d0..f7a0eace68 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3065,41 +3065,6 @@ static inline bool arm_cpu_bswap_data(CPUARMState *env) } #endif -#ifndef CONFIG_USER_ONLY -/** - * arm_regime_tbi0: - * @env: CPUARMState - * @mmu_idx: MMU index indicating required translation regime - * - * Extracts the TBI0 value from the appropriate TCR for the current EL - * - * Returns: the TBI0 value. - */ -uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx); - -/** - * arm_regime_tbi1: - * @env: CPUARMState - * @mmu_idx: MMU index indicating required translation regime - * - * Extracts the TBI1 value from the appropriate TCR for the current EL - * - * Returns: the TBI1 value. - */ -uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx); -#else -/* We can't handle tagged addresses properly in user-only mode */ -static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - return 0; -} - -static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - return 0; -} -#endif - void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags); diff --git a/target/arm/helper.c b/target/arm/helper.c index 99ceed2cab..3ad5909b1e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8967,48 +8967,6 @@ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) return mmu_idx; } -/* Returns TBI0 value for current regime el */ -uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - TCR *tcr; - uint32_t el; - - /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert - * a stage 1+2 mmu index into the appropriate stage 1 mmu index. - */ - mmu_idx = stage_1_mmu_idx(mmu_idx); - - tcr = regime_tcr(env, mmu_idx); - el = regime_el(env, mmu_idx); - - if (el > 1) { - return extract64(tcr->raw_tcr, 20, 1); - } else { - return extract64(tcr->raw_tcr, 37, 1); - } -} - -/* Returns TBI1 value for current regime el */ -uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - TCR *tcr; - uint32_t el; - - /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert - * a stage 1+2 mmu index into the appropriate stage 1 mmu index. - */ - mmu_idx = stage_1_mmu_idx(mmu_idx); - - tcr = regime_tcr(env, mmu_idx); - el = regime_el(env, mmu_idx); - - if (el > 1) { - return 0; - } else { - return extract64(tcr->raw_tcr, 38, 1); - } -} - /* Return the TTBR associated with this translation regime */ static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn) @@ -13041,9 +12999,16 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, *pc = env->pc; flags = ARM_TBFLAG_AARCH64_STATE_MASK; - /* Get control bits for tagged addresses */ - flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT); - flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT); + +#ifndef CONFIG_USER_ONLY + /* Get control bits for tagged addresses. Note that the + * translator only uses this for instruction addresses. + */ + flags |= (aa64_va_parameters(env, 0, mmu_idx, false).tbi + << ARM_TBFLAG_TBI0_SHIFT); + flags |= (aa64_va_parameters(env, -1, mmu_idx, false).tbi + << ARM_TBFLAG_TBI1_SHIFT); +#endif if (cpu_isar_feature(aa64_sve, cpu)) { int sve_el = sve_exception_el(env, current_el); From patchwork Fri Dec 7 10:36:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153131 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp349016ljp; Fri, 7 Dec 2018 02:55:35 -0800 (PST) X-Google-Smtp-Source: AFSGD/Uy/y6c36VW/FTtDfRzyJZDQKkG26xWhPXMoKtR+/OO/2mXIwHhllS7L25vOddfRIXBU0n9 X-Received: by 2002:a37:d4d9:: with SMTP id s86mr1335126qks.190.1544180135809; Fri, 07 Dec 2018 02:55:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544180135; cv=none; d=google.com; s=arc-20160816; b=S+lJ/VbG7uWKmeHGrpQasmKUZhIzK5f3c/VU9sg1kaS2jMBKDHzUHKBCg2WFesz4z5 DK9QPsIA8mteXklWadue6HmYGmrcj72OAfw62m0HAxBF9X0BIQ8ThJTJrClXcXyUUx5h wOGUcPFRHHXDIXYaoskJvoJL/uMgLMlzrBlnT6jOZTbzUCPxeVmekNmEWal9wi0GGUB1 xpQpWXgI5VFXSo38InbixTYa1c6nAoAEVCYYPaSeP2/8lIpi2ZFL289pSp0hq+1e9OZ0 FMqgperUwUFf/z6nytZkWt1LxaeU9+Q0VhXxcT2SuVn4m+xic3/x99cRbYnnXzCw5J76 Yo2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=offWiYQFX6nV0RjdB1cFsP2+NJhS8A/OLt/978IHcjg=; b=GnAqxUMRTgr+k+DFL7rmp8ldr5KBc3gv1v8I9Sjexr+y6/BTL4yB4ZGpiG+S2nM2v6 dNXb8kbvA1Eg25YsENKJO/VlyRf2eywxpLhsXu9k6C9y5Z76QF7OeepRwSRRghKq5cSv AJ0QW7G0VvSrhCeOS+kxfFwOpHQ/hLW3ofm0FpBgzsbNAJcheoN0Sld5UDrEz6+HqVeK LlaITrcdcXvFWEjffNPm+w9Ze9dINBljzpdDTIbJt1nfHafXFpsV3pw/upOUCFyqr6r0 1p5Suf+OLzBxDYWhmIrVz5IYsTVJDusbq6D8FtHjLB4PG8UcUO79wPo/TorPwB27fNo2 T4gw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jdTuc7UT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id b2si362227qtc.147.2018.12.07.02.55.35 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 07 Dec 2018 02:55:35 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jdTuc7UT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45349 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDnD-0004C1-8W for patch@linaro.org; Fri, 07 Dec 2018 05:55:35 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59264) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDVJ-0008HH-Ak for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVDVH-0007tA-MT for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:05 -0500 Received: from mail-oi1-x243.google.com ([2607:f8b0:4864:20::243]:38516) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gVDVH-0007t2-Gl for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:03 -0500 Received: by mail-oi1-x243.google.com with SMTP id a77so3000547oii.5 for ; Fri, 07 Dec 2018 02:37:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=offWiYQFX6nV0RjdB1cFsP2+NJhS8A/OLt/978IHcjg=; b=jdTuc7UTLxakTXJoDEcLuj92E6HS4WIqNWatLV19tr8AojY6hmvxZRiGCxk4Vc0+dT /W4PfTm78t1ky6eKraYBXyXDL9IqYw2edaB5/IVPZL3peKD4xWMCEkraxKDMpYIBJ9U9 PfKmyPAAeSlafuCUSJ9zuEcD4RQA9HVkd/Gr0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=offWiYQFX6nV0RjdB1cFsP2+NJhS8A/OLt/978IHcjg=; b=oDS3KEoIBAo88TPfX59wV5jflKQKPATkwa1VEELmWZFoRlkW53cNKu2SFBlhq/t+zX 9CF5MAqm2nb5Ho3ZYGUuAVM/Ea9rqk9AB3dZWVzWQADCCFReT6qaK+drmCd+GSx8Vaxo JRHKzL9R2BtILSzvParf1/BVZuBrDdn8FZ2Osp4tvg1KXd8RnmwDCCisXTN8k+WIS1AI qwZ0ZOVmWjI3OyQ12jyBAfJMp4xY1ExVG/xoWaDdvPM328wHNKTCHSTR/WrTZgVRihzl DWJM9n85Mvn2sfcslqRqldxfACB+Qu7CSTfD2BYf79TcBUApKUsrgjrI/egsDuch2DeP g8xw== X-Gm-Message-State: AA+aEWZSGckHMS4sp94+2aV6D4KMm6vs1JiHMIQJaptqDXgly6dHHfmY JaagU5I9YcIeEIv2xnirXYefh+83iQA= X-Received: by 2002:aca:b58b:: with SMTP id e133mr958099oif.25.1544179022546; Fri, 07 Dec 2018 02:37:02 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.37.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:37:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:23 -0600 Message-Id: <20181207103631.28193-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org> References: <20181207103631.28193-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::243 Subject: [Qemu-devel] [PATCH 18/26] target/arm: Export aa64_va_parameters to internals.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We need to reuse this from helper-a64.c. Provide a stub definition for CONFIG_USER_ONLY. This matches the stub definitions that we removed for arm_regime_tbi{0,1} before. Signed-off-by: Richard Henderson --- target/arm/internals.h | 29 +++++++++++++++++++++++++++++ target/arm/helper.c | 16 ++-------------- 2 files changed, 31 insertions(+), 14 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/internals.h b/target/arm/internals.h index 6bc0daf560..4d25b267e8 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -912,4 +912,33 @@ void arm_cpu_update_virq(ARMCPU *cpu); */ void arm_cpu_update_vfiq(ARMCPU *cpu); +typedef struct ARMVAParameters { + unsigned tsz : 8; + unsigned select : 1; + bool tbi : 1; + bool epd : 1; + bool hpd : 1; + bool ha : 1; + bool hd : 1; + bool using16k : 1; + bool using64k : 1; +} ARMVAParameters; + +#ifdef CONFIG_USER_ONLY +static inline ARMVAParameters aa64_va_parameters(CPUARMState *env, + uint64_t va, + ARMMMUIdx mmu_idx, bool data) +{ + return (ARMVAParameters) { + /* 48-bit address space */ + .tsz = 16, + /* We can't handle tagged addresses properly in user-only mode */ + .tbi = false, + }; +} +#else +ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, + ARMMMUIdx mmu_idx, bool data); +#endif + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index 3ad5909b1e..c73525f813 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9712,20 +9712,8 @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; } -typedef struct ARMVAParameters { - unsigned tsz : 8; - unsigned select : 1; - bool tbi : 1; - bool epd : 1; - bool hpd : 1; - bool ha : 1; - bool hd : 1; - bool using16k : 1; - bool using64k : 1; -} ARMVAParameters; - -static ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, - ARMMMUIdx mmu_idx, bool data) +ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, + ARMMMUIdx mmu_idx, bool data) { uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; uint32_t el = regime_el(env, mmu_idx); From patchwork Fri Dec 7 10:36:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153133 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp352833ljp; Fri, 7 Dec 2018 03:00:38 -0800 (PST) X-Google-Smtp-Source: AFSGD/XwAVSO9Corfh7uWBPQKoShkZ/b5PqtON14b0q8mXuVxpH00oG0kjU7u0j3k4Yc1Wz5VTEf X-Received: by 2002:a37:4953:: with SMTP id w80mr1360255qka.238.1544180438193; Fri, 07 Dec 2018 03:00:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544180438; cv=none; d=google.com; s=arc-20160816; b=NPBBNLk+5fhRZpof3eE648sFWoP5TOnlw40Pe8fUZo3AfxwcdDP/ZBlg/GB6gQ06Ld T7lO1/NMJF+wGJu7l5ovJaO+CQrCW43xgI0IKvnWG5/mwpGTRBVcDiAtxWlKAmDhFsF3 4r5/Kndj1WYY1AFWqLoU0qbOec7KmGQ6bIIdyzyXZaq7FZQ2ktW4NeYyJueqB2SJEPnc 08DwjNkvO4KEe9vz2a6n8e8tYvsv+KA+r2aqk3bJOr6cqT5hrEK8r8uAQ3d6+U11GNEb Tzd4sPt6udSlMb1Er86QsKvp3A0vnij6GV9rK9jdSjSPlipLwwxqaCDQYo+uaBBp1NXy vd/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=5yu4uyPHL3e78QtSCoAY0ppDIHvd0b6Uk3Mi12v7j8w=; b=OIjmYi1fj2EjaAMIAqHZrCKbOkm+0nTA5694azv66651vygKlplgS3pcUWgcgeIOJd 92nbm9zh3Ih+pAyT1a7EezH3J4N/PH590Vt/5NeNphQ6eABHGTfO4ETGfFptj4YAHMHE q9TtgvOfWdBgVf53R/8hBQhwNqdy+RLjToF8vJw/pYOH0f/iy7wKGdNa98TzXLXRHjze 4CuvgwQIQRjmOkdtHN65ckyaQuMZu1rHEHdrKQcbHLWXBYn3RgMgLFa3t69Z9PdBpDSE IpIc6l6JWsbI5A3d15WsL3K+TXvqYI5BYdJJR7bs8RVAoaBV0g7MGb11Jw6x/TgUtLMu fXYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OVo9lW1c; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id f3si1450230qtd.85.2018.12.07.03.00.37 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 07 Dec 2018 03:00:38 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OVo9lW1c; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45380 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDs5-00038y-Eb for patch@linaro.org; Fri, 07 Dec 2018 06:00:37 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59281) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDVN-0008J8-0z for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVDVJ-0007uU-D2 for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:08 -0500 Received: from mail-oi1-x244.google.com ([2607:f8b0:4864:20::244]:43649) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gVDVJ-0007tb-7O for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:05 -0500 Received: by mail-oi1-x244.google.com with SMTP id u18so2982962oie.10 for ; Fri, 07 Dec 2018 02:37:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5yu4uyPHL3e78QtSCoAY0ppDIHvd0b6Uk3Mi12v7j8w=; b=OVo9lW1cP5dzowO6NYScgmp7x7q3pFMv2rp/V3EckNWpDpD49g808zmYvSTJlQJ7KC IptwsYnQlE/542fyQ8OHtmKNeaqxouu1TPBmUOUS2NvUy0QEE5OWK8LvsqqAp1XipaBl ePnbceGXPjsCYsLlj559kM/DK6IjYSWaVQ78c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5yu4uyPHL3e78QtSCoAY0ppDIHvd0b6Uk3Mi12v7j8w=; b=VuxgXae1Xpdkgw7kbawSKZnXGbNRNihJhmSOEi2IkdsCjKact5kzsAwS/A95EBGC7/ 73MYkIbebvm5Qv1ua1nzGEiwpILqWSCadKILWpKnU7w/JHPlWtj6nVIsHpVNSs+U7wq3 KUVTwi6kJDeygC3POa482XtNVcHPWcYi18hXJqEj61F7rvGBF98zWSUeNgmGz3le3G45 9AEUXhewGnfd3sg/IEE8jJIJ/A97eXJGNrb9DLAPbqiV46S07HMQQOhpWOvzYGo451VS s29/aDeB4jiIqS8uiVBRQ6tLAOPB3+LoUMHODTmOrCdNSv7ajjw2Ey5vMc+R+PEl6oZr uctQ== X-Gm-Message-State: AA+aEWbzXVTQxUgyFVbqdVrlQsBnzGwQKTOereh1OJGc8llAYSr8/GPz Ng5Ph0rQkhakj1HgAKvCi8rPKANcwWU= X-Received: by 2002:aca:b2c4:: with SMTP id b187mr939690oif.245.1544179023968; Fri, 07 Dec 2018 02:37:03 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.37.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:37:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:24 -0600 Message-Id: <20181207103631.28193-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org> References: <20181207103631.28193-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::244 Subject: [Qemu-devel] [PATCH 19/26] target/arm: Implement pauth_strip X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Stripping out the authentication data does not require any crypto, it merely requires the virtual address parameters. Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) -- 2.17.2 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 0818fd5451..8860704720 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1069,15 +1069,27 @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, g_assert_not_reached(); /* FIXME */ } +static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) +{ + uint64_t extfield = -param.select; + int bot_pac_bit = 64 - param.tsz; + int top_pac_bit = 64 - 8 * param.tbi; + + return deposit64(ptr, bot_pac_bit, top_pac_bit - bot_pac_bit, extfield); +} + static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, uint64_t *key, bool data, int keynumber) { g_assert_not_reached(); /* FIXME */ } -static uint64_t pauth_strip(CPUARMState *env, uint64_t a, bool data) +static uint64_t pauth_strip(CPUARMState *env, uint64_t ptr, bool data) { - g_assert_not_reached(); /* FIXME */ + ARMMMUIdx mmu_idx = arm_mmu_idx(env); + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); + + return pauth_original_ptr(ptr, param); } static void QEMU_NORETURN pauth_trap(CPUARMState *env, int target_el, From patchwork Fri Dec 7 10:36:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153122 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp342428ljp; Fri, 7 Dec 2018 02:46:54 -0800 (PST) X-Google-Smtp-Source: AFSGD/UcDS/mtadLnvrywa5Cfevnbtq++bAQbU5HuXwOe5Vgr9J2e6GhCCkzLWct04QQE50p3jYB X-Received: by 2002:aed:2803:: with SMTP id r3mr1410510qtd.316.1544179614684; Fri, 07 Dec 2018 02:46:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544179614; cv=none; d=google.com; s=arc-20160816; b=Zl1wkYcntnhDHiLWwhZQHahb/TCFr9dVmaFoBB2z5zhTsymA0PJG1TmybudBZpnEUh FLVB+l5o6cT+njx4Q34lluQCwJW9876UjVQyYo6/hSUv6GPuQPOyzpR4nVMe/KrjNhDU +FLqqMJikVkawo0YVmERsb22cLUxD25sP2Jw/vtbOmcwdy97Dj7eAiK3xvOpoNk2fcwu JHa0r/+yXjtTbSSTEu2NFppJ8gKISF79L8eKfPXDHZcgvu0bcYElIpUAndrXBLQUaoEM jPDgstFbA+8slECVcW/t6i0IjjuOPMNdmX6myuStmyAITbQrssr9LrqxB01pocj3OudZ PMmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=v40BxgpKv12FE0ZZ8FSnShn6GuP1goSUKV4ipG2SSGc=; b=HjwznvM56vvOHIvDIdlpXuexcLbfHdygo6ISPpJwOgEhM2lEV+4HiKxMeP9R3Ifm5i nAfQPb9eVl84om+2OmVxdHkDE29p5jOg5GqP2V2yGL0N0uwzSo5xJ2/bU/wdmqt4i6bQ XTYASAtZcLfs84dZspH3cZaUOYnlMPk04e4uUOLluERy+g7EJdgcYFKUrhXD0yfpbj1s e9bllkPeLqRTLYoQciqeyqrHli84V6kAJ4VD8cy/MYDIiF6C9JZvP7AMVGKD98nJyqrh rNbLMa4soQMKD4gLhyE2frMdOzRXVO34olEkZVkv8sbDTBAbBj7dhRpraaw6KUOe7oJe Q2KA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Heq5uqRp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id h191si2305711qka.21.2018.12.07.02.46.54 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 07 Dec 2018 02:46:54 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Heq5uqRp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45304 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDen-0003g6-FW for patch@linaro.org; Fri, 07 Dec 2018 05:46:53 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59310) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDVP-0008NO-L0 for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVDVM-0007x0-Vx for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:11 -0500 Received: from mail-ot1-x343.google.com ([2607:f8b0:4864:20::343]:44470) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gVDVL-0007ud-Ny for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:07 -0500 Received: by mail-ot1-x343.google.com with SMTP id f18so3328706otl.11 for ; Fri, 07 Dec 2018 02:37:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=v40BxgpKv12FE0ZZ8FSnShn6GuP1goSUKV4ipG2SSGc=; b=Heq5uqRpMiNHc7xLJWKJcH42KfiSK8y6/ZGVa9fbtSevA9Gk05hAtVN/nEYPcmxFcH h6vgvb0XLTDNyFzEGWSGjwcXJNgHt4yuobpaF3ZN57cjZOOmUNY5J1yIXQkyN8c2wUrj +utIVMYFHA08lPWp6qeDO7PUM2c3u+rovshTM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=v40BxgpKv12FE0ZZ8FSnShn6GuP1goSUKV4ipG2SSGc=; b=Wq/nRbDvQhl7O4bydpYX1utVoi7Q93Z15Ra80dbYLo3R82vB+83abfYyU2WtLShrOI dAUxy44uvUjWjwJgY+hcU4unNVXMCaME2wZVknRxTqoKuVPSK6s5+i3VgHfpuhCE1QwB vC8OaFv4LUktaYNZtvRz2NA0A9K8geDE1jQC5LamLiRf9r4O4fmH80zSrEFbD5nlK2Jf JD8vM/hxxowmZkBC7abmQEP0Oli33daduroR4+ATy/ZujM8xZyIJpWdYu/qUzJi8mxk1 wqfsw+AZIp7nzsgqNyn845/SA9x3g+WZME/wdWeE7BXGTyXHxrp5D8o9axKHypWeqLgU Dl0A== X-Gm-Message-State: AA+aEWYbF/XmBART+uxH3T+UHildGBePwGHGef8VBSVHK82Ejix/13k7 OafXIGgTsfwzj9389/4zbXbG1Z7by1g= X-Received: by 2002:a9d:5a81:: with SMTP id w1mr1126807oth.317.1544179025289; Fri, 07 Dec 2018 02:37:05 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.37.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:37:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:25 -0600 Message-Id: <20181207103631.28193-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org> References: <20181207103631.28193-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::343 Subject: [Qemu-devel] [PATCH 20/26] target/arm: Implement pauth_auth X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is not really functional yet, because the crypto is not yet implemented. This, however follows the Auth pseudo function. Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 8860704720..2c14a71f03 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1081,7 +1081,26 @@ static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, uint64_t *key, bool data, int keynumber) { - g_assert_not_reached(); /* FIXME */ + ARMMMUIdx mmu_idx = arm_mmu_idx(env); + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); + int bot_bit, top_bit; + uint64_t pac, orig_ptr, test; + + orig_ptr = pauth_original_ptr(ptr, param); + pac = pauth_computepac(orig_ptr, modifier, key[1], key[0]); + bot_bit = 64 - param.tsz; + top_bit = 64 - 8 * param.tbi; + + test = (pac ^ ptr) & ~MAKE_64BIT_MASK(55, 1); + if (unlikely(extract64(test, bot_bit, top_bit - bot_bit))) { + int error_code = (keynumber << 1) | (keynumber ^ 1); + if (param.tbi) { + return deposit64(ptr, 53, 2, error_code); + } else { + return deposit64(ptr, 61, 2, error_code); + } + } + return orig_ptr; } static uint64_t pauth_strip(CPUARMState *env, uint64_t ptr, bool data) From patchwork Fri Dec 7 10:36:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153123 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp343591ljp; Fri, 7 Dec 2018 02:48:26 -0800 (PST) X-Google-Smtp-Source: AFSGD/WKVlZnDAZCIiNNwlxvhk6du2RZR9pyV8tyvZQR/H7fZ0wX5ELHT0TeSj9j1GcEU/xzW3gO X-Received: by 2002:a37:654b:: with SMTP id z72mr1349409qkb.226.1544179706134; Fri, 07 Dec 2018 02:48:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544179706; cv=none; d=google.com; s=arc-20160816; b=OYGYJkPUcPgsEE+96v7QwAb/K7yv7JvptTkE67BkuINmF0X2V/P9AtNT8DWpmq0WHo oGVcb/jWfLkNbZCb32qNNY+v+Q95StRSG+wIRb6DSaqEVFhLQfsMTgKkMipbBC1GENjA 8rcE1/wIuhAjwI2HNyODegFB0fCMjHVNXqNZ1nVsrWfrISAfgsC9sExNqsMGrvUyxgai whsKkrYeQyiAx9Q85q2ZcinU7iXtiv66z//M0V00kPAGeDYUNAzk26zkNnQYW3UAVqw/ t7V495jXTZTu3xzmZZxqahDk90rZXShPA9gCN6G28QFeiwrSS579X4nxp9JkCXUArU6T o/7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=mluYwWpzbSidK6xqnbY4fc6xxXyLqYViTVIwxlRneVs=; b=SYfksjFBQdPSoECgfzJM34qxj3xU2AgQGMAAuOaTI0Z+PhlNAtV+QOGWxizOYK0byr iIhimIEgz8ik3L7ZdRz6GZbr5IPDY9sdFIrLRGMbiY3CdU17IKPzXiKlvj0CXF8tAszK 5qy0FpXKsAMzHD+KJd3elZ7kL3mraUqKFqgETgosB2h53tRvkEc4EO57slqZGxdqRJgZ Nv0+CjLp8JiqZFH6D4sKK7DUwGlVA5V2tdxKeAV8nIBn27OYIM8l0lWahIWeeNRH/vFR Lb40WJL91gYwr17GfvD7j9MEeAt2+gkXKaoa5wXySB3q4mQmWhboEh+56RRqJYWiP/xu BtSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VERZwzWN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id n83si1962297qkl.183.2018.12.07.02.48.25 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 07 Dec 2018 02:48:26 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VERZwzWN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45313 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDgH-0005R9-JB for patch@linaro.org; Fri, 07 Dec 2018 05:48:25 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59299) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDVP-0008Mu-3h for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVDVN-0007xm-6V for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:10 -0500 Received: from mail-oi1-x22b.google.com ([2607:f8b0:4864:20::22b]:41787) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gVDVM-0007vI-V5 for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:09 -0500 Received: by mail-oi1-x22b.google.com with SMTP id j21so2985213oii.8 for ; Fri, 07 Dec 2018 02:37:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mluYwWpzbSidK6xqnbY4fc6xxXyLqYViTVIwxlRneVs=; b=VERZwzWNIYP3tKJNbCIpC+sVX+JmL6s2Hcu87dpx3NNjUBqYeZywF1WvAglL5zMXUf o/92TZaoM9MufJVb5JgcUsbeoKQjNJ1kc6UHzT88IOTJ5Y5o6h7sKua5T+frcMlyz/VT Li1J+iKM8sg1D7tK8KigrSGIgVFAKh5sbaQr8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mluYwWpzbSidK6xqnbY4fc6xxXyLqYViTVIwxlRneVs=; b=Ba4HgaHRe7NdMZlW4+T144nijBLhTAOTJobk5SqjimqtqQsLQ6FfkB6xTuA3EpM2T6 SR7UTmgTij/kbqVkDPLGe+8bQiOmtPFDTvcRXfiC35QbMNK4jjNyq0byqtzfw8ZpxqNT QbMHOw2S5qGQM+BQTZgO5/eJUlrFlsyWWl1qfaMb02H1YJakGeo3iWYCIrI7M52u0H6a 3fp0fBc/afxLnnALhWbcGozrdNps6ISjcPuaJUTJhjG9YZstYRqLcEKXDGsP5ENhYbBg 3BmEj8C39NJu2WylUJ5g6HToLF7pb1dftsHOcq/ea7NH12guP0BKsQrfi5ThHnVzQfut eoRQ== X-Gm-Message-State: AA+aEWYtePdOTzvefGGo5tayFeQhwSI6JB2cg1gA0UrccuTuWnJGJHHk AmLW13d1x3e+9gz/b9UsLS2oB6noSw4= X-Received: by 2002:aca:53cd:: with SMTP id h196mr959337oib.355.1544179026640; Fri, 07 Dec 2018 02:37:06 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.37.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:37:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:26 -0600 Message-Id: <20181207103631.28193-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org> References: <20181207103631.28193-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::22b Subject: [Qemu-devel] [PATCH 21/26] target/arm: Implement pauth_addpac X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is not really functional yet, because the crypto is not yet implemented. This, however follows the AddPAC pseudo function. Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 40 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 2c14a71f03..28bdf6f0b2 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1066,7 +1066,45 @@ static uint64_t pauth_computepac(uint64_t data, uint64_t modifier, static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, uint64_t *key, bool data) { - g_assert_not_reached(); /* FIXME */ + ARMMMUIdx mmu_idx = arm_mmu_idx(env); + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); + uint64_t pac, ext_ptr, ext, test; + int bot_bit, top_bit; + + /* If tagged pointers are in use, use ptr<55>, otherwise ptr<63>. */ + if (param.tbi) { + ext = sextract64(ptr, 55, 1); + } else { + ext = sextract64(ptr, 63, 1); + } + + /* Build a pointer with known good extension bits. */ + top_bit = 64 - 8 * param.tbi; + bot_bit = 64 - param.tsz; + ext_ptr = deposit64(ptr, bot_bit, top_bit - bot_bit, ext); + + pac = pauth_computepac(ext_ptr, modifier, key[1], key[0]); + + /* Check if the ptr has good extension bits and corrupt the + * pointer authentication code if not. + */ + test = sextract64(ptr, bot_bit, top_bit - bot_bit); + if (test != 0 && test != -1) { + pac ^= 1ull << (top_bit - 1); + } + + /* Preserve the determination between upper and lower at bit 55, + * and insert pointer authentication code. + */ + if (param.tbi) { + ptr &= ~MAKE_64BIT_MASK(bot_bit, 55 - bot_bit); + pac &= MAKE_64BIT_MASK(bot_bit, 54 - bot_bit); + } else { + ptr &= MAKE_64BIT_MASK(0, bot_bit - 1); + pac &= ~(MAKE_64BIT_MASK(55, 1) | MAKE_64BIT_MASK(0, bot_bit - 1)); + } + ext &= MAKE_64BIT_MASK(55, 1); + return pac | ext | ptr; } static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) From patchwork Fri Dec 7 10:36:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153125 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp343928ljp; Fri, 7 Dec 2018 02:48:52 -0800 (PST) X-Google-Smtp-Source: AFSGD/V4opCQbgjDxVkp7jHsYi6IYO2vHbTu2vSRGxMoNQPWaJg2dcyMC4tYssB5tLqSpSBqLdQg X-Received: by 2002:a37:6191:: with SMTP id v139mr1325010qkb.25.1544179731906; Fri, 07 Dec 2018 02:48:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544179731; cv=none; d=google.com; s=arc-20160816; b=hOM1/23jg+Gg5PYpOCFUh/hS/0MM2QtsKV3DWueCx78maPvMX9+b+kOJVT/h0uA9La AHg0PNUvQhvFPDprQ8eJgEDtGf1aDFkR36ANiZEdfHPRZqS6iKpJ0I6FTWilJdsEOw/U DJfOAWQZW0xDdSws5rscQUnEi+ldYsdnIQHPj7PX8o2olN57hGyDNdJkVztbL0Q5WK8A mlGC16dTGDBNITNSm9cCvlmAcuOATbpAMThYlKSNXg/o4PhWryO1Y+/LmzBEQNjjjJ2h 7GYBxAbhwullTEdnw1+k49Y51oAbWKCb6MGnrZU1pSkYfTkG5wdfEtLWSluf4VXYavvs Kgrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=uB5+GUDHh+mqCdQwaG/2qelvT+02F/oQB88LhTrzX2I=; b=wbiw8hufVLA2LD1K1koZgVP0PgIPzCc8LOo+wYpzDtIPPcEau0ggFhdjDH0WfH6hZe rCU4UZM/XzdmbJIZ+uMIlCR+0ZaQLx1wF5ctowXs37zvKyqj2z5PCe4rg1kp6xLSwlkL EWtQxG9VuOFJ2TjfWC/ZYdB/fjHh+H1McsD97u7WjuzY4Pl5dEq3wF61LrNvPgXdA/qM 8TnIA2UxmpMAdjjjYAEW3P19QQVMnsdJkE36lvz1UqswrTQTOs8noWnwx1hFww+u0Ge7 rlhqvuL4CH5/BDqdjLChj655fqQpFkCf28Fxv+fr+88I/sV7UvVH3safRcP5oV2iepQG x1Cg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="fGwb/B1R"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id i13si60948qtm.380.2018.12.07.02.48.51 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 07 Dec 2018 02:48:51 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="fGwb/B1R"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45314 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDgh-0005U7-Cw for patch@linaro.org; Fri, 07 Dec 2018 05:48:51 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59326) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDVQ-0008Ph-Ue for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVDVP-00080Z-3S for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:12 -0500 Received: from mail-ot1-x342.google.com ([2607:f8b0:4864:20::342]:39207) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gVDVN-0007wZ-3E for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:10 -0500 Received: by mail-ot1-x342.google.com with SMTP id n8so3360342otl.6 for ; Fri, 07 Dec 2018 02:37:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uB5+GUDHh+mqCdQwaG/2qelvT+02F/oQB88LhTrzX2I=; b=fGwb/B1ReikzSKUzONQ+uGm79PNaBWsX3+/rykpO/7Vxq1ECFC2jklIf/kQMKcngMO 3aWfoEotl3wuOwtmqMYbJY6X4tRTv+Tu445I665K7ngMfF412rJuO8BpQdmCeCBP2bBB KoFFyByTh1VF2FklZINCVOfqdu4gyW0xbfVAo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uB5+GUDHh+mqCdQwaG/2qelvT+02F/oQB88LhTrzX2I=; b=lnbKfW7H06MST/p/n9kU/Ko8AA4cDVfGn63teYk++s5IojkM9fyFnPLGLwCM1i2exY /+KYs9nQaRlOe/dtRvCgw6lI3tV82OoGpcBgZF27/28OmQM1Hn3yRq4i0lpnOvP2qLLp x5b5UOlgTwW9+ZSc0SNMyVF2fLbEs+39HOTQUTdJXeEX+vOLyPVe/ZE2Qfzw1topW9Yv h4GB+Q0mEzNo+JVPJd+yMsm23+ma7XEuSAhGL7cB4KiEa4ouSSDqL/UsCJ8KFeCFVWWc Gl3XN9QY29JV674oS5BWNazz/A0jBEWnJPC/wuxoFW9fEbPfBQ7mwHAr63Vr/mV283tc c3vQ== X-Gm-Message-State: AA+aEWYTVMWrdYawxREDrpnr0/Y+sPCgVK/OlEB0b7Q/kRG4CW0fC/AF kc9Z9JTVqucKZkFoxHLpoK1ThgMdy2s= X-Received: by 2002:a9d:58f:: with SMTP id 15mr1029746otd.218.1544179027988; Fri, 07 Dec 2018 02:37:07 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.37.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:37:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:27 -0600 Message-Id: <20181207103631.28193-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org> References: <20181207103631.28193-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 Subject: [Qemu-devel] [PATCH 22/26] target/arm: Implement pauth_computepac X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is the main crypto routine, an implementation of QARMA. This matches, as much as possible, ARM pseudocode. Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 240 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 239 insertions(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 28bdf6f0b2..c6755a7a07 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1057,10 +1057,248 @@ uint32_t HELPER(sqrt_f16)(uint32_t a, void *fpstp) * Helpers for ARMv8.3-PAuth. */ +static uint64_t pac_cell_shuffle(uint64_t i) +{ + uint64_t o = 0; + + o |= extract64(i, 52, 4); + o |= extract64(i, 24, 4) << 4; + o |= extract64(i, 44, 4) << 8; + o |= extract64(i, 0, 4) << 12; + + o |= extract64(i, 28, 4) << 16; + o |= extract64(i, 48, 4) << 20; + o |= extract64(i, 4, 4) << 24; + o |= extract64(i, 40, 4) << 28; + + o |= i & MAKE_64BIT_MASK(32, 4); + o |= extract64(i, 12, 4) << 36; + o |= extract64(i, 56, 4) << 40; + o |= extract64(i, 8, 4) << 44; + + o |= extract64(i, 36, 4) << 48; + o |= extract64(i, 16, 4) << 52; + o |= extract64(i, 40, 4) << 56; + o |= i & MAKE_64BIT_MASK(60, 4); + + return o; +} + +static uint64_t pac_cell_inv_shuffle(uint64_t i) +{ + uint64_t o = 0; + + o |= extract64(i, 12, 4); + o |= extract64(i, 24, 4) << 4; + o |= extract64(i, 48, 4) << 8; + o |= extract64(i, 36, 4) << 12; + + o |= extract64(i, 56, 4) << 16; + o |= extract64(i, 44, 4) << 20; + o |= extract64(i, 4, 4) << 24; + o |= extract64(i, 16, 4) << 28; + + o |= i & MAKE_64BIT_MASK(32, 4); + o |= extract64(i, 52, 4) << 36; + o |= extract64(i, 28, 4) << 40; + o |= extract64(i, 8, 4) << 44; + + o |= extract64(i, 20, 4) << 48; + o |= extract64(i, 0, 4) << 52; + o |= extract64(i, 40, 4) << 56; + o |= i & MAKE_64BIT_MASK(60, 4); + + return o; +} + +static uint64_t pac_sub(uint64_t i) +{ + static const uint8_t sub[16] = { + 0xb, 0x6, 0x8, 0xf, 0xc, 0x0, 0x9, 0xe, + 0x3, 0x7, 0x4, 0x5, 0xd, 0x2, 0x1, 0xa, + }; + uint64_t o = 0; + int b; + + for (b = 0; b < 64; b += 16) { + o |= (uint64_t)sub[(i >> b) & 0xf] << b; + } + return o; +} + +static uint64_t pac_inv_sub(uint64_t i) +{ + static const uint8_t inv_sub[16] = { + 0x5, 0xe, 0xd, 0x8, 0xa, 0xb, 0x1, 0x9, + 0x2, 0x6, 0xf, 0x0, 0x4, 0xc, 0x7, 0x3, + }; + uint64_t o = 0; + int b; + + for (b = 0; b < 64; b += 16) { + o |= (uint64_t)inv_sub[(i >> b) & 0xf] << b; + } + return o; +} + +static int rot_cell(int cell, int n) +{ + cell |= cell << 4; + cell >>= n; + return cell & 0xf; +} + +static uint64_t pac_mult(uint64_t i) +{ + uint64_t o = 0; + int b; + + for (b = 0; b < 4 * 4; b += 4) { + int i0, i4, i8, ic, t0, t1, t2, t3; + + i0 = extract64(i, b, 4); + i4 = extract64(i, b + 4 * 4, 4); + i8 = extract64(i, b + 8 * 4, 4); + ic = extract64(i, b + 12 * 4, 4); + + t0 = rot_cell(i8, 1) ^ rot_cell(i4, 2) ^ rot_cell(i0, 1); + t1 = rot_cell(ic, 1) ^ rot_cell(i4, 1) ^ rot_cell(i0, 2); + t2 = rot_cell(ic, 2) ^ rot_cell(i8, 1) ^ rot_cell(i0, 1); + t3 = rot_cell(ic, 2) ^ rot_cell(i8, 2) ^ rot_cell(i4, 1); + + o |= (uint64_t)t3 << b; + o |= (uint64_t)t2 << (b + 4 * 4); + o |= (uint64_t)t1 << (b + 8 * 4); + o |= (uint64_t)t0 << (b + 12 * 4); + } + return o; +} + +static uint64_t tweak_cell_rot(uint64_t cell) +{ + return (cell >> 1) | (((cell ^ (cell >> 1)) & 1) << 3); +} + +static uint64_t tweak_shuffle(uint64_t i) +{ + uint64_t o = 0; + + o |= extract64(i, 16, 4) << 0; + o |= extract64(i, 20, 4) << 4; + o |= tweak_cell_rot(extract64(i, 24, 4)) << 8; + o |= extract64(i, 28, 4) << 12; + + o |= tweak_cell_rot(extract64(i, 44, 4)) << 16; + o |= extract64(i, 8, 4) << 20; + o |= extract64(i, 12, 4) << 24; + o |= tweak_cell_rot(extract64(i, 32, 4)) << 28; + + o |= extract64(i, 48, 4) << 32; + o |= extract64(i, 52, 4) << 36; + o |= extract64(i, 56, 4) << 40; + o |= tweak_cell_rot(extract64(i, 60, 4)) << 44; + + o |= tweak_cell_rot(extract64(i, 0, 4)) << 48; + o |= extract64(i, 4, 4) << 52; + o |= tweak_cell_rot(extract64(i, 40, 4)) << 56; + o |= tweak_cell_rot(extract64(i, 36, 4)) << 60; + + return o; +} + +static uint64_t tweak_cell_inv_rot(uint64_t cell) +{ + return ((cell << 1) & 0xf) | ((cell & 1) ^ (cell >> 3)); +} + +static uint64_t tweak_inv_shuffle(uint64_t i) +{ + uint64_t o = 0; + + o |= tweak_cell_inv_rot(extract64(i, 48, 4)); + o |= extract64(i, 52, 4) << 4; + o |= extract64(i, 20, 4) << 8; + o |= extract64(i, 24, 4) << 12; + + o |= extract64(i, 0, 4) << 16; + o |= extract64(i, 4, 4) << 20; + o |= tweak_cell_inv_rot(extract64(i, 8, 4)) << 24; + o |= extract64(i, 12, 4) << 28; + + o |= tweak_cell_inv_rot(extract64(i, 28, 4)) << 32; + o |= tweak_cell_inv_rot(extract64(i, 60, 4)) << 36; + o |= tweak_cell_inv_rot(extract64(i, 56, 4)) << 40; + o |= tweak_cell_inv_rot(extract64(i, 16, 4)) << 44; + + o |= extract64(i, 32, 4) << 48; + o |= extract64(i, 36, 4) << 52; + o |= extract64(i, 40, 4) << 56; + o |= tweak_cell_inv_rot(extract64(i, 44, 4)) << 60; + + return o; +} + +/* Note that in the ARM pseudocode, key0 contains bits <127:64> + * and key1 contains bits <63:0> of the 128-bit key. + */ static uint64_t pauth_computepac(uint64_t data, uint64_t modifier, uint64_t key0, uint64_t key1) { - g_assert_not_reached(); /* FIXME */ + static const uint64_t RC[5] = { + 0x0000000000000000ull, + 0x13198A2E03707344ull, + 0xA4093822299F31D0ull, + 0x082EFA98EC4E6C89ull, + 0x452821E638D01377ull, + }; + const uint64_t alpha = 0xC0AC29B7C97C50DDull; + uint64_t workingval, runningmod, roundkey, modk0; + int i; + + modk0 = (key0 << 63) | ((key0 >> 1) ^ (key0 >> 63)); + runningmod = modifier; + workingval = data ^ key0; + + for (i = 0; i <= 4; ++i) { + roundkey = key1 ^ runningmod; + workingval ^= roundkey; + workingval ^= RC[i]; + if (i > 0) { + workingval = pac_cell_shuffle(workingval); + workingval = pac_mult(workingval); + } + workingval = pac_sub(workingval); + runningmod = tweak_shuffle(runningmod); + } + roundkey = modk0 ^ runningmod; + workingval ^= roundkey; + workingval = pac_cell_shuffle(workingval); + workingval = pac_mult(workingval); + workingval = pac_sub(workingval); + workingval = pac_cell_shuffle(workingval); + workingval = pac_mult(workingval); + workingval ^= key1; + workingval = pac_cell_inv_shuffle(workingval); + workingval = pac_inv_sub(workingval); + workingval = pac_mult(workingval); + workingval = pac_cell_inv_shuffle(workingval); + workingval ^= key0; + workingval ^= runningmod; + for (i = 0; i <= 4; ++i) { + workingval = pac_inv_sub(workingval); + if (i < 4) { + workingval = pac_mult(workingval); + workingval = pac_cell_inv_shuffle(workingval); + } + runningmod = tweak_inv_shuffle(runningmod); + roundkey = key1 ^ runningmod; + workingval ^= RC[4-i]; + workingval ^= roundkey; + workingval ^= alpha; + } + workingval ^= modk0; + + return workingval; } static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, From patchwork Fri Dec 7 10:36:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153126 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp344492ljp; Fri, 7 Dec 2018 02:49:39 -0800 (PST) X-Google-Smtp-Source: AFSGD/V8ciQSu+gszVlcVsmVoCh9MsG6xUsvvC9wplhl8gzIBg/8Up1gt4tswiolHKXa854PbmdJ X-Received: by 2002:a37:5257:: with SMTP id g84mr1338515qkb.76.1544179778960; Fri, 07 Dec 2018 02:49:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544179778; cv=none; d=google.com; s=arc-20160816; b=GeAyfhjtUuPZ763wK3gitvYSAO8IKhoH3Ub7EawjrgPYWQOtbUXpE5JPjbY4GKjRUQ 9k6Sn+IBaTjdHn1sUjH/s3v2s8Xi5XakjZxSHAXdp27iCq0DxV+ywG5YocO64JXwYftS 1DSMZHl3eMwIaNLkQtspqkTwQxhrH4f4QCrpxhi5a/GZbVYsZGx91Zqr4nVHxVmOBmib 6dS9plEdF8EIM8mM2Ql2xxmOUm+2FBEJ1QKjpfIjZJupTPAIiyjDXme7IP1XY4+Vfdkw PbgRO4kJah5F+1s4Q9nVS1tFEt6mhjkhz1Syt8kETSKBxoB5fSJ6ZoWj+JDJTIlk9QYZ gVNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=vKZBxe3wDrlJ4/VJOPG7grSwXuHqjLEI0JsXXyswkOE=; b=A0TYqdy5TniSxJ0deUigApreNc2rMoNDEWfjQIEfRser6AyucfrnPS/u3sWXYrpdQO bNCtDgbYCY9I39REXIZ3pnhImvN04tG1LgkJCcOl2FcXxym+WqSC4lJTF5LEfthNQ6hk f+jvRy28ol/Kc3sXXXCMHc7lgrPL2Q4xJj1OPkJpsgZ2mn7zdh0wn+DBKHJtsBPUfUyD xxrawID9oLFY30zk4ngD2IO8JnKunYkxLPb5cZ89Bi9mHFcJPY204In6Ux4bcUotg4Sk T0is4X+kfKgj2LoMVc+0IzANh8MMxDli4x1lP8FYAN7bL8fKCmlN18A7R53AE+/wfFB7 toig== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="D4L+SE/8"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id c66si1930167qkf.32.2018.12.07.02.49.38 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 07 Dec 2018 02:49:38 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="D4L+SE/8"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45316 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDhS-00070S-Bf for patch@linaro.org; Fri, 07 Dec 2018 05:49:38 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59325) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDVQ-0008Pg-UJ for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVDVP-00080p-7Q for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:12 -0500 Received: from mail-ot1-x342.google.com ([2607:f8b0:4864:20::342]:33402) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gVDVP-00080C-15 for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:11 -0500 Received: by mail-ot1-x342.google.com with SMTP id i20so3387094otl.0 for ; Fri, 07 Dec 2018 02:37:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vKZBxe3wDrlJ4/VJOPG7grSwXuHqjLEI0JsXXyswkOE=; b=D4L+SE/8ydM+X2OOotOHvvXhwQT50/FHw35HakJ6RI+Jz+WgJWNNX9OiXojpUBjrSi 1UtTTkRb1yuWwIZmW9LQ2D0URCEipqcdqhe/mgXLq2EHTHnE8EO5qIn9rruBiUT3YDNF BdbQC2Oi+XHpslyET4zgAuw0AJttp6uXEqJgc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vKZBxe3wDrlJ4/VJOPG7grSwXuHqjLEI0JsXXyswkOE=; b=HfbbKWrQJAK36TQtlPth3AR04pS89UTKC3FYyPkSf5KNUoZv3KqmiqlrUutE/BpAuD 67t9LPTInbfViJVT5AIaDm5Jf77LD8n8RAiFYuUt24J1HHpFgOZzAMcEksdyBdNW/RJg OgxsYevcnkBTUrcSCkwKHqnHBNSeHEutCFWXjgLow2OpoKRIFJgJ3XC2jCTQUhMmorjD IdKC1EZy1GdLTiFWfcsSWZuCkGA8ZMthYGB/lxM7HqR6X/hFywDRM6B256UyVHGcgBEi UfQqwlRoxHcL8C9ndTCS1QlhuBY0+/zIDbON69LLeWKMQ6jVn2HrR4vEmd69rJb4W2nb Gu9w== X-Gm-Message-State: AA+aEWb9E5Y9PZlNZSTLchyi5px05HLrTtvQNB7Ueyn1s/hy6A2ynrgF ZE5GM6lqR2cRkb650mMC5ori0HE97XI= X-Received: by 2002:a9d:6a41:: with SMTP id h1mr1122962otn.332.1544179029563; Fri, 07 Dec 2018 02:37:09 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.37.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:37:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:28 -0600 Message-Id: <20181207103631.28193-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org> References: <20181207103631.28193-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 Subject: [Qemu-devel] [PATCH 23/26] target/arm: Add PAuth system registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/helper.c | 66 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) -- 2.17.2 diff --git a/target/arm/helper.c b/target/arm/helper.c index c73525f813..f466c174e6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5071,6 +5071,66 @@ static CPAccessResult access_lor_other(CPUARMState *env, return access_lor_ns(env); } +#ifdef TARGET_AARCH64 +static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el = arm_current_el(env); + + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_APK)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && (env->cp15.scr_el3 & SCR_APK)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo pauth_reginfo[] = { + { .name = "APDAKEYLOW_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 0, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apda_key[0]) }, + { .name = "APDAKEYHI_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 1, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apda_key[1]) }, + { .name = "APDBKEYLOW_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 2, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apdb_key[0]) }, + { .name = "APDBKEYHI_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 3, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apdb_key[1]) }, + { .name = "APGAKEYLOW_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 0, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apia_key[0]) }, + { .name = "APGAKEYHI_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 1, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apia_key[1]) }, + { .name = "APIAKEYLOW_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 0, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apia_key[0]) }, + { .name = "APIAKEYHI_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 1, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apia_key[1]) }, + { .name = "APIBKEYLOW_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 2, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apib_key[0]) }, + { .name = "APIBKEYHI_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apib_key[1]) }, + REGINFO_SENTINEL +}; +#endif + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -5855,6 +5915,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &zcr_el3_reginfo); } } + +#ifdef TARGET_AARCH64 + if (cpu_isar_feature(aa64_pauth, cpu)) { + define_arm_cp_regs(cpu, pauth_reginfo); + } +#endif } void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) From patchwork Fri Dec 7 10:36:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153134 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp353069ljp; Fri, 7 Dec 2018 03:00:50 -0800 (PST) X-Google-Smtp-Source: AFSGD/WiD2tQ4/AUHneh9E5Zb8uBJ04PS26rCzgSt8QOfqoqpGSnCTTAR0KzUq+t+Jwp1rO4Gl02 X-Received: by 2002:a37:b2c2:: with SMTP id b185mr1316149qkf.194.1544180450013; Fri, 07 Dec 2018 03:00:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544180450; cv=none; d=google.com; s=arc-20160816; b=stqhbrtwi8GXv+InFJeAxAgecyQKLf3Zwtt+Vv4hAi06AkO3geWCJQm/tl4T6lJhsx HHjIimN5JS3NwKveWrtwDZQU31mmPk3sali2ybzMyZ6BuWruq2xX7hHM8BxyAs3C309N tGy7nst0m/G11CasOHV6R1jwTV37cL+93g+zoNBuCaJjmNmflAlILPCzb6mdkhTVtPiG 2kaxNyA8AkpZ4BSvrj2DP+fZKvqUa6KhYnySxF/wGub+aZtnGnAwpFGQ2c78HeoQpz9B qMKcvN878e3ACZFlxRou8a66+juazS2hum1EQhrQkshtHVyUkEedwYkvdJvj8CI6YODe 4QFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=U+CvM+uKLk7wZoL2et6kG5fijz4SeoZRCLhgUSu16Lc=; b=tNA4eAmvGG3abTDvOw09uXoPy755KdFEi7Dsq5kghjjTJFmr8qMGn3sjMES7RTQd5N vLbhO2ohI444y92udq+Ji6RplzhNZPO/xmI2ATiXOdfyJC7w4gmbgvMOg1P/KIatOvEz L/ABLaQcBc3321kynPXLrJYc9UaLTX6WTj7bxpbe1dpFmssCISaltRWZywx9rfUe0Ysp g0VBFLuGiKJbvv8InaQbkzBMFCjSvGbzBXncLDtUtgY8xZ43J5qtOw0yj04aomWOoyJd +xsl6x+wxIkBoGKJf3kZ4DjYmAC5/ZkeX2xXCKJJ+kqVjKAJ9TH/geXX3cJRI9z27Uxq MSvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZzCYzlbi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id j129si177497qkj.265.2018.12.07.03.00.49 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 07 Dec 2018 03:00:49 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZzCYzlbi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45381 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDsH-0003AL-AK for patch@linaro.org; Fri, 07 Dec 2018 06:00:49 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59356) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDVW-00007M-4y for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVDVS-00083O-ST for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:17 -0500 Received: from mail-ot1-x341.google.com ([2607:f8b0:4864:20::341]:42501) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gVDVQ-00081A-Rp for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:12 -0500 Received: by mail-ot1-x341.google.com with SMTP id v23so3332045otk.9 for ; Fri, 07 Dec 2018 02:37:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=U+CvM+uKLk7wZoL2et6kG5fijz4SeoZRCLhgUSu16Lc=; b=ZzCYzlbi/twqVQN0/OZ6HOHzP0gGrsX2Rrrev8uY4QyyErWO+5wRle5NkLzjNJjMug S0vrmqjJL/2usvF8E+QgltKNjvyQ8xNDIT2ecLZHMOJQEO5YFj7qAOG0DoVMO1z+nLhz Q/uui4nrEa6ty8GyIpk49IgC3q0EwMDZM76Is= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=U+CvM+uKLk7wZoL2et6kG5fijz4SeoZRCLhgUSu16Lc=; b=MtCS4d+qCxkEMjPNl4HE7lF7tBS2xxxC9uWi6eG4iufmx0WjUOWcH9R5yFsS22INvw zRtyJmC4dc0qafGiv3u/5kvzQcKGh7Xyda1KAz9TEjsSv8PECrUeRQyNVDWy2r1gdePG s9ED/p04c8NKBLFBOUwUvuO8fPrnkuoTqmWkCnciggIA6k7K2/EdbdMmTyfRTZ8KNpJx B1g+gbni13y8ppX7jy7DOcXXsmbgs+xe2aI9vCbf6z0huib3Idd1QNZNHOKKlDI2XsQ4 kNsNCZT/deCy8vjtyJVwQpdap+87brq8XLwT1PNb8TmcEzVtn75kE4eDqxK83207kWUN I1sA== X-Gm-Message-State: AA+aEWaKCCTZ6SnqeJBYw6JO9YF48BQq2WJb3+SCQw+mMImtPIKS1/Qy q1uV5flVC2j1sfK+Ie1BxyIP6zHihQA= X-Received: by 2002:a9d:728a:: with SMTP id t10mr1007751otj.216.1544179030932; Fri, 07 Dec 2018 02:37:10 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.37.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:37:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:29 -0600 Message-Id: <20181207103631.28193-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org> References: <20181207103631.28193-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::341 Subject: [Qemu-devel] [PATCH 24/26] target/arm: Enable PAuth for user-only -cpu max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.2 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1d57be0c91..84f70b2a24 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -316,6 +316,10 @@ static void aarch64_max_initfn(Object *obj) t = cpu->isar.id_aa64isar1; t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); + t = FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected only */ + t = FIELD_DP64(t, ID_AA64ISAR1, API, 0); + t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1); + t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0); cpu->isar.id_aa64isar1 = t; t = cpu->isar.id_aa64pfr0; From patchwork Fri Dec 7 10:36:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153128 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp346414ljp; Fri, 7 Dec 2018 02:52:09 -0800 (PST) X-Google-Smtp-Source: AFSGD/UYt+dA2zIOBGgDr3G6lNmxCrFqWsgZvp7cO7issV0ux8bavNDYrdkLzaLU3jpY14HrUQjt X-Received: by 2002:aed:2d26:: with SMTP id h35mr1454605qtd.373.1544179929616; Fri, 07 Dec 2018 02:52:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544179929; cv=none; d=google.com; s=arc-20160816; b=S9EOW6Ehg1JiDfBAzoV5o5TBUe5dahoocrrD3BCs9NIPguFoWmxcULA2QKohPU7UQf eN7iAPfC0HfNyQsSSI4eYtpXGyK8kS1dfq4RJaDAVHgbKFjKSVAn4UhaN67EB1CtTsmf RblkSKAV6lMcfLkvOPiTyVYEmFTiYJYBZn82fxcAzdMgy+iDPxZKtu7uddQ+Ox79UzNP 9HcLCozEc0s819Y5SQkzuPEMxJoIvdtt6Lre2vRfMemyZK1Rg4ffjRIGdWym0UOoEALL iwWi29Q8ZK7C1+Ml4HehrNPplCVIta8lIGN/sSZxdKrljxWMoZZ6javB3D3Ik+KJfsaX lzwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=5lV189kkOB6fne0CCcwUJT1P8TEOV3BpZfvcoTnPXCM=; b=VaL+KppxigcaBYV67x6exT59Uu1ION6ET1fAhg4gN305qjPeE4x9bMbiuUfiaM0RAv leClCFH6NAxBq8JUdeVtOtTM1IQjvQOL2pehccTCLqObQ0LPGCsobO3uiMSdmEKzb8Ny SIt8hxSCOYs2xSU3VrvB2zxgzY8CLHqsmz9/lcyvakjhK8WCO2Dn4rtArxftKM725of/ 7WTtbJMU5/7uyYZueG4Jw/bZB1YD4+EmkNjo+dCMZvVvkDf6FCYvP0oHLxJpqaUQMDXN IVVufE4z+ergPta2Sc2faZRVDnUdHipqC1IqIX3tsZhDOMqEyj0dgw40luI27mAqz1kJ jrZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=EUcDoANT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 52si2004088qvr.211.2018.12.07.02.52.09 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 07 Dec 2018 02:52:09 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=EUcDoANT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45330 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDjp-00014Y-CT for patch@linaro.org; Fri, 07 Dec 2018 05:52:08 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59359) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDVW-00007P-5a for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVDVT-00083Y-3E for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:18 -0500 Received: from mail-ot1-x344.google.com ([2607:f8b0:4864:20::344]:36579) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gVDVS-00082D-Si for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:14 -0500 Received: by mail-ot1-x344.google.com with SMTP id k98so3366346otk.3 for ; Fri, 07 Dec 2018 02:37:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5lV189kkOB6fne0CCcwUJT1P8TEOV3BpZfvcoTnPXCM=; b=EUcDoANTxOlK54eUhc+sTv+udh2nYitot4t9Etf7IQRueIYEFNRns8PX2UUNpsZWQd a7fdAdEj1bS1SvNWNd/yD6ZGH/7EWW/QXM0jcgRZoWUg9bnlkW5ojHFj5jZ8jGRS6004 jcYM2wX4tEHhMUXMKeZGioE11DwTDIRrKx4p8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5lV189kkOB6fne0CCcwUJT1P8TEOV3BpZfvcoTnPXCM=; b=s7pNrEtWeCd04ilC536sMXObVzgKgEAGoxSH4TgW6EQCVLcdbE7aGXBxQJUEE38LpE F2Ud6XiVvB1zacmyWM7V57fRnBsReBfEfFBAolr0lr+sPEXlu+DYUfusdK0IgmtucLqu VRhalyQ6QJuHEAxubILAWHxi6jv3LrS+bLy4YCqWOx6sDkihIWK8zip+XjdWbey2kdQJ YMRkc4YO7X5pwZzcfNCGnAtG/jt5HinoiBOBozWD4yOKkkfB1q3OquBvhkcGBct4wofA 4DmtaJp/yQxM+StrapM1+B9H9vDEt9al4gfNl1hXzZwAlMQMa9c5H8Dn/FI5L2cnBAjP cRvA== X-Gm-Message-State: AA+aEWYscz4iF7WKKytIZ2oZ/rF8KPLry3cB0pecYBaiq3YGkEtS0veN lws1yjqhHkD+d32DwuWgu2hlLeisPSI= X-Received: by 2002:a9d:a2e:: with SMTP id 43mr1006720otg.8.1544179032363; Fri, 07 Dec 2018 02:37:12 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.37.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:37:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:30 -0600 Message-Id: <20181207103631.28193-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org> References: <20181207103631.28193-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 Subject: [Qemu-devel] [PATCH 25/26] target/arm: Enable PAuth for user-only, part 2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" FIXME: We should have an attribute that controls the EL1 enable bits. We may not always want to turn on pointer authentication with -cpu max. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.17.2 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0b185f8d30..bc2c9eb551 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -162,6 +162,12 @@ static void arm_cpu_reset(CPUState *s) env->pstate = PSTATE_MODE_EL0t; /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; + /* Enable all PAC keys. */ + env->cp15.sctlr_el[1] |= SCTLR_EnIA | SCTLR_EnIB; + env->cp15.sctlr_el[1] |= SCTLR_EnDA | SCTLR_EnDB; + /* Enable all PAC instructions */ + env->cp15.hcr_el2 |= HCR_API; + env->cp15.scr_el3 |= SCR_API; /* and to the FP/Neon instructions */ env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); /* and to the SVE instructions */ From patchwork Fri Dec 7 10:36:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153129 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp347336ljp; Fri, 7 Dec 2018 02:53:21 -0800 (PST) X-Google-Smtp-Source: AFSGD/WRQ2b60YN5H8gEgwNopTBXRw7bOaH9MwdBCg91HIEMu9Pf2wc9lzfOdPxMimncmKU9AFL7 X-Received: by 2002:a37:8882:: with SMTP id k124mr1295145qkd.1.1544180001021; Fri, 07 Dec 2018 02:53:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544180001; cv=none; d=google.com; s=arc-20160816; b=beG/8QtL8+AzAF0MgAvf/OS2C214adKA/ucEzSgSDrwU/UZ5sPRnlCI66YnFw28IDW kV918+C/bcdRYArC6x1OxKbUas7MwgiTyaJbeKTBWxr7sLQFPSkGlf6vDd1Or7lWMnHs rN6mGCue1oTZEyBAMMK19IyBzUp/ZMBbXHyA26WzNcem4++q6Nh5WV92pO/NRL7x6C61 RhfH0ikCdsoiYbZkqUQ4FrGwKyhzNzUaF5ehc+AzD4O7HvUcyuuLZAKahanBCuYbsWRb ZB9JL/ymouE0UI/EcmKBbYSTWVo2OuDCDd0iJDXTS7P5muBhxfx03X3rGu+uxPgT21M+ jKsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=U+yA0gpIKvjd3st8336MWjcYGoymhOrHRSCnKqU8W1M=; b=VEIdXczwugOceWmbZW40KCstM8s0xdAbqwFFrWODgaO6/YhrG+TtHkHYaIpXCSpaoX gOmnLI9QtL6aUMy8sUMFUNhpgZdWeWGTCLS83ukvy+E6h2cSnNespV3oG7yqfx9mThLV 2NwVJhEZx3ytSA9tgSdpvDdyQvfAFJLAq8M2SL0YA0Qm5GoTMeM2L3jGYpfp3K22+zgR qOXV5wrnE+I8zgq6eBsBGSlT7Yhjh+79RmqeBHct3s9ng3Tq4M6xQOK5G8xOwTozwSyM cBXBoN6HURe4XC01ysnxwDxYgSALwAcawq4XZgFBno120Yu65GuEcTpfwIPwhe3vp0I/ NaCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AIZY0ejo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id q128si1959971qka.151.2018.12.07.02.53.20 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 07 Dec 2018 02:53:21 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AIZY0ejo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45336 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDl2-0002oM-Ey for patch@linaro.org; Fri, 07 Dec 2018 05:53:20 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59358) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDVW-00007O-5e for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVDVT-00083g-4l for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:18 -0500 Received: from mail-ot1-x342.google.com ([2607:f8b0:4864:20::342]:41505) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gVDVS-00082y-Vf for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:15 -0500 Received: by mail-ot1-x342.google.com with SMTP id u16so3339889otk.8 for ; Fri, 07 Dec 2018 02:37:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=U+yA0gpIKvjd3st8336MWjcYGoymhOrHRSCnKqU8W1M=; b=AIZY0ejoG1yXxsUlm3vBzEUoACwtyVyxXKTsJEN9MKhIyIBGVxmTCCD3Y1d6FwKRa8 ZG+PA2qipXo5XdDy7yPLJ7NGxm3AMcQ/5b+o13rgwtd0g5jHYGFv5sii6w9JCBc6UlFN usS6jm9wEJIsdeELqrhdL5BfkOWvWpSa26TdU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=U+yA0gpIKvjd3st8336MWjcYGoymhOrHRSCnKqU8W1M=; b=ljYoN0Y8JA6NJa6xLp2VdpKAzF0gbBb1qChmxbr046qJeOve7nS9fj0030F4RON3iJ qwOOKkACXRJoX3ruROa7Zws32zWMo4qYBnp2eXT2HtX5k11ZQSoZ43AWZ1OfQ3vLj9s7 ZVMyxQwh5P09HoJa+vC2V91xMAULXLjsx8tt5cO2L+LL7P1WPNiOlgdTLCqU6wWRhsNg p7Netzmbmeo4wCkBfZfKW0hsaazEvQJe6/JV4EYmbc+hfAufLXq9Ih/PAOMrAnpvjoD8 Xs2uxeMz57VecvfScIWxE9UJDKLf3rG1MQNqIiKWTIkrSPHq1u8XUnYpP5su/3o63C+k 31vA== X-Gm-Message-State: AA+aEWYutx+HOrKkFAiw8lhS1ka2HMHBHeo/RMmViQrs4SzKe7tgYFpO 101p1wbYlshmJ0XvIMINQMK5hcgdpiY= X-Received: by 2002:a9d:3e4a:: with SMTP id h10mr1179313otg.74.1544179033691; Fri, 07 Dec 2018 02:37:13 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.37.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:37:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:31 -0600 Message-Id: <20181207103631.28193-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org> References: <20181207103631.28193-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 Subject: [Qemu-devel] [PATCH 26/26] target/arm: Tidy TBI handling in gen_a64_set_pc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We can perform this with fewer operations. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 65 ++++++++++++++------------------------ 1 file changed, 23 insertions(+), 42 deletions(-) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 99e1405dff..15080cbb3c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -261,7 +261,7 @@ void gen_a64_set_pc_im(uint64_t val) /* Load the PC from a generic TCG variable. * * If address tagging is enabled via the TCR TBI bits, then loading - * an address into the PC will clear out any tag in the it: + * an address into the PC will clear out any tag in it: * + for EL2 and EL3 there is only one TBI bit, and if it is set * then the address is zero-extended, clearing bits [63:56] * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0 @@ -276,56 +276,37 @@ void gen_a64_set_pc_im(uint64_t val) */ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) { + bool tbi0 = s->tbi0, tbi1 = s->tbi1; if (s->current_el <= 1) { - /* Test if NEITHER or BOTH TBI values are set. If so, no need to - * examine bit 55 of address, can just generate code. - * If mixed, then test via generated code - */ - if (s->tbi0 && s->tbi1) { - TCGv_i64 tmp_reg = tcg_temp_new_i64(); - /* Both bits set, sign extension from bit 55 into [63:56] will - * cover both cases - */ - tcg_gen_shli_i64(tmp_reg, src, 8); - tcg_gen_sari_i64(cpu_pc, tmp_reg, 8); - tcg_temp_free_i64(tmp_reg); - } else if (!s->tbi0 && !s->tbi1) { - /* Neither bit set, just load it as-is */ - tcg_gen_mov_i64(cpu_pc, src); - } else { - TCGv_i64 tcg_tmpval = tcg_temp_new_i64(); - TCGv_i64 tcg_bit55 = tcg_temp_new_i64(); - TCGv_i64 tcg_zero = tcg_const_i64(0); + if (tbi0 || tbi1) { + /* Sign-extend from bit 55. */ + tcg_gen_sextract_i64(cpu_pc, src, 0, 56); - tcg_gen_andi_i64(tcg_bit55, src, (1ull << 55)); + if (tbi0 != tbi1) { + TCGv_i64 tcg_zero = tcg_const_i64(0); - if (s->tbi0) { - /* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */ - tcg_gen_andi_i64(tcg_tmpval, src, - 0x00FFFFFFFFFFFFFFull); - tcg_gen_movcond_i64(TCG_COND_EQ, cpu_pc, tcg_bit55, tcg_zero, - tcg_tmpval, src); - } else { - /* tbi0==0, tbi1==1, so 1-fill upper byte if bit 55 = 1 */ - tcg_gen_ori_i64(tcg_tmpval, src, - 0xFF00000000000000ull); - tcg_gen_movcond_i64(TCG_COND_NE, cpu_pc, tcg_bit55, tcg_zero, - tcg_tmpval, src); + /* + * The two TBI bits differ. + * If tbi0, then !tbi1: only use the extension if positive. + * if !tbi0, then tbi1: only use the extension if negative. + */ + tcg_gen_movcond_i64(tbi0 ? TCG_COND_GE : TCG_COND_LT, + cpu_pc, cpu_pc, tcg_zero, cpu_pc, src); + tcg_temp_free_i64(tcg_zero); } - tcg_temp_free_i64(tcg_zero); - tcg_temp_free_i64(tcg_bit55); - tcg_temp_free_i64(tcg_tmpval); + return; } - } else { /* EL > 1 */ - if (s->tbi0) { + } else { + if (tbi0) { /* Force tag byte to all zero */ - tcg_gen_andi_i64(cpu_pc, src, 0x00FFFFFFFFFFFFFFull); - } else { - /* Load unmodified address */ - tcg_gen_mov_i64(cpu_pc, src); + tcg_gen_extract_i64(cpu_pc, src, 0, 56); + return; } } + + /* Load unmodified address */ + tcg_gen_mov_i64(cpu_pc, src); } typedef struct DisasCompare64 {