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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y15-20020a05600015cf00b00203e324347bsm6316599wry.102.2022.03.18.06.23.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 06:23:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/21] target/arm: Fix sve2 ldnt1 and stnt1 Date: Fri, 18 Mar 2022 13:22:46 +0000 Message-Id: <20220318132306.3254960-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220318132306.3254960-1-peter.maydell@linaro.org> References: <20220318132306.3254960-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42e (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson For both ldnt1 and stnt1, the meaning of the Rn and Rm are different from ld1 and st1: the vector and integer registers are reversed, and the integer register 31 refers to XZR instead of SP. Secondly, the 64-bit version of ldnt1 was being interpreted as 32-bit unpacked unscaled offset instead of 64-bit unscaled offset, which discarded the upper 32 bits of the address coming from the vector argument. Thirdly, validate that the memory element size is in range for the vector element size for ldnt1. For ld1, we do this via independent decode patterns, but for ldnt1 we need to do it manually. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/826 Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20220308031655.240710-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/sve.decode | 5 ++- target/arm/translate-sve.c | 51 +++++++++++++++++++++++++++++-- tests/tcg/aarch64/test-826.c | 50 ++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 4 +++ tests/tcg/configure.sh | 4 +++ 5 files changed, 109 insertions(+), 5 deletions(-) create mode 100644 tests/tcg/aarch64/test-826.c diff --git a/target/arm/sve.decode b/target/arm/sve.decode index c60b9f0fec5..0388cce3bd9 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1575,10 +1575,9 @@ USDOT_zzzz 01000100 .. 0 ..... 011 110 ..... ..... @rda_rn_rm ### SVE2 Memory Gather Load Group -# SVE2 64-bit gather non-temporal load -# (scalar plus unpacked 32-bit unscaled offsets) +# SVE2 64-bit gather non-temporal load (scalar plus 64-bit unscaled offsets) LDNT1_zprz 1100010 msz:2 00 rm:5 1 u:1 0 pg:3 rn:5 rd:5 \ - &rprr_gather_load xs=0 esz=3 scale=0 ff=0 + &rprr_gather_load xs=2 esz=3 scale=0 ff=0 # SVE2 32-bit gather non-temporal load (scalar plus 32-bit unscaled offsets) LDNT1_zprz 1000010 msz:2 00 rm:5 10 u:1 pg:3 rn:5 rd:5 \ diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 33ca1bcfac3..2c23459e768 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -6487,10 +6487,33 @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a) static bool trans_LDNT1_zprz(DisasContext *s, arg_LD1_zprz *a) { + gen_helper_gvec_mem_scatter *fn = NULL; + bool be = s->be_data == MO_BE; + bool mte = s->mte_active[0]; + + if (a->esz < a->msz + !a->u) { + return false; + } if (!dc_isar_feature(aa64_sve2, s)) { return false; } - return trans_LD1_zprz(s, a); + if (!sve_access_check(s)) { + return true; + } + + switch (a->esz) { + case MO_32: + fn = gather_load_fn32[mte][be][0][0][a->u][a->msz]; + break; + case MO_64: + fn = gather_load_fn64[mte][be][0][2][a->u][a->msz]; + break; + } + assert(fn != NULL); + + do_mem_zpz(s, a->rd, a->pg, a->rn, 0, + cpu_reg(s, a->rm), a->msz, false, fn); + return true; } /* Indexed by [mte][be][xs][msz]. */ @@ -6647,10 +6670,34 @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a) static bool trans_STNT1_zprz(DisasContext *s, arg_ST1_zprz *a) { + gen_helper_gvec_mem_scatter *fn; + bool be = s->be_data == MO_BE; + bool mte = s->mte_active[0]; + + if (a->esz < a->msz) { + return false; + } if (!dc_isar_feature(aa64_sve2, s)) { return false; } - return trans_ST1_zprz(s, a); + if (!sve_access_check(s)) { + return true; + } + + switch (a->esz) { + case MO_32: + fn = scatter_store_fn32[mte][be][0][a->msz]; + break; + case MO_64: + fn = scatter_store_fn64[mte][be][2][a->msz]; + break; + default: + g_assert_not_reached(); + } + + do_mem_zpz(s, a->rd, a->pg, a->rn, 0, + cpu_reg(s, a->rm), a->msz, true, fn); + return true; } /* diff --git a/tests/tcg/aarch64/test-826.c b/tests/tcg/aarch64/test-826.c new file mode 100644 index 00000000000..f59740a8c50 --- /dev/null +++ b/tests/tcg/aarch64/test-826.c @@ -0,0 +1,50 @@ +#include +#include +#include +#include +#include +#include + +static void *expected; + +void sigsegv(int sig, siginfo_t *info, void *vuc) +{ + ucontext_t *uc = vuc; + + assert(info->si_addr == expected); + uc->uc_mcontext.pc += 4; +} + +int main() +{ + struct sigaction sa = { + .sa_sigaction = sigsegv, + .sa_flags = SA_SIGINFO + }; + + void *page; + long ofs; + + if (sigaction(SIGSEGV, &sa, NULL) < 0) { + perror("sigaction"); + return EXIT_FAILURE; + } + + page = mmap(0, getpagesize(), PROT_NONE, MAP_PRIVATE | MAP_ANON, -1, 0); + if (page == MAP_FAILED) { + perror("mmap"); + return EXIT_FAILURE; + } + + ofs = 0x124; + expected = page + ofs; + + asm("ptrue p0.d, vl1\n\t" + "dup z0.d, %0\n\t" + "ldnt1h {z1.d}, p0/z, [z0.d, %1]\n\t" + "dup z1.d, %1\n\t" + "ldnt1h {z0.d}, p0/z, [z1.d, %0]" + : : "r"(page), "r"(ofs) : "v0", "v1"); + + return EXIT_SUCCESS; +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index ac07acde66d..f7121cb4d88 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -86,7 +86,11 @@ run-gdbstub-sve-ioctls: sve-ioctls EXTRA_RUNS += run-gdbstub-sysregs run-gdbstub-sve-ioctls endif +endif +ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_SVE2),) +AARCH64_TESTS += test-826 +test-826: CFLAGS+=-march=armv8.1-a+sve2 endif TESTS += $(AARCH64_TESTS) diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh index ed4b5ccb1f0..84f928f7f87 100755 --- a/tests/tcg/configure.sh +++ b/tests/tcg/configure.sh @@ -299,6 +299,10 @@ for target in $target_list; do -march=armv8.1-a+sve -o $TMPE $TMPC; then echo "CROSS_CC_HAS_SVE=y" >> $config_target_mak fi + if do_compiler "$target_compiler" $target_compiler_cflags \ + -march=armv8.1-a+sve2 -o $TMPE $TMPC; then + echo "CROSS_CC_HAS_SVE2=y" >> $config_target_mak + fi if do_compiler "$target_compiler" $target_compiler_cflags \ -march=armv8.3-a -o $TMPE $TMPC; then echo "CROSS_CC_HAS_ARMV8_3=y" >> $config_target_mak From patchwork Fri Mar 18 13:22:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 552600 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp2072519mag; Fri, 18 Mar 2022 06:24:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwbN2fvtCHcVmPpTQI5oasgkPPV5LAMF1xG8PmLvNi/Hb0HznK/pD8DOaOksFOmKfc0ZCD/ X-Received: by 2002:a05:620a:4493:b0:67b:1ead:13b8 with SMTP id x19-20020a05620a449300b0067b1ead13b8mr5734596qkp.716.1647609867387; Fri, 18 Mar 2022 06:24:27 -0700 (PDT) ARC-Seal: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y15-20020a05600015cf00b00203e324347bsm6316599wry.102.2022.03.18.06.23.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 06:23:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/21] target/arm: Fix pauth_check_trap vs SEL2 Date: Fri, 18 Mar 2022 13:22:47 +0000 Message-Id: <20220318132306.3254960-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220318132306.3254960-1-peter.maydell@linaro.org> References: <20220318132306.3254960-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::435 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson When arm_is_el2_enabled was introduced, we missed updating pauth_check_trap. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/788 Fixes: e6ef0169264b ("target/arm: use arm_is_el2_enabled() where applicable") Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20220315021205.342768-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/pauth_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index cd6df18150b..739aa520ddd 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c @@ -390,7 +390,7 @@ static void QEMU_NORETURN pauth_trap(CPUARMState *env, int target_el, static void pauth_check_trap(CPUARMState *env, int el, uintptr_t ra) { - if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) { + if (el < 2 && arm_is_el2_enabled(env)) { uint64_t hcr = arm_hcr_el2_eff(env); bool trap = !(hcr & HCR_API); if (el == 0) { From patchwork Fri Mar 18 13:22:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 552601 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp2072567mag; Fri, 18 Mar 2022 06:24:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxyaFec6Yy9fFQUA2hTvqwYLNQGM9KkalXyqS716XG0DERt9YFnhJDt05xhyTDrZqhO0lPb X-Received: by 2002:ac8:5a8f:0:b0:2e1:df21:d86f with SMTP id c15-20020ac85a8f000000b002e1df21d86fmr7445852qtc.450.1647609872052; Fri, 18 Mar 2022 06:24:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647609872; cv=none; d=google.com; s=arc-20160816; b=pjIASVO21wBzV8ZRMf1fr/eqGIyYFj+qZTq+dTGcgAS+X8kd8tv9QpoRG0QkyFQ7pm UwD4dAJttywljSY0HkEOX4NKsbgNhFiAjhVUtJqRrMvwVWC28WS9kL2BF3yzT67kMQr/ c8Kuj3Jd3ieQAqIBPErNJPw2pt0EusxeYmqy5rjaK1uJUMSKhUPwaVXnxTL1zBwGs61K Tlmhv+TPskm0h9hKpbrBreihEjnBvfGF1SD30uJyASqUw7OCU8UPjcj5t7UcqoVBmBUU PrTWbEjUKY5j9+upFbGt3A/leeD4ZKoOQ9HV4O7wmtN0lMIWrckIjk5ViBCUUREGJMyE AHUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=JKtif+TYuN8uHF9F8OrENpLieeGqAT6wfgiqLUoWSVk=; b=PQ8GbY7SVsiyi47vIHZeo3ZRoAAg01lhf550k4WIHUQGunmafj1txWSuxS131msgGv s4CJcZtNieb5sgve2AevpvCMiMdk+u3zfM0upze+vO+WGRXuLmZ8r8J1G0vjcDTeNGiU DWhtZGwcVVjUZi5oNNSGZa0I6qIUdyX/7D1sBOtLIB7hPtysT0FEbXcO/GYgmbHW2vNS HZYZC/+cy5MBVmVXY6T9wrFp/14FDgD7v6ZLtzZbnCcfllfWz15geuy8evh3ty7LmK1s 25ZR73Ngz+hTPLzBHyfr26hYpQk7uZaj97X2tM8sVVh6dwMBRlwu+cHBTpIPgeoUg1rA Huwg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Rf+tDPeQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y15-20020a05600015cf00b00203e324347bsm6316599wry.102.2022.03.18.06.23.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 06:23:13 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/21] target/arm: Fix handling of LPAE block descriptors Date: Fri, 18 Mar 2022 13:22:48 +0000 Message-Id: <20220318132306.3254960-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220318132306.3254960-1-peter.maydell@linaro.org> References: <20220318132306.3254960-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42d (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" LPAE descriptors come in three forms: * table descriptors, giving the address of the next level page table * page descriptors, which occur only at level 3 and describe the mapping of one page (which might be 4K, 16K or 64K) * block descriptors, which occur at higher page table levels, and describe the mapping of huge pages QEMU's page-table-walk code treats block and page entries identically, simply ORing in a number of bits from the input virtual address that depends on the level of the page table that we stopped at; we depend on the previous masking of descaddr with descaddrmask to have already cleared out the low bits of the descriptor word. This is not quite right: the address field in a block descriptor is smaller, and so there are bits which are valid address bits in a page descriptor or a table descriptor but which are not supposed to be part of the address in a block descriptor, and descaddrmask does not clear them. We previously mostly got away with this because those descriptor bits are RES0; however with FEAT_BBM (part of Armv8.4) block descriptor bit 16 is defined to be the nT bit. No emulated QEMU CPU has FEAT_BBM yet, but if the host CPU has it then we might see it when using KVM or hvf. Explicitly zero out all the descaddr bits we're about to OR vaddr bits into. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/790 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220304165628.2345765-1-peter.maydell@linaro.org --- target/arm/helper.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 088956eecf0..b5c8caafe84 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11706,11 +11706,17 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, indexmask = indexmask_grainsize; continue; } - /* Block entry at level 1 or 2, or page entry at level 3. + /* + * Block entry at level 1 or 2, or page entry at level 3. * These are basically the same thing, although the number - * of bits we pull in from the vaddr varies. + * of bits we pull in from the vaddr varies. Note that although + * descaddrmask masks enough of the low bits of the descriptor + * to give a correct page or table address, the address field + * in a block descriptor is smaller; so we need to explicitly + * clear the lower bits here before ORing in the low vaddr bits. */ page_size = (1ULL << ((stride * (4 - level)) + 3)); + descaddr &= ~(page_size - 1); descaddr |= (address & (page_size - 1)); /* Extract attributes from the descriptor */ attrs = extract64(descriptor, 2, 10) From patchwork Fri Mar 18 13:22:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 552604 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp2074798mag; Fri, 18 Mar 2022 06:27:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw3d98WLZH+aTn6X3W92E4SzJCP8PtUcQe77sa+SuZUod8wmdXTvk/HbVrDj0QsyPrkW2zf X-Received: by 2002:ad4:4ea9:0:b0:440:fc40:6da9 with SMTP id ed9-20020ad44ea9000000b00440fc406da9mr2426490qvb.58.1647610068233; Fri, 18 Mar 2022 06:27:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647610068; cv=none; d=google.com; s=arc-20160816; b=Pp6guSCD+wXQ7bWcwNZreBpQ68jvSHy2SpoOT5YH57xTQI2QEpMxB437IBm+Q/qtAQ VNxNocjNMsxaYkLcjHB2zO1sjksVBtoi7O2HSVUycZrGqCq/RnCIvQSBUbehVNW4+yHp M4wgb1Yi/rXHiT4Xp1CWURrnx3yGNtgpCa6d+yllYEo7L9r+DeL0kjlFABbWleXXfkBA kwlHhzGBXBne7k98E5EEhniUvSHJ4y58R8/653yeXtXcI+UDZMCkKaEFhbwssKLqpt6x asZfAgdIbXeA4ZZeDcdidrfZmMws7qx+/t9Q35dO0w86Vjw+VIdDvILUWDi5ve7JgcjZ N7qA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dOFSsJD7GyN8WerJViFJLtaAtHU5mpmh2G7A0ZQ4yoM=; b=Tx5uKrhJ4lhCLkbk1WlyxQqXzvgQxJ5CWd1YG/ylM9wu4xlvu/LnZ8P8jJxwToShgU 0/1uFuldsaKKzehOtmMgLJkoMIWcZoTy4T7AGebVmSp0+coEZ/xp96uG1ecME4QiqSDT 4FbySlFhR5ORtetXJosN6e9lX7TzjJpjF2po+1H365saurAz5V3O1cP+a2+HPmo68mCS CcLo5mV1Nd6Y0qb0pwrYbCIjZB+SV6IpFGREF2vDx8gN0K3XzGiJ0LponZWWIlllfF5q pYPm/ZxcmusByA1WVO6EAKBbDUS1I93qDXrhttFiiJU0LCerSnW8WvcuV3z2AMy8E9cN 2GHg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sY14NSzv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y15-20020a05600015cf00b00203e324347bsm6316599wry.102.2022.03.18.06.23.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 06:23:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/21] hw/dma/xlnx_csu_dma: Set TYPE_XLNX_CSU_DMA class_size Date: Fri, 18 Mar 2022 13:22:49 +0000 Message-Id: <20220318132306.3254960-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220318132306.3254960-1-peter.maydell@linaro.org> References: <20220318132306.3254960-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32c (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In commit 00f05c02f9e7342f we gave the TYPE_XLNX_CSU_DMA object its own class struct, but forgot to update the TypeInfo::class_size accordingly. This meant that not enough memory was allocated for the class struct, and the initialization of xcdc->read in the class init function wrote off the end of the memory. Add the missing line. Found by running 'check-qtest-aarch64' with a clang address-sanitizer build, which complains: ==2542634==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x61000000ab00 at pc 0x559a20aebc29 bp 0x7fff97df74d0 sp 0x7fff97df74c8 WRITE of size 8 at 0x61000000ab00 thread T0 #0 0x559a20aebc28 in xlnx_csu_dma_class_init /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../hw/dma/xlnx_csu_dma.c:722:16 #1 0x559a21bf297c in type_initialize /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:365:9 #2 0x559a21bf3442 in object_class_foreach_tramp /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:1070:5 #3 0x7f09bcb641b7 in g_hash_table_foreach (/usr/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x401b7) #4 0x559a21bf3c27 in object_class_foreach /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:1092:5 #5 0x559a21bf3c27 in object_class_get_list /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:1149:5 #6 0x559a2081a2fd in select_machine /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../softmmu/vl.c:1661:24 #7 0x559a2081a2fd in qemu_create_machine /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../softmmu/vl.c:2146:35 #8 0x559a2081a2fd in qemu_init /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../softmmu/vl.c:3706:5 #9 0x559a20720ed5 in main /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../softmmu/main.c:49:5 #10 0x7f09baec00b2 in __libc_start_main /build/glibc-sMfBJT/glibc-2.31/csu/../csu/libc-start.c:308:16 #11 0x559a2067673d in _start (/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/qemu-system-aarch64+0xf4b73d) 0x61000000ab00 is located 0 bytes to the right of 192-byte region [0x61000000aa40,0x61000000ab00) allocated by thread T0 here: #0 0x559a206eeff2 in calloc (/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/qemu-system-aarch64+0xfc3ff2) #1 0x7f09bcb7bef0 in g_malloc0 (/usr/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x57ef0) #2 0x559a21bf3442 in object_class_foreach_tramp /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:1070:5 Fixes: 00f05c02f9e7342f ("hw/dma/xlnx_csu_dma: Support starting a read transfer through a class method") Signed-off-by: Peter Maydell Reviewed-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 20220308150207.2546272-1-peter.maydell@linaro.org --- hw/dma/xlnx_csu_dma.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c index 84f782fcdc0..60ada3286b4 100644 --- a/hw/dma/xlnx_csu_dma.c +++ b/hw/dma/xlnx_csu_dma.c @@ -744,6 +744,7 @@ static const TypeInfo xlnx_csu_dma_info = { .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(XlnxCSUDMA), .class_init = xlnx_csu_dma_class_init, + .class_size = sizeof(XlnxCSUDMAClass), .instance_init = xlnx_csu_dma_init, .interfaces = (InterfaceInfo[]) { { TYPE_STREAM_SINK }, From patchwork Fri Mar 18 13:22:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 552605 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp2074810mag; Fri, 18 Mar 2022 06:27:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz2PyLF/W8MvQi98PpmsoSj047hudET4B9ztrdGsRt+wNQ8O0IVfTQjUcth9bLhf+2P6PrO X-Received: by 2002:a05:622a:1a12:b0:2e1:a631:aecc with SMTP id f18-20020a05622a1a1200b002e1a631aeccmr7430160qtb.383.1647610068680; Fri, 18 Mar 2022 06:27:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647610068; cv=none; d=google.com; s=arc-20160816; b=LT0DapTay6ycmM6TMVhW1OH2Xyj5bGS90c/Kyd+pYuwKxCsBAkxEUY6NBzyLwp5AFW 31cVJ5jGULdKjzK/lZ0mzrJy99jnH/6QCCF1VYtTWr1FbsBjD+BcUrMt6ZgwyQLLYbYP zzWDgBpgOho7CdkZfKDD+VeiU9HzHE3pTq0KDbpMHTaW3Ybh+NMYHK789furU+2+wqQZ THzxg9IJmjEPnndDE1kDGi0o48be1+YoKxTgpyG1yqWlqHanPmphaILfYJ8eFaT52zLG NsX3mXsknn+mZC3TRwwoER1/UEyoWoYCB4BOZhqkusyeLy5f8fzu7KIQtvci8WcqQKrd hg0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=s6v9sW/5b+lNngegiNeXR9i1AkvUX9wJBIUB91fUBiA=; b=yVkRyuE/eR6i/ETJIn/L6reosZhdyK3EWxcuTrjxT2xz88wJ+t5GgipqGhGlAJPbqu ggonF94WHDEwQ9l0AVNps0kXQiJLzTNR3U5l04ci/y0pfke9S2QXHANsrTiNn92YogtQ pcq2/nNbUmno4sf6bL/WwxnDqoycIxW+RlCvqU340FZonzn3m3V0WaabsoIdnB3liUr2 glZ3RRUheESNmvHiBgvG+T0ZzZjQRWD3+tuWqKcBS2ImN7STdC8gJ5boUCbR3g+3101b rvD7EcV36vXYtcW2+FC98bdGbe8HK9l6kbFyZfCuX2+ON2No6lc9OKJ1/5cjsWW4GS1j GQIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hTrotaJV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y15-20020a05600015cf00b00203e324347bsm6316599wry.102.2022.03.18.06.23.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 06:23:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/21] hw/misc/npcm7xx_clk: Don't leak string in npcm7xx_clk_sel_init() Date: Fri, 18 Mar 2022 13:22:50 +0000 Message-Id: <20220318132306.3254960-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220318132306.3254960-1-peter.maydell@linaro.org> References: <20220318132306.3254960-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32e (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In npcm7xx_clk_sel_init() we allocate a string with g_strdup_printf(). Use g_autofree so we free it rather than leaking it. (Detected with the clang leak sanitizer.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20220308170302.2582820-1-peter.maydell@linaro.org --- hw/misc/npcm7xx_clk.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c index 0b61070c52f..bc2b879feb5 100644 --- a/hw/misc/npcm7xx_clk.c +++ b/hw/misc/npcm7xx_clk.c @@ -612,8 +612,8 @@ static void npcm7xx_clk_sel_init(Object *obj) NPCM7xxClockSELState *sel = NPCM7XX_CLOCK_SEL(obj); for (i = 0; i < NPCM7XX_CLK_SEL_MAX_INPUT; ++i) { - sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel), - g_strdup_printf("clock-in[%d]", i), + g_autofree char *s = g_strdup_printf("clock-in[%d]", i); + sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel), s, npcm7xx_clk_update_sel_cb, sel, ClockUpdate); } sel->clock_out = qdev_init_clock_out(DEVICE(sel), "clock-out"); From patchwork Fri Mar 18 13:22:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 552608 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp2077535mag; Fri, 18 Mar 2022 06:31:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyZmt7TDQrll4gfBy7roNKIyV65nq6aYAg4ZHK++HqYKdo9axdX3B12EnsF4w+0molo4pJw X-Received: by 2002:ac8:5dd2:0:b0:2e0:688f:ba8f with SMTP id e18-20020ac85dd2000000b002e0688fba8fmr7271965qtx.139.1647610269834; Fri, 18 Mar 2022 06:31:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647610269; cv=none; d=google.com; s=arc-20160816; b=AESPimNrtiifcbmd0HIk+caigHplTm7HXvi0hOaNRNa8XCjcXquuxuSMoNHTebzo2U K3aBnZph19Y5nTy8bW3hh0Bm2IUqXNJnJ8xNZRbgG+6YzRCE4NDXjPW6U2vO0oLuoDOs M5ocvSM+W5v038vWx47DvFiCwCMQFkHDpvIlgXWYzpNBTeLDrPjiesk5rtoJcipiwcsB peEJqABKTlaoMHBpxmGPMg1MaB/xSx/SZ5m1wlWZ33HuiP6geWtE9sHQ6tNq/TMaPGe6 hJrqBFre1igaiG4ODMA6PmdrAyIIjRPwCrsn0ujeHCrrXMzE0YjuxK020e39J2G1I53n Mvxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DEWExO7QLDaNCo9Eg6pGlE4QUxy0uT2YlPbVNfGUVoE=; b=yVKDoxaZ1PRrilVkCIannUVlUG7weUNk1wG2J5WTF9ovW1wUFBxGyQZMWt41wPXiPd qHKPzloR252YmAKmESUKbuHoLnvYm1yZNxEDbDI5kwlNZvi0R7gB9P6CFG6keAe107/M BMzWASXHDcfDxSwv9JJp7iOFik457KqxWqh57dM0Od+zDlg5TyMSNeftWpOw8L+qt7yz ddEoz3xD+JOM0wKLb0zRAmhvPrWQbVjs46Zo8lJAkrbFbrfu91TOR7XMqXtuF06PoeFV VJZA33rh/eZg2zg6exz1h1jXxBjSDoUuI3VgGCygdOHHX8LNZhOWzFMCtI50GGMCk+Pk irOQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=f60ua8If; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y15-20020a05600015cf00b00203e324347bsm6316599wry.102.2022.03.18.06.23.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 06:23:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/21] nsis installer: List emulators in alphabetical order Date: Fri, 18 Mar 2022 13:22:51 +0000 Message-Id: <20220318132306.3254960-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220318132306.3254960-1-peter.maydell@linaro.org> References: <20220318132306.3254960-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32e (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We currently list the emulators in the Windows installer's dialog in an essentially random order (it's whatever glob.glob() returns them to, which is filesystem-implementation-dependent). Add a call to sorted() so they appear in alphabetical order. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Stefan Weil Reviewed-by: John Snow Message-id: 20220305105743.2384766-2-peter.maydell@linaro.org --- scripts/nsis.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/scripts/nsis.py b/scripts/nsis.py index 5135a058316..383bef70332 100644 --- a/scripts/nsis.py +++ b/scripts/nsis.py @@ -34,9 +34,9 @@ def main(): with open( os.path.join(destdir + args.prefix, "system-emulations.nsh"), "w" ) as nsh: - for exe in glob.glob( + for exe in sorted(glob.glob( os.path.join(destdir + args.prefix, "qemu-system-*.exe") - ): + )): exe = os.path.basename(exe) arch = exe[12:-4] nsh.write( From patchwork Fri Mar 18 13:22:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 552603 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp2074545mag; Fri, 18 Mar 2022 06:27:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx318X//NRr6q+M4/rkx3MiT5mVeC4iAJj60YShEdDdw4HZ1nX0TvjKdVzfT7usXceffYgc X-Received: by 2002:a05:6214:2a4f:b0:440:eb44:fef5 with SMTP id jf15-20020a0562142a4f00b00440eb44fef5mr5144913qvb.81.1647610044634; Fri, 18 Mar 2022 06:27:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647610044; cv=none; d=google.com; s=arc-20160816; b=1CsvyrnuVQQgXChKQYCkau+TzQloaW0aD1NvoaKKa5je5SJPSFEZwElSJtFo91fYp9 Pi8imWe6pj7TZNCXuCRIt1HHAirdmog21IPGbQLvp1kOR/swHLi9ZQztTL7/JdJidJcJ qea7bOPfNWwYHJAPa3kQQYHu/HrpOPNabwkw0JSKBeq/IeH9Dcioyx2Y/fPceUlzUuGF dm/Zo0a/JUrzC1UveuutiuHfW9CcSnMGBfy4E33sMq3OVHvTGJ/5HP9VYRrDVHyGmt6M eD4tOyqj0hJzfEaSLhfZn+7zvXfpf1PzxBkontje03SK/yxTgSct6RkdnUAS8bEHnPxn 2oyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=e2Ca19v+BtrvPQ188u+XK9x8duUflsMT25zrs87XFmk=; b=OPDf/GuefNUu/8AlIYGYMdY20K3OYeOWO6eOjYLiLQrmqa7Jo3aexgSrOWi1+Xev2g Vk75s3INZaUxGq/4BnH4SqUNmXpQDJG9rOqwxm4Y3spXJ4titePD2kPU7+uz6k6ucJGF S/xk7Kj7U9p3HMP+UQqmtCilb0hGPag0608Xzt+DegTNNp2TkaoIcYh+R+zu/uM6K1UD mJYX4ZXLgVHXdd7HO8JFym8FwOojnMnU0XI3gWETZvKO2u502GdwHZdxHQ5WO/ylhUQq Q8+Qv12b0JIeZ/wfGVQJZG08UhR6io9P+MUyMH7ZUeul4FKVI19ro5rcW3+jWuEwkR7p 8jMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ANIuJ6mU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y15-20020a05600015cf00b00203e324347bsm6316599wry.102.2022.03.18.06.23.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 06:23:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/21] nsis installer: Suppress "ANSI targets are deprecated" warning Date: Fri, 18 Mar 2022 13:22:52 +0000 Message-Id: <20220318132306.3254960-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220318132306.3254960-1-peter.maydell@linaro.org> References: <20220318132306.3254960-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42d (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When we build our Windows installer, it emits the warning: warning 7998: ANSI targets are deprecated Fix this by making our installer a Unicode installer instead. These won't work on Win95/98/ME, but we already do not support those. See https://nsis.sourceforge.io/Docs/Chapter4.html#aunicodetarget for the documentation of the Unicode directive. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Stefan Weil Message-id: 20220305105743.2384766-3-peter.maydell@linaro.org --- qemu.nsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qemu.nsi b/qemu.nsi index c3df8c9d3b0..6edd82b385d 100644 --- a/qemu.nsi +++ b/qemu.nsi @@ -35,6 +35,9 @@ !define OUTFILE "qemu-setup.exe" !endif +; Build a unicode installer +Unicode true + ; Use maximum compression. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y15-20020a05600015cf00b00203e324347bsm6316599wry.102.2022.03.18.06.23.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 06:23:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/21] nsis installer: Fix mouse-over descriptions for emulators Date: Fri, 18 Mar 2022 13:22:53 +0000 Message-Id: <20220318132306.3254960-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220318132306.3254960-1-peter.maydell@linaro.org> References: <20220318132306.3254960-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42c (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We use the nsis.py script to write out an installer script Section for each emulator executable, so the exact set of Sections depends on which executables were built. However the part of qemu.nsi which specifies mouse-over descriptions for each Section still has a hard-coded and very outdated list (with just i386 and alpha). This causes two problems. Firstly, if you build the installer for a configuration where you didn't build the i386 binaries you get warnings like this: warning 6000: unknown variable/constant "{Section_i386}" detected, ignoring (macro:_==:1) warning 6000: unknown variable/constant "{Section_i386w}" detected, ignoring (macro:_==:1) (this happens in our gitlab CI jobs, for instance). Secondly, most of the emulators in the generated installer don't have any mouseover text. Make nsis.py generate a second output file which has the necessary MUI_DESCRIPTION_TEXT lines for each Section it creates, so we can include that at the right point in qemu.nsi to set the mouse-over text. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: John Snow Message-id: 20220305105743.2384766-4-peter.maydell@linaro.org --- qemu.nsi | 5 +---- scripts/nsis.py | 13 ++++++++++++- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/qemu.nsi b/qemu.nsi index 6edd82b385d..564d617d11f 100644 --- a/qemu.nsi +++ b/qemu.nsi @@ -228,10 +228,7 @@ SectionEnd ; Descriptions (mouse-over). !insertmacro MUI_FUNCTION_DESCRIPTION_BEGIN !insertmacro MUI_DESCRIPTION_TEXT ${SectionSystem} "System emulation." - !insertmacro MUI_DESCRIPTION_TEXT ${Section_alpha} "Alpha system emulation." - !insertmacro MUI_DESCRIPTION_TEXT ${Section_alphaw} "Alpha system emulation (GUI)." - !insertmacro MUI_DESCRIPTION_TEXT ${Section_i386} "PC i386 system emulation." - !insertmacro MUI_DESCRIPTION_TEXT ${Section_i386w} "PC i386 system emulation (GUI)." +!include "${BINDIR}\system-mui-text.nsh" !insertmacro MUI_DESCRIPTION_TEXT ${SectionTools} "Tools." !ifdef DLLDIR !insertmacro MUI_DESCRIPTION_TEXT ${SectionDll} "Runtime Libraries (DLL)." diff --git a/scripts/nsis.py b/scripts/nsis.py index 383bef70332..462d6cac3b6 100644 --- a/scripts/nsis.py +++ b/scripts/nsis.py @@ -33,7 +33,9 @@ def main(): subprocess.run(["make", "install", "DESTDIR=" + destdir + os.path.sep]) with open( os.path.join(destdir + args.prefix, "system-emulations.nsh"), "w" - ) as nsh: + ) as nsh, open( + os.path.join(destdir + args.prefix, "system-mui-text.nsh"), "w" + ) as muinsh: for exe in sorted(glob.glob( os.path.join(destdir + args.prefix, "qemu-system-*.exe") )): @@ -49,6 +51,15 @@ def main(): arch, exe ) ) + if arch.endswith('w'): + desc = arch[:-1] + " emulation (GUI)." + else: + desc = arch + " emulation." + + muinsh.write( + """ + !insertmacro MUI_DESCRIPTION_TEXT ${{Section_{0}}} "{1}" + """.format(arch, desc)) for exe in glob.glob(os.path.join(destdir + args.prefix, "*.exe")): signcode(exe) From patchwork Fri Mar 18 13:22:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 552606 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp2077419mag; Fri, 18 Mar 2022 06:31:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw3N02HO1p4dZT9ZhEQriYytTEH9oB0i28hFynCoyWpoRI9ymJn8XW+tyHPB0XD0VM+K34q X-Received: by 2002:a05:6214:e4c:b0:440:de46:f156 with SMTP id o12-20020a0562140e4c00b00440de46f156mr6965559qvc.29.1647610262068; Fri, 18 Mar 2022 06:31:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647610262; cv=none; d=google.com; s=arc-20160816; b=tJPkFF8DVSXkLXE8O2Tq//OvCKglA5lX4SyULYjCANQUU3cUa2dtb9WdAw11+YIFu9 eko5vgUhlmZWRZ43dnkEmNHfcJK1pi84F5iCf1WeKrwiFJqEsReiyHr/1+hJpp3Yu8Rh OC9DNGdEKMwVvc/SMU0EG6iythzw5RGWl4K/vRJwtpljaJxHTskNx2EXF6uSaJr6zjOZ 8s/OiBayl3fJ2z09rkkadtuG1xPFU82NVBT6JibfFtVaw59zY/PdJGqWJVcGKAg6V+Cd Lg/J8gfS0qvBFrWzOlVTeZPoBicsm9/ujSyaJrH/S6uE5crZWHPovQFWXZIb+c0uuMPY rH9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rAR5UrC/EDjfSgwvecxgN1md0yBcDrI2n/IH7Cc540Y=; b=zFY1CyT27fbxud5a2bu5JLexIv8LuHL6LO++pULg5UY0ZK7UJNtcvAFZKZ36QZ3xms uE+KvhyHBBYRV4/56wPvEU7CeB5sp29fOEas+do07pc6mXuH8Rl7VDMY5TDN9zpHici2 KvLgc6WoEE6a/hDydxTX9wv1eQAoZnnpkBc9yUo7TDLw5a/JMM4TO0t0LTHsh7LyQCsc 3XEvXCyzQO0nizuHqtm8AkiPgFXhlPfgA6zjhQhQtGxw61j5gov2RyqRYIdEKk6HXkY/ 6jYPLi65cv8KOGEMwNU2sF/luPMuhcIpQ5IZCBhPSlW7GxMxJRK6cXlkXfeHcplGbeiK 8OHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=o1uw5syH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y15-20020a05600015cf00b00203e324347bsm6316599wry.102.2022.03.18.06.23.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 06:23:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/21] hw/intc: Rename CONFIG_ARM_GIC_TCG into CONFIG_ARM_GICV3_TCG Date: Fri, 18 Mar 2022 13:22:54 +0000 Message-Id: <20220318132306.3254960-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220318132306.3254960-1-peter.maydell@linaro.org> References: <20220318132306.3254960-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::431 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Eric Auger CONFIG_ARM_GIC_TCG actually guards the compilation of TCG GICv3 specific files. So let's rename it into CONFIG_ARM_GICV3_TCG Signed-off-by: Eric Auger Reviewed-by: Andrew Jones Message-id: 20220308182452.223473-2-eric.auger@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/Kconfig | 2 +- hw/intc/meson.build | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index ec8d4cec297..a7cf301eab2 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -25,7 +25,7 @@ config APIC select MSI_NONBROKEN select I8259 -config ARM_GIC_TCG +config ARM_GICV3_TCG bool default y depends on ARM_GIC && TCG diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 81ccdb0d78c..d6d012fb264 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -6,7 +6,7 @@ softmmu_ss.add(when: 'CONFIG_ARM_GIC', if_true: files( 'arm_gicv3_common.c', 'arm_gicv3_its_common.c', )) -softmmu_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files( +softmmu_ss.add(when: 'CONFIG_ARM_GICV3_TCG', if_true: files( 'arm_gicv3.c', 'arm_gicv3_dist.c', 'arm_gicv3_its.c', @@ -28,7 +28,7 @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-in specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c')) specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c')) specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c')) -specific_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files('arm_gicv3_cpuif.c')) +specific_ss.add(when: 'CONFIG_ARM_GICV3_TCG', if_true: files('arm_gicv3_cpuif.c')) specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c')) specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c')) From patchwork Fri Mar 18 13:22:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 552610 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp2080026mag; Fri, 18 Mar 2022 06:34:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxM8PRZxW5509RRmIpxZVP6xl0+M6jlWAP02fM2Gm//bNy+h4B4ABV5aRFAnJ/34RdgK5ZG X-Received: by 2002:ac8:7f42:0:b0:2e1:fd5f:742e with SMTP id g2-20020ac87f42000000b002e1fd5f742emr4493081qtk.123.1647610466798; Fri, 18 Mar 2022 06:34:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647610466; cv=none; d=google.com; s=arc-20160816; b=SbWLTrkgyPu7SMlKwA9Vrqqs15kCBcEuzTmw42JhOsYxkvTor5BIIiWILJet3iVDkm unv/KcnCm2khcmkn3tLRD2EqAO4pWYw7ZsGMmsYEW5yS1zVdBv1nPsx2Mld+8FhFHiEq /nu7F1E17RWqZhLiNpgoBcL4YcwFxtuQH7R1liNukAMZ+BuFWatHW1Qm9HMVBowbpJB+ fx8/CmjE9vDoXciRkzkWGnit0RY04R/tUd+HBDusEySp9DIKw0lyGXjrc1lSqXg0917Y tyKnUNbMbSV/Tt+krBSriOt6mNaWXcvptoRIiZx62j2EW+Ayj6JacZO2MvPDuBNfHD4k o2YQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=w+JI1qq6cdVD2iag3w2GaYZANAYR6mX3L0DIG064z08=; b=su2ELQxmnlJomC/DOMjMk2xyvJH2JcejRatKAH5+wn6KGiRP92Ehjk6TVcC3Hhg+4f KBu+l6Tnd040jyLPxTImnLEgh4/hoWJKKS0I4JbM871gRCjhWv4t3K7Qv6DFtzfXUQhy +OliGVznptY3Hzcsn7wBk71X3dxSvfms4JwbssHcta2I0kVKB2C8Yf9BbDa9ZayVe9m+ 3903zr/k40rHP0Ey41ZJsCDQpw90kDCKuLSEQN1bWaSxSr5jJQwwfztruGBFfjdod8go 0LUShHhZjGTSwPEiQ4rg+tvNPOwDwCal1JNs08khlRsEiBUcrDFVj6pzu/BcyEp+hK63 Ic4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oiGoivpK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y15-20020a05600015cf00b00203e324347bsm6316599wry.102.2022.03.18.06.23.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 06:23:19 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/21] hw/arm/virt: Fix gic-version=max when CONFIG_ARM_GICV3_TCG is unset Date: Fri, 18 Mar 2022 13:22:55 +0000 Message-Id: <20220318132306.3254960-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220318132306.3254960-1-peter.maydell@linaro.org> References: <20220318132306.3254960-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42e (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Eric Auger In TCG mode, if gic-version=max we always select GICv3 even if CONFIG_ARM_GICV3_TCG is unset. We shall rather select GICv2. This also brings the benefit of fixing qos tests errors for tests using gic-version=max with CONFIG_ARM_GICV3_TCG unset. Signed-off-by: Eric Auger Reviewed-by: Andrew Jones Message-id: 20220308182452.223473-3-eric.auger@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/virt.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 46a42502bc5..d2e5ecd234a 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1852,7 +1852,12 @@ static void finalize_gic_version(VirtMachineState *vms) vms->gic_version = VIRT_GIC_VERSION_2; break; case VIRT_GIC_VERSION_MAX: - vms->gic_version = VIRT_GIC_VERSION_3; + if (module_object_class_by_name("arm-gicv3")) { + /* CONFIG_ARM_GICV3_TCG was set */ + vms->gic_version = VIRT_GIC_VERSION_3; + } else { + vms->gic_version = VIRT_GIC_VERSION_2; + } break; case VIRT_GIC_VERSION_HOST: error_report("gic-version=host requires KVM"); From patchwork Fri Mar 18 13:22:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 552607 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp2077506mag; Fri, 18 Mar 2022 06:31:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy3C8ZSdsy0/z/sOHVx8CbNcFmK0dpkXtn0/LQWKQ3xaX16dWCKdyc4t8RjZ1BG/vkSAcjm X-Received: by 2002:ad4:5743:0:b0:435:9b32:a6b0 with SMTP id q3-20020ad45743000000b004359b32a6b0mr7036849qvx.122.1647610267832; Fri, 18 Mar 2022 06:31:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647610267; cv=none; d=google.com; s=arc-20160816; b=N+7JsYZjmIiFEqLfZNMOLhuN4axzW6KHUYDQdYChVKsuV2hAYv0TihQErbDZQb6MyV yt7bDKB3dt6Xm/Zs26vYv+8Mx+LxrVTSb7z6gURWsFyvbKQWUk/8toDBDb/vavUpwTYr gWifky2X1yiogaxpvHv3UJ6Sb1eUzOVS2VmfPm2WlIR4gVr5NupR9KhG+SOIv7Be+84g LsNgAm/LfBtIygNXcXmd6okRnZad5plWcPkBdXlRbKnL11p/YF7d7nXOVk9BhnVtuJJA 4gopmp52qV6KHZO1rim4ppTPH/tlYrnyoepCuON6kCYXqBF+FkOi+n11Cd8zcw65Vczr wbpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=F5b5cXpmQL4zvEgjGCRXLiRUXPPFUSGLdiVG1e343YA=; b=TzlPYYEolSWysBKaECqiJTX70uVIkliwXPhe3PGtTGot1PF8LtO55UTgiSk2XMCf8I FCVz9GOdUtaVWxWLyARHc3HncanORk4BEGzqCm9+zul7HuSpyRMKiHen1b3QKuTTV6nn z4glmHSx9bps/j/ChMy2p/8qLBc/fgHWHUYeExsvPrEMJj6ixeBE9IbZsltb2TNxjKLQ p2VfIl2elmq9mSkbVzGJ6GTXCSUa2mLC9W9NJnSWhMnzM3j9vY/+T18f0rKt2Loa2dsN Firb5uuiS9HRJtSgg6ukvJBqc1f0r/sU59e2oYoXLX4htpXb7vaO7LZQfnD0TjGsWdBg fAaQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YA9YH96z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y15-20020a05600015cf00b00203e324347bsm6316599wry.102.2022.03.18.06.23.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 06:23:20 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/21] target/arm: Log M-profile vector table accesses Date: Fri, 18 Mar 2022 13:22:56 +0000 Message-Id: <20220318132306.3254960-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220318132306.3254960-1-peter.maydell@linaro.org> References: <20220318132306.3254960-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::432 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Currently the CPU_LOG_INT logging misses some useful information about loads from the vector table. Add logging where we load vector table entries. This is particularly helpful for cases where the user has accidentally not put a vector table in their image at all, which can result in confusing guest crashes at startup. Here's an example of the new logging for a case where the vector table contains garbage: Loaded reset SP 0x0 PC 0x0 from vector table Loaded reset SP 0xd008f8df PC 0xf000bf00 from vector table Taking exception 3 [Prefetch Abort] on CPU 0 ...with CFSR.IACCVIOL ...BusFault with BFSR.STKERR ...taking pending nonsecure exception 3 ...loading from element 3 of non-secure vector table at 0xc ...loaded new PC 0x20000558 ---------------- IN: 0x20000558: 08000079 stmdaeq r0, {r0, r3, r4, r5, r6} (The double reset logging is the result of our long-standing "CPUs all get reset twice" weirdness; it looks a bit ugly but it'll go away if we ever fix that :-)) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Message-id: 20220315204306.2797684-2-peter.maydell@linaro.org --- target/arm/cpu.c | 5 +++++ target/arm/m_helper.c | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 185d4e774d5..498fb9f71b3 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "qemu/qemu-print.h" #include "qemu/timer.h" +#include "qemu/log.h" #include "qemu-common.h" #include "target/arm/idau.h" #include "qemu/module.h" @@ -366,6 +367,10 @@ static void arm_cpu_reset(DeviceState *dev) initial_pc = ldl_phys(s->as, vecbase + 4); } + qemu_log_mask(CPU_LOG_INT, + "Loaded reset SP 0x%x PC 0x%x from vector table\n", + initial_msp, initial_pc); + env->regs[13] = initial_msp & 0xFFFFFFFC; env->regs[15] = initial_pc & ~1; env->thumb = initial_pc & 1; diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 648a3b3fc16..3bd16c0c465 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -679,6 +679,10 @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure, ARMMMUIdx mmu_idx; bool exc_secure; + qemu_log_mask(CPU_LOG_INT, + "...loading from element %d of %s vector table at 0x%x\n", + exc, targets_secure ? "secure" : "non-secure", addr); + mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, targets_secure, true); /* @@ -719,6 +723,7 @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure, goto load_fail; } *pvec = vector_entry; + qemu_log_mask(CPU_LOG_INT, "...loaded new PC 0x%x\n", *pvec); return true; load_fail: From patchwork Fri Mar 18 13:22:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 552614 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp2082067mag; Fri, 18 Mar 2022 06:37:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwY5peidFbVE8AayFqmqGoopuIAaAhUEU6Ug7GRa4/XhZjqbGvqYsjsp6wh8ZaO0kl+YgB8 X-Received: by 2002:a05:620a:4083:b0:67d:a6e3:523c with SMTP id f3-20020a05620a408300b0067da6e3523cmr5874559qko.601.1647610648715; Fri, 18 Mar 2022 06:37:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647610648; cv=none; d=google.com; s=arc-20160816; b=wVby/hMo9hvnoSRgJ9nxgh8+B7O5ZUIESmNDuCKoKhg6LTgxxsXzPTf0BnVJR3bXxb /0BlmV+8Z220BdOD4s7P4ETPOtH4x5jH6do67MG0O7itSlmlEyUHT2uJZd7M4DGGm2/+ v03FE7F7+5/szo2NB1IdLDoT/9ZYMP/jvSp7Aw5tMkuxrVZqeA7FSZwo0IR4AaosBL83 mHSc1XtAaXupVNisiFWDenSHqiQDYxrFFIqCSYffRhs6jplELu3Zxvne9/RvnhPSm/by C60i5Bpd8C11QppVqkhGCtHiBb+rEnO5WY8nN+69O1/wGuzczMter/vYM8IZsRdSOHls xC7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=BdSqB/hxDC2NJFyRoZAEcCAYDQy1ee8PfJktNbNz4sU=; b=ureFqC8JsrVo2C5J/RFQWlFTHd3BMAe6j+Fp8TnJrLYvF4C6LB1reFeCqba4NyhsjJ tVQMdS/uHZRbhpfMcDp83qtUM7TJ+SxXF7NzO/ZtItFMzq+jUt3Oi1edh8o2TQucqzix KRlzfw6piTY3/3u6f5wI30D88KbIzQCiUkq60WOHmqRTCeEliu9smmYfT9DIW/SV/67Q PH8WyLmmjb8ivDCbvbe5DO0E8s6IICJOE5QsD5GfOlg/Ri6Cg6SznPhyNDEC2UjZi3+H lVfglfNwIIQVeWMtGwfFEcjiBGWxDWGyQ3r/9rBndcQgRQBTcoGtOK+PxJMz+gonK0cu aHLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xMbYwIsK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y15-20020a05600015cf00b00203e324347bsm6316599wry.102.2022.03.18.06.23.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 06:23:21 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/21] target/arm: Log fault address for M-profile faults Date: Fri, 18 Mar 2022 13:22:57 +0000 Message-Id: <20220318132306.3254960-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220318132306.3254960-1-peter.maydell@linaro.org> References: <20220318132306.3254960-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::433 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For M-profile, the fault address is not always exposed to the guest in a fault register (for instance the BFAR bus fault address register is only updated for bus faults on data accesses, not instruction accesses). Currently we log the address only if we're putting it into a particular guest-visible register. Since we always have it, log it generically, to make logs of i-side faults a bit clearer. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Message-id: 20220315204306.2797684-3-peter.maydell@linaro.org --- target/arm/m_helper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 3bd16c0c465..b7a0fe01141 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -2272,7 +2272,13 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) * Note that for M profile we don't have a guest facing FSR, but * the env->exception.fsr will be populated by the code that * raises the fault, in the A profile short-descriptor format. + * + * Log the exception.vaddress now regardless of subtype, because + * logging below only logs it when it goes into a guest visible + * register. */ + qemu_log_mask(CPU_LOG_INT, "...at fault address 0x%x\n", + (uint32_t)env->exception.vaddress); switch (env->exception.fsr & 0xf) { case M_FAKE_FSR_NSC_EXEC: /* From patchwork Fri Mar 18 13:22:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 552609 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp2078805mag; Fri, 18 Mar 2022 06:32:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxXzEtXImw1BgulrL4Z+1w1PzQKI4VhSeM6cMUuxECZa+RVZSHYmOgHiW9PKAGhivBNB84f X-Received: by 2002:a0c:c404:0:b0:431:31c3:3d15 with SMTP id r4-20020a0cc404000000b0043131c33d15mr7108761qvi.116.1647610364515; Fri, 18 Mar 2022 06:32:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647610364; cv=none; d=google.com; s=arc-20160816; b=qLSYy+8lcOVDPJxv+cUXNBfT/1lMBmdm0xlrg45vKsXE77XZvDSEZVIVsQqO9FlrXq 7KLDf45xZEsK6teoEURUCvHKr1HfJW6UVIqCushohAxUM4eknYTqo7J80uQF88wxAMNX likWuNH7/ruEkI6tXJz9TxowMKcfVZbY2gElV9bOte27jRMqSism+ZNcvQkr7TebMNMn 5FM/7GeUkUGeHASvWcq9/nYUpnv03InboZcEQRPh2IgRaRmE7X8/ZAme4STznDpYqiEP 8nwrqPTZfSHsfKuEXas/UYmLCCbcyCJLjV+0WeUQKahtu0MDLHYokS+Sfe1VBtFXPSAD rmpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=skh7ZtJM7j+brlaef0ORPlmyZxfZeY2D1B+dwRbY6ME=; b=Bfw5+gKFsFjlETPXZGd4kklqB+Q2g9m3Hd/vyM3BrPHwl1I7yICIFBZXNscHRmTYQ1 V2VOYSrojNropLRfvo9euqX2RmDVhXy3u0+80FuiL/SzuEgtVG9uMoIDoVaPtOwNMQ22 dGQOVoXAS0Ah9nBZMX1Nbyp9WXWdwviR+pLoRCXEYkzRGqf5Kz326TSR19U+25KPha9p yywmG758mYCcoAi2ABKp+tqOahI841pKijLSEs6bsTJcrwZQy41d/fW47029O2hicsZ3 psarNE789n7iOXJJBTDhHboJgvMn8ntNc3VYTCWHSoktKpwzkmOrBwOtzIZAVRE/pMzU E8LA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="l/gtrMwX"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y15-20020a05600015cf00b00203e324347bsm6316599wry.102.2022.03.18.06.23.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 06:23:22 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/21] hw/arm/xlnx-zynqmp: Add an unimplemented SERDES area Date: Fri, 18 Mar 2022 13:22:58 +0000 Message-Id: <20220318132306.3254960-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220318132306.3254960-1-peter.maydell@linaro.org> References: <20220318132306.3254960-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::336 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Add an unimplemented SERDES (Serializer/Deserializer) area. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Francisco Iglesias Signed-off-by: Edgar E. Iglesias Message-id: 20220316164645.2303510-2-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-zynqmp.h | 2 +- hw/arm/xlnx-zynqmp.c | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 9424f81c377..0552ba18b41 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -85,7 +85,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) /* * Unimplemented mmio regions needed to boot some images. */ -#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 1 +#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 2 struct XlnxZynqMPState { /*< private >*/ diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 6d0e4116db7..47324cdc441 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -52,6 +52,10 @@ #define QSPI_DMA_ADDR 0xff0f0800 #define NUM_QSPI_IRQ_LINES 2 +/* Serializer/Deserializer. */ +#define SERDES_ADDR 0xfd400000 +#define SERDES_SIZE 0x20000 + #define DP_ADDR 0xfd4a0000 #define DP_IRQ 113 @@ -284,6 +288,7 @@ static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s) hwaddr size; } unimp_areas[ARRAY_SIZE(s->mr_unimp)] = { { .name = "apu", APU_ADDR, APU_SIZE }, + { .name = "serdes", SERDES_ADDR, SERDES_SIZE }, }; unsigned int nr; From patchwork Fri Mar 18 13:22:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 552612 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp2080124mag; Fri, 18 Mar 2022 06:34:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw5dm2Y4zbkFGue0W9xpbu66F5Q1zyqUzJAHyrfIneztMjRVg7QAQBP8ounwoW8GE9zD6FL X-Received: by 2002:a37:3d5:0:b0:67b:335d:59c3 with SMTP id 204-20020a3703d5000000b0067b335d59c3mr5640428qkd.739.1647610474635; Fri, 18 Mar 2022 06:34:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647610474; cv=none; d=google.com; s=arc-20160816; b=u+infRn/myOwBEU2kYUI8LrrpbUMvf7DXBEP5HVgO+nMUG6/VQRPr8jdH7ReJgFmM9 qiuNY3TvSgJKrbdnqyNBFD4OSnh7siGDABQ6SUaV36AuiHGeoQcBvBCJH4siJs+sKHLF t55eS6OZ2ApjRcied5p4lY0IWuXNPFNv3SUTQWCKpQ0WxLTNeLDNK12n8+Zh1viBGjKC Sw0ki1D7ATFnkLCYx3q0/YZx2HfIhKckKmRZBVWuyaIxsOY86mXYjXIO15T+vMNw6q3C JGCIoLpT0HWAlPiP1YRSjq9g8EgMwtRHw9k3Y/fh1vooTF0MP4bkZS3KQkChC0VLhDSd NeBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=zbF++87+DFHxQnZv6iADOqjq+cHo8qKgkOCe675Yq1U=; b=p3lpYfLIqZsV7WQVq1Q1IOW13WZfAOmcQnm/EmE7wdxMpMDoIeimSoQCs+3cqH3gVN Me4A4zPabfY4ooCVIDdg8tlIFlKik8qeqYIxYUISPMO2pQEyw6LaqWBhDYuQiRi28bfl aDVeAWU+WKpow0FqqZcOapuWS5BrM4CzhDIbq/x8niL6YX2X7ZH1Jbr8UtAUCTjEBHdG eeS5k1B/ZcRH84Ka6yCwcINrvIRN4xCVqa1QbsrHflANFO9elJMfDE5XTFvAwDtfxUoS F5HEffTGVMHyK6rKYCJwlk/lATt+T1uq5E+Dt0x/+rJnPfUydSuTDs8Yd1Tyj2gQsduV Kw8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=n8goMrk5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y15-20020a05600015cf00b00203e324347bsm6316599wry.102.2022.03.18.06.23.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 06:23:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/21] target/arm: Make rvbar settable after realize Date: Fri, 18 Mar 2022 13:22:59 +0000 Message-Id: <20220318132306.3254960-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220318132306.3254960-1-peter.maydell@linaro.org> References: <20220318132306.3254960-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::332 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Make the rvbar property settable after realize. This is done in preparation to model the ZynqMP's runtime configurable rvbar. Signed-off-by: Edgar E. Iglesias Message-id: 20220316164645.2303510-3-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 3 ++- target/arm/cpu.c | 12 +++++++----- target/arm/helper.c | 10 +++++++--- 3 files changed, 16 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 157f214cce1..23879de5fa7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -447,6 +447,7 @@ typedef struct CPUArchState { uint64_t vbar_el[4]; }; uint32_t mvbar; /* (monitor) vector base address register */ + uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ struct { /* FCSE PID. */ uint32_t fcseidr_ns; uint32_t fcseidr_s; @@ -985,7 +986,7 @@ struct ArchCPU { /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ uint32_t dcz_blocksize; - uint64_t rvbar; + uint64_t rvbar_prop; /* Property/input signals. */ /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ int gic_num_lrs; /* number of list registers */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 498fb9f71b3..5d4ca7a2270 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -236,7 +236,10 @@ static void arm_cpu_reset(DeviceState *dev) } else { env->pstate = PSTATE_MODE_EL1h; } - env->pc = cpu->rvbar; + + /* Sample rvbar at reset. */ + env->cp15.rvbar = cpu->rvbar_prop; + env->pc = env->cp15.rvbar; #endif } else { #if defined(CONFIG_USER_ONLY) @@ -1135,9 +1138,6 @@ static Property arm_cpu_reset_cbar_property = static Property arm_cpu_reset_hivecs_property = DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); -static Property arm_cpu_rvbar_property = - DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); - #ifndef CONFIG_USER_ONLY static Property arm_cpu_has_el2_property = DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); @@ -1240,7 +1240,9 @@ void arm_cpu_post_init(Object *obj) } if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property); + object_property_add_uint64_ptr(obj, "rvbar", + &cpu->rvbar_prop, + OBJ_PROP_FLAG_READWRITE); } #ifndef CONFIG_USER_ONLY diff --git a/target/arm/helper.c b/target/arm/helper.c index b5c8caafe84..812ca591f4e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7967,7 +7967,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo rvbar = { .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, - .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar + .access = PL1_R, + .fieldoffset = offsetof(CPUARMState, cp15.rvbar), }; define_one_arm_cp_reg(cpu, &rvbar); } @@ -8011,7 +8012,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo rvbar = { .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, - .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar + .access = PL2_R, + .fieldoffset = offsetof(CPUARMState, cp15.rvbar), }; define_one_arm_cp_reg(cpu, &rvbar); } @@ -8048,7 +8050,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo el3_regs[] = { { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1, - .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar }, + .access = PL3_R, + .fieldoffset = offsetof(CPUARMState, cp15.rvbar), + }, { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, .access = PL3_RW, From patchwork Fri Mar 18 13:23:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 552615 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp2082105mag; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y15-20020a05600015cf00b00203e324347bsm6316599wry.102.2022.03.18.06.23.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 06:23:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/21] hw/misc: Add a model of the Xilinx ZynqMP CRF Date: Fri, 18 Mar 2022 13:23:00 +0000 Message-Id: <20220318132306.3254960-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220318132306.3254960-1-peter.maydell@linaro.org> References: <20220318132306.3254960-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32a (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Add a model of the Xilinx ZynqMP CRF. At the moment this is mostly a stub model. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Edgar E. Iglesias Message-id: 20220316164645.2303510-4-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- include/hw/misc/xlnx-zynqmp-crf.h | 211 ++++++++++++++++++++++++ hw/misc/xlnx-zynqmp-crf.c | 266 ++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + 3 files changed, 478 insertions(+) create mode 100644 include/hw/misc/xlnx-zynqmp-crf.h create mode 100644 hw/misc/xlnx-zynqmp-crf.c diff --git a/include/hw/misc/xlnx-zynqmp-crf.h b/include/hw/misc/xlnx-zynqmp-crf.h new file mode 100644 index 00000000000..02ef0bdeeee --- /dev/null +++ b/include/hw/misc/xlnx-zynqmp-crf.h @@ -0,0 +1,211 @@ +/* + * QEMU model of the CRF - Clock Reset FPD. + * + * Copyright (c) 2022 Xilinx Inc. + * SPDX-License-Identifier: GPL-2.0-or-later + * Written by Edgar E. Iglesias + */ +#ifndef HW_MISC_XLNX_ZYNQMP_CRF_H +#define HW_MISC_XLNX_ZYNQMP_CRF_H + +#include "hw/sysbus.h" +#include "hw/register.h" + +#define TYPE_XLNX_ZYNQMP_CRF "xlnx.zynqmp_crf" +OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPCRF, XLNX_ZYNQMP_CRF) + +REG32(ERR_CTRL, 0x0) + FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1) +REG32(IR_STATUS, 0x4) + FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1) +REG32(IR_MASK, 0x8) + FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1) +REG32(IR_ENABLE, 0xc) + FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1) +REG32(IR_DISABLE, 0x10) + FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1) +REG32(CRF_WPROT, 0x1c) + FIELD(CRF_WPROT, ACTIVE, 0, 1) +REG32(APLL_CTRL, 0x20) + FIELD(APLL_CTRL, POST_SRC, 24, 3) + FIELD(APLL_CTRL, PRE_SRC, 20, 3) + FIELD(APLL_CTRL, CLKOUTDIV, 17, 1) + FIELD(APLL_CTRL, DIV2, 16, 1) + FIELD(APLL_CTRL, FBDIV, 8, 7) + FIELD(APLL_CTRL, BYPASS, 3, 1) + FIELD(APLL_CTRL, RESET, 0, 1) +REG32(APLL_CFG, 0x24) + FIELD(APLL_CFG, LOCK_DLY, 25, 7) + FIELD(APLL_CFG, LOCK_CNT, 13, 10) + FIELD(APLL_CFG, LFHF, 10, 2) + FIELD(APLL_CFG, CP, 5, 4) + FIELD(APLL_CFG, RES, 0, 4) +REG32(APLL_FRAC_CFG, 0x28) + FIELD(APLL_FRAC_CFG, ENABLED, 31, 1) + FIELD(APLL_FRAC_CFG, SEED, 22, 3) + FIELD(APLL_FRAC_CFG, ALGRTHM, 19, 1) + FIELD(APLL_FRAC_CFG, ORDER, 18, 1) + FIELD(APLL_FRAC_CFG, DATA, 0, 16) +REG32(DPLL_CTRL, 0x2c) + FIELD(DPLL_CTRL, POST_SRC, 24, 3) + FIELD(DPLL_CTRL, PRE_SRC, 20, 3) + FIELD(DPLL_CTRL, CLKOUTDIV, 17, 1) + FIELD(DPLL_CTRL, DIV2, 16, 1) + FIELD(DPLL_CTRL, FBDIV, 8, 7) + FIELD(DPLL_CTRL, BYPASS, 3, 1) + FIELD(DPLL_CTRL, RESET, 0, 1) +REG32(DPLL_CFG, 0x30) + FIELD(DPLL_CFG, LOCK_DLY, 25, 7) + FIELD(DPLL_CFG, LOCK_CNT, 13, 10) + FIELD(DPLL_CFG, LFHF, 10, 2) + FIELD(DPLL_CFG, CP, 5, 4) + FIELD(DPLL_CFG, RES, 0, 4) +REG32(DPLL_FRAC_CFG, 0x34) + FIELD(DPLL_FRAC_CFG, ENABLED, 31, 1) + FIELD(DPLL_FRAC_CFG, SEED, 22, 3) + FIELD(DPLL_FRAC_CFG, ALGRTHM, 19, 1) + FIELD(DPLL_FRAC_CFG, ORDER, 18, 1) + FIELD(DPLL_FRAC_CFG, DATA, 0, 16) +REG32(VPLL_CTRL, 0x38) + FIELD(VPLL_CTRL, POST_SRC, 24, 3) + FIELD(VPLL_CTRL, PRE_SRC, 20, 3) + FIELD(VPLL_CTRL, CLKOUTDIV, 17, 1) + FIELD(VPLL_CTRL, DIV2, 16, 1) + FIELD(VPLL_CTRL, FBDIV, 8, 7) + FIELD(VPLL_CTRL, BYPASS, 3, 1) + FIELD(VPLL_CTRL, RESET, 0, 1) +REG32(VPLL_CFG, 0x3c) + FIELD(VPLL_CFG, LOCK_DLY, 25, 7) + FIELD(VPLL_CFG, LOCK_CNT, 13, 10) + FIELD(VPLL_CFG, LFHF, 10, 2) + FIELD(VPLL_CFG, CP, 5, 4) + FIELD(VPLL_CFG, RES, 0, 4) +REG32(VPLL_FRAC_CFG, 0x40) + FIELD(VPLL_FRAC_CFG, ENABLED, 31, 1) + FIELD(VPLL_FRAC_CFG, SEED, 22, 3) + FIELD(VPLL_FRAC_CFG, ALGRTHM, 19, 1) + FIELD(VPLL_FRAC_CFG, ORDER, 18, 1) + FIELD(VPLL_FRAC_CFG, DATA, 0, 16) +REG32(PLL_STATUS, 0x44) + FIELD(PLL_STATUS, VPLL_STABLE, 5, 1) + FIELD(PLL_STATUS, DPLL_STABLE, 4, 1) + FIELD(PLL_STATUS, APLL_STABLE, 3, 1) + FIELD(PLL_STATUS, VPLL_LOCK, 2, 1) + FIELD(PLL_STATUS, DPLL_LOCK, 1, 1) + FIELD(PLL_STATUS, APLL_LOCK, 0, 1) +REG32(APLL_TO_LPD_CTRL, 0x48) + FIELD(APLL_TO_LPD_CTRL, DIVISOR0, 8, 6) +REG32(DPLL_TO_LPD_CTRL, 0x4c) + FIELD(DPLL_TO_LPD_CTRL, DIVISOR0, 8, 6) +REG32(VPLL_TO_LPD_CTRL, 0x50) + FIELD(VPLL_TO_LPD_CTRL, DIVISOR0, 8, 6) +REG32(ACPU_CTRL, 0x60) + FIELD(ACPU_CTRL, CLKACT_HALF, 25, 1) + FIELD(ACPU_CTRL, CLKACT_FULL, 24, 1) + FIELD(ACPU_CTRL, DIVISOR0, 8, 6) + FIELD(ACPU_CTRL, SRCSEL, 0, 3) +REG32(DBG_TRACE_CTRL, 0x64) + FIELD(DBG_TRACE_CTRL, CLKACT, 24, 1) + FIELD(DBG_TRACE_CTRL, DIVISOR0, 8, 6) + FIELD(DBG_TRACE_CTRL, SRCSEL, 0, 3) +REG32(DBG_FPD_CTRL, 0x68) + FIELD(DBG_FPD_CTRL, CLKACT, 24, 1) + FIELD(DBG_FPD_CTRL, DIVISOR0, 8, 6) + FIELD(DBG_FPD_CTRL, SRCSEL, 0, 3) +REG32(DP_VIDEO_REF_CTRL, 0x70) + FIELD(DP_VIDEO_REF_CTRL, CLKACT, 24, 1) + FIELD(DP_VIDEO_REF_CTRL, DIVISOR1, 16, 6) + FIELD(DP_VIDEO_REF_CTRL, DIVISOR0, 8, 6) + FIELD(DP_VIDEO_REF_CTRL, SRCSEL, 0, 3) +REG32(DP_AUDIO_REF_CTRL, 0x74) + FIELD(DP_AUDIO_REF_CTRL, CLKACT, 24, 1) + FIELD(DP_AUDIO_REF_CTRL, DIVISOR1, 16, 6) + FIELD(DP_AUDIO_REF_CTRL, DIVISOR0, 8, 6) + FIELD(DP_AUDIO_REF_CTRL, SRCSEL, 0, 3) +REG32(DP_STC_REF_CTRL, 0x7c) + FIELD(DP_STC_REF_CTRL, CLKACT, 24, 1) + FIELD(DP_STC_REF_CTRL, DIVISOR1, 16, 6) + FIELD(DP_STC_REF_CTRL, DIVISOR0, 8, 6) + FIELD(DP_STC_REF_CTRL, SRCSEL, 0, 3) +REG32(DDR_CTRL, 0x80) + FIELD(DDR_CTRL, CLKACT, 24, 1) + FIELD(DDR_CTRL, DIVISOR0, 8, 6) + FIELD(DDR_CTRL, SRCSEL, 0, 3) +REG32(GPU_REF_CTRL, 0x84) + FIELD(GPU_REF_CTRL, PP1_CLKACT, 26, 1) + FIELD(GPU_REF_CTRL, PP0_CLKACT, 25, 1) + FIELD(GPU_REF_CTRL, CLKACT, 24, 1) + FIELD(GPU_REF_CTRL, DIVISOR0, 8, 6) + FIELD(GPU_REF_CTRL, SRCSEL, 0, 3) +REG32(SATA_REF_CTRL, 0xa0) + FIELD(SATA_REF_CTRL, CLKACT, 24, 1) + FIELD(SATA_REF_CTRL, DIVISOR0, 8, 6) + FIELD(SATA_REF_CTRL, SRCSEL, 0, 3) +REG32(PCIE_REF_CTRL, 0xb4) + FIELD(PCIE_REF_CTRL, CLKACT, 24, 1) + FIELD(PCIE_REF_CTRL, DIVISOR0, 8, 6) + FIELD(PCIE_REF_CTRL, SRCSEL, 0, 3) +REG32(GDMA_REF_CTRL, 0xb8) + FIELD(GDMA_REF_CTRL, CLKACT, 24, 1) + FIELD(GDMA_REF_CTRL, DIVISOR0, 8, 6) + FIELD(GDMA_REF_CTRL, SRCSEL, 0, 3) +REG32(DPDMA_REF_CTRL, 0xbc) + FIELD(DPDMA_REF_CTRL, CLKACT, 24, 1) + FIELD(DPDMA_REF_CTRL, DIVISOR0, 8, 6) + FIELD(DPDMA_REF_CTRL, SRCSEL, 0, 3) +REG32(TOPSW_MAIN_CTRL, 0xc0) + FIELD(TOPSW_MAIN_CTRL, CLKACT, 24, 1) + FIELD(TOPSW_MAIN_CTRL, DIVISOR0, 8, 6) + FIELD(TOPSW_MAIN_CTRL, SRCSEL, 0, 3) +REG32(TOPSW_LSBUS_CTRL, 0xc4) + FIELD(TOPSW_LSBUS_CTRL, CLKACT, 24, 1) + FIELD(TOPSW_LSBUS_CTRL, DIVISOR0, 8, 6) + FIELD(TOPSW_LSBUS_CTRL, SRCSEL, 0, 3) +REG32(DBG_TSTMP_CTRL, 0xf8) + FIELD(DBG_TSTMP_CTRL, DIVISOR0, 8, 6) + FIELD(DBG_TSTMP_CTRL, SRCSEL, 0, 3) +REG32(RST_FPD_TOP, 0x100) + FIELD(RST_FPD_TOP, PCIE_CFG_RESET, 19, 1) + FIELD(RST_FPD_TOP, PCIE_BRIDGE_RESET, 18, 1) + FIELD(RST_FPD_TOP, PCIE_CTRL_RESET, 17, 1) + FIELD(RST_FPD_TOP, DP_RESET, 16, 1) + FIELD(RST_FPD_TOP, SWDT_RESET, 15, 1) + FIELD(RST_FPD_TOP, AFI_FM5_RESET, 12, 1) + FIELD(RST_FPD_TOP, AFI_FM4_RESET, 11, 1) + FIELD(RST_FPD_TOP, AFI_FM3_RESET, 10, 1) + FIELD(RST_FPD_TOP, AFI_FM2_RESET, 9, 1) + FIELD(RST_FPD_TOP, AFI_FM1_RESET, 8, 1) + FIELD(RST_FPD_TOP, AFI_FM0_RESET, 7, 1) + FIELD(RST_FPD_TOP, GDMA_RESET, 6, 1) + FIELD(RST_FPD_TOP, GPU_PP1_RESET, 5, 1) + FIELD(RST_FPD_TOP, GPU_PP0_RESET, 4, 1) + FIELD(RST_FPD_TOP, GPU_RESET, 3, 1) + FIELD(RST_FPD_TOP, GT_RESET, 2, 1) + FIELD(RST_FPD_TOP, SATA_RESET, 1, 1) +REG32(RST_FPD_APU, 0x104) + FIELD(RST_FPD_APU, ACPU3_PWRON_RESET, 13, 1) + FIELD(RST_FPD_APU, ACPU2_PWRON_RESET, 12, 1) + FIELD(RST_FPD_APU, ACPU1_PWRON_RESET, 11, 1) + FIELD(RST_FPD_APU, ACPU0_PWRON_RESET, 10, 1) + FIELD(RST_FPD_APU, APU_L2_RESET, 8, 1) + FIELD(RST_FPD_APU, ACPU3_RESET, 3, 1) + FIELD(RST_FPD_APU, ACPU2_RESET, 2, 1) + FIELD(RST_FPD_APU, ACPU1_RESET, 1, 1) + FIELD(RST_FPD_APU, ACPU0_RESET, 0, 1) +REG32(RST_DDR_SS, 0x108) + FIELD(RST_DDR_SS, DDR_RESET, 3, 1) + FIELD(RST_DDR_SS, APM_RESET, 2, 1) + +#define CRF_R_MAX (R_RST_DDR_SS + 1) + +struct XlnxZynqMPCRF { + SysBusDevice parent_obj; + MemoryRegion iomem; + qemu_irq irq_ir; + + RegisterInfoArray *reg_array; + uint32_t regs[CRF_R_MAX]; + RegisterInfo regs_info[CRF_R_MAX]; +}; + +#endif diff --git a/hw/misc/xlnx-zynqmp-crf.c b/hw/misc/xlnx-zynqmp-crf.c new file mode 100644 index 00000000000..57bc8cf49ae --- /dev/null +++ b/hw/misc/xlnx-zynqmp-crf.c @@ -0,0 +1,266 @@ +/* + * QEMU model of the CRF - Clock Reset FPD. + * + * Copyright (c) 2022 Xilinx Inc. + * SPDX-License-Identifier: GPL-2.0-or-later + * Written by Edgar E. Iglesias + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/register.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "migration/vmstate.h" +#include "hw/irq.h" +#include "hw/misc/xlnx-zynqmp-crf.h" +#include "target/arm/arm-powerctl.h" + +#ifndef XLNX_ZYNQMP_CRF_ERR_DEBUG +#define XLNX_ZYNQMP_CRF_ERR_DEBUG 0 +#endif + +#define CRF_MAX_CPU 4 + +static void ir_update_irq(XlnxZynqMPCRF *s) +{ + bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK]; + qemu_set_irq(s->irq_ir, pending); +} + +static void ir_status_postw(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque); + ir_update_irq(s); +} + +static uint64_t ir_enable_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque); + uint32_t val = val64; + + s->regs[R_IR_MASK] &= ~val; + ir_update_irq(s); + return 0; +} + +static uint64_t ir_disable_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque); + uint32_t val = val64; + + s->regs[R_IR_MASK] |= val; + ir_update_irq(s); + return 0; +} + +static uint64_t rst_fpd_apu_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque); + uint32_t val = val64; + uint32_t val_old = s->regs[R_RST_FPD_APU]; + unsigned int i; + + for (i = 0; i < CRF_MAX_CPU; i++) { + uint32_t mask = (1 << (R_RST_FPD_APU_ACPU0_RESET_SHIFT + i)); + + if ((val ^ val_old) & mask) { + if (val & mask) { + arm_set_cpu_off(i); + } else { + arm_set_cpu_on_and_reset(i); + } + } + } + return val64; +} + +static const RegisterAccessInfo crf_regs_info[] = { + { .name = "ERR_CTRL", .addr = A_ERR_CTRL, + },{ .name = "IR_STATUS", .addr = A_IR_STATUS, + .w1c = 0x1, + .post_write = ir_status_postw, + },{ .name = "IR_MASK", .addr = A_IR_MASK, + .reset = 0x1, + .ro = 0x1, + },{ .name = "IR_ENABLE", .addr = A_IR_ENABLE, + .pre_write = ir_enable_prew, + },{ .name = "IR_DISABLE", .addr = A_IR_DISABLE, + .pre_write = ir_disable_prew, + },{ .name = "CRF_WPROT", .addr = A_CRF_WPROT, + },{ .name = "APLL_CTRL", .addr = A_APLL_CTRL, + .reset = 0x12c09, + .rsvd = 0xf88c80f6, + },{ .name = "APLL_CFG", .addr = A_APLL_CFG, + .rsvd = 0x1801210, + },{ .name = "APLL_FRAC_CFG", .addr = A_APLL_FRAC_CFG, + .rsvd = 0x7e330000, + },{ .name = "DPLL_CTRL", .addr = A_DPLL_CTRL, + .reset = 0x2c09, + .rsvd = 0xf88c80f6, + },{ .name = "DPLL_CFG", .addr = A_DPLL_CFG, + .rsvd = 0x1801210, + },{ .name = "DPLL_FRAC_CFG", .addr = A_DPLL_FRAC_CFG, + .rsvd = 0x7e330000, + },{ .name = "VPLL_CTRL", .addr = A_VPLL_CTRL, + .reset = 0x12809, + .rsvd = 0xf88c80f6, + },{ .name = "VPLL_CFG", .addr = A_VPLL_CFG, + .rsvd = 0x1801210, + },{ .name = "VPLL_FRAC_CFG", .addr = A_VPLL_FRAC_CFG, + .rsvd = 0x7e330000, + },{ .name = "PLL_STATUS", .addr = A_PLL_STATUS, + .reset = 0x3f, + .rsvd = 0xc0, + .ro = 0x3f, + },{ .name = "APLL_TO_LPD_CTRL", .addr = A_APLL_TO_LPD_CTRL, + .reset = 0x400, + .rsvd = 0xc0ff, + },{ .name = "DPLL_TO_LPD_CTRL", .addr = A_DPLL_TO_LPD_CTRL, + .reset = 0x400, + .rsvd = 0xc0ff, + },{ .name = "VPLL_TO_LPD_CTRL", .addr = A_VPLL_TO_LPD_CTRL, + .reset = 0x400, + .rsvd = 0xc0ff, + },{ .name = "ACPU_CTRL", .addr = A_ACPU_CTRL, + .reset = 0x3000400, + .rsvd = 0xfcffc0f8, + },{ .name = "DBG_TRACE_CTRL", .addr = A_DBG_TRACE_CTRL, + .reset = 0x2500, + .rsvd = 0xfeffc0f8, + },{ .name = "DBG_FPD_CTRL", .addr = A_DBG_FPD_CTRL, + .reset = 0x1002500, + .rsvd = 0xfeffc0f8, + },{ .name = "DP_VIDEO_REF_CTRL", .addr = A_DP_VIDEO_REF_CTRL, + .reset = 0x1002300, + .rsvd = 0xfec0c0f8, + },{ .name = "DP_AUDIO_REF_CTRL", .addr = A_DP_AUDIO_REF_CTRL, + .reset = 0x1032300, + .rsvd = 0xfec0c0f8, + },{ .name = "DP_STC_REF_CTRL", .addr = A_DP_STC_REF_CTRL, + .reset = 0x1203200, + .rsvd = 0xfec0c0f8, + },{ .name = "DDR_CTRL", .addr = A_DDR_CTRL, + .reset = 0x1000500, + .rsvd = 0xfeffc0f8, + },{ .name = "GPU_REF_CTRL", .addr = A_GPU_REF_CTRL, + .reset = 0x1500, + .rsvd = 0xf8ffc0f8, + },{ .name = "SATA_REF_CTRL", .addr = A_SATA_REF_CTRL, + .reset = 0x1001600, + .rsvd = 0xfeffc0f8, + },{ .name = "PCIE_REF_CTRL", .addr = A_PCIE_REF_CTRL, + .reset = 0x1500, + .rsvd = 0xfeffc0f8, + },{ .name = "GDMA_REF_CTRL", .addr = A_GDMA_REF_CTRL, + .reset = 0x1000500, + .rsvd = 0xfeffc0f8, + },{ .name = "DPDMA_REF_CTRL", .addr = A_DPDMA_REF_CTRL, + .reset = 0x1000500, + .rsvd = 0xfeffc0f8, + },{ .name = "TOPSW_MAIN_CTRL", .addr = A_TOPSW_MAIN_CTRL, + .reset = 0x1000400, + .rsvd = 0xfeffc0f8, + },{ .name = "TOPSW_LSBUS_CTRL", .addr = A_TOPSW_LSBUS_CTRL, + .reset = 0x1000800, + .rsvd = 0xfeffc0f8, + },{ .name = "DBG_TSTMP_CTRL", .addr = A_DBG_TSTMP_CTRL, + .reset = 0xa00, + .rsvd = 0xffffc0f8, + }, + { .name = "RST_FPD_TOP", .addr = A_RST_FPD_TOP, + .reset = 0xf9ffe, + .rsvd = 0xf06001, + },{ .name = "RST_FPD_APU", .addr = A_RST_FPD_APU, + .reset = 0x3d0f, + .rsvd = 0xc2f0, + .pre_write = rst_fpd_apu_prew, + },{ .name = "RST_DDR_SS", .addr = A_RST_DDR_SS, + .reset = 0xf, + .rsvd = 0xf3, + } +}; + +static void crf_reset_enter(Object *obj, ResetType type) +{ + XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj); + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { + register_reset(&s->regs_info[i]); + } +} + +static void crf_reset_hold(Object *obj) +{ + XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj); + ir_update_irq(s); +} + +static const MemoryRegionOps crf_ops = { + .read = register_read_memory, + .write = register_write_memory, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, +}; + +static void crf_init(Object *obj) +{ + XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + + s->reg_array = + register_init_block32(DEVICE(obj), crf_regs_info, + ARRAY_SIZE(crf_regs_info), + s->regs_info, s->regs, + &crf_ops, + XLNX_ZYNQMP_CRF_ERR_DEBUG, + CRF_R_MAX * 4); + sysbus_init_mmio(sbd, &s->reg_array->mem); + sysbus_init_irq(sbd, &s->irq_ir); +} + +static void crf_finalize(Object *obj) +{ + XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj); + register_finalize_block(s->reg_array); +} + +static const VMStateDescription vmstate_crf = { + .name = TYPE_XLNX_ZYNQMP_CRF, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPCRF, CRF_R_MAX), + VMSTATE_END_OF_LIST(), + } +}; + +static void crf_class_init(ObjectClass *klass, void *data) +{ + ResettableClass *rc = RESETTABLE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->vmsd = &vmstate_crf; + rc->phases.enter = crf_reset_enter; + rc->phases.hold = crf_reset_hold; +} + +static const TypeInfo crf_info = { + .name = TYPE_XLNX_ZYNQMP_CRF, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(XlnxZynqMPCRF), + .class_init = crf_class_init, + .instance_init = crf_init, + .instance_finalize = crf_finalize, +}; + +static void crf_register_types(void) +{ + type_register_static(&crf_info); +} + +type_init(crf_register_types) diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 645585371a8..61397f3bbb2 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -84,6 +84,7 @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files( )) softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c')) softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c')) +specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c')) softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files( 'xlnx-versal-xramc.c', 'xlnx-versal-pmc-iou-slcr.c', From patchwork Fri Mar 18 13:23:01 2022 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y15-20020a05600015cf00b00203e324347bsm6316599wry.102.2022.03.18.06.23.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 06:23:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/21] hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF Date: Fri, 18 Mar 2022 13:23:01 +0000 Message-Id: <20220318132306.3254960-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220318132306.3254960-1-peter.maydell@linaro.org> References: <20220318132306.3254960-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42a (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Connect the ZynqMP CRF - Clock Reset FPD device. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Francisco Iglesias Reviewed-by: Luc Michel Signed-off-by: Edgar E. Iglesias Message-id: 20220316164645.2303510-5-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-zynqmp.h | 2 ++ hw/arm/xlnx-zynqmp.c | 16 ++++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 0552ba18b41..7938f223a4a 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -39,6 +39,7 @@ #include "hw/nvram/xlnx-bbram.h" #include "hw/nvram/xlnx-zynqmp-efuse.h" #include "hw/or-irq.h" +#include "hw/misc/xlnx-zynqmp-crf.h" #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp" OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) @@ -124,6 +125,7 @@ struct XlnxZynqMPState { XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH]; XlnxCSUDMA qspi_dma; qemu_or_irq qspi_irq_orgate; + XlnxZynqMPCRF crf; char *boot_cpu; ARMCPU *boot_cpu_ptr; diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 47324cdc441..f4575eea7fa 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -52,6 +52,9 @@ #define QSPI_DMA_ADDR 0xff0f0800 #define NUM_QSPI_IRQ_LINES 2 +#define CRF_ADDR 0xfd1a0000 +#define CRF_IRQ 120 + /* Serializer/Deserializer. */ #define SERDES_ADDR 0xfd400000 #define SERDES_SIZE 0x20000 @@ -280,6 +283,18 @@ static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic) sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]); } +static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic) +{ + SysBusDevice *sbd; + + object_initialize_child(OBJECT(s), "crf", &s->crf, TYPE_XLNX_ZYNQMP_CRF); + sbd = SYS_BUS_DEVICE(&s->crf); + + sysbus_realize(sbd, &error_fatal); + sysbus_mmio_map(sbd, 0, CRF_ADDR); + sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]); +} + static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s) { static const struct UnimpInfo { @@ -684,6 +699,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) xlnx_zynqmp_create_bbram(s, gic_spi); xlnx_zynqmp_create_efuse(s, gic_spi); + xlnx_zynqmp_create_crf(s, gic_spi); xlnx_zynqmp_create_unimp_mmio(s); for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { From patchwork Fri Mar 18 13:23:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 552618 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp2084354mag; Fri, 18 Mar 2022 06:40:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwxKi0G3U0ArpYDT4X6AhqKuNJ1BgGOsR808vyFo6SHJLCT4rVf6Yca087xkVYw2wIfJ551 X-Received: by 2002:a05:620a:44d4:b0:67d:ba87:e4ee with SMTP id y20-20020a05620a44d400b0067dba87e4eemr5795305qkp.734.1647610845095; Fri, 18 Mar 2022 06:40:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647610845; cv=none; d=google.com; s=arc-20160816; b=rsthowqKGeF8VNpdZDDyh6fDYXe63vwDZyEw9vkxRCpOnJ4wKzGi0cpL3v/tkyvG9o LSmSyjts0WhF8iQwZp5EOVhSx+1WBpuzNroFB0HZ5+Vh7hsy+hDHNGKM7AqGElBw+ceF USy9vNOGeJDRfi9FK5nIG2KbLNDl2ikelEXM+GjrQkREG0XRxm9aJ/IK3DsehOsbHxLX yyEX3ZCVEl6tY62CgVjjb9ysv2KKOdo39EWd5/AzIvDdJDdhBHFQqizWuEAcCT8Panp5 hErf4Yt93Gx3rGcpW0P9616aIYcuMv4T2ctDNko71n+KKvRYX1kPD4IK0I/OZa6DH6vO cBbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WEBPKtTl0A+spGyHf/Omw3nlUPpx87pLP+QlMJlWJIU=; b=LmR5Rw+ux/hqnDMfhWyobfa5IdRafTbeFL+19cwEJ/j1yYHTLNHN82Yc26mSIxCZz+ vMopptEXG9tKnuO0McpysReUYYlKNEbcaX0KLe2xyL5JaAKl1HlzouSJvRknJZxLL6l4 9SaKff4bezc+n3TT6Sn46lVPFvtCyoj8k5Oy0OxHIkiLqIpKO94aLt6ylgGZ0ctrfbr6 r+5RT71aqYd47KgUVfiu0hXpn3Yv4wKj6WkMYlbEuLskfy0jYHOFxxtK05dIH5+LwPyd vrrtLruuw+R7+stzOX017pOZlUj09T9Jq4Umj2fbL/buxPHcz4H5TFspJ3quqvbPVruD Akmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=irmgDjt5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y15-20020a05600015cf00b00203e324347bsm6316599wry.102.2022.03.18.06.23.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 06:23:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/21] hw/misc: Add a model of the Xilinx ZynqMP APU Control Date: Fri, 18 Mar 2022 13:23:02 +0000 Message-Id: <20220318132306.3254960-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220318132306.3254960-1-peter.maydell@linaro.org> References: <20220318132306.3254960-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32f (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Add a model of the Xilinx ZynqMP APU Control. Reviewed-by: Luc Michel Signed-off-by: Edgar E. Iglesias Message-id: 20220316164645.2303510-6-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 93 +++++++++ hw/misc/xlnx-zynqmp-apu-ctrl.c | 253 +++++++++++++++++++++++++ hw/misc/meson.build | 1 + 3 files changed, 347 insertions(+) create mode 100644 include/hw/misc/xlnx-zynqmp-apu-ctrl.h create mode 100644 hw/misc/xlnx-zynqmp-apu-ctrl.c diff --git a/include/hw/misc/xlnx-zynqmp-apu-ctrl.h b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h new file mode 100644 index 00000000000..b8ca9434afb --- /dev/null +++ b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h @@ -0,0 +1,93 @@ +/* + * QEMU model of ZynqMP APU Control. + * + * Copyright (c) 2013-2022 Xilinx Inc + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Written by Peter Crosthwaite and + * Edgar E. Iglesias + * + */ +#ifndef HW_MISC_XLNX_ZYNQMP_APU_CTRL_H +#define HW_MISC_XLNX_ZYNQMP_APU_CTRL_H + +#include "hw/sysbus.h" +#include "hw/register.h" +#include "target/arm/cpu.h" + +#define TYPE_XLNX_ZYNQMP_APU_CTRL "xlnx.apu-ctrl" +OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPAPUCtrl, XLNX_ZYNQMP_APU_CTRL) + +REG32(APU_ERR_CTRL, 0x0) + FIELD(APU_ERR_CTRL, PSLVERR, 0, 1) +REG32(ISR, 0x10) + FIELD(ISR, INV_APB, 0, 1) +REG32(IMR, 0x14) + FIELD(IMR, INV_APB, 0, 1) +REG32(IEN, 0x18) + FIELD(IEN, INV_APB, 0, 1) +REG32(IDS, 0x1c) + FIELD(IDS, INV_APB, 0, 1) +REG32(CONFIG_0, 0x20) + FIELD(CONFIG_0, CFGTE, 24, 4) + FIELD(CONFIG_0, CFGEND, 16, 4) + FIELD(CONFIG_0, VINITHI, 8, 4) + FIELD(CONFIG_0, AA64NAA32, 0, 4) +REG32(CONFIG_1, 0x24) + FIELD(CONFIG_1, L2RSTDISABLE, 29, 1) + FIELD(CONFIG_1, L1RSTDISABLE, 28, 1) + FIELD(CONFIG_1, CP15DISABLE, 0, 4) +REG32(RVBARADDR0L, 0x40) + FIELD(RVBARADDR0L, ADDR, 2, 30) +REG32(RVBARADDR0H, 0x44) + FIELD(RVBARADDR0H, ADDR, 0, 8) +REG32(RVBARADDR1L, 0x48) + FIELD(RVBARADDR1L, ADDR, 2, 30) +REG32(RVBARADDR1H, 0x4c) + FIELD(RVBARADDR1H, ADDR, 0, 8) +REG32(RVBARADDR2L, 0x50) + FIELD(RVBARADDR2L, ADDR, 2, 30) +REG32(RVBARADDR2H, 0x54) + FIELD(RVBARADDR2H, ADDR, 0, 8) +REG32(RVBARADDR3L, 0x58) + FIELD(RVBARADDR3L, ADDR, 2, 30) +REG32(RVBARADDR3H, 0x5c) + FIELD(RVBARADDR3H, ADDR, 0, 8) +REG32(ACE_CTRL, 0x60) + FIELD(ACE_CTRL, AWQOS, 16, 4) + FIELD(ACE_CTRL, ARQOS, 0, 4) +REG32(SNOOP_CTRL, 0x80) + FIELD(SNOOP_CTRL, ACE_INACT, 4, 1) + FIELD(SNOOP_CTRL, ACP_INACT, 0, 1) +REG32(PWRCTL, 0x90) + FIELD(PWRCTL, CLREXMONREQ, 17, 1) + FIELD(PWRCTL, L2FLUSHREQ, 16, 1) + FIELD(PWRCTL, CPUPWRDWNREQ, 0, 4) +REG32(PWRSTAT, 0x94) + FIELD(PWRSTAT, CLREXMONACK, 17, 1) + FIELD(PWRSTAT, L2FLUSHDONE, 16, 1) + FIELD(PWRSTAT, DBGNOPWRDWN, 0, 4) + +#define APU_R_MAX ((R_PWRSTAT) + 1) + +#define APU_MAX_CPU 4 + +struct XlnxZynqMPAPUCtrl { + SysBusDevice busdev; + + ARMCPU *cpus[APU_MAX_CPU]; + /* WFIs towards PMU. */ + qemu_irq wfi_out[4]; + /* CPU Power status towards INTC Redirect. */ + qemu_irq cpu_power_status[4]; + qemu_irq irq_imr; + + uint8_t cpu_pwrdwn_req; + uint8_t cpu_in_wfi; + + RegisterInfoArray *reg_array; + uint32_t regs[APU_R_MAX]; + RegisterInfo regs_info[APU_R_MAX]; +}; + +#endif diff --git a/hw/misc/xlnx-zynqmp-apu-ctrl.c b/hw/misc/xlnx-zynqmp-apu-ctrl.c new file mode 100644 index 00000000000..20de23cf671 --- /dev/null +++ b/hw/misc/xlnx-zynqmp-apu-ctrl.c @@ -0,0 +1,253 @@ +/* + * QEMU model of the ZynqMP APU Control. + * + * Copyright (c) 2013-2022 Xilinx Inc + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Written by Peter Crosthwaite and + * Edgar E. Iglesias + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/log.h" +#include "migration/vmstate.h" +#include "hw/qdev-properties.h" +#include "hw/sysbus.h" +#include "hw/irq.h" +#include "hw/register.h" + +#include "qemu/bitops.h" +#include "qapi/qmp/qerror.h" + +#include "hw/misc/xlnx-zynqmp-apu-ctrl.h" + +#ifndef XILINX_ZYNQMP_APU_ERR_DEBUG +#define XILINX_ZYNQMP_APU_ERR_DEBUG 0 +#endif + +static void update_wfi_out(void *opaque) +{ + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(opaque); + unsigned int i, wfi_pending; + + wfi_pending = s->cpu_pwrdwn_req & s->cpu_in_wfi; + for (i = 0; i < APU_MAX_CPU; i++) { + qemu_set_irq(s->wfi_out[i], !!(wfi_pending & (1 << i))); + } +} + +static void zynqmp_apu_rvbar_post_write(RegisterInfo *reg, uint64_t val) +{ + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque); + int i; + + for (i = 0; i < APU_MAX_CPU; ++i) { + uint64_t rvbar = s->regs[R_RVBARADDR0L + 2 * i] + + ((uint64_t)s->regs[R_RVBARADDR0H + 2 * i] << 32); + if (s->cpus[i]) { + object_property_set_int(OBJECT(s->cpus[i]), "rvbar", rvbar, + &error_abort); + } + } +} + +static void zynqmp_apu_pwrctl_post_write(RegisterInfo *reg, uint64_t val) +{ + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque); + unsigned int i, new; + + for (i = 0; i < APU_MAX_CPU; i++) { + new = val & (1 << i); + /* Check if CPU's CPUPWRDNREQ has changed. If yes, update GPIOs. */ + if (new != (s->cpu_pwrdwn_req & (1 << i))) { + qemu_set_irq(s->cpu_power_status[i], !!new); + } + s->cpu_pwrdwn_req &= ~(1 << i); + s->cpu_pwrdwn_req |= new; + } + update_wfi_out(s); +} + +static void imr_update_irq(XlnxZynqMPAPUCtrl *s) +{ + bool pending = s->regs[R_ISR] & ~s->regs[R_IMR]; + qemu_set_irq(s->irq_imr, pending); +} + +static void isr_postw(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque); + imr_update_irq(s); +} + +static uint64_t ien_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque); + uint32_t val = val64; + + s->regs[R_IMR] &= ~val; + imr_update_irq(s); + return 0; +} + +static uint64_t ids_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque); + uint32_t val = val64; + + s->regs[R_IMR] |= val; + imr_update_irq(s); + return 0; +} + +static const RegisterAccessInfo zynqmp_apu_regs_info[] = { +#define RVBAR_REGDEF(n) \ + { .name = "RVBAR CPU " #n " Low", .addr = A_RVBARADDR ## n ## L, \ + .reset = 0xffff0000ul, \ + .post_write = zynqmp_apu_rvbar_post_write, \ + },{ .name = "RVBAR CPU " #n " High", .addr = A_RVBARADDR ## n ## H, \ + .post_write = zynqmp_apu_rvbar_post_write, \ + } + { .name = "ERR_CTRL", .addr = A_APU_ERR_CTRL, + },{ .name = "ISR", .addr = A_ISR, + .w1c = 0x1, + .post_write = isr_postw, + },{ .name = "IMR", .addr = A_IMR, + .reset = 0x1, + .ro = 0x1, + },{ .name = "IEN", .addr = A_IEN, + .pre_write = ien_prew, + },{ .name = "IDS", .addr = A_IDS, + .pre_write = ids_prew, + },{ .name = "CONFIG_0", .addr = A_CONFIG_0, + .reset = 0xf0f, + },{ .name = "CONFIG_1", .addr = A_CONFIG_1, + }, + RVBAR_REGDEF(0), + RVBAR_REGDEF(1), + RVBAR_REGDEF(2), + RVBAR_REGDEF(3), + { .name = "ACE_CTRL", .addr = A_ACE_CTRL, + .reset = 0xf000f, + },{ .name = "SNOOP_CTRL", .addr = A_SNOOP_CTRL, + },{ .name = "PWRCTL", .addr = A_PWRCTL, + .post_write = zynqmp_apu_pwrctl_post_write, + },{ .name = "PWRSTAT", .addr = A_PWRSTAT, + .ro = 0x3000f, + } +}; + +static void zynqmp_apu_reset_enter(Object *obj, ResetType type) +{ + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj); + int i; + + for (i = 0; i < APU_R_MAX; ++i) { + register_reset(&s->regs_info[i]); + } + + s->cpu_pwrdwn_req = 0; + s->cpu_in_wfi = 0; +} + +static void zynqmp_apu_reset_hold(Object *obj) +{ + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj); + + update_wfi_out(s); + imr_update_irq(s); +} + +static const MemoryRegionOps zynqmp_apu_ops = { + .read = register_read_memory, + .write = register_write_memory, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + } +}; + +static void zynqmp_apu_handle_wfi(void *opaque, int irq, int level) +{ + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(opaque); + + s->cpu_in_wfi = deposit32(s->cpu_in_wfi, irq, 1, level); + update_wfi_out(s); +} + +static void zynqmp_apu_init(Object *obj) +{ + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj); + int i; + + s->reg_array = + register_init_block32(DEVICE(obj), zynqmp_apu_regs_info, + ARRAY_SIZE(zynqmp_apu_regs_info), + s->regs_info, s->regs, + &zynqmp_apu_ops, + XILINX_ZYNQMP_APU_ERR_DEBUG, + APU_R_MAX * 4); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->reg_array->mem); + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq_imr); + + for (i = 0; i < APU_MAX_CPU; ++i) { + g_autofree gchar *prop_name = g_strdup_printf("cpu%d", i); + object_property_add_link(obj, prop_name, TYPE_ARM_CPU, + (Object **)&s->cpus[i], + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG); + } + + /* wfi_out is used to connect to PMU GPIs. */ + qdev_init_gpio_out_named(DEVICE(obj), s->wfi_out, "wfi_out", 4); + /* CPU_POWER_STATUS is used to connect to INTC redirect. */ + qdev_init_gpio_out_named(DEVICE(obj), s->cpu_power_status, + "CPU_POWER_STATUS", 4); + /* wfi_in is used as input from CPUs as wfi request. */ + qdev_init_gpio_in_named(DEVICE(obj), zynqmp_apu_handle_wfi, "wfi_in", 4); +} + +static void zynqmp_apu_finalize(Object *obj) +{ + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj); + register_finalize_block(s->reg_array); +} + +static const VMStateDescription vmstate_zynqmp_apu = { + .name = TYPE_XLNX_ZYNQMP_APU_CTRL, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPAPUCtrl, APU_R_MAX), + VMSTATE_END_OF_LIST(), + } +}; + +static void zynqmp_apu_class_init(ObjectClass *klass, void *data) +{ + ResettableClass *rc = RESETTABLE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->vmsd = &vmstate_zynqmp_apu; + + rc->phases.enter = zynqmp_apu_reset_enter; + rc->phases.hold = zynqmp_apu_reset_hold; +} + +static const TypeInfo zynqmp_apu_info = { + .name = TYPE_XLNX_ZYNQMP_APU_CTRL, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(XlnxZynqMPAPUCtrl), + .class_init = zynqmp_apu_class_init, + .instance_init = zynqmp_apu_init, + .instance_finalize = zynqmp_apu_finalize, +}; + +static void zynqmp_apu_register_types(void) +{ + type_register_static(&zynqmp_apu_info); +} + +type_init(zynqmp_apu_register_types) diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 61397f3bbb2..6fb69612e06 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -85,6 +85,7 @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files( softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c')) softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c')) specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c')) +specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c')) softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files( 'xlnx-versal-xramc.c', 'xlnx-versal-pmc-iou-slcr.c', From patchwork Fri Mar 18 13:23:03 2022 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y15-20020a05600015cf00b00203e324347bsm6316599wry.102.2022.03.18.06.23.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 06:23:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/21] hw/arm/xlnx-zynqmp: Connect the ZynqMP APU Control Date: Fri, 18 Mar 2022 13:23:03 +0000 Message-Id: <20220318132306.3254960-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220318132306.3254960-1-peter.maydell@linaro.org> References: <20220318132306.3254960-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::432 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Connect the ZynqMP APU Control device. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Francisco Iglesias Reviewed-by: Luc Michel Signed-off-by: Edgar E. Iglesias Message-id: 20220316164645.2303510-7-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-zynqmp.h | 4 +++- hw/arm/xlnx-zynqmp.c | 25 +++++++++++++++++++++++-- 2 files changed, 26 insertions(+), 3 deletions(-) diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 7938f223a4a..9d9a9d0bf9d 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -39,6 +39,7 @@ #include "hw/nvram/xlnx-bbram.h" #include "hw/nvram/xlnx-zynqmp-efuse.h" #include "hw/or-irq.h" +#include "hw/misc/xlnx-zynqmp-apu-ctrl.h" #include "hw/misc/xlnx-zynqmp-crf.h" #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp" @@ -86,7 +87,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) /* * Unimplemented mmio regions needed to boot some images. */ -#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 2 +#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 1 struct XlnxZynqMPState { /*< private >*/ @@ -125,6 +126,7 @@ struct XlnxZynqMPState { XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH]; XlnxCSUDMA qspi_dma; qemu_or_irq qspi_irq_orgate; + XlnxZynqMPAPUCtrl apu_ctrl; XlnxZynqMPCRF crf; char *boot_cpu; diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index f4575eea7fa..5bfe285a191 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -66,7 +66,7 @@ #define DPDMA_IRQ 116 #define APU_ADDR 0xfd5c0000 -#define APU_SIZE 0x100 +#define APU_IRQ 153 #define IPI_ADDR 0xFF300000 #define IPI_IRQ 64 @@ -283,6 +283,27 @@ static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic) sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]); } +static void xlnx_zynqmp_create_apu_ctrl(XlnxZynqMPState *s, qemu_irq *gic) +{ + SysBusDevice *sbd; + int i; + + object_initialize_child(OBJECT(s), "apu-ctrl", &s->apu_ctrl, + TYPE_XLNX_ZYNQMP_APU_CTRL); + sbd = SYS_BUS_DEVICE(&s->apu_ctrl); + + for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { + g_autofree gchar *name = g_strdup_printf("cpu%d", i); + + object_property_set_link(OBJECT(&s->apu_ctrl), name, + OBJECT(&s->apu_cpu[i]), &error_abort); + } + + sysbus_realize(sbd, &error_fatal); + sysbus_mmio_map(sbd, 0, APU_ADDR); + sysbus_connect_irq(sbd, 0, gic[APU_IRQ]); +} + static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic) { SysBusDevice *sbd; @@ -302,7 +323,6 @@ static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s) hwaddr base; hwaddr size; } unimp_areas[ARRAY_SIZE(s->mr_unimp)] = { - { .name = "apu", APU_ADDR, APU_SIZE }, { .name = "serdes", SERDES_ADDR, SERDES_SIZE }, }; unsigned int nr; @@ -699,6 +719,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) xlnx_zynqmp_create_bbram(s, gic_spi); xlnx_zynqmp_create_efuse(s, gic_spi); + xlnx_zynqmp_create_apu_ctrl(s, gic_spi); xlnx_zynqmp_create_crf(s, gic_spi); xlnx_zynqmp_create_unimp_mmio(s); From patchwork Fri Mar 18 13:23:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 552617 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp2082733mag; Fri, 18 Mar 2022 06:38:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxYPfn3yJ2zBzYJtkCXsiI99Bb2PpIvBHZvoCsYKzQNJ2T1GSqGFvfVVDhUCBOaHBlMCTWn X-Received: by 2002:ad4:4eeb:0:b0:435:b435:81f4 with SMTP id dv11-20020ad44eeb000000b00435b43581f4mr6990363qvb.35.1647610703927; Fri, 18 Mar 2022 06:38:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647610703; cv=none; d=google.com; s=arc-20160816; b=zasllCbN0w3PYvMEsHZvAyGRU2D0r11JSr6k0cRDZYPEue0zSelAuzjzuXbxqHsa/3 +PPAHkrHUQ3Sl8MKfBX1t7GAOEQQEyTZ2XkJE801XHjhgk+Gh1aF33selCeAnxFfTO3q LgENzRhZr416fGPxZ5uzPG1HnGgeoE3tnF0Q2vVyaTveunshAKE9fn5jbhelJmtQPjVJ T0eAfp2JB7KW5qkMBdDMlegsxT22rIobwHsNrbYpaU1AXrxIFm2VJzEiILteOj5d94f4 NSRc7tX6i3GO7ctkXKSR5vliRa82HFM2eRwUOL2WnHGic5/E0RPS3qpOFbsgXgIe8HPW j47Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=n35AFs9v+Ihl4A7Mb9rzofI88nppswgEUkv1KZhYPHc=; b=EmgGW5Q5w3Bz6tyPWTbOPKFRpxpCNN4FTavLDP/4byjOxdb4Gok8dgiLkqJspWIDtR VxCADt+7WCWSAKM9VBffNCXDn/ijD48UoaxGh4dx2eNP8rfygTr0/jtWPZrCJ640+P/+ Ds+mJicgCL/YumavG7c92nAIlWl+gWV8ipqRKoOq6z4SmBA4I6wpLLSU8UFr1/m5srSy btXaqUF7fQV4Yo4SALNzlJ92rgcx62E1uUegQycVYlgKwnYz9693HM17sJwliYmMW5XN 18ukbxf2OUFcEqMCqE+jIFmAyK/Ons4gNYy281w8njSkdrk5JM5rv7A8vVPBch11SVSI crkA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MF0qHKz6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y15-20020a05600015cf00b00203e324347bsm6316599wry.102.2022.03.18.06.23.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 06:23:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/21] util/osdep: Avoid madvise proto on modern Solaris Date: Fri, 18 Mar 2022 13:23:04 +0000 Message-Id: <20220318132306.3254960-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220318132306.3254960-1-peter.maydell@linaro.org> References: <20220318132306.3254960-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42e (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Andrew Deason On older Solaris releases (before Solaris 11), we didn't get a prototype for madvise, and so util/osdep.c provides its own prototype. Some time between the public Solaris 11.4 release and Solaris 11.4.42 CBE, we started getting an madvise prototype that looks like this: extern int madvise(void *, size_t, int); which conflicts with the prototype in util/osdeps.c. Instead of always declaring this prototype, check if we're missing the madvise() prototype, and only declare it ourselves if the prototype is missing. Move the prototype to include/qemu/osdep.h, the normal place to handle platform-specific header quirks. The 'missing_madvise_proto' meson check contains an obviously wrong prototype for madvise. So if that code compiles and links, we must be missing the actual prototype for madvise. Signed-off-by: Andrew Deason Message-id: 20220316035227.3702-2-adeason@sinenomine.net Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- meson.build | 23 +++++++++++++++++++++-- include/qemu/osdep.h | 8 ++++++++ util/osdep.c | 3 --- 3 files changed, 29 insertions(+), 5 deletions(-) diff --git a/meson.build b/meson.build index bae62efc9c3..282e7c46505 100644 --- a/meson.build +++ b/meson.build @@ -1715,11 +1715,30 @@ config_host_data.set('CONFIG_FDATASYNC', cc.links(gnu_source_prefix + ''' #error Not supported #endif }''')) -config_host_data.set('CONFIG_MADVISE', cc.links(gnu_source_prefix + ''' + +has_madvise = cc.links(gnu_source_prefix + ''' #include #include #include - int main(void) { return madvise(NULL, 0, MADV_DONTNEED); }''')) + int main(void) { return madvise(NULL, 0, MADV_DONTNEED); }''') +missing_madvise_proto = false +if has_madvise + # Some platforms (illumos and Solaris before Solaris 11) provide madvise() + # but forget to prototype it. In this case, has_madvise will be true (the + # test program links despite a compile warning). To detect the + # missing-prototype case, we try again with a definitely-bogus prototype. + # This will only compile if the system headers don't provide the prototype; + # otherwise the conflicting prototypes will cause a compiler error. + missing_madvise_proto = cc.links(gnu_source_prefix + ''' + #include + #include + #include + extern int madvise(int); + int main(void) { return madvise(0); }''') +endif +config_host_data.set('CONFIG_MADVISE', has_madvise) +config_host_data.set('HAVE_MADVISE_WITHOUT_PROTOTYPE', missing_madvise_proto) + config_host_data.set('CONFIG_MEMFD', cc.links(gnu_source_prefix + ''' #include int main(void) { return memfd_create("foo", MFD_ALLOW_SEALING); }''')) diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 322103aadbd..f2274b24cbf 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -400,6 +400,14 @@ void qemu_anon_ram_free(void *ptr, size_t size); #define SIGIO SIGPOLL #endif +#ifdef HAVE_MADVISE_WITHOUT_PROTOTYPE +/* + * See MySQL bug #7156 (http://bugs.mysql.com/bug.php?id=7156) for discussion + * about Solaris missing the madvise() prototype. + */ +extern int madvise(char *, size_t, int); +#endif + #if defined(CONFIG_LINUX) #ifndef BUS_MCEERR_AR #define BUS_MCEERR_AR 4 diff --git a/util/osdep.c b/util/osdep.c index 7c4deda6feb..1825399bcf5 100644 --- a/util/osdep.c +++ b/util/osdep.c @@ -28,9 +28,6 @@ #ifdef CONFIG_SOLARIS #include -/* See MySQL bug #7156 (http://bugs.mysql.com/bug.php?id=7156) for - discussion about Solaris header problems */ -extern int madvise(char *, size_t, int); #endif #include "qemu-common.h" From patchwork Fri Mar 18 13:23:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 552616 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp2082160mag; Fri, 18 Mar 2022 06:37:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyuzjnKLFe8qNHqyTfK0XrVeTxNMaL6WRG3SK6ZgYnVlaZGjrBK1N5odO/LVORGhFhRuIpj X-Received: by 2002:a05:622a:19aa:b0:2e1:bbde:7434 with SMTP id u42-20020a05622a19aa00b002e1bbde7434mr7680268qtc.160.1647610656581; Fri, 18 Mar 2022 06:37:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647610656; cv=none; d=google.com; s=arc-20160816; b=zl8dWuDkSfRYmQoQ3oLC1u3/pa9MFcEPYQlYGW5p/Gx5S4F0Kp6VnpU2V3qgm92Xj+ ntY/4we5EC2rrRtGkg8npmvViV5mnbgEs3k2ImQcPigikVVABY48mOrqldUHw6rpQ+7B 33658crd/jzfgRdeTEONwWz75QJQ43WXHD3QR1EFXai4SN1cfd4Hyp54kOEgeC6fMGMO AOjecof8YO+GivPtI78m5LkXTgjQbQ2OmT0MW73f14IqUyXbadX757z+KBOT4SEx0cy/ 674pxXFgjH97SSrDXUqlj1ANCJ03mgHU7u5mzJ8NPe5pGp7GbF9CcDETIDX4Ff7xRRnw dYhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=h4aEzyIE/QZgB0XPdQFg8Zi6U0RcdXK16fZmuwh6B20=; b=eZq+oY039bCQH8XhmXZpfRaObIs+8rMJvo87KMeG6M1vYikGFCu4KJGDZqJ6a1GKJq monxnXwb5VYJuWl6NT9H0K1Yl8i3JLTwyxZJu3fgR3DOxJVB3zef5MBUYoka+qOTlVkF optx3k03hk6fMMUYgqnTACTXGqFXbJS+vQ6O5CBrraLJNrdfEykXOg979eFEJto4T/NV mJEUVRf9Pysr4daR6laKEGDvJmrkOnCT4+FoRAwepjPF/muwDJ9gLjyrezZFw9J8bejg IX+z/aGMkV0mYWGOok1u4175lgxEgzd2MFJiQWwulKmZDKKU1slNAzMMzJyVbRljtdzp mXBQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=r7BarEy1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y15-20020a05600015cf00b00203e324347bsm6316599wry.102.2022.03.18.06.23.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 06:23:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/21] hw/i386/acpi-build: Avoid 'sun' identifier Date: Fri, 18 Mar 2022 13:23:05 +0000 Message-Id: <20220318132306.3254960-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220318132306.3254960-1-peter.maydell@linaro.org> References: <20220318132306.3254960-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42c (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Andrew Deason On Solaris, 'sun' is #define'd to 1, which causes errors if a variable is named 'sun'. Slightly change the name of the var for the Slot User Number so we can build on Solaris. Reviewed-by: Ani Sinha Signed-off-by: Andrew Deason Reviewed-by: Michael S. Tsirkin Message-id: 20220316035227.3702-3-adeason@sinenomine.net Signed-off-by: Peter Maydell --- hw/i386/acpi-build.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 4ad4d7286c8..dcf6ece3d04 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -583,7 +583,7 @@ Aml *aml_pci_device_dsm(void) Aml *bnum = aml_arg(4); Aml *func = aml_arg(2); Aml *rev = aml_arg(1); - Aml *sun = aml_arg(5); + Aml *sunum = aml_arg(5); method = aml_method("PDSM", 6, AML_SERIALIZED); @@ -594,7 +594,7 @@ Aml *aml_pci_device_dsm(void) UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); ifctx = aml_if(aml_equal(aml_arg(0), UUID)); { - aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sun), acpi_index)); + aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); ifctx1 = aml_if(aml_equal(func, zero)); { uint8_t byte_list[1]; From patchwork Fri Mar 18 13:23:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 552619 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6713:0:0:0:0 with SMTP id u19csp2087061mag; Fri, 18 Mar 2022 06:44:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwMPGAtOwmPT73p28KLxYv5WA9a0ZR8paX9gv7jIeLHkyyEIbSoOj3D3WxMBWmuQ8G910W/ X-Received: by 2002:a05:6214:23c5:b0:435:3700:d65 with SMTP id hr5-20020a05621423c500b0043537000d65mr6773626qvb.65.1647611072278; Fri, 18 Mar 2022 06:44:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1647611072; cv=none; d=google.com; s=arc-20160816; b=kh6JcS8dkLhIDpb2dqrcevW3uj1orrAxSg12xdCy9xzPz6e4hTy7PdsE2Bb0REVKdF e/GkQ7qHL305NByY6PRY4XdFS+DUy8PGDvEvpRas/rz161OrSNzRHjORePX/09I2khDm N8Ms9U7ypxLGYX1PaM7nGJioLdAQArM2qp5sKKz78sSamkQLPFojyjPNyPuK6/lZXNiP YBddVZ9mOIRNnayxV9xPNVjIV2lf1Zwf2asDym12j/swv92tNlOXAFygBA+SwkQ2oN+v l6wlI8s9quJgdpMxNVl6RI4/HXIe6KyA5+MHiC+5ooWyyPrltxiA7vAvkwA4sUU89Ldw ATfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Jsr4pB71msnavT45jlstw0IyWfAWo6VMkQJ10uKrMqk=; b=qmJJNSLVd36txj1UOerj7i4X5Jr12SsMT2hBFXq8tZupmtfdhyXbINc5nxn9auey9k I+rYeqj/gL9WIyAKPulp9FCN9qZ1AmO8fWlf8I8lr7+7Yc8Z/waIPbKXbk9zM3ZexpMs UspyudI1h7dpYuUbECjpijtOCwzhOiaknnX9WedWJmlh62uoZKriJNVhz+G+LbW6QFMt 61grFsgZ7NjoJRrBGo0SU9YqaUQy+3eMFqGIdsAThWsmFZPPzZQGjDdvyqy/yzx3uCv1 l8+uMA5QPCqCsaKRwQtq/DlMI18aWBEM3HePkQ5DTLO3BYzFAO3gYHFTXVKSCXWttuKJ Ur3g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=B79wn6m9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y15-20020a05600015cf00b00203e324347bsm6316599wry.102.2022.03.18.06.23.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 06:23:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/21] util/osdep: Remove some early cruft Date: Fri, 18 Mar 2022 13:23:06 +0000 Message-Id: <20220318132306.3254960-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220318132306.3254960-1-peter.maydell@linaro.org> References: <20220318132306.3254960-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32d (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Andrew Deason The include for statvfs.h has not been needed since all statvfs calls were removed in commit 4a1418e07bdc ("Unbreak large mem support by removing kqemu"). The comment mentioning CONFIG_BSD hasn't made sense since an include for config-host.h was removed in commit aafd75841001 ("util: Clean up includes"). Remove this cruft. Reviewed-by: Peter Maydell Signed-off-by: Andrew Deason Message-id: 20220316035227.3702-4-adeason@sinenomine.net Signed-off-by: Peter Maydell --- util/osdep.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/util/osdep.c b/util/osdep.c index 1825399bcf5..394804d32e1 100644 --- a/util/osdep.c +++ b/util/osdep.c @@ -23,13 +23,6 @@ */ #include "qemu/osdep.h" #include "qapi/error.h" - -/* Needed early for CONFIG_BSD etc. */ - -#ifdef CONFIG_SOLARIS -#include -#endif - #include "qemu-common.h" #include "qemu/cutils.h" #include "qemu/sockets.h"