From patchwork Fri Mar 18 16:08:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 553082 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50E39C43219 for ; Fri, 18 Mar 2022 16:08:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236075AbiCRQJw (ORCPT ); Fri, 18 Mar 2022 12:09:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53072 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235104AbiCRQJu (ORCPT ); Fri, 18 Mar 2022 12:09:50 -0400 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB9328CCEA; Fri, 18 Mar 2022 09:08:31 -0700 (PDT) Received: by mail-ej1-x62c.google.com with SMTP id qa43so17850789ejc.12; Fri, 18 Mar 2022 09:08:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=oYnAnrWU13qc8rQ7MPOxKFwqoXsKN+1WmTS68IkDyt4=; b=IYWICB10auDKADqRkK67j/3pUWIbxXpjkiWVRzQwBQHdSQmqkByK8FtVcNuz6u9Qh0 AcWhGteKEAIFcAQizai26018iUQDciXloTAFzjJcuvC1/h0IieBq6mPy4dwCLCiswDmq StYaWFrDpMigBpbP0FeefigjNzBJ9CNUBqEbMt5WbspJsuKyTk6YY2twm2HoYirvwh6V e6oJ5yVcIhKEOEN8V7IJtHdSWCHhnJTUHTaykVzWO+8hy/8Q632eZsE1GpMEYDPZ1MA/ wzfAVR/YMzpXg3ZKRCF/bcQx+maQ6JYR3YpY7obcLSKdFfkBzcxkFiHKwmPKCudBFOOm ITHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oYnAnrWU13qc8rQ7MPOxKFwqoXsKN+1WmTS68IkDyt4=; b=aV/B6U6X9U3gHAE+0E0Rss3l7lsbUxMgqTzL5Uin6fQ5M04rfio5oOS9cAg2XcBasZ uZ5eqdco1+I47GmcO1AG2KUbBt0Vbl9eUpiMMUqonNF4grzAIHct8mN+FmdCeOvEKaJ9 r8M8tZT6IrlU2TgSuibPcYRE24NhFN1iECDlMC/txLdwRqt5kFnYh0i8YKwWKJsu9Vcd /CaJufd0mrTMuc++q3gqvjHVP2wNrjLhekvNq5hdeEExnk5m0jqaQphClvrl3yep8G4b zIdzD6IltKzk7cESF6GPfkIl6bg9V+M2DsGU/BYWeR91ZyimNTg/xCaE2IaU1JGVsSh9 dU/g== X-Gm-Message-State: AOAM533UAVcYiC7E4XNUd1CSc8zkY3rcO9hGCAtdevJY2qZXm0QvoNkk 05iDnjlvwZ1ZsMk0nNsntOs= X-Google-Smtp-Source: ABdhPJyjiVrkUrzXJNvhN0lLGaJeq0OTV2S+YCR9gl+sNX3dM8BlHFTyqoVx/vXJPzREo/k3simk8w== X-Received: by 2002:a17:906:36ce:b0:6d6:e540:ed65 with SMTP id b14-20020a17090636ce00b006d6e540ed65mr9644625ejc.330.1647619710058; Fri, 18 Mar 2022 09:08:30 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id e9-20020a170906c00900b006d4a45869basm3754118ejz.199.2022.03.18.09.08.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 09:08:29 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 01/16] clk: introduce clk_hw_get_index_of_parent new API Date: Fri, 18 Mar 2022 17:08:12 +0100 Message-Id: <20220318160827.8860-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220318160827.8860-1-ansuelsmth@gmail.com> References: <20220318160827.8860-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Clk can have multiple parents. Some clk may require to get the cached index of other parent that are not current associated with the clk. We have clk_hw_get_parent_index() that returns the index of the current parent but we can't get the index of other parents of the provided clk. Introduce clk_hw_get_index_of_parent() to get the cached index of the parent of the provided clk. This permits a direct access of the internal clk_fetch_parent_index(). Signed-off-by: Ansuel Smith --- drivers/clk/clk.c | 14 ++++++++++++++ include/linux/clk-provider.h | 1 + 2 files changed, 15 insertions(+) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 8de6a22498e7..bdd70a88394c 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -1726,6 +1726,20 @@ int clk_hw_get_parent_index(struct clk_hw *hw) } EXPORT_SYMBOL_GPL(clk_hw_get_parent_index); +/** + * clk_hw_get_index_of_parent - return the index of the parent clock + * @hw: clk_hw associated with the clk being consumed + * @parent: clk_hw of the parent to be fetched the index of + * + * Fetches and returns the index of parent clock provided. + * Returns -EINVAL if the given parent index can't be provided. + */ +int clk_hw_get_index_of_parent(struct clk_hw *hw, const struct clk_hw *parent) +{ + return clk_fetch_parent_index(hw->core, parent->core); +} +EXPORT_SYMBOL_GPL(clk_hw_get_index_of_parent); + /* * Update the orphan status of @core and all its children. */ diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 2faa6f7aa8a8..5708c0b3ef1c 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -1198,6 +1198,7 @@ unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, unsigned int index); +int clk_hw_get_index_of_parent(struct clk_hw *hw, const struct clk_hw *parent); int clk_hw_get_parent_index(struct clk_hw *hw); int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent); unsigned int __clk_get_enable_count(struct clk *clk); From patchwork Fri Mar 18 16:08:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 553081 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EDCFC433F5 for ; Fri, 18 Mar 2022 16:08:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238056AbiCRQJw (ORCPT ); Fri, 18 Mar 2022 12:09:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236846AbiCRQJw (ORCPT ); Fri, 18 Mar 2022 12:09:52 -0400 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B6F874AE34; Fri, 18 Mar 2022 09:08:32 -0700 (PDT) Received: by mail-ej1-x62d.google.com with SMTP id qa43so17850851ejc.12; Fri, 18 Mar 2022 09:08:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8P3wAYvgFlPve71dG0z5aPiI1G8WoaU4vYr3l4vmoOE=; b=i86czUUj48GF/XUBd4oJWgosZdkLhkpsIfS0o0q9ban90irXapDS3ihASlkLccZLVZ vxftBTmrSk1NlL6yjXf4B/FzqXhzxwf+ZJz7zEA05T9pf8nJJVeJtWYHaLCNL8+ZKAqF goBW0CL4ae5dfsVF2/mGpDDmIKja5BhFUh9o/Ligq1ATfufQ+qKrm0M4BeVzOsiYVxS3 kvXhPJg384UydiFZeoaQWvs0Dwu2I8rM7lWnvgcQmlF6BHNhhkF4R9BRhvpDrFz6LgnE O+6HnVE5j4IbXmvRHwCqNnK8NCi6ATn8PWTOIMpBfSHBSWQlzhklOuNy/4LzpyjgrpsP gJow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8P3wAYvgFlPve71dG0z5aPiI1G8WoaU4vYr3l4vmoOE=; b=N4Cge0b1tuAp+CZ5fvcCDsf0qMnAsYF2808bXvCsbs3Xf87OUSYMYjr/broKS9P7Xb gWNsaxAr8g5wj5+qS6XKx7mn6vOte3NBktdB6UyMEFryhi/QVlPKmOJQM2LU5B3ofRFJ I+lP2T5U1fv63ve9nDmS9SwMj4o4jCOiEaOt4tCVUDu5wQWEFY+QSyPbByOIhe3jGS11 3AkhXew0ZzmlsilxhPZRLVU3GnsgfEyxhRd8K9ffbS3RNmLLs08anWE7o5OE+hQgaUWU 6fw8KENf28nQSg5d2uB7/1SkC5JxtezjGpev1iJZN6tkXwfX+mMvCm1niZTGKBDHF7C2 GfLA== X-Gm-Message-State: AOAM531+Y8xC71dx/eS528Pm744++Wa/A+bZWuHNeTSUwO/tiC0D2GyY MKINVSp3RSwqxz46ZlZo28w= X-Google-Smtp-Source: ABdhPJxL7N8UZ0Kslm/zsfSZruSQrN6GVCwekkXlKlbC+ExhJ6RwLyAgMrsRnk6FcrGLGa7kfNAZMw== X-Received: by 2002:a17:906:b052:b0:6ce:88a5:e42a with SMTP id bj18-20020a170906b05200b006ce88a5e42amr9854436ejb.237.1647619711156; Fri, 18 Mar 2022 09:08:31 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id e9-20020a170906c00900b006d4a45869basm3754118ejz.199.2022.03.18.09.08.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 09:08:30 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 02/16] clk: qcom: gcc-ipq806x: skip pxo/cxo fixed clk if already present Date: Fri, 18 Mar 2022 17:08:13 +0100 Message-Id: <20220318160827.8860-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220318160827.8860-1-ansuelsmth@gmail.com> References: <20220318160827.8860-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Skip pxo/cxo clock registration if they are already defined in DTS as fixed clock. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index d6b7adb4be38..27f6d7626abb 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -3061,15 +3062,22 @@ static int gcc_ipq806x_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct regmap *regmap; + struct clk *clk; int ret; - ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000); - if (ret) - return ret; + clk = clk_get(dev, "cxo"); + if (IS_ERR(clk)) { + ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000); + if (ret) + return ret; + } - ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000); - if (ret) - return ret; + clk = clk_get(dev, "pxo"); + if (IS_ERR(clk)) { + ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000); + if (ret) + return ret; + } ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc); if (ret) From patchwork Fri Mar 18 16:08:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 552693 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74098C43217 for ; Fri, 18 Mar 2022 16:08:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238356AbiCRQJx (ORCPT ); Fri, 18 Mar 2022 12:09:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53178 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238185AbiCRQJw (ORCPT ); Fri, 18 Mar 2022 12:09:52 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA85F4FC46; Fri, 18 Mar 2022 09:08:33 -0700 (PDT) Received: by mail-ej1-x635.google.com with SMTP id pv16so18033034ejb.0; Fri, 18 Mar 2022 09:08:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=XhL5PcXPAVYZIaqVjbCyrF3IgCwpUk1BeN4L/hsgGTo=; b=qzZNmheckii7QD5B6iClmT8S/PvmDeu/o1DSZKpegT9SOmdJLN03FPiDEE4+dI1i6L y8OEsCn5zq6gWGNu44Td39d3oEfyRIRAdQuW2hFtACB4ey1XRBtMUIXCEDzQsP91rb5T ysXx3/vrsXll9Ja/ynKboUT64F8mrewZ02PeX9qIu5Oa1E+KJBde83iiBDTYQzlv6nXr quSsnwauwp+x1Kv3IX2u2o9RjCRT4SsSLtIWTrqz67KD4x0hmRyh832KW83anEEiNZSo 6qbNSmg62K6h216Gc94cierMEbIxhRiFHBpiQYGfe5NVrSbyXmgYKy0+zwx7mqvX3UtU oITA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XhL5PcXPAVYZIaqVjbCyrF3IgCwpUk1BeN4L/hsgGTo=; b=QZiLDem4o5pTgrcTxjhh1AN0r1ooJvZU3xbTpYAnGBzYZI9tyWGVVTjjwLF34SHWMM smzLklySoF3q0cBkc7HY40tLKThXdXaNJrpAwO1S1MgGEm40mJaF0CEaxQoqu2zm9shP njLLlzpxtEhKiVS9NtqOgmBIZoZfstH6QNqCJM36qiPKXSfcYFfyX/Dh/WdKb2Lpt8A7 uIU8MK8KiwvH7F9Rz8xbL8OPJWoaK7XtmSoeEVnOrYJCBqpzMEIVNcNaneud7I4BD1tF +OZy1/H1T+ydZvuqOB1oPbJNY/S3mWNBKOGgFv/q20KvKYeHyhJAyO9Cpi6HxLGCa7R5 irLQ== X-Gm-Message-State: AOAM530ivcPCWY1hZKBI/SRbA+L8fPHXP69VKPlvP03lKKghzBmk7h6j 0nr8r5KV+xVSWyBQDvHZ3cY= X-Google-Smtp-Source: ABdhPJzz7S9OaQ0+IgohlMwoZ4xu/sUe6wt2Q7iMdSBrrmc9PPLUjlxOJZ5cITsoF1KKXdkSLJBRpQ== X-Received: by 2002:a17:906:1f11:b0:685:d50e:3bf9 with SMTP id w17-20020a1709061f1100b00685d50e3bf9mr9829780ejj.275.1647619712207; Fri, 18 Mar 2022 09:08:32 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id e9-20020a170906c00900b006d4a45869basm3754118ejz.199.2022.03.18.09.08.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 09:08:31 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 03/16] clk: qcom: gcc-ipq806x: add PXO_SRC in clk table Date: Fri, 18 Mar 2022 17:08:14 +0100 Message-Id: <20220318160827.8860-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220318160827.8860-1-ansuelsmth@gmail.com> References: <20220318160827.8860-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org PXO_SRC is currently defined in the gcc include and referenced in the ipq8064 DTSI. Correctly provide a clk after gcc probe to fix kernel panic if a driver starts to actually use it. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 27f6d7626abb..7271d3afdc89 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -26,6 +26,8 @@ #include "clk-hfpll.h" #include "reset.h" +static struct clk_regmap pxo = { }; + static struct clk_pll pll0 = { .l_reg = 0x30c4, .m_reg = 0x30c8, @@ -2754,6 +2756,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = { }; static struct clk_regmap *gcc_ipq806x_clks[] = { + [PXO_SRC] = NULL, [PLL0] = &pll0.clkr, [PLL0_VOTE] = &pll0_vote, [PLL3] = &pll3.clkr, @@ -3083,6 +3086,10 @@ static int gcc_ipq806x_probe(struct platform_device *pdev) if (ret) return ret; + clk = clk_get(dev, "pxo"); + pxo.hw = *__clk_get_hw(clk); + gcc_ipq806x_clks[PXO_SRC] = &pxo; + regmap = dev_get_regmap(dev, NULL); if (!regmap) return -ENODEV; From patchwork Fri Mar 18 16:08:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 553080 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D319C433EF for ; Fri, 18 Mar 2022 16:08:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238512AbiCRQJ4 (ORCPT ); Fri, 18 Mar 2022 12:09:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53252 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238420AbiCRQJx (ORCPT ); Fri, 18 Mar 2022 12:09:53 -0400 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E918D4AE34; Fri, 18 Mar 2022 09:08:34 -0700 (PDT) Received: by mail-ed1-x52f.google.com with SMTP id w4so10797525edc.7; Fri, 18 Mar 2022 09:08:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8h0dp/sRCWnE/SzxqBhwWtp3OCJwunZ7486W2HMfBko=; b=Wen3GLrBPeCotIbEPWJodN1XTTyhTbJEexnWKAy7jaeGjMMJOZd6AlFY9j8UraoAHr ASkXZotE44o0Cr9yPNsXYUQOGCtw42G0GUgdDgqxL6GYQTGngDOK2e3tBYdU1ZnJSlqm DuLRdGiZVFWY8SQdlEJ/Fb8FvFukes6RpcqQ1BlLaH/oGQEgrl9bSWa5G2JrA7VfgXKE rslHwvz9+kM2IfxqnfjOA5QlUViwb7MV2KqpNDG/epAZEu9/LGh8nza3donxeurTffrp p+gYmaiYgB0CmJqRxglI6qnwQ32I1Q19U9/taI+FrzlPjm4jcwbTrFRLVaKnekLM2aQI Cavw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8h0dp/sRCWnE/SzxqBhwWtp3OCJwunZ7486W2HMfBko=; b=3qP6h4hnqgSLArD/8LZsV3gLy8sKq6MVxE4vWmyxKNX0xZelsHHzfhyesTw5LxL+Yz qMX6SrWCjWY6UlV924TxjTuqRS1UlY9T3oY5pf4VglZTUCh299GfHzMgc9zf6rRzGrO7 8ZzfHsUEltsPjxTxwQUv6/uGR8V7NxwpPx2AtJ2CC1nI7Cf1Eqe9akWiJciAwdtws4cT RvrHJv1zL6GhNY/6LJ2NBUkDyKd00WvCr0o2u0HChgFsGKaBFK2D1osFCIMH0bBHbbCM /uo/NVPvJAKhGUYjlfS/pqXdVzLZkwW60m2LOs9J8GXKGAnbUt63vff0S5oCI/uYycu+ YDkg== X-Gm-Message-State: AOAM532KIDINqKa1J2Diyx7vtRq/0MtNhJaNJzSbpjj0QBjC9hCnd3Eu v2CuC8DrYaic7s6LOp04je+9yo4YKrE= X-Google-Smtp-Source: ABdhPJx7trjKAv2zwSvRNB00Gs8Z5nESlKG2+jmEeDulGrr6zLYqKg+gaNtuw/+6TNxoPV6XWYoqPQ== X-Received: by 2002:a05:6402:27ce:b0:416:aff4:86c1 with SMTP id c14-20020a05640227ce00b00416aff486c1mr10000463ede.339.1647619713359; Fri, 18 Mar 2022 09:08:33 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id e9-20020a170906c00900b006d4a45869basm3754118ejz.199.2022.03.18.09.08.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 09:08:33 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 04/16] clk: qcom: clk-hfpll: use poll_timeout macro Date: Fri, 18 Mar 2022 17:08:15 +0100 Message-Id: <20220318160827.8860-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220318160827.8860-1-ansuelsmth@gmail.com> References: <20220318160827.8860-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Use regmap_read_poll_timeout macro instead of do-while structure. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/clk-hfpll.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/clk-hfpll.c b/drivers/clk/qcom/clk-hfpll.c index e847d586a73a..a4e347eb4d4d 100644 --- a/drivers/clk/qcom/clk-hfpll.c +++ b/drivers/clk/qcom/clk-hfpll.c @@ -12,6 +12,8 @@ #include "clk-regmap.h" #include "clk-hfpll.h" +#define HFPLL_BUSY_WAIT_TIMEOUT 100 + #define PLL_OUTCTRL BIT(0) #define PLL_BYPASSNL BIT(1) #define PLL_RESET_N BIT(2) @@ -72,13 +74,12 @@ static void __clk_hfpll_enable(struct clk_hw *hw) regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N); /* Wait for PLL to lock. */ - if (hd->status_reg) { - do { - regmap_read(regmap, hd->status_reg, &val); - } while (!(val & BIT(hd->lock_bit))); - } else { + if (hd->status_reg) + regmap_read_poll_timeout(regmap, hd->status_reg, val, + !(val & BIT(hd->lock_bit)), USEC_PER_MSEC * 2, + HFPLL_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC); + else udelay(60); - } /* Enable PLL output. */ regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL); From patchwork Fri Mar 18 16:08:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 552692 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21561C43217 for ; Fri, 18 Mar 2022 16:08:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238535AbiCRQJ6 (ORCPT ); Fri, 18 Mar 2022 12:09:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53336 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238452AbiCRQJy (ORCPT ); Fri, 18 Mar 2022 12:09:54 -0400 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DF8B34FC46; Fri, 18 Mar 2022 09:08:35 -0700 (PDT) Received: by mail-ej1-x62d.google.com with SMTP id ja24so12523704ejc.11; Fri, 18 Mar 2022 09:08:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=KJy+bVD9Yq3kRrz9Gx7NWpfnxrb/beBV0JaHxbyWaTA=; b=nFRf8ahYGpA1x0VacaTigxdCKWLvbB58VsYm2jh0AtNZyxcuI/Vdwu8jNvyk6YGTxW 3WaBMCWYBw2rW0BZ4e25aaMEjD/BNhRIS6WnId8S0sTK0LNt6Yuno4VcrobyKTrcmvHf xbeX1Xn90+y2gsgzfGke4tdifbrCFfaG+MCP92Sj987N2Tio5cZnsASrWwQGGYA+tmni qpkLIVfNgWgm/F84j93LccOBhtUvIMKFa2OIDNSEFDJmVCxpWGY0Aargg4R2aGU0Bs8U 3LdO5MO+NY49KWe9welKxidfZX7TDQD8pDn2s1gsaiIN3qWrf7sHgSwDuzUdzOIIwvTC yCZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KJy+bVD9Yq3kRrz9Gx7NWpfnxrb/beBV0JaHxbyWaTA=; b=4FeLuV1FzXwjUM/T1Aozd5wnTSJxEWx7WOiR4m/WkJi3MKsW4i0CCdgmDxkMvy4BXG KQSXDvaSHr6gQLSPo+r3crUlhXakZqeU0QnK6EFnAAGQqsuGwPyhY+KLjMcO2G6fbdNS +OL+pAA0PZRbTPd+1EGeQOsGj6YGmr36jhaYwRBS6VjU33e9SlNtJzxdc99vSZaNU0fs PoK3rHgJnz2r+yQg2Po5L4CCSwBWLM+FVSGoP5RfrSeEt6k2x4ajZc4oO8Lp/vhk8KOV 6uSEQ5yVkpGMWV+qdrGPqYnq/cp7s7mqLr0u5u2m6z/HLQt0h9x7AH+1cikGW6KOnpw3 ukyg== X-Gm-Message-State: AOAM533msziJARA/j8rw4XkfoH0pF8RCj9HuyfEvYD7dVYxHS578wkQL xe8mlXPCQyvMobDO8j9kvcM= X-Google-Smtp-Source: ABdhPJy9nmoIz+paAY/jLeL0eZrAk6Bhll0kYEG6X+zp+M2E84b/Q8etgY/8YkQoKm+D4ze0bGg0CA== X-Received: by 2002:a17:906:6547:b0:6bd:e2ad:8c82 with SMTP id u7-20020a170906654700b006bde2ad8c82mr9186558ejn.693.1647619714335; Fri, 18 Mar 2022 09:08:34 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id e9-20020a170906c00900b006d4a45869basm3754118ejz.199.2022.03.18.09.08.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 09:08:34 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 05/16] clk: qcom: kpss-xcc: convert to parent data API Date: Fri, 18 Mar 2022 17:08:16 +0100 Message-Id: <20220318160827.8860-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220318160827.8860-1-ansuelsmth@gmail.com> References: <20220318160827.8860-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the driver to parent data API. From the Documentation pll8_vote and pxo should be declared in the DTS so fw_name can be used instead of parent_names. Name is still used to save regression on old definition. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/kpss-xcc.c | 25 ++++++++----------------- 1 file changed, 8 insertions(+), 17 deletions(-) diff --git a/drivers/clk/qcom/kpss-xcc.c b/drivers/clk/qcom/kpss-xcc.c index 4fec1f9142b8..347f70e9f5fe 100644 --- a/drivers/clk/qcom/kpss-xcc.c +++ b/drivers/clk/qcom/kpss-xcc.c @@ -12,9 +12,9 @@ #include #include -static const char *aux_parents[] = { - "pll8_vote", - "pxo", +static const struct clk_parent_data aux_parents[] = { + { .name = "pll8_vote", .fw_name = "pll8_vote" }, + { .name = "pxo", .fw_name = "pxo" }, }; static unsigned int aux_parent_map[] = { @@ -32,8 +32,8 @@ MODULE_DEVICE_TABLE(of, kpss_xcc_match_table); static int kpss_xcc_driver_probe(struct platform_device *pdev) { const struct of_device_id *id; - struct clk *clk; void __iomem *base; + struct clk_hw *hw; const char *name; id = of_match_device(kpss_xcc_match_table, &pdev->dev); @@ -55,24 +55,15 @@ static int kpss_xcc_driver_probe(struct platform_device *pdev) base += 0x28; } - clk = clk_register_mux_table(&pdev->dev, name, aux_parents, - ARRAY_SIZE(aux_parents), 0, base, 0, 0x3, - 0, aux_parent_map, NULL); + hw = __devm_clk_hw_register_mux(&pdev->dev, NULL, name, ARRAY_SIZE(aux_parents), + NULL, NULL, aux_parents, 0, base, 0, 0x3, + 0, aux_parent_map, NULL); - platform_set_drvdata(pdev, clk); - - return PTR_ERR_OR_ZERO(clk); -} - -static int kpss_xcc_driver_remove(struct platform_device *pdev) -{ - clk_unregister_mux(platform_get_drvdata(pdev)); - return 0; + return PTR_ERR_OR_ZERO(hw); } static struct platform_driver kpss_xcc_driver = { .probe = kpss_xcc_driver_probe, - .remove = kpss_xcc_driver_remove, .driver = { .name = "kpss-xcc", .of_match_table = kpss_xcc_match_table, From patchwork Fri Mar 18 16:08:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 553079 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7638C433EF for ; Fri, 18 Mar 2022 16:08:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233639AbiCRQKO (ORCPT ); Fri, 18 Mar 2022 12:10:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53442 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238501AbiCRQJ4 (ORCPT ); Fri, 18 Mar 2022 12:09:56 -0400 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0DFC78CCEF; Fri, 18 Mar 2022 09:08:36 -0700 (PDT) Received: by mail-ed1-x533.google.com with SMTP id z92so9854222ede.13; Fri, 18 Mar 2022 09:08:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=fDLuIDyRCuRCH3Dc/gWWNAl91bj4g20Fwm4jwXMbE5A=; b=MduW0K6yHWbOsRruvibz3UTGJImXF0ExFolwO2lNWVKyIBt7jgF+l2QJsT41ebVEPI IVoAf1g1PCOJqiW4eRtatPzMW4SwAa38vWHIl9z5MkVQiCtbNIO/VETa6se47BBmic7y ZLcmZvHg4zM/C2ZL9lM3+sRrTbmLHklIxD3jUXU0qt3vbftwyB/1W+O3FwQZHiEL5ua6 dFLWsLEeKV5omikVBUoR4rP6PD2JsJ8La3eAGxCzawQ4yv9I8cnA4RwFEVaWpoRKobOg /L2h+S+jG/F5b4LQ+dNbjo9I0VUAFFVWD+w1n45znA5RZ0Z4CihD+4F4g2bTDFztRTMQ KTlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fDLuIDyRCuRCH3Dc/gWWNAl91bj4g20Fwm4jwXMbE5A=; b=AqdWTyERPcR8AE7RvMupXOatIyLKLguSsPXZaG2Tyg2dJw7iz5NXvSu6qm2ewGyBnV W+/DwTmqMkG5Guw4sgZg0ofrYT5htUU0v0mNrlg7HLmCrvNSUh8M0wz+/jVLpMFCLwhK Nb6UD+X6sk83/qOU8okoH9qlvwmUuip+PjaG/lgrnZ+GOFoUuyXTGDf1qcz/50Bi4lPW ngUw1pF/PCB8TL0nYEyFNODHZJ5IkO0f/djgS1/UfEMGv+6wSQ4LnCfOkO0m54zX54JS zH+K8+eo0CrbFoJjgmqHf4X3A7DTXf9CprRsO9M4KpMI6GQ8doIpidV+d4OhKcPqg1XZ cOFg== X-Gm-Message-State: AOAM533yHT/erAjHzGiIBmYP3z8tG1rtLUHNw8D58TuOTs+xxAEhmZlL BpGFkJpUktIK8xZvmq8II6g= X-Google-Smtp-Source: ABdhPJwIDAuBvS9AYUlCGpqVsISVE7aKrNYqxs51mhuj+MA5Dhb/Xs39RkotESnqjHahIUYIT1Aerw== X-Received: by 2002:a05:6402:1906:b0:418:ff14:62b8 with SMTP id e6-20020a056402190600b00418ff1462b8mr7591325edz.40.1647619715322; Fri, 18 Mar 2022 09:08:35 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id e9-20020a170906c00900b006d4a45869basm3754118ejz.199.2022.03.18.09.08.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 09:08:34 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 06/16] clk: qcom: clk-krait: unlock spin after mux completion Date: Fri, 18 Mar 2022 17:08:17 +0100 Message-Id: <20220318160827.8860-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220318160827.8860-1-ansuelsmth@gmail.com> References: <20220318160827.8860-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Unlock spinlock after the mux switch is completed to prevent any corner case of mux request while the switch still needs to be done. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/clk-krait.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c index 59f1af415b58..e447fcc3806d 100644 --- a/drivers/clk/qcom/clk-krait.c +++ b/drivers/clk/qcom/clk-krait.c @@ -32,11 +32,12 @@ static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel) regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT); } krait_set_l2_indirect_reg(mux->offset, regval); - spin_unlock_irqrestore(&krait_clock_reg_lock, flags); /* Wait for switch to complete. */ mb(); udelay(1); + + spin_unlock_irqrestore(&krait_clock_reg_lock, flags); } static int krait_mux_set_parent(struct clk_hw *hw, u8 index) From patchwork Fri Mar 18 16:08:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 552691 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DC0EC4332F for ; Fri, 18 Mar 2022 16:09:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238644AbiCRQKP (ORCPT ); Fri, 18 Mar 2022 12:10:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238533AbiCRQJ5 (ORCPT ); Fri, 18 Mar 2022 12:09:57 -0400 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F40FC4FC46; Fri, 18 Mar 2022 09:08:37 -0700 (PDT) Received: by mail-ed1-x52d.google.com with SMTP id x34so9642446ede.8; Fri, 18 Mar 2022 09:08:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=uKLqUE0HqMblkYxTDEoLkraH8fYkNKsZ80vlgdu8msQ=; b=RufIWNE/YK0iS48SJ2ZYrw2MT1i03P+usPEkru8m+4u/RVv1Diwub+Wo+ikhTcWr5D Cl6yBI/JYT8m2JncckCo20qU+HN41iLIjytTKiPmvIxIoPpnHuhsPXpMxOuLptn8L2G0 YsSFEjq9x1zN1uv+TlOHU2JL7hCs7Ee0vdOV7BBgFNPn3VbgH3jHIq7YRkSGHxdF/c3l LljjlKjrqU7ukX5hyD33oYGWlCNQy4EY2dQixqq4Zlk2OPQqy5AZmepJ/NDb9Oe5m0SH IWhY95pqKiOkg2VDjUNiM0LibhRpLmSriFGxBTvad7WFPsUpBU+TaZtU1sLATXP6umfo EUVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uKLqUE0HqMblkYxTDEoLkraH8fYkNKsZ80vlgdu8msQ=; b=rK4UuqLtcT9OAhPIZ8Tqy7gH+AJIsQdx4Nz0+a0p6Wzyp1npymymoRLjhwWRFG2bZ+ qdyP+8yDl6YCzaRHvbN1hu76jGrJWJpfHXN/Tm9dUix3yjQKoiWivIW/YfroxH8d8h6D pE/rD/uhardANgrG7OIGqx9hQFRiK5qkXy7pcfeFaij6fbt9JrU3/ZRs5iQQLHk6oU1e MjFZGBJxu9YMW6Jjg+vQhCANHx5eEzq6X43247y8AKsxwmA7sbRXpk19AL9I8tV7+zDw SBKjZukR6S/fE31tsqoH8lA6jcCPVfGpNZlX1S63kZm9xdZurPbQyvV1Z3di2xcnCEqE zo2w== X-Gm-Message-State: AOAM533NqRqenpCK1z+CxdzvMSrzeXT15bU6+oSo5LHm8usWL+Cy922Q 69qeHt6gEubFDpbK1RouwlE= X-Google-Smtp-Source: ABdhPJxsL05n0fvaqhEOnEtKNa3kuV1zQUKIgI36M9DAjeWdtThBRpLXiaKwp19iUHf4uWjrz2MrjQ== X-Received: by 2002:a05:6402:350b:b0:419:1c11:23ed with SMTP id b11-20020a056402350b00b004191c1123edmr358545edd.8.1647619716333; Fri, 18 Mar 2022 09:08:36 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id e9-20020a170906c00900b006d4a45869basm3754118ejz.199.2022.03.18.09.08.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 09:08:36 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 07/16] clk: qcom: clk-krait: add hw_parent check for div2_round_rate Date: Fri, 18 Mar 2022 17:08:18 +0100 Message-Id: <20220318160827.8860-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220318160827.8860-1-ansuelsmth@gmail.com> References: <20220318160827.8860-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Check if hw_parent is present before calculating the round_rate to prevent kernel panic. On error -EINVAL is reported. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/clk-krait.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c index e447fcc3806d..b6b7650dbf15 100644 --- a/drivers/clk/qcom/clk-krait.c +++ b/drivers/clk/qcom/clk-krait.c @@ -80,7 +80,12 @@ EXPORT_SYMBOL_GPL(krait_mux_clk_ops); static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { - *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2); + struct clk_hw *hw_parent = clk_hw_get_parent(hw); + + if (!hw_parent) + return -EINVAL; + + *parent_rate = clk_hw_round_rate(hw_parent, rate * 2); return DIV_ROUND_UP(*parent_rate, 2); } From patchwork Fri Mar 18 16:08:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 553078 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C2E8C43217 for ; Fri, 18 Mar 2022 16:09:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238664AbiCRQKR (ORCPT ); Fri, 18 Mar 2022 12:10:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238538AbiCRQJ6 (ORCPT ); Fri, 18 Mar 2022 12:09:58 -0400 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 091758CCEE; Fri, 18 Mar 2022 09:08:39 -0700 (PDT) Received: by mail-ej1-x62a.google.com with SMTP id r13so17938695ejd.5; Fri, 18 Mar 2022 09:08:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1tacB+H58ZcVKBVcWE3u+TMM2y65iIDEoWk8hI94hWs=; b=S8VdB15TP2RZH8tklMdLLDLT4qys66EcWGO5AmvsBftJ+w6pcQF9OUhn4Oh/hRGEmg BCj/QTuVAP5L1XRHEWuWGRvWIufvGdd1deyJ1I9ca7e1sHrlzeXnGkJHdEddDYk4k41w Ifr5YcZKThHCIIxECO1JmkRjlF9RfdNIEbZcuTtaYczOeBkq+Q22692xRXHsCVYoNBEb Tybm8gpiZky6HTx8qDALaqIhRF7/XP3m6jRh4g3GPYqnReJOD0kAwXY8+2KGCQeWi6H3 L+egDM9XLA84hfoom43IPG9FmhJ7Ci+Vo9GK10dQV8dEJS07DvEbg+hDYG43aJcxYCGp dddg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1tacB+H58ZcVKBVcWE3u+TMM2y65iIDEoWk8hI94hWs=; b=yVeKQ2s+V/QuAjsIsu+WX2Ho9TJkGTeyUO+qWU7v48z+WRbQkY6XKxR2bqXrxXju0q NUkX07XqI96+XerJSqkZwOYeETMMpLRxPtjaT8Ib2M9unAHUcoE7OFHsMEv0DhMRfbsY 4JW+LkL8G1sdbZ6ymgdRHTNN5Unc4owvxA6a/IIo7h9I6lO3r7jDCwFtEiADJHG1n9Co hF6a2ocdB0ROHpy9Z/Wxl2xFofJ03QpFgBEKjhIDA+zq6heSfhrNtTd8DuE6YyhduveV Y5WiAR4Sxy88qZfrrh9UpBS3O40lLYRHO3Z6MQmMZmnYT0MGfwJPGumVj3yJ5MdlewQc bT1Q== X-Gm-Message-State: AOAM531SeMzgk+I4jQKUDRGjApJMK1TjWOuZoxWwBKo7SnJm3qquyh1+ tifRBDzVk+J2km+pUulhUHA= X-Google-Smtp-Source: ABdhPJyjbdYbskM3iuqrC1qVTEmng+sR1PNqK/RxD1xOs583/qnFJu8+Fw2FSUNGFBDghEMh77ws+g== X-Received: by 2002:a17:907:8a04:b0:6cd:2902:8db3 with SMTP id sc4-20020a1709078a0400b006cd29028db3mr9442670ejc.530.1647619717321; Fri, 18 Mar 2022 09:08:37 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id e9-20020a170906c00900b006d4a45869basm3754118ejz.199.2022.03.18.09.08.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 09:08:37 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 08/16] clk: qcom: krait-cc: convert to parent_data API Date: Fri, 18 Mar 2022 17:08:19 +0100 Message-Id: <20220318160827.8860-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220318160827.8860-1-ansuelsmth@gmail.com> References: <20220318160827.8860-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Modernize the krait-cc driver to parent-data API and refactor to drop any use of clk_names. From Documentation all the required clocks should be declared in DTS so fw_name can be correctly used to get the parents for all the muxes. Name is also declared to save compatibility with old implementation. Also fix the parent order of the sec_mux that was wrong and incorrectly report the wrong safe parent if it's not hardcoded. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/krait-cc.c | 126 +++++++++++++++++++----------------- 1 file changed, 66 insertions(+), 60 deletions(-) diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index 4d4b657d33c3..645ad9e8dd73 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -69,21 +69,22 @@ static int krait_notifier_register(struct device *dev, struct clk *clk, return ret; } -static int +static struct clk * krait_add_div(struct device *dev, int id, const char *s, unsigned int offset) { struct krait_div2_clk *div; + static struct clk_parent_data p_data[1]; struct clk_init_data init = { - .num_parents = 1, + .num_parents = ARRAY_SIZE(p_data), .ops = &krait_div2_clk_ops, .flags = CLK_SET_RATE_PARENT, }; - const char *p_names[1]; struct clk *clk; + char *parent_name; div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); if (!div) - return -ENOMEM; + return ERR_PTR(-ENOMEM); div->width = 2; div->shift = 6; @@ -93,43 +94,49 @@ krait_add_div(struct device *dev, int id, const char *s, unsigned int offset) init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s); if (!init.name) - return -ENOMEM; + return ERR_PTR(-ENOMEM); - init.parent_names = p_names; - p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s); - if (!p_names[0]) { - kfree(init.name); - return -ENOMEM; + init.parent_data = p_data; + parent_name = kasprintf(GFP_KERNEL, "hfpll%s", s); + if (!parent_name) { + clk = ERR_PTR(-ENOMEM); + goto err_parent_name; } + p_data[0].fw_name = parent_name; + p_data[0].name = parent_name; + clk = devm_clk_register(dev, &div->hw); - kfree(p_names[0]); + + kfree(parent_name); +err_parent_name: kfree(init.name); - return PTR_ERR_OR_ZERO(clk); + return clk; } -static int +static struct clk * krait_add_sec_mux(struct device *dev, int id, const char *s, unsigned int offset, bool unique_aux) { int ret; struct krait_mux_clk *mux; - static const char *sec_mux_list[] = { - "acpu_aux", - "qsb", + static struct clk_parent_data sec_mux_list[2] = { + { .name = "qsb", .fw_name = "qsb" }, + {}, }; struct clk_init_data init = { - .parent_names = sec_mux_list, + .parent_data = sec_mux_list, .num_parents = ARRAY_SIZE(sec_mux_list), .ops = &krait_mux_clk_ops, .flags = CLK_SET_RATE_PARENT, }; struct clk *clk; + char *parent_name; mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); if (!mux) - return -ENOMEM; + return ERR_PTR(-ENOMEM); mux->offset = offset; mux->lpl = id >= 0; @@ -141,44 +148,51 @@ krait_add_sec_mux(struct device *dev, int id, const char *s, init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); if (!init.name) - return -ENOMEM; + return ERR_PTR(-ENOMEM); if (unique_aux) { - sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s); - if (!sec_mux_list[0]) { + parent_name = kasprintf(GFP_KERNEL, "acpu%s_aux", s); + if (!parent_name) { clk = ERR_PTR(-ENOMEM); goto err_aux; } + sec_mux_list[1].fw_name = parent_name; + sec_mux_list[1].name = parent_name; + } else { + sec_mux_list[1].name = "apu_aux"; } clk = devm_clk_register(dev, &mux->hw); + if (IS_ERR(clk)) + goto err_clk; ret = krait_notifier_register(dev, clk, mux); if (ret) - goto unique_aux; + clk = ERR_PTR(ret); -unique_aux: +err_clk: if (unique_aux) - kfree(sec_mux_list[0]); + kfree(parent_name); err_aux: kfree(init.name); - return PTR_ERR_OR_ZERO(clk); + return clk; } static struct clk * -krait_add_pri_mux(struct device *dev, int id, const char *s, - unsigned int offset) +krait_add_pri_mux(struct device *dev, struct clk *hfpll_div, struct clk *sec_mux, + int id, const char *s, unsigned int offset) { int ret; struct krait_mux_clk *mux; - const char *p_names[3]; + static struct clk_parent_data p_data[3]; struct clk_init_data init = { - .parent_names = p_names, - .num_parents = ARRAY_SIZE(p_names), + .parent_data = p_data, + .num_parents = ARRAY_SIZE(p_data), .ops = &krait_mux_clk_ops, .flags = CLK_SET_RATE_PARENT, }; struct clk *clk; + char *hfpll_name; mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); if (!mux) @@ -196,36 +210,29 @@ krait_add_pri_mux(struct device *dev, int id, const char *s, if (!init.name) return ERR_PTR(-ENOMEM); - p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s); - if (!p_names[0]) { + hfpll_name = kasprintf(GFP_KERNEL, "hfpll%s", s); + if (!hfpll_name) { clk = ERR_PTR(-ENOMEM); - goto err_p0; + goto err_hfpll; } - p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s); - if (!p_names[1]) { - clk = ERR_PTR(-ENOMEM); - goto err_p1; - } + p_data[0].fw_name = hfpll_name; + p_data[0].name = hfpll_name; - p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); - if (!p_names[2]) { - clk = ERR_PTR(-ENOMEM); - goto err_p2; - } + p_data[1].hw = __clk_get_hw(hfpll_div); + p_data[2].hw = __clk_get_hw(sec_mux); clk = devm_clk_register(dev, &mux->hw); + if (IS_ERR(clk)) + goto err_clk; ret = krait_notifier_register(dev, clk, mux); if (ret) - goto err_p3; -err_p3: - kfree(p_names[2]); -err_p2: - kfree(p_names[1]); -err_p1: - kfree(p_names[0]); -err_p0: + clk = ERR_PTR(ret); + +err_clk: + kfree(hfpll_name); +err_hfpll: kfree(init.name); return clk; } @@ -233,11 +240,10 @@ krait_add_pri_mux(struct device *dev, int id, const char *s, /* id < 0 for L2, otherwise id == physical CPU number */ static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux) { - int ret; unsigned int offset; void *p = NULL; const char *s; - struct clk *clk; + struct clk *hfpll_div, *sec_mux, *clk; if (id >= 0) { offset = 0x4501 + (0x1000 * id); @@ -249,19 +255,19 @@ static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux) s = "_l2"; } - ret = krait_add_div(dev, id, s, offset); - if (ret) { - clk = ERR_PTR(ret); + hfpll_div = krait_add_div(dev, id, s, offset); + if (IS_ERR(hfpll_div)) { + clk = hfpll_div; goto err; } - ret = krait_add_sec_mux(dev, id, s, offset, unique_aux); - if (ret) { - clk = ERR_PTR(ret); + sec_mux = krait_add_sec_mux(dev, id, s, offset, unique_aux); + if (IS_ERR(sec_mux)) { + clk = sec_mux; goto err; } - clk = krait_add_pri_mux(dev, id, s, offset); + clk = krait_add_pri_mux(dev, hfpll_div, sec_mux, id, s, offset); err: kfree(p); return clk; From patchwork Fri Mar 18 16:08:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 552690 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE287C4321E for ; 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[93.42.69.170]) by smtp.googlemail.com with ESMTPSA id e9-20020a170906c00900b006d4a45869basm3754118ejz.199.2022.03.18.09.08.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 09:08:38 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 09/16] clk: qcom: krait-cc: drop pr_info and register qsb only if needed Date: Fri, 18 Mar 2022 17:08:20 +0100 Message-Id: <20220318160827.8860-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220318160827.8860-1-ansuelsmth@gmail.com> References: <20220318160827.8860-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Replace pr_info() with dev_info() to provide better diagnostics. Register qsb fixed clk only if it's not declared in DTS. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/krait-cc.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index 645ad9e8dd73..e9508e3104ea 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -308,7 +308,9 @@ static int krait_cc_probe(struct platform_device *pdev) return -ENODEV; /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */ - clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); + if (IS_ERR(clk_get(dev, "qsb"))) + clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); + if (IS_ERR(clk)) return PTR_ERR(clk); @@ -363,25 +365,25 @@ static int krait_cc_probe(struct platform_device *pdev) cur_rate = clk_get_rate(l2_pri_mux_clk); aux_rate = 384000000; if (cur_rate == 1) { - pr_info("L2 @ QSB rate. Forcing new rate.\n"); + dev_info(dev, "L2 @ QSB rate. Forcing new rate.\n"); cur_rate = aux_rate; } clk_set_rate(l2_pri_mux_clk, aux_rate); clk_set_rate(l2_pri_mux_clk, 2); clk_set_rate(l2_pri_mux_clk, cur_rate); - pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000); + dev_info(dev, "L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000); for_each_possible_cpu(cpu) { clk = clks[cpu]; cur_rate = clk_get_rate(clk); if (cur_rate == 1) { - pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu); + dev_info(dev, "CPU%d @ QSB rate. Forcing new rate.\n", cpu); cur_rate = aux_rate; } clk_set_rate(clk, aux_rate); clk_set_rate(clk, 2); clk_set_rate(clk, cur_rate); - pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000); + dev_info(dev, "CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000); } of_clk_add_provider(dev->of_node, krait_of_get, clks); From patchwork Fri Mar 18 16:08:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 553077 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4605DC433F5 for ; Fri, 18 Mar 2022 16:09:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238667AbiCRQKU (ORCPT ); Fri, 18 Mar 2022 12:10:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53462 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238607AbiCRQKO (ORCPT ); Fri, 18 Mar 2022 12:10:14 -0400 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 436398CCFD; Fri, 18 Mar 2022 09:08:41 -0700 (PDT) Received: by mail-ej1-x631.google.com with SMTP id j15so3838706eje.9; Fri, 18 Mar 2022 09:08:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=HxwJ/rmGXQIKgHQmjTVr7v/2TGpe+xuVVbkVjt0eYLU=; b=PbpFHnlhHwJ1PrE15oOIJDeMBczuvBHO8xJQcgpSliVes/4h26WJHDNrxkDPBbqsig 9uz/pPofF6Gc7vkP6XONfbmZuTa4m1stb7RGw+pgP5qaEvSXhvQYqxFt2rj7Fw/999nk Cu03MaNqW8mx8c/zsj2BZuMq8buYeksMlRKi6fumhgIGOkWkAIXKMOgDUh7h0AWaiiox mMM/DQQtGZieHep9VuXUDkIHv6VeRUIFFqJU0hjdItW0lSLnY8kIOaFdfjDohsvyeowK ZDR+65MeoL89FC160Sb4nrxLipMx9ctNwiCfo4t5+4P9B6PALxiLhacFpaaKiiNKqc37 vbeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HxwJ/rmGXQIKgHQmjTVr7v/2TGpe+xuVVbkVjt0eYLU=; b=N45GvyCX/gmmqigv3PAz/Y5pdvxob6KZFkVJZiN9VM/5mn+tEvtmNdvSL3zdqHMwat CX5PM/qccKM2hmOLjMJN2bEWgyCq0hX8joicp1i+wbaGyS5yemHxZZnoziJdCzjA7mmP ASiHya80N1ZPINlZfMAFNAGClRnBXEFDPicggv63xoCG5/bHVT9dV2kdx+x101w9dxeJ SPtVPDBMmbWbjmHRxEXdY+aZwhfO9+KWNUzA2ugtsUUbcGCAUIay6ljaLrEl4RrclQPd q8nRdi104P12ER2J/eQtbd1JUTkoZ5hTeGxpYcx76h/R1OZHosgUbh4KEM87nbDz3qwK 4Jyw== X-Gm-Message-State: AOAM531UcNpBSclsQ6/8X9q2iRolc8Xs4T4b1b20sMSD0K5N1sjolGkP e3IBODc+Pf4rJD5qcGmwjkA= X-Google-Smtp-Source: ABdhPJydW1ocXPo0I+XrzjEOy220muUYxXLLxTR/Xh2npTCUP0z9NSimx0XN1JvEzwmvNnN7/SX1Mg== X-Received: by 2002:a17:907:72ce:b0:6db:aed5:833e with SMTP id du14-20020a17090772ce00b006dbaed5833emr9510378ejc.420.1647619719430; Fri, 18 Mar 2022 09:08:39 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id e9-20020a170906c00900b006d4a45869basm3754118ejz.199.2022.03.18.09.08.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 09:08:39 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 10/16] clk: qcom: krait-cc: drop hardcoded safe_sel Date: Fri, 18 Mar 2022 17:08:21 +0100 Message-Id: <20220318160827.8860-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220318160827.8860-1-ansuelsmth@gmail.com> References: <20220318160827.8860-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Drop hardcoded safe_sel definition and use helper to correctly calculate it. We assume qsb clk is always present as it should be declared in DTS per Documentation and in the absence of that, it's declared as a fixed clk. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/krait-cc.c | 40 +++++++++++++++++++++++++------------ 1 file changed, 27 insertions(+), 13 deletions(-) diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index e9508e3104ea..5f98ee1c3681 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -26,6 +26,17 @@ static unsigned int pri_mux_map[] = { 0, }; +static u8 krait_get_mux_sel(struct krait_mux_clk *mux, struct clk *safe_clk) +{ + struct clk_hw *safe_hw = __clk_get_hw(safe_clk); + + /* + * We can ignore errors from clk_hw_get_index_of_parent() + * as we create these parents in this driver. + */ + return clk_hw_get_index_of_parent(&mux->hw, safe_hw); +} + /* * Notifier function for switching the muxes to safe parent * while the hfpll is getting reprogrammed. @@ -116,8 +127,8 @@ krait_add_div(struct device *dev, int id, const char *s, unsigned int offset) } static struct clk * -krait_add_sec_mux(struct device *dev, int id, const char *s, - unsigned int offset, bool unique_aux) +krait_add_sec_mux(struct device *dev, struct clk *qsb, int id, + const char *s, unsigned int offset, bool unique_aux) { int ret; struct krait_mux_clk *mux; @@ -144,7 +155,6 @@ krait_add_sec_mux(struct device *dev, int id, const char *s, mux->shift = 2; mux->parent_map = sec_mux_map; mux->hw.init = &init; - mux->safe_sel = 0; init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); if (!init.name) @@ -166,6 +176,7 @@ krait_add_sec_mux(struct device *dev, int id, const char *s, if (IS_ERR(clk)) goto err_clk; + mux->safe_sel = krait_get_mux_sel(mux, qsb); ret = krait_notifier_register(dev, clk, mux); if (ret) clk = ERR_PTR(ret); @@ -204,7 +215,6 @@ krait_add_pri_mux(struct device *dev, struct clk *hfpll_div, struct clk *sec_mux mux->lpl = id >= 0; mux->parent_map = pri_mux_map; mux->hw.init = &init; - mux->safe_sel = 2; init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s); if (!init.name) @@ -226,6 +236,7 @@ krait_add_pri_mux(struct device *dev, struct clk *hfpll_div, struct clk *sec_mux if (IS_ERR(clk)) goto err_clk; + mux->safe_sel = krait_get_mux_sel(mux, sec_mux); ret = krait_notifier_register(dev, clk, mux); if (ret) clk = ERR_PTR(ret); @@ -238,7 +249,9 @@ krait_add_pri_mux(struct device *dev, struct clk *hfpll_div, struct clk *sec_mux } /* id < 0 for L2, otherwise id == physical CPU number */ -static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux) +static struct clk * +krait_add_clks(struct device *dev, struct clk *qsb, int id, + bool unique_aux) { unsigned int offset; void *p = NULL; @@ -261,7 +274,7 @@ static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux) goto err; } - sec_mux = krait_add_sec_mux(dev, id, s, offset, unique_aux); + sec_mux = krait_add_sec_mux(dev, qsb, id, s, offset, unique_aux); if (IS_ERR(sec_mux)) { clk = sec_mux; goto err; @@ -301,18 +314,19 @@ static int krait_cc_probe(struct platform_device *pdev) int cpu; struct clk *clk; struct clk **clks; - struct clk *l2_pri_mux_clk; + struct clk *l2_pri_mux_clk, *qsb; id = of_match_device(krait_cc_match_table, dev); if (!id) return -ENODEV; /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */ - if (IS_ERR(clk_get(dev, "qsb"))) - clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); + qsb = clk_get(dev, "qsb"); + if (IS_ERR(qsb)) + qsb = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); - if (IS_ERR(clk)) - return PTR_ERR(clk); + if (IS_ERR(qsb)) + return PTR_ERR(qsb); if (!id->data) { clk = clk_register_fixed_factor(dev, "acpu_aux", @@ -327,13 +341,13 @@ static int krait_cc_probe(struct platform_device *pdev) return -ENOMEM; for_each_possible_cpu(cpu) { - clk = krait_add_clks(dev, cpu, id->data); + clk = krait_add_clks(dev, qsb, cpu, id->data); if (IS_ERR(clk)) return PTR_ERR(clk); clks[cpu] = clk; } - l2_pri_mux_clk = krait_add_clks(dev, -1, id->data); + l2_pri_mux_clk = krait_add_clks(dev, qsb, -1, id->data); if (IS_ERR(l2_pri_mux_clk)) return PTR_ERR(l2_pri_mux_clk); clks[4] = l2_pri_mux_clk; From patchwork Fri Mar 18 16:08:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 552689 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A2B3C3527B for ; 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[93.42.69.170]) by smtp.googlemail.com with ESMTPSA id e9-20020a170906c00900b006d4a45869basm3754118ejz.199.2022.03.18.09.08.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 09:08:40 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 11/16] clk: qcom: krait-cc: force sec_mux to QSB Date: Fri, 18 Mar 2022 17:08:22 +0100 Message-Id: <20220318160827.8860-12-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220318160827.8860-1-ansuelsmth@gmail.com> References: <20220318160827.8860-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Now that we have converted every driver to parent_data, it was notice that the bootloader can't really leave the system in a strange state where l2 or the cpu0/1 can be sourced in a number of ways for example cpu1 sourcing out of qsb, l2 sourcing out of pxo. To correctly reset the mux and the HFPLL force the sec_mux to QSB. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/krait-cc.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index 5f98ee1c3681..299eb4c81d96 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -15,6 +15,8 @@ #include "clk-krait.h" +#define QSB_RATE 1 + static unsigned int sec_mux_map[] = { 2, 0, @@ -181,6 +183,13 @@ krait_add_sec_mux(struct device *dev, struct clk *qsb, int id, if (ret) clk = ERR_PTR(ret); + /* + * Force the sec_mux to be set to QSB rate. + * This is needed to correctly set the parents and + * to later reset mux and HFPLL to a known freq. + */ + clk_set_rate(clk, QSB_RATE); + err_clk: if (unique_aux) kfree(parent_name); @@ -378,7 +387,7 @@ static int krait_cc_probe(struct platform_device *pdev) */ cur_rate = clk_get_rate(l2_pri_mux_clk); aux_rate = 384000000; - if (cur_rate == 1) { + if (cur_rate == QSB_RATE) { dev_info(dev, "L2 @ QSB rate. Forcing new rate.\n"); cur_rate = aux_rate; } @@ -389,7 +398,7 @@ static int krait_cc_probe(struct platform_device *pdev) for_each_possible_cpu(cpu) { clk = clks[cpu]; cur_rate = clk_get_rate(clk); - if (cur_rate == 1) { + if (cur_rate == QSB_RATE) { dev_info(dev, "CPU%d @ QSB rate. Forcing new rate.\n", cpu); cur_rate = aux_rate; } From patchwork Fri Mar 18 16:08:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 553076 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DF51C433F5 for ; Fri, 18 Mar 2022 16:09:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238678AbiCRQK1 (ORCPT ); Fri, 18 Mar 2022 12:10:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238618AbiCRQKO (ORCPT ); Fri, 18 Mar 2022 12:10:14 -0400 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 86BF8245B2; Fri, 18 Mar 2022 09:08:43 -0700 (PDT) Received: by mail-ej1-x634.google.com with SMTP id u23so8339932ejt.1; Fri, 18 Mar 2022 09:08:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/RImxULSEIcXltj7eh82B63gODFmYdSpUPrpbmj5VVA=; b=Mre129SUos0QigZGiTepLRmoM+DqmTR/OLSwil9AJ/bS7houyWDVpZDi42wYKlSA4p Rj25TQCKbx9dQj0eQod7E0QMeO74akMiq+Rx8v/VBYFdsLudSa/QLRcH/jxsYWSsUek4 WGREYSTPvQjkbfpJQvJGkPKlgPy37dUJEeAcEYHibIyGaPFEleRZ0c4Ptczi2qWA0Pi5 ruuVvgfSJb6upjLC0jfcgvFtBycbvI08Or1aABsumMYaqlexJ1pOeV8rfmVGWw/o/pRj nLmvZiPGUa4oFPznCFrm3DFdHqFsqTm/CScGx9b1oHoMs2Fhj9xQ8Y2XNdGNvDovo0SL zIXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/RImxULSEIcXltj7eh82B63gODFmYdSpUPrpbmj5VVA=; b=jLMDoxErjf/ABRU3DIx5t7JbBFCMycHcxj3GqdZb00nRIhe2CXD7YHOAs9sSZtLpAe c3OSzvUeBtSJaVwwpZ5wCfWPiz0IEqIeLoCr2NvxqH+swjWgPWpniAE0/KtMBbOEKPQr p5utYZVUDWvMij2CShCWReXwJ0CDDFC8t7+zNmro65ux+Ndcga0UgIvi2slxnkRC5+Vv v/inzblbIny6YQCJYcGwQE1T5irP4BLJ7bndgGKRGQr16Fnq4hRCx1slm4zice03xx+b AEyKnFmAKZjetlRhHSRIETxnrxg3E5UvRxJMrKmvkvHMTuhJcRM7NZyJhwVttnCJCiqS lC0w== X-Gm-Message-State: AOAM533HIlspyHkcXeKbz3CkoTuHQlJPP0apyNpYKWMGL8HHwXlwW8Mg fP+0MQStyv4FMcH7Kp6DC7zRd83p9T4= X-Google-Smtp-Source: ABdhPJzA/H+VijZ8k5uM7408Pw9MByYHTdRFjaZXdPE2cnSlYXwhJU6adYKcjS1wO8I1ACG6RerrKw== X-Received: by 2002:a17:906:d555:b0:6da:ac8c:f66b with SMTP id cr21-20020a170906d55500b006daac8cf66bmr9458704ejc.107.1647619721489; Fri, 18 Mar 2022 09:08:41 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id e9-20020a170906c00900b006d4a45869basm3754118ejz.199.2022.03.18.09.08.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 09:08:41 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 12/16] clk: qcom: clk-krait: add apq/ipq8064 errata workaround Date: Fri, 18 Mar 2022 17:08:23 +0100 Message-Id: <20220318160827.8860-13-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220318160827.8860-1-ansuelsmth@gmail.com> References: <20220318160827.8860-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add apq/ipq8064 errata workaround where the sec_src clock gating needs to be disabled during switching. To enable this set disable_sec_src_gating in the mux struct. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/clk-krait.c | 16 ++++++++++++++++ drivers/clk/qcom/clk-krait.h | 1 + drivers/clk/qcom/krait-cc.c | 1 + 3 files changed, 18 insertions(+) diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c index b6b7650dbf15..7ba5dbc72bce 100644 --- a/drivers/clk/qcom/clk-krait.c +++ b/drivers/clk/qcom/clk-krait.c @@ -18,13 +18,23 @@ static DEFINE_SPINLOCK(krait_clock_reg_lock); #define LPL_SHIFT 8 +#define SECCLKAGD BIT(4) + static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel) { unsigned long flags; u32 regval; spin_lock_irqsave(&krait_clock_reg_lock, flags); + regval = krait_get_l2_indirect_reg(mux->offset); + + /* apq/ipq8064 Errata: disable sec_src clock gating during switch. */ + if (mux->disable_sec_src_gating) { + regval |= SECCLKAGD; + krait_set_l2_indirect_reg(mux->offset, regval); + } + regval &= ~(mux->mask << mux->shift); regval |= (sel & mux->mask) << mux->shift; if (mux->lpl) { @@ -33,6 +43,12 @@ static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel) } krait_set_l2_indirect_reg(mux->offset, regval); + /* apq/ipq8064 Errata: re-enabled sec_src clock gating. */ + if (mux->disable_sec_src_gating) { + regval &= ~SECCLKAGD; + krait_set_l2_indirect_reg(mux->offset, regval); + } + /* Wait for switch to complete. */ mb(); udelay(1); diff --git a/drivers/clk/qcom/clk-krait.h b/drivers/clk/qcom/clk-krait.h index 9120bd2f5297..f930538c539e 100644 --- a/drivers/clk/qcom/clk-krait.h +++ b/drivers/clk/qcom/clk-krait.h @@ -15,6 +15,7 @@ struct krait_mux_clk { u8 safe_sel; u8 old_index; bool reparent; + bool disable_sec_src_gating; struct clk_hw hw; struct notifier_block clk_nb; diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index 299eb4c81d96..cb8b267f1dc5 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -157,6 +157,7 @@ krait_add_sec_mux(struct device *dev, struct clk *qsb, int id, mux->shift = 2; mux->parent_map = sec_mux_map; mux->hw.init = &init; + mux->disable_sec_src_gating = true; init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); if (!init.name) From patchwork Fri Mar 18 16:08:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 552688 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49E1EC43219 for ; Fri, 18 Mar 2022 16:09:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238683AbiCRQK1 (ORCPT ); Fri, 18 Mar 2022 12:10:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54766 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238623AbiCRQKO (ORCPT ); Fri, 18 Mar 2022 12:10:14 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F1B7340F9; Fri, 18 Mar 2022 09:08:44 -0700 (PDT) Received: by mail-ej1-x635.google.com with SMTP id d10so17885068eje.10; Fri, 18 Mar 2022 09:08:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=QkfgyebL6ZDeFyix3jLmVd6pOSFa+uhSyC95dgb9bxk=; b=BerOL3dQ/78Oz2+oKSWkFCE9uaVT6/DIBQQ8Rf+MrUS6iK2qnUAwH4dFavAWJtThvk 4l1Uyqa1tOzGV+OaTSdhPJGqdowyXPu7l5oO+1mzZSA/jC5dnA9JfHacSrssQYFm2kH6 b+rcN79MrT2Va1Hk5g9DDZWOv12Q9cXuBpw+qzSQGb3JiIPX9muFJ4vVnIf8D+LrB+uj mucvpW5naHtIoo+zKmIf5ln0Q7wAubSj4afnw1l4RcWwwIiupGDtv/40DzgpPe1D2aBy 6BaiiwdmvCLMPRZFL6vM3Gkg7kUWq024LI0DVnj+danIN7G83riQjZudloxciqTggS4W I4ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QkfgyebL6ZDeFyix3jLmVd6pOSFa+uhSyC95dgb9bxk=; b=g56AwcPzcpM05UGe7fdJ4xrXoVepImjVedkU4hpxVeYdx7qiPpLLspyWo20Mvz7KvH kgl8aXp+4PgsQvIiuyBHyuSSwTP0SbBmwJ5OlFgL0ou9hTXL0MWKHgnMe1Puw6O9q1hZ CNcuuAuJW6ZGYOOpHPMuc9sAc4P4kBpx7/UZaiP3bcNZ8tawB+AzWpFfFJb80Cv8Knqu jqAZIjryUSru+ciGxX/pnW4JM2JtsAiyuaxIKQghOr+a8wIx7vMlrrEa4yx5mzzwEHSM pdpf+TeuhGslEkAmZARwmiRc+q4aUjLO5WuaOnkIdfBwMmhW+xOx1ZYuC2wnHaZy/G7Y mYDg== X-Gm-Message-State: AOAM5313WzXRAI9sf6bkXWHQ570AP21f1cpb7mu0IdcTY0tW/I2z9L/h hg+/Yx7dGHsWl3mmXWFHeb4= X-Google-Smtp-Source: ABdhPJyZqP28BOQfcEmKipl+Cj0mTuDHc92ASgrJShX6ni25UYRIgU+ok8PZTyj1dGq3jkwchkm0JQ== X-Received: by 2002:a17:907:7fa2:b0:6d8:2397:42 with SMTP id qk34-20020a1709077fa200b006d823970042mr9513040ejc.218.1647619722468; Fri, 18 Mar 2022 09:08:42 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id e9-20020a170906c00900b006d4a45869basm3754118ejz.199.2022.03.18.09.08.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 09:08:42 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 13/16] clk: qcom: clk-krait: add enable disable ops Date: Fri, 18 Mar 2022 17:08:24 +0100 Message-Id: <20220318160827.8860-14-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220318160827.8860-1-ansuelsmth@gmail.com> References: <20220318160827.8860-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add enable/disable ops for krait mux. On disable the mux is set to the safe selection. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/clk-krait.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c index 7ba5dbc72bce..061af57b0ec2 100644 --- a/drivers/clk/qcom/clk-krait.c +++ b/drivers/clk/qcom/clk-krait.c @@ -85,7 +85,25 @@ static u8 krait_mux_get_parent(struct clk_hw *hw) return clk_mux_val_to_index(hw, mux->parent_map, 0, sel); } +static int krait_mux_enable(struct clk_hw *hw) +{ + struct krait_mux_clk *mux = to_krait_mux_clk(hw); + + __krait_mux_set_sel(mux, mux->en_mask); + + return 0; +} + +static void krait_mux_disable(struct clk_hw *hw) +{ + struct krait_mux_clk *mux = to_krait_mux_clk(hw); + + __krait_mux_set_sel(mux, mux->safe_sel); +} + const struct clk_ops krait_mux_clk_ops = { + .enable = krait_mux_enable, + .disable = krait_mux_disable, .set_parent = krait_mux_set_parent, .get_parent = krait_mux_get_parent, .determine_rate = __clk_mux_determine_rate_closest, From patchwork Fri Mar 18 16:08:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 553075 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79C0BC4321E for ; Fri, 18 Mar 2022 16:09:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234218AbiCRQK2 (ORCPT ); Fri, 18 Mar 2022 12:10:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238627AbiCRQKP (ORCPT ); Fri, 18 Mar 2022 12:10:15 -0400 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 531AA13FA9; Fri, 18 Mar 2022 09:08:45 -0700 (PDT) Received: by mail-ej1-x62a.google.com with SMTP id d10so17885174eje.10; Fri, 18 Mar 2022 09:08:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=fMAOn8pwa3go68WYxvsLY0rJlkkqdpP8FjSo1TfU57o=; b=Tgra4fbpbW9t+HZRAw86segcuw0VfmNAIXD5YHR39256d4GYZ6jRq5mda6yC7mWYQ1 38wYF6XtHAn7ii6r+E28n02Q614VsVdebJwi2gquWnk3ZMMBwEa6OyZc636obr9HlYD1 kwcj0/daNDs8aIBHhENu4XWnwnrLuJmYre2+KV+2If1J8Amck0jhlDyuuWLPpN3u/NAl WLxMezdDq2b2UL4RZaaxerSk8TF+LkEeHXdTTCpSRJ2V9A7OuySPqa+wTqvfvxPbDqhU jKfQ30vQ+cNDS309kyFWBBLU1CiGuVTvK/ijisAI9QZYte9RYqNaECvlpRW+6Rroit0O TTdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fMAOn8pwa3go68WYxvsLY0rJlkkqdpP8FjSo1TfU57o=; b=ynOLbfj6fcj/CeJ/uFPz9gFuzUYIf/o//ogD8+Ek6OWh0O9ELX3Fpe+StwHlKVyhPn V6oHx0k8tNGWxdG2zrR0u2/JA0mRPEx9a3SA0uraWkYap9qwpl7KWwqWv1jcNwdZmyVM 8lLrW1XGSWh7lfItSpSz+5rks2ofRcLfckL7w3k6mCbSTjCDb7eOv1wqEJlNL4cGMrg1 GnNMacw307LMuvlXzsCF8lduqpzN9x/+ZgxRillqglhsb6gejSBknrPQGXLwc4CwiQI3 qsyFguDL2WBgL7hwufSHMujWyGTEDB8jPRaCMZD1GCdMT9/IWXVmYJu43qWB0IbLbTYV LRMQ== X-Gm-Message-State: AOAM530DzoUu4p3BE0WLMg+qzcdm9+mlbxQJvYOnpMn2/7cc6Tixklbk p4hzX8vzRDZvmgzxGuaGfzk= X-Google-Smtp-Source: ABdhPJxGRu5YdV2nhP6CtQGugP2YPlfhsiru2e+bq88JZH7KtZ35S1O8/ZUUOUYJI0B5PWn5t3M/fA== X-Received: by 2002:a17:907:9687:b0:6df:8f17:c16b with SMTP id hd7-20020a170907968700b006df8f17c16bmr8238158ejc.363.1647619723638; Fri, 18 Mar 2022 09:08:43 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id e9-20020a170906c00900b006d4a45869basm3754118ejz.199.2022.03.18.09.08.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 09:08:43 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 14/16] dt-bindings: clock: Convert qcom,krait-cc to yaml Date: Fri, 18 Mar 2022 17:08:25 +0100 Message-Id: <20220318160827.8860-15-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220318160827.8860-1-ansuelsmth@gmail.com> References: <20220318160827.8860-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert qcom,krait-cc to yaml and add missing l2 clocks and names definiton. Signed-off-by: Ansuel Smith --- .../bindings/clock/qcom,krait-cc.txt | 34 ---------- .../bindings/clock/qcom,krait-cc.yaml | 63 +++++++++++++++++++ 2 files changed, 63 insertions(+), 34 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt deleted file mode 100644 index 030ba60dab08..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt +++ /dev/null @@ -1,34 +0,0 @@ -Krait Clock Controller - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,krait-cc-v1" - "qcom,krait-cc-v2" - -- #clock-cells: - Usage: required - Value type: - Definition: must be 1 - -- clocks: - Usage: required - Value type: - Definition: reference to the clock parents of hfpll, secondary muxes. - -- clock-names: - Usage: required - Value type: - Definition: must be "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb". - -Example: - - kraitcc: clock-controller { - compatible = "qcom,krait-cc-v1"; - clocks = <&hfpll0>, <&hfpll1>, <&acpu0_aux>, <&acpu1_aux>, ; - clock-names = "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb"; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml b/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml new file mode 100644 index 000000000000..f89b70ab01ae --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,krait-cc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Krait Clock Controller + +maintainers: + - Ansuel Smith + +description: | + Qualcomm Krait Clock Controller used to correctly scale the CPU and the L2 + rates. + +properties: + compatible: + enum: + - qcom,krait-cc-v1 + - qcom,krait-cc-v2 + + clocks: + items: + - description: phandle to hfpll for CPU0 mux + - description: phandle to hfpll for CPU1 mux + - description: phandle to hfpll for L2 mux + - description: phandle to CPU0 aux clock + - description: phandle to CPU1 aux clock + - description: phandle to L2 aux clock + - description: phandle to QSB fixed clk + + clock-names: + items: + - const: hfpll0 + - const: hfpll1 + - const: hfpll_l2 + - const: acpu0_aux + - const: acpu1_aux + - const: acpu_l2_aux + - const: qsb + + '#clock-cells': + const: 1 + +required: + - compatible + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller { + compatible = "qcom,krait-cc-v1"; + clocks = <&hfpll0>, <&hfpll1>, <&hfpll_l2>, + <&acpu0_aux>, <&acpu1_aux>, <&acpu_l2_aux>, <&qsb>; + clock-names = "hfpll0", "hfpll1", "hfpll_l2", + "acpu0_aux", "acpu1_aux", "acpu_l2_aux", "qsb"; + #clock-cells = <1>; + }; +... From patchwork Fri Mar 18 16:08:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 552687 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA090C43217 for ; Fri, 18 Mar 2022 16:09:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238715AbiCRQK3 (ORCPT ); Fri, 18 Mar 2022 12:10:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53442 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238638AbiCRQKP (ORCPT ); Fri, 18 Mar 2022 12:10:15 -0400 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92F9F201AA; Fri, 18 Mar 2022 09:08:46 -0700 (PDT) Received: by mail-ej1-x631.google.com with SMTP id u23so8340234ejt.1; Fri, 18 Mar 2022 09:08:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=KF5KajzdUjlsueHw3PGEQrW6QOzbz3BzoTgHX03BJeo=; b=F6E4RUrnpJmvXhfhcqyY04JCA7xMBLH8puqhFPnrF8wBOHDnse26GzZ9eXG1yx8/qI RX9G1GsnuThqUO+SrkhlaO7uNbMbbqm9vCI6RNwF3B3HmB+c/tO9tgKm9l5UIA2O8xY5 lVK0BqRCKu1/cEqBjBDFe/EPPUgSVft9bGtArodKm1XO2zhZFWV1LRsKV9cVlMqSAs4i sFxaU9EY5kBm3xXvqbHen7QLjHZmHWerXcqaqAeVWxpuNwhawMhDt1xj4yUL5OcD+TaU mmqk7z+x1CBbIJNJsEI9LoChrv9mBvpMRmegf+0egVsT0HCgc8RcWGG5+/JjWCNH2CqP QOdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KF5KajzdUjlsueHw3PGEQrW6QOzbz3BzoTgHX03BJeo=; b=wej62SZOBUyPKxOakSB2Ubzug5FN8UMB64rtIPdFMSbN/iUIuY+6YHLn2GrHbuYplJ eFdMP2sFhz0YP9FXGXldjOJtuI/u4WE+rau6ebhQBOJPZO9aWLj/ES/GfQqI/3K6cKXi jsPjU5fhIi4YcEwicL/LoBBU3U0KnW1pbLjF8U0T4ocTkwF20UI926YRAx+B7UDbALMM ahcLB6xFrCuAqhzByMf8dWFf0dldcc9xEg1+VLywogIkm/p1r1OPOK6BJdY7ns3yoI1u W2TSo8E6BMnGdzNsQ9lUO37xGHgyTP+0LHKMQbW4sKPLvOZ9VhNQKZoAPfTC1lmpDorO nx8w== X-Gm-Message-State: AOAM531bEPIew0Yv7CwR9Kqnm/SzFuz4AP9UgiBcjvzn1v+WimsLgWyj gmE1/18Q65WF7acw2aYp6bk= X-Google-Smtp-Source: ABdhPJy1F26DEhhuhvt+bv1CovoXSvITpXqmY9HuSFLB3fNtqcm4BAhjdw2XN/nIf3Bm7jI3q7mg8w== X-Received: by 2002:a17:907:7da6:b0:6db:2e12:b85f with SMTP id oz38-20020a1709077da600b006db2e12b85fmr9140378ejc.312.1647619724841; Fri, 18 Mar 2022 09:08:44 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id e9-20020a170906c00900b006d4a45869basm3754118ejz.199.2022.03.18.09.08.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 09:08:44 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 15/16] ARM: dts: qcom: qcom-ipq8064: add missing krait-cc compatible and clocks Date: Fri, 18 Mar 2022 17:08:26 +0100 Message-Id: <20220318160827.8860-16-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220318160827.8860-1-ansuelsmth@gmail.com> References: <20220318160827.8860-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add missing krait-cc clock-controller and define missing aux clock for CPUs. Also change phandle for l2cc node to point to pxo_board instead of gcc PXO_SRC. Signed-off-by: Ansuel Smith --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 996f4458d9fc..888f17d64283 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -468,11 +468,19 @@ IRQ_TYPE_EDGE_RISING)>, acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu0_aux"; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + #clock-cells = <0>; }; acc1: clock-controller@2098000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu1_aux"; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + #clock-cells = <0>; }; adm_dma: dma-controller@18300000 { @@ -782,11 +790,21 @@ tcsr: syscon@1a400000 { l2cc: clock-controller@2011000 { compatible = "qcom,kpss-gcc", "syscon"; reg = <0x2011000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; clock-names = "pll8_vote", "pxo"; clock-output-names = "acpu_l2_aux"; }; + kraitcc: clock-controller { + compatible = "qcom,krait-cc-v1"; + clocks = <&gcc PLL9>, <&gcc PLL10>, <&gcc PLL12>, + <&acc0>, <&acc1>, <&l2cc>, <&qsb>; + clock-names = "hfpll0", "hfpll1", "hfpll_l2", + "acpu0_aux", "acpu1_aux", "acpu_l2_aux", + "qsb"; + #clock-cells = <1>; + }; + lcc: clock-controller@28000000 { compatible = "qcom,lcc-ipq8064"; reg = <0x28000000 0x1000>; From patchwork Fri Mar 18 16:08:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 553074 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F8E3C433EF for ; Fri, 18 Mar 2022 16:09:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238525AbiCRQKc (ORCPT ); Fri, 18 Mar 2022 12:10:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54796 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238643AbiCRQKP (ORCPT ); Fri, 18 Mar 2022 12:10:15 -0400 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC90A2BF3; Fri, 18 Mar 2022 09:08:47 -0700 (PDT) Received: by mail-ej1-x632.google.com with SMTP id qx21so17855195ejb.13; Fri, 18 Mar 2022 09:08:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=GsYDL/OyQ4CKGuUspknG5Sq0zM6BGuA8VP+jOV/hNlQ=; b=ebXb9I72pym+b2ARd9uIcThbuFCa2zTTvq6DwWnh2cn7k4g7ka0sLgJwVfb0WcgITv Dxmksz2ER2pRqV4EOwJ6QkoMW4Tlx9uS5oJ53HLlJSaJWyIrnGevCK/wE2fHqmd9jPrH Yt+xHCFUIoA1ijN1KZv+G1Ys9wa2JMoNyNF1lc9OtMYcPfwZSA6zmFj3q/B4YfCW4llw IdhSgKBI/91+xjErPzes71c1cbAtk90DK+eHDvPF7RWXw4E8omJGsn7PyEXAOKHd+OdX dkzjUDiWgKHrG3SCYnXroXjtJ7E2mobSEvP1xyNWnDoDfR5ZVYb8S1QD89orG5+Cslqd Tz/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GsYDL/OyQ4CKGuUspknG5Sq0zM6BGuA8VP+jOV/hNlQ=; b=kmcKl1NiEtI6G8i7YdQozTbeEoc0dsm2iOmSb1jEWuNElLrqTgxUmu0QdcL6GJ3Dn0 wy2xvvDUsxmOrKqbsFLof4Yz/+2a6eljrckAJNz6haYKq+3ZJ4d8LXIDe9C3Ei14nlMk ZHhrRxNPPqRrOwybXTWF7u1plV2tI8Q5yD0Mya+HC4HiJhrnvZ7Bx9KcdpQLNd9sQ1F5 QehA/i7xahb9LjBxTQhoAe8Bok6TmwQCSm2Bl+GqqfDElmxHZjNgR1LSCq6QZmN3aodW rm6FYYds+SAWmrlzdzjs5qt0VCMJv/DcujFYcedy7L69nRNYfR9rv/ONSB8z1yx8E9Z/ cx+w== X-Gm-Message-State: AOAM533MBIO5Sd3dbnwOA/W1zNII0HzQxwKVWAWdOW9ivGNkrDGc8huh KWOFRpZzI5WH2yb8IsJSewc= X-Google-Smtp-Source: ABdhPJxbAgDpTcZCM/28nsz/se8K3HvJP5o7yyvu3PWKlT9r7h1VJe0eG27GmsHqhYQlIj99DMk2LQ== X-Received: by 2002:a17:906:57c1:b0:6d6:da73:e9c0 with SMTP id u1-20020a17090657c100b006d6da73e9c0mr9800874ejr.45.1647619725920; Fri, 18 Mar 2022 09:08:45 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id e9-20020a170906c00900b006d4a45869basm3754118ejz.199.2022.03.18.09.08.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 09:08:45 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 16/16] dt-bindings: arm: msm: Convert kpss driver Documentation to yaml Date: Fri, 18 Mar 2022 17:08:27 +0100 Message-Id: <20220318160827.8860-17-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220318160827.8860-1-ansuelsmth@gmail.com> References: <20220318160827.8860-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert kpss-acc and kpss-gcc Documentation to yaml. Fix multiple Documentation error and provide additional example for kpss-gcc-v2. Signed-off-by: Ansuel Smith --- .../bindings/arm/msm/qcom,kpss-acc.txt | 49 ---------- .../bindings/arm/msm/qcom,kpss-acc.yaml | 97 +++++++++++++++++++ .../bindings/arm/msm/qcom,kpss-gcc.txt | 44 --------- .../bindings/arm/msm/qcom,kpss-gcc.yaml | 63 ++++++++++++ 4 files changed, 160 insertions(+), 93 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.yaml delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.yaml diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt deleted file mode 100644 index 7f696362a4a1..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt +++ /dev/null @@ -1,49 +0,0 @@ -Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) - -The KPSS ACC provides clock, power domain, and reset control to a Krait CPU. -There is one ACC register region per CPU within the KPSS remapped region as -well as an alias register region that remaps accesses to the ACC associated -with the CPU accessing the region. - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: should be one of: - "qcom,kpss-acc-v1" - "qcom,kpss-acc-v2" - -- reg: - Usage: required - Value type: - Definition: the first element specifies the base address and size of - the register region. An optional second element specifies - the base address and size of the alias register region. - -- clocks: - Usage: required - Value type: - Definition: reference to the pll parents. - -- clock-names: - Usage: required - Value type: - Definition: must be "pll8_vote", "pxo". - -- clock-output-names: - Usage: optional - Value type: - Definition: Name of the output clock. Typically acpuX_aux where X is a - CPU number starting at 0. - -Example: - - clock-controller@2088000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0x02088000 0x1000>, - <0x02008000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu0_aux"; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.yaml new file mode 100644 index 000000000000..6e8ef4f85eab --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/msm/qcom,kpss-acc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) + +maintainers: + - Ansuel Smith + +description: | + The KPSS ACC provides clock, power domain, and reset control to a Krait CPU. + There is one ACC register region per CPU within the KPSS remapped region as + well as an alias register region that remaps accesses to the ACC associated + with the CPU accessing the region. + +properties: + compatible: + enum: + - qcom,kpss-acc-v1 + - qcom,kpss-acc-v2 + + reg: + items: + - description: Base address and size of the register region + - description: Optional base address and size of the alias register region + + clocks: + items: + - description: phandle to pll8_vote + - description: phandle to pxo_board + + clock-names: + items: + - const: pll8_vote + - const: pxo + + clock-output-names: + description: Name of the aux clock. Krait can have at most 4 cpu. + enum: + - acpu0_aux + - acpu1_aux + - acpu2_aux + - acpu3_aux + + '#clock-cells': + const: 0 + +required: + - compatible + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: qcom,kpss-acc-v1 + then: + required: + - clocks + - clock-names + - clock-output-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@2088000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu0_aux"; + #clock-cells = <0>; + }; + + clock-controller@2098000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu1_aux"; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + #clock-cells = <0>; + }; + + - | + clock-controller@f9088000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf9088000 0x1000>, + <0xf9008000 0x1000>; + }; +... diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt deleted file mode 100644 index e628758950e1..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt +++ /dev/null @@ -1,44 +0,0 @@ -Krait Processor Sub-system (KPSS) Global Clock Controller (GCC) - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: should be one of the following. The generic compatible - "qcom,kpss-gcc" should also be included. - "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc" - "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc" - "qcom,kpss-gcc-msm8974", "qcom,kpss-gcc" - "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc" - -- reg: - Usage: required - Value type: - Definition: base address and size of the register region - -- clocks: - Usage: required - Value type: - Definition: reference to the pll parents. - -- clock-names: - Usage: required - Value type: - Definition: must be "pll8_vote", "pxo". - -- clock-output-names: - Usage: required - Value type: - Definition: Name of the output clock. Typically acpu_l2_aux indicating - an L2 cache auxiliary clock. - -Example: - - l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"; - reg = <0x2011000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu_l2_aux"; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.yaml new file mode 100644 index 000000000000..578e2eccb7db --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/msm/qcom,kpss-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Krait Processor Sub-system (KPSS) Global Clock Controller (GCC) + +maintainers: + - Ansuel Smith + +description: | + Krait Processor Sub-system (KPSS) Global Clock Controller (GCC). Used + to control L2 mux (in the current implementation). + +properties: + compatible: + const: qcom,kpss-gcc + + reg: + items: + - description: Base address and size of the register region + + clocks: + items: + - description: phandle to pll8_vote + - description: phandle to pxo_board + + clock-names: + items: + - const: pll8_vote + - const: pxo + + clock-output-names: + const: acpu_l2_aux + + '#clock-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - clock-output-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@2011000 { + compatible = "qcom,kpss-gcc"; + reg = <0x2011000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu_l2_aux"; + #clock-cells = <0>; + }; +... +