From patchwork Sun Mar 20 11:34:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 553239 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98DD0C433EF for ; Sun, 20 Mar 2022 16:28:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245471AbiCTQ3j (ORCPT ); Sun, 20 Mar 2022 12:29:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39832 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239460AbiCTQ3h (ORCPT ); Sun, 20 Mar 2022 12:29:37 -0400 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 55773344FD; Sun, 20 Mar 2022 09:28:13 -0700 (PDT) Received: by mail-wm1-x333.google.com with SMTP id bg31-20020a05600c3c9f00b00381590dbb33so7222684wmb.3; Sun, 20 Mar 2022 09:28:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=oYnAnrWU13qc8rQ7MPOxKFwqoXsKN+1WmTS68IkDyt4=; b=duToya5GyaLrkMJnWO2Ls+N6vIz4sThEzI6BF9OYmhyrvl2ruxuAfIao2I+rTdaSxw vtKjV3zt1JeGbrLC3LH77YcdTpotON/o+N9hXrKbwXwsnp2eu9LZk55EKEdegcdJH8nc 9FopJPT3Ga9wLmX+fRy2UJ3xmZgsIXOCzwcoowAuU274HQGiJ2sPETOzW5adLwcxdN6J vwjj2m4+PMmLjCTRlMzvDM1i008MbYFC91MrF8TgYYm6XkH6XynhZbGfq3noMXWt9F9p wb86T2fp/y9DXDctCyM6lVPgW3qijB+nasEaHRHzoWSEULfQCAe96nPRxbdJjmMNQhaG /HCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oYnAnrWU13qc8rQ7MPOxKFwqoXsKN+1WmTS68IkDyt4=; b=tO8yRoCZxVMsm+9C4JZJNoL6bG5toPHoEgBeZHJci/KhImNuZUUX4jdnjOjVq3W9kh qf9pWKg0PFn36ArL/c79RhIuEVe7zgJqp64jmluZsIe+Pwnsp9Oxju2QrdZZI1KHLzAr E+cdulUSJxo+gb25V8/+VZLnQoaVkfMOQBL3XpftFb8s+X6XqqteA+m0DL0StK/V/FQh VY6wELNxP/zL6o0QupUmmwuMXsu1gPkM4NLUuzQSAskjgTAnbiTrE/Kl5l32sQURnq2q 8PxHctC1GRRfj/vTkehnWWgQIW9IEf9Y82MSl3gNUnBR7t8tyZ8Q5SxvtIgPCfqhBj3+ MK+Q== X-Gm-Message-State: AOAM5303J64dTi7U/0WVPzRUNHjVdJD2hn+kTWEUqZM/5y4wpQKikBLv apHO2hSDnK8wAxyVzIco7DTOP+M8FJE= X-Google-Smtp-Source: ABdhPJzsF2L39vQVemrWbD2ydWVKnPPXKF1H8NNqmf5MZ1reKui8rBG7oZSXKiz9gJuAoFmP0qhQ/g== X-Received: by 2002:a05:600c:3d0e:b0:38c:9b5e:52c0 with SMTP id bh14-20020a05600c3d0e00b0038c9b5e52c0mr4428465wmb.3.1647793691696; Sun, 20 Mar 2022 09:28:11 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id y6-20020a05600015c600b00203fa70b4ebsm6760085wry.53.2022.03.20.09.28.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Mar 2022 09:28:11 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 01/18] clk: introduce clk_hw_get_index_of_parent new API Date: Sun, 20 Mar 2022 12:34:13 +0100 Message-Id: <20220320113430.26076-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220320113430.26076-1-ansuelsmth@gmail.com> References: <20220320113430.26076-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Clk can have multiple parents. Some clk may require to get the cached index of other parent that are not current associated with the clk. We have clk_hw_get_parent_index() that returns the index of the current parent but we can't get the index of other parents of the provided clk. Introduce clk_hw_get_index_of_parent() to get the cached index of the parent of the provided clk. This permits a direct access of the internal clk_fetch_parent_index(). Signed-off-by: Ansuel Smith --- drivers/clk/clk.c | 14 ++++++++++++++ include/linux/clk-provider.h | 1 + 2 files changed, 15 insertions(+) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 8de6a22498e7..bdd70a88394c 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -1726,6 +1726,20 @@ int clk_hw_get_parent_index(struct clk_hw *hw) } EXPORT_SYMBOL_GPL(clk_hw_get_parent_index); +/** + * clk_hw_get_index_of_parent - return the index of the parent clock + * @hw: clk_hw associated with the clk being consumed + * @parent: clk_hw of the parent to be fetched the index of + * + * Fetches and returns the index of parent clock provided. + * Returns -EINVAL if the given parent index can't be provided. + */ +int clk_hw_get_index_of_parent(struct clk_hw *hw, const struct clk_hw *parent) +{ + return clk_fetch_parent_index(hw->core, parent->core); +} +EXPORT_SYMBOL_GPL(clk_hw_get_index_of_parent); + /* * Update the orphan status of @core and all its children. */ diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 2faa6f7aa8a8..5708c0b3ef1c 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -1198,6 +1198,7 @@ unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, unsigned int index); +int clk_hw_get_index_of_parent(struct clk_hw *hw, const struct clk_hw *parent); int clk_hw_get_parent_index(struct clk_hw *hw); int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent); unsigned int __clk_get_enable_count(struct clk *clk); From patchwork Sun Mar 20 11:34:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 553237 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 290D0C4167E for ; Sun, 20 Mar 2022 16:28:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245493AbiCTQ3q (ORCPT ); Sun, 20 Mar 2022 12:29:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39924 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245469AbiCTQ3i (ORCPT ); Sun, 20 Mar 2022 12:29:38 -0400 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77EA034641; Sun, 20 Mar 2022 09:28:14 -0700 (PDT) Received: by mail-wm1-x32a.google.com with SMTP id o30-20020a05600c511e00b0038c9cfb79cbso459452wms.1; Sun, 20 Mar 2022 09:28:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8P3wAYvgFlPve71dG0z5aPiI1G8WoaU4vYr3l4vmoOE=; b=SFtzoD64TaQzPSLPWXnXCW7cW+np83Bf6OQnuSus43XleVePiClweVC3y4JFv+jT9a bb7q9P/mkk0hjCT+w/RiFK/W4p29/Dq0+U0xLc3Qed9pU1O69bmIS4y4S8z08SmT20v7 c9uB9aEUZDlrteDwrhXJDyEbGcZ4sl0YhF4hXhK1QNOFTYiESAZzc1bgqcevu/ywnKYJ oQENVuC6L8Wo6p/++tNda2hoDQsDtOSMD+ItG3mgkLsh5qYHG46WAI4GN7kMe6ypybLv PYnZEpTWlBivOmnjsEO15ZIWXi6M6LOagKQI4iV98H8zK6qGZkd3bP9V1gEj89bQtCix TZIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8P3wAYvgFlPve71dG0z5aPiI1G8WoaU4vYr3l4vmoOE=; b=qis2QJZJbzq/xr79XdpaJRRNfum7C1dM93majSw/tsI3YQQG74O2WdapnWfhJxUyZ/ 90z2+DfXa90za1std4AXmdFohWAy57HVbReMTiBMiQdW0jagaRqVkSfrN7ePW0mkGiad aPvITdTft99fRjXRA8JY+zxwFxDiYxrvizVNb3GVEXglngDWvudUsDCCt0VT+JqifeGt pi8hKCrtMHuI3lVb33xI2VdqObpv6EAcE8gC7ivba7DfeUG8nu8TcOGHIyTPWSpvlJQU Jkcu91AjeehQT4cUzoB+gsr6VPoophZPytSY+DUsMtzbql35HWu9Ab9stP710+uPChW+ Ntig== X-Gm-Message-State: AOAM532R+8yY0wKbJVWSnyM/W7FeDbseY+I7gY+WOA19E3ro5NaKrxkd bpToMLLaVKGOV76VM6iwjRjvppaHdeI= X-Google-Smtp-Source: ABdhPJz1GOmXaYQZUAA0skYDcx6omh1lEo3AeWkKPBF6mOQaprrVroYAY0T2KtU2owtV9IlwtGbYQg== X-Received: by 2002:a05:600c:a06:b0:37b:fdd8:4f8 with SMTP id z6-20020a05600c0a0600b0037bfdd804f8mr24304139wmp.41.1647793692871; Sun, 20 Mar 2022 09:28:12 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id y6-20020a05600015c600b00203fa70b4ebsm6760085wry.53.2022.03.20.09.28.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Mar 2022 09:28:12 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 02/18] clk: qcom: gcc-ipq806x: skip pxo/cxo fixed clk if already present Date: Sun, 20 Mar 2022 12:34:14 +0100 Message-Id: <20220320113430.26076-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220320113430.26076-1-ansuelsmth@gmail.com> References: <20220320113430.26076-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Skip pxo/cxo clock registration if they are already defined in DTS as fixed clock. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index d6b7adb4be38..27f6d7626abb 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -3061,15 +3062,22 @@ static int gcc_ipq806x_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct regmap *regmap; + struct clk *clk; int ret; - ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000); - if (ret) - return ret; + clk = clk_get(dev, "cxo"); + if (IS_ERR(clk)) { + ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000); + if (ret) + return ret; + } - ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000); - if (ret) - return ret; + clk = clk_get(dev, "pxo"); + if (IS_ERR(clk)) { + ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000); + if (ret) + return ret; + } ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc); if (ret) From patchwork Sun Mar 20 11:34:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 553238 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFBAAC433FE for ; Sun, 20 Mar 2022 16:28:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245488AbiCTQ3o (ORCPT ); Sun, 20 Mar 2022 12:29:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245475AbiCTQ3k (ORCPT ); Sun, 20 Mar 2022 12:29:40 -0400 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05081344FD; Sun, 20 Mar 2022 09:28:17 -0700 (PDT) Received: by mail-wr1-x436.google.com with SMTP id d7so17849512wrb.7; Sun, 20 Mar 2022 09:28:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8h0dp/sRCWnE/SzxqBhwWtp3OCJwunZ7486W2HMfBko=; b=B0atMPIder4N8TYzrHjKga4/7nhsneKYsEcoH6kos02/gg5Yn2wwVo/AA73vcSdScA 5+6kZJGk0GqaIWEuFkJeI2/yCIAH5X+FxabhJzXcedFjtZCcgSnU7nq6Qeeiod1cj85+ 26dN+n5uOgJOJNPJGDoOzxudbCnM7cpJlOt+nCMgRzsXBr689x7Llduc/k2f6i7Mqjzs U5Cs0O6e8/ewWfPwxqBFjsSxHhHoeqDm+Ug9duoj525HZZJZrI38MtdgcLip8mA5Jfgn HJcz1dNOM7zU3V/7xbvUBJ1TPTR31rDa580elBXgdYOUpe1hynwQM2v9NmPQLrCSRdUV 2ZRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8h0dp/sRCWnE/SzxqBhwWtp3OCJwunZ7486W2HMfBko=; b=H//iICjD7Lf55ewOUOF/c7KKA0/fHP8F1xy3wwVVw1Xx8KAYenPWKqWDFsEVdnLMC6 VhsM5ldaJrg7fX4HJWQ5hp/sFKK7IcWixDeI9nDcPaf6XqcEl+9AROM7oKQEbajJGsnu uHurP/79NMmSqDD04XjzpQb4bc5vfmzn4QZ11rNNrcWDg2JJ8Lom0R0d3fW2HgTRX2O7 Ll88PQMNuoAtANgc2Dp9doBg6xyDbcjXk1SEAq/q7le/S7bnb+lYhUnObUkRWfeHgrDo uxbSBeTs/rcVgnr6HVsgfOIxncOy67eed29ugDNh+n/jCcYv9CY8h1l/1n77e8eS8f9L V1UQ== X-Gm-Message-State: AOAM533RYuJAatKTk2rpvKo5R6fQCO/DEqQMPZ/jgfaNdHFHHmA86Z90 V2Yg5PjOfAunzQB3/nQ6WOE3dmFBeMo= X-Google-Smtp-Source: ABdhPJzVnwSL99bC9SXDX+khcfZLP0yrgqadr9Ahdtx3UDvRCpWSKetOLw+Ppv/JNS9xkqj+x1qA1g== X-Received: by 2002:adf:a4ce:0:b0:203:fce0:755e with SMTP id h14-20020adfa4ce000000b00203fce0755emr7469376wrb.510.1647793695282; Sun, 20 Mar 2022 09:28:15 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id y6-20020a05600015c600b00203fa70b4ebsm6760085wry.53.2022.03.20.09.28.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Mar 2022 09:28:14 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 04/18] clk: qcom: clk-hfpll: use poll_timeout macro Date: Sun, 20 Mar 2022 12:34:16 +0100 Message-Id: <20220320113430.26076-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220320113430.26076-1-ansuelsmth@gmail.com> References: <20220320113430.26076-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Use regmap_read_poll_timeout macro instead of do-while structure. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/clk-hfpll.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/clk-hfpll.c b/drivers/clk/qcom/clk-hfpll.c index e847d586a73a..a4e347eb4d4d 100644 --- a/drivers/clk/qcom/clk-hfpll.c +++ b/drivers/clk/qcom/clk-hfpll.c @@ -12,6 +12,8 @@ #include "clk-regmap.h" #include "clk-hfpll.h" +#define HFPLL_BUSY_WAIT_TIMEOUT 100 + #define PLL_OUTCTRL BIT(0) #define PLL_BYPASSNL BIT(1) #define PLL_RESET_N BIT(2) @@ -72,13 +74,12 @@ static void __clk_hfpll_enable(struct clk_hw *hw) regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N); /* Wait for PLL to lock. */ - if (hd->status_reg) { - do { - regmap_read(regmap, hd->status_reg, &val); - } while (!(val & BIT(hd->lock_bit))); - } else { + if (hd->status_reg) + regmap_read_poll_timeout(regmap, hd->status_reg, val, + !(val & BIT(hd->lock_bit)), USEC_PER_MSEC * 2, + HFPLL_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC); + else udelay(60); - } /* Enable PLL output. */ regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL); From patchwork Sun Mar 20 11:34:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 553236 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC98AC41535 for ; Sun, 20 Mar 2022 16:28:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245505AbiCTQ3r (ORCPT ); Sun, 20 Mar 2022 12:29:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245479AbiCTQ3m (ORCPT ); Sun, 20 Mar 2022 12:29:42 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3243C344DC; Sun, 20 Mar 2022 09:28:18 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id u16so16850496wru.4; Sun, 20 Mar 2022 09:28:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=KJy+bVD9Yq3kRrz9Gx7NWpfnxrb/beBV0JaHxbyWaTA=; b=cEoglGD+MtPj1LCuCCZuLMiLqdVULATaMu0uGt9BgJy8BBxAqnLp+KqyEDvgNd1Lq/ t2U9TbqbI1R9d+Gwm/fc1tEMl9/n+KanIP//vi/Il+HoJloMDxOxf0aJ/ffCY5zY0jVp DZz3MhFSdyuHrPj4p6XnfYpUVAjeQb7quikiu/AEZrsp2rHIJ6QIboUvdjw4lSCCdEzm c+N2PGnnfo5N6xqS6sxRDOaNR8CItuup4tKai+7el0Ty1rurZ5FEUpcNzwiYwufq62Wt F7YuNz6TH7FcqJ5oxvU2mBIzYG5P13yRhf00mtat3legkY7d7pV2pMIwwAkI+dFqlTKJ 2XZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KJy+bVD9Yq3kRrz9Gx7NWpfnxrb/beBV0JaHxbyWaTA=; b=zYLtqLq3tpz3hERA9le0mWSPsYKfJm5wPXKFfo82ve8TzPVRJFeQ/KbacGGXIuIY5A M394n+ujwRJ0ISO9RJaXZUu1+LYP2gl8Tkyi5ub4WUDTMrKSCgybSKNCu2Iaz8XAouNJ LtSOYTeNnqiwwBfStRsP5HN3OeMV/0WZKqiE3UMiyZeohVkBNA5CLOdGT6uL6jMca04V iaerhT7NzQZueSh0tJ7jHZmnniJ8RNGBNHuZK2ldNpoertCa5VsSL4I9F9TDJ58lC04K VeekpooRk/s/NjpGhsr0OEm7UjDW41KopUBbsfAMCY7XD6ea/Pcys0cvXRl/ObIRs0ZX YwHQ== X-Gm-Message-State: AOAM5320ubd+JFGws/V7e2AERjbHH7ziO75cQZje0/ifP6Df5GZd/NPh 4iQcxK0Pn/3LY/mUS8LP5IzD1MYzLxM= X-Google-Smtp-Source: ABdhPJw2JIU7ooviqse14YqNA/qhNtEj6Knv7qKcUYq0tPlvtH8e24pjHNNqEE7r0N8gpygJxg96kA== X-Received: by 2002:a5d:584a:0:b0:203:97f6:5975 with SMTP id i10-20020a5d584a000000b0020397f65975mr15150068wrf.612.1647793696495; Sun, 20 Mar 2022 09:28:16 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id y6-20020a05600015c600b00203fa70b4ebsm6760085wry.53.2022.03.20.09.28.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Mar 2022 09:28:16 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 05/18] clk: qcom: kpss-xcc: convert to parent data API Date: Sun, 20 Mar 2022 12:34:17 +0100 Message-Id: <20220320113430.26076-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220320113430.26076-1-ansuelsmth@gmail.com> References: <20220320113430.26076-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the driver to parent data API. From the Documentation pll8_vote and pxo should be declared in the DTS so fw_name can be used instead of parent_names. Name is still used to save regression on old definition. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/kpss-xcc.c | 25 ++++++++----------------- 1 file changed, 8 insertions(+), 17 deletions(-) diff --git a/drivers/clk/qcom/kpss-xcc.c b/drivers/clk/qcom/kpss-xcc.c index 4fec1f9142b8..347f70e9f5fe 100644 --- a/drivers/clk/qcom/kpss-xcc.c +++ b/drivers/clk/qcom/kpss-xcc.c @@ -12,9 +12,9 @@ #include #include -static const char *aux_parents[] = { - "pll8_vote", - "pxo", +static const struct clk_parent_data aux_parents[] = { + { .name = "pll8_vote", .fw_name = "pll8_vote" }, + { .name = "pxo", .fw_name = "pxo" }, }; static unsigned int aux_parent_map[] = { @@ -32,8 +32,8 @@ MODULE_DEVICE_TABLE(of, kpss_xcc_match_table); static int kpss_xcc_driver_probe(struct platform_device *pdev) { const struct of_device_id *id; - struct clk *clk; void __iomem *base; + struct clk_hw *hw; const char *name; id = of_match_device(kpss_xcc_match_table, &pdev->dev); @@ -55,24 +55,15 @@ static int kpss_xcc_driver_probe(struct platform_device *pdev) base += 0x28; } - clk = clk_register_mux_table(&pdev->dev, name, aux_parents, - ARRAY_SIZE(aux_parents), 0, base, 0, 0x3, - 0, aux_parent_map, NULL); + hw = __devm_clk_hw_register_mux(&pdev->dev, NULL, name, ARRAY_SIZE(aux_parents), + NULL, NULL, aux_parents, 0, base, 0, 0x3, + 0, aux_parent_map, NULL); - platform_set_drvdata(pdev, clk); - - return PTR_ERR_OR_ZERO(clk); -} - -static int kpss_xcc_driver_remove(struct platform_device *pdev) -{ - clk_unregister_mux(platform_get_drvdata(pdev)); - return 0; + return PTR_ERR_OR_ZERO(hw); } static struct platform_driver kpss_xcc_driver = { .probe = kpss_xcc_driver_probe, - .remove = kpss_xcc_driver_remove, .driver = { .name = "kpss-xcc", .of_match_table = kpss_xcc_match_table, From patchwork Sun Mar 20 11:34:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 553235 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E75BC4707E for ; Sun, 20 Mar 2022 16:28:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245521AbiCTQ3t (ORCPT ); Sun, 20 Mar 2022 12:29:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40254 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245490AbiCTQ3p (ORCPT ); Sun, 20 Mar 2022 12:29:45 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FECC344DC; Sun, 20 Mar 2022 09:28:21 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id h23so17241625wrb.8; Sun, 20 Mar 2022 09:28:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1tacB+H58ZcVKBVcWE3u+TMM2y65iIDEoWk8hI94hWs=; b=AoJChIRauwDPPpAs6BiYi9HrDAQ2laxo9Eb3ZRwqREkTz5ve1GJkKXg22/V/FVnu+4 yww94l2l7NSUS2FKRaFvQLvzN+T1Hedi7gkxwZE6k3saj4dDyieHQgF5Rsl4f/ZVCJes 3xXJHCSDQrF4owvkF/PPDjyQNwbRkMia3diLAKXI6OfgAiRTxiZ5KttN6+2jKNuCHTnW Iv/jomO74aw7OEPAiOqEkcx2WffHU5Uw2FwN5DKxWb6a+MWmFWO8OIZew7O0L7CNA8MA E8UXqS6pubEtsiAOTmF3mxZhsx/PncrWvuacjqxqBuCjurFKqcgtFSdKdhgZP8qg/93x 8bQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1tacB+H58ZcVKBVcWE3u+TMM2y65iIDEoWk8hI94hWs=; b=r7+mOkEvhCnnnh1Pb4l1BHZUcPUy0dMkXAYBSuR6/PjfMbCNEBR+D+34r36UDHpahX WU8RGbqfPh0Y2hHj6wMcNbaOoWqLtAGJLezAy1l8XtcQESAXVv9vjaGMtkIuhxIAEuXT nOcPKpBPmFHxtq84ep0q/QyXRxWcBI/Dwcpix4mxT9XH2CFRP8tbemQbklmSIqSCSiV/ QnrcftLd9DEsPqQCc+6b7jQ3mrbQKvwtZXF/RTt5uQZJ0yKuQBUZGlCWhP7Vzw2QcmJ6 cZzBFcF3pc4pecfbE6kLe6mdGxK4BJ+UGFdzcgYwqU/MuumraqIEsjFedWDMQ6fHO5Qz 8JQw== X-Gm-Message-State: AOAM5338aBeuBtnLeD9EmgaJoC93z0hLnqbhOj3xjC8KwZwsY9Ceb8Hs OKpqZAT3LNFEvx4EhtZs0RM= X-Google-Smtp-Source: ABdhPJyXnW1/YJCbKhn+tUEsw5gMm2PXKKFkecZeM9xTxn+kIAu2b2zkJ1X2aN49tKfwqoLhH6WKRw== X-Received: by 2002:a05:6000:18ae:b0:204:62a:20f4 with SMTP id b14-20020a05600018ae00b00204062a20f4mr4477530wri.640.1647793699956; Sun, 20 Mar 2022 09:28:19 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id y6-20020a05600015c600b00203fa70b4ebsm6760085wry.53.2022.03.20.09.28.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Mar 2022 09:28:19 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 08/18] clk: qcom: krait-cc: convert to parent_data API Date: Sun, 20 Mar 2022 12:34:20 +0100 Message-Id: <20220320113430.26076-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220320113430.26076-1-ansuelsmth@gmail.com> References: <20220320113430.26076-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Modernize the krait-cc driver to parent-data API and refactor to drop any use of clk_names. From Documentation all the required clocks should be declared in DTS so fw_name can be correctly used to get the parents for all the muxes. Name is also declared to save compatibility with old implementation. Also fix the parent order of the sec_mux that was wrong and incorrectly report the wrong safe parent if it's not hardcoded. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/krait-cc.c | 126 +++++++++++++++++++----------------- 1 file changed, 66 insertions(+), 60 deletions(-) diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index 4d4b657d33c3..645ad9e8dd73 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -69,21 +69,22 @@ static int krait_notifier_register(struct device *dev, struct clk *clk, return ret; } -static int +static struct clk * krait_add_div(struct device *dev, int id, const char *s, unsigned int offset) { struct krait_div2_clk *div; + static struct clk_parent_data p_data[1]; struct clk_init_data init = { - .num_parents = 1, + .num_parents = ARRAY_SIZE(p_data), .ops = &krait_div2_clk_ops, .flags = CLK_SET_RATE_PARENT, }; - const char *p_names[1]; struct clk *clk; + char *parent_name; div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); if (!div) - return -ENOMEM; + return ERR_PTR(-ENOMEM); div->width = 2; div->shift = 6; @@ -93,43 +94,49 @@ krait_add_div(struct device *dev, int id, const char *s, unsigned int offset) init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s); if (!init.name) - return -ENOMEM; + return ERR_PTR(-ENOMEM); - init.parent_names = p_names; - p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s); - if (!p_names[0]) { - kfree(init.name); - return -ENOMEM; + init.parent_data = p_data; + parent_name = kasprintf(GFP_KERNEL, "hfpll%s", s); + if (!parent_name) { + clk = ERR_PTR(-ENOMEM); + goto err_parent_name; } + p_data[0].fw_name = parent_name; + p_data[0].name = parent_name; + clk = devm_clk_register(dev, &div->hw); - kfree(p_names[0]); + + kfree(parent_name); +err_parent_name: kfree(init.name); - return PTR_ERR_OR_ZERO(clk); + return clk; } -static int +static struct clk * krait_add_sec_mux(struct device *dev, int id, const char *s, unsigned int offset, bool unique_aux) { int ret; struct krait_mux_clk *mux; - static const char *sec_mux_list[] = { - "acpu_aux", - "qsb", + static struct clk_parent_data sec_mux_list[2] = { + { .name = "qsb", .fw_name = "qsb" }, + {}, }; struct clk_init_data init = { - .parent_names = sec_mux_list, + .parent_data = sec_mux_list, .num_parents = ARRAY_SIZE(sec_mux_list), .ops = &krait_mux_clk_ops, .flags = CLK_SET_RATE_PARENT, }; struct clk *clk; + char *parent_name; mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); if (!mux) - return -ENOMEM; + return ERR_PTR(-ENOMEM); mux->offset = offset; mux->lpl = id >= 0; @@ -141,44 +148,51 @@ krait_add_sec_mux(struct device *dev, int id, const char *s, init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); if (!init.name) - return -ENOMEM; + return ERR_PTR(-ENOMEM); if (unique_aux) { - sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s); - if (!sec_mux_list[0]) { + parent_name = kasprintf(GFP_KERNEL, "acpu%s_aux", s); + if (!parent_name) { clk = ERR_PTR(-ENOMEM); goto err_aux; } + sec_mux_list[1].fw_name = parent_name; + sec_mux_list[1].name = parent_name; + } else { + sec_mux_list[1].name = "apu_aux"; } clk = devm_clk_register(dev, &mux->hw); + if (IS_ERR(clk)) + goto err_clk; ret = krait_notifier_register(dev, clk, mux); if (ret) - goto unique_aux; + clk = ERR_PTR(ret); -unique_aux: +err_clk: if (unique_aux) - kfree(sec_mux_list[0]); + kfree(parent_name); err_aux: kfree(init.name); - return PTR_ERR_OR_ZERO(clk); + return clk; } static struct clk * -krait_add_pri_mux(struct device *dev, int id, const char *s, - unsigned int offset) +krait_add_pri_mux(struct device *dev, struct clk *hfpll_div, struct clk *sec_mux, + int id, const char *s, unsigned int offset) { int ret; struct krait_mux_clk *mux; - const char *p_names[3]; + static struct clk_parent_data p_data[3]; struct clk_init_data init = { - .parent_names = p_names, - .num_parents = ARRAY_SIZE(p_names), + .parent_data = p_data, + .num_parents = ARRAY_SIZE(p_data), .ops = &krait_mux_clk_ops, .flags = CLK_SET_RATE_PARENT, }; struct clk *clk; + char *hfpll_name; mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); if (!mux) @@ -196,36 +210,29 @@ krait_add_pri_mux(struct device *dev, int id, const char *s, if (!init.name) return ERR_PTR(-ENOMEM); - p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s); - if (!p_names[0]) { + hfpll_name = kasprintf(GFP_KERNEL, "hfpll%s", s); + if (!hfpll_name) { clk = ERR_PTR(-ENOMEM); - goto err_p0; + goto err_hfpll; } - p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s); - if (!p_names[1]) { - clk = ERR_PTR(-ENOMEM); - goto err_p1; - } + p_data[0].fw_name = hfpll_name; + p_data[0].name = hfpll_name; - p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); - if (!p_names[2]) { - clk = ERR_PTR(-ENOMEM); - goto err_p2; - } + p_data[1].hw = __clk_get_hw(hfpll_div); + p_data[2].hw = __clk_get_hw(sec_mux); clk = devm_clk_register(dev, &mux->hw); + if (IS_ERR(clk)) + goto err_clk; ret = krait_notifier_register(dev, clk, mux); if (ret) - goto err_p3; -err_p3: - kfree(p_names[2]); -err_p2: - kfree(p_names[1]); -err_p1: - kfree(p_names[0]); -err_p0: + clk = ERR_PTR(ret); + +err_clk: + kfree(hfpll_name); +err_hfpll: kfree(init.name); return clk; } @@ -233,11 +240,10 @@ krait_add_pri_mux(struct device *dev, int id, const char *s, /* id < 0 for L2, otherwise id == physical CPU number */ static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux) { - int ret; unsigned int offset; void *p = NULL; const char *s; - struct clk *clk; + struct clk *hfpll_div, *sec_mux, *clk; if (id >= 0) { offset = 0x4501 + (0x1000 * id); @@ -249,19 +255,19 @@ static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux) s = "_l2"; } - ret = krait_add_div(dev, id, s, offset); - if (ret) { - clk = ERR_PTR(ret); + hfpll_div = krait_add_div(dev, id, s, offset); + if (IS_ERR(hfpll_div)) { + clk = hfpll_div; goto err; } - ret = krait_add_sec_mux(dev, id, s, offset, unique_aux); - if (ret) { - clk = ERR_PTR(ret); + sec_mux = krait_add_sec_mux(dev, id, s, offset, unique_aux); + if (IS_ERR(sec_mux)) { + clk = sec_mux; goto err; } - clk = krait_add_pri_mux(dev, id, s, offset); + clk = krait_add_pri_mux(dev, hfpll_div, sec_mux, id, s, offset); err: kfree(p); return clk; From patchwork Sun Mar 20 11:34:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 553234 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B84BFC35280 for ; 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[93.42.69.170]) by smtp.googlemail.com with ESMTPSA id y6-20020a05600015c600b00203fa70b4ebsm6760085wry.53.2022.03.20.09.28.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Mar 2022 09:28:21 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 10/18] clk: qcom: krait-cc: drop hardcoded safe_sel Date: Sun, 20 Mar 2022 12:34:22 +0100 Message-Id: <20220320113430.26076-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220320113430.26076-1-ansuelsmth@gmail.com> References: <20220320113430.26076-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Drop hardcoded safe_sel definition and use helper to correctly calculate it. We assume qsb clk is always present as it should be declared in DTS per Documentation and in the absence of that, it's declared as a fixed clk. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/krait-cc.c | 40 +++++++++++++++++++++++++------------ 1 file changed, 27 insertions(+), 13 deletions(-) diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index e9508e3104ea..5f98ee1c3681 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -26,6 +26,17 @@ static unsigned int pri_mux_map[] = { 0, }; +static u8 krait_get_mux_sel(struct krait_mux_clk *mux, struct clk *safe_clk) +{ + struct clk_hw *safe_hw = __clk_get_hw(safe_clk); + + /* + * We can ignore errors from clk_hw_get_index_of_parent() + * as we create these parents in this driver. + */ + return clk_hw_get_index_of_parent(&mux->hw, safe_hw); +} + /* * Notifier function for switching the muxes to safe parent * while the hfpll is getting reprogrammed. @@ -116,8 +127,8 @@ krait_add_div(struct device *dev, int id, const char *s, unsigned int offset) } static struct clk * -krait_add_sec_mux(struct device *dev, int id, const char *s, - unsigned int offset, bool unique_aux) +krait_add_sec_mux(struct device *dev, struct clk *qsb, int id, + const char *s, unsigned int offset, bool unique_aux) { int ret; struct krait_mux_clk *mux; @@ -144,7 +155,6 @@ krait_add_sec_mux(struct device *dev, int id, const char *s, mux->shift = 2; mux->parent_map = sec_mux_map; mux->hw.init = &init; - mux->safe_sel = 0; init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); if (!init.name) @@ -166,6 +176,7 @@ krait_add_sec_mux(struct device *dev, int id, const char *s, if (IS_ERR(clk)) goto err_clk; + mux->safe_sel = krait_get_mux_sel(mux, qsb); ret = krait_notifier_register(dev, clk, mux); if (ret) clk = ERR_PTR(ret); @@ -204,7 +215,6 @@ krait_add_pri_mux(struct device *dev, struct clk *hfpll_div, struct clk *sec_mux mux->lpl = id >= 0; mux->parent_map = pri_mux_map; mux->hw.init = &init; - mux->safe_sel = 2; init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s); if (!init.name) @@ -226,6 +236,7 @@ krait_add_pri_mux(struct device *dev, struct clk *hfpll_div, struct clk *sec_mux if (IS_ERR(clk)) goto err_clk; + mux->safe_sel = krait_get_mux_sel(mux, sec_mux); ret = krait_notifier_register(dev, clk, mux); if (ret) clk = ERR_PTR(ret); @@ -238,7 +249,9 @@ krait_add_pri_mux(struct device *dev, struct clk *hfpll_div, struct clk *sec_mux } /* id < 0 for L2, otherwise id == physical CPU number */ -static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux) +static struct clk * +krait_add_clks(struct device *dev, struct clk *qsb, int id, + bool unique_aux) { unsigned int offset; void *p = NULL; @@ -261,7 +274,7 @@ static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux) goto err; } - sec_mux = krait_add_sec_mux(dev, id, s, offset, unique_aux); + sec_mux = krait_add_sec_mux(dev, qsb, id, s, offset, unique_aux); if (IS_ERR(sec_mux)) { clk = sec_mux; goto err; @@ -301,18 +314,19 @@ static int krait_cc_probe(struct platform_device *pdev) int cpu; struct clk *clk; struct clk **clks; - struct clk *l2_pri_mux_clk; + struct clk *l2_pri_mux_clk, *qsb; id = of_match_device(krait_cc_match_table, dev); if (!id) return -ENODEV; /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */ - if (IS_ERR(clk_get(dev, "qsb"))) - clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); + qsb = clk_get(dev, "qsb"); + if (IS_ERR(qsb)) + qsb = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); - if (IS_ERR(clk)) - return PTR_ERR(clk); + if (IS_ERR(qsb)) + return PTR_ERR(qsb); if (!id->data) { clk = clk_register_fixed_factor(dev, "acpu_aux", @@ -327,13 +341,13 @@ static int krait_cc_probe(struct platform_device *pdev) return -ENOMEM; for_each_possible_cpu(cpu) { - clk = krait_add_clks(dev, cpu, id->data); + clk = krait_add_clks(dev, qsb, cpu, id->data); if (IS_ERR(clk)) return PTR_ERR(clk); clks[cpu] = clk; } - l2_pri_mux_clk = krait_add_clks(dev, -1, id->data); + l2_pri_mux_clk = krait_add_clks(dev, qsb, -1, id->data); if (IS_ERR(l2_pri_mux_clk)) return PTR_ERR(l2_pri_mux_clk); clks[4] = l2_pri_mux_clk; From patchwork Sun Mar 20 11:34:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 553233 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 916BFC433F5 for ; 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[93.42.69.170]) by smtp.googlemail.com with ESMTPSA id y6-20020a05600015c600b00203fa70b4ebsm6760085wry.53.2022.03.20.09.28.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Mar 2022 09:28:24 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 12/18] clk: qcom: clk-krait: add apq/ipq8064 errata workaround Date: Sun, 20 Mar 2022 12:34:24 +0100 Message-Id: <20220320113430.26076-13-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220320113430.26076-1-ansuelsmth@gmail.com> References: <20220320113430.26076-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add apq/ipq8064 errata workaround where the sec_src clock gating needs to be disabled during switching. To enable this set disable_sec_src_gating in the mux struct. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/clk-krait.c | 16 ++++++++++++++++ drivers/clk/qcom/clk-krait.h | 1 + drivers/clk/qcom/krait-cc.c | 1 + 3 files changed, 18 insertions(+) diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c index b6b7650dbf15..7ba5dbc72bce 100644 --- a/drivers/clk/qcom/clk-krait.c +++ b/drivers/clk/qcom/clk-krait.c @@ -18,13 +18,23 @@ static DEFINE_SPINLOCK(krait_clock_reg_lock); #define LPL_SHIFT 8 +#define SECCLKAGD BIT(4) + static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel) { unsigned long flags; u32 regval; spin_lock_irqsave(&krait_clock_reg_lock, flags); + regval = krait_get_l2_indirect_reg(mux->offset); + + /* apq/ipq8064 Errata: disable sec_src clock gating during switch. */ + if (mux->disable_sec_src_gating) { + regval |= SECCLKAGD; + krait_set_l2_indirect_reg(mux->offset, regval); + } + regval &= ~(mux->mask << mux->shift); regval |= (sel & mux->mask) << mux->shift; if (mux->lpl) { @@ -33,6 +43,12 @@ static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel) } krait_set_l2_indirect_reg(mux->offset, regval); + /* apq/ipq8064 Errata: re-enabled sec_src clock gating. */ + if (mux->disable_sec_src_gating) { + regval &= ~SECCLKAGD; + krait_set_l2_indirect_reg(mux->offset, regval); + } + /* Wait for switch to complete. */ mb(); udelay(1); diff --git a/drivers/clk/qcom/clk-krait.h b/drivers/clk/qcom/clk-krait.h index 9120bd2f5297..f930538c539e 100644 --- a/drivers/clk/qcom/clk-krait.h +++ b/drivers/clk/qcom/clk-krait.h @@ -15,6 +15,7 @@ struct krait_mux_clk { u8 safe_sel; u8 old_index; bool reparent; + bool disable_sec_src_gating; struct clk_hw hw; struct notifier_block clk_nb; diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index 299eb4c81d96..cb8b267f1dc5 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -157,6 +157,7 @@ krait_add_sec_mux(struct device *dev, struct clk *qsb, int id, mux->shift = 2; mux->parent_map = sec_mux_map; mux->hw.init = &init; + mux->disable_sec_src_gating = true; init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); if (!init.name) From patchwork Sun Mar 20 11:34:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 553232 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5C75C433EF for ; Sun, 20 Mar 2022 16:28:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245598AbiCTQaE (ORCPT ); Sun, 20 Mar 2022 12:30:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245557AbiCTQ3z (ORCPT ); Sun, 20 Mar 2022 12:29:55 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 665923585B; Sun, 20 Mar 2022 09:28:28 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id j10so4786862wrb.13; Sun, 20 Mar 2022 09:28:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Uw2FgXL2MG6c1O6jLTs0CVZuitMyMBRaze5ZuwDxY6M=; b=MlcxB5b6b6VXQQFL4W/XmzxZwI1BpuQNepAMcrLZAhfmZZRhm1j1W6jChuCiwZ50Fw Mb3IVa66bZUPLCi4X7WRw/hcAflBCE2r2dKnKcAdRGfgMScfi/JYhtpD+O0JhspS4xwk yn8tusbHISLjtvBd8hF16y+TmTZ5OJ8IOT7dbh/OnLawNn4cAEQadxuHHXGIxN5DdR0C A/XW0tp7jmBMU3sBEOMjsohrazOlB37opjvsftWsShWGnHz+1g5g9ULOHRp9Zj6K1xd2 onR0GxF1ccM4Fi22Pz01YsM9sMIoBAsniaUD7CSZYQR9Yvjtq4DI29kf1e7BfDvemwsu d+Jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Uw2FgXL2MG6c1O6jLTs0CVZuitMyMBRaze5ZuwDxY6M=; b=sZld4a6u/okxgmQX8XBs8/IB8AfTvl13d0yCJFLQ/QtcjekTjHdyDb0W6Fl5z4px2z 46ebTShbb5MiwdBOOFnZyBsTh6u6yYgcIYCvzP8h58h1vXsS0a5hu513Nha4FtjI2Y5Q OzSJSa9eWPsNbT+XQvbNNIKplog08wnd5r6jkpc4RMWoDAFbODhnSnvIjty6DVl5XmKc 6i0DRSXq9yXaj/gnNoeDQS3X51Am8nOblf6R1pdFIqtvhL88oADP+8Mn8KrBnFjMA12M Qzisqu6+uqGfvKRth4s8m//5vNiDaPHSzq0eQ2NapejWIhaZg3VM7KM59Vqsuo5FV/RO p8hw== X-Gm-Message-State: AOAM533w0RaubIp41YrIc2bD0tjBBYtj9DTg56lfxjBti6t/WS96x/xN ccNU2FL8KbFYUx+CqCN9wrk= X-Google-Smtp-Source: ABdhPJxuN/CtqeHIEo6ox/UTDdleHxTwkFNSSbvHF/17UR/qoDBoag9oEwXwNDgCcK4K+MmQ2aMlTA== X-Received: by 2002:a05:6000:1ace:b0:203:d465:1a83 with SMTP id i14-20020a0560001ace00b00203d4651a83mr15195713wry.26.1647793706671; Sun, 20 Mar 2022 09:28:26 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id y6-20020a05600015c600b00203fa70b4ebsm6760085wry.53.2022.03.20.09.28.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Mar 2022 09:28:26 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 14/18] dt-bindings: clock: Convert qcom,krait-cc to yaml Date: Sun, 20 Mar 2022 12:34:26 +0100 Message-Id: <20220320113430.26076-15-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220320113430.26076-1-ansuelsmth@gmail.com> References: <20220320113430.26076-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert qcom,krait-cc to yaml Documentation. Signed-off-by: Ansuel Smith --- .../bindings/clock/qcom,krait-cc.txt | 34 ----------- .../bindings/clock/qcom,krait-cc.yaml | 59 +++++++++++++++++++ 2 files changed, 59 insertions(+), 34 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt deleted file mode 100644 index 030ba60dab08..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt +++ /dev/null @@ -1,34 +0,0 @@ -Krait Clock Controller - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,krait-cc-v1" - "qcom,krait-cc-v2" - -- #clock-cells: - Usage: required - Value type: - Definition: must be 1 - -- clocks: - Usage: required - Value type: - Definition: reference to the clock parents of hfpll, secondary muxes. - -- clock-names: - Usage: required - Value type: - Definition: must be "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb". - -Example: - - kraitcc: clock-controller { - compatible = "qcom,krait-cc-v1"; - clocks = <&hfpll0>, <&hfpll1>, <&acpu0_aux>, <&acpu1_aux>, ; - clock-names = "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb"; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml b/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml new file mode 100644 index 000000000000..3223fce915bb --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,krait-cc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Krait Clock Controller + +maintainers: + - Ansuel Smith + +description: | + Qualcomm Krait Clock Controller used to correctly scale the CPU and the L2 + rates. + +properties: + compatible: + enum: + - qcom,krait-cc-v1 + - qcom,krait-cc-v2 + + clocks: + items: + - description: phandle to hfpll for CPU0 mux + - description: phandle to hfpll for CPU1 mux + - description: phandle to CPU0 aux clock + - description: phandle to CPU1 aux clock + - description: phandle to QSB fixed clk + + clock-names: + items: + - const: hfpll0 + - const: hfpll1 + - const: acpu0_aux + - const: acpu1_aux + - const: qsb + + '#clock-cells': + const: 1 + +required: + - compatible + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller { + compatible = "qcom,krait-cc-v1"; + clocks = <&hfpll0>, <&hfpll1>, <&hfpll_l2>, + <&acpu0_aux>, <&acpu1_aux>, <&acpu_l2_aux>, <&qsb>; + clock-names = "hfpll0", "hfpll1", + "acpu0_aux", "acpu1_aux", "qsb"; + #clock-cells = <1>; + }; +... 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[93.42.69.170]) by smtp.googlemail.com with ESMTPSA id y6-20020a05600015c600b00203fa70b4ebsm6760085wry.53.2022.03.20.09.28.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Mar 2022 09:28:28 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 16/18] ARM: dts: qcom: qcom-ipq8064: add missing krait-cc compatible and clocks Date: Sun, 20 Mar 2022 12:34:28 +0100 Message-Id: <20220320113430.26076-17-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220320113430.26076-1-ansuelsmth@gmail.com> References: <20220320113430.26076-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add missing krait-cc clock-controller and define missing aux clock for CPUs. Also change phandle for l2cc node to point to pxo_board instead of gcc PXO_SRC. Signed-off-by: Ansuel Smith --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 996f4458d9fc..888f17d64283 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -468,11 +468,19 @@ IRQ_TYPE_EDGE_RISING)>, acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu0_aux"; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + #clock-cells = <0>; }; acc1: clock-controller@2098000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu1_aux"; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + #clock-cells = <0>; }; adm_dma: dma-controller@18300000 { @@ -782,11 +790,21 @@ tcsr: syscon@1a400000 { l2cc: clock-controller@2011000 { compatible = "qcom,kpss-gcc", "syscon"; reg = <0x2011000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; clock-names = "pll8_vote", "pxo"; clock-output-names = "acpu_l2_aux"; }; + kraitcc: clock-controller { + compatible = "qcom,krait-cc-v1"; + clocks = <&gcc PLL9>, <&gcc PLL10>, <&gcc PLL12>, + <&acc0>, <&acc1>, <&l2cc>, <&qsb>; + clock-names = "hfpll0", "hfpll1", "hfpll_l2", + "acpu0_aux", "acpu1_aux", "acpu_l2_aux", + "qsb"; + #clock-cells = <1>; + }; + lcc: clock-controller@28000000 { compatible = "qcom,lcc-ipq8064"; reg = <0x28000000 0x1000>; From patchwork Sun Mar 20 11:34:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 553230 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 256F7C433EF for ; Sun, 20 Mar 2022 16:28:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245584AbiCTQaN (ORCPT ); Sun, 20 Mar 2022 12:30:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245585AbiCTQaD (ORCPT ); Sun, 20 Mar 2022 12:30:03 -0400 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4B0134656; Sun, 20 Mar 2022 09:28:32 -0700 (PDT) Received: by mail-wm1-x32b.google.com with SMTP id bg31-20020a05600c3c9f00b00381590dbb33so7222886wmb.3; Sun, 20 Mar 2022 09:28:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=bUbi/jkzYIKSOu8T7OV/skgoIWQk4BHawXnXdm1xB5I=; b=QBfsjPV1XhoP5TR9nsbodr4/tWA62M6TCQ+D/v4Rrlnr0Opm3EEHHihqX0tPW+Jfqm OQs6vgTDFJcfW0rEm9mDlhIkg1MMLfwW9WjuwoUSLi4pGhYBdaWXOzMTAsoZ+aTKg3zZ kpQKsf01ab1ZKflLaRWZEgC8sAPL4V4YHziilfXjgo/wkzqUqGy1QJHvMMMwrRXJ6vj5 MbWwBLmaqX5PLtdjzafeVHC07m2GBxQ/Ahl+1v7rOzufYaGxk7EArv+r/XsoDtKEoEIh x2GnJ6zvHJuqXIXWNt135+62fZT/11VboelJWlqmPt6ndE6HD02HnsWX/wq3GAdu85Gn JFGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bUbi/jkzYIKSOu8T7OV/skgoIWQk4BHawXnXdm1xB5I=; b=ZZXxs/nCM8pCByfwOc+Dp2a18PLc1yZZVq1kKrWkg+mboiCwjTYPrnGOhEeW1ikdEx bm6qItVZ/QCa6XNuo3RqGjqKR/azKIInXhX2KXQ948FAnUnuTLnhbiTsEmCBk+SD8A7g FNf0BRQ/rIsH0LK9pU1msQMmBHWpKBjOEFVx3/xGY4BhHThVoOM7Mv4bjpn9T8zFN0Qb LABDvJ1YMGEqZ1IJrFISSUtjja9onL80WPUVJYjFtICxOGVrFAKriJgPHk05bn34MVZe 76X8S2te7tTwI1EcLToR1t/yzIIr/viiPecT49SaNytTaiOqQGwJ2vDYsywYk5ZNA2ge RvrA== X-Gm-Message-State: AOAM531oXSJqeZd6p4WHe+mK+GMh+sbaxGle7NQOwbIz5StWhKLEpS4P m3u+04FWVARnxVVRS2P85mo= X-Google-Smtp-Source: ABdhPJxQEeFWTDjt9U0eUu1Y+jsiC77yc6QUch/tNSKtkN/tpZTxvIGkyhsnawpJHsgdcwmo9KYENA== X-Received: by 2002:a05:600c:4142:b0:38c:9dc6:c87a with SMTP id h2-20020a05600c414200b0038c9dc6c87amr3628753wmm.114.1647793710898; Sun, 20 Mar 2022 09:28:30 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-69-170.ip85.fastwebnet.it. [93.42.69.170]) by smtp.googlemail.com with ESMTPSA id y6-20020a05600015c600b00203fa70b4ebsm6760085wry.53.2022.03.20.09.28.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Mar 2022 09:28:30 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 18/18] dt-bindings: arm: msm: Convert kpss-gcc driver Documentation to yaml Date: Sun, 20 Mar 2022 12:34:30 +0100 Message-Id: <20220320113430.26076-19-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220320113430.26076-1-ansuelsmth@gmail.com> References: <20220320113430.26076-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert kpss-gcc driver Documentation to yaml. Signed-off-by: Ansuel Smith --- .../bindings/arm/msm/qcom,kpss-gcc.txt | 44 ------------ .../bindings/arm/msm/qcom,kpss-gcc.yaml | 68 +++++++++++++++++++ 2 files changed, 68 insertions(+), 44 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.yaml diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt deleted file mode 100644 index e628758950e1..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt +++ /dev/null @@ -1,44 +0,0 @@ -Krait Processor Sub-system (KPSS) Global Clock Controller (GCC) - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: should be one of the following. The generic compatible - "qcom,kpss-gcc" should also be included. - "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc" - "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc" - "qcom,kpss-gcc-msm8974", "qcom,kpss-gcc" - "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc" - -- reg: - Usage: required - Value type: - Definition: base address and size of the register region - -- clocks: - Usage: required - Value type: - Definition: reference to the pll parents. - -- clock-names: - Usage: required - Value type: - Definition: must be "pll8_vote", "pxo". - -- clock-output-names: - Usage: required - Value type: - Definition: Name of the output clock. Typically acpu_l2_aux indicating - an L2 cache auxiliary clock. - -Example: - - l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"; - reg = <0x2011000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu_l2_aux"; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.yaml new file mode 100644 index 000000000000..351a88407f4b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/msm/qcom,kpss-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Krait Processor Sub-system (KPSS) Global Clock Controller (GCC) + +maintainers: + - Ansuel Smith + +description: | + Krait Processor Sub-system (KPSS) Global Clock Controller (GCC). Used + to control L2 mux (in the current implementation). + +properties: + compatible: + items: + - enum: + - qcom,kpss-gcc-ipq8064 + - qcom,kpss-gcc-apq8064 + - qcom,kpss-gcc-msm8974 + - qcom,kpss-gcc-msm8960 + - const: qcom,kpss-gcc + + reg: + maxItems: 1 + + clocks: + items: + - description: phandle to pll8_vote + - description: phandle to pxo_board + + clock-names: + items: + - const: pll8_vote + - const: pxo + + clock-output-names: + const: acpu_l2_aux + + '#clock-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - clock-output-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@2011000 { + compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"; + reg = <0x2011000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu_l2_aux"; + #clock-cells = <0>; + }; +... +