From patchwork Mon Dec 10 17:33:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153329 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3820876ljp; Mon, 10 Dec 2018 09:38:05 -0800 (PST) X-Google-Smtp-Source: AFSGD/VAmKlkYLAm40F9ZPEF+GOzEkOyc857Yuaaf8ruMhw3ibAYo97vJhHEKcXf/kP2xPeSL02F X-Received: by 2002:ac8:6606:: with SMTP id c6mr12757519qtp.376.1544463485781; Mon, 10 Dec 2018 09:38:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544463485; cv=none; d=google.com; s=arc-20160816; b=YULMBAlJhq267aiNDta9XPW8juu+1kU0y08G35Kqo5jLcLnQBPlOnKN6vql4hAtTAN +H75702FTlXG90USFjI6IjJD1GHyV0G0qpDWhXLfX47nPwMH+GW8sXJqAHLG3S8ebRT7 HNMBahsO+zt7G9P6uJBO9VM5tAYScgvL//1G9N4sAUd/MY6phi884ETWMAwDqK+0FhGO JJfATz1bE4UXDHznq5fTy1Zby4wAP1VNZvbgppnJm59V4VUFPkEjdS+tPEOskwkdh8J4 mDwljVS9XjPtnhzTDOQPuC4LVodgA9y8zwXdjesRepD4ROs5UFI3tmxtbX3TLYB6yW9r HRdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:message-id:date:to:from; bh=XrrvaNK5KSWO794UIa9YfLiwDTnI3zyl8SdKGJWMoTU=; b=FQNV3wdxmN5jGchRhMH3pc8A15qGqM1OX0jdzLgYOrfeMzJZ/alVapS3NlqK+d8Ugc F9vBe1i01kt+D+wPB3cH4CCpNbm9vjc8+0O/mYMr34ypfdpX+hsitALYGphEMsurOIvY OtnIw78tlJEK8RLfS/ho/h8T3qrUL20K6Q8ozOQGBF9wbahKG76MXMFEJD1Fg4jJdv5k aqx1zEIF8YnniT6c20bPuicICwVVbNHaxgIip6nWBetDMwAiWzwOip74uVlH8RZkzIn5 gWW3PiTHseKD26QPkgeULpB5IxZicK4LTzz2t4lcLeWMZELgZbvucYrpN67/Yi0QBAJ3 YfJA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id w123si2659908qka.53.2018.12.10.09.38.05 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 10 Dec 2018 09:38:05 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33986 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gWPVM-0003B6-QL for patch@linaro.org; Mon, 10 Dec 2018 12:38:04 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46613) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gWPRN-00080l-3f for qemu-devel@nongnu.org; Mon, 10 Dec 2018 12:33:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gWPRK-0004Pb-Ln for qemu-devel@nongnu.org; Mon, 10 Dec 2018 12:33:56 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:53448) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gWPRK-0004Oe-Cg for qemu-devel@nongnu.org; Mon, 10 Dec 2018 12:33:54 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gWPRH-0000QH-3P; Mon, 10 Dec 2018 17:33:51 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 10 Dec 2018 17:33:50 +0000 Message-Id: <20181210173350.13073-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [RFC] hw/alpha/typhoon: Stop calling cpu_unassigned_access() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , patches@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The typhoon MemoryRegionOps callbacks directly call cpu_unassigned_access(), presumably as the old-fashioned way to provoke a CPU exception. This won't work since commit 6ad4d7eed05a1e235 when we switched Alpha over to the transaction_failed hook API, because now cpu_unassigned_access() is a no-op for Alpha. Make the MemoryRegionOps callbacks use the read_with_attrs and write_with_attrs hooks, so they can signal a failure that should cause a CPU exception by returning MEMTX_ERROR. Signed-off-by: Peter Maydell --- RFC because untested, since I don't have an alpha test image. hw/alpha/typhoon.c | 47 ++++++++++++++++++++++++++-------------------- 1 file changed, 27 insertions(+), 20 deletions(-) -- 2.19.2 Tested-by: Richard Henderson Reviewed-by: Richard Henderson diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c index 8004afe45b3..cbacea5fbd8 100644 --- a/hw/alpha/typhoon.c +++ b/hw/alpha/typhoon.c @@ -75,7 +75,9 @@ static void cpu_irq_change(AlphaCPU *cpu, uint64_t req) } } -static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size) +static MemTxResult cchip_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) { CPUState *cpu = current_cpu; TyphoonState *s = opaque; @@ -196,11 +198,11 @@ static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size) break; default: - cpu_unassigned_access(cpu, addr, false, false, 0, size); - return -1; + return MEMTX_ERROR; } - return ret; + *data = ret; + return MEMTX_OK; } static uint64_t dchip_read(void *opaque, hwaddr addr, unsigned size) @@ -209,7 +211,8 @@ static uint64_t dchip_read(void *opaque, hwaddr addr, unsigned size) return 0; } -static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size) +static MemTxResult pchip_read(void *opaque, hwaddr addr, uint64_t *data, + unsigned size, MemTxAttrs attrs) { TyphoonState *s = opaque; uint64_t ret = 0; @@ -294,15 +297,16 @@ static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size) break; default: - cpu_unassigned_access(current_cpu, addr, false, false, 0, size); - return -1; + return MEMTX_ERROR; } - return ret; + *data = ret; + return MEMTX_OK; } -static void cchip_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) +static MemTxResult cchip_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) { TyphoonState *s = opaque; uint64_t oldval, newval; @@ -446,9 +450,10 @@ static void cchip_write(void *opaque, hwaddr addr, break; default: - cpu_unassigned_access(current_cpu, addr, true, false, 0, size); - return; + return MEMTX_ERROR; } + + return MEMTX_OK; } static void dchip_write(void *opaque, hwaddr addr, @@ -457,8 +462,9 @@ static void dchip_write(void *opaque, hwaddr addr, /* Skip this. It's all related to DRAM timing and setup. */ } -static void pchip_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) +static MemTxResult pchip_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) { TyphoonState *s = opaque; uint64_t oldval; @@ -553,14 +559,15 @@ static void pchip_write(void *opaque, hwaddr addr, break; default: - cpu_unassigned_access(current_cpu, addr, true, false, 0, size); - return; + return MEMTX_ERROR; } + + return MEMTX_OK; } static const MemoryRegionOps cchip_ops = { - .read = cchip_read, - .write = cchip_write, + .read_with_attrs = cchip_read, + .write_with_attrs = cchip_write, .endianness = DEVICE_LITTLE_ENDIAN, .valid = { .min_access_size = 8, @@ -587,8 +594,8 @@ static const MemoryRegionOps dchip_ops = { }; static const MemoryRegionOps pchip_ops = { - .read = pchip_read, - .write = pchip_write, + .read_with_attrs = pchip_read, + .write_with_attrs = pchip_write, .endianness = DEVICE_LITTLE_ENDIAN, .valid = { .min_access_size = 8,