From patchwork Mon Dec 10 17:56:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153335 Delivered-To: patches@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3837005ljp; Mon, 10 Dec 2018 09:56:31 -0800 (PST) X-Google-Smtp-Source: AFSGD/WKSfSfIr1Ady5XKYgUkAeVZXN1rY4yTeElrtQqLrAtEZ1m8lBtEebNWr/n4YXLLqxxOckw X-Received: by 2002:a05:6000:100f:: with SMTP id a15mr11211976wrx.298.1544464591553; Mon, 10 Dec 2018 09:56:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544464591; cv=none; d=google.com; s=arc-20160816; b=imbqjODCcbPan7SBTchMTikAsa6govVHA6I8BhbXJDroeg6GUHJAesuwTF51HEhjba QVm3lY+2EahuLY3WCqeO2OtvblqtvWV9dHsm7WFYxkuMChcJ6thla1Q19kGJmUkyhO4D qqdLdTRfm1+byhGS85xskUpa/08Jwsllr2YO0QTp7XCvTBUz4fTgRYQFiQcZZrDZr/a4 qKSay78xMVfpON85zKWI5aCaHc9eaT2KWu3+c325oN0elAGgl42z24LPbLXFtC1l6BV/ neGykqFGdjsbsSNNCLc18t7scGSOkxHE2M4FZQtPULBwLT/kSEh4pPaS9gzSkQ0P1Wt1 tWoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from; bh=aKb+GQ39qwbya/ILg9WAabF2JPUXpHiwE6tuYhLsxis=; b=pLyr3g776fXQE4lV+SuI9wAhW30RjG6oYUZ16qD5Xi/Ky3uYhJMZ0thg41JKBGAZx1 4Fpjw3lx53DPtal1j5WZUDjr7JrO19ulmhZoNfazBnFB/XnR/uY5Rk1o+3KvbkeibvOB IOPHOoDmO5DrwFAVCsP5A2qI9kzKxq+LGPanZkRsGTTpm9+akE42Ep8UVltPCU4X2jNg 3dQGPn+1prxqdGQ4NRzD5WjYV1d+ULsCtRe0Aqmq7MpokFgFPm58AlUyhmPT6MqyX87b Afc0vr0uDc6gcBz/Z0KjAjktMjNlDcwhXYN+I/oER4bupCa+40jkhPba1f7aJrcg+qmU 7doA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id q9si7687419wre.214.2018.12.10.09.56.31 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 Dec 2018 09:56:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gWPnC-0000U1-JG; Mon, 10 Dec 2018 17:56:30 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, "Edgar E. Iglesias" Subject: [RFC] target/microblaze: Switch to transaction_failed hook Date: Mon, 10 Dec 2018 17:56:30 +0000 Message-Id: <20181210175630.30643-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 MIME-Version: 1.0 Switch the microblaze target from the old unassigned_access hook to the transaction_failed hook. The notable difference is that rather than it being called for all physical memory accesses which fail (including those made by DMA devices or by the gdbstub), it is only called for those made by the CPU via its MMU. For microblaze this makes no difference because none of the target CPU code needs to make loads or stores by physical address. Signed-off-by: Peter Maydell --- A straightforward conversion, but tagged RFC because I don't have any microblaze test images and have tested only with "make check". target/microblaze/cpu.h | 7 ++++--- target/microblaze/cpu.c | 2 +- target/microblaze/op_helper.c | 20 ++++++++++---------- 3 files changed, 15 insertions(+), 14 deletions(-) -- 2.19.2 Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 3c4e0ba80ac..03ca91007d5 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -388,9 +388,10 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, } #if !defined(CONFIG_USER_ONLY) -void mb_cpu_unassigned_access(CPUState *cpu, hwaddr addr, - bool is_write, bool is_exec, int is_asi, - unsigned size); +void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, + unsigned size, MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr); #endif #endif diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 9b546a2c18e..49876b19b38 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -297,7 +297,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) #ifdef CONFIG_USER_ONLY cc->handle_mmu_fault = mb_cpu_handle_mmu_fault; #else - cc->do_unassigned_access = mb_cpu_unassigned_access; + cc->do_transaction_failed = mb_cpu_transaction_failed; cc->get_phys_page_debug = mb_cpu_get_phys_page_debug; #endif dc->vmsd = &vmstate_mb_cpu; diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 7cdbbcccaef..d25d3b626c8 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -486,18 +486,18 @@ void helper_mmu_write(CPUMBState *env, uint32_t ext, uint32_t rn, uint32_t v) mmu_write(env, ext, rn, v); } -void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr, - bool is_write, bool is_exec, int is_asi, - unsigned size) +void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, + unsigned size, MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr) { MicroBlazeCPU *cpu; CPUMBState *env; - - qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n", - addr, is_write ? 1 : 0, is_exec ? 1 : 0); - if (cs == NULL) { - return; - } + qemu_log_mask(CPU_LOG_INT, "Transaction failed: vaddr 0x%" VADDR_PRIx + " physaddr 0x" TARGET_FMT_plx "size %d access type %s\n", + addr, physaddr, size, + access_type == MMU_INST_FETCH ? "INST_FETCH" : + (access_type == MMU_DATA_LOAD ? "DATA_LOAD" : "DATA_STORE")); cpu = MICROBLAZE_CPU(cs); env = &cpu->env; if (!(env->sregs[SR_MSR] & MSR_EE)) { @@ -505,7 +505,7 @@ void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr, } env->sregs[SR_EAR] = addr; - if (is_exec) { + if (access_type == MMU_INST_FETCH) { if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) { env->sregs[SR_ESR] = ESR_EC_INSN_BUS; helper_raise_exception(env, EXCP_HW_EXCP);