From patchwork Mon Apr 4 06:40:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 556478 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F6DCC433F5 for ; Mon, 4 Apr 2022 06:40:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377511AbiDDGmU (ORCPT ); Mon, 4 Apr 2022 02:42:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237532AbiDDGmU (ORCPT ); Mon, 4 Apr 2022 02:42:20 -0400 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB18D2B246 for ; Sun, 3 Apr 2022 23:40:23 -0700 (PDT) Received: by mail-ej1-x631.google.com with SMTP id ot30so7841312ejb.12 for ; Sun, 03 Apr 2022 23:40:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=8gCgi9p6TQq4anxDc6yg6qvIn2LRBKe/bblZh/HGFbI=; b=D3wXcsYlnjTOFVZAZ55nRd97pR9b05nmrThFjbi/X+vRgaCEOgRUfOSYCQ/64n7ery xyXa+ZAxEX9u29ExhayG/++ZyLvlGDitznAuSsSZ0+PUC061DP7Elrw8YPW0HoIen2ZH ZehLlWOUgAqK+DDGnvje7RFhyh1WcguupVArAohM2LzTX1SQV5xE5N3XzGya7km/P76T IyESDXJsFeKcEJ96r0yhpJTJgdHtvF0XhfgUIRX/2UeeFIrhDaqQV4L0RGEAS3K6qWTo 7YnE6O/d3rAIR6lbsp76Ri3y0RNSdpw9VJqiCJLxN9jXGq/FJnZzqHmeZRXHWnamGDuy Pxyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=8gCgi9p6TQq4anxDc6yg6qvIn2LRBKe/bblZh/HGFbI=; b=DOShAvuGsMMgkGM3NibFxqLwfuVrFLORW5lDcehgrzrn7i/ipkiASgfWYS9TQBvzco BTfivAQSqFvzDHewCKGvnMI3MK/LaTnUIsuSnUBgWQL1LHRBImhJyPBTvDUNSSGSIMHH X9yNkZvsZgxyspwFmXTjbIB8UIVWmNKLn1TtCopPaE7JF/Li4dkAdBpJpWo7tV42seJB hYTSRiK+kENm2hMvk7dNsBRczF935YRiK6UsGE+GuJyM0DS4PsGvNfbPXovryd6N9ydu eVP/tBHvXISHcukF5XDLZjT+G94u0hWE8G7A1xlD/boo2+IZ6oEZYzNtNeETIQmwJMtX DLkg== X-Gm-Message-State: AOAM531uPvMtwpLpwkm/xSiU5MP/m8c2v8E7PxF7ML0axDmDDofWM5W7 OGvpZmRT1esWRZyJXiKdQvq4bQ== X-Google-Smtp-Source: ABdhPJxx4XA9m4Y0ezx+xMbqpjNDdZ4/b0rLJQGyTSRnV7VNL8h3tZTlWBj7fdxRpU/0WLK5BggX8g== X-Received: by 2002:a17:906:2f97:b0:6ce:3ef6:94be with SMTP id w23-20020a1709062f9700b006ce3ef694bemr9704339eji.136.1649054422386; Sun, 03 Apr 2022 23:40:22 -0700 (PDT) Received: from localhost.localdomain (xdsl-188-155-201-27.adslplus.ch. [188.155.201.27]) by smtp.gmail.com with ESMTPSA id i14-20020a50cfce000000b0041cbaba8743sm2676515edk.56.2022.04.03.23.40.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Apr 2022 23:40:21 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Mark Brown , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Cc: Kuldeep Singh , Krzysztof Kozlowski Subject: [PATCH v3 1/2] spi: dt-bindings: qcom,spi-geni-qcom: convert to dtschema Date: Mon, 4 Apr 2022 08:40:16 +0200 Message-Id: <20220404064017.68634-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Convert the GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) bindings to DT Schema. The original bindings in TXT were not complete, so add during conversion properties already used in DTS and/or in the driver: dmas, interconnects, operating points and power-domains. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring --- Changes since v2: 1. Drop reg-names. Changes since v1: 1. Correct $ref path and remove interconnect minItems (Kuldeep). 2. Remove child tpm device from example. 3. Pad reg hex addresses with 00. --- .../bindings/spi/qcom,spi-geni-qcom.txt | 39 ------ .../bindings/spi/qcom,spi-geni-qcom.yaml | 116 ++++++++++++++++++ 2 files changed, 116 insertions(+), 39 deletions(-) delete mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt deleted file mode 100644 index c8c1e913f4e7..000000000000 --- a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt +++ /dev/null @@ -1,39 +0,0 @@ -GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) - -The QUP v3 core is a GENI based AHB slave that provides a common data path -(an output FIFO and an input FIFO) for serial peripheral interface (SPI) -mini-core. - -SPI in master mode supports up to 50MHz, up to four chip selects, programmable -data path from 4 bits to 32 bits and numerous protocol variants. - -Required properties: -- compatible: Must contain "qcom,geni-spi". -- reg: Must contain SPI register location and length. -- interrupts: Must contain SPI controller interrupts. -- clock-names: Must contain "se". -- clocks: Serial engine core clock needed by the device. -- #address-cells: Must be <1> to define a chip select address on - the SPI bus. -- #size-cells: Must be <0>. - -SPI Controller nodes must be child of GENI based Qualcomm Universal -Peripharal. Please refer GENI based QUP wrapper controller node bindings -described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml. - -SPI slave nodes must be children of the SPI master node and conform to SPI bus -binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt. - -Example: - spi0: spi@a84000 { - compatible = "qcom,geni-spi"; - reg = <0xa84000 0x4000>; - interrupts = ; - clock-names = "se"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qup_1_spi_2_active>; - pinctrl-1 = <&qup_1_spi_2_sleep>; - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml new file mode 100644 index 000000000000..e2c7b934c50d --- /dev/null +++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/qcom,spi-geni-qcom.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) + +maintainers: + - Andy Gross + - Bjorn Andersson + - Krzysztof Kozlowski + +description: + The QUP v3 core is a GENI based AHB slave that provides a common data path + (an output FIFO and an input FIFO) for serial peripheral interface (SPI) + mini-core. + + SPI in master mode supports up to 50MHz, up to four chip selects, + programmable data path from 4 bits to 32 bits and numerous protocol variants. + + SPI Controller nodes must be child of GENI based Qualcomm Universal + Peripharal. Please refer GENI based QUP wrapper controller node bindings + described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml. + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + const: qcom,geni-spi + + clocks: + maxItems: 1 + + clock-names: + const: se + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: qup-core + - const: qup-config + + interrupts: + maxItems: 1 + + operating-points-v2: true + + power-domains: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + - interrupts + - reg + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0x00880000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + }; + + - | + #include + + spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0x00884000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi1_default>; + interrupts = ; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + }; From patchwork Mon Apr 4 06:40:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 556143 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05EEFC43217 for ; Mon, 4 Apr 2022 06:40:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377515AbiDDGmV (ORCPT ); Mon, 4 Apr 2022 02:42:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51372 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377508AbiDDGmU (ORCPT ); Mon, 4 Apr 2022 02:42:20 -0400 Received: from mail-ed1-x529.google.com (mail-ed1-x529.google.com [IPv6:2a00:1450:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D05942B244 for ; Sun, 3 Apr 2022 23:40:24 -0700 (PDT) Received: by mail-ed1-x529.google.com with SMTP id x20so1934565edi.12 for ; Sun, 03 Apr 2022 23:40:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aBZDFp5sBs6J3g/EbSOQZDxB8Eo5i8sxnYaCg1uwbEg=; b=wgg7ju3ElvWrT6cJjhmLfYxYRiDe9dwONdNcVNsWjgitTxkh+jv4A1Gy8ggvgum/jI v0M55S4lvjdwGAvtYDNJliPH9gPtNCTkZLODCjozOXPzv/lGEQebeK5YiZcktPWl4+gz /vNZhi6ZHkXxrKl+ew0pzV7Tx3hLmZTz2lckeT7GPm6FR2Ab/woZ9FT6yVo5Y4RWasUm OJ6ZaCd1Ku3EnYg4XH7XfJLl2TvZJbg0UPZGYEaQbAhzxUDGqlOFt3U+b5/ti+pGIlnJ ZaEYXZ0l30eUpv065UG/8UdHodq19smf58afb+TW7A40P5m4pAn8kRsHqQ3Wx6uJ1kwy wZ8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aBZDFp5sBs6J3g/EbSOQZDxB8Eo5i8sxnYaCg1uwbEg=; b=7cryfv/XxlUBI9aJ1+7gMq0i0hbzH1YiANeTFywsfZAXbT6oa/5z9mYWO+EwShABzW 4FcTFDWcOG9PZFJhwc84shTrv7ZPOeJ7J69rlYO3FJCEnAMEDkp/NSz35h4SoxQpwaHB f+Pf/OkchIPRR/6fFFDCrD6LEfsvXebQHMGcFvcstwmjo53kJHFNfYef6THBtgqHzBew Zfb+uk0W5gAAXTJRX5bFDt7JARXKGMwOEH8cfl5F8Np3Q0qMRv2RztPTpcxlrfkrepSS OleIwjz1/XA0Ib7QHfIHrSd5NrjnaBM7/SgCV0RN6zwrXXsUJGf4ZscXDqorELR7Ussk DkRg== X-Gm-Message-State: AOAM531DjbjMhwozq1F2vykYJ/ZVqVUCu24EuX68H/XcD0rO9jKmxox+ FYMack9hvn9vk+PhxPcVXZ6ZKA== X-Google-Smtp-Source: ABdhPJwLjXvgri1RM9eAm8lvCGBHie2/hsRTVk/DgPFdm/bBz5YZQF5gtz8n4QIxS0vPOxh4DYIKTw== X-Received: by 2002:a05:6402:278f:b0:41b:79b1:39b4 with SMTP id b15-20020a056402278f00b0041b79b139b4mr19057440ede.163.1649054423382; Sun, 03 Apr 2022 23:40:23 -0700 (PDT) Received: from localhost.localdomain (xdsl-188-155-201-27.adslplus.ch. [188.155.201.27]) by smtp.gmail.com with ESMTPSA id i14-20020a50cfce000000b0041cbaba8743sm2676515edk.56.2022.04.03.23.40.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Apr 2022 23:40:22 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Mark Brown , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Cc: Kuldeep Singh , Krzysztof Kozlowski Subject: [PATCH v3 2/2] dt-bindings: qcom: qcom, geni-se: refer to dtschema for SPI Date: Mon, 4 Apr 2022 08:40:17 +0200 Message-Id: <20220404064017.68634-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220404064017.68634-1-krzysztof.kozlowski@linaro.org> References: <20220404064017.68634-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org After adding DT schema for the SPI controller, the Qualcomm GENI Serial Engine QUP Wrapper Controller bindings can reference it directly for full schema validation. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Kuldeep Singh Reviewed-by: Rob Herring --- Changes since v2: 1. Add tag. Changes since v1: 1. None Patch depends on previous patch (DT schema conversion). --- .../bindings/soc/qcom/qcom,geni-se.yaml | 22 +------------------ 1 file changed, 1 insertion(+), 21 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml index 690ce6a355de..1bc12b6a7e01 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml @@ -103,27 +103,7 @@ patternProperties: supports up to 50MHz, up to four chip selects, programmable data path from 4 bits to 32 bits and numerous protocol variants. - $ref: /spi/spi-controller.yaml# - - properties: - compatible: - enum: - - qcom,geni-spi - - interrupts: - maxItems: 1 - - "#address-cells": - const: 1 - - "#size-cells": - const: 0 - - required: - - compatible - - interrupts - - "#address-cells" - - "#size-cells" + $ref: /schemas/spi/qcom,spi-geni-qcom.yaml# "i2c@[0-9a-f]+$": type: object