From patchwork Thu Apr 7 07:44:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincent Whitchurch X-Patchwork-Id: 558698 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E5DBC433F5 for ; Thu, 7 Apr 2022 07:44:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242079AbiDGHqr (ORCPT ); Thu, 7 Apr 2022 03:46:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59826 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242080AbiDGHqp (ORCPT ); Thu, 7 Apr 2022 03:46:45 -0400 Received: from smtp1.axis.com (smtp1.axis.com [195.60.68.17]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E309B201B3; Thu, 7 Apr 2022 00:44:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=axis.com; q=dns/txt; s=axis-central1; t=1649317485; x=1680853485; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vA3kixnFjao/9/fHNVBKrG7js6zXxb2/Djlg20H3FvE=; b=cXt2dZZiZX2S9nCWfCk5JC/4ZWuNU2Hohwnvt6+nNwMHZgpy1/jutTYC s/I4VPntNzz2ZhjhDEwz8VdT7E3TIzscwwgLFaf00xVnPmQN2YmiOn27l lm6opZufaG6KU4FPGDJG0Q2GGaDtw8IVFPZnkEvXQTWKSipPnuzje0Mqr 7oYGtF1wh3W6CtzoSsfm0HyYCDuerg4bwIj+1Fi5Py/ceOi/1Ww8aNhmq HmoWtCAv+b4iaBU1ZWBzq1YMrsmbnV+qeL0/QpeBhCXEqa0StVlgzN2HP 1+2VwsC4SkD/BOlCSLoIYXV2VKx83fNKgxi1xgxXomDUWfu2TyqhGK+ao A==; From: Vincent Whitchurch To: , , CC: , Vincent Whitchurch , , , , , , Subject: [PATCH v3 1/4] dt-bindings: timer: exynos4210-mct: Add ARTPEC-8 MCT support Date: Thu, 7 Apr 2022 09:44:29 +0200 Message-ID: <20220407074432.424578-2-vincent.whitchurch@axis.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220407074432.424578-1-vincent.whitchurch@axis.com> References: <20220407074432.424578-1-vincent.whitchurch@axis.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org The ARTPEC-8 has an MCT with 4 global and 8 local timer interrupts. The SoC has a quad-core Cortex-A53 and a single-core Cortex-A5 which share one MCT with one global and eight local timers. The Cortex-A53 and Cortex-A5 do not have cache-coherency between them, and therefore run two separate kernels. The Cortex-A53 boots first and starts the global free-running counter and also registers a clock events device using the global timer. (This global timer clock events is usually replaced by arch timer clock events for each of the cores.) When the A5 boots (via the A53), it should not use the global timer interrupts or write to the global timer registers. This is because even if there are four global comparators, the control bits for all four are in the same registers, and we would need to synchronize between the cpus. Instead, the global timer FRC (already started by the A53) should be used as the clock source, and one of the local timers which are not used by the A53 can be used for clock events on the A5. To support this hardware, add a compatible for the MCT as well as two new properties to describe the hardware-mandated sharing of the FRC and dedicating local timers to specific processors. Signed-off-by: Vincent Whitchurch --- Notes: v3: - Add all required bindings for ARTPEC-8 in one patch - Rename and split local-timer-only to samsung,local-timers and samsung,frc-shared - Restrict above properties to the ARTPEC-8 compatible. - Rewrite descriptions of properties to hopefully describe hardware. v2: - Use devicetree property instead of module parameter. .../timer/samsung,exynos4210-mct.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml index 1584944c7ac4..bcfc849ca087 100644 --- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml @@ -25,6 +25,7 @@ properties: - samsung,exynos4412-mct - items: - enum: + - axis,artpec8-mct - samsung,exynos3250-mct - samsung,exynos5250-mct - samsung,exynos5260-mct @@ -46,6 +47,19 @@ properties: reg: maxItems: 1 + samsung,frc-shared: + type: boolean + description: | + Indicates that the hardware requires that this processor share the + free-running counter with a different (main) processor. + + samsung,local-timers: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 16 + description: | + List of indices of local timers usable from this processor. + interrupts: description: | Interrupts should be put in specific order. This is, the local timer @@ -75,6 +89,17 @@ required: - reg allOf: + - if: + not: + properties: + compatible: + contains: + enum: + - axis,artpec8-mct + then: + properties: + samsung,local-timers: false + samsung,frc-shared: false - if: properties: compatible: @@ -102,6 +127,7 @@ allOf: compatible: contains: enum: + - axis,artpec8-mct - samsung,exynos5260-mct - samsung,exynos5420-mct - samsung,exynos5433-mct From patchwork Thu Apr 7 07:44:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincent Whitchurch X-Patchwork-Id: 558699 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3D7AC433F5 for ; Thu, 7 Apr 2022 07:44:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242070AbiDGHqo (ORCPT ); Thu, 7 Apr 2022 03:46:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59720 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242065AbiDGHqn (ORCPT ); Thu, 7 Apr 2022 03:46:43 -0400 Received: from smtp1.axis.com (smtp1.axis.com [195.60.68.17]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 979838A33E; Thu, 7 Apr 2022 00:44:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=axis.com; q=dns/txt; s=axis-central1; t=1649317484; x=1680853484; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3Nt6l/9HvPB8EWvbnvVd3ZZ20Hk+Zo41nv15TzjFgHI=; b=eHMph5qta/o1xIqnuaph6ezehu7sttEPWYYpgy+lMENpOvJ4lf9tLx9a RLbLnWyLYYSWV5fExZ5laiJvz+BZBcURMfDmqY69inf6e+J4PQ42bbYj+ v84fX4/XalidARPQuyd79CliEpQC6qayPdsX8K8Gj0gDlszPbIY/8aD76 7EpQ29tP5T/FqMcC40nxP9Z2jySLfoKrwheqsQhVCm9wr6E7bRbuDC5Up EqhG+K165HATWNpBUuNWXWT9qN0vq5Wqfpz4kJTkRfDgA7y4eAwaZvKPa Fjtnxxr8Ibpg5A335HzmehaAK0ZDraP2ozfGJapGVoU/Cv4S6HxH4YNoj g==; From: Vincent Whitchurch To: , , CC: , Vincent Whitchurch , , , , , , Subject: [PATCH v3 2/4] clocksource/drivers/exynos_mct: Support frc-shared property Date: Thu, 7 Apr 2022 09:44:30 +0200 Message-ID: <20220407074432.424578-3-vincent.whitchurch@axis.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220407074432.424578-1-vincent.whitchurch@axis.com> References: <20220407074432.424578-1-vincent.whitchurch@axis.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org When the FRC is shared with another main processor, the other processor is assumed to have started it and this processor should not write to the global registers. Signed-off-by: Vincent Whitchurch Reviewed-by: Krzysztof Kozlowski --- Notes: v3: - Split FRC sharing handling from local timer indices handling - Remove addition of global variable. drivers/clocksource/exynos_mct.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index f29c812b70c9..12023831dedf 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -233,9 +233,16 @@ static cycles_t exynos4_read_current_timer(void) } #endif -static int __init exynos4_clocksource_init(void) +static int __init exynos4_clocksource_init(bool frc_shared) { - exynos4_mct_frc_start(); + /* + * When the frc is shared, the main processer should have already + * turned it on and we shouldn't be writing to TCON. + */ + if (frc_shared) + mct_frc.resume = NULL; + else + exynos4_mct_frc_start(); #if defined(CONFIG_ARM) exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer; @@ -605,6 +612,7 @@ static int __init exynos4_timer_interrupts(struct device_node *np, static int __init mct_init_dt(struct device_node *np, unsigned int int_type) { + bool frc_shared = of_property_read_bool(np, "samsung,frc-shared"); int ret; ret = exynos4_timer_resources(np); @@ -615,10 +623,17 @@ static int __init mct_init_dt(struct device_node *np, unsigned int int_type) if (ret) return ret; - ret = exynos4_clocksource_init(); + ret = exynos4_clocksource_init(frc_shared); if (ret) return ret; + /* + * When the FRC is shared with a main processor, this secondary + * processor cannot use the global comparator. + */ + if (frc_shared) + return ret; + return exynos4_clockevent_init(); } From patchwork Thu Apr 7 07:44:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincent Whitchurch X-Patchwork-Id: 559115 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E353C4332F for ; Thu, 7 Apr 2022 07:44:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242072AbiDGHqp (ORCPT ); Thu, 7 Apr 2022 03:46:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242066AbiDGHqn (ORCPT ); Thu, 7 Apr 2022 03:46:43 -0400 Received: from smtp1.axis.com (smtp1.axis.com [195.60.68.17]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9804C8CCD7; Thu, 7 Apr 2022 00:44:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=axis.com; q=dns/txt; s=axis-central1; t=1649317484; x=1680853484; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mz29Z7g6XhZMBEyDRcC5tTyavLUBWPycQxmbBGsMjXg=; b=NyXR4hg5UcFB3Jv7w04WGn+Zyh4a3uzeRqCPECArNPc3PcUJ5Qwz0kbv xod9/rT7jlegJxPvIGgr1E5o1c7j6nkKSjRIVWZFLBx8Q/Ff67Cd21ne9 L5W/BAQmeSu9bMPI/T2wgp9E6pt1tHv0kmgdY2XeAv6GS/KmlFwTCN9c1 qljE/cYWvQCZ/xzlJdqw6VSvRzyEFg87GVAqPA51bxHISMOHX/4HxGRSm RcFkE4W8s68BnDiLeoIDgMBsFVHzSjLQpNQHNSdyrje76DGo+Ocl0dRcu HMMRXO+Pa6G85n3nL1FLexbn8FdnsNIKQR0XWsYijcTsxvOJoWEWJ/Bpd A==; From: Vincent Whitchurch To: , , CC: , Vincent Whitchurch , , , , , , Subject: [PATCH v3 3/4] clocksource/drivers/exynos_mct: Support local-timers property Date: Thu, 7 Apr 2022 09:44:31 +0200 Message-ID: <20220407074432.424578-4-vincent.whitchurch@axis.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220407074432.424578-1-vincent.whitchurch@axis.com> References: <20220407074432.424578-1-vincent.whitchurch@axis.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org If the device tree indicates that the hardware requires that the processor only use certain local timers, respect that. Signed-off-by: Vincent Whitchurch --- Notes: v3: - Use array in devicetree - Remove addition of global variable - Split out FRC sharing changes drivers/clocksource/exynos_mct.c | 51 ++++++++++++++++++++++++++++---- 1 file changed, 45 insertions(+), 6 deletions(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index 12023831dedf..4093a71ff618 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -33,7 +33,7 @@ #define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248) #define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C) #define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300) -#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x)) +#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * (x))) #define EXYNOS4_MCT_L_MASK (0xffffff00) #define MCT_L_TCNTB_OFFSET (0x00) @@ -66,6 +66,8 @@ #define MCT_L0_IRQ 4 /* Max number of IRQ as per DT binding document */ #define MCT_NR_IRQS 20 +/* Max number of local timers */ +#define MCT_NR_LOCAL (MCT_NR_IRQS - MCT_L0_IRQ) enum { MCT_INT_SPI, @@ -456,7 +458,6 @@ static int exynos4_mct_starting_cpu(unsigned int cpu) per_cpu_ptr(&percpu_mct_tick, cpu); struct clock_event_device *evt = &mevt->evt; - mevt->base = EXYNOS4_MCT_L_BASE(cpu); snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu); evt->name = mevt->name; @@ -528,7 +529,9 @@ static int __init exynos4_timer_resources(struct device_node *np) } static int __init exynos4_timer_interrupts(struct device_node *np, - unsigned int int_type) + unsigned int int_type, + u32 *local_idx, + size_t nr_local) { int nr_irqs, i, err, cpu; @@ -561,13 +564,19 @@ static int __init exynos4_timer_interrupts(struct device_node *np, } else { for_each_possible_cpu(cpu) { int mct_irq; + unsigned int irqidx; struct mct_clock_event_device *pcpu_mevt = per_cpu_ptr(&percpu_mct_tick, cpu); + if (cpu >= nr_local) + break; + + irqidx = MCT_L0_IRQ + local_idx[cpu]; + pcpu_mevt->evt.irq = -1; - if (MCT_L0_IRQ + cpu >= ARRAY_SIZE(mct_irqs)) + if (irqidx >= ARRAY_SIZE(mct_irqs)) break; - mct_irq = mct_irqs[MCT_L0_IRQ + cpu]; + mct_irq = mct_irqs[irqidx]; irq_set_status_flags(mct_irq, IRQ_NOAUTOEN); if (request_irq(mct_irq, @@ -583,6 +592,15 @@ static int __init exynos4_timer_interrupts(struct device_node *np, } } + for_each_possible_cpu(cpu) { + struct mct_clock_event_device *mevt = per_cpu_ptr(&percpu_mct_tick, cpu); + + if (cpu >= nr_local) + break; + + mevt->base = EXYNOS4_MCT_L_BASE(local_idx[cpu]); + } + /* Install hotplug callbacks which configure the timer on this CPU */ err = cpuhp_setup_state(CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING, "clockevents/exynos4/mct_timer:starting", @@ -613,13 +631,34 @@ static int __init exynos4_timer_interrupts(struct device_node *np, static int __init mct_init_dt(struct device_node *np, unsigned int int_type) { bool frc_shared = of_property_read_bool(np, "samsung,frc-shared"); + u32 local_idx[MCT_NR_LOCAL] = {0}; + int nr_local; int ret; + nr_local = of_property_count_u32_elems(np, "samsung,local-timers"); + if (nr_local == 0) + return -EINVAL; + if (nr_local > 0) { + if (nr_local > ARRAY_SIZE(local_idx)) + return -EINVAL; + + ret = of_property_read_u32_array(np, "samsung,local-timers", + local_idx, nr_local); + if (ret) + return ret; + } else { + int i; + + nr_local = ARRAY_SIZE(local_idx); + for (i = 0; i < nr_local; i++) + local_idx[i] = i; + } + ret = exynos4_timer_resources(np); if (ret) return ret; - ret = exynos4_timer_interrupts(np, int_type); + ret = exynos4_timer_interrupts(np, int_type, local_idx, nr_local); if (ret) return ret; From patchwork Thu Apr 7 07:44:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincent Whitchurch X-Patchwork-Id: 558700 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32D81C433F5 for ; Thu, 7 Apr 2022 07:44:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232490AbiDGHqm (ORCPT ); Thu, 7 Apr 2022 03:46:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242070AbiDGHql (ORCPT ); Thu, 7 Apr 2022 03:46:41 -0400 Received: from smtp1.axis.com (smtp1.axis.com [195.60.68.17]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27A8127CD0; Thu, 7 Apr 2022 00:44:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=axis.com; q=dns/txt; s=axis-central1; t=1649317481; x=1680853481; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9o4101lhSUaQUglAFx0wOW4oYv+E/yNVxgL5P9cf4Zo=; b=VJrOk/7EUbpRczszWKSuBwyZfGY9EcYvbqFGFFRedxfiEhuviuhmBBJh XkIqP39evglXV/VG2X5UqeTwoC2iXS2gT+h4/mNPyQPWP2XvgFA9Q4sY+ eh3UUy6If3DB/dpupc0m/LQ6gOEZXIYPoLC+MH68cUBqqstcJ50ut6Fem qptQw6Qbu1o7gqqHHRylaCpsxqCv5eOeK6rNOxNbU14m85+kU25ajr52K DtE8t92CoxjuswbiHJOm6CFVfBNlHV8qYSGPX5IfdGEaP4kyV8PEfNKn3 O9pUJGbKribV729GdNV9kVhH5z/Yl/zFwKnwrrX0HCsCgN47GZ6OwpGEg A==; From: Vincent Whitchurch To: , , CC: , Vincent Whitchurch , , , , , , , Krzysztof Kozlowski Subject: [PATCH v3 4/4] clocksource/drivers/exynos_mct: Enable building on ARTPEC Date: Thu, 7 Apr 2022 09:44:32 +0200 Message-ID: <20220407074432.424578-5-vincent.whitchurch@axis.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220407074432.424578-1-vincent.whitchurch@axis.com> References: <20220407074432.424578-1-vincent.whitchurch@axis.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This timer block is used on ARTPEC-8. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Vincent Whitchurch --- Notes: v3: - Add Krzysztof's Reviewed-by. drivers/clocksource/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index ae95d06a4a8f..2ea981ef23af 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -419,7 +419,7 @@ config ATMEL_TCB_CLKSRC config CLKSRC_EXYNOS_MCT bool "Exynos multi core timer driver" if COMPILE_TEST depends on ARM || ARM64 - depends on ARCH_EXYNOS || COMPILE_TEST + depends on ARCH_ARTPEC || ARCH_EXYNOS || COMPILE_TEST help Support for Multi Core Timer controller on Exynos SoCs.