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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.15.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:15:55 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 01/41] hw/intc/arm_gicv3_its: Add missing blank line Date: Fri, 8 Apr 2022 15:15:10 +0100 Message-Id: <20220408141550.1271295-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In commit b6f96009acc we split do_process_its_cmd() from process_its_cmd(), but forgot the usual blank line between function definitions. Add it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_its.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index 87466732139..44914f25780 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -380,6 +380,7 @@ static ItsCmdResult do_process_its_cmd(GICv3ITSState *s, uint32_t devid, } return CMD_CONTINUE; } + static ItsCmdResult process_its_cmd(GICv3ITSState *s, const uint64_t *cmdpkt, ItsCmdType cmd) { From patchwork Fri Apr 8 14:15:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558808 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp365109map; Fri, 8 Apr 2022 07:20:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwEh15shBQSlpblnXTBTG1Po/4+jUDKWtXCbdDkAqH7iDRJEgcW590bjliTHT6rFlJgMT1u X-Received: by 2002:a25:8708:0:b0:63d:ab3f:c39d with SMTP id a8-20020a258708000000b0063dab3fc39dmr14165185ybl.94.1649427601343; Fri, 08 Apr 2022 07:20:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649427601; cv=none; d=google.com; s=arc-20160816; b=iZ418JGG8cHV0PHXSw1HBVLuMKzCFD5K22+6TrDrYEmoqixDJIyaonkOr7Wi5+GMhn bw8Ksf0KZLFobHxYn2yR2X3z2pH3+nWvIKdOusgCsoojySBC4tKyU6iHr12ScPar/WQC eF1V9TOpafYmur86OHOgCSrx2+YN/evivLRKWv1XP+BtvSijrCKNXQINLApoFQVdVV9f xPLH4e56MfYA7WGmZDx5i7bN+HbL0+3s6kIffs6v2AvpAQGEhHHgmPj8XtF/YvTFdScc 3kmn4iV0PnHgujKK79rSelDznubiaW9o3bQ00e/146Jx6W2TVE2LqvE+umCo8P9wl1Sx doxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=aUGTtcuyRkJLND+YR/BochtoXe47TvFlIFGMevyBOhE=; b=LVj0Hvtr+bAVZBEXZGVpSMRwZbT6tDtaARbfmEw0w0uUbKbCLWmn0itAUfsKly4uja 5wKGYuc7/2Qk3Stqrsv3i38SqWSHLTL6/eTY77okOML86yoSVMwMjKtpXgIka9GCh8fA lkF8BtbfXtaZ+Q1MFNCXamTeKBUe9sSWgzvbnndydHcn3x24IMRVkDIlgnHlY5DO2u/P cW5096awBnLl3/gso1hly5Ji3QsMXxdYxwezJcomU9Nm8r5Wn8fb1wwoVHiFxzY8BYQ2 fTFjsrLK/qOlovhE5W+WgF3AxIKTMNoHMXdnOEkHXjrsuZvseYQXDtGcEh1Mp/gCS/zg gahA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=humxBtPO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.15.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:15:56 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 02/41] hw/intc/arm_gicv3: Sanity-check num-cpu property Date: Fri, 8 Apr 2022 15:15:11 +0100 Message-Id: <20220408141550.1271295-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In the GICv3 code we implicitly rely on there being at least one CPU and thus at least one redistributor and CPU interface. Sanity-check that the property the board code sets is not zero. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- Doing this would be a board code error, but we might as well get a clean diagnostic for it and not have to think about num_cpu == 0 as a special case later. --- hw/intc/arm_gicv3_common.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 4ca5ae9bc56..90204be25b6 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -328,6 +328,10 @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp) s->num_irq, GIC_INTERNAL); return; } + if (s->num_cpu == 0) { + error_setg(errp, "num-cpu must be at least 1"); + return; + } /* ITLinesNumber is represented as (N / 32) - 1, so this is an * implementation imposed restriction, not an architectural one, From patchwork Fri Apr 8 14:15:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558807 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp363172map; Fri, 8 Apr 2022 07:17:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJynLC8KLLjCSlgoJ/J3/C6zcP9YfUpmfNWrkJIe25wkRC9QjZhwtWuqzAIAx0ZEpCSH3FDT X-Received: by 2002:a81:1586:0:b0:2eb:f462:6602 with SMTP id 128-20020a811586000000b002ebf4626602mr79055ywv.128.1649427469223; Fri, 08 Apr 2022 07:17:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649427469; cv=none; d=google.com; s=arc-20160816; b=q0g7fqRRMDd22kWjTzs0RRC1ZFqHJtcUIFNpQt03LVxgsxFfjWmt3EPvrH0eNRY11p lhTEsYeUd/Bs6CZyOUlxNMuAzAxLpRSxDxmRy7nrhk+SvNRA1Tb1S2+SaPtO0EoU/FsO ATC0ju4m9ijgyA8+Cjmf9L5ooJ11+p+J02n2MfQePZ2FH8+lSRrLt1jLj9RzM8Bj048M DJEkSC9rU8ldrZeWrHHdf7HDEX6zjWrwo4JhfiQp73fs6F9V1TTOKYFUVOwiz/+1+mMZ CiHNQBpepcfUEAKa8iZbHHT8R6Nzm1Xo6vlyE4N6dBVnbWXpnWXPyKVLOInHcJDjh9TK /P9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=nWU/XAW1dTVCsMubCYBZ/twfuj48VjZonfG2m35ljcs=; b=sgMWG9j3PwOB2nMk8Hh4EYKXVPuKFB2EZfsTOmAr8bMqTG4dAqmBzMSAXyN1We3cs4 sZEznf01xFjlr9oQQBL5VjiyOcKZjv5WpU8wPd7fhU4nKL6MaCe9oWtn69P7KgdUEAB6 wrhr7PfYW2m7ANLM7YGrSY3ilgLJI8klP724z763eBNKpT6Y20bFES/I394k6Xj8l17B h7wTQa6g6EQKTNAXp99xEK17bqj/612aEi7Yz4lvXGjW6nanp5eq7OKHI/WGpd1vhTK1 dgt4hx5KNVt3yUwUzi8fiL8NyOK7Ei9LDTVGHeHB9N+Fn0lABKelpK8Pf5baOgNbJ0PK em+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AiFsdbvx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.15.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:15:57 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 03/41] hw/intc/arm_gicv3: Insist that redist region capacity matches CPU count Date: Fri, 8 Apr 2022 15:15:12 +0100 Message-Id: <20220408141550.1271295-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Boards using the GICv3 need to configure it with both the total number of CPUs and also the sizes of all the memory regions which contain redistributors (one redistributor per CPU). At the moment the GICv3 checks that the number of CPUs specified is not too many to fit in the defined redistributor regions, but in fact the code assumes that the two match exactly. For instance when we set the GICR_TYPER.Last bit on the final redistributor in each region, we assume that we don't need to consider the possibility of a region being only half full of redistributors or even completely empty. We also assume in gicv3_redist_read() and gicv3_redist_write() that we can calculate the CPU index from the offset within the MemoryRegion and that this will always be in range. Fortunately all the board code sets the redistributor region sizes to exactly match the CPU count, so this isn't a visible bug. We could in theory make the GIC code handle non-full redistributor regions, or have it automatically reduce the provided region sizes to match the CPU count, but the simplest thing is just to strengthen the error check and insist that the CPU count and redistributor region size settings match exactly, since all the board code does that anyway. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 90204be25b6..c797c82786b 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -354,9 +354,9 @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp) for (i = 0; i < s->nb_redist_regions; i++) { rdist_capacity += s->redist_region_count[i]; } - if (rdist_capacity < s->num_cpu) { + if (rdist_capacity != s->num_cpu) { error_setg(errp, "Capacity of the redist regions(%d) " - "is less than number of vcpus(%d)", + "does not match the number of vcpus(%d)", rdist_capacity, s->num_cpu); return; } From patchwork Fri Apr 8 14:15:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558805 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp363143map; Fri, 8 Apr 2022 07:17:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyHMG3jk2oJDtgy/sy2KFN6yXYRMHCVb1Rz8mZPEpNzPSFasXms0rxYCe2j5tHy0AeLOmji X-Received: by 2002:a81:b51:0:b0:2eb:c585:1622 with SMTP id 78-20020a810b51000000b002ebc5851622mr7477330ywl.288.1649427467762; Fri, 08 Apr 2022 07:17:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649427467; cv=none; d=google.com; s=arc-20160816; b=JDOyhvzS+lyBjmzuYJAvGIaaGQBQjFuQMy59v40cwXYZfpraFwky8W5jz+JTy5DmUV vmF6Bn/MlD77kv/SctQViWDHNDjjQv2UwXpXtb7z8c0UfhMUc/qhMAeaJFsMGVjLGDxj u4oDRL1ZaSY4H/+nhbvrnL8Ko4Org7RUEzU7zChYlgkPecgTnBPfNdwianN5xEXrNNaA uHj/EPLgDI/H3q8HYUYkO+eZ1S9p92zHBHvYz8rBZbM6sQ7h6e8oPwbIpLgelrVxc1Nk 5rLOB2yrb5Q6ZZ2muWd5BI0wiWsqjMN1tipg/3waZv9wI2ezBjxLBrAcXdLXPwYo14JJ r2+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=UgfSynmK+XRGptalQdPXQzCZuxEoEEBnalXv3aPbwZY=; b=VYH/HHOsKtnpU0xW82OfhxhLrORlEL4QtdabYteBhilxgbix9xEx6kg6K8KJB+tsFr BmA4p4QJOWMFfYsYhM6Ev8MWdxzBIMO+V4BiUxFW0Kxqkatf5GeVM+Ff8xs6+brBvSBW FyVd4+ASO5tsr3b+bcjasGP+OaQ+7MJLoD3YuKjzB1EwyJYZHtg0x4VMr7HrNGVOtkIR 6o32VvbYaYHG+dtUJ9M2Z6F1MadA3KTdeNU32oiEtTDyUTEukN37+9i3I9mQkgy33xUD ANDY4bnE89BPlaZ1GrTNwYq8Exbs7GM7doTrI1YlqqyLOlGC1c056rMYql5Qv7nLHaY6 MBcw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gQzwbiEh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.15.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:15:57 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 04/41] hw/intc/arm_gicv3: Report correct PIDR0 values for ID registers Date: Fri, 8 Apr 2022 15:15:13 +0100 Message-Id: <20220408141550.1271295-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We use the common function gicv3_idreg() to supply the CoreSight ID register values for the GICv3 for the copies of these ID registers in the distributor, redistributor and ITS register frames. This isn't quite correct, because while most of the register values are the same, the PIDR0 value should vary to indicate which of these three frames it is. (You can see this and also the correct values of these PIDR0 registers by looking at the GIC-600 or GIC-700 TRMs, for example.) Make gicv3_idreg() take an extra argument for the PIDR0 value. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/gicv3_internal.h | 15 +++++++++++++-- hw/intc/arm_gicv3_dist.c | 2 +- hw/intc/arm_gicv3_its.c | 2 +- hw/intc/arm_gicv3_redist.c | 2 +- 4 files changed, 16 insertions(+), 5 deletions(-) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 2bf1baef047..dec413f7cfa 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -555,7 +555,12 @@ static inline uint32_t gicv3_iidr(void) return 0x43b; } -static inline uint32_t gicv3_idreg(int regoffset) +/* CoreSight PIDR0 values for ARM GICv3 implementations */ +#define GICV3_PIDR0_DIST 0x92 +#define GICV3_PIDR0_REDIST 0x93 +#define GICV3_PIDR0_ITS 0x94 + +static inline uint32_t gicv3_idreg(int regoffset, uint8_t pidr0) { /* Return the value of the CoreSight ID register at the specified * offset from the first ID register (as found in the distributor @@ -565,7 +570,13 @@ static inline uint32_t gicv3_idreg(int regoffset) static const uint8_t gicd_ids[] = { 0x44, 0x00, 0x00, 0x00, 0x92, 0xB4, 0x3B, 0x00, 0x0D, 0xF0, 0x05, 0xB1 }; - return gicd_ids[regoffset / 4]; + + regoffset /= 4; + + if (regoffset == 4) { + return pidr0; + } + return gicd_ids[regoffset]; } /** diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c index 28d913b2114..7f6275363ea 100644 --- a/hw/intc/arm_gicv3_dist.c +++ b/hw/intc/arm_gicv3_dist.c @@ -557,7 +557,7 @@ static bool gicd_readl(GICv3State *s, hwaddr offset, } case GICD_IDREGS ... GICD_IDREGS + 0x2f: /* ID registers */ - *data = gicv3_idreg(offset - GICD_IDREGS); + *data = gicv3_idreg(offset - GICD_IDREGS, GICV3_PIDR0_DIST); return true; case GICD_SGIR: /* WO registers, return unknown value */ diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index 44914f25780..f8467b61ec5 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -1161,7 +1161,7 @@ static bool its_readl(GICv3ITSState *s, hwaddr offset, break; case GITS_IDREGS ... GITS_IDREGS + 0x2f: /* ID registers */ - *data = gicv3_idreg(offset - GITS_IDREGS); + *data = gicv3_idreg(offset - GITS_IDREGS, GICV3_PIDR0_ITS); break; case GITS_TYPER: *data = extract64(s->typer, 0, 32); diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 412a04f59cf..dc9729e8395 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -234,7 +234,7 @@ static MemTxResult gicr_readl(GICv3CPUState *cs, hwaddr offset, *data = cs->gicr_nsacr; return MEMTX_OK; case GICR_IDREGS ... GICR_IDREGS + 0x2f: - *data = gicv3_idreg(offset - GICR_IDREGS); + *data = gicv3_idreg(offset - GICR_IDREGS, GICV3_PIDR0_REDIST); return MEMTX_OK; default: return MEMTX_ERROR; From patchwork Fri Apr 8 14:15:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558806 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp363169map; Fri, 8 Apr 2022 07:17:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwij/HjLODcq92RVBPNX1Q16r9VrlPef4u/cezyLvf+FWK1FlS0uNG7GYD7T1wBm8ZKrbyE X-Received: by 2002:a81:c42:0:b0:2eb:6a2d:cefd with SMTP id 63-20020a810c42000000b002eb6a2dcefdmr16423991ywm.333.1649427469147; Fri, 08 Apr 2022 07:17:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649427469; cv=none; d=google.com; s=arc-20160816; b=xd9nKCJtab7AGuScTD8CIjBwUpOwRZvI2ZkN/GZXHHPnjikavnFpJ5w8LugaA3vEeO 0SsGrDnCFZvRrIr/WW5OhIWkqTHgNM3xGTW7qdWn7iGKvD1zaw88QTfwgAaqTLWZWdN/ Tnq9MPO0ZyATBOidq+4mhTdnFa0NuVAObCjA/rhvGhE/kbArqParjQVH25lbGgTcjtrr byoowV1Z6m5gSe1uirSXDO9AAeVZn5pgZOykUzPEZNdLcWrhaxGoyEUMHpF9KgOxRT1H ws8F9NfoBJRdZ2WZaWH3T0aMuJTcOfffogQR2bgwgk/o5BqCJduWWccbDDN6KUId4/MI V4sg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3Se3GkmVa4NV7sCfZ/9G2/g6YhJ+ing9knztzsyRUdw=; b=DSR1FpuUDnGeX8fTswD0kh4gfvQMz+KEH/PQleqaL2sZ4JxYrnwil95Xyc6z0bAxCT C7nqh3KkPUa5M+K0A86Y2WJNAZZTxLLikrnHQKGLWkPqSf1TEsGAtRJ1MkKTzTBWAwIr R8EGl/Kxaj3iQMkZoOoJD25G9bRmGoP26/WgYv0nlsp9qOAQezIlK4YjFR5lHeiYOxBA WS5A0lUAm2xCzmZb+lDGx+h4xDl3gAUCxOpPu6A9a1A+sMaCr0a6/dQQfqAiK6AxJTtU xXWY5Atv5TPG/XYmys6VHK/SKll9M4rulGRgYE4qQhJ+i8/N/I374mTH1XJjGDGzCDEF O5ZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ysNJeUqh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.15.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:15:58 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 05/41] target/arm/cpu.c: ignore VIRQ and VFIQ if no EL2 Date: Fri, 8 Apr 2022 15:15:14 +0100 Message-Id: <20220408141550.1271295-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In a GICv3, it is impossible for the GIC to deliver a VIRQ or VFIQ to the CPU unless the CPU has EL2, because VIRQ and VFIQ are only configurable via EL2-only system registers. Moreover, in our implementation we were only calculating and updating the state of the VIRQ and VFIQ lines in gicv3_cpuif_virt_irq_fiq_update() when those EL2 system registers changed. We were therefore able to assert in arm_cpu_set_irq() that we didn't see a VIRQ or VFIQ line update if EL2 wasn't present. This assumption no longer holds with GICv4: * even if the CPU does not have EL2 the guest is able to cause the GIC to deliver a virtual LPI by programming the ITS (which is a silly thing for it to do, but possible) * because we now need to recalculate the state of the VIRQ and VFIQ lines in more cases than just "some EL2 GIC sysreg was written", we will see calls to arm_cpu_set_irq() for "VIRQ is 0, VFIQ is 0" even if the guest is not using the virtual LPI parts of the ITS Remove the assertions, and instead simply ignore the state of the VIRQ and VFIQ lines if the CPU does not have EL2. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5d4ca7a2270..1140ce5829e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -694,6 +694,16 @@ static void arm_cpu_set_irq(void *opaque, int irq, int level) [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ }; + if (!arm_feature(env, ARM_FEATURE_EL2) && + (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) { + /* + * The GIC might tell us about VIRQ and VFIQ state, but if we don't + * have EL2 support we don't care. (Unless the guest is doing something + * silly this will only be calls saying "level is still 0".) + */ + return; + } + if (level) { env->irq_line_state |= mask[irq]; } else { @@ -702,11 +712,9 @@ static void arm_cpu_set_irq(void *opaque, int irq, int level) switch (irq) { case ARM_CPU_VIRQ: - assert(arm_feature(env, ARM_FEATURE_EL2)); arm_cpu_update_virq(cpu); break; case ARM_CPU_VFIQ: - assert(arm_feature(env, ARM_FEATURE_EL2)); arm_cpu_update_vfiq(cpu); break; case ARM_CPU_IRQ: From patchwork Fri Apr 8 14:15:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558809 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp366105map; Fri, 8 Apr 2022 07:21:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwBEduxJgOLMquWZC4o+/mA7cGfhXB6o08NiTG2qLmJopvj0zV7lXAHSZd9uKync1bF5xCN X-Received: by 2002:a25:abed:0:b0:641:19bc:b03c with SMTP id v100-20020a25abed000000b0064119bcb03cmr216440ybi.483.1649427676249; Fri, 08 Apr 2022 07:21:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649427676; cv=none; d=google.com; s=arc-20160816; b=kPgMuE3/Uq2Ykw6vFmx0WAvyE6tzDHHficlx3JYDdq2AXsQajar3h4Iznj1CJKHNZj +R//BT5D7OQ5a5wquR96VxccHZSzlBTcXjbkP0fm4GCYFGbvXv93i81PLqPH5+BM2isL 7TyO0W52Oi14sPZvkWXfxkpnsgmjBTFIXQWm/W1m3hue+o5Y/q4quKmwG8eD/qKGnn9V 86G4Jxey2mvOfyXzrtBThsGiqbTfFtSHILiLAh3LM1RbfteIS08dtSqlLd57ftNzbhX4 7Qk91t42P3Wa/tSZ8ZIbGBUlUu61S20RwC3hKByYodTb5hWQGUpjRf1qoBZ/Kz07p5C6 QTzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kl+2ZVJ+6xTCifWmFmG6E383UT0qNH2bxah0KF3V4pw=; b=GoD20HwgZr0CzkfWWWfKrasJtGHk6qjTA22QolsofvyiAdn/lItKDTJOZlXj6EZ56i OJpDyUBv7GJfxNQBGfQ96vAmmAfI17qwXXT/qrZoLP3+zhg91u7I0vKFNWVXNxGaA4/6 +xScYJj82dCOkiZU5FC6zNQ61iPhP/7eW1BaU1kMajg+SOnkKo4/p4ljDW9KJ6d+pKnQ XW4mtXML/TGj0lGC3MwUIuWtaqOLqUbiJrEp0n040bvI8288caBQUEw/zMt09aLzEeSc 0LV7DVTBxMTC29KfgNEcSUrpa1g7H1QTrIMik1KInjTFH2i4Ab2vKlUdxbcLG5X6CUC7 09bw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UvuViJ6H; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.15.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:15:59 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 06/41] hw/intc/arm_gicv3_its: Factor out "is intid a valid LPI ID?" Date: Fri, 8 Apr 2022 15:15:15 +0100 Message-Id: <20220408141550.1271295-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In process_mapti() we check interrupt IDs to see whether they are in the valid LPI range. Factor this out into its own utility function, as we're going to want it elsewhere too for GICv4. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_its.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index f8467b61ec5..400cdf83794 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -79,6 +79,12 @@ typedef enum ItsCmdResult { CMD_CONTINUE = 1, } ItsCmdResult; +static inline bool intid_in_lpi_range(uint32_t id) +{ + return id >= GICV3_LPI_INTID_START && + id < (1ULL << (GICD_TYPER_IDBITS + 1)); +} + static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz) { uint64_t result = 0; @@ -410,7 +416,6 @@ static ItsCmdResult process_mapti(GICv3ITSState *s, const uint64_t *cmdpkt, uint32_t devid, eventid; uint32_t pIntid = 0; uint64_t num_eventids; - uint32_t num_intids; uint16_t icid = 0; DTEntry dte; ITEntry ite; @@ -438,7 +443,6 @@ static ItsCmdResult process_mapti(GICv3ITSState *s, const uint64_t *cmdpkt, return CMD_STALL; } num_eventids = 1ULL << (dte.size + 1); - num_intids = 1ULL << (GICD_TYPER_IDBITS + 1); if (icid >= s->ct.num_entries) { qemu_log_mask(LOG_GUEST_ERROR, @@ -460,7 +464,7 @@ static ItsCmdResult process_mapti(GICv3ITSState *s, const uint64_t *cmdpkt, return CMD_CONTINUE; } - if (pIntid < GICV3_LPI_INTID_START || pIntid >= num_intids) { + if (!intid_in_lpi_range(pIntid)) { qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid interrupt ID 0x%x\n", __func__, pIntid); return CMD_CONTINUE; From patchwork Fri Apr 8 14:15:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558810 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp366805map; Fri, 8 Apr 2022 07:22:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzJvGQSTJoO0bhOESqTgabaEbvTwQI5AsTqbUV5ChiZc8H2arCue5PdBar2xBywTmc6GsAW X-Received: by 2002:a25:9010:0:b0:63c:ffd6:6f7c with SMTP id s16-20020a259010000000b0063cffd66f7cmr13454267ybl.87.1649427723340; Fri, 08 Apr 2022 07:22:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649427723; cv=none; d=google.com; s=arc-20160816; b=mw5maqBmqz+Vpb+AXWvjNpSSHZWHbnRGng5ruQZzQ7JncXDN4QiRftwDPJOw1MxzNd avOT5FGMWHRGmgZ2IjAlOn7WKpfDogZYMAwKz0xQxunXmu2fLCBm7caccAkpKpTBoc0c r4lWJ/whpkH0JTZUHteL0VN/S8W3OTsEXTntMfdfsf00zXDMiUG9GQH3iFXQVo1gVwZD 0S/kybD1ARFEpOr+vLrlyggwhrLxBVIbYt/SIp8Wk10qVu4DbytFvSVLul9DX19tEByd Q2miZ86j5YstFf8gKurfXJDX43tLxPIzjk8+E4Wa4Pv8GBWLB0U7QzsN1g5k1/+gbhvt QWKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=S+YvDc8DedNVliPTdGBNFfK23a5rnWxdXtkXVjY58mc=; b=qEMNTh3+/cqSFQUIq9Oo7+BWf8Zz8QwWgpIyWprFEN44dF1ZUJypLvX58+Kr4d2XUl 5hy5cYRwwdY1Cmf5IXOZyfDSZhxjpfFstMAKAOEVADoZQQOmSn0l/Ut76CGP1xt+tZNA 9gfHD0BfCk4AUrq63SRI2GeuQ4rGVUiWSjiLEBjn1oKA2rYFrCTuhM+3VgRDAVbTL26S y32Be2edbQ/95Ca0jV+aqRlrUX90vhhKWu5GGRoRI/9/9E7AD6T1SYOgwCj6pq9NzTus 1u2DTxERefF6C5JlJkOjkK3diC7ciBUX3Ecf33aS14UmMfyKsXl7kNiUghNVaeLIIJFL 14iQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=npD8nl3z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:00 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 07/41] hw/intc/arm_gicv3_its: Implement GITS_BASER2 for GICv4 Date: Fri, 8 Apr 2022 15:15:16 +0100 Message-Id: <20220408141550.1271295-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The GICv4 defines a new in-guest-memory table for the ITS: this is the vPE table. Implement the new GITS_BASER2 register which the guest uses to tell the ITS where the vPE table is located, including the decode of the register fields into the TableDesc structure which we do for the GITS_BASER when the guest enables the ITS. We guard provision of the new register with the its_feature_virtual() function, which does a check of the GITS_TYPER.Virtual bit which indicates presence of ITS support for virtual LPIs. Since this bit is currently always zero, GICv4-specific features will not be accessible to the guest yet. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/gicv3_internal.h | 16 ++++++++++++++++ include/hw/intc/arm_gicv3_its_common.h | 1 + hw/intc/arm_gicv3_its.c | 25 +++++++++++++++++++++++++ 3 files changed, 42 insertions(+) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index dec413f7cfa..4613b9e59ba 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -280,6 +280,7 @@ FIELD(GITS_CTLR, ENABLED, 0, 1) FIELD(GITS_CTLR, QUIESCENT, 31, 1) FIELD(GITS_TYPER, PHYSICAL, 0, 1) +FIELD(GITS_TYPER, VIRTUAL, 1, 1) FIELD(GITS_TYPER, ITT_ENTRY_SIZE, 4, 4) FIELD(GITS_TYPER, IDBITS, 8, 5) FIELD(GITS_TYPER, DEVBITS, 13, 5) @@ -298,6 +299,7 @@ FIELD(GITS_TYPER, CIL, 36, 1) #define GITS_BASER_PAGESIZE_64K 2 #define GITS_BASER_TYPE_DEVICE 1ULL +#define GITS_BASER_TYPE_VPE 2ULL #define GITS_BASER_TYPE_COLLECTION 4ULL #define GITS_PAGE_SIZE_4K 0x1000 @@ -419,6 +421,20 @@ FIELD(DTE, ITTADDR, 6, 44) FIELD(CTE, VALID, 0, 1) FIELD(CTE, RDBASE, 1, RDBASE_PROCNUM_LENGTH) +/* + * 8 bytes VPE table entry size: + * Valid = 1 bit, VPTsize = 5 bits, VPTaddr = 36 bits, RDbase = 16 bits + * + * Field sizes for Valid and size are mandated; field sizes for RDbase + * and VPT_addr are IMPDEF. + */ +#define GITS_VPE_SIZE 0x8ULL + +FIELD(VTE, VALID, 0, 1) +FIELD(VTE, VPTSIZE, 1, 5) +FIELD(VTE, VPTADDR, 6, 36) +FIELD(VTE, RDBASE, 42, RDBASE_PROCNUM_LENGTH) + /* Special interrupt IDs */ #define INTID_SECURE 1020 #define INTID_NONSECURE 1021 diff --git a/include/hw/intc/arm_gicv3_its_common.h b/include/hw/intc/arm_gicv3_its_common.h index 0f130494dd3..7d1cc0f7177 100644 --- a/include/hw/intc/arm_gicv3_its_common.h +++ b/include/hw/intc/arm_gicv3_its_common.h @@ -78,6 +78,7 @@ struct GICv3ITSState { TableDesc dt; TableDesc ct; + TableDesc vpet; CmdQDesc cq; Error *migration_blocker; diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index 400cdf83794..609c29496a0 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -79,6 +79,12 @@ typedef enum ItsCmdResult { CMD_CONTINUE = 1, } ItsCmdResult; +/* True if the ITS supports the GICv4 virtual LPI feature */ +static bool its_feature_virtual(GICv3ITSState *s) +{ + return s->typer & R_GITS_TYPER_VIRTUAL_MASK; +} + static inline bool intid_in_lpi_range(uint32_t id) { return id >= GICV3_LPI_INTID_START && @@ -946,6 +952,15 @@ static void extract_table_params(GICv3ITSState *s) idbits = 16; } break; + case GITS_BASER_TYPE_VPE: + td = &s->vpet; + /* + * For QEMU vPEIDs are always 16 bits. (GICv4.1 allows an + * implementation to implement fewer bits and report this + * via GICD_TYPER2.) + */ + idbits = 16; + break; default: /* * GITS_BASER.TYPE is read-only, so GITS_BASER_RO_MASK @@ -1425,6 +1440,7 @@ static void gicv3_its_reset(DeviceState *dev) /* * setting GITS_BASER0.Type = 0b001 (Device) * GITS_BASER1.Type = 0b100 (Collection Table) + * GITS_BASER2.Type = 0b010 (vPE) for GICv4 and later * GITS_BASER.Type,where n = 3 to 7 are 0b00 (Unimplemented) * GITS_BASER<0,1>.Page_Size = 64KB * and default translation table entry size to 16 bytes @@ -1442,6 +1458,15 @@ static void gicv3_its_reset(DeviceState *dev) GITS_BASER_PAGESIZE_64K); s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER, ENTRYSIZE, GITS_CTE_SIZE - 1); + + if (its_feature_virtual(s)) { + s->baser[2] = FIELD_DP64(s->baser[2], GITS_BASER, TYPE, + GITS_BASER_TYPE_VPE); + s->baser[2] = FIELD_DP64(s->baser[2], GITS_BASER, PAGESIZE, + GITS_BASER_PAGESIZE_64K); + s->baser[2] = FIELD_DP64(s->baser[2], GITS_BASER, ENTRYSIZE, + GITS_VPE_SIZE - 1); + } } static void gicv3_its_post_load(GICv3ITSState *s) From patchwork Fri Apr 8 14:15:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558811 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp367066map; Fri, 8 Apr 2022 07:22:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxNdsewmvMJGJ0WmI9xFjbF56H/U5tiSOauGeIEMZ+no6kCZmPbmyHOTp7Wd2pKCsVQck/T X-Received: by 2002:a5b:f8d:0:b0:628:620c:a45f with SMTP id q13-20020a5b0f8d000000b00628620ca45fmr13099568ybh.17.1649427743595; Fri, 08 Apr 2022 07:22:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649427743; cv=none; d=google.com; s=arc-20160816; b=ONT6gIL+wwuxTYRL5gr5yTCam3hFgEQbdq8V4eu6wOBeUs+hjA06xl5t9VzrwhDkfC YSHbcmX8+K4m2jEjoDJpjCw9Q0AKMdoWCg76ltKhbIjMbMH05l8sSLwfclixws5HaA0v 97rGyFwFNJ+5Ris+BVf2Lo6YYD7OvYYg9od2X4GYv0ofDkiPAKVnRRHferNSMDx5qkVc 3Vl5SJRs8MZ3P8yoNGwIuqZL3vDF3OHNJY7mYzftabCCbyu3exE1ua2Xs5lINsYUHPvq rK2Oh9RMbiVdFZuHHGPB+4TknxtSZp+AqtWK/Md7E3CRoE8AKonQG1Lxe33t4ctdenlQ 5dwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0qy9U68mC1EeGqtN5ZnmG6vvYW4DtojrPnaWG7hfNQA=; b=inK71WylLioE7qyhdg61fAkexgD5zn2G85jv9UWyEahVFnJ58KBvOJwIxpaHAAoS61 cIVjzR8HmvEEv69FOWRc/eknq9j6HoXYXXql6DCW2nqdJFUqzuX62ws7XzvOt/ubskWK GrVjxiMXB6N1WvghMSOq3gENjYtFLzNNbSge5JZDlNIy6NLUls5ABPibl9Oz0WgEq2Oa S6a4774z7XJ1SR09HwaMcG2TYj8r69MFGxY5YVwRhprRkEUb8AEXluQfm9VO5DsLjjKK WnEV2KbI610MlaU+OTCCUeFy2sGHjmgyy5vUpNrnpDSFCDiDZRfToGroEERDOEW+TG3v pSXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BerPhU+f; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:01 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 08/41] hw/intc/arm_gicv3_its: Implement VMAPI and VMAPTI Date: Fri, 8 Apr 2022 15:15:17 +0100 Message-Id: <20220408141550.1271295-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Implement the GICv4 VMAPI and VMAPTI commands. These write an interrupt translation table entry that maps (DeviceID,EventID) to (vPEID,vINTID,doorbell). The only difference between VMAPI and VMAPTI is that VMAPI assumes vINTID == EventID rather than both being specified in the command packet. (This code won't be reachable until we allow the GIC version to be set to 4. Support for reading this new virtual-interrupt DTE and handling it correctly will be implemented in a later commit.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/gicv3_internal.h | 9 ++++ hw/intc/arm_gicv3_its.c | 91 ++++++++++++++++++++++++++++++++++++++++ hw/intc/trace-events | 2 + 3 files changed, 102 insertions(+) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 4613b9e59ba..d3670a8894e 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -329,6 +329,8 @@ FIELD(GITS_TYPER, CIL, 36, 1) #define GITS_CMD_INVALL 0x0D #define GITS_CMD_MOVALL 0x0E #define GITS_CMD_DISCARD 0x0F +#define GITS_CMD_VMAPTI 0x2A +#define GITS_CMD_VMAPI 0x2B /* MAPC command fields */ #define ICID_LENGTH 16 @@ -368,6 +370,13 @@ FIELD(MOVI_0, DEVICEID, 32, 32) FIELD(MOVI_1, EVENTID, 0, 32) FIELD(MOVI_2, ICID, 0, 16) +/* VMAPI, VMAPTI command fields */ +FIELD(VMAPTI_0, DEVICEID, 32, 32) +FIELD(VMAPTI_1, EVENTID, 0, 32) +FIELD(VMAPTI_1, VPEID, 32, 16) +FIELD(VMAPTI_2, VINTID, 0, 32) /* VMAPTI only */ +FIELD(VMAPTI_2, DOORBELL, 32, 32) + /* * 12 bytes Interrupt translation Table Entry size * as per Table 5.3 in GICv3 spec diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index 609c29496a0..e1f26a205e4 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -91,6 +91,12 @@ static inline bool intid_in_lpi_range(uint32_t id) id < (1ULL << (GICD_TYPER_IDBITS + 1)); } +static inline bool valid_doorbell(uint32_t id) +{ + /* Doorbell fields may be an LPI, or 1023 to mean "no doorbell" */ + return id == INTID_SPURIOUS || intid_in_lpi_range(id); +} + static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz) { uint64_t result = 0; @@ -486,6 +492,85 @@ static ItsCmdResult process_mapti(GICv3ITSState *s, const uint64_t *cmdpkt, return update_ite(s, eventid, &dte, &ite) ? CMD_CONTINUE : CMD_STALL; } +static ItsCmdResult process_vmapti(GICv3ITSState *s, const uint64_t *cmdpkt, + bool ignore_vintid) +{ + uint32_t devid, eventid, vintid, doorbell, vpeid; + uint32_t num_eventids; + DTEntry dte; + ITEntry ite; + + if (!its_feature_virtual(s)) { + return CMD_CONTINUE; + } + + devid = FIELD_EX64(cmdpkt[0], VMAPTI_0, DEVICEID); + eventid = FIELD_EX64(cmdpkt[1], VMAPTI_1, EVENTID); + vpeid = FIELD_EX64(cmdpkt[1], VMAPTI_1, VPEID); + doorbell = FIELD_EX64(cmdpkt[2], VMAPTI_2, DOORBELL); + if (ignore_vintid) { + vintid = eventid; + trace_gicv3_its_cmd_vmapi(devid, eventid, vpeid, doorbell); + } else { + vintid = FIELD_EX64(cmdpkt[2], VMAPTI_2, VINTID); + trace_gicv3_its_cmd_vmapti(devid, eventid, vpeid, vintid, doorbell); + } + + if (devid >= s->dt.num_entries) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid DeviceID 0x%x (must be less than 0x%x)\n", + __func__, devid, s->dt.num_entries); + return CMD_CONTINUE; + } + + if (get_dte(s, devid, &dte) != MEMTX_OK) { + return CMD_STALL; + } + + if (!dte.valid) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: no entry in device table for DeviceID 0x%x\n", + __func__, devid); + return CMD_CONTINUE; + } + + num_eventids = 1ULL << (dte.size + 1); + + if (eventid >= num_eventids) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: EventID 0x%x too large for DeviceID 0x%x " + "(must be less than 0x%x)\n", + __func__, eventid, devid, num_eventids); + return CMD_CONTINUE; + } + if (!intid_in_lpi_range(vintid)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: VIntID 0x%x not a valid LPI\n", + __func__, vintid); + return CMD_CONTINUE; + } + if (!valid_doorbell(doorbell)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Doorbell 0x%x not 1023 and not a valid LPI\n", + __func__, doorbell); + return CMD_CONTINUE; + } + if (vpeid >= s->vpet.num_entries) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: VPEID 0x%x out of range (must be less than 0x%x)\n", + __func__, vpeid, s->vpet.num_entries); + return CMD_CONTINUE; + } + /* add ite entry to interrupt translation table */ + ite.valid = true; + ite.inttype = ITE_INTTYPE_VIRTUAL; + ite.intid = vintid; + ite.icid = 0; + ite.doorbell = doorbell; + ite.vpeid = vpeid; + return update_ite(s, eventid, &dte, &ite) ? CMD_CONTINUE : CMD_STALL; +} + /* * Update the Collection Table entry for @icid to @cte. Returns true * on success, false if there was a memory access error. @@ -872,6 +957,12 @@ static void process_cmdq(GICv3ITSState *s) case GITS_CMD_MOVALL: result = process_movall(s, cmdpkt); break; + case GITS_CMD_VMAPTI: + result = process_vmapti(s, cmdpkt, false); + break; + case GITS_CMD_VMAPI: + result = process_vmapti(s, cmdpkt, true); + break; default: trace_gicv3_its_cmd_unknown(cmd); break; diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 53414aa1979..c6b2b9ab459 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -187,6 +187,8 @@ gicv3_its_cmd_mapti(uint32_t devid, uint32_t eventid, uint32_t icid, uint32_t in gicv3_its_cmd_inv(void) "GICv3 ITS: command INV or INVALL" gicv3_its_cmd_movall(uint64_t rd1, uint64_t rd2) "GICv3 ITS: command MOVALL RDbase1 0x%" PRIx64 " RDbase2 0x%" PRIx64 gicv3_its_cmd_movi(uint32_t devid, uint32_t eventid, uint32_t icid) "GICv3 ITS: command MOVI DeviceID 0x%x EventID 0x%x ICID 0x%x" +gicv3_its_cmd_vmapi(uint32_t devid, uint32_t eventid, uint32_t vpeid, uint32_t doorbell) "GICv3 ITS: command VMAPI DeviceID 0x%x EventID 0x%x vPEID 0x%x Dbell_pINTID 0x%x" +gicv3_its_cmd_vmapti(uint32_t devid, uint32_t eventid, uint32_t vpeid, uint32_t vintid, uint32_t doorbell) "GICv3 ITS: command VMAPI DeviceID 0x%x EventID 0x%x vPEID 0x%x vINTID 0x%x Dbell_pINTID 0x%x" gicv3_its_cmd_unknown(unsigned cmd) "GICv3 ITS: unknown command 0x%x" gicv3_its_cte_read(uint32_t icid, int valid, uint32_t rdbase) "GICv3 ITS: Collection Table read for ICID 0x%x: valid %d RDBase 0x%x" gicv3_its_cte_write(uint32_t icid, int valid, uint32_t rdbase) "GICv3 ITS: Collection Table write for ICID 0x%x: valid %d RDBase 0x%x" From patchwork Fri Apr 8 14:15:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558815 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp370705map; Fri, 8 Apr 2022 07:26:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzBh11Bc42BvFfUq5nE+7gIi0N+6f7046sja0BSBTkpT9VqyTtTydvUn5yM4YXXSs3ikbBd X-Received: by 2002:a25:c384:0:b0:641:1569:906 with SMTP id t126-20020a25c384000000b0064115690906mr936481ybf.274.1649427996490; Fri, 08 Apr 2022 07:26:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649427996; cv=none; d=google.com; s=arc-20160816; b=kUfSDkfpLJGvGI+elUP07wzmfe9HM4pVNIzRpyU6ycqC3/ghgWmuDdoCB3fOmMnNhj ao8CqpZ2vc17A+66mFqawBmjytwdcuIuqFShPYl2k/ZH8l+GcLbtsHJNXxS/3cVEPyO+ 3NpYpZ141CcPGchV6qKkczMTQj5uh2zESPtyn7xCuB29Ue1gnMLB+SEuAO6CkwHG+E3K GZhPFQWhCn5oNOvEdiL/JAndSOQ9p//APbcO1Y8eh0S+09gjwDzsAVKESAodyVCcbTOP /NH/TadsTkiZDqm3jIlYr4WpOxzem9kGlkXIHxdTOsy1nQrd2wbciqmago4eZdWNOQIh W+yw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=UrqFewR1f0mSQHOdTAILd1OutcJSbJ3Z6zOAySPXrP4=; b=mC2QHUpLmdPxHwJby4IkXKWr21KtI4d3ywMHkOO1BJw71IRlLAZnJzbHVx349ubP/3 bvXGKmMth0lI6lmcbGHUfQdGJWvVbs9mNcwYXqQtIrHJK4lh71ZVJoBgsDaWRSj3Li/G QmIT/gOl+HrRKEg8rnOkR6e/U24WtS+dT1gyd3dT/D6nuLHXpw2t18Mcr7Qrlm/Rn8Wn kZxhwsjzK08BDb7K4QmC/J2PM8VNlBSRS7Eu3n/zjCQ25S/ACChCXHaYXGSkNDR8v6eZ WrCWzSMf0gCePMavkalZe4MnItMyeBqMkY7cD2ISiqXbVRWoJ4o8M6Q/PXr1/SfwEkO6 04fg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="y8L6VHm/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:02 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 09/41] hw/intc/arm_gicv3_its: Implement VMAPP Date: Fri, 8 Apr 2022 15:15:18 +0100 Message-Id: <20220408141550.1271295-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Implement the GICv4 VMAPP command, which writes an entry to the vPE table. For GICv4.1 this command has extra fields in the command packet and additional behaviour. We define the 4.1-only fields with the FIELD macro, but only implement the GICv4.0 version of the command. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- GICv4.1 emulation is on my todo list, but I'm starting with just the 4.0 parts first. --- hw/intc/gicv3_internal.h | 12 ++++++ hw/intc/arm_gicv3_its.c | 88 ++++++++++++++++++++++++++++++++++++++++ hw/intc/trace-events | 2 + 3 files changed, 102 insertions(+) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index d3670a8894e..bbb8a20ce61 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -329,6 +329,7 @@ FIELD(GITS_TYPER, CIL, 36, 1) #define GITS_CMD_INVALL 0x0D #define GITS_CMD_MOVALL 0x0E #define GITS_CMD_DISCARD 0x0F +#define GITS_CMD_VMAPP 0x29 #define GITS_CMD_VMAPTI 0x2A #define GITS_CMD_VMAPI 0x2B @@ -377,6 +378,17 @@ FIELD(VMAPTI_1, VPEID, 32, 16) FIELD(VMAPTI_2, VINTID, 0, 32) /* VMAPTI only */ FIELD(VMAPTI_2, DOORBELL, 32, 32) +/* VMAPP command fields */ +FIELD(VMAPP_0, ALLOC, 8, 1) /* GICv4.1 only */ +FIELD(VMAPP_0, PTZ, 9, 1) /* GICv4.1 only */ +FIELD(VMAPP_0, VCONFADDR, 16, 36) /* GICv4.1 only */ +FIELD(VMAPP_1, DEFAULT_DOORBELL, 0, 32) /* GICv4.1 only */ +FIELD(VMAPP_1, VPEID, 32, 16) +FIELD(VMAPP_2, RDBASE, 16, 36) +FIELD(VMAPP_2, V, 63, 1) +FIELD(VMAPP_3, VPTSIZE, 0, 8) /* For GICv4.0, bits [7:6] are RES0 */ +FIELD(VMAPP_3, VPTADDR, 16, 36) + /* * 12 bytes Interrupt translation Table Entry size * as per Table 5.3 in GICv3 spec diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index e1f26a205e4..ea2b4b9e5a7 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -61,6 +61,12 @@ typedef struct ITEntry { uint32_t vpeid; } ITEntry; +typedef struct VTEntry { + bool valid; + unsigned vptsize; + uint32_t rdbase; + uint64_t vptaddr; +} VTEntry; /* * The ITS spec permits a range of CONSTRAINED UNPREDICTABLE options @@ -842,6 +848,85 @@ static ItsCmdResult process_movi(GICv3ITSState *s, const uint64_t *cmdpkt) return update_ite(s, eventid, &dte, &old_ite) ? CMD_CONTINUE : CMD_STALL; } +/* + * Update the vPE Table entry at index @vpeid with the entry @vte. + * Returns true on success, false if there was a memory access error. + */ +static bool update_vte(GICv3ITSState *s, uint32_t vpeid, const VTEntry *vte) +{ + AddressSpace *as = &s->gicv3->dma_as; + uint64_t entry_addr; + uint64_t vteval = 0; + MemTxResult res = MEMTX_OK; + + trace_gicv3_its_vte_write(vpeid, vte->valid, vte->vptsize, vte->vptaddr, + vte->rdbase); + + if (vte->valid) { + vteval = FIELD_DP64(vteval, VTE, VALID, 1); + vteval = FIELD_DP64(vteval, VTE, VPTSIZE, vte->vptsize); + vteval = FIELD_DP64(vteval, VTE, VPTADDR, vte->vptaddr); + vteval = FIELD_DP64(vteval, VTE, RDBASE, vte->rdbase); + } + + entry_addr = table_entry_addr(s, &s->vpet, vpeid, &res); + if (res != MEMTX_OK) { + return false; + } + if (entry_addr == -1) { + /* No L2 table for this index: discard write and continue */ + return true; + } + address_space_stq_le(as, entry_addr, vteval, MEMTXATTRS_UNSPECIFIED, &res); + return res == MEMTX_OK; +} + +static ItsCmdResult process_vmapp(GICv3ITSState *s, const uint64_t *cmdpkt) +{ + VTEntry vte; + uint32_t vpeid; + + if (!its_feature_virtual(s)) { + return CMD_CONTINUE; + } + + vpeid = FIELD_EX64(cmdpkt[1], VMAPP_1, VPEID); + vte.rdbase = FIELD_EX64(cmdpkt[2], VMAPP_2, RDBASE); + vte.valid = FIELD_EX64(cmdpkt[2], VMAPP_2, V); + vte.vptsize = FIELD_EX64(cmdpkt[3], VMAPP_3, VPTSIZE); + vte.vptaddr = FIELD_EX64(cmdpkt[3], VMAPP_3, VPTADDR); + + trace_gicv3_its_cmd_vmapp(vpeid, vte.rdbase, vte.valid, + vte.vptaddr, vte.vptsize); + + /* + * For GICv4.0 the VPT_size field is only 5 bits, whereas we + * define our field macros to include the full GICv4.1 8 bits. + * The range check on VPT_size will catch the cases where + * the guest set the RES0-in-GICv4.0 bits [7:6]. + */ + if (vte.vptsize > FIELD_EX64(s->typer, GITS_TYPER, IDBITS)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid VPT_size 0x%x\n", __func__, vte.vptsize); + return CMD_CONTINUE; + } + + if (vte.valid && vte.rdbase >= s->gicv3->num_cpu) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid rdbase 0x%x\n", __func__, vte.rdbase); + return CMD_CONTINUE; + } + + if (vpeid >= s->vpet.num_entries) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: VPEID 0x%x out of range (must be less than 0x%x)\n", + __func__, vpeid, s->vpet.num_entries); + return CMD_CONTINUE; + } + + return update_vte(s, vpeid, &vte) ? CMD_CONTINUE : CMD_STALL; +} + /* * Current implementation blocks until all * commands are processed @@ -963,6 +1048,9 @@ static void process_cmdq(GICv3ITSState *s) case GITS_CMD_VMAPI: result = process_vmapti(s, cmdpkt, true); break; + case GITS_CMD_VMAPP: + result = process_vmapp(s, cmdpkt); + break; default: trace_gicv3_its_cmd_unknown(cmd); break; diff --git a/hw/intc/trace-events b/hw/intc/trace-events index c6b2b9ab459..2fcc9e40e55 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -189,6 +189,7 @@ gicv3_its_cmd_movall(uint64_t rd1, uint64_t rd2) "GICv3 ITS: command MOVALL RDba gicv3_its_cmd_movi(uint32_t devid, uint32_t eventid, uint32_t icid) "GICv3 ITS: command MOVI DeviceID 0x%x EventID 0x%x ICID 0x%x" gicv3_its_cmd_vmapi(uint32_t devid, uint32_t eventid, uint32_t vpeid, uint32_t doorbell) "GICv3 ITS: command VMAPI DeviceID 0x%x EventID 0x%x vPEID 0x%x Dbell_pINTID 0x%x" gicv3_its_cmd_vmapti(uint32_t devid, uint32_t eventid, uint32_t vpeid, uint32_t vintid, uint32_t doorbell) "GICv3 ITS: command VMAPI DeviceID 0x%x EventID 0x%x vPEID 0x%x vINTID 0x%x Dbell_pINTID 0x%x" +gicv3_its_cmd_vmapp(uint32_t vpeid, uint64_t rdbase, int valid, uint64_t vptaddr, uint32_t vptsize) "GICv3 ITS: command VMAPP vPEID 0x%x RDbase 0x%" PRIx64 " V %d VPT_addr 0x%" PRIx64 " VPT_size 0x%x" gicv3_its_cmd_unknown(unsigned cmd) "GICv3 ITS: unknown command 0x%x" gicv3_its_cte_read(uint32_t icid, int valid, uint32_t rdbase) "GICv3 ITS: Collection Table read for ICID 0x%x: valid %d RDBase 0x%x" gicv3_its_cte_write(uint32_t icid, int valid, uint32_t rdbase) "GICv3 ITS: Collection Table write for ICID 0x%x: valid %d RDBase 0x%x" @@ -199,6 +200,7 @@ gicv3_its_ite_write(uint64_t ittaddr, uint32_t eventid, int valid, int inttype, gicv3_its_dte_read(uint32_t devid, int valid, uint32_t size, uint64_t ittaddr) "GICv3 ITS: Device Table read for DeviceID 0x%x: valid %d size 0x%x ITTaddr 0x%" PRIx64 gicv3_its_dte_write(uint32_t devid, int valid, uint32_t size, uint64_t ittaddr) "GICv3 ITS: Device Table write for DeviceID 0x%x: valid %d size 0x%x ITTaddr 0x%" PRIx64 gicv3_its_dte_read_fault(uint32_t devid) "GICv3 ITS: Device Table read for DeviceID 0x%x: faulted" +gicv3_its_vte_write(uint32_t vpeid, int valid, uint32_t vptsize, uint64_t vptaddr, uint32_t rdbase) "GICv3 ITS: vPE Table write for vPEID 0x%x: valid %d VPTsize 0x%x VPTaddr 0x%" PRIx64 " RDbase 0x%x" # armv7m_nvic.c nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d" From patchwork Fri Apr 8 14:15:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558814 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp368749map; Fri, 8 Apr 2022 07:24:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwgsgxzjBhdleSHFxWN4kbDoAo5GHppNvY/O9sCGn+EMWskREfNQaxXF+QoWyWwK0nAKBPd X-Received: by 2002:a81:e105:0:b0:2d0:6b27:2009 with SMTP id w5-20020a81e105000000b002d06b272009mr16087694ywh.462.1649427870269; Fri, 08 Apr 2022 07:24:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649427870; cv=none; d=google.com; s=arc-20160816; b=WPU81JvVQNZ0m3V6OYSqycYCAToreyEF/k/+bh11To2GgpQoe9f5mnuN90lGygfjmO vU17lNX4UOebGjZ6UpFHU+LGlGnCYk+ogLiQPVcM1H/EtSiMqRR+8TGInP21yWaf0JiB /iZvQdRqMaOtO4LNAWaCngVPIl9dY/Lf/5BR+zQbNHamZR+IJRFTsHLv3vj2TpJeu/6T Th6/j8JI+YUe8Ary7cMQtB7oROwCKTiXTHMm9GWMsmXdk1Ev6xlP4AqoSMVZb+nX1mR2 DFctViNLZoUiIEd//0XVG7ghcm76LF59d4yLKhEpUv2TRtOuI9uj3xUXA/rF3tsukLXV GNDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=udZXKhjCILW7E0fUX7TNoreN3wUNIEE/HPBGgOlM0/Q=; b=dfM9Kg0Wd07owJCzCYcd5Pvc1XTYENP8+lxwlBywfmncdrhT8vNIm7+KIx3h9uSB3i 3vAVaV1+kjAMVPkmugW4dx7lORsZQAQJRHQ9/HQKC3o09g5M4CaCJmwLsStFnMmerXWx vXm77TKdgGG+dc7VEUYkct6dNVZdhS25Cm1Qh7hkXYh3IAlRRHCXZy+n8N6IhNZL/Eqk LiMyrR9TqtC4XEqXq8StVODzJ+Ghi7LA1sO0LFBLad56t6PN6xdy2hAB5dnAQA2NoixD igi5yf60xxZDzug46snn64HGxfBEsGBq79P5WYY6Oiy5cqr00kysLoLCxxfielTeS+j+ lZvA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qCzJ0W4G; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:03 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 10/41] hw/intc/arm_gicv3_its: Distinguish success and error cases of CMD_CONTINUE Date: Fri, 8 Apr 2022 15:15:19 +0100 Message-Id: <20220408141550.1271295-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In the ItsCmdResult enum, we currently distinguish only CMD_STALL (failure, stall processing of the command queue) and CMD_CONTINUE (keep processing the queue), and we use the latter both for "there was a parameter error, go on to the next command" and "the command succeeded, go on to the next command". Sometimes we would like to distinguish those two cases, so add CMD_CONTINUE_OK to the enum to represent the success situation, and use it in the relevant places. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_its.c | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index ea2b4b9e5a7..ba1893c072b 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -78,11 +78,13 @@ typedef struct VTEntry { * and continue processing. * The process_* functions which handle individual ITS commands all * return an ItsCmdResult which tells process_cmdq() whether it should - * stall or keep going. + * stall, keep going because of an error, or keep going because the + * command was a success. */ typedef enum ItsCmdResult { CMD_STALL = 0, CMD_CONTINUE = 1, + CMD_CONTINUE_OK = 2, } ItsCmdResult; /* True if the ITS supports the GICv4 virtual LPI feature */ @@ -400,9 +402,9 @@ static ItsCmdResult do_process_its_cmd(GICv3ITSState *s, uint32_t devid, ITEntry ite = {}; /* remove mapping from interrupt translation table */ ite.valid = false; - return update_ite(s, eventid, &dte, &ite) ? CMD_CONTINUE : CMD_STALL; + return update_ite(s, eventid, &dte, &ite) ? CMD_CONTINUE_OK : CMD_STALL; } - return CMD_CONTINUE; + return CMD_CONTINUE_OK; } static ItsCmdResult process_its_cmd(GICv3ITSState *s, const uint64_t *cmdpkt, @@ -495,7 +497,7 @@ static ItsCmdResult process_mapti(GICv3ITSState *s, const uint64_t *cmdpkt, ite.icid = icid; ite.doorbell = INTID_SPURIOUS; ite.vpeid = 0; - return update_ite(s, eventid, &dte, &ite) ? CMD_CONTINUE : CMD_STALL; + return update_ite(s, eventid, &dte, &ite) ? CMD_CONTINUE_OK : CMD_STALL; } static ItsCmdResult process_vmapti(GICv3ITSState *s, const uint64_t *cmdpkt, @@ -574,7 +576,7 @@ static ItsCmdResult process_vmapti(GICv3ITSState *s, const uint64_t *cmdpkt, ite.icid = 0; ite.doorbell = doorbell; ite.vpeid = vpeid; - return update_ite(s, eventid, &dte, &ite) ? CMD_CONTINUE : CMD_STALL; + return update_ite(s, eventid, &dte, &ite) ? CMD_CONTINUE_OK : CMD_STALL; } /* @@ -635,7 +637,7 @@ static ItsCmdResult process_mapc(GICv3ITSState *s, const uint64_t *cmdpkt) return CMD_CONTINUE; } - return update_cte(s, icid, &cte) ? CMD_CONTINUE : CMD_STALL; + return update_cte(s, icid, &cte) ? CMD_CONTINUE_OK : CMD_STALL; } /* @@ -696,7 +698,7 @@ static ItsCmdResult process_mapd(GICv3ITSState *s, const uint64_t *cmdpkt) return CMD_CONTINUE; } - return update_dte(s, devid, &dte) ? CMD_CONTINUE : CMD_STALL; + return update_dte(s, devid, &dte) ? CMD_CONTINUE_OK : CMD_STALL; } static ItsCmdResult process_movall(GICv3ITSState *s, const uint64_t *cmdpkt) @@ -725,13 +727,13 @@ static ItsCmdResult process_movall(GICv3ITSState *s, const uint64_t *cmdpkt) if (rd1 == rd2) { /* Move to same target must succeed as a no-op */ - return CMD_CONTINUE; + return CMD_CONTINUE_OK; } /* Move all pending LPIs from redistributor 1 to redistributor 2 */ gicv3_redist_movall_lpis(&s->gicv3->cpu[rd1], &s->gicv3->cpu[rd2]); - return CMD_CONTINUE; + return CMD_CONTINUE_OK; } static ItsCmdResult process_movi(GICv3ITSState *s, const uint64_t *cmdpkt) @@ -845,7 +847,7 @@ static ItsCmdResult process_movi(GICv3ITSState *s, const uint64_t *cmdpkt) /* Update the ICID field in the interrupt translation table entry */ old_ite.icid = new_icid; - return update_ite(s, eventid, &dte, &old_ite) ? CMD_CONTINUE : CMD_STALL; + return update_ite(s, eventid, &dte, &old_ite) ? CMD_CONTINUE_OK : CMD_STALL; } /* @@ -924,7 +926,7 @@ static ItsCmdResult process_vmapp(GICv3ITSState *s, const uint64_t *cmdpkt) return CMD_CONTINUE; } - return update_vte(s, vpeid, &vte) ? CMD_CONTINUE : CMD_STALL; + return update_vte(s, vpeid, &vte) ? CMD_CONTINUE_OK : CMD_STALL; } /* @@ -963,7 +965,7 @@ static void process_cmdq(GICv3ITSState *s) } while (wr_offset != rd_offset) { - ItsCmdResult result = CMD_CONTINUE; + ItsCmdResult result = CMD_CONTINUE_OK; void *hostmem; hwaddr buflen; uint64_t cmdpkt[GITS_CMDQ_ENTRY_WORDS]; @@ -1055,7 +1057,8 @@ static void process_cmdq(GICv3ITSState *s) trace_gicv3_its_cmd_unknown(cmd); break; } - if (result == CMD_CONTINUE) { + if (result != CMD_STALL) { + /* CMD_CONTINUE or CMD_CONTINUE_OK */ rd_offset++; rd_offset %= s->cq.num_entries; s->creadr = FIELD_DP64(s->creadr, GITS_CREADR, OFFSET, rd_offset); From patchwork Fri Apr 8 14:15:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558813 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp368727map; Fri, 8 Apr 2022 07:24:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxz5Zyk3X6+fgXaWaiYDZAG2iwLgekbVWdKwoG7sXhFSZDCUwdRFXK55BQsBhKKjsXdzOV0 X-Received: by 2002:a81:6d05:0:b0:2ea:cb7f:9fc0 with SMTP id i5-20020a816d05000000b002eacb7f9fc0mr16454001ywc.297.1649427868228; Fri, 08 Apr 2022 07:24:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649427868; cv=none; d=google.com; s=arc-20160816; b=jCmLa0oNi4DVqwbadMMVBMPLFce9NlvX/9Z9NegKQKET7ShnCYl3Vx4t9rOGr+XOJ+ yQH+ZUCFJ9l9RxHTYeSno4ioCnGTXL3dqgz8EqMb4Wk4pSjeUZzVhS1VRRRZlYNoAB+E 4a9v7ZXop2R97guXCKKPGqKs8koBtKI4oizCFBh+4kOBFGvbxL99fmc8oyzhn3im+fQ6 fMgAGTc8B8ryzBH50F80tSPP2nfjfGT/e39nT165qvOEFwKaKSJzkf0MxH7U6rjpSO2P rqOGO02m/QUclTwXrffZF3ho3ICJAP0b3Zh5LQWpqOjwGgt2QyuTOArNqjdUsiATiJ1H VBcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=JOex7zXlNRw0uzuroIWAH3oSHzCyU5BsmZyuU+iBsAg=; b=V+X9gvhXpcg7I4NrDqJju9kMT3Kizz8gMTOCeNtSu7LRLKF0Wj6iLFqMd39uotOkxX SGKTlGxHkbTYBvPbjguU+QCOC/tkZzX6mA+edcno5LGhKusxdI2wrcqLBBF93kfVUL9f BeJ3FuyogMLOWxl3Ledvm2ep6exDFEJFzxQHR+7f2F6aEM62kepZKCR9pbL2SjYwp1CY WYakdHX0IZQenii83lMeIdV4CDkoMQuULXSGRQEijYIHfzozmJzvO5GKjmuNQp+ggkIY kT4j2oSFHDcnDQembmkpATD+pfku6RlWEGh8GEjHH4y4eph6pqH4ZPgGRNJ+YR1hrt0n 8cCg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z5xyUyJt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:03 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 11/41] hw/intc/arm_gicv3_its: Factor out "find ITE given devid, eventid" Date: Fri, 8 Apr 2022 15:15:20 +0100 Message-Id: <20220408141550.1271295-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The operation of finding an interrupt table entry given a (DeviceID, EventID) pair is necessary in multiple different ITS commands. The process requires first using the DeviceID as an index into the device table to find the DTE, and then useng the EventID as an index into the interrupt table specified by that DTE to find the ITE. We also need to handle all the possible error cases: indexes out of range, table memory not readable, table entries not valid. Factor this out into a separate lookup_ite() function which we can then call from the places where we were previously open-coding this sequence. We'll also need this for some of the new GICv4.0 commands. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_its.c | 124 +++++++++++++++++++++------------------- 1 file changed, 64 insertions(+), 60 deletions(-) diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index ba1893c072b..fe1bea2dd81 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -314,6 +314,60 @@ out: return res; } +/* + * Given a (DeviceID, EventID), look up the corresponding ITE, including + * checking for the various invalid-value cases. If we find a valid ITE, + * fill in @ite and @dte and return CMD_CONTINUE_OK. Otherwise return + * CMD_STALL or CMD_CONTINUE as appropriate (and the contents of @ite + * should not be relied on). + * + * The string @who is purely for the LOG_GUEST_ERROR messages, + * and should indicate the name of the calling function or similar. + */ +static ItsCmdResult lookup_ite(GICv3ITSState *s, const char *who, + uint32_t devid, uint32_t eventid, ITEntry *ite, + DTEntry *dte) +{ + uint64_t num_eventids; + + if (devid >= s->dt.num_entries) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid command attributes: devid %d>=%d", + who, devid, s->dt.num_entries); + return CMD_CONTINUE; + } + + if (get_dte(s, devid, dte) != MEMTX_OK) { + return CMD_STALL; + } + if (!dte->valid) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid command attributes: " + "invalid dte for %d\n", who, devid); + return CMD_CONTINUE; + } + + num_eventids = 1ULL << (dte->size + 1); + if (eventid >= num_eventids) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid command attributes: eventid %d >= %" + PRId64 "\n", who, eventid, num_eventids); + return CMD_CONTINUE; + } + + if (get_ite(s, eventid, dte, ite) != MEMTX_OK) { + return CMD_STALL; + } + + if (!ite->valid) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid command attributes: invalid ITE\n", who); + return CMD_CONTINUE; + } + + return CMD_CONTINUE_OK; +} + /* * This function handles the processing of following commands based on * the ItsCmdType parameter passed:- @@ -325,42 +379,17 @@ out: static ItsCmdResult do_process_its_cmd(GICv3ITSState *s, uint32_t devid, uint32_t eventid, ItsCmdType cmd) { - uint64_t num_eventids; DTEntry dte; CTEntry cte; ITEntry ite; + ItsCmdResult cmdres; - if (devid >= s->dt.num_entries) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid command attributes: devid %d>=%d", - __func__, devid, s->dt.num_entries); - return CMD_CONTINUE; + cmdres = lookup_ite(s, __func__, devid, eventid, &ite, &dte); + if (cmdres != CMD_CONTINUE_OK) { + return cmdres; } - if (get_dte(s, devid, &dte) != MEMTX_OK) { - return CMD_STALL; - } - if (!dte.valid) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid command attributes: " - "invalid dte for %d\n", __func__, devid); - return CMD_CONTINUE; - } - - num_eventids = 1ULL << (dte.size + 1); - if (eventid >= num_eventids) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid command attributes: eventid %d >= %" - PRId64 "\n", - __func__, eventid, num_eventids); - return CMD_CONTINUE; - } - - if (get_ite(s, eventid, &dte, &ite) != MEMTX_OK) { - return CMD_STALL; - } - - if (!ite.valid || ite.inttype != ITE_INTTYPE_PHYSICAL) { + if (ite.inttype != ITE_INTTYPE_PHYSICAL) { qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid command attributes: invalid ITE\n", __func__); @@ -740,10 +769,10 @@ static ItsCmdResult process_movi(GICv3ITSState *s, const uint64_t *cmdpkt) { uint32_t devid, eventid; uint16_t new_icid; - uint64_t num_eventids; DTEntry dte; CTEntry old_cte, new_cte; ITEntry old_ite; + ItsCmdResult cmdres; devid = FIELD_EX64(cmdpkt[0], MOVI_0, DEVICEID); eventid = FIELD_EX64(cmdpkt[1], MOVI_1, EVENTID); @@ -751,37 +780,12 @@ static ItsCmdResult process_movi(GICv3ITSState *s, const uint64_t *cmdpkt) trace_gicv3_its_cmd_movi(devid, eventid, new_icid); - if (devid >= s->dt.num_entries) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid command attributes: devid %d>=%d", - __func__, devid, s->dt.num_entries); - return CMD_CONTINUE; - } - if (get_dte(s, devid, &dte) != MEMTX_OK) { - return CMD_STALL; + cmdres = lookup_ite(s, __func__, devid, eventid, &old_ite, &dte); + if (cmdres != CMD_CONTINUE_OK) { + return cmdres; } - if (!dte.valid) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid command attributes: " - "invalid dte for %d\n", __func__, devid); - return CMD_CONTINUE; - } - - num_eventids = 1ULL << (dte.size + 1); - if (eventid >= num_eventids) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid command attributes: eventid %d >= %" - PRId64 "\n", - __func__, eventid, num_eventids); - return CMD_CONTINUE; - } - - if (get_ite(s, eventid, &dte, &old_ite) != MEMTX_OK) { - return CMD_STALL; - } - - if (!old_ite.valid || old_ite.inttype != ITE_INTTYPE_PHYSICAL) { + if (old_ite.inttype != ITE_INTTYPE_PHYSICAL) { qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid command attributes: invalid ITE\n", __func__); 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:04 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 12/41] hw/intc/arm_gicv3_its: Factor out CTE lookup sequence Date: Fri, 8 Apr 2022 15:15:21 +0100 Message-Id: <20220408141550.1271295-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Factor out the sequence of looking up a CTE from an ICID including the validity and error checks. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- I think process_movi() in particular is now a lot cleaner to read with all the error-checking factored out. --- hw/intc/arm_gicv3_its.c | 109 ++++++++++++++-------------------------- 1 file changed, 39 insertions(+), 70 deletions(-) diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index fe1bea2dd81..2cbac76256d 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -368,6 +368,36 @@ static ItsCmdResult lookup_ite(GICv3ITSState *s, const char *who, return CMD_CONTINUE_OK; } +/* + * Given an ICID, look up the corresponding CTE, including checking for various + * invalid-value cases. If we find a valid CTE, fill in @cte and return + * CMD_CONTINUE_OK; otherwise return CMD_STALL or CMD_CONTINUE (and the + * contents of @cte should not be relied on). + * + * The string @who is purely for the LOG_GUEST_ERROR messages, + * and should indicate the name of the calling function or similar. + */ +static ItsCmdResult lookup_cte(GICv3ITSState *s, const char *who, + uint32_t icid, CTEntry *cte) +{ + if (icid >= s->ct.num_entries) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid ICID 0x%x\n", who, icid); + return CMD_CONTINUE; + } + if (get_cte(s, icid, cte) != MEMTX_OK) { + return CMD_STALL; + } + if (!cte->valid) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid CTE\n", who); + return CMD_CONTINUE; + } + if (cte->rdbase >= s->gicv3->num_cpu) { + return CMD_CONTINUE; + } + return CMD_CONTINUE_OK; +} + + /* * This function handles the processing of following commands based on * the ItsCmdType parameter passed:- @@ -396,29 +426,9 @@ static ItsCmdResult do_process_its_cmd(GICv3ITSState *s, uint32_t devid, return CMD_CONTINUE; } - if (ite.icid >= s->ct.num_entries) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid ICID 0x%x in ITE (table corrupted?)\n", - __func__, ite.icid); - return CMD_CONTINUE; - } - - if (get_cte(s, ite.icid, &cte) != MEMTX_OK) { - return CMD_STALL; - } - if (!cte.valid) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid command attributes: invalid CTE\n", - __func__); - return CMD_CONTINUE; - } - - /* - * Current implementation only supports rdbase == procnum - * Hence rdbase physical address is ignored - */ - if (cte.rdbase >= s->gicv3->num_cpu) { - return CMD_CONTINUE; + cmdres = lookup_cte(s, __func__, ite.icid, &cte); + if (cmdres != CMD_CONTINUE_OK) { + return cmdres; } if ((cmd == CLEAR) || (cmd == DISCARD)) { @@ -792,54 +802,13 @@ static ItsCmdResult process_movi(GICv3ITSState *s, const uint64_t *cmdpkt) return CMD_CONTINUE; } - if (old_ite.icid >= s->ct.num_entries) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid ICID 0x%x in ITE (table corrupted?)\n", - __func__, old_ite.icid); - return CMD_CONTINUE; + cmdres = lookup_cte(s, __func__, old_ite.icid, &old_cte); + if (cmdres != CMD_CONTINUE_OK) { + return cmdres; } - - if (new_icid >= s->ct.num_entries) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid command attributes: ICID 0x%x\n", - __func__, new_icid); - return CMD_CONTINUE; - } - - if (get_cte(s, old_ite.icid, &old_cte) != MEMTX_OK) { - return CMD_STALL; - } - if (!old_cte.valid) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid command attributes: " - "invalid CTE for old ICID 0x%x\n", - __func__, old_ite.icid); - return CMD_CONTINUE; - } - - if (get_cte(s, new_icid, &new_cte) != MEMTX_OK) { - return CMD_STALL; - } - if (!new_cte.valid) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid command attributes: " - "invalid CTE for new ICID 0x%x\n", - __func__, new_icid); - return CMD_CONTINUE; - } - - if (old_cte.rdbase >= s->gicv3->num_cpu) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: CTE has invalid rdbase 0x%x\n", - __func__, old_cte.rdbase); - return CMD_CONTINUE; - } - - if (new_cte.rdbase >= s->gicv3->num_cpu) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: CTE has invalid rdbase 0x%x\n", - __func__, new_cte.rdbase); - return CMD_CONTINUE; + cmdres = lookup_cte(s, __func__, new_icid, &new_cte); + if (cmdres != CMD_CONTINUE_OK) { + return cmdres; } if (old_cte.rdbase != new_cte.rdbase) { From patchwork Fri Apr 8 14:15:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558817 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp371797map; Fri, 8 Apr 2022 07:27:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzpPyGWcPC0OGpCNhdKybO0OhAgY4J+vcdvVy+tlIsPonyP7ld6eM1F2lBnqe6OpZMrCLTH X-Received: by 2002:a25:6642:0:b0:633:b9f4:b57d with SMTP id z2-20020a256642000000b00633b9f4b57dmr13700666ybm.394.1649428077827; Fri, 08 Apr 2022 07:27:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649428077; cv=none; d=google.com; s=arc-20160816; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:05 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 13/41] hw/intc/arm_gicv3_its: Split out process_its_cmd() physical interrupt code Date: Fri, 8 Apr 2022 15:15:22 +0100 Message-Id: <20220408141550.1271295-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split the part of process_its_cmd() which is specific to physical interrupts into its own function. This is the part which starts by taking the ICID and looking it up in the collection table. The handling of virtual interrupts is significantly different (involving a lookup in the vPE table) so structuring the code with one sub-function for the physical interrupt case and one for the virtual interrupt case will be clearer than putting both cases in one large function. The code for handling the "remove mapping from ITE" for the DISCARD command remains in process_its_cmd() because it is common to both virtual and physical interrupts. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_its.c | 51 ++++++++++++++++++++++++++--------------- 1 file changed, 33 insertions(+), 18 deletions(-) diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index 2cbac76256d..8ea1fc366d3 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -397,6 +397,19 @@ static ItsCmdResult lookup_cte(GICv3ITSState *s, const char *who, return CMD_CONTINUE_OK; } +static ItsCmdResult process_its_cmd_phys(GICv3ITSState *s, const ITEntry *ite, + int irqlevel) +{ + CTEntry cte; + ItsCmdResult cmdres; + + cmdres = lookup_cte(s, __func__, ite->icid, &cte); + if (cmdres != CMD_CONTINUE_OK) { + return cmdres; + } + gicv3_redist_process_lpi(&s->gicv3->cpu[cte.rdbase], ite->intid, irqlevel); + return CMD_CONTINUE_OK; +} /* * This function handles the processing of following commands based on @@ -410,34 +423,36 @@ static ItsCmdResult do_process_its_cmd(GICv3ITSState *s, uint32_t devid, uint32_t eventid, ItsCmdType cmd) { DTEntry dte; - CTEntry cte; ITEntry ite; ItsCmdResult cmdres; + int irqlevel; cmdres = lookup_ite(s, __func__, devid, eventid, &ite, &dte); if (cmdres != CMD_CONTINUE_OK) { return cmdres; } - if (ite.inttype != ITE_INTTYPE_PHYSICAL) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid command attributes: invalid ITE\n", - __func__); - return CMD_CONTINUE; + irqlevel = (cmd == CLEAR || cmd == DISCARD) ? 0 : 1; + + switch (ite.inttype) { + case ITE_INTTYPE_PHYSICAL: + cmdres = process_its_cmd_phys(s, &ite, irqlevel); + break; + case ITE_INTTYPE_VIRTUAL: + if (!its_feature_virtual(s)) { + /* Can't happen unless guest is illegally writing to table memory */ + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid type %d in ITE (table corrupted?)\n", + __func__, ite.inttype); + return CMD_CONTINUE; + } + /* The GICv4 virtual interrupt handling will go here */ + g_assert_not_reached(); + default: + g_assert_not_reached(); } - cmdres = lookup_cte(s, __func__, ite.icid, &cte); - if (cmdres != CMD_CONTINUE_OK) { - return cmdres; - } - - if ((cmd == CLEAR) || (cmd == DISCARD)) { - gicv3_redist_process_lpi(&s->gicv3->cpu[cte.rdbase], ite.intid, 0); - } else { - gicv3_redist_process_lpi(&s->gicv3->cpu[cte.rdbase], ite.intid, 1); - } - - if (cmd == DISCARD) { + if (cmdres == CMD_CONTINUE_OK && cmd == DISCARD) { ITEntry ite = {}; /* remove mapping from interrupt translation table */ ite.valid = false; From patchwork Fri Apr 8 14:15:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558827 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp378182map; Fri, 8 Apr 2022 07:35:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwbhN5y+nNnkwcUDTXbvkBCcqWbp/8rCyKGVfe+eTHRmDCizHAHwZ3ODZN2jKnuQ5CKAiou X-Received: by 2002:a25:268a:0:b0:641:1592:80f8 with SMTP id m132-20020a25268a000000b00641159280f8mr960201ybm.328.1649428504001; Fri, 08 Apr 2022 07:35:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649428503; cv=none; d=google.com; s=arc-20160816; b=IEU/1KMhB1Mm5USIhVsLGzZ4U5ykrRUcVYMpx0vRjcC92h5Nxt94KixLV39XoLIE// U0OaZVDOwQcwtsaey4aeV1Dvf2NApg0QdwvtHR3y5TnAiNIHD3t5b9O6tTt/RB/dspsA uaw+ZJblNBfgWE5ASL9Lseff+o1CyXMoTwVCVfTvVzsMYPHtubb+U3KIwvPkzgR0qM5m SYeB9ijvTNE0itCr8p4O1pihE6RxA9Wa5czwOTf+nBSY6iT5/zIrumOFzOAxMKw18n97 fAF8p+FFhPf/n3DJrz+xL19vwEqz35o3tpP84578yMgx2ZltDkzEy33g7GM0trfE0/zz eTPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=r5Os54AuqgX8iDZbxzhpLBt252Rh5bhRamIuRASjQ/I=; b=ma5pNJIWWOUK0tdLiTagCJLj1eizFLf/szb43qHvkIothxEYlnAkm5bGrrxod72fzC h4LdgL7IzEstBUMJhGmtXnbqH+aXpMWBGuMjUbnfSIQos022k5aPbfjAmJioWTmsb1rr sM3lxOzj34xxAb2UHvr3Iev0dsZriwGUAHrCR5HKC+T1ZBVTR+Cf8BFSwkLSVbFC2DEc 87JH+0zG9yqe1PsxKxFFvpj6i19uwhGydgPMv8kxPIPi8436Uzk+ah0mSS96pVhtt2aw BVfp1wIqLpCkh4tXDa7PTJKbPZg9v5Y1WaBPp8doqiOb3Md8p3BvR5yjIJdNC0/W7af7 t2EQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=u0pwI84h; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:06 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 14/41] hw/intc/arm_gicv3_its: Handle virtual interrupts in process_its_cmd() Date: Fri, 8 Apr 2022 15:15:23 +0100 Message-Id: <20220408141550.1271295-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For GICv4, interrupt table entries read by process_its_cmd() may indicate virtual LPIs which are to be directly injected into a VM. Implement the ITS side of the code for handling this. This is similar to the existing handling of physical LPIs, but instead of looking up a collection ID in a collection table, we look up a vPEID in a vPE table. As with the physical LPIs, we leave the rest of the work to code in the redistributor device. The redistributor half will be implemented in a later commit; for now we just provide a stub function which does nothing. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/gicv3_internal.h | 17 +++++++ hw/intc/arm_gicv3_its.c | 99 +++++++++++++++++++++++++++++++++++++- hw/intc/arm_gicv3_redist.c | 9 ++++ hw/intc/trace-events | 2 + 4 files changed, 125 insertions(+), 2 deletions(-) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index bbb8a20ce61..6e22c8072e9 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -527,6 +527,23 @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data, void gicv3_dist_set_irq(GICv3State *s, int irq, int level); void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level); void gicv3_redist_process_lpi(GICv3CPUState *cs, int irq, int level); +/** + * gicv3_redist_process_vlpi: + * @cs: GICv3CPUState + * @irq: (virtual) interrupt number + * @vptaddr: (guest) address of VLPI table + * @doorbell: doorbell (physical) interrupt number (1023 for "no doorbell") + * @level: level to set @irq to + * + * Process a virtual LPI being directly injected by the ITS. This function + * will update the VLPI table specified by @vptaddr and @vptsize. If the + * vCPU corresponding to that VLPI table is currently running on + * the CPU associated with this redistributor, directly inject the VLPI + * @irq. If the vCPU is not running on this CPU, raise the doorbell + * interrupt instead. + */ +void gicv3_redist_process_vlpi(GICv3CPUState *cs, int irq, uint64_t vptaddr, + int doorbell, int level); void gicv3_redist_lpi_pending(GICv3CPUState *cs, int irq, int level); /** * gicv3_redist_update_lpi: diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index 8ea1fc366d3..21bc1a6c18b 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -314,6 +314,42 @@ out: return res; } +/* + * Read the vPE Table entry at index @vpeid. On success (including + * successfully determining that there is no valid entry for this index), + * we return MEMTX_OK and populate the VTEntry struct accordingly. + * If there is an error reading memory then we return the error code. + */ +static MemTxResult get_vte(GICv3ITSState *s, uint32_t vpeid, VTEntry *vte) +{ + MemTxResult res = MEMTX_OK; + AddressSpace *as = &s->gicv3->dma_as; + uint64_t entry_addr = table_entry_addr(s, &s->vpet, vpeid, &res); + uint64_t vteval; + + if (entry_addr == -1) { + /* No L2 table entry, i.e. no valid VTE, or a memory error */ + vte->valid = false; + goto out; + } + vteval = address_space_ldq_le(as, entry_addr, MEMTXATTRS_UNSPECIFIED, &res); + if (res != MEMTX_OK) { + goto out; + } + vte->valid = FIELD_EX64(vteval, VTE, VALID); + vte->vptsize = FIELD_EX64(vteval, VTE, VPTSIZE); + vte->vptaddr = FIELD_EX64(vteval, VTE, VPTADDR); + vte->rdbase = FIELD_EX64(vteval, VTE, RDBASE); +out: + if (res != MEMTX_OK) { + trace_gicv3_its_vte_read_fault(vpeid); + } else { + trace_gicv3_its_vte_read(vpeid, vte->valid, vte->vptsize, + vte->vptaddr, vte->rdbase); + } + return res; +} + /* * Given a (DeviceID, EventID), look up the corresponding ITE, including * checking for the various invalid-value cases. If we find a valid ITE, @@ -397,6 +433,38 @@ static ItsCmdResult lookup_cte(GICv3ITSState *s, const char *who, return CMD_CONTINUE_OK; } +/* + * Given a VPEID, look up the corresponding VTE, including checking + * for various invalid-value cases. if we find a valid VTE, fill in @vte + * and return CMD_CONTINUE_OK; otherwise return CMD_STALL or CMD_CONTINUE + * (and the contents of @vte should not be relied on). + * + * The string @who is purely for the LOG_GUEST_ERROR messages, + * and should indicate the name of the calling function or similar. + */ +static ItsCmdResult lookup_vte(GICv3ITSState *s, const char *who, + uint32_t vpeid, VTEntry *vte) +{ + if (vpeid >= s->vpet.num_entries) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid VPEID 0x%x\n", who, vpeid); + return CMD_CONTINUE; + } + + if (get_vte(s, vpeid, vte) != MEMTX_OK) { + return CMD_STALL; + } + if (!vte->valid) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid VTE for VPEID 0x%x\n", who, vpeid); + return CMD_CONTINUE; + } + + if (vte->rdbase >= s->gicv3->num_cpu) { + return CMD_CONTINUE; + } + return CMD_CONTINUE_OK; +} + static ItsCmdResult process_its_cmd_phys(GICv3ITSState *s, const ITEntry *ite, int irqlevel) { @@ -411,6 +479,33 @@ static ItsCmdResult process_its_cmd_phys(GICv3ITSState *s, const ITEntry *ite, return CMD_CONTINUE_OK; } +static ItsCmdResult process_its_cmd_virt(GICv3ITSState *s, const ITEntry *ite, + int irqlevel) +{ + VTEntry vte; + ItsCmdResult cmdres; + + cmdres = lookup_vte(s, __func__, ite->vpeid, &vte); + if (cmdres != CMD_CONTINUE_OK) { + return cmdres; + } + + if (!intid_in_lpi_range(ite->intid) || + ite->intid >= (1ULL << (vte.vptsize + 1))) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: intid 0x%x out of range\n", + __func__, ite->intid); + return CMD_CONTINUE; + } + + /* + * For QEMU the actual pending of the vLPI is handled in the + * redistributor code + */ + gicv3_redist_process_vlpi(&s->gicv3->cpu[vte.rdbase], ite->intid, + vte.vptaddr << 16, ite->doorbell, irqlevel); + return CMD_CONTINUE_OK; +} + /* * This function handles the processing of following commands based on * the ItsCmdType parameter passed:- @@ -446,8 +541,8 @@ static ItsCmdResult do_process_its_cmd(GICv3ITSState *s, uint32_t devid, __func__, ite.inttype); return CMD_CONTINUE; } - /* The GICv4 virtual interrupt handling will go here */ - g_assert_not_reached(); + cmdres = process_its_cmd_virt(s, &ite, irqlevel); + break; default: g_assert_not_reached(); } diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index dc9729e8395..b08b599c887 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -788,6 +788,15 @@ void gicv3_redist_movall_lpis(GICv3CPUState *src, GICv3CPUState *dest) gicv3_redist_update_lpi(dest); } +void gicv3_redist_process_vlpi(GICv3CPUState *cs, int irq, uint64_t vptaddr, + int doorbell, int level) +{ + /* + * The redistributor handling for being handed a VLPI by the ITS + * will be added in a subsequent commit. + */ +} + void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level) { /* Update redistributor state for a change in an external PPI input line */ diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 2fcc9e40e55..d529914eca2 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -200,6 +200,8 @@ gicv3_its_ite_write(uint64_t ittaddr, uint32_t eventid, int valid, int inttype, gicv3_its_dte_read(uint32_t devid, int valid, uint32_t size, uint64_t ittaddr) "GICv3 ITS: Device Table read for DeviceID 0x%x: valid %d size 0x%x ITTaddr 0x%" PRIx64 gicv3_its_dte_write(uint32_t devid, int valid, uint32_t size, uint64_t ittaddr) "GICv3 ITS: Device Table write for DeviceID 0x%x: valid %d size 0x%x ITTaddr 0x%" PRIx64 gicv3_its_dte_read_fault(uint32_t devid) "GICv3 ITS: Device Table read for DeviceID 0x%x: faulted" +gicv3_its_vte_read(uint32_t vpeid, int valid, uint32_t vptsize, uint64_t vptaddr, uint32_t rdbase) "GICv3 ITS: vPE Table read for vPEID 0x%x: valid %d VPTsize 0x%x VPTaddr 0x%" PRIx64 " RDbase 0x%x" +gicv3_its_vte_read_fault(uint32_t vpeid) "GICv3 ITS: vPE Table read for vPEID 0x%x: faulted" gicv3_its_vte_write(uint32_t vpeid, int valid, uint32_t vptsize, uint64_t vptaddr, uint32_t rdbase) "GICv3 ITS: vPE Table write for vPEID 0x%x: valid %d VPTsize 0x%x VPTaddr 0x%" PRIx64 " RDbase 0x%x" # armv7m_nvic.c From patchwork Fri Apr 8 14:15:24 2022 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:07 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 15/41] hw/intc/arm_gicv3: Keep pointers to every connected ITS Date: Fri, 8 Apr 2022 15:15:24 +0100 Message-Id: <20220408141550.1271295-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The GICv4 ITS VMOVP command's semantics require it to perform the operation on every ITS connected to the same GIC that the ITS that received the command is attached to. This means that the GIC object needs to keep a pointer to every ITS that is connected to it (previously it was sufficient for the ITS to have a pointer to its GIC). Add a glib ptrarray to the GICv3 object which holds pointers to every connected ITS, and make the ITS add itself to the array for the GIC it is connected to when it is realized. Note that currently all QEMU machine types with an ITS have exactly one ITS in the system, so typically the length of this ptrarray will be 1. Multiple ITSes are typically used to improve performance on real hardware, so we wouldn't need to have more than one unless we were modelling a real machine type that had multile ITSes. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/gicv3_internal.h | 9 +++++++++ include/hw/intc/arm_gicv3_common.h | 2 ++ hw/intc/arm_gicv3_common.c | 2 ++ hw/intc/arm_gicv3_its.c | 2 ++ hw/intc/arm_gicv3_its_kvm.c | 2 ++ 5 files changed, 17 insertions(+) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 6e22c8072e9..69a59daf867 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -709,4 +709,13 @@ static inline void gicv3_cache_all_target_cpustates(GICv3State *s) void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s); +/* + * The ITS should call this when it is realized to add itself + * to its GIC's list of connected ITSes. + */ +static inline void gicv3_add_its(GICv3State *s, DeviceState *its) +{ + g_ptr_array_add(s->itslist, its); +} + #endif /* QEMU_ARM_GICV3_INTERNAL_H */ diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h index fc38e4b7dca..08b27789385 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -272,6 +272,8 @@ struct GICv3State { uint32_t gicd_nsacr[DIV_ROUND_UP(GICV3_MAXIRQ, 16)]; GICv3CPUState *cpu; + /* List of all ITSes connected to this GIC */ + GPtrArray *itslist; }; #define GICV3_BITMAP_ACCESSORS(BMP) \ diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index c797c82786b..dcc5ce28c6a 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -414,6 +414,8 @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp) cpuidx += s->redist_region_count[i]; s->cpu[cpuidx - 1].gicr_typer |= GICR_TYPER_LAST; } + + s->itslist = g_ptr_array_new(); } static void arm_gicv3_finalize(Object *obj) diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index 21bc1a6c18b..6ff3c3b0348 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -1680,6 +1680,8 @@ static void gicv3_arm_its_realize(DeviceState *dev, Error **errp) } } + gicv3_add_its(s->gicv3, dev); + gicv3_its_init_mmio(s, &gicv3_its_control_ops, &gicv3_its_translation_ops); /* set the ITS default features supported */ diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c index 0b4cbed28b3..529c7bd4946 100644 --- a/hw/intc/arm_gicv3_its_kvm.c +++ b/hw/intc/arm_gicv3_its_kvm.c @@ -106,6 +106,8 @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp) kvm_arm_register_device(&s->iomem_its_cntrl, -1, KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_ITS_ADDR_TYPE, s->dev_fd, 0); + gicv3_add_its(s->gicv3, dev); + gicv3_its_init_mmio(s, NULL, NULL); if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, From patchwork Fri Apr 8 14:15:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558825 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp377335map; Fri, 8 Apr 2022 07:34:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyEGIkqy2hPf+bjjkNnnIZPV3f8IWwhiuOU3Xwvne6Gpc7Q1lGT6/pmGi+8IeBXG4Cepo+z X-Received: by 2002:a81:c8f:0:b0:2eb:e7a2:8954 with SMTP id 137-20020a810c8f000000b002ebe7a28954mr2290141ywm.28.1649428448532; Fri, 08 Apr 2022 07:34:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649428448; cv=none; d=google.com; s=arc-20160816; b=Edw5SAqKiK3F6eMcibtMEgSl9dt6AnRUKzLVuzgOxOwYeKM+sI6NyKqk2mC1ZgJbKl o0rpLh1fvdytjST784GQ3k1u5WAeFVXx6rPnktLQTQyGQB2O8zTbSatVEc0MQr14uXu3 W1a4apit7g0cyXqsfhxbeSugxgnOWhBQ/Vv70Ptg2NHt0gTlyJxt1zJ09jS8RYZ87Wre /WPWTpq5h1e7Lk/iH76IOcL5Apd/tXMp97h8VPczOkcmbuESmBkzjUzXMG7HcRbvvAQR lpVyaBAOl2baZHWTDOa1x0h/XnDD/JvqgMd5agM/62jkdCuexkGHhX/JQz+TTWBsN+6i 5y2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8It9aP5C1087IcKyM4TQrezews+cehKhHUndmZrknH4=; b=oeDfOwszH6PjxrOlWbPjp3qVYKopZvkdcJqHdrArcl2wZp3vCNWItKxhQqGnNFmTcJ 0T9dOCWXY10oXW2zjyyL9rCqoujXz5hrmjMKLTQfV+ThQGo9wmYHLrWxP5N66me+GTe5 r1hz5ss5IbRd43iFVj3onWUgx57Nhg+JvYHpVPMA09CtFQ5GTUhFRh0jq0aNmjGefqVF aX+xlINEHa3dLKdwgJ5euVnUWOCzGmdRa2I4CxMZ6PO6Y1IMjihgYyu0hOGFM1uXp7qn rGEAHeFU/bQ4OQJykRP7kYAS+4/BRnb3SmB+ly/I9YXlMmTlvy8wlOAGmUdsdXdMy1im iyfA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xkPpjGL7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:08 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 16/41] hw/intc/arm_gicv3_its: Implement VMOVP Date: Fri, 8 Apr 2022 15:15:25 +0100 Message-Id: <20220408141550.1271295-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Implement the GICv4 VMOVP command, which updates an entry in the vPE table to change its rdbase field. This command is unique in the ITS command set because its effects must be propagated to all the other ITSes connected to the same GIC as the ITS which executes the VMOVP command. The GICv4 spec allows two implementation choices for handling the propagation to other ITSes: * If GITS_TYPER.VMOVP is 1, the guest only needs to issue the command on one ITS, and the implementation handles the propagation to all ITSes * If GITS_TYPER.VMOVP is 0, the guest must issue the command on every ITS, and arrange for the ITSes to synchronize the updates with each other by setting ITSList and Sequence Number fields in the command packets We choose the GITS_TYPER.VMOVP = 1 approach, and synchronously execute the update on every ITS. For GICv4.1 this command has extra fields in the command packet and additional behaviour. We define the 4.1-only fields with the FIELD macro, but only implement the GICv4.0 version of the command. Note that we don't update the reported GITS_TYPER value here; we'll do that later in a commit which updates all the reported feature bit and ID register values for GICv4. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/gicv3_internal.h | 18 ++++++++++ hw/intc/arm_gicv3_its.c | 75 ++++++++++++++++++++++++++++++++++++++++ hw/intc/trace-events | 1 + 3 files changed, 94 insertions(+) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 69a59daf867..c1467ce7263 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -329,6 +329,7 @@ FIELD(GITS_TYPER, CIL, 36, 1) #define GITS_CMD_INVALL 0x0D #define GITS_CMD_MOVALL 0x0E #define GITS_CMD_DISCARD 0x0F +#define GITS_CMD_VMOVP 0x22 #define GITS_CMD_VMAPP 0x29 #define GITS_CMD_VMAPTI 0x2A #define GITS_CMD_VMAPI 0x2B @@ -389,6 +390,14 @@ FIELD(VMAPP_2, V, 63, 1) FIELD(VMAPP_3, VPTSIZE, 0, 8) /* For GICv4.0, bits [7:6] are RES0 */ FIELD(VMAPP_3, VPTADDR, 16, 36) +/* VMOVP command fields */ +FIELD(VMOVP_0, SEQNUM, 32, 16) /* not used for GITS_TYPER.VMOVP == 1 */ +FIELD(VMOVP_1, ITSLIST, 0, 16) /* not used for GITS_TYPER.VMOVP == 1 */ +FIELD(VMOVP_1, VPEID, 32, 16) +FIELD(VMOVP_2, RDBASE, 16, 36) +FIELD(VMOVP_2, DB, 63, 1) /* GICv4.1 only */ +FIELD(VMOVP_3, DEFAULT_DOORBELL, 0, 32) /* GICv4.1 only */ + /* * 12 bytes Interrupt translation Table Entry size * as per Table 5.3 in GICv3 spec @@ -718,4 +727,13 @@ static inline void gicv3_add_its(GICv3State *s, DeviceState *its) g_ptr_array_add(s->itslist, its); } +/* + * The ITS can use this for operations that must be performed on + * every ITS connected to the same GIC that it is + */ +static inline void gicv3_foreach_its(GICv3State *s, GFunc func, void *opaque) +{ + g_ptr_array_foreach(s->itslist, func, opaque); +} + #endif /* QEMU_ARM_GICV3_INTERNAL_H */ diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index 6ff3c3b0348..bd82c84b46d 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -1012,6 +1012,78 @@ static ItsCmdResult process_vmapp(GICv3ITSState *s, const uint64_t *cmdpkt) return update_vte(s, vpeid, &vte) ? CMD_CONTINUE_OK : CMD_STALL; } +typedef struct VmovpCallbackData { + uint64_t rdbase; + uint32_t vpeid; + /* + * Overall command result. If more than one callback finds an + * error, STALL beats CONTINUE. + */ + ItsCmdResult result; +} VmovpCallbackData; + +static void vmovp_callback(gpointer data, gpointer opaque) +{ + /* + * This function is called to update the VPEID field in a VPE + * table entry for this ITS. This might be because of a VMOVP + * command executed on any ITS that is connected to the same GIC + * as this ITS. We need to read the VPE table entry for the VPEID + * and update its RDBASE field. + */ + GICv3ITSState *s = data; + VmovpCallbackData *cbdata = opaque; + VTEntry vte; + ItsCmdResult cmdres; + + cmdres = lookup_vte(s, __func__, cbdata->vpeid, &vte); + switch (cmdres) { + case CMD_STALL: + cbdata->result = CMD_STALL; + return; + case CMD_CONTINUE: + if (cbdata->result != CMD_STALL) { + cbdata->result = CMD_CONTINUE; + } + return; + case CMD_CONTINUE_OK: + break; + } + + vte.rdbase = cbdata->rdbase; + if (!update_vte(s, cbdata->vpeid, &vte)) { + cbdata->result = CMD_STALL; + } +} + +static ItsCmdResult process_vmovp(GICv3ITSState *s, const uint64_t *cmdpkt) +{ + VmovpCallbackData cbdata; + + if (!its_feature_virtual(s)) { + return CMD_CONTINUE; + } + + cbdata.vpeid = FIELD_EX64(cmdpkt[1], VMOVP_1, VPEID); + cbdata.rdbase = FIELD_EX64(cmdpkt[2], VMOVP_2, RDBASE); + + trace_gicv3_its_cmd_vmovp(cbdata.vpeid, cbdata.rdbase); + + if (cbdata.rdbase >= s->gicv3->num_cpu) { + return CMD_CONTINUE; + } + + /* + * Our ITS implementation reports GITS_TYPER.VMOVP == 1, which means + * that when the VMOVP command is executed on an ITS to change the + * VPEID field in a VPE table entry the change must be propagated + * to all the ITSes connected to the same GIC. + */ + cbdata.result = CMD_CONTINUE_OK; + gicv3_foreach_its(s->gicv3, vmovp_callback, &cbdata); + return cbdata.result; +} + /* * Current implementation blocks until all * commands are processed @@ -1136,6 +1208,9 @@ static void process_cmdq(GICv3ITSState *s) case GITS_CMD_VMAPP: result = process_vmapp(s, cmdpkt); break; + case GITS_CMD_VMOVP: + result = process_vmovp(s, cmdpkt); + break; default: trace_gicv3_its_cmd_unknown(cmd); break; diff --git a/hw/intc/trace-events b/hw/intc/trace-events index d529914eca2..a2dd1bdb6c3 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -190,6 +190,7 @@ gicv3_its_cmd_movi(uint32_t devid, uint32_t eventid, uint32_t icid) "GICv3 ITS: gicv3_its_cmd_vmapi(uint32_t devid, uint32_t eventid, uint32_t vpeid, uint32_t doorbell) "GICv3 ITS: command VMAPI DeviceID 0x%x EventID 0x%x vPEID 0x%x Dbell_pINTID 0x%x" gicv3_its_cmd_vmapti(uint32_t devid, uint32_t eventid, uint32_t vpeid, uint32_t vintid, uint32_t doorbell) "GICv3 ITS: command VMAPI DeviceID 0x%x EventID 0x%x vPEID 0x%x vINTID 0x%x Dbell_pINTID 0x%x" gicv3_its_cmd_vmapp(uint32_t vpeid, uint64_t rdbase, int valid, uint64_t vptaddr, uint32_t vptsize) "GICv3 ITS: command VMAPP vPEID 0x%x RDbase 0x%" PRIx64 " V %d VPT_addr 0x%" PRIx64 " VPT_size 0x%x" +gicv3_its_cmd_vmovp(uint32_t vpeid, uint64_t rdbase) "GICv3 ITS: command VMOVP vPEID 0x%x RDbase 0x%" PRIx64 gicv3_its_cmd_unknown(unsigned cmd) "GICv3 ITS: unknown command 0x%x" gicv3_its_cte_read(uint32_t icid, int valid, uint32_t rdbase) "GICv3 ITS: Collection Table read for ICID 0x%x: valid %d RDBase 0x%x" gicv3_its_cte_write(uint32_t icid, int valid, uint32_t rdbase) "GICv3 ITS: Collection Table write for ICID 0x%x: valid %d RDBase 0x%x" From patchwork Fri Apr 8 14:15:26 2022 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:09 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 17/41] hw/intc/arm_gicv3_its: Implement VSYNC Date: Fri, 8 Apr 2022 15:15:26 +0100 Message-Id: <20220408141550.1271295-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The VSYNC command forces the ITS to synchronize all outstanding ITS operations for the specified vPEID, so that subsequent writse to GITS_TRANSLATER honour them. The QEMU implementation is always in sync, so for us this is a nop, like the existing SYNC command. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/gicv3_internal.h | 1 + hw/intc/arm_gicv3_its.c | 11 +++++++++++ hw/intc/trace-events | 1 + 3 files changed, 13 insertions(+) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index c1467ce7263..ef1d75b3cf4 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -330,6 +330,7 @@ FIELD(GITS_TYPER, CIL, 36, 1) #define GITS_CMD_MOVALL 0x0E #define GITS_CMD_DISCARD 0x0F #define GITS_CMD_VMOVP 0x22 +#define GITS_CMD_VSYNC 0x25 #define GITS_CMD_VMAPP 0x29 #define GITS_CMD_VMAPTI 0x2A #define GITS_CMD_VMAPI 0x2B diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index bd82c84b46d..05d64630450 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -1165,6 +1165,17 @@ static void process_cmdq(GICv3ITSState *s) */ trace_gicv3_its_cmd_sync(); break; + case GITS_CMD_VSYNC: + /* + * VSYNC also is a nop, because our implementation is always + * in sync. + */ + if (!its_feature_virtual(s)) { + result = CMD_CONTINUE; + break; + } + trace_gicv3_its_cmd_vsync(); + break; case GITS_CMD_MAPD: result = process_mapd(s, cmdpkt); break; diff --git a/hw/intc/trace-events b/hw/intc/trace-events index a2dd1bdb6c3..b9efe14c690 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -191,6 +191,7 @@ gicv3_its_cmd_vmapi(uint32_t devid, uint32_t eventid, uint32_t vpeid, uint32_t d gicv3_its_cmd_vmapti(uint32_t devid, uint32_t eventid, uint32_t vpeid, uint32_t vintid, uint32_t doorbell) "GICv3 ITS: command VMAPI DeviceID 0x%x EventID 0x%x vPEID 0x%x vINTID 0x%x Dbell_pINTID 0x%x" gicv3_its_cmd_vmapp(uint32_t vpeid, uint64_t rdbase, int valid, uint64_t vptaddr, uint32_t vptsize) "GICv3 ITS: command VMAPP vPEID 0x%x RDbase 0x%" PRIx64 " V %d VPT_addr 0x%" PRIx64 " VPT_size 0x%x" gicv3_its_cmd_vmovp(uint32_t vpeid, uint64_t rdbase) "GICv3 ITS: command VMOVP vPEID 0x%x RDbase 0x%" PRIx64 +gicv3_its_cmd_vsync(void) "GICv3 ITS: command VSYNC" gicv3_its_cmd_unknown(unsigned cmd) "GICv3 ITS: unknown command 0x%x" gicv3_its_cte_read(uint32_t icid, int valid, uint32_t rdbase) "GICv3 ITS: Collection Table read for ICID 0x%x: valid %d RDBase 0x%x" gicv3_its_cte_write(uint32_t icid, int valid, uint32_t rdbase) "GICv3 ITS: Collection Table write for ICID 0x%x: valid %d RDBase 0x%x" From patchwork Fri Apr 8 14:15:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558818 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp372096map; Fri, 8 Apr 2022 07:28:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzHRHmLHUnXTL9Cp4otFrJTGo1NdbhqvhhqqpferdnJ53Vk9WMCqepjVT8AbQDx173fxGLH X-Received: by 2002:a25:f54:0:b0:63d:e875:11f5 with SMTP id 81-20020a250f54000000b0063de87511f5mr13101886ybp.25.1649428097632; Fri, 08 Apr 2022 07:28:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649428097; cv=none; d=google.com; s=arc-20160816; b=XrZBpv8Td+CK7CKgHBaetUofnihIfRSAK/qt0p7KWh9CFCabYv4qipdzA1H8Ttz/YB XCxCoeyhHFmMdhyigmY1mRECL348nyKY+2JQc4L8t+skGHYOEHwMwMpWG9cRGMpmy/CY KWBgkU5UX0gHTTbthPw7XDASfsYfBok7TLT6Z+ucflKKq1GKi8uD4MMVjrA/rA8mGmc1 5xUeO3gFvwbCnf/w21HRcjf9fQqZOD1gZ6/YInCUms9U7zdGCUc/K16JMReQFOtFgp9w hO5w6T4TOkAcVZmvj0elwdBVl7QSFMFfG/ki7SOgNkMRXO+CDDE+eEOBXTVhcar79Eog 62yg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ZRoPRBmXacMzWSmsgshOhCccbNOLKeiYJX1157x7z/M=; b=qufOCjXFdphUsnlBZeGolHsmjGo6ml5H9jfqHQba7aq55lnDgUG+ZghK5q7axwqhbp bjw1Ddi/OAqU8PgsPNsPaZ+cY6k67EvawSgsSD9S03KsJkypKfzSTFkrfdC4LtRPI40f AP1Zsp5rcocTjuOBhwcHx8IS/yMhVrJvrECfgJ4dYWzgCwT5c5GbMktfBeK3WtqakEfk m/Fnn4FIcppLxo/I4W4GVVEuxmF4/IOihDkdU5qQOpjTMT0aTbaBCdEbAYxsHRDTmd7A dkfaeQ9uH0X9eL37H7DYnPSK3gozTMY8sA5/OlPfOL8nitp4jypOlVP5cB62sdzjj8dZ MO9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cb1qfChv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:10 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 18/41] hw/intc/arm_gicv3_its: Implement INV command properly Date: Fri, 8 Apr 2022 15:15:27 +0100 Message-Id: <20220408141550.1271295-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We were previously implementing INV (like INVALL) to just blow away cached highest-priority-pending-LPI information on all connected redistributors. For GICv4.0, this isn't going to be sufficient, because the LPI we are invalidating cached information for might be either physical or virtual, and the required action is different for those two cases. So we need to do the full process of looking up the ITE from the devid and eventid. This also means we can do the error checks that the spec lists for this command. Split out INV handling into a process_inv() function like our other command-processing functions. For the moment, stick to handling only physical LPIs; we will add the vLPI parts later. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- We could also improve INVALL to only prod the one redistributor specified by the ICID in the command packet, but since INVALL is only for physical LPIs I am leaving it as it is. --- hw/intc/gicv3_internal.h | 12 +++++++++ hw/intc/arm_gicv3_its.c | 50 +++++++++++++++++++++++++++++++++++++- hw/intc/arm_gicv3_redist.c | 11 +++++++++ hw/intc/trace-events | 3 ++- 4 files changed, 74 insertions(+), 2 deletions(-) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index ef1d75b3cf4..25ea19de385 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -373,6 +373,10 @@ FIELD(MOVI_0, DEVICEID, 32, 32) FIELD(MOVI_1, EVENTID, 0, 32) FIELD(MOVI_2, ICID, 0, 16) +/* INV command fields */ +FIELD(INV_0, DEVICEID, 32, 32) +FIELD(INV_1, EVENTID, 0, 32) + /* VMAPI, VMAPTI command fields */ FIELD(VMAPTI_0, DEVICEID, 32, 32) FIELD(VMAPTI_1, EVENTID, 0, 32) @@ -573,6 +577,14 @@ void gicv3_redist_update_lpi(GICv3CPUState *cs); * an incoming migration has loaded new state. */ void gicv3_redist_update_lpi_only(GICv3CPUState *cs); +/** + * gicv3_redist_inv_lpi: + * @cs: GICv3CPUState + * @irq: LPI to invalidate cached information for + * + * Forget or update any cached information associated with this LPI. + */ +void gicv3_redist_inv_lpi(GICv3CPUState *cs, int irq); /** * gicv3_redist_mov_lpi: * @src: source redistributor diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index 05d64630450..6ba554c16ea 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -1084,6 +1084,50 @@ static ItsCmdResult process_vmovp(GICv3ITSState *s, const uint64_t *cmdpkt) return cbdata.result; } +static ItsCmdResult process_inv(GICv3ITSState *s, const uint64_t *cmdpkt) +{ + uint32_t devid, eventid; + ITEntry ite; + DTEntry dte; + CTEntry cte; + ItsCmdResult cmdres; + + devid = FIELD_EX64(cmdpkt[0], INV_0, DEVICEID); + eventid = FIELD_EX64(cmdpkt[1], INV_1, EVENTID); + + trace_gicv3_its_cmd_inv(devid, eventid); + + cmdres = lookup_ite(s, __func__, devid, eventid, &ite, &dte); + if (cmdres != CMD_CONTINUE_OK) { + return cmdres; + } + + switch (ite.inttype) { + case ITE_INTTYPE_PHYSICAL: + cmdres = lookup_cte(s, __func__, ite.icid, &cte); + if (cmdres != CMD_CONTINUE_OK) { + return cmdres; + } + gicv3_redist_inv_lpi(&s->gicv3->cpu[cte.rdbase], ite.intid); + break; + case ITE_INTTYPE_VIRTUAL: + if (!its_feature_virtual(s)) { + /* Can't happen unless guest is illegally writing to table memory */ + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid type %d in ITE (table corrupted?)\n", + __func__, ite.inttype); + return CMD_CONTINUE; + } + /* We will implement the vLPI invalidation in a later commit */ + g_assert_not_reached(); + break; + default: + g_assert_not_reached(); + } + + return CMD_CONTINUE_OK; +} + /* * Current implementation blocks until all * commands are processed @@ -1192,14 +1236,18 @@ static void process_cmdq(GICv3ITSState *s) result = process_its_cmd(s, cmdpkt, DISCARD); break; case GITS_CMD_INV: + result = process_inv(s, cmdpkt); + break; case GITS_CMD_INVALL: /* * Current implementation doesn't cache any ITS tables, * but the calculated lpi priority information. We only * need to trigger lpi priority re-calculation to be in * sync with LPI config table or pending table changes. + * INVALL operates on a collection specified by ICID so + * it only affects physical LPIs. */ - trace_gicv3_its_cmd_inv(); + trace_gicv3_its_cmd_invall(); for (i = 0; i < s->gicv3->num_cpu; i++) { gicv3_redist_update_lpi(&s->gicv3->cpu[i]); } diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index b08b599c887..78650a3bb4c 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -681,6 +681,17 @@ void gicv3_redist_process_lpi(GICv3CPUState *cs, int irq, int level) gicv3_redist_lpi_pending(cs, irq, level); } +void gicv3_redist_inv_lpi(GICv3CPUState *cs, int irq) +{ + /* + * The only cached information for LPIs we have is the HPPLPI. + * We could be cleverer about identifying when we don't need + * to do a full rescan of the pending table, but until we find + * this is a performance issue, just always recalculate. + */ + gicv3_redist_update_lpi(cs); +} + void gicv3_redist_mov_lpi(GICv3CPUState *src, GICv3CPUState *dest, int irq) { /* diff --git a/hw/intc/trace-events b/hw/intc/trace-events index b9efe14c690..ae4a3cfb004 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -184,7 +184,8 @@ gicv3_its_cmd_mapd(uint32_t devid, uint32_t size, uint64_t ittaddr, int valid) " gicv3_its_cmd_mapc(uint32_t icid, uint64_t rdbase, int valid) "GICv3 ITS: command MAPC ICID 0x%x RDbase 0x%" PRIx64 " V %d" gicv3_its_cmd_mapi(uint32_t devid, uint32_t eventid, uint32_t icid) "GICv3 ITS: command MAPI DeviceID 0x%x EventID 0x%x ICID 0x%x" gicv3_its_cmd_mapti(uint32_t devid, uint32_t eventid, uint32_t icid, uint32_t intid) "GICv3 ITS: command MAPTI DeviceID 0x%x EventID 0x%x ICID 0x%x pINTID 0x%x" -gicv3_its_cmd_inv(void) "GICv3 ITS: command INV or INVALL" +gicv3_its_cmd_inv(uint32_t devid, uint32_t eventid) "GICv3 ITS: command INV DeviceID 0x%x EventID 0x%x" +gicv3_its_cmd_invall(void) "GICv3 ITS: command INVALL" gicv3_its_cmd_movall(uint64_t rd1, uint64_t rd2) "GICv3 ITS: command MOVALL RDbase1 0x%" PRIx64 " RDbase2 0x%" PRIx64 gicv3_its_cmd_movi(uint32_t devid, uint32_t eventid, uint32_t icid) "GICv3 ITS: command MOVI DeviceID 0x%x EventID 0x%x ICID 0x%x" gicv3_its_cmd_vmapi(uint32_t devid, uint32_t eventid, uint32_t vpeid, uint32_t doorbell) "GICv3 ITS: command VMAPI DeviceID 0x%x EventID 0x%x vPEID 0x%x Dbell_pINTID 0x%x" From patchwork Fri Apr 8 14:15:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558829 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp380392map; Fri, 8 Apr 2022 07:37:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzXjoFe5nfmJ8K9/IPF11LCko1eXDAtf1rFPHsQg9Z1BDuuj5gzYzq8k0hpDWxWSzdUhsQ3 X-Received: by 2002:a25:b591:0:b0:63e:387:1350 with SMTP id q17-20020a25b591000000b0063e03871350mr14996264ybj.224.1649428673435; Fri, 08 Apr 2022 07:37:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649428673; cv=none; d=google.com; s=arc-20160816; b=c268Rsn//U3R+xZCb85fhIUmZyRtAjBcfP8GrNd8fvMVPiHAHFXvFhhaF8Oylqcr22 5JD2k/zQ/6Z8/wOIj3VBTcMqUUCJnQALRCHG32OvPvHmdE8mKTiiEYS8Dcx42sj7AcXU GLZhdo6w8VPr91NhYnZagq7jGYjuuGBoaErnK7yWnYpVGQ/oKl0/DLYigJAqRh4Q3G3P Av8XdWL087Xnnj182W9yS76i2+CCpj0Vk85ZKSStu249VAVG6345tL2j+J8uL0e3uIB8 pZmCLZkyAOIu3fDMkFB8Zp283DcWrmsCrhElkhA0DgPQVcAHqxd0GTfXfUERRzxytkfE gx/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=IW3bX6iSTzjY92yAkhrP7T+aVrPKgsiAz2F7JAZ7pV8=; b=xIngadvyIp5LVsnPJErL59PufTsIkKAC4tCyVjgsfYXZUxxCZ90BTAomj9wiM6gd7q qa6SFPkT4trZcHlLJ9uUKjpsEtREvU0hTbHhTZ3Emp+/gV4amBFy8b2+XSs8xZdlDvLW ZT32inerCcLu6gOhXFItf6qaBElbe4CCzJXTvUBZMwgtYsYnE9hrvRhrDQY+HN0KhHMq 7ByDNHm/Kat5CWU2pkDsZd+e3PVsKTijgsbPYwZHT98I0jNirHJUJTDX6nhfCzIxT4qc AReUNWzY2Qj4Ik+Z71ezC6A5ogO1MRCvRQf1CFrN4SN9v7e4fVwj6YW36xLbOjvPK/E6 aJvA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CLTVJ1sp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:10 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 19/41] hw/intc/arm_gicv3_its: Implement INV for virtual interrupts Date: Fri, 8 Apr 2022 15:15:28 +0100 Message-Id: <20220408141550.1271295-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Implement the ITS side of the handling of the INV command for virtual interrupts; as usual this calls into a redistributor function which we leave as a stub to fill in later. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/gicv3_internal.h | 9 +++++++++ hw/intc/arm_gicv3_its.c | 16 ++++++++++++++-- hw/intc/arm_gicv3_redist.c | 8 ++++++++ 3 files changed, 31 insertions(+), 2 deletions(-) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 25ea19de385..2f653a9b917 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -585,6 +585,15 @@ void gicv3_redist_update_lpi_only(GICv3CPUState *cs); * Forget or update any cached information associated with this LPI. */ void gicv3_redist_inv_lpi(GICv3CPUState *cs, int irq); +/** + * gicv3_redist_inv_vlpi: + * @cs: GICv3CPUState + * @irq: vLPI to invalidate cached information for + * @vptaddr: (guest) address of vLPI table + * + * Forget or update any cached information associated with this vLPI. + */ +void gicv3_redist_inv_vlpi(GICv3CPUState *cs, int irq, uint64_t vptaddr); /** * gicv3_redist_mov_lpi: * @src: source redistributor diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index 6ba554c16ea..c8b90e6b0d9 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -1090,6 +1090,7 @@ static ItsCmdResult process_inv(GICv3ITSState *s, const uint64_t *cmdpkt) ITEntry ite; DTEntry dte; CTEntry cte; + VTEntry vte; ItsCmdResult cmdres; devid = FIELD_EX64(cmdpkt[0], INV_0, DEVICEID); @@ -1118,8 +1119,19 @@ static ItsCmdResult process_inv(GICv3ITSState *s, const uint64_t *cmdpkt) __func__, ite.inttype); return CMD_CONTINUE; } - /* We will implement the vLPI invalidation in a later commit */ - g_assert_not_reached(); + + cmdres = lookup_vte(s, __func__, ite.vpeid, &vte); + if (cmdres != CMD_CONTINUE_OK) { + return cmdres; + } + if (!intid_in_lpi_range(ite.intid) || + ite.intid >= (1ULL << (vte.vptsize + 1))) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: intid 0x%x out of range\n", + __func__, ite.intid); + return CMD_CONTINUE; + } + gicv3_redist_inv_vlpi(&s->gicv3->cpu[vte.rdbase], ite.intid, + vte.vptaddr << 16); break; default: g_assert_not_reached(); diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 78650a3bb4c..856494b4e8f 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -808,6 +808,14 @@ void gicv3_redist_process_vlpi(GICv3CPUState *cs, int irq, uint64_t vptaddr, */ } +void gicv3_redist_inv_vlpi(GICv3CPUState *cs, int irq, uint64_t vptaddr) +{ + /* + * The redistributor handling for invalidating cached information + * about a VLPI will be added in a subsequent commit. + */ +} + void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level) { /* Update redistributor state for a change in an external PPI input line */ From patchwork Fri Apr 8 14:15:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558816 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp370819map; Fri, 8 Apr 2022 07:26:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyGytynf3K29tQVYlVcmyZJyk9LLCesQdDVcVfFCd39/s1wfQ5/nzOpdXeeNQ6NQXpHi8Xk X-Received: by 2002:a05:690c:13:b0:2e4:da22:27d9 with SMTP id bc19-20020a05690c001300b002e4da2227d9mr16950440ywb.298.1649428004598; Fri, 08 Apr 2022 07:26:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649428004; cv=none; d=google.com; s=arc-20160816; b=r3nkavppbIY3e9XK6kVKtAkIdf3KPleQHl/HQ+Z83w8WFZrwqtDbSV4eXIdm0FVrso Ssm5x5WwABsThIAZWHZTT1JR+UNEGxM0n+eDYxyZYSNLqKYFSG9r0rx/PxTd1xhyi2Ti 84ICrUWt0cbAUgtoyKumCNivA9cOsKEVK44kx9iP30JW+M0/J+g90gwxTyMKFh1WAYpX 0SKI/Ksr/8XDThHiAiR5+NU6f/UZawPWD0Lrltwn96L4UrC7BlrQn0oOLIhLOS0KO0IN S5wTjwnHIED7CcMXpRh9ojJna2aTD6L5vDb2Wap87dhjQAApDCUtO19gf5sAxCU17u/C HPDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lAmRCo+P0tpuQq9W7lDg7RirtMlu4mcCLIbEFy1deTM=; b=sPXotvVF4GbX1sZm/uGJ9PE3qyQIwh4+d5Akr6IMhPkzkMz19Py+O/514yhXWyAL81 rDrW4RJuIU7MK4j+AB/gJFQLqhwRKNVJGyu5enU+L1oEbx+9WFQDLOiH99/XSDBo9Ja/ o/7AauNi7YsNfn6JRfjF060OKLVSWBQtBD6C0wzoUDorrtVU80yP5R2JH4fyDkGooOZ6 UBP3ydYXrdWeom5G2Af6Uqxy7KtxYuW8bAF2oOuFN7BuWBN3DmSeZ6zhzVdhJgnkDmPK bYPJYoqljQtWul1Man0MQN25yDXtMffYvtN5G6XqSeXZ/TiB2Y3Dc8iT+n9p7bqxah9z O/mg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uYIZskyB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:12 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 20/41] hw/intc/arm_gicv3_its: Implement VMOVI Date: Fri, 8 Apr 2022 15:15:29 +0100 Message-Id: <20220408141550.1271295-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Implement the GICv4 VMOVI command, which moves the pending state of a virtual interrupt from one redistributor to another. As with MOVI, we handle the "parse and validate command arguments and table lookups" part in the ITS source file, and pass the final results to a function in the redistributor which will do the actual operation. As with the "make a VLPI pending" change, for the moment we leave that redistributor function as a stub, to be implemented in a later commit. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/gicv3_internal.h | 23 +++++++++++ hw/intc/arm_gicv3_its.c | 82 ++++++++++++++++++++++++++++++++++++++ hw/intc/arm_gicv3_redist.c | 10 +++++ hw/intc/trace-events | 1 + 4 files changed, 116 insertions(+) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 2f653a9b917..050e19d133b 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -329,6 +329,7 @@ FIELD(GITS_TYPER, CIL, 36, 1) #define GITS_CMD_INVALL 0x0D #define GITS_CMD_MOVALL 0x0E #define GITS_CMD_DISCARD 0x0F +#define GITS_CMD_VMOVI 0x21 #define GITS_CMD_VMOVP 0x22 #define GITS_CMD_VSYNC 0x25 #define GITS_CMD_VMAPP 0x29 @@ -403,6 +404,13 @@ FIELD(VMOVP_2, RDBASE, 16, 36) FIELD(VMOVP_2, DB, 63, 1) /* GICv4.1 only */ FIELD(VMOVP_3, DEFAULT_DOORBELL, 0, 32) /* GICv4.1 only */ +/* VMOVI command fields */ +FIELD(VMOVI_0, DEVICEID, 32, 32) +FIELD(VMOVI_1, EVENTID, 0, 32) +FIELD(VMOVI_1, VPEID, 32, 16) +FIELD(VMOVI_2, D, 0, 1) +FIELD(VMOVI_2, DOORBELL, 32, 32) + /* * 12 bytes Interrupt translation Table Entry size * as per Table 5.3 in GICv3 spec @@ -614,6 +622,21 @@ void gicv3_redist_mov_lpi(GICv3CPUState *src, GICv3CPUState *dest, int irq); * by the ITS MOVALL command. */ void gicv3_redist_movall_lpis(GICv3CPUState *src, GICv3CPUState *dest); +/** + * gicv3_redist_mov_vlpi: + * @src: source redistributor + * @src_vptaddr: (guest) address of source VLPI table + * @dest: destination redistributor + * @dest_vptaddr: (guest) address of destination VLPI table + * @irq: VLPI to update + * @doorbell: doorbell for destination (1023 for "no doorbell") + * + * Move the pending state of the specified VLPI from @src to @dest, + * as required by the ITS VMOVI command. + */ +void gicv3_redist_mov_vlpi(GICv3CPUState *src, uint64_t src_vptaddr, + GICv3CPUState *dest, uint64_t dest_vptaddr, + int irq, int doorbell); void gicv3_redist_send_sgi(GICv3CPUState *cs, int grp, int irq, bool ns); void gicv3_init_cpuif(GICv3State *s); diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index c8b90e6b0d9..aef024009b2 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -1084,6 +1084,85 @@ static ItsCmdResult process_vmovp(GICv3ITSState *s, const uint64_t *cmdpkt) return cbdata.result; } +static ItsCmdResult process_vmovi(GICv3ITSState *s, const uint64_t *cmdpkt) +{ + uint32_t devid, eventid, vpeid, doorbell; + bool doorbell_valid; + DTEntry dte; + ITEntry ite; + VTEntry old_vte, new_vte; + ItsCmdResult cmdres; + + if (!its_feature_virtual(s)) { + return CMD_CONTINUE; + } + + devid = FIELD_EX64(cmdpkt[0], VMOVI_0, DEVICEID); + eventid = FIELD_EX64(cmdpkt[1], VMOVI_1, EVENTID); + vpeid = FIELD_EX64(cmdpkt[1], VMOVI_1, VPEID); + doorbell_valid = FIELD_EX64(cmdpkt[2], VMOVI_2, D); + doorbell = FIELD_EX64(cmdpkt[2], VMOVI_2, DOORBELL); + + trace_gicv3_its_cmd_vmovi(devid, eventid, vpeid, doorbell_valid, doorbell); + + if (doorbell_valid && !valid_doorbell(doorbell)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid doorbell 0x%x\n", __func__, doorbell); + return CMD_CONTINUE; + } + + cmdres = lookup_ite(s, __func__, devid, eventid, &ite, &dte); + if (cmdres != CMD_CONTINUE_OK) { + return cmdres; + } + + if (ite.inttype != ITE_INTTYPE_VIRTUAL) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: ITE is not for virtual interrupt\n", + __func__); + return CMD_CONTINUE; + } + + cmdres = lookup_vte(s, __func__, ite.vpeid, &old_vte); + if (cmdres != CMD_CONTINUE_OK) { + return cmdres; + } + cmdres = lookup_vte(s, __func__, vpeid, &new_vte); + if (cmdres != CMD_CONTINUE_OK) { + return cmdres; + } + + if (!intid_in_lpi_range(ite.intid) || + ite.intid >= (1ULL << (old_vte.vptsize + 1)) || + ite.intid >= (1ULL << (new_vte.vptsize + 1))) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: ITE intid 0x%x out of range\n", + __func__, ite.intid); + return CMD_CONTINUE; + } + + ite.vpeid = vpeid; + if (doorbell_valid) { + ite.doorbell = doorbell; + } + + /* + * Move the LPI from the old redistributor to the new one. We don't + * need to do anything if the guest somehow specified the + * same pending table for source and destination. + */ + if (old_vte.vptaddr != new_vte.vptaddr) { + gicv3_redist_mov_vlpi(&s->gicv3->cpu[old_vte.rdbase], + old_vte.vptaddr << 16, + &s->gicv3->cpu[new_vte.rdbase], + new_vte.vptaddr << 16, + ite.intid, + ite.doorbell); + } + + /* Update the ITE to the new VPEID and possibly doorbell values */ + return update_ite(s, eventid, &dte, &ite) ? CMD_CONTINUE_OK : CMD_STALL; +} + static ItsCmdResult process_inv(GICv3ITSState *s, const uint64_t *cmdpkt) { uint32_t devid, eventid; @@ -1282,6 +1361,9 @@ static void process_cmdq(GICv3ITSState *s) case GITS_CMD_VMOVP: result = process_vmovp(s, cmdpkt); break; + case GITS_CMD_VMOVI: + result = process_vmovi(s, cmdpkt); + break; default: trace_gicv3_its_cmd_unknown(cmd); break; diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 856494b4e8f..dc25997d1f9 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -808,6 +808,16 @@ void gicv3_redist_process_vlpi(GICv3CPUState *cs, int irq, uint64_t vptaddr, */ } +void gicv3_redist_mov_vlpi(GICv3CPUState *src, uint64_t src_vptaddr, + GICv3CPUState *dest, uint64_t dest_vptaddr, + int irq, int doorbell) +{ + /* + * The redistributor handling for moving a VLPI will be added + * in a subsequent commit. + */ +} + void gicv3_redist_inv_vlpi(GICv3CPUState *cs, int irq, uint64_t vptaddr) { /* diff --git a/hw/intc/trace-events b/hw/intc/trace-events index ae4a3cfb004..9894756e55a 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -193,6 +193,7 @@ gicv3_its_cmd_vmapti(uint32_t devid, uint32_t eventid, uint32_t vpeid, uint32_t gicv3_its_cmd_vmapp(uint32_t vpeid, uint64_t rdbase, int valid, uint64_t vptaddr, uint32_t vptsize) "GICv3 ITS: command VMAPP vPEID 0x%x RDbase 0x%" PRIx64 " V %d VPT_addr 0x%" PRIx64 " VPT_size 0x%x" gicv3_its_cmd_vmovp(uint32_t vpeid, uint64_t rdbase) "GICv3 ITS: command VMOVP vPEID 0x%x RDbase 0x%" PRIx64 gicv3_its_cmd_vsync(void) "GICv3 ITS: command VSYNC" +gicv3_its_cmd_vmovi(uint32_t devid, uint32_t eventid, uint32_t vpeid, int dbvalid, uint32_t doorbell) "GICv3 ITS: command VMOVI DeviceID 0x%x EventID 0x%x vPEID 0x%x D %d Dbell_pINTID 0x%x" gicv3_its_cmd_unknown(unsigned cmd) "GICv3 ITS: unknown command 0x%x" gicv3_its_cte_read(uint32_t icid, int valid, uint32_t rdbase) "GICv3 ITS: Collection Table read for ICID 0x%x: valid %d RDBase 0x%x" gicv3_its_cte_write(uint32_t icid, int valid, uint32_t rdbase) "GICv3 ITS: Collection Table write for ICID 0x%x: valid %d RDBase 0x%x" From patchwork Fri Apr 8 14:15:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558822 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp375328map; Fri, 8 Apr 2022 07:32:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwORUVVlPxJTtNGl3puFbcpC52kFUwqsQmorZ99H1gWF1anPeNDqm4mWCdeUxGDXdyO/6xU X-Received: by 2002:a25:e311:0:b0:61e:9e77:a455 with SMTP id z17-20020a25e311000000b0061e9e77a455mr13945811ybd.567.1649428322072; Fri, 08 Apr 2022 07:32:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649428322; cv=none; d=google.com; s=arc-20160816; b=vKILUm7T1Rl//SK4ozsTa343wJPjmiPDkUD/LOmV71thrgF2jVgSAkPQ85vZ6mydr+ HwmRll+RK7gK1/7H1o6Vo2Zu+RvtHbSICGlMdMAVkKeBPpTvbnGydb7SnJ0SZZC1BMQm 0jY0PCnLcZcmZ2ophcsrsONzzSR2oqlM7/xUkHWdYqo9GPqGQ3dbIiNVvFvEyxSY6HcJ o46SZxfSN0bZ4RBoo1MstIRsCz4FyDg/SNw7+z6ujPRcdKctey0rjmKhaQif6wmmlazP bvUHEY/UbvlehyKneT86HjUnP9W7eWVqiij7a5HV1MEW2enZt+iT2Rqk2yDD840gyKr+ K/GQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kvY7XIDQD5f22XxKR8jUlDNLZTSeCG2ZcDviwiXdLAA=; b=A70Coapkk48aAip9WDSSIAJVBZtEFhrKEcHlrQ66Ft3dzt+tIjFX1vDV3z/Q/LiomQ eoyjuETxERjPHW9nAECZaapMrdiuWbSXhGRcwyCgauEqb8n1DSQB5CzZQZ3RgGaJSm7B eVxvEMZlHZofTP6lIAel/HQIyzhCjqofCbfbnCENRwJH6kGjXz4963w4OZUZkFPcAUBL aLU5NCj/yEyF9pLcjdz1A4qd2mCDmetzLlRVKJuWw/NZZ32msGe3vr9AF3Cg1guchV0v hW4q3TMLbyUqRnmW6L2/IF4DKMafSRAd58Knyuw0iDHKRdr1P2uvt+w4nBOMYNXIHQ4b Gn5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=r4eXNSHj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:12 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 21/41] hw/intc/arm_gicv3_its: Implement VINVALL Date: Fri, 8 Apr 2022 15:15:30 +0100 Message-Id: <20220408141550.1271295-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The VINVALL command should cause any cached information in the ITS or redistributor for the specified vCPU to be dropped or otherwise made consistent with the in-memory LPI configuration tables. Here we implement the command and table parsing, leaving the redistributor part as a stub for the moment, as usual. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/gicv3_internal.h | 13 +++++++++++++ hw/intc/arm_gicv3_its.c | 26 ++++++++++++++++++++++++++ hw/intc/arm_gicv3_redist.c | 5 +++++ hw/intc/trace-events | 1 + 4 files changed, 45 insertions(+) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 050e19d133b..8d58d38836f 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -335,6 +335,7 @@ FIELD(GITS_TYPER, CIL, 36, 1) #define GITS_CMD_VMAPP 0x29 #define GITS_CMD_VMAPTI 0x2A #define GITS_CMD_VMAPI 0x2B +#define GITS_CMD_VINVALL 0x2D /* MAPC command fields */ #define ICID_LENGTH 16 @@ -411,6 +412,9 @@ FIELD(VMOVI_1, VPEID, 32, 16) FIELD(VMOVI_2, D, 0, 1) FIELD(VMOVI_2, DOORBELL, 32, 32) +/* VINVALL command fields */ +FIELD(VINVALL_1, VPEID, 32, 16) + /* * 12 bytes Interrupt translation Table Entry size * as per Table 5.3 in GICv3 spec @@ -637,6 +641,15 @@ void gicv3_redist_movall_lpis(GICv3CPUState *src, GICv3CPUState *dest); void gicv3_redist_mov_vlpi(GICv3CPUState *src, uint64_t src_vptaddr, GICv3CPUState *dest, uint64_t dest_vptaddr, int irq, int doorbell); +/** + * gicv3_redist_vinvall: + * @cs: GICv3CPUState + * @vptaddr: address of VLPI pending table + * + * On redistributor @cs, invalidate all cached information associated + * with the vCPU defined by @vptaddr. + */ +void gicv3_redist_vinvall(GICv3CPUState *cs, uint64_t vptaddr); void gicv3_redist_send_sgi(GICv3CPUState *cs, int grp, int irq, bool ns); void gicv3_init_cpuif(GICv3State *s); diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index aef024009b2..6c44cccd369 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -1163,6 +1163,29 @@ static ItsCmdResult process_vmovi(GICv3ITSState *s, const uint64_t *cmdpkt) return update_ite(s, eventid, &dte, &ite) ? CMD_CONTINUE_OK : CMD_STALL; } +static ItsCmdResult process_vinvall(GICv3ITSState *s, const uint64_t *cmdpkt) +{ + VTEntry vte; + uint32_t vpeid; + ItsCmdResult cmdres; + + if (!its_feature_virtual(s)) { + return CMD_CONTINUE; + } + + vpeid = FIELD_EX64(cmdpkt[1], VINVALL_1, VPEID); + + trace_gicv3_its_cmd_vinvall(vpeid); + + cmdres = lookup_vte(s, __func__, vpeid, &vte); + if (cmdres != CMD_CONTINUE_OK) { + return cmdres; + } + + gicv3_redist_vinvall(&s->gicv3->cpu[vte.rdbase], vte.vptaddr << 16); + return CMD_CONTINUE_OK; +} + static ItsCmdResult process_inv(GICv3ITSState *s, const uint64_t *cmdpkt) { uint32_t devid, eventid; @@ -1364,6 +1387,9 @@ static void process_cmdq(GICv3ITSState *s) case GITS_CMD_VMOVI: result = process_vmovi(s, cmdpkt); break; + case GITS_CMD_VINVALL: + result = process_vinvall(s, cmdpkt); + break; default: trace_gicv3_its_cmd_unknown(cmd); break; diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index dc25997d1f9..7c75dd6f072 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -818,6 +818,11 @@ void gicv3_redist_mov_vlpi(GICv3CPUState *src, uint64_t src_vptaddr, */ } +void gicv3_redist_vinvall(GICv3CPUState *cs, uint64_t vptaddr) +{ + /* The redistributor handling will be added in a subsequent commit */ +} + void gicv3_redist_inv_vlpi(GICv3CPUState *cs, int irq, uint64_t vptaddr) { /* diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 9894756e55a..004a1006fb8 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -194,6 +194,7 @@ gicv3_its_cmd_vmapp(uint32_t vpeid, uint64_t rdbase, int valid, uint64_t vptaddr gicv3_its_cmd_vmovp(uint32_t vpeid, uint64_t rdbase) "GICv3 ITS: command VMOVP vPEID 0x%x RDbase 0x%" PRIx64 gicv3_its_cmd_vsync(void) "GICv3 ITS: command VSYNC" gicv3_its_cmd_vmovi(uint32_t devid, uint32_t eventid, uint32_t vpeid, int dbvalid, uint32_t doorbell) "GICv3 ITS: command VMOVI DeviceID 0x%x EventID 0x%x vPEID 0x%x D %d Dbell_pINTID 0x%x" +gicv3_its_cmd_vinvall(uint32_t vpeid) "GICv3 ITS: command VINVALL vPEID 0x%x" gicv3_its_cmd_unknown(unsigned cmd) "GICv3 ITS: unknown command 0x%x" gicv3_its_cte_read(uint32_t icid, int valid, uint32_t rdbase) "GICv3 ITS: Collection Table read for ICID 0x%x: valid %d RDBase 0x%x" gicv3_its_cte_write(uint32_t icid, int valid, uint32_t rdbase) "GICv3 ITS: Collection Table write for ICID 0x%x: valid %d RDBase 0x%x" From patchwork Fri Apr 8 14:15:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558831 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp381051map; Fri, 8 Apr 2022 07:38:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzVwb+1oTmP8D5YH9AtNGEMYQ4louq5nTdYwoYmTTPxxEVtq/qtXys67ITqKOoTsr32memk X-Received: by 2002:a25:4013:0:b0:63d:b15b:f468 with SMTP id n19-20020a254013000000b0063db15bf468mr14670236yba.636.1649428731347; Fri, 08 Apr 2022 07:38:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649428731; cv=none; d=google.com; s=arc-20160816; b=HbAJ8qPjHLa6YtAT4x3XutS6nfjhaEOpopKCIsg5/pakmZshh5M8XirDP3UB3y9/7p QfNEyF/2K8aX0Zeg//2Qp93x1nJOR/zpSz7zXx+t02AQGNnC/IjnBZ1NLaA277UTS5L3 7nNqFWWV3gVgbmy7NAQ1U5xMiZR8PdwrkB4P0xYdGBhxzqWbQ5hB4RHLHeI/lmvoZaOk ZJm55xllLxErEpm+gwhzzFqk050Pr1iFPO9Y4ejY+vZMk3DyDaSpioZSu9khYVz7mONr Aa2pPn7HbQ41CQVYF3Ny2TYcodlORapdwUSOYmUsY/jedPogt4h5ShRQS5k2/iYVBDnW uITA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4X5gt1qh1B1TGFcyO7ZbfSY/eEx5BCkyPS7Ts12JMq0=; b=D9S4wO7hHHRAFj8Qb6pCSQgfHxhvKZ6dQTNqgwt9XUisxaZb4CytHm25qDsT54loMV UubkfgoVu7r1dzufRxbce5JYyNMNYY9nCaqZ2CtP7kVk3eybhJvA2bokeOQXfXC5wiAX ZW08YmUM1o2qn5Bi3cRB5ieWgO3npKk5O0ZvPm4lr4y6mLjDfFuuWAzjaVxq8WbVoO+0 ul1vWdvTk6MHo4BdVOr5Jcx3m93t09wRJup7f45O1oke0ykL/zxCvKknSKVvyvqz56hx QVIQ+6j10PcXOSt3BIPASgucosTgDtmGXlZSFKoK9188cJdI+Tc1boAePKU7R0zAdrMC DmiA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jOXXMYgP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:13 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 22/41] hw/intc/arm_gicv3: Implement GICv4's new redistributor frame Date: Fri, 8 Apr 2022 15:15:31 +0100 Message-Id: <20220408141550.1271295-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The GICv4 extends the redistributor register map -- where GICv3 had two 64KB frames per CPU, GICv4 has four frames. Add support for the extra frame by using a new gicv3_redist_size() function in the places in the GIC implementation which currently use a fixed constant size for the redistributor register block. (Until we implement the extra registers they will RAZ/WI.) Any board that wants to use a GICv4 will need to also adjust to handle the different sized redistributor register block; that will be done separately. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/gicv3_internal.h | 21 +++++++++++++++++++++ include/hw/intc/arm_gicv3_common.h | 5 +++++ hw/intc/arm_gicv3_common.c | 2 +- hw/intc/arm_gicv3_redist.c | 8 ++++---- 4 files changed, 31 insertions(+), 5 deletions(-) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 8d58d38836f..9720ccf7507 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -489,6 +489,27 @@ FIELD(VTE, RDBASE, 42, RDBASE_PROCNUM_LENGTH) /* Functions internal to the emulated GICv3 */ +/** + * gicv3_redist_size: + * @s: GICv3State + * + * Return the size of the redistributor register frame in bytes + * (which depends on what GIC version this is) + */ +static inline int gicv3_redist_size(GICv3State *s) +{ + /* + * Redistributor size is controlled by the redistributor GICR_TYPER.VLPIS. + * It's the same for every redistributor in the GIC, so arbitrarily + * use the register field in the first one. + */ + if (s->cpu[0].gicr_typer & GICR_TYPER_VLPIS) { + return GICV4_REDIST_SIZE; + } else { + return GICV3_REDIST_SIZE; + } +} + /** * gicv3_intid_is_special: * @intid: interrupt ID diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h index 08b27789385..40bc404a652 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -38,7 +38,12 @@ #define GICV3_LPI_INTID_START 8192 +/* + * The redistributor in GICv3 has two 64KB frames per CPU; in + * GICv4 it has four 64KB frames per CPU. + */ #define GICV3_REDIST_SIZE 0x20000 +#define GICV4_REDIST_SIZE 0x40000 /* Number of SGI target-list bits */ #define GICV3_TARGETLIST_BITS 16 diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index dcc5ce28c6a..18999e3c8bb 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -295,7 +295,7 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler, memory_region_init_io(®ion->iomem, OBJECT(s), ops ? &ops[1] : NULL, region, name, - s->redist_region_count[i] * GICV3_REDIST_SIZE); + s->redist_region_count[i] * gicv3_redist_size(s)); sysbus_init_mmio(sbd, ®ion->iomem); g_free(name); } diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 7c75dd6f072..9f1fe09a78e 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -442,8 +442,8 @@ MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data, * in the memory map); if so then the GIC has multiple MemoryRegions * for the redistributors. */ - cpuidx = region->cpuidx + offset / GICV3_REDIST_SIZE; - offset %= GICV3_REDIST_SIZE; + cpuidx = region->cpuidx + offset / gicv3_redist_size(s); + offset %= gicv3_redist_size(s); cs = &s->cpu[cpuidx]; @@ -501,8 +501,8 @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data, * in the memory map); if so then the GIC has multiple MemoryRegions * for the redistributors. */ - cpuidx = region->cpuidx + offset / GICV3_REDIST_SIZE; - offset %= GICV3_REDIST_SIZE; + cpuidx = region->cpuidx + offset / gicv3_redist_size(s); + offset %= gicv3_redist_size(s); cs = &s->cpu[cpuidx]; From patchwork Fri Apr 8 14:15:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558820 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp372734map; Fri, 8 Apr 2022 07:29:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyHgeSFa+z7u24VXeBosU/zy6WZZWjgJCQ9199WoCGgmIJNg2rNhatrZ/wCoxIbdWKHLOb8 X-Received: by 2002:a0d:c906:0:b0:2e7:f90b:5a4e with SMTP id l6-20020a0dc906000000b002e7f90b5a4emr16218402ywd.51.1649428144726; Fri, 08 Apr 2022 07:29:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649428144; cv=none; d=google.com; s=arc-20160816; b=t+Z+NTd/BosKVtlhsjtAp52uHGvuWM8gi7uHkiL+uH//uXUOQpVFBY5k+NfRasDhHi o8i27xtPIkBlslc8lZ35QDk+bzYgAGAivcufdOEp9ws4/OQ2kivqEK4UTQoioB+ROAKu YCtCbMuDyzbBainPRtN5qJw+LtmN7P9pwOxgjXSf4jRh3Q+HxFMECtImRr4AGi5rJlxb kK0kHaOaTFLsdigymFfZpumcbOTPcs3s3+8cuyxg4etog+VL3LPZJ5NA4iB2AGj1WqXv rMe6tvkVui1LbMpZJHQO1Fc872B6hP9RDdCgMOgWKBst7zA/FWOE/I99pITf4w8YtRSW RbjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=RUqo09ErOg1M6skc6e7vosGnWtwA6stMdKCkU3VyoI4=; b=UgOlrPZGh7+Pvwd+R5s/20t4JurzTtJWspoSc9ThiKt3UmAY0fLzhlRF5Ae8GlJk+z Ml6JAlv4rhOWvhKxQ+7rU+/LB+7SE0M7esDidQvk9x3nMbsF0OxrgJ2vNgCS+NR8CIm+ gUD8MZwsAeYw8v6zd8rdS79i7LzBQWDjhb8aRUVs3fR1aZPznyuvbe4Pe6txR+h2Jk94 yWwRD7cL7/fDRmfmt2SGkNTZT86mMT2X1YktnMSVsYBOYWA6t0UJw4jhusaUgt5meHKG 3nBW2MU5Ge0KXtbOSCAJmyV1YnJZ7b5dQ8Dz+MCaGV+KYsWF6PKTydcvTm/FwQFZeMe7 o0rw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pLVIREd6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:14 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 23/41] hw/intc/arm_gicv3: Implement new GICv4 redistributor registers Date: Fri, 8 Apr 2022 15:15:32 +0100 Message-Id: <20220408141550.1271295-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Implement the new GICv4 redistributor registers: GICR_VPROPBASER and GICR_VPENDBASER; for the moment we implement these as simple reads-as-written stubs, together with the necessary migration and reset handling. We don't put ID-register checks on the handling of these registers, because they are all in the only-in-v4 extra register frames, so they're not accessible in a GICv3. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- GICv4.1 adds two further registers in the new VLPI frame, as well as changing the layout of VPROPBASER and VPENDBASER, but we aren't implementing v4.1 yet, just v4. --- hw/intc/gicv3_internal.h | 21 +++++++++++ include/hw/intc/arm_gicv3_common.h | 3 ++ hw/intc/arm_gicv3_common.c | 22 ++++++++++++ hw/intc/arm_gicv3_redist.c | 56 ++++++++++++++++++++++++++++++ 4 files changed, 102 insertions(+) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 9720ccf7507..795bf57d2b3 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -77,6 +77,7 @@ * Redistributor frame offsets from RD_base */ #define GICR_SGI_OFFSET 0x10000 +#define GICR_VLPI_OFFSET 0x20000 /* * Redistributor registers, offsets from RD_base @@ -109,6 +110,10 @@ #define GICR_IGRPMODR0 (GICR_SGI_OFFSET + 0x0D00) #define GICR_NSACR (GICR_SGI_OFFSET + 0x0E00) +/* VLPI redistributor registers, offsets from VLPI_base */ +#define GICR_VPROPBASER (GICR_VLPI_OFFSET + 0x70) +#define GICR_VPENDBASER (GICR_VLPI_OFFSET + 0x78) + #define GICR_CTLR_ENABLE_LPIS (1U << 0) #define GICR_CTLR_CES (1U << 1) #define GICR_CTLR_RWP (1U << 3) @@ -143,6 +148,22 @@ FIELD(GICR_PENDBASER, PTZ, 62, 1) #define GICR_PROPBASER_IDBITS_THRESHOLD 0xd +/* These are the GICv4 VPROPBASER and VPENDBASER layouts; v4.1 is different */ +FIELD(GICR_VPROPBASER, IDBITS, 0, 5) +FIELD(GICR_VPROPBASER, INNERCACHE, 7, 3) +FIELD(GICR_VPROPBASER, SHAREABILITY, 10, 2) +FIELD(GICR_VPROPBASER, PHYADDR, 12, 40) +FIELD(GICR_VPROPBASER, OUTERCACHE, 56, 3) + +FIELD(GICR_VPENDBASER, INNERCACHE, 7, 3) +FIELD(GICR_VPENDBASER, SHAREABILITY, 10, 2) +FIELD(GICR_VPENDBASER, PHYADDR, 16, 36) +FIELD(GICR_VPENDBASER, OUTERCACHE, 56, 3) +FIELD(GICR_VPENDBASER, DIRTY, 60, 1) +FIELD(GICR_VPENDBASER, PENDINGLAST, 61, 1) +FIELD(GICR_VPENDBASER, IDAI, 62, 1) +FIELD(GICR_VPENDBASER, VALID, 63, 1) + #define ICC_CTLR_EL1_CBPR (1U << 0) #define ICC_CTLR_EL1_EOIMODE (1U << 1) #define ICC_CTLR_EL1_PMHE (1U << 6) diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h index 40bc404a652..7ff5a1aa5fc 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -179,6 +179,9 @@ struct GICv3CPUState { uint32_t gicr_igrpmodr0; uint32_t gicr_nsacr; uint8_t gicr_ipriorityr[GIC_INTERNAL]; + /* VLPI_base page registers */ + uint64_t gicr_vpropbaser; + uint64_t gicr_vpendbaser; /* CPU interface */ uint64_t icc_sre_el1; diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 18999e3c8bb..14d76d74840 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -144,6 +144,25 @@ const VMStateDescription vmstate_gicv3_cpu_sre_el1 = { } }; +static bool gicv4_needed(void *opaque) +{ + GICv3CPUState *cs = opaque; + + return cs->gic->revision > 3; +} + +const VMStateDescription vmstate_gicv3_gicv4 = { + .name = "arm_gicv3_cpu/gicv4", + .version_id = 1, + .minimum_version_id = 1, + .needed = gicv4_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT64(gicr_vpropbaser, GICv3CPUState), + VMSTATE_UINT64(gicr_vpendbaser, GICv3CPUState), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_gicv3_cpu = { .name = "arm_gicv3_cpu", .version_id = 1, @@ -175,6 +194,7 @@ static const VMStateDescription vmstate_gicv3_cpu = { .subsections = (const VMStateDescription * []) { &vmstate_gicv3_cpu_virt, &vmstate_gicv3_cpu_sre_el1, + &vmstate_gicv3_gicv4, NULL } }; @@ -444,6 +464,8 @@ static void arm_gicv3_common_reset(DeviceState *dev) cs->gicr_waker = GICR_WAKER_ProcessorSleep | GICR_WAKER_ChildrenAsleep; cs->gicr_propbaser = 0; cs->gicr_pendbaser = 0; + cs->gicr_vpropbaser = 0; + cs->gicr_vpendbaser = 0; /* If we're resetting a TZ-aware GIC as if secure firmware * had set it up ready to start a kernel in non-secure, we * need to set interrupts to group 1 so the kernel can use them. diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 9f1fe09a78e..c310d7f8ff2 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -236,6 +236,23 @@ static MemTxResult gicr_readl(GICv3CPUState *cs, hwaddr offset, case GICR_IDREGS ... GICR_IDREGS + 0x2f: *data = gicv3_idreg(offset - GICR_IDREGS, GICV3_PIDR0_REDIST); return MEMTX_OK; + /* + * VLPI frame registers. We don't need a version check for + * VPROPBASER and VPENDBASER because gicv3_redist_size() will + * prevent pre-v4 GIC from passing us offsets this high. + */ + case GICR_VPROPBASER: + *data = extract64(cs->gicr_vpropbaser, 0, 32); + return MEMTX_OK; + case GICR_VPROPBASER + 4: + *data = extract64(cs->gicr_vpropbaser, 32, 32); + return MEMTX_OK; + case GICR_VPENDBASER: + *data = extract64(cs->gicr_vpendbaser, 0, 32); + return MEMTX_OK; + case GICR_VPENDBASER + 4: + *data = extract64(cs->gicr_vpendbaser, 32, 32); + return MEMTX_OK; default: return MEMTX_ERROR; } @@ -379,6 +396,23 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset, "%s: invalid guest write to RO register at offset " TARGET_FMT_plx "\n", __func__, offset); return MEMTX_OK; + /* + * VLPI frame registers. We don't need a version check for + * VPROPBASER and VPENDBASER because gicv3_redist_size() will + * prevent pre-v4 GIC from passing us offsets this high. + */ + case GICR_VPROPBASER: + cs->gicr_vpropbaser = deposit64(cs->gicr_vpropbaser, 0, 32, value); + return MEMTX_OK; + case GICR_VPROPBASER + 4: + cs->gicr_vpropbaser = deposit64(cs->gicr_vpropbaser, 32, 32, value); + return MEMTX_OK; + case GICR_VPENDBASER: + cs->gicr_vpendbaser = deposit64(cs->gicr_vpendbaser, 0, 32, value); + return MEMTX_OK; + case GICR_VPENDBASER + 4: + cs->gicr_vpendbaser = deposit64(cs->gicr_vpendbaser, 32, 32, value); + return MEMTX_OK; default: return MEMTX_ERROR; } @@ -397,6 +431,17 @@ static MemTxResult gicr_readll(GICv3CPUState *cs, hwaddr offset, case GICR_PENDBASER: *data = cs->gicr_pendbaser; return MEMTX_OK; + /* + * VLPI frame registers. We don't need a version check for + * VPROPBASER and VPENDBASER because gicv3_redist_size() will + * prevent pre-v4 GIC from passing us offsets this high. + */ + case GICR_VPROPBASER: + *data = cs->gicr_vpropbaser; + return MEMTX_OK; + case GICR_VPENDBASER: + *data = cs->gicr_vpendbaser; + return MEMTX_OK; default: return MEMTX_ERROR; } @@ -418,6 +463,17 @@ static MemTxResult gicr_writell(GICv3CPUState *cs, hwaddr offset, "%s: invalid guest write to RO register at offset " TARGET_FMT_plx "\n", __func__, offset); return MEMTX_OK; + /* + * VLPI frame registers. We don't need a version check for + * VPROPBASER and VPENDBASER because gicv3_redist_size() will + * prevent pre-v4 GIC from passing us offsets this high. + */ + case GICR_VPROPBASER: + cs->gicr_vpropbaser = value; + return MEMTX_OK; + case GICR_VPENDBASER: + cs->gicr_vpendbaser = value; + return MEMTX_OK; default: return MEMTX_ERROR; } From patchwork Fri Apr 8 14:15:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558833 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp382446map; Fri, 8 Apr 2022 07:40:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyZCWIIPi4JqlSquoviLSWxbobpFkSw5/llKAZOhPmcxUtXfYBdiFj/9ePl0DwA7JHxR29A X-Received: by 2002:a5b:ac1:0:b0:63d:9fd4:ebf4 with SMTP id a1-20020a5b0ac1000000b0063d9fd4ebf4mr13578014ybr.648.1649428836258; Fri, 08 Apr 2022 07:40:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649428836; cv=none; d=google.com; s=arc-20160816; b=0oAWks20Ht1OmtG9iPstMBWvafWpDnpUM1F15p0mGdyMO+icld40HgNaKbSvdMAnIA RihuMqtvOx82J02aYheYbllPOQKnyRFfe7RkFtpjfFwno5BNZtQmjItheepzY0fd3//5 cJFt5DbnJ74qE9oOA+Mz9UbfiWPgPtJpU7qrNy7b1OYp36py/6ekJRdo7gyMMCbDvzK0 V363bqpbWye5fPcm0k6X0ldFSaOMAQ0UxtyXbtQIJ28xBo80tXkoTprQW9d5OQ9Qvseo 5rAjLtsUuxL888j3Y9CqmwRyxqv0W6WJ+5oQWEAwf/ajy6mZ5WnhmBtFnv7m4u4L3DqB Wvxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+91rGjHM43jV+u2RiWuTQSi49T2BNr1THBEc0q/ZCAY=; b=EcanxLN5YGhCfXnHYxlkd55Rt2BGO3yLmLWFWHFmYdA9tX5Lv1uEzrKUK8R/8EOglf TO74Ig9CMJJ994XG2jNy6L1f+R+Tp4kbx0vZyCr5tYQZjqS7uE556uvCI0E99hBWSH0i En8iHd3a7wCcILibnP/PTAh+qtqnMiiSBXoHP18WYtj7sXh6DyRG3PjmjeBhdL78zddy dHBaNY94JjHwTfO00VqFLJC2rMCus8jgC+Da2QeA6IviY+/AJf8ct58jr7LjEVpyWaNi ILHFflG+dhjm7sQHXVGjXwamvW8Z9kRwxGU4ZghdbwX7iGa1xHGIJ29Azv5P37nMV+fs KtQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IVK5GFre; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:15 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 24/41] hw/intc/arm_gicv3_cpuif: Split "update vIRQ/vFIQ" from gicv3_cpuif_virt_update() Date: Fri, 8 Apr 2022 15:15:33 +0100 Message-Id: <20220408141550.1271295-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The function gicv3_cpuif_virt_update() currently sets all of vIRQ, vFIQ and the maintenance interrupt. This implies that it has to be used quite carefully -- as the comment notes, setting the maintenance interrupt will typically cause the GIC code to be re-entered recursively. For handling vLPIs, we need the redistributor to be able to tell the cpuif to update the vIRQ and vFIQ lines when the highest priority pending vLPI changes. Since that change can't cause the maintenance interrupt state to change, we can pull the "update vIRQ/vFIQ" parts of gicv3_cpuif_virt_update() out into a separate function, which the redistributor can then call without having to worry about the reentrancy issue. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/gicv3_internal.h | 11 +++++++ hw/intc/arm_gicv3_cpuif.c | 64 ++++++++++++++++++++++++--------------- hw/intc/trace-events | 3 +- 3 files changed, 53 insertions(+), 25 deletions(-) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 795bf57d2b3..f25ddeca579 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -707,6 +707,17 @@ void gicv3_init_cpuif(GICv3State *s); */ void gicv3_cpuif_update(GICv3CPUState *cs); +/* + * gicv3_cpuif_virt_irq_fiq_update: + * @cs: GICv3CPUState for the CPU to update + * + * Recalculate whether to assert the virtual IRQ or FIQ lines after + * a change to the current highest priority pending virtual interrupt. + * Note that this does not recalculate and change the maintenance + * interrupt status (for that, see gicv3_cpuif_virt_update()). + */ +void gicv3_cpuif_virt_irq_fiq_update(GICv3CPUState *cs); + static inline uint32_t gicv3_iidr(void) { /* Return the Implementer Identification Register value diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 1a3d440a54b..5fb64d4663c 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -370,30 +370,20 @@ static uint32_t maintenance_interrupt_state(GICv3CPUState *cs) return value; } -static void gicv3_cpuif_virt_update(GICv3CPUState *cs) +void gicv3_cpuif_virt_irq_fiq_update(GICv3CPUState *cs) { - /* Tell the CPU about any pending virtual interrupts or - * maintenance interrupts, following a change to the state - * of the CPU interface relevant to virtual interrupts. - * - * CAUTION: this function will call qemu_set_irq() on the - * CPU maintenance IRQ line, which is typically wired up - * to the GIC as a per-CPU interrupt. This means that it - * will recursively call back into the GIC code via - * gicv3_redist_set_irq() and thus into the CPU interface code's - * gicv3_cpuif_update(). It is therefore important that this - * function is only called as the final action of a CPU interface - * register write implementation, after all the GIC state - * fields have been updated. gicv3_cpuif_update() also must - * not cause this function to be called, but that happens - * naturally as a result of there being no architectural - * linkage between the physical and virtual GIC logic. + /* + * Tell the CPU about any pending virtual interrupts. + * This should only be called for changes that affect the + * vIRQ and vFIQ status and do not change the maintenance + * interrupt status. This means that unlike gicv3_cpuif_virt_update() + * this function won't recursively call back into the GIC code. + * The main use of this is when the redistributor has changed the + * highest priority pending virtual LPI. */ int idx; int irqlevel = 0; int fiqlevel = 0; - int maintlevel = 0; - ARMCPU *cpu = ARM_CPU(cs->cpu); idx = hppvi_index(cs); trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs), idx); @@ -410,16 +400,42 @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs) } } + trace_gicv3_cpuif_virt_set_irqs(gicv3_redist_affid(cs), fiqlevel, irqlevel); + qemu_set_irq(cs->parent_vfiq, fiqlevel); + qemu_set_irq(cs->parent_virq, irqlevel); +} + +static void gicv3_cpuif_virt_update(GICv3CPUState *cs) +{ + /* + * Tell the CPU about any pending virtual interrupts or + * maintenance interrupts, following a change to the state + * of the CPU interface relevant to virtual interrupts. + * + * CAUTION: this function will call qemu_set_irq() on the + * CPU maintenance IRQ line, which is typically wired up + * to the GIC as a per-CPU interrupt. This means that it + * will recursively call back into the GIC code via + * gicv3_redist_set_irq() and thus into the CPU interface code's + * gicv3_cpuif_update(). It is therefore important that this + * function is only called as the final action of a CPU interface + * register write implementation, after all the GIC state + * fields have been updated. gicv3_cpuif_update() also must + * not cause this function to be called, but that happens + * naturally as a result of there being no architectural + * linkage between the physical and virtual GIC logic. + */ + ARMCPU *cpu = ARM_CPU(cs->cpu); + int maintlevel = 0; + + gicv3_cpuif_virt_irq_fiq_update(cs); + if ((cs->ich_hcr_el2 & ICH_HCR_EL2_EN) && maintenance_interrupt_state(cs) != 0) { maintlevel = 1; } - trace_gicv3_cpuif_virt_set_irqs(gicv3_redist_affid(cs), fiqlevel, - irqlevel, maintlevel); - - qemu_set_irq(cs->parent_vfiq, fiqlevel); - qemu_set_irq(cs->parent_virq, irqlevel); + trace_gicv3_cpuif_virt_set_maint_irq(gicv3_redist_affid(cs), maintlevel); qemu_set_irq(cpu->gicv3_maintenance_interrupt, maintlevel); } diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 004a1006fb8..36c3fe4da0b 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -152,7 +152,8 @@ gicv3_icv_dir_write(uint32_t cpu, uint64_t val) "GICv3 ICV_DIR write cpu 0x%x va gicv3_icv_iar_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_IAR%d read cpu 0x%x value 0x%" PRIx64 gicv3_icv_eoir_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_EOIR%d write cpu 0x%x value 0x%" PRIx64 gicv3_cpuif_virt_update(uint32_t cpuid, int idx) "GICv3 CPU i/f 0x%x virt HPPI update LR index %d" -gicv3_cpuif_virt_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel, int maintlevel) "GICv3 CPU i/f 0x%x virt HPPI update: setting FIQ %d IRQ %d maintenance-irq %d" +gicv3_cpuif_virt_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel) "GICv3 CPU i/f 0x%x virt HPPI update: setting FIQ %d IRQ %d" +gicv3_cpuif_virt_set_maint_irq(uint32_t cpuid, int maintlevel) "GICv3 CPU i/f 0x%x virt HPPI update: setting maintenance-irq %d" # arm_gicv3_dist.c gicv3_dist_read(uint64_t offset, uint64_t data, unsigned size, bool secure) "GICv3 distributor read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" From patchwork Fri Apr 8 14:15:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558824 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp376325map; Fri, 8 Apr 2022 07:33:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzWgRGU6KSXfGyCPSrOzDM2e/IO4+faTZ3Fu5k6CAHbgaZRMdXJBP3oEADdnKU4hiQTUpIn X-Received: by 2002:a25:9e8d:0:b0:63e:6dd5:a08c with SMTP id p13-20020a259e8d000000b0063e6dd5a08cmr5341993ybq.105.1649428383478; Fri, 08 Apr 2022 07:33:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649428383; cv=none; d=google.com; s=arc-20160816; b=EYT4GJWtj6vkt/Clnr307YDJufmdad4Mvkh6252jdXcV/yuMrMDhyN5fY+NmZ/gLbF ezpfiK0/C0U1JE9xSo8xirP3yUyVzKKRg7UuGzGeEMYRfh5J6PQxu3RZosBZgBUCW6P4 gHMJkQEuidzHqVP54F4P+zokhM1IjZZWie1fwOGo3+JAPwxYExMTSUkv1U3ykHa55fVa uRzZdnxx8brNgxt9u50EqCMb/V6vFDG6KjLz4RdVqF2hgM/ZwTBizjzqB7xo6hHcSR8/ TW7FDWXYHhmgDByax2YXwpvKtMNtN9M5sui9ati4JLjo6NEOyPICny5Z734pphNyODhA rR/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=7FBcibg4X/BLH2Q3G0Mri1MqJFY48xt240Kc+XhivMw=; b=ihYUD1hmk4HbOa9vT3VN7mT99KlXOH106X0FDtzam8y2DkumnYCqTKuzRbmZ1IKDT0 BJtxSyx1V2TwTD0h26PuHKl7RagcaNNgzvtiip8MFnvBVd1qVIZRPJ3U/KGKXcCusKLL dLnjwyaQsteIACHoVfzhElWJk9ehZ41ET5dZ+9JdxYaViyKB9xGP0TLRIfVQZGF6dkFb EWg3bndGr6XPqu8PqIU+FBOmQJ5pz5pvU1A62emGXnsRKWBvKnTJoAHOl37gGseKFv5m 6x/oq3/WDVcSekJtLVOsZisSMsGzOFYG6Rv6KnfdN/X/G0FP7KzXKFPAy2myeVtj1Vre dvjw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DyRGq6hv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:16 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 25/41] hw/intc/arm_gicv3_cpuif: Support vLPIs Date: Fri, 8 Apr 2022 15:15:34 +0100 Message-Id: <20220408141550.1271295-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The CPU interface changes to support vLPIs are fairly minor: in the parts of the code that currently look at the list registers to determine the highest priority pending virtual interrupt, we must also look at the highest priority pending vLPI. To do this we change hppvi_index() to check the vLPI and return a special-case value if that is the right virtual interrupt to take. The callsites (which handle HPPIR and IAR registers and the "raise vIRQ and vFIQ lines" code) then have to handle this special-case value. This commit includes two interfaces with the as-yet-unwritten redistributor code: * the new GICv3CPUState::hppvlpi will be set by the redistributor (in the same way as the existing hpplpi does for physical LPIs) * when the CPU interface acknowledges a vLPI it needs to set it to non-pending; the new gicv3_redist_vlpi_pending() function (which matches the existing gicv3_redist_lpi_pending() used for physical LPIs) is a stub that will be filled in later Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/gicv3_internal.h | 13 ++++ include/hw/intc/arm_gicv3_common.h | 3 + hw/intc/arm_gicv3_common.c | 1 + hw/intc/arm_gicv3_cpuif.c | 119 +++++++++++++++++++++++++++-- hw/intc/arm_gicv3_redist.c | 8 ++ hw/intc/trace-events | 2 +- 6 files changed, 140 insertions(+), 6 deletions(-) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index f25ddeca579..07644b2be6f 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -612,6 +612,19 @@ void gicv3_redist_process_lpi(GICv3CPUState *cs, int irq, int level); */ void gicv3_redist_process_vlpi(GICv3CPUState *cs, int irq, uint64_t vptaddr, int doorbell, int level); +/** + * gicv3_redist_vlpi_pending: + * @cs: GICv3CPUState + * @irq: (virtual) interrupt number + * @level: level to set @irq to + * + * Set/clear the pending status of a virtual LPI in the vLPI table + * that this redistributor is currently using. (The difference between + * this and gicv3_redist_process_vlpi() is that this is called from + * the cpuif and does not need to do the not-running-on-this-vcpu checks.) + */ +void gicv3_redist_vlpi_pending(GICv3CPUState *cs, int irq, int level); + void gicv3_redist_lpi_pending(GICv3CPUState *cs, int irq, int level); /** * gicv3_redist_update_lpi: diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h index 7ff5a1aa5fc..4e416100559 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -219,6 +219,9 @@ struct GICv3CPUState { */ PendingIrq hpplpi; + /* Cached information recalculated from vLPI tables in guest memory */ + PendingIrq hppvlpi; + /* This is temporary working state, to avoid a malloc in gicv3_update() */ bool seenbetter; }; diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 14d76d74840..3f47b3501fe 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -487,6 +487,7 @@ static void arm_gicv3_common_reset(DeviceState *dev) cs->hppi.prio = 0xff; cs->hpplpi.prio = 0xff; + cs->hppvlpi.prio = 0xff; /* State in the CPU interface must *not* be reset here, because it * is part of the CPU's reset domain, not the GIC device's. diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 5fb64d4663c..f11863ff613 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -21,6 +21,12 @@ #include "hw/irq.h" #include "cpu.h" +/* + * Special case return value from hppvi_index(); must be larger than + * the architecturally maximum possible list register index (which is 15) + */ +#define HPPVI_INDEX_VLPI 16 + static GICv3CPUState *icc_cs_from_env(CPUARMState *env) { return env->gicv3state; @@ -157,10 +163,18 @@ static int ich_highest_active_virt_prio(GICv3CPUState *cs) static int hppvi_index(GICv3CPUState *cs) { - /* Return the list register index of the highest priority pending + /* + * Return the list register index of the highest priority pending * virtual interrupt, as per the HighestPriorityVirtualInterrupt * pseudocode. If no pending virtual interrupts, return -1. + * If the highest priority pending virtual interrupt is a vLPI, + * return HPPVI_INDEX_VLPI. + * (The pseudocode handles checking whether the vLPI is higher + * priority than the highest priority list register at every + * callsite of HighestPriorityVirtualInterrupt; we check it here.) */ + ARMCPU *cpu = ARM_CPU(cs->cpu); + CPUARMState *env = &cpu->env; int idx = -1; int i; /* Note that a list register entry with a priority of 0xff will @@ -202,6 +216,23 @@ static int hppvi_index(GICv3CPUState *cs) } } + /* + * "no pending vLPI" is indicated with prio = 0xff, which always + * fails the priority check here. vLPIs are only considered + * when we are in Non-Secure state. + */ + if (cs->hppvlpi.prio < prio && !arm_is_secure(env)) { + if (cs->hppvlpi.grp == GICV3_G0) { + if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG0) { + return HPPVI_INDEX_VLPI; + } + } else { + if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1) { + return HPPVI_INDEX_VLPI; + } + } + } + return idx; } @@ -289,6 +320,47 @@ static bool icv_hppi_can_preempt(GICv3CPUState *cs, uint64_t lr) return false; } +static bool icv_hppvlpi_can_preempt(GICv3CPUState *cs) +{ + /* + * Return true if we can signal the highest priority pending vLPI. + * We can assume we're Non-secure because hppvi_index() already + * tested for that. + */ + uint32_t mask, rprio, vpmr; + + if (!(cs->ich_hcr_el2 & ICH_HCR_EL2_EN)) { + /* Virtual interface disabled */ + return false; + } + + vpmr = extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT, + ICH_VMCR_EL2_VPMR_LENGTH); + + if (cs->hppvlpi.prio >= vpmr) { + /* Priority mask masks this interrupt */ + return false; + } + + rprio = ich_highest_active_virt_prio(cs); + if (rprio == 0xff) { + /* No running interrupt so we can preempt */ + return true; + } + + mask = icv_gprio_mask(cs, cs->hppvlpi.grp); + + /* + * We only preempt a running interrupt if the pending interrupt's + * group priority is sufficient (the subpriorities are not considered). + */ + if ((cs->hppvlpi.prio & mask) < (rprio & mask)) { + return true; + } + + return false; +} + static uint32_t eoi_maintenance_interrupt_state(GICv3CPUState *cs, uint32_t *misr) { @@ -386,8 +458,18 @@ void gicv3_cpuif_virt_irq_fiq_update(GICv3CPUState *cs) int fiqlevel = 0; idx = hppvi_index(cs); - trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs), idx); - if (idx >= 0) { + trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs), idx, + cs->hppvlpi.irq, cs->hppvlpi.grp, + cs->hppvlpi.prio); + if (idx == HPPVI_INDEX_VLPI) { + if (icv_hppvlpi_can_preempt(cs)) { + if (cs->hppvlpi.grp == GICV3_G0) { + fiqlevel = 1; + } else { + irqlevel = 1; + } + } + } else if (idx >= 0) { uint64_t lr = cs->ich_lr_el2[idx]; if (icv_hppi_can_preempt(cs, lr)) { @@ -619,7 +701,11 @@ static uint64_t icv_hppir_read(CPUARMState *env, const ARMCPRegInfo *ri) int idx = hppvi_index(cs); uint64_t value = INTID_SPURIOUS; - if (idx >= 0) { + if (idx == HPPVI_INDEX_VLPI) { + if (cs->hppvlpi.grp == grp) { + value = cs->hppvlpi.irq; + } + } else if (idx >= 0) { uint64_t lr = cs->ich_lr_el2[idx]; int thisgrp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0; @@ -650,6 +736,18 @@ static void icv_activate_irq(GICv3CPUState *cs, int idx, int grp) cs->ich_apr[grp][regno] |= (1 << regbit); } +static void icv_activate_vlpi(GICv3CPUState *cs) +{ + uint32_t mask = icv_gprio_mask(cs, cs->hppvlpi.grp); + int prio = cs->hppvlpi.prio & mask; + int aprbit = prio >> (8 - cs->vprebits); + int regno = aprbit / 32; + int regbit = aprbit % 32; + + cs->ich_apr[cs->hppvlpi.grp][regno] |= (1 << regbit); + gicv3_redist_vlpi_pending(cs, cs->hppvlpi.irq, 0); +} + static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri) { GICv3CPUState *cs = icc_cs_from_env(env); @@ -657,7 +755,12 @@ static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri) int idx = hppvi_index(cs); uint64_t intid = INTID_SPURIOUS; - if (idx >= 0) { + if (idx == HPPVI_INDEX_VLPI) { + if (cs->hppvlpi.grp == grp && icv_hppvlpi_can_preempt(cs)) { + intid = cs->hppvlpi.irq; + icv_activate_vlpi(cs); + } + } else if (idx >= 0) { uint64_t lr = cs->ich_lr_el2[idx]; int thisgrp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0; @@ -2632,6 +2735,12 @@ static void gicv3_cpuif_el_change_hook(ARMCPU *cpu, void *opaque) GICv3CPUState *cs = opaque; gicv3_cpuif_update(cs); + /* + * Because vLPIs are only pending in NonSecure state, + * an EL change can change the VIRQ/VFIQ status (but + * cannot affect the maintenance interrupt state) + */ + gicv3_cpuif_virt_irq_fiq_update(cs); } void gicv3_init_cpuif(GICv3State *s) diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index c310d7f8ff2..3464972c139 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -855,6 +855,14 @@ void gicv3_redist_movall_lpis(GICv3CPUState *src, GICv3CPUState *dest) gicv3_redist_update_lpi(dest); } +void gicv3_redist_vlpi_pending(GICv3CPUState *cs, int irq, int level) +{ + /* + * The redistributor handling for changing the pending state + * of a vLPI will be added in a subsequent commit. + */ +} + void gicv3_redist_process_vlpi(GICv3CPUState *cs, int irq, uint64_t vptaddr, int doorbell, int level) { diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 36c3fe4da0b..5271590304b 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -151,7 +151,7 @@ gicv3_icv_hppir_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_HPPIR%d rea gicv3_icv_dir_write(uint32_t cpu, uint64_t val) "GICv3 ICV_DIR write cpu 0x%x value 0x%" PRIx64 gicv3_icv_iar_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_IAR%d read cpu 0x%x value 0x%" PRIx64 gicv3_icv_eoir_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_EOIR%d write cpu 0x%x value 0x%" PRIx64 -gicv3_cpuif_virt_update(uint32_t cpuid, int idx) "GICv3 CPU i/f 0x%x virt HPPI update LR index %d" +gicv3_cpuif_virt_update(uint32_t cpuid, int idx, int hppvlpi, int grp, int prio) "GICv3 CPU i/f 0x%x virt HPPI update LR index %d HPPVLPI %d grp %d prio %d" gicv3_cpuif_virt_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel) "GICv3 CPU i/f 0x%x virt HPPI update: setting FIQ %d IRQ %d" gicv3_cpuif_virt_set_maint_irq(uint32_t cpuid, int maintlevel) "GICv3 CPU i/f 0x%x virt HPPI update: setting maintenance-irq %d" From patchwork Fri Apr 8 14:15:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558826 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp377565map; Fri, 8 Apr 2022 07:34:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyPQvXV7iyLEFrjhQMM73MPZvKOj95MTRJ2YhZQlHAPBgOLkE7BQzxlB+LGZMCBNQHiDQBb X-Received: by 2002:a81:2f12:0:b0:2eb:d54c:6abb with SMTP id v18-20020a812f12000000b002ebd54c6abbmr5176564ywv.123.1649428464087; Fri, 08 Apr 2022 07:34:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649428464; cv=none; d=google.com; s=arc-20160816; b=AyZilVMAhcbrX5lW7hEOAYZAkW2Ramh+ntiIQxORp7UJt6ethpdKsyUjP51ZqIM76U oboD5/qEYF1x5+Bbxneza4GDRYFV5/zlriSUB8BaWxDclqgv957TBiZFvZQsgaZRoh+/ k5k+lwbdlfzzKK6fPLMPGliK+cCV19QfJNfBqwcUpUMsPfNj3kMpYS+SEF/jh2lmdBWs mDqSwwe/w9gWDzCOyPkkPbmHKlpz9x9d+MrQ9AgtlTPfNqdGtyOwZK7VQaL3k5QBxkI/ aSOLYc1mgbqP04c6zY84GosHcifM1JOxtN0ObbiaqMPa8e2KWdMFuQnici8P+xJmHabM H9jg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=c2w8hD7BvI/mrPbeJHM/ddfGPpF2hd8m8r56TLjlSxo=; b=1Ku+mloazAWX2qEr9qpo4qv9FWMZA39ulbT4Wpfbt+s+H2OTjwJDSxKqDR4qkkrMp9 7sqPEX4YO75uCm5JNA1j/zOUorpkQVEplUCwtkMNb+sXKIk+wnbEd46UCjlETvJH/ks4 ahMM7YdZGZV64BbNU3pQjU4MjjvCvemKzP8928c23eBbSQKsbetRhyIuVqcfqcZwUn8V jk9RL9wBOYv1EI8jVFKasGugKphVaTgW+3h6oDLHaHkMx+76hUfKrry3puu/v9aACl31 gs10l1R761SpuOtZFwjYJ5rJQxPbHDbT/+M00VAr3v4uX5x155+XQXJXH8Pht9fAf6GY dgwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=McqFH8HA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:17 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 26/41] hw/intc/arm_gicv3_cpuif: Don't recalculate maintenance irq unnecessarily Date: Fri, 8 Apr 2022 15:15:35 +0100 Message-Id: <20220408141550.1271295-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The maintenance interrupt state depends only on: * ICH_HCR_EL2 * ICH_LR_EL2 * ICH_VMCR_EL2 fields VENG0 and VENG1 Now we have a separate function that updates only the vIRQ and vFIQ lines, use that in places that only change state that affects vIRQ and vFIQ but not the maintenance interrupt. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_cpuif.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index f11863ff613..d627ddac90f 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -543,7 +543,7 @@ static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU; - gicv3_cpuif_virt_update(cs); + gicv3_cpuif_virt_irq_fiq_update(cs); return; } @@ -588,7 +588,7 @@ static void icv_bpr_write(CPUARMState *env, const ARMCPRegInfo *ri, write_vbpr(cs, grp, value); - gicv3_cpuif_virt_update(cs); + gicv3_cpuif_virt_irq_fiq_update(cs); } static uint64_t icv_pmr_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -615,7 +615,7 @@ static void icv_pmr_write(CPUARMState *env, const ARMCPRegInfo *ri, cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT, ICH_VMCR_EL2_VPMR_LENGTH, value); - gicv3_cpuif_virt_update(cs); + gicv3_cpuif_virt_irq_fiq_update(cs); } static uint64_t icv_igrpen_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -682,7 +682,7 @@ static void icv_ctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VEOIM_SHIFT, 1, value & ICC_CTLR_EL1_EOIMODE ? 1 : 0); - gicv3_cpuif_virt_update(cs); + gicv3_cpuif_virt_irq_fiq_update(cs); } static uint64_t icv_rpr_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -2452,7 +2452,7 @@ static void ich_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value); cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU; - gicv3_cpuif_virt_update(cs); + gicv3_cpuif_virt_irq_fiq_update(cs); } static uint64_t ich_hcr_read(CPUARMState *env, const ARMCPRegInfo *ri) From patchwork Fri Apr 8 14:15:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558828 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp379297map; Fri, 8 Apr 2022 07:36:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy05qeLoS5gR0GJxETvgPxWJPneSnqmGZyMiz8ZmioXh0t1kePVK1/qdO8K6+b1yc3j8WRi X-Received: by 2002:a25:b9ca:0:b0:619:649f:1bf6 with SMTP id y10-20020a25b9ca000000b00619649f1bf6mr13789755ybj.196.1649428590912; Fri, 08 Apr 2022 07:36:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649428590; cv=none; d=google.com; s=arc-20160816; b=YPYlcjErw3HFqg+/Q5qheODvyPPQqxNu11DM1W1Hj8q5FE4BKZkluhS0PbDcTepqj5 dC/X84+yHId08mYLHixGpIWGOwEmwAaSNgx+d8XZL8pmOyg2zUe2CedM/M39eLnWrXJl rGGmeqOxTJWxl35Via/wfPTdePEuWm8PmX4qxWPMtQ0a5/D0krUxnNEp8UHF/3eeOCDT +ReMF7IXK4n3Dp5dZkkbdEay5ycioFnRdvN1biQZ/oi8N+0EXcFO5lKzxZ/WsdM2AsWp YkVqUAKeC5wzKHEanCC08Ce6JXhZBVv71UPY2SvFcuvTaX9ktjrGZdWM+m8CeekQBo/x g2aQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=L6tbfFm8N5ZoKDybbZ+JmSH4TaIf15FtacXwnPlIlf8=; b=voP7QMYDzPUZ6tjareDSzJ0QzZHYhKBq1AlJ3leI8NGicyD87qfZGgPC6jPC1Pdmm8 iCq/oxqeHXIkOOMkrP8AjMpHx16rkbIe1mff0tR9ZcBHIoV3fXW6E0lpUrQIIjRopR4H tl/A11h0oSZUl0wHJIZvgrvX2FPymCXmEA5lknwNpuP9Geyqo+8diH93PouoIiwVTy3D MmeuWOj2UdXI3hHjPGsOPFVFjc2Wa79JkHq5I2n4+aCKWtfBQVbD7YROWZCOGxL6UvwG KFuQkPIb2emjubOhVQ7eBW4WqJlW6+977ntcBGTJwVnQJRVjGdgqpdxfYX11Z2dLnyK7 ZcXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=r2ovS9d9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:18 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 27/41] hw/intc/arm_gicv3_redist: Factor out "update hpplpi for one LPI" logic Date: Fri, 8 Apr 2022 15:15:36 +0100 Message-Id: <20220408141550.1271295-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Currently the functions which update the highest priority pending LPI information by looking at the LPI Pending and Configuration tables are hard-coded to use the physical LPI tables addressed by GICR_PENDBASER and GICR_PROPBASER. To support virtual LPIs we will need to do essentially the same job, but looking at the current virtual LPI Pending and Configuration tables and updating cs->hppvlpi instead of cs->hpplpi. Factor out the common part of the gicv3_redist_check_lpi_priority() function into a new update_for_one_lpi() function, which updates a PendingIrq struct if the specified LPI is higher priority than what is currently recorded there. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_redist.c | 74 ++++++++++++++++++++++++-------------- 1 file changed, 47 insertions(+), 27 deletions(-) diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 3464972c139..571e0fa8309 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -60,6 +60,49 @@ static uint32_t gicr_read_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs, return reg; } +/** + * update_for_one_lpi: Update pending information if this LPI is better + * + * @cs: GICv3CPUState + * @irq: interrupt to look up in the LPI Configuration table + * @ctbase: physical address of the LPI Configuration table to use + * @ds: true if priority value should not be shifted + * @hpp: points to pending information to update + * + * Look up @irq in the Configuration table specified by @ctbase + * to see if it is enabled and what its priority is. If it is an + * enabled interrupt with a higher priority than that currently + * recorded in @hpp, update @hpp. + */ +static void update_for_one_lpi(GICv3CPUState *cs, int irq, + uint64_t ctbase, bool ds, PendingIrq *hpp) +{ + uint8_t lpite; + uint8_t prio; + + address_space_read(&cs->gic->dma_as, + ctbase + ((irq - GICV3_LPI_INTID_START) * sizeof(lpite)), + MEMTXATTRS_UNSPECIFIED, &lpite, sizeof(lpite)); + + if (!(lpite & LPI_CTE_ENABLED)) { + return; + } + + if (ds) { + prio = lpite & LPI_PRIORITY_MASK; + } else { + prio = ((lpite & LPI_PRIORITY_MASK) >> 1) | 0x80; + } + + if ((prio < hpp->prio) || + ((prio == hpp->prio) && (irq <= hpp->irq))) { + hpp->irq = irq; + hpp->prio = prio; + /* LPIs and vLPIs are always non-secure Grp1 interrupts */ + hpp->grp = GICV3_G1NS; + } +} + static uint8_t gicr_read_ipriorityr(GICv3CPUState *cs, MemTxAttrs attrs, int irq) { @@ -598,34 +641,11 @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data, static void gicv3_redist_check_lpi_priority(GICv3CPUState *cs, int irq) { - AddressSpace *as = &cs->gic->dma_as; - uint64_t lpict_baddr; - uint8_t lpite; - uint8_t prio; + uint64_t lpict_baddr = cs->gicr_propbaser & R_GICR_PROPBASER_PHYADDR_MASK; - lpict_baddr = cs->gicr_propbaser & R_GICR_PROPBASER_PHYADDR_MASK; - - address_space_read(as, lpict_baddr + ((irq - GICV3_LPI_INTID_START) * - sizeof(lpite)), MEMTXATTRS_UNSPECIFIED, &lpite, - sizeof(lpite)); - - if (!(lpite & LPI_CTE_ENABLED)) { - return; - } - - if (cs->gic->gicd_ctlr & GICD_CTLR_DS) { - prio = lpite & LPI_PRIORITY_MASK; - } else { - prio = ((lpite & LPI_PRIORITY_MASK) >> 1) | 0x80; - } - - if ((prio < cs->hpplpi.prio) || - ((prio == cs->hpplpi.prio) && (irq <= cs->hpplpi.irq))) { - cs->hpplpi.irq = irq; - cs->hpplpi.prio = prio; - /* LPIs are always non-secure Grp1 interrupts */ - cs->hpplpi.grp = GICV3_G1NS; - } + update_for_one_lpi(cs, irq, lpict_baddr, + cs->gic->gicd_ctlr & GICD_CTLR_DS, + &cs->hpplpi); } void gicv3_redist_update_lpi_only(GICv3CPUState *cs) From patchwork Fri Apr 8 14:15:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558838 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp385114map; Fri, 8 Apr 2022 07:44:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy49RGBRCvhmOTrZHINkCM2DJfxvqQ3292ejEluSfJ46uG3+Vjgl7SCFGWEgbWRkOr1Kq9D X-Received: by 2002:a0d:e545:0:b0:2e7:f8bd:c0a3 with SMTP id o66-20020a0de545000000b002e7f8bdc0a3mr16227485ywe.339.1649429046168; Fri, 08 Apr 2022 07:44:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649429046; cv=none; d=google.com; s=arc-20160816; b=P9NKEIiAVNEWfRuMFAgYTik0Ltr1f9bZCcuC7FNjbOM5urXgdYr838aLToeuSlY2+c ywezfNy+G8KMr5G0x+bIgMWM3Z2hvMbHNbilU4jEIiqYRi8KZ/n9hOfQJuacnJndpetz 0owoSZ6WLkfzTiPhsvdex7sg5myBGSSGfTLK96eXuBC9ApXVf037e3cMtsavnt1ZWpbh s2oM2KjZ2nA9mA+bP1xq9Mk//r3KLp3fZ/ZgN2Ei+/6aEfsVBSoPMUwDBrJBG6SQ9PlG VKkrgFdt5kY7/AyJo6hSaiPi3qqrDTr1JnYOpSxt6QeHpBXc5Wtpvx6Wu9S9kZOustZg uymg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/SF58xglVqb/RRANG/yGXyzTNT64YvBR8SylTgH6uh4=; b=OLbHYz4SOGGVWoCb6wCpb78r7eQkDrsw+yd7Oemmy7cvcfDMTz9xj4Q+k29abLenXd KyGjZwY9cqEAqxvOufhgKrQurchJbvIDKhlDUUGmOEYMjj60gzlSpd/PEBzZvQ6UwIpx 7b/UAqiOuRwYk43Irjr1dfPnc0j0U4DRXYbcP9LHNRPgbMGealYOyJiHwwUOeBhI7sWk ii6rrb1YYwYxrOE309GqmDJJ8SkMz9e7UQteWhFGQRcdJrQB/IxAyDyvA9H88pLy1X5R YUepsfBJXf2J8isywch8FjYnbpyj1hxjfGEPPOvcnsiKPfkdhGDS561o7+wLDnzbJzOt seHg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fVjw8TJc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:19 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 28/41] hw/intc/arm_gicv3_redist: Factor out "update hpplpi for all LPIs" logic Date: Fri, 8 Apr 2022 15:15:37 +0100 Message-Id: <20220408141550.1271295-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Factor out the common part of gicv3_redist_update_lpi_only() into a new function update_for_all_lpis(), which does a full rescan of an LPI Pending table and sets the specified PendingIrq struct with the highest priority pending enabled LPI it finds. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_redist.c | 66 ++++++++++++++++++++++++++------------ 1 file changed, 46 insertions(+), 20 deletions(-) diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 571e0fa8309..2379389d14e 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -103,6 +103,48 @@ static void update_for_one_lpi(GICv3CPUState *cs, int irq, } } +/** + * update_for_all_lpis: Fully scan LPI tables and find best pending LPI + * + * @cs: GICv3CPUState + * @ptbase: physical address of LPI Pending table + * @ctbase: physical address of LPI Configuration table + * @ptsizebits: size of tables, specified as number of interrupt ID bits minus 1 + * @ds: true if priority value should not be shifted + * @hpp: points to pending information to set + * + * Recalculate the highest priority pending enabled LPI from scratch, + * and set @hpp accordingly. + * + * We scan the LPI pending table @ptbase; for each pending LPI, we read the + * corresponding entry in the LPI configuration table @ctbase to extract + * the priority and enabled information. + * + * We take @ptsizebits in the form idbits-1 because this is the way that + * LPI table sizes are architecturally specified in GICR_PROPBASER.IDBits + * and in the VMAPP command's VPT_size field. + */ +static void update_for_all_lpis(GICv3CPUState *cs, uint64_t ptbase, + uint64_t ctbase, unsigned ptsizebits, + bool ds, PendingIrq *hpp) +{ + AddressSpace *as = &cs->gic->dma_as; + uint8_t pend; + uint32_t pendt_size = (1ULL << (ptsizebits + 1)); + int i, bit; + + hpp->prio = 0xff; + + for (i = GICV3_LPI_INTID_START / 8; i < pendt_size / 8; i++) { + address_space_read(as, ptbase + i, MEMTXATTRS_UNSPECIFIED, &pend, 1); + while (pend) { + bit = ctz32(pend); + update_for_one_lpi(cs, i * 8 + bit, ctbase, ds, hpp); + pend &= ~(1 << bit); + } + } +} + static uint8_t gicr_read_ipriorityr(GICv3CPUState *cs, MemTxAttrs attrs, int irq) { @@ -657,11 +699,7 @@ void gicv3_redist_update_lpi_only(GICv3CPUState *cs) * priority is lower than the last computed high priority lpi interrupt. * If yes, replace current LPI as the new high priority lpi interrupt. */ - AddressSpace *as = &cs->gic->dma_as; - uint64_t lpipt_baddr; - uint32_t pendt_size = 0; - uint8_t pend; - int i, bit; + uint64_t lpipt_baddr, lpict_baddr; uint64_t idbits; idbits = MIN(FIELD_EX64(cs->gicr_propbaser, GICR_PROPBASER, IDBITS), @@ -671,23 +709,11 @@ void gicv3_redist_update_lpi_only(GICv3CPUState *cs) return; } - cs->hpplpi.prio = 0xff; - lpipt_baddr = cs->gicr_pendbaser & R_GICR_PENDBASER_PHYADDR_MASK; + lpict_baddr = cs->gicr_propbaser & R_GICR_PROPBASER_PHYADDR_MASK; - /* Determine the highest priority pending interrupt among LPIs */ - pendt_size = (1ULL << (idbits + 1)); - - for (i = GICV3_LPI_INTID_START / 8; i < pendt_size / 8; i++) { - address_space_read(as, lpipt_baddr + i, MEMTXATTRS_UNSPECIFIED, &pend, - sizeof(pend)); - - while (pend) { - bit = ctz32(pend); - gicv3_redist_check_lpi_priority(cs, i * 8 + bit); - pend &= ~(1 << bit); - } - } + update_for_all_lpis(cs, lpipt_baddr, lpict_baddr, idbits, + cs->gic->gicd_ctlr & GICD_CTLR_DS, &cs->hpplpi); } void gicv3_redist_update_lpi(GICv3CPUState *cs) From patchwork Fri Apr 8 14:15:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558841 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp387447map; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:19 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 29/41] hw/intc/arm_gicv3_redist: Recalculate hppvlpi on VPENDBASER writes Date: Fri, 8 Apr 2022 15:15:38 +0100 Message-Id: <20220408141550.1271295-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The guest uses GICR_VPENDBASER to tell the redistributor when it is scheduling or descheduling a vCPU. When it writes and changes the VALID bit from 0 to 1, it is scheduling a vCPU, and we must update our view of the current highest priority pending vLPI from the new Pending and Configuration tables. When it writes and changes the VALID bit from 1 to 0, it is descheduling, which means that there is no longer a highest priority pending vLPI. The specification allows the implementation to use part of the vLPI Pending table as an IMPDEF area where it can cache information when a vCPU is descheduled, so that it can avoid having to do a full rescan of the tables when the vCPU is scheduled again. For now, we don't take advantage of this, and simply do a complete rescan. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_redist.c | 87 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 84 insertions(+), 3 deletions(-) diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 2379389d14e..bfdde36a206 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -185,6 +185,87 @@ static void gicr_write_ipriorityr(GICv3CPUState *cs, MemTxAttrs attrs, int irq, cs->gicr_ipriorityr[irq] = value; } +static void gicv3_redist_update_vlpi_only(GICv3CPUState *cs) +{ + uint64_t ptbase, ctbase, idbits; + + if (!FIELD_EX64(cs->gicr_vpendbaser, GICR_VPENDBASER, VALID)) { + cs->hppvlpi.prio = 0xff; + return; + } + + ptbase = cs->gicr_vpendbaser & R_GICR_VPENDBASER_PHYADDR_MASK; + ctbase = cs->gicr_vpropbaser & R_GICR_VPROPBASER_PHYADDR_MASK; + idbits = FIELD_EX64(cs->gicr_vpropbaser, GICR_VPROPBASER, IDBITS); + + update_for_all_lpis(cs, ptbase, ctbase, idbits, true, &cs->hppvlpi); +} + +static void gicv3_redist_update_vlpi(GICv3CPUState *cs) +{ + gicv3_redist_update_vlpi_only(cs); + gicv3_cpuif_virt_irq_fiq_update(cs); +} + +static void gicr_write_vpendbaser(GICv3CPUState *cs, uint64_t newval) +{ + /* Write @newval to GICR_VPENDBASER, handling its effects */ + bool oldvalid = FIELD_EX64(cs->gicr_vpendbaser, GICR_VPENDBASER, VALID); + bool newvalid = FIELD_EX64(newval, GICR_VPENDBASER, VALID); + bool pendinglast; + + /* + * The DIRTY bit is read-only and for us is always zero; + * other fields are writeable. + */ + newval &= R_GICR_VPENDBASER_INNERCACHE_MASK | + R_GICR_VPENDBASER_SHAREABILITY_MASK | + R_GICR_VPENDBASER_PHYADDR_MASK | + R_GICR_VPENDBASER_OUTERCACHE_MASK | + R_GICR_VPENDBASER_PENDINGLAST_MASK | + R_GICR_VPENDBASER_IDAI_MASK | + R_GICR_VPENDBASER_VALID_MASK; + + if (oldvalid && newvalid) { + /* + * Changing other fields while VALID is 1 is UNPREDICTABLE; + * we choose to log and ignore the write. + */ + if (cs->gicr_vpendbaser ^ newval) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Changing GICR_VPENDBASER when VALID=1 " + "is UNPREDICTABLE\n", __func__); + } + return; + } + if (!oldvalid && !newvalid) { + cs->gicr_vpendbaser = newval; + return; + } + + if (newvalid) { + /* + * Valid going from 0 to 1: update hppvlpi from tables. + * If IDAI is 0 we are allowed to use the info we cached in + * the IMPDEF area of the table. + * PendingLast is RES1 when we make this transition. + */ + pendinglast = true; + } else { + /* + * Valid going from 1 to 0: + * Set PendingLast if there was a pending enabled interrupt + * for the vPE that was just descheduled. + * If we cache info in the IMPDEF area, write it out here. + */ + pendinglast = cs->hppvlpi.prio != 0xff; + } + + newval = FIELD_DP64(newval, GICR_VPENDBASER, PENDINGLAST, pendinglast); + cs->gicr_vpendbaser = newval; + gicv3_redist_update_vlpi(cs); +} + static MemTxResult gicr_readb(GICv3CPUState *cs, hwaddr offset, uint64_t *data, MemTxAttrs attrs) { @@ -493,10 +574,10 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset, cs->gicr_vpropbaser = deposit64(cs->gicr_vpropbaser, 32, 32, value); return MEMTX_OK; case GICR_VPENDBASER: - cs->gicr_vpendbaser = deposit64(cs->gicr_vpendbaser, 0, 32, value); + gicr_write_vpendbaser(cs, deposit64(cs->gicr_vpendbaser, 0, 32, value)); return MEMTX_OK; case GICR_VPENDBASER + 4: - cs->gicr_vpendbaser = deposit64(cs->gicr_vpendbaser, 32, 32, value); + gicr_write_vpendbaser(cs, deposit64(cs->gicr_vpendbaser, 32, 32, value)); return MEMTX_OK; default: return MEMTX_ERROR; @@ -557,7 +638,7 @@ static MemTxResult gicr_writell(GICv3CPUState *cs, hwaddr offset, cs->gicr_vpropbaser = value; return MEMTX_OK; case GICR_VPENDBASER: - cs->gicr_vpendbaser = value; + gicr_write_vpendbaser(cs, value); return MEMTX_OK; default: return MEMTX_ERROR; From patchwork Fri Apr 8 14:15:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558832 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp381202map; Fri, 8 Apr 2022 07:39:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx+7uktJvywOIszVeJqpgGBMacZDWpgKu/ZeBlshZI3LGKTy9Gvj/uXXgoDf9vlt4hKvFhm X-Received: by 2002:a25:b7c8:0:b0:633:5650:781e with SMTP id u8-20020a25b7c8000000b006335650781emr13560423ybj.466.1649428741203; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:20 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 30/41] hw/intc/arm_gicv3_redist: Factor out "update bit in pending table" code Date: Fri, 8 Apr 2022 15:15:39 +0100 Message-Id: <20220408141550.1271295-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Factor out the code which sets a single bit in an LPI pending table. We're going to need this for handling vLPI tables, not just the physical LPI table. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_redist.c | 49 +++++++++++++++++++++++--------------- 1 file changed, 30 insertions(+), 19 deletions(-) diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index bfdde36a206..64e5d96ac36 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -145,6 +145,34 @@ static void update_for_all_lpis(GICv3CPUState *cs, uint64_t ptbase, } } +/** + * set_lpi_pending_bit: Set or clear pending bit for an LPI + * + * @cs: GICv3CPUState + * @ptbase: physical address of LPI Pending table + * @irq: LPI to change pending state for + * @level: 0 to clear pending state, 1 to set + * + * Returns true if we needed to do something, false if the pending bit + * was already at @level. + */ +static bool set_pending_table_bit(GICv3CPUState *cs, uint64_t ptbase, + int irq, int level) +{ + AddressSpace *as = &cs->gic->dma_as; + uint64_t addr = ptbase + irq / 8; + uint8_t pend; + + address_space_read(as, addr, MEMTXATTRS_UNSPECIFIED, &pend, 1); + if (extract32(pend, irq % 8, 1) == level) { + /* Bit already at requested state, no action required */ + return false; + } + pend = deposit32(pend, irq % 8, 1, level ? 1 : 0); + address_space_write(as, addr, MEMTXATTRS_UNSPECIFIED, &pend, 1); + return true; +} + static uint8_t gicr_read_ipriorityr(GICv3CPUState *cs, MemTxAttrs attrs, int irq) { @@ -809,30 +837,13 @@ void gicv3_redist_lpi_pending(GICv3CPUState *cs, int irq, int level) * This function updates the pending bit in lpi pending table for * the irq being activated or deactivated. */ - AddressSpace *as = &cs->gic->dma_as; uint64_t lpipt_baddr; - bool ispend = false; - uint8_t pend; - /* - * get the bit value corresponding to this irq in the - * lpi pending table - */ lpipt_baddr = cs->gicr_pendbaser & R_GICR_PENDBASER_PHYADDR_MASK; - - address_space_read(as, lpipt_baddr + ((irq / 8) * sizeof(pend)), - MEMTXATTRS_UNSPECIFIED, &pend, sizeof(pend)); - - ispend = extract32(pend, irq % 8, 1); - - /* no change in the value of pending bit, return */ - if (ispend == level) { + if (!set_pending_table_bit(cs, lpipt_baddr, irq, level)) { + /* no change in the value of pending bit, return */ return; } - pend = deposit32(pend, irq % 8, 1, level ? 1 : 0); - - address_space_write(as, lpipt_baddr + ((irq / 8) * sizeof(pend)), - MEMTXATTRS_UNSPECIFIED, &pend, sizeof(pend)); /* * check if this LPI is better than the current hpplpi, if yes From patchwork Fri Apr 8 14:15:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558837 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp384364map; Fri, 8 Apr 2022 07:43:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx4VTvfSREzBaPkLoAtd8d4WpHZHNWSmpJMdCQ46fVw5EWPlbX7+gsuovWFB7SELdqCOgy/ X-Received: by 2002:a81:70d7:0:b0:2eb:6e49:612b with SMTP id l206-20020a8170d7000000b002eb6e49612bmr16702009ywc.414.1649428982489; Fri, 08 Apr 2022 07:43:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649428982; cv=none; d=google.com; s=arc-20160816; b=KfBm+1Dmn1HC69GIyWepFg93SZTURJq2k7gbrfYVJj3JAvBf1DRHEdMrSCK8XAOyBC qdRdI01zggTGJRckQ5hu4oLcvnRTjTU1MUtsSN6845KIaOLEIz7a8Qys6JEVEquI6b1U +1O9VZ6lpZvV8sIbc8WOEaB1xnyPUsMAq0iogCtKQ8PP7lsMuGGEqyLieWRDXDuN1laG 1x3Itcj/ChBXiG8FlZQfnGd9V2WxoOuIAo8Mm7ukG6OsRs7o9wjLQgD4VjzG3E10BC0G kIlJRue1NeA2G7pMLgqARe/X42G6wWKHY1lWzj2oiYEy0fK5nFSKIqnOSAWXfCH6+d6L dv+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=wpIByKslkvTJxYsYScwOMJpdk5pjHsxRK95xfG0789k=; b=X5Rn3hODn6uFi3/4EQVqJGQWSbTUq09kkLoKsMiR0MK0ccREnRXauYkxkW+c/85IYt twt0SB4NXyBCfmOjU5WxR/pdNnZzxyaslAM4KZAxgokq5UBancA4R/OUVkHpgyCS6fu0 BD3a5itWd9o1M9aTwnkGR6gbHjINAJRmlzlAR2p9Q/DMJJz4hQJ8MA94i8Ju+06/D+PI qFe/dKgoQ1gtmYCjxalF/NTxul3xHtgXmMMpMLf+VQomRw3xJAX9azTbjcPIVyAc4uX7 RkzEfKCxhAl9oa7Gl9aDIcy13Wo2jjKEij7zffssGqogD41X37L3Tty5vg0wWmOXh557 41pw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=URmm8zLv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:21 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 31/41] hw/intc/arm_gicv3_redist: Implement gicv3_redist_process_vlpi() Date: Fri, 8 Apr 2022 15:15:40 +0100 Message-Id: <20220408141550.1271295-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Implement the function gicv3_redist_process_vlpi(), which was left as just a stub earlier. This function deals with being handed a VLPI by the ITS. It must set the bit in the pending table. If the vCPU is currently resident we must recalculate the highest priority pending vLPI; otherwise we may need to ring a "doorbell" interrupt to let the hypervisor know it might want to reschedule the vCPU. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_redist.c | 48 ++++++++++++++++++++++++++++++++++---- 1 file changed, 44 insertions(+), 4 deletions(-) diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 64e5d96ac36..be36978b45c 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -60,6 +60,19 @@ static uint32_t gicr_read_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs, return reg; } +static bool vcpu_resident(GICv3CPUState *cs, uint64_t vptaddr) +{ + /* + * Return true if a vCPU is resident, which is defined by + * whether the GICR_VPENDBASER register is marked VALID and + * has the right virtual pending table address. + */ + if (!FIELD_EX64(cs->gicr_vpendbaser, GICR_VPENDBASER, VALID)) { + return false; + } + return vptaddr == (cs->gicr_vpendbaser & R_GICR_VPENDBASER_PHYADDR_MASK); +} + /** * update_for_one_lpi: Update pending information if this LPI is better * @@ -1004,10 +1017,37 @@ void gicv3_redist_vlpi_pending(GICv3CPUState *cs, int irq, int level) void gicv3_redist_process_vlpi(GICv3CPUState *cs, int irq, uint64_t vptaddr, int doorbell, int level) { - /* - * The redistributor handling for being handed a VLPI by the ITS - * will be added in a subsequent commit. - */ + bool bit_changed; + bool resident = vcpu_resident(cs, vptaddr); + uint64_t ctbase; + + if (resident) { + uint32_t idbits = FIELD_EX64(cs->gicr_vpropbaser, GICR_VPROPBASER, IDBITS); + if (irq >= (1ULL << (idbits + 1))) { + return; + } + } + + bit_changed = set_pending_table_bit(cs, vptaddr, irq, level); + if (resident && bit_changed) { + if (level) { + /* Check whether this vLPI is now the best */ + ctbase = cs->gicr_vpropbaser & R_GICR_VPROPBASER_PHYADDR_MASK; + update_for_one_lpi(cs, irq, ctbase, true, &cs->hppvlpi); + gicv3_cpuif_virt_irq_fiq_update(cs); + } else { + /* Only need to recalculate if this was previously the best vLPI */ + if (irq == cs->hppvlpi.irq) { + gicv3_redist_update_vlpi(cs); + } + } + } + + if (!resident && level && doorbell != INTID_SPURIOUS && + (cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS)) { + /* vCPU is not currently resident: ring the doorbell */ + gicv3_redist_process_lpi(cs, doorbell, 1); + } } void gicv3_redist_mov_vlpi(GICv3CPUState *src, uint64_t src_vptaddr, From patchwork Fri Apr 8 14:15:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558835 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp383176map; Fri, 8 Apr 2022 07:41:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy5d/Pm2rQ4DikmadjpKsSjzLFjvCHXVLg5IC7rzdayaIDd+jIefdDRL2zXoyt4vqZBiIYC X-Received: by 2002:a25:e905:0:b0:641:cf9:9522 with SMTP id n5-20020a25e905000000b006410cf99522mr1519859ybd.132.1649428893346; Fri, 08 Apr 2022 07:41:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649428893; cv=none; d=google.com; s=arc-20160816; b=Ugyh4Z31Me1T/RuvhlY3UdQ0cZ+kLmvr2tcFvC6Yf0JdwqUeXd7i+Zi8bjhJXUu/q2 V7qgUaASJrQ0h+UC2J5yBl03rpanXBgK0Fp8ui4FuHkbXtZZCXlScV7zujGZaqB80rQS HSmRaXquzFuMxAOjc9OCaRSMzcCQRB162S5a5HVGTAJe9z6ifETWAzbXXDukLi2e4ICi kDjit4nSHpLIWglI9r35GuvKk3K52Vx8ZyOvk7qcGu07eyEQ+XDtjrXtAn8ZmyG4wBkY IpP0vFd1b/jUGoRb2dBpCWJA5NqhK0kq81D7CHDLMkTRzGuFJqP37SZgffHFxGKWT6dA C4DA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=v/FccBwulgnorLUec58TR8669DB+itEmBYjarGh6iH8=; b=XCenw5KUvVFMNNFVlS0CViGM+xQgU/RBRU/NHzyaWx5hIdWBdP0qbbd2QDq94xvnpZ ZfU4KiTONk90xlP8YYOUXaGERqd/5kU/ajXXGVl0M+VAJihrXSx1NDXIYCnrnQ4CTAEX 2jzKwLGSUj1V+dWPThlwywlJCahOcK6TnjcDx2V40F52RVZHgBonkh/vWp4fghV04r3H I+YX+wscjqINECDHeGJDxKq0fAf4otxxwDkrLrvZ7yAorOBYdyMe92Q6MozHjnrx9HTx E7U317MUWTfjioDVGmcMnSevEtT+B70h4s1Xh/gDaP48V1QpJhS7r2DbHibiHiI8Yh3M R0Zg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TqXwTRoP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:22 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 32/41] hw/intc/arm_gicv3_redist: Implement gicv3_redist_vlpi_pending() Date: Fri, 8 Apr 2022 15:15:41 +0100 Message-Id: <20220408141550.1271295-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Implement the function gicv3_redist_vlpi_pending(), which was previously left as a stub. This is the function that is called by the CPU interface when it changes the state of a vLPI. It's similar to gicv3_redist_process_vlpi(), but we know that the vCPU is definitely resident on the redistributor and the irq is in range, so it is a bit simpler. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_redist.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index be36978b45c..eadf5e8265e 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -1009,9 +1009,28 @@ void gicv3_redist_movall_lpis(GICv3CPUState *src, GICv3CPUState *dest) void gicv3_redist_vlpi_pending(GICv3CPUState *cs, int irq, int level) { /* - * The redistributor handling for changing the pending state - * of a vLPI will be added in a subsequent commit. + * Change the pending state of the specified vLPI. + * Unlike gicv3_redist_process_vlpi(), we know here that the + * vCPU is definitely resident on this redistributor, and that + * the irq is in range. */ + uint64_t vptbase, ctbase; + + vptbase = FIELD_EX64(cs->gicr_vpendbaser, GICR_VPENDBASER, PHYADDR) << 16; + + if (set_pending_table_bit(cs, vptbase, irq, level)) { + if (level) { + /* Check whether this vLPI is now the best */ + ctbase = cs->gicr_vpropbaser & R_GICR_VPROPBASER_PHYADDR_MASK; + update_for_one_lpi(cs, irq, ctbase, true, &cs->hppvlpi); + gicv3_cpuif_virt_irq_fiq_update(cs); + } else { + /* Only need to recalculate if this was previously the best vLPI */ + if (irq == cs->hppvlpi.irq) { + gicv3_redist_update_vlpi(cs); + } + } + } } void gicv3_redist_process_vlpi(GICv3CPUState *cs, int irq, uint64_t vptaddr, From patchwork Fri Apr 8 14:15:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558830 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp380778map; Fri, 8 Apr 2022 07:38:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy8zCl6sQurjNaUYbAnWDMrrDS700xjcsXdABA4IvxuVGP5sHDnENTrXYNWwlOINpgRdkoT X-Received: by 2002:a05:6902:724:b0:635:1972:616f with SMTP id l4-20020a056902072400b006351972616fmr15428450ybt.453.1649428705617; Fri, 08 Apr 2022 07:38:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649428705; cv=none; d=google.com; s=arc-20160816; b=TbUj5pyyLbmT+akgV6H9H+Ab+MTeURVH1LmJQFeA8bHnYfxsiKBydNR+6oC636nuAg Cy3I4xBeo7VFIvG0YSz761RXqZz4yaQP0f7BQgLc4iHu5wELDQnzdnTH4mITTAmyxQoD f6uuBPjiPuCI8so7lzIgffBpbnTUDnOMGlPoOegEb012JnRyPwzUVibJrC5qTvWoK+f5 09bludDOENHi5kQLtnzOuQt4EYZHM1vEL+40FOwrVxqH6+aOaJ8HS81Ajj0zCIHXf4gj zvuVgHWTA/ilBy2XcbEjOAxAPvltOIjvQA2dBDKHZR4xoI21WKeMs8y6Mj0+5gTXk8Q3 9tAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=uV/e+BBmbxBdtYd8klSJiLxOGkKS0wc1pLrl5b3TSlU=; b=e5KCFmIz6lu/NPUNwQtqJ0P+GYK2k3+2K++rCUOWHVkAF8AQ5Yp/3YoGaTDdcohNV4 F70sUogpxDgrrZ08Y7FbjIDvzlKdhaQzOuxbnj8sEnab1XeyFO56ohSnyKqw9dJAWT1n fM1L5sGU+LDsu9c+574LdCnIvrWZFdhoNKvn4A7SwaWLyWRkvVMBQQS+YAi/iK1lOSgl bYDgFPmoPiIPmqcYtfZREF4eEPhjShqevfjBpAfXBD+iTSJBtOUO2L0bV0qW/uwKLhhl txoopsFEx2JjKC181A5oddiCAZ698zplVV8yq+jNmarFgE3umSE1/EqAbiWC8vR1FffN okVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PmQJXd6t; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:23 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 33/41] hw/intc/arm_gicv3_redist: Use set_pending_table_bit() in mov handling Date: Fri, 8 Apr 2022 15:15:42 +0100 Message-Id: <20220408141550.1271295-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We can use our new set_pending_table_bit() utility function in gicv3_redist_mov_lpi() to clear the bit in the source pending table, rather than doing the "load, clear bit, store" ourselves. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_redist.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index eadf5e8265e..3127af3e2ca 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -909,11 +909,9 @@ void gicv3_redist_mov_lpi(GICv3CPUState *src, GICv3CPUState *dest, int irq) * we choose to NOP. If LPIs are disabled on source there's nothing * to be transferred anyway. */ - AddressSpace *as = &src->gic->dma_as; uint64_t idbits; uint32_t pendt_size; uint64_t src_baddr; - uint8_t src_pend; if (!(src->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) || !(dest->gicr_ctlr & GICR_CTLR_ENABLE_LPIS)) { @@ -932,15 +930,10 @@ void gicv3_redist_mov_lpi(GICv3CPUState *src, GICv3CPUState *dest, int irq) src_baddr = src->gicr_pendbaser & R_GICR_PENDBASER_PHYADDR_MASK; - address_space_read(as, src_baddr + (irq / 8), - MEMTXATTRS_UNSPECIFIED, &src_pend, sizeof(src_pend)); - if (!extract32(src_pend, irq % 8, 1)) { + if (!set_pending_table_bit(src, src_baddr, irq, 0)) { /* Not pending on source, nothing to do */ return; } - src_pend &= ~(1 << (irq % 8)); - address_space_write(as, src_baddr + (irq / 8), - MEMTXATTRS_UNSPECIFIED, &src_pend, sizeof(src_pend)); if (irq == src->hpplpi.irq) { /* * We just made this LPI not-pending so only need to update From patchwork Fri Apr 8 14:15:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558840 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp387080map; Fri, 8 Apr 2022 07:46:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzRx+mysNEf2zwYJ3l12WU4jY72J98YUSMdz5Bb3XW5Bisa/Sr4+LZ+d11i9vn42/D3VWBe X-Received: by 2002:a25:9788:0:b0:631:f878:e68d with SMTP id i8-20020a259788000000b00631f878e68dmr14167071ybo.251.1649429195829; Fri, 08 Apr 2022 07:46:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649429195; cv=none; d=google.com; s=arc-20160816; b=lNN28uMgAIDgAtlbELMTEmnpg9Lslru/4DA4S0zL5pRZMV9l91GDBmx179TkSD4ZlT uNO5vbxwixWzUvP7C/OvKPf0Fd+1bN9kUZwyfqBl+sccAEGZ3yba/uq7fj3XwPndycbY NFV8MjYtVo9dOd9xG5xNyQciWCJfL7Jv0MSJ+Deih0kipd1i/afzrG4eCi7gmx72Zm3b QkKdTAc4+ys60zcRtNK1oCmto92HSXzmLznNGohkO0mchJ6JnIUazaBeI+3tRWaTG55R aI7AdblarL41DBu5DTdJd82Uj8xYWcpTTsNVuI0lZB0M7gAEgUczAcAlc/zB/Y32TIT2 nFpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Ks7J+0C271Igfu0vbL909LbuL+1GBzKju/AYg8mpFsw=; b=gpO2BTIAZteDVRe5C+yTSsUYtVIx6Y/97QcPeh7uogsAGgZCNxVxfdttZ0aX/l3CtT ePlna0TVdAHRQGQ3AgJjAHs51Jq+xIk8OKRU3dBcOq1HqhhyKy/yWscQoY62Zf5YbV4Y oSkIRUMjiOdjOLlB6Cj4nnDXtLgbQPhyB61rOi5dG04muUVMgiYCLi+Xn5QZDwR9AGKF EOH4sZDGjmFIyc9k/2rBJR5Lehke3Y8EENk7vrzOx3UA4tRlcevTB7YGekjC5SdyVqGm QnVPhj+ksQdh0bodt0PHhWCEtDgn0wJvDgI4etmY4SGDntcx3XUY0cQ2OT6iMpDptIQy cadA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=F9s+HR23; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:24 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 34/41] hw/intc/arm_gicv3_redist: Implement gicv3_redist_mov_vlpi() Date: Fri, 8 Apr 2022 15:15:43 +0100 Message-Id: <20220408141550.1271295-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Implement the gicv3_redist_mov_vlpi() function (previously left as a stub). This function handles the work of a VMOVI command: it marks the vLPI not-pending on the source and pending on the destination. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_redist.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 3127af3e2ca..9866dd94c60 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -1067,9 +1067,25 @@ void gicv3_redist_mov_vlpi(GICv3CPUState *src, uint64_t src_vptaddr, int irq, int doorbell) { /* - * The redistributor handling for moving a VLPI will be added - * in a subsequent commit. + * Move the specified vLPI's pending state from the source redistributor + * to the destination. */ + if (!set_pending_table_bit(src, src_vptaddr, irq, 0)) { + /* Not pending on source, nothing to do */ + return; + } + if (vcpu_resident(src, src_vptaddr) && irq == src->hppvlpi.irq) { + /* + * Update src's cached highest-priority pending vLPI if we just made + * it not-pending + */ + gicv3_redist_update_vlpi(src); + } + /* + * Mark the vLPI pending on the destination (ringing the doorbell + * if the vCPU isn't resident) + */ + gicv3_redist_process_vlpi(dest, irq, dest_vptaddr, doorbell, irq); } void gicv3_redist_vinvall(GICv3CPUState *cs, uint64_t vptaddr) From patchwork Fri Apr 8 14:15:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558843 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp389747map; Fri, 8 Apr 2022 07:49:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzPcxh9BowSO4DZ8OJ3dEpIfy0UJv3EcMb26lo+aD7nYGgx6bT7raWhn7W0PgXieAannin8 X-Received: by 2002:a81:1b11:0:b0:2e6:a60b:2d6f with SMTP id b17-20020a811b11000000b002e6a60b2d6fmr16229736ywb.3.1649429380625; Fri, 08 Apr 2022 07:49:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649429380; cv=none; d=google.com; s=arc-20160816; b=rnM43MsU1htDmARyPzOvL5DpxYAJA+84gNEgJShTkORi01SpewfTYYjv3iy7+UF9kP sDKMZ+cRMj3cR+o5KRnp8w5imyX/TrzEo++/QJS6AsXjBnekYiXqsvMAmsnma2AIB8Vp ewuOkg9jDMzzjQ1nQkihLiBfw8wvo9s0SxX1dnS+zj4qqmByTqWDmGxDeyZJvv6thS4e EXli3AlC1YhGCX533aVEALlKCkNJz7gDl4RG7CFURAa0T+WDBmPplkw2ohzsj8zRmPlS kG3VLqezWPYK8tJzT9HtKOveHueBowKsTZQyPKchDRFvKyt5PuNyg+kJEkHkfh6K2wNx BiBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mApTko4JykaeGu3JC9+7iWWX8yyHP0SNoqvMYS15NqA=; b=NrQeyMMyW2V/ZzX0yQPU484Ee+QV5lzG+oZcgJWkpNfx38kkQ3SW6QSj9mM2Fat51t 74S8WWGyuRNL+Vj7gwNVE6JFwtP2VsdXUvmv7IM4x9maXGuY5Iyb1KN0vzXxevmj8I7Z +4tkSjGVMB5QfEatYpB7Qqh9buPglXHon+AMcWHiT0vLL/6iLZY8qnXumLibIPhq5Rz4 Md1mJvOGF72K+ZRWyL6eP4yKTgjL6tSd0VJckTwSaBndAjb02QYzWNivy0b463NyeEw4 lYf3elQLWBzGrWa61K38Xc5OPR4XXhkh5ivEj+kChCb+fPgARQ4BW8t0eLnlVRzv+5Rx KFSw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cC4yf2QD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:25 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 35/41] hw/intc/arm_gicv3_redist: Implement gicv3_redist_vinvall() Date: Fri, 8 Apr 2022 15:15:44 +0100 Message-Id: <20220408141550.1271295-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Implement the gicv3_redist_vinvall() function (previously left as a stub). This function handles the work of a VINVALL command: it must invalidate any cached information associated with a specific vCPU. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_redist.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 9866dd94c60..a586c9ef498 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -1090,7 +1090,13 @@ void gicv3_redist_mov_vlpi(GICv3CPUState *src, uint64_t src_vptaddr, void gicv3_redist_vinvall(GICv3CPUState *cs, uint64_t vptaddr) { - /* The redistributor handling will be added in a subsequent commit */ + if (!vcpu_resident(cs, vptaddr)) { + /* We don't have anything cached if the vCPU isn't resident */ + return; + } + + /* Otherwise, our only cached information is the HPPVLPI info */ + gicv3_redist_update_vlpi(cs); } void gicv3_redist_inv_vlpi(GICv3CPUState *cs, int irq, uint64_t vptaddr) From patchwork Fri Apr 8 14:15:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558844 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp390315map; Fri, 8 Apr 2022 07:50:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzlhnSufPh969RWPeU8Sp+Kabf9+cpCAo92AX8RI+TEAbceKc8ard4ovHhUtjgsKVxVxoSr X-Received: by 2002:a25:268a:0:b0:641:1592:80f8 with SMTP id m132-20020a25268a000000b00641159280f8mr1013966ybm.328.1649429423425; Fri, 08 Apr 2022 07:50:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649429423; cv=none; d=google.com; s=arc-20160816; b=Tp6f0NfQd/Od5yQ7cXavY8B7sWfr5dKbWFigEkttdmuIihcduNFQbeI0cGs9UVnfw2 HSPIW8WJqK98nfvQw4/8i8U4ofg3Dyztgssyvh/Vra20S/POa6dXe7RLX7bJbIogsCO9 NvUz1GDqi50CIbOAQCmeANFnNOSibHsOr2QZUc76nEhFVSNvwkoq3W/CfdaXscW8GygO efs+O6cKELOVf5TQ6rdCtEVOS7ibf1x4c8Ef1t6257oXmtU/74TMVuZEoU6RUJRo+MYN mBe5sDqa/FQgGhhnWJL3v5fr4vx/XFfrnrTPsZARJPZIMcl3y4f87HddLLs3C+E86ZZg rvgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=LtZz4rR4JTiEt09cH5eXBwQY/mFcoau4efeuuU9fWxY=; b=jIJbsbqWdkn1DcQftuGY3Gd1wOTMzfpbLY3+SQTyq9DhysgAsraZhHFBgfcRzVISk1 igw3oyYa00efa1DYhpW7+YBIUTMetyfuQ4FtwsWrQs2NK08eFobBZT4e9qzlaLlMhWW4 xEcZF8lrZPTomONvMylklomRmTaIOOwZSoIhYHVTqHIozhFq0EP2TRNolSho3IS5r5OM 5Nkd3Ix6ku+1XRQYuKUklgVMoyL+KB+UdY2EmzYPCdAP9B0kMbfFgfnGauDGLwBM2P90 i8NAMpDObqv3d4CMBq482n6ctMYpm69tzuzAl99Aqj1Guc9VDfPRtTXNK2FvBN5aQovU Xuiw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IQ0AkNqG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:26 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 36/41] hw/intc/arm_gicv3_redist: Implement gicv3_redist_inv_vlpi() Date: Fri, 8 Apr 2022 15:15:45 +0100 Message-Id: <20220408141550.1271295-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Implement the function gicv3_redist_inv_vlpi(), which was previously left as a stub. This is the function that does the work of the INV command for a virtual interrupt. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_redist.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index a586c9ef498..0738d3822d1 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -1102,9 +1102,12 @@ void gicv3_redist_vinvall(GICv3CPUState *cs, uint64_t vptaddr) void gicv3_redist_inv_vlpi(GICv3CPUState *cs, int irq, uint64_t vptaddr) { /* - * The redistributor handling for invalidating cached information - * about a VLPI will be added in a subsequent commit. + * The only cached information for LPIs we have is the HPPLPI. + * We could be cleverer about identifying when we don't need + * to do a full rescan of the pending table, but until we find + * this is a performance issue, just always recalculate. */ + gicv3_redist_vinvall(cs, vptaddr); } void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level) From patchwork Fri Apr 8 14:15:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558834 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp382697map; Fri, 8 Apr 2022 07:40:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxJWLHRubRYXs7bzm/zzPBpM6AeALVPIvMYXhV4jBaqW8503nHL0vQv1KANkchsAAW2RoyT X-Received: by 2002:a25:f305:0:b0:63e:76f4:4643 with SMTP id c5-20020a25f305000000b0063e76f44643mr4611530ybs.580.1649428855390; Fri, 08 Apr 2022 07:40:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649428855; cv=none; d=google.com; s=arc-20160816; b=Km/ETgq2qmxotBYS5rUrJTz9KuPB1AmUIpoR4ORuCLVry9hc30f+EvtDP4CY+0KVA4 +sm1c5yYbxBgtqz56xmmZUBjUGPZn2vNAtyd4KQwfv0OGcZ/0puht7kDusm0wvO5dAjP xDtpFLk2wlzM5x4Zg3NSIZYZtYD75BR52Fygzo1sd2dFBWCpXLmEPjDeIz8uLqgQH9kV +Q2jJAa4NEunIatDUxyOiLo8HA1vpIUY8HHYXS59ZdDv1vaY7+P+JG/6VXWKKWAEYj7F bcb/gxXsmlprXQLT0aYRoEctZnBjqMQquCag7C/VXmUMWwbRitInUiVY35zMoxoAt2a5 peqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9WO0uuchbjE/iukCWaKI+CQ8T+7VqjTELcpt1RFvvfs=; b=yzkJLE959RmMiHjB8MVHN2K46sI7iLdkdSDKHkMF2GXYqpdrQujyMpjGZR1cwvq2lR wUJBdLjAknZiXGmakzBY3phQksWfB7ZfVT/hGGLdTyuEXr59GqcArhciuEiHCLgA41DJ MD1iUrnvvXGm4pAvo6hSf1ulVIJvwanpZ7dvKYfIT/zRnxiqhHAB7PvX0M0ooa5uA0q+ 6zvtS5ODHe8z9MDtIOFI93UhM+FiXYFel1B3iDZkHgf5NW4/8rvwjWthSTKpksSWZ6Xb ZJonVJAlCtaIbz+/smZ66bX0vIxigvNvRiMp4fgUK7VZFyseNnycuvojhr7kPQhXpeXc TsgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wT5Qr6RX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:26 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 37/41] hw/intc/arm_gicv3: Update ID and feature registers for GICv4 Date: Fri, 8 Apr 2022 15:15:46 +0100 Message-Id: <20220408141550.1271295-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Update the various GIC ID and feature registers for GICv4: * PIDR2 [7:4] is the GIC architecture revision * GICD_TYPER.DVIS is 1 to indicate direct vLPI injection support * GICR_TYPER.VLPIS is 1 to indicate redistributor support for vLPIs * GITS_TYPER.VIRTUAL is 1 to indicate vLPI support * GITS_TYPER.VMOVP is 1 to indicate that our VMOVP implementation handles cross-ITS synchronization for the guest * ICH_VTR_EL2.nV4 is 0 to indicate direct vLPI injection support Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/gicv3_internal.h | 15 +++++++++++---- hw/intc/arm_gicv3_common.c | 7 +++++-- hw/intc/arm_gicv3_cpuif.c | 6 +++++- hw/intc/arm_gicv3_dist.c | 7 ++++--- hw/intc/arm_gicv3_its.c | 7 ++++++- hw/intc/arm_gicv3_redist.c | 2 +- 6 files changed, 32 insertions(+), 12 deletions(-) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 07644b2be6f..0bf68452395 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -309,6 +309,7 @@ FIELD(GITS_TYPER, SEIS, 18, 1) FIELD(GITS_TYPER, PTA, 19, 1) FIELD(GITS_TYPER, CIDBITS, 32, 4) FIELD(GITS_TYPER, CIL, 36, 1) +FIELD(GITS_TYPER, VMOVP, 37, 1) #define GITS_IDREGS 0xFFD0 @@ -747,23 +748,29 @@ static inline uint32_t gicv3_iidr(void) #define GICV3_PIDR0_REDIST 0x93 #define GICV3_PIDR0_ITS 0x94 -static inline uint32_t gicv3_idreg(int regoffset, uint8_t pidr0) +static inline uint32_t gicv3_idreg(GICv3State *s, int regoffset, uint8_t pidr0) { /* Return the value of the CoreSight ID register at the specified * offset from the first ID register (as found in the distributor * and redistributor register banks). - * These values indicate an ARM implementation of a GICv3. + * These values indicate an ARM implementation of a GICv3 or v4. */ static const uint8_t gicd_ids[] = { - 0x44, 0x00, 0x00, 0x00, 0x92, 0xB4, 0x3B, 0x00, 0x0D, 0xF0, 0x05, 0xB1 + 0x44, 0x00, 0x00, 0x00, 0x92, 0xB4, 0x0B, 0x00, 0x0D, 0xF0, 0x05, 0xB1 }; + uint32_t id; regoffset /= 4; if (regoffset == 4) { return pidr0; } - return gicd_ids[regoffset]; + id = gicd_ids[regoffset]; + if (regoffset == 6) { + /* PIDR2 bits [7:4] are the GIC architecture revision */ + id |= s->revision << 4; + } + return id; } /** diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 3f47b3501fe..181f342f32c 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -406,8 +406,8 @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp) * Last == 1 if this is the last redistributor in a series of * contiguous redistributor pages * DirectLPI == 0 (direct injection of LPIs not supported) - * VLPIS == 0 (virtual LPIs not supported) - * PLPIS == 0 (physical LPIs not supported) + * VLPIS == 1 if vLPIs supported (GICv4 and up) + * PLPIS == 1 if LPIs supported */ cpu_affid = object_property_get_uint(OBJECT(cpu), "mp-affinity", NULL); @@ -422,6 +422,9 @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp) if (s->lpi_enable) { s->cpu[i].gicr_typer |= GICR_TYPER_PLPIS; + if (s->revision > 3) { + s->cpu[i].gicr_typer |= GICR_TYPER_VLPIS; + } } } diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index d627ddac90f..8404f46ee0b 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -2578,11 +2578,15 @@ static uint64_t ich_vtr_read(CPUARMState *env, const ARMCPRegInfo *ri) uint64_t value; value = ((cs->num_list_regs - 1) << ICH_VTR_EL2_LISTREGS_SHIFT) - | ICH_VTR_EL2_TDS | ICH_VTR_EL2_NV4 | ICH_VTR_EL2_A3V + | ICH_VTR_EL2_TDS | ICH_VTR_EL2_A3V | (1 << ICH_VTR_EL2_IDBITS_SHIFT) | ((cs->vprebits - 1) << ICH_VTR_EL2_PREBITS_SHIFT) | ((cs->vpribits - 1) << ICH_VTR_EL2_PRIBITS_SHIFT); + if (cs->gic->revision < 4) { + value |= ICH_VTR_EL2_NV4; + } + trace_gicv3_ich_vtr_read(gicv3_redist_affid(cs), value); return value; } diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c index 7f6275363ea..b9ed955e36b 100644 --- a/hw/intc/arm_gicv3_dist.c +++ b/hw/intc/arm_gicv3_dist.c @@ -383,7 +383,7 @@ static bool gicd_readl(GICv3State *s, hwaddr offset, * No1N == 1 (1-of-N SPI interrupts not supported) * A3V == 1 (non-zero values of Affinity level 3 supported) * IDbits == 0xf (we support 16-bit interrupt identifiers) - * DVIS == 0 (Direct virtual LPI injection not supported) + * DVIS == 1 (Direct virtual LPI injection supported) if GICv4 * LPIS == 1 (LPIs are supported if affinity routing is enabled) * num_LPIs == 0b00000 (bits [15:11],Number of LPIs as indicated * by GICD_TYPER.IDbits) @@ -399,8 +399,9 @@ static bool gicd_readl(GICv3State *s, hwaddr offset, * so we only need to check the DS bit. */ bool sec_extn = !(s->gicd_ctlr & GICD_CTLR_DS); + bool dvis = s->revision >= 4; - *data = (1 << 25) | (1 << 24) | (sec_extn << 10) | + *data = (1 << 25) | (1 << 24) | (dvis << 18) | (sec_extn << 10) | (s->lpi_enable << GICD_TYPER_LPIS_SHIFT) | (0xf << 19) | itlinesnumber; return true; @@ -557,7 +558,7 @@ static bool gicd_readl(GICv3State *s, hwaddr offset, } case GICD_IDREGS ... GICD_IDREGS + 0x2f: /* ID registers */ - *data = gicv3_idreg(offset - GICD_IDREGS, GICV3_PIDR0_DIST); + *data = gicv3_idreg(s, offset - GICD_IDREGS, GICV3_PIDR0_DIST); return true; case GICD_SGIR: /* WO registers, return unknown value */ diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index 6c44cccd369..56f43faafd4 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -1699,7 +1699,7 @@ static bool its_readl(GICv3ITSState *s, hwaddr offset, break; case GITS_IDREGS ... GITS_IDREGS + 0x2f: /* ID registers */ - *data = gicv3_idreg(offset - GITS_IDREGS, GICV3_PIDR0_ITS); + *data = gicv3_idreg(s->gicv3, offset - GITS_IDREGS, GICV3_PIDR0_ITS); break; case GITS_TYPER: *data = extract64(s->typer, 0, 32); @@ -1946,6 +1946,11 @@ static void gicv3_arm_its_realize(DeviceState *dev, Error **errp) s->typer = FIELD_DP64(s->typer, GITS_TYPER, DEVBITS, ITS_DEVBITS); s->typer = FIELD_DP64(s->typer, GITS_TYPER, CIL, 1); s->typer = FIELD_DP64(s->typer, GITS_TYPER, CIDBITS, ITS_CIDBITS); + if (s->gicv3->revision >= 4) { + /* Our VMOVP handles cross-ITS synchronization itself */ + s->typer = FIELD_DP64(s->typer, GITS_TYPER, VMOVP, 1); + s->typer = FIELD_DP64(s->typer, GITS_TYPER, VIRTUAL, 1); + } } static void gicv3_its_reset(DeviceState *dev) diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 0738d3822d1..82dab296456 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -441,7 +441,7 @@ static MemTxResult gicr_readl(GICv3CPUState *cs, hwaddr offset, *data = cs->gicr_nsacr; return MEMTX_OK; case GICR_IDREGS ... GICR_IDREGS + 0x2f: - *data = gicv3_idreg(offset - GICR_IDREGS, GICV3_PIDR0_REDIST); + *data = gicv3_idreg(cs->gic, offset - GICR_IDREGS, GICV3_PIDR0_REDIST); return MEMTX_OK; /* * VLPI frame registers. We don't need a version check for From patchwork Fri Apr 8 14:15:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558836 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp384356map; Fri, 8 Apr 2022 07:43:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzDZcF4bXG1+SWB68Q2MuU6TKdUMtgGXdvMNycj3BYW8pCGcRzVZCU/1sL5Q8lQzyqalnDz X-Received: by 2002:a25:9e81:0:b0:624:3b8a:514b with SMTP id p1-20020a259e81000000b006243b8a514bmr13926541ybq.266.1649428983380; Fri, 08 Apr 2022 07:43:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649428983; cv=none; d=google.com; s=arc-20160816; b=Vc/lSUE2srSDSDxQH1laxe4kAqha+DVIpnNDgVIQRBG+7ipBy98DZxpAf7fj7ksZih Btjby39PrC4+ap1DB2XiLnmb5fNSxALnWe8Px23ds6wE5rSOdY9ZbMLZfxcurOkzRdLf 64FlnwxxIIhAZTYwzaXbmPQ434/UGPxcJsTXhF6SyREVMpCmFohE2v+/yvyWWLmOXUlb GFiNe0wwwUtPMgOtcipJ6vguewGG0rlBZ3WJwLsOxcyjHQjlgnEiPMev/LiOzn80tLRr Mhtqlq8Po7O1ZlAoGLdCYsogq9kvoshA3JlrljGnzSTJYfp9zQyFSQrMRDRPDMVCkBDE 5aNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=XnswKnW47+8+9tHo/ACX303pdkhT+++S3GFx5eRGIRU=; b=H7aXzJWkgavmxpgHfcg7RJilrjwmVlp9zKYnoWzTeE0YcQiz7+xDSqYoxZLqfw0nsd jKhko47JYy3QISs7L89MNgSnnnBDeEosNsyAKMitaCwAYHZCulZz28Ls5cPoMriZxJYH fYmwYp1QC9uvKF6PVQ6IkLihIFRPeQaHtxyDNcAsrUy6r8qQEo2n32CmrYn7wUnFOrGO YWgUkCFj/v4mKjAJo/Mu/xCG4xncY5gxZ7bjXVD4l0Iw7CmmH3ychGtJjyx10FOnLCnQ M/WufvQGhJj+4RGmHN6faU4YCkg8n1kNzpAncr9OW0PWlwo3BBK7yU0Hg+9bZN5Fhwlq hbtw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="h2p/RXIg"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e83-20020a255056000000b0063dbdcab10dsi613281ybb.550.2022.04.08.07.43.03 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 08 Apr 2022 07:43:03 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="h2p/RXIg"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59792 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ncppG-000284-Qd for patch@linaro.org; Fri, 08 Apr 2022 10:43:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43200) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ncpPb-0007PP-Oy for qemu-devel@nongnu.org; Fri, 08 Apr 2022 10:16:31 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:46044) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ncpPZ-0002Tz-UC for qemu-devel@nongnu.org; Fri, 08 Apr 2022 10:16:31 -0400 Received: by mail-wr1-x42b.google.com with SMTP id w4so13010209wrg.12 for ; Fri, 08 Apr 2022 07:16:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XnswKnW47+8+9tHo/ACX303pdkhT+++S3GFx5eRGIRU=; b=h2p/RXIgXv5UOyE1d6rbKEqNFYNv6xK7BgY5D5cRkUPk21TO8P2SWtXi6uunuRadD0 GFeKnRas7QsSB1eFReob96bryoubXa2GeDg/y9YMfqDBhtcqno2f+aXr3q1aFWvBJf6N bl44yl4j5eBXMTZ33LNrtXyRYYfvigAwe3ucd+nPxbIBxKcxZrIOfUFB5qsGH05ddG3x JCIs45FSJpTxwBQS8BWopL9ZjSDxxopfwoD1bZpdl6MXKcu30uCU1PMJB98Gdi/E4hZj KukMvkFU4p0DX5AzfoSLttk5Xw/RNslAsf4iT41M9+OZnxo6A896JUPU5evYHg53jafg G55A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XnswKnW47+8+9tHo/ACX303pdkhT+++S3GFx5eRGIRU=; b=KLuGTrPTg3eO6m21Eduf5RGe9Y2oJzlIGeZKD9RpQ2HSKktFeVXVwDhOvcbGWOGu7W mC/yUtEIWRXpHtlrqp/lIHCuo2Za6e6rYg6XDFUyUqWK6EpZMCmR2vveCpXS/FxQAMep Zwvb/aFUSJzEx3NM7k3mYD7e/HtBU3JXXoiknuOdmYsm8Tg+K4xK9kx5pZbd1FFA6W9o pXV746jKYH/LL+c39ubCMyqYXH4uZ+jyevPN/e3n2kXL0s0o5MGmfmE669CEsh7J5S9+ rvbfSd/tCG7DG0xBhTG4xL4KmQtEVEziQQajvEcZvwv8GAiwhh7GNdaByYA/fbAqXTeq 5TIg== X-Gm-Message-State: AOAM531as3fNMqumlTcsCh7f+sRLP1lPnlov3aruH6npwNe4VMsbaNvj AE3IpIdrJInl1w9PvXGvivjFHw== X-Received: by 2002:a5d:6c67:0:b0:204:ff0:87a8 with SMTP id r7-20020a5d6c67000000b002040ff087a8mr15159472wrz.627.1649427388116; Fri, 08 Apr 2022 07:16:28 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:27 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 38/41] hw/intc/arm_gicv3: Allow 'revision' property to be set to 4 Date: Fri, 8 Apr 2022 15:15:47 +0100 Message-Id: <20220408141550.1271295-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that we have implemented all the GICv4 requirements, relax the error-checking on the GIC object's 'revision' property to allow a TCG GIC to be a GICv4, whilst still constraining the KVM GIC to GICv3. Our 'revision' property doesn't consider the possibility of wanting to specify the minor version of the GIC -- for instance there is a GICv3.1 which adds support for extended SPI and PPI ranges, among other things, and also GICv4.1. But since the QOM property is internal to QEMU, not user-facing, we can cross that bridge when we come to it. Within the GIC implementation itself code generally checks against the appropriate ID register feature bits, and the only use of s->revision is for setting those ID register bits. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_common.c | 12 +++++++----- hw/intc/arm_gicv3_kvm.c | 5 +++++ 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 181f342f32c..5634c6fc788 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -326,12 +326,14 @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp) GICv3State *s = ARM_GICV3_COMMON(dev); int i, rdist_capacity, cpuidx; - /* revision property is actually reserved and currently used only in order - * to keep the interface compatible with GICv2 code, avoiding extra - * conditions. However, in future it could be used, for example, if we - * implement GICv4. + /* + * This GIC device supports only revisions 3 and 4. The GICv1/v2 + * is a separate device. + * Note that subclasses of this device may impose further restrictions + * on the GIC revision: notably, the in-kernel KVM GIC doesn't + * support GICv4. */ - if (s->revision != 3) { + if (s->revision != 3 && s->revision != 4) { error_setg(errp, "unsupported GIC revision %d", s->revision); return; } diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 5ec5ff9ef6e..06f5aceee52 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -781,6 +781,11 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) return; } + if (s->revision != 3) { + error_setg(errp, "unsupported GIC revision %d for in-kernel GIC", + s->revision); + } + if (s->security_extn) { error_setg(errp, "the in-kernel VGICv3 does not implement the " "security extensions"); From patchwork Fri Apr 8 14:15:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558839 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp385332map; Fri, 8 Apr 2022 07:44:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJywUF48CfF7dsMGKx/9i/YurMzYtbFG/Nq/grJfmllelLrNYbXh1PkoyWlsPNNbjdSWe4Hf X-Received: by 2002:a81:368a:0:b0:2ea:f500:ab99 with SMTP id d132-20020a81368a000000b002eaf500ab99mr16427508ywa.70.1649429059158; Fri, 08 Apr 2022 07:44:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649429059; cv=none; d=google.com; s=arc-20160816; b=kXF+6hDwNwnrirR9u/E6xgU46pRrBMqg3IzXzGL+1QfGiN2Z8EYpIZ+fA+ezr3+Jfx 6u+GEIOv2zwObZztABL2gO/0kGtadi0RK/JczzlBRLwqvFNiwPTo8L5aKgJbFiWRfgbR CbVKCvyX1TbLM+GqNIJjPlPIXPjBsFbuR25vkf182Kv3knSzCI6mE8KsycDi3MnX1tbg tf2esJGneAtA3RX6X1cchejzVWlhepi6/kQ2zqt5ABO4zXawCZaXNu/QLSIARmplX6SH ZG1qvOFoq7e7aXkXL3ULymjRQSHO4rLlTMKjS9aossCr5hYRbFekar6PiDOQ0oY4gC/1 dWBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dkdiantr7+5+MkqtF+jpkZPTMHRoOYAGUVHwgCU5zUs=; b=Jby2le6Hj37w4M4wiwTWaxGJqCojyXMLKi0QHr380qHXOTFgQlXbkmdjzDY+zUrcPi oNc6dnvpgwVAH6DMxBGPUJ9qqfX40HumWjJXclqGPWitlv8mCVnEFBnPRjoLdvKgjvLL NmL9DKtCt2lSi3zYl5yv0WWlYR+4K52C4bPV6AJ48+4dvR7HAAvffL1M18VseWo2D8oz /3jNmGfXeS0TJGBj1qZCzrEI8QGP5t7JodpfQR6Ij1/IStzBDH7D5+Vm2Lj+oBqoMbU0 glpuMeUCHpaGY0HIho1ht5jAr4FCP4Ymj4O/X41EhNoqP7bvFX/uGG2nZHRn5i9eAbgP R4BA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=awDZuFVi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:28 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 39/41] hw/arm/virt: Use VIRT_GIC_VERSION_* enum values in create_gic() Date: Fri, 8 Apr 2022 15:15:48 +0100 Message-Id: <20220408141550.1271295-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Everywhere we need to check which GIC version we're using, we look at vms->gic_version and use the VIRT_GIC_VERSION_* enum values, except in create_gic(), which copies vms->gic_version into a local 'int' variable and makes direct comparisons against values 2 and 3. For consistency, change this function to check the GIC version the same way we do elsewhere. This includes not implicitly relying on the enumeration type values happening to match the integer 'revision' values the GIC device object wants. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/arm/virt.c | 31 +++++++++++++++++++++++-------- 1 file changed, 23 insertions(+), 8 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index d2e5ecd234a..594a3d0660a 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -690,14 +690,29 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem) /* We create a standalone GIC */ SysBusDevice *gicbusdev; const char *gictype; - int type = vms->gic_version, i; + int i; unsigned int smp_cpus = ms->smp.cpus; uint32_t nb_redist_regions = 0; + int revision; - gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); + if (vms->gic_version == VIRT_GIC_VERSION_2) { + gictype = gic_class_name(); + } else { + gictype = gicv3_class_name(); + } + switch (vms->gic_version) { + case VIRT_GIC_VERSION_2: + revision = 2; + break; + case VIRT_GIC_VERSION_3: + revision = 3; + break; + default: + g_assert_not_reached(); + } vms->gic = qdev_new(gictype); - qdev_prop_set_uint32(vms->gic, "revision", type); + qdev_prop_set_uint32(vms->gic, "revision", revision); qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); /* Note that the num-irq property counts both internal and external * interrupts; there are always 32 of the former (mandated by GIC spec). @@ -707,7 +722,7 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem) qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); } - if (type == 3) { + if (vms->gic_version == VIRT_GIC_VERSION_3) { uint32_t redist0_capacity = vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); @@ -742,7 +757,7 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem) gicbusdev = SYS_BUS_DEVICE(vms->gic); sysbus_realize_and_unref(gicbusdev, &error_fatal); sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); - if (type == 3) { + if (vms->gic_version == VIRT_GIC_VERSION_3) { sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); if (nb_redist_regions == 2) { sysbus_mmio_map(gicbusdev, 2, @@ -780,7 +795,7 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem) ppibase + timer_irq[irq])); } - if (type == 3) { + if (vms->gic_version == VIRT_GIC_VERSION_3) { qemu_irq irq = qdev_get_gpio_in(vms->gic, ppibase + ARCH_GIC_MAINT_IRQ); qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", @@ -806,9 +821,9 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem) fdt_add_gic_node(vms); - if (type == 3 && vms->its) { + if (vms->gic_version == VIRT_GIC_VERSION_3 && vms->its) { create_its(vms); - } else if (type == 2) { + } else if (vms->gic_version == VIRT_GIC_VERSION_2) { create_v2m(vms); } } From patchwork Fri Apr 8 14:15:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558842 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp387750map; Fri, 8 Apr 2022 07:47:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJztvNZrqVLID9SXeimytDJbnfIhqp0NCmWs5JAqgVAPK9VwFwGFoKnonRhiNk6OSWi3Ct2A X-Received: by 2002:a25:4e82:0:b0:633:68d7:b864 with SMTP id c124-20020a254e82000000b0063368d7b864mr14584240ybb.514.1649429243491; Fri, 08 Apr 2022 07:47:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649429243; cv=none; d=google.com; s=arc-20160816; b=EvejTcwhz5UA5e18J0uYEwCNv2sEqtS/W5j337lokB7tGxEY4jR8ZmxTGDuIB/itoj ocmOHsW+rKBc3ELi1wrbkN/Zz2kodeWdt1mFSraPCQEIsSF1cCJOBunyZtfG+Uz0LU6t NKs+IeOtDnkOpFEFoxiWG/DiUFndIeVY1AEOgwF1feCEkkIROxWNylANMlvXDQcijJYK d+CKvkjjte+ZDjaN7NH3qIgJled9BLlMSXTUTVSoMCVOJf910rayZ7A4jZPLlRvAnBfP NbASItWxuwND07GMP9BWkROhDmCWt2biGG5mn0lPCClOgrrGW4QStSEAD0TDPCJMaKHQ n7vg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5zSoEvcrQQwqi7GYc6f0O7/9jPr6MDaUmhyGqTfq6Ic=; b=i9eBpglqOAvgM1xVvEvYV1CaWHKEF04WQj6Y7pLQjjdl1sqK9VNh0FyBCVn+lM9kWQ ffpvyk9wbWj4bX3BufChQtPWU1C3CYQQ+pYP6mts+149826Pug3jrCY4zmvcbzfAMeEE C0NqW7f4PcOYDx9WncxNPkKeXSsWjXS9ak39so0LYARznF7oy35jknyEPFDqLwSh4fQa MRfxRoye2e7jqVr7CHVY8uwkzNmUo0M0OHyS47cYq2rEW5BTRO1+6ZJ7E5RdcXw0QB3c dNqlxzFH/Iw6ZudhrETtRWN2bPDSSVtz7rDe18GMS784mlruesPn+TnCpXH3RBKKTwKT wNNQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Pj1cJYTG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:29 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 40/41] hw/arm/virt: Abstract out calculation of redistributor region capacity Date: Fri, 8 Apr 2022 15:15:49 +0100 Message-Id: <20220408141550.1271295-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In several places in virt.c we calculate the number of redistributors that fit in a region of our memory map, which is the size of the region divided by the size of a single redistributor frame. For GICv4, the redistributor frame is a different size from that for GICv3. Abstract out the calculation of redistributor region capacity so that we have one place we need to change to handle GICv4 rather than several. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/virt.h | 9 +++++++-- hw/arm/virt.c | 11 ++++------- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 7e76ee26198..360463e6bfb 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -185,11 +185,16 @@ OBJECT_DECLARE_TYPE(VirtMachineState, VirtMachineClass, VIRT_MACHINE) void virt_acpi_setup(VirtMachineState *vms); bool virt_is_acpi_enabled(VirtMachineState *vms); +/* Return number of redistributors that fit in the specified region */ +static uint32_t virt_redist_capacity(VirtMachineState *vms, int region) +{ + return vms->memmap[region].size / GICV3_REDIST_SIZE; +} + /* Return the number of used redistributor regions */ static inline int virt_gicv3_redist_region_count(VirtMachineState *vms) { - uint32_t redist0_capacity = - vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; + uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST); assert(vms->gic_version == VIRT_GIC_VERSION_3); diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 594a3d0660a..577c1e65188 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -723,8 +723,7 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem) } if (vms->gic_version == VIRT_GIC_VERSION_3) { - uint32_t redist0_capacity = - vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; + uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST); uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); nb_redist_regions = virt_gicv3_redist_region_count(vms); @@ -743,7 +742,7 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem) if (nb_redist_regions == 2) { uint32_t redist1_capacity = - vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; + virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", MIN(smp_cpus - redist0_count, redist1_capacity)); @@ -2048,10 +2047,8 @@ static void machvirt_init(MachineState *machine) * many redistributors we can fit into the memory map. */ if (vms->gic_version == VIRT_GIC_VERSION_3) { - virt_max_cpus = - vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; - virt_max_cpus += - vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; + virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST) + + virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); } else { virt_max_cpus = GIC_NCPU; } From patchwork Fri Apr 8 14:15:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558845 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp393004map; Fri, 8 Apr 2022 07:53:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx7bVAcroVFWh3vcpiJaNJeUzGm4RiT/CigWCxBZnFJTdVw9a7FC/lHmBoqSvB6yjtnVKdu X-Received: by 2002:a25:b7c4:0:b0:633:602d:daa6 with SMTP id u4-20020a25b7c4000000b00633602ddaa6mr13974778ybj.273.1649429635796; Fri, 08 Apr 2022 07:53:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649429635; cv=none; d=google.com; s=arc-20160816; b=ceu+aJwP/0QeuXNp2nmjMW4Qrmx0RDHlGO+86OuW1TE9VXZLJj3amknI8Vro3uuhGC 4cWR6rHCXxPDrorBwhCoSizgcVkx3ickCKrXKZSG/ICQPkPe9QMM590InprZK6KcUUV4 WtSf0yXem6RDW68IVj5JFkNj3A87LgM2+JUPyb8WzTQuGHleThAf2Tss8NyG+gdTJiA0 7NFWok1IIgMV/cs7b/vW9ivwvbs51XT5mbp1GM7EsCtPeh63YJ1mv+Enc6Fo9Vb+0mzY STcz2crqd6rHUDVtcOr4VUT0HYKNgZsXlKQLDJrs6cPeFIrGjkZ8cMKNAW6/ZipqQmlh qmPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=QiNb/fWTGwmLaiD1DUdHdEATfanLil6GCXqbm2UfHKk=; b=D8G1+DvVoQ95+vz7Z636VnlWeWQPEdczcasuO0VLQvBycolLcP6kjcGqAD0BBxPBxt cOnUr5yLaB6+8erBpSH4ZlGdze0VoFNKpABtg4BTy9VrsKJle2qpup9do70UsD3lFWdS GcoiwbnGRIdxT0t+nIEq5kekrVOgetQFLTh989f5j18tSpdnujuzSLi1BQoQX1bQtaD2 8AUwkHb4gz046NZwd37ok5SwmQR08Ehdv7cK8dSpLI5pk6hy+Uji75XMqWLtSgbSnQF7 0VhGqlHLiWnfUwRdWfEh4Y2krSjeRUPOrfzTZH9cV0BlR7dHdaUuJ0cVnVHS9o/+7ruK S2BA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yVHLooKa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:30 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 41/41] hw/arm/virt: Support TCG GICv4 Date: Fri, 8 Apr 2022 15:15:50 +0100 Message-Id: <20220408141550.1271295-42-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add support for the TCG GICv4 to the virt board. For the board, the GICv4 is very similar to the GICv3, with the only difference being the size of the redistributor frame. The changes here are thus: * calculating virt_redist_capacity correctly for GICv4 * changing various places which were "if GICv3" to be "if not GICv2" * the commandline option handling Note that using GICv4 reduces the maximum possible number of CPUs on the virt board from 512 to 317, because we can now only fit half as many redistributors into the redistributor regions we have defined. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- docs/system/arm/virt.rst | 5 ++- include/hw/arm/virt.h | 12 +++++-- hw/arm/virt.c | 70 ++++++++++++++++++++++++++++++---------- 3 files changed, 67 insertions(+), 20 deletions(-) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 1544632b674..5d13ec2798a 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -99,11 +99,14 @@ gic-version GICv2 ``3`` GICv3 + ``4`` + GICv4 (requires ``virtualization`` to be ``on``) ``host`` Use the same GIC version the host provides, when using KVM ``max`` Use the best GIC version possible (same as host when using KVM; - currently same as ``3``` for TCG, but this may change in future) + with TCG this is currently ``3`` if ``virtualization`` is ``off`` and + ``4`` if ``virtualization`` is ``on``, but this may change in future) its Set ``on``/``off`` to enable/disable ITS instantiation. The default is ``on`` diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 360463e6bfb..15feabac63d 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -113,6 +113,7 @@ typedef enum VirtGICType { VIRT_GIC_VERSION_HOST, VIRT_GIC_VERSION_2, VIRT_GIC_VERSION_3, + VIRT_GIC_VERSION_4, VIRT_GIC_VERSION_NOSEL, } VirtGICType; @@ -188,7 +189,14 @@ bool virt_is_acpi_enabled(VirtMachineState *vms); /* Return number of redistributors that fit in the specified region */ static uint32_t virt_redist_capacity(VirtMachineState *vms, int region) { - return vms->memmap[region].size / GICV3_REDIST_SIZE; + uint32_t redist_size; + + if (vms->gic_version == VIRT_GIC_VERSION_3) { + redist_size = GICV3_REDIST_SIZE; + } else { + redist_size = GICV4_REDIST_SIZE; + } + return vms->memmap[region].size / redist_size; } /* Return the number of used redistributor regions */ @@ -196,7 +204,7 @@ static inline int virt_gicv3_redist_region_count(VirtMachineState *vms) { uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST); - assert(vms->gic_version == VIRT_GIC_VERSION_3); + assert(vms->gic_version != VIRT_GIC_VERSION_2); return (MACHINE(vms)->smp.cpus > redist0_capacity && vms->highmem_redists) ? 2 : 1; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 577c1e65188..dfedc6b22ee 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -522,7 +522,7 @@ static void fdt_add_gic_node(VirtMachineState *vms) qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); - if (vms->gic_version == VIRT_GIC_VERSION_3) { + if (vms->gic_version != VIRT_GIC_VERSION_2) { int nb_redist_regions = virt_gicv3_redist_region_count(vms); qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", @@ -708,6 +708,9 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem) case VIRT_GIC_VERSION_3: revision = 3; break; + case VIRT_GIC_VERSION_4: + revision = 4; + break; default: g_assert_not_reached(); } @@ -722,7 +725,7 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem) qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); } - if (vms->gic_version == VIRT_GIC_VERSION_3) { + if (vms->gic_version != VIRT_GIC_VERSION_2) { uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST); uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); @@ -756,7 +759,7 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem) gicbusdev = SYS_BUS_DEVICE(vms->gic); sysbus_realize_and_unref(gicbusdev, &error_fatal); sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); - if (vms->gic_version == VIRT_GIC_VERSION_3) { + if (vms->gic_version != VIRT_GIC_VERSION_2) { sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); if (nb_redist_regions == 2) { sysbus_mmio_map(gicbusdev, 2, @@ -794,7 +797,7 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem) ppibase + timer_irq[irq])); } - if (vms->gic_version == VIRT_GIC_VERSION_3) { + if (vms->gic_version != VIRT_GIC_VERSION_2) { qemu_irq irq = qdev_get_gpio_in(vms->gic, ppibase + ARCH_GIC_MAINT_IRQ); qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", @@ -820,7 +823,7 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem) fdt_add_gic_node(vms); - if (vms->gic_version == VIRT_GIC_VERSION_3 && vms->its) { + if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) { create_its(vms); } else if (vms->gic_version == VIRT_GIC_VERSION_2) { create_v2m(vms); @@ -1672,10 +1675,10 @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) * purposes are to make TCG consistent (with 64-bit KVM hosts) * and to improve SGI efficiency. */ - if (vms->gic_version == VIRT_GIC_VERSION_3) { - clustersz = GICV3_TARGETLIST_BITS; - } else { + if (vms->gic_version == VIRT_GIC_VERSION_2) { clustersz = GIC_TARGETLIST_BITS; + } else { + clustersz = GICV3_TARGETLIST_BITS; } } return arm_cpu_mp_affinity(idx, clustersz); @@ -1808,6 +1811,10 @@ static void finalize_gic_version(VirtMachineState *vms) error_report( "gic-version=3 is not supported with kernel-irqchip=off"); exit(1); + case VIRT_GIC_VERSION_4: + error_report( + "gic-version=4 is not supported with kernel-irqchip=off"); + exit(1); } } @@ -1845,6 +1852,9 @@ static void finalize_gic_version(VirtMachineState *vms) case VIRT_GIC_VERSION_2: case VIRT_GIC_VERSION_3: break; + case VIRT_GIC_VERSION_4: + error_report("gic-version=4 is not supported with KVM"); + exit(1); } /* Check chosen version is effectively supported by the host */ @@ -1868,7 +1878,12 @@ static void finalize_gic_version(VirtMachineState *vms) case VIRT_GIC_VERSION_MAX: if (module_object_class_by_name("arm-gicv3")) { /* CONFIG_ARM_GICV3_TCG was set */ - vms->gic_version = VIRT_GIC_VERSION_3; + if (vms->virt) { + /* GICv4 only makes sense if CPU has EL2 */ + vms->gic_version = VIRT_GIC_VERSION_4; + } else { + vms->gic_version = VIRT_GIC_VERSION_3; + } } else { vms->gic_version = VIRT_GIC_VERSION_2; } @@ -1876,6 +1891,12 @@ static void finalize_gic_version(VirtMachineState *vms) case VIRT_GIC_VERSION_HOST: error_report("gic-version=host requires KVM"); exit(1); + case VIRT_GIC_VERSION_4: + if (!vms->virt) { + error_report("gic-version=4 requires virtualization enabled"); + exit(1); + } + break; case VIRT_GIC_VERSION_2: case VIRT_GIC_VERSION_3: break; @@ -2043,14 +2064,16 @@ static void machvirt_init(MachineState *machine) vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; } - /* The maximum number of CPUs depends on the GIC version, or on how - * many redistributors we can fit into the memory map. + /* + * The maximum number of CPUs depends on the GIC version, or on how + * many redistributors we can fit into the memory map (which in turn + * depends on whether this is a GICv3 or v4). */ - if (vms->gic_version == VIRT_GIC_VERSION_3) { + if (vms->gic_version == VIRT_GIC_VERSION_2) { + virt_max_cpus = GIC_NCPU; + } else { virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST) + virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); - } else { - virt_max_cpus = GIC_NCPU; } if (max_cpus > virt_max_cpus) { @@ -2431,8 +2454,19 @@ static void virt_set_mte(Object *obj, bool value, Error **errp) static char *virt_get_gic_version(Object *obj, Error **errp) { VirtMachineState *vms = VIRT_MACHINE(obj); - const char *val = vms->gic_version == VIRT_GIC_VERSION_3 ? "3" : "2"; + const char *val; + switch (vms->gic_version) { + case VIRT_GIC_VERSION_4: + val = "4"; + break; + case VIRT_GIC_VERSION_3: + val = "3"; + break; + default: + val = "2"; + break; + } return g_strdup(val); } @@ -2440,7 +2474,9 @@ static void virt_set_gic_version(Object *obj, const char *value, Error **errp) { VirtMachineState *vms = VIRT_MACHINE(obj); - if (!strcmp(value, "3")) { + if (!strcmp(value, "4")) { + vms->gic_version = VIRT_GIC_VERSION_4; + } else if (!strcmp(value, "3")) { vms->gic_version = VIRT_GIC_VERSION_3; } else if (!strcmp(value, "2")) { vms->gic_version = VIRT_GIC_VERSION_2; @@ -2898,7 +2934,7 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) virt_set_gic_version); object_class_property_set_description(oc, "gic-version", "Set GIC version. " - "Valid values are 2, 3, host and max"); + "Valid values are 2, 3, 4, host and max"); object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu); object_class_property_set_description(oc, "iommu",