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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id a2si786683qvj.165.2018.12.13.07.03.37 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 07:03:38 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53118 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSWX-0003yR-EW for patch@linaro.org; Thu, 13 Dec 2018 10:03:37 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35840) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSO6-000415-9s for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:54:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXSO5-00076F-Gn for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:54:54 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:53506) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gXSO5-0006zA-5I for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:54:53 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gXSNy-0007FB-F6 for qemu-devel@nongnu.org; Thu, 13 Dec 2018 14:54:46 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 14:54:09 +0000 Message-Id: <20181213145445.17935-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213145445.17935-1-peter.maydell@linaro.org> References: <20181213145445.17935-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 01/37] hw: arm: musicpal: drop TYPE_WM8750 in object_property_set_link() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Li Qiang The third argument of object_property_set_link() is the name of property, not related with the QOM type name, using the constant string instead. Signed-off-by: Li Qiang Reviewed-by: Philippe Mathieu-Daudé Message-id: 1542880825-2604-1-git-send-email-liq3ea@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/musicpal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.19.2 diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index 9648b3af44e..726ae29394e 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -1696,7 +1696,7 @@ static void musicpal_init(MachineState *machine) dev = qdev_create(NULL, TYPE_MV88W8618_AUDIO); s = SYS_BUS_DEVICE(dev); object_property_set_link(OBJECT(dev), OBJECT(wm8750_dev), - TYPE_WM8750, NULL); + "wm8750", NULL); qdev_init_nofail(dev); sysbus_mmio_map(s, 0, MP_AUDIO_BASE); sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]); From patchwork Thu Dec 13 14:54:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153666 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp907899ljp; Thu, 13 Dec 2018 07:06:16 -0800 (PST) X-Google-Smtp-Source: AFSGD/XI1fse/Lu4DhY+rTPzHGxoqTx3R5H8PputKZwYYu2zoQjkOkp8YqFQpjMHncg1jo+LMZwJ X-Received: by 2002:aed:2ee5:: with SMTP id k92mr24922557qtd.304.1544713575937; Thu, 13 Dec 2018 07:06:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544713575; cv=none; d=google.com; s=arc-20160816; b=bevICF3Off+ZQufee4F1ps6rE1ZSvDxwyxz5k/3BNJgQ5zvY4fDx8nremoCj1zn3e9 P2MpG3ovICDL4990k0NTNSzt1M867NAbknrXzoil4x0GLYxxrYf1aoRMlNp4jBy/HDTa EqsHkwCn1rPGxrf3cSPQsdoB0RE+fCxNP7Bt5PcjJugDcUTzEBL9wmMAN6Qp+tXU/88p 5vMVcYrYUyb72n9mmf+tojONSgSXfqKgb0fQLYSj7pt9R+KIkML+PDREKpi/ET9zpShK iUNncy4xj/tpdAmS9/OG2ZtV17rR9QsmFa+MFcQG3hSNNzyTa1vHdJpGQ4EwHRUJ/qlj pcqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=fFpAQSNlR2rkTq1Ttjr9hQS9DIwgpX3a59+joYeymzw=; b=JmlA6O0Br5JzwYoj6V4f5bx8cBriQ62SAdGUNgQN2JjDy+Kiu+mFx9IK3G7QdLeXQT UCxpB0A5Mg5r09mZvC0pyBSZxm7ugAwUchZXKCgbH7ybC02pQ/r0nnsVXrgthEzJAM/6 dglrs199hjlhNgNUgd0sFVlKxeMYFAOCgava3cabeWAfldH4SaYcSngnt5cQETZEp8ZY x0yknZFrWFhqF14dvJZqGJd/GZDKWJZviPai48qr5sZACpgoxjGDxH1gto2wslfRelGQ uMf84I1QWEDewtozsQZOKUFLSBBlvHZFcf1YX08NJ2eLBnVszCt1rUwOnuNkJ9m3Weqp z6pQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id h14si1173807qvo.31.2018.12.13.07.06.15 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 07:06:15 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53129 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSZ5-0005Dc-CX for patch@linaro.org; Thu, 13 Dec 2018 10:06:15 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35807) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSO5-0003zu-9L for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:54:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXSO4-00073q-3y for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:54:53 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:53506) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gXSO3-0006zA-Ry for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:54:52 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gXSNy-0007FP-Vg for qemu-devel@nongnu.org; Thu, 13 Dec 2018 14:54:46 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 14:54:10 +0000 Message-Id: <20181213145445.17935-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213145445.17935-1-peter.maydell@linaro.org> References: <20181213145445.17935-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 02/37] Allow AArch64 processors to boot from a kernel placed over 4GB X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Ricardo Perez Blanco Architecturally, it's possible for an AArch64 machine to have all of its RAM over the 4GB mark, but our kernel/initrd loading code in boot.c assumes that the upper half of the addresses to load these images to is always zero. Write the whole 64 bit address into the bootloader code fragment, not just the low half. Note that, currently, none of the existing QEMU machines have their main memory over 4GBs, so this was not a user-visible bug. Signed-off-by: Ricardo Perez Blanco [PMM: revised commit message and tweaked some long lines] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/boot.c | 35 ++++++++++++++++++++++------------- 1 file changed, 22 insertions(+), 13 deletions(-) -- 2.19.2 diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 586baa9b647..94fce128028 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -63,8 +63,10 @@ typedef enum { FIXUP_TERMINATOR, /* end of insns */ FIXUP_BOARDID, /* overwrite with board ID number */ FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */ - FIXUP_ARGPTR, /* overwrite with pointer to kernel args */ - FIXUP_ENTRYPOINT, /* overwrite with kernel entry point */ + FIXUP_ARGPTR_LO, /* overwrite with pointer to kernel args */ + FIXUP_ARGPTR_HI, /* overwrite with pointer to kernel args (high half) */ + FIXUP_ENTRYPOINT_LO, /* overwrite with kernel entry point */ + FIXUP_ENTRYPOINT_HI, /* overwrite with kernel entry point (high half) */ FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */ FIXUP_BOOTREG, /* overwrite with boot register address */ FIXUP_DSB, /* overwrite with correct DSB insn for cpu */ @@ -83,10 +85,10 @@ static const ARMInsnFixup bootloader_aarch64[] = { { 0xaa1f03e3 }, /* mov x3, xzr */ { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */ { 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */ - { 0, FIXUP_ARGPTR }, /* arg: .word @DTB Lower 32-bits */ - { 0 }, /* .word @DTB Higher 32-bits */ - { 0, FIXUP_ENTRYPOINT }, /* entry: .word @Kernel Entry Lower 32-bits */ - { 0 }, /* .word @Kernel Entry Higher 32-bits */ + { 0, FIXUP_ARGPTR_LO }, /* arg: .word @DTB Lower 32-bits */ + { 0, FIXUP_ARGPTR_HI}, /* .word @DTB Higher 32-bits */ + { 0, FIXUP_ENTRYPOINT_LO }, /* entry: .word @Kernel Entry Lower 32-bits */ + { 0, FIXUP_ENTRYPOINT_HI }, /* .word @Kernel Entry Higher 32-bits */ { 0, FIXUP_TERMINATOR } }; @@ -106,8 +108,8 @@ static const ARMInsnFixup bootloader[] = { { 0xe59f2004 }, /* ldr r2, [pc, #4] */ { 0xe59ff004 }, /* ldr pc, [pc, #4] */ { 0, FIXUP_BOARDID }, - { 0, FIXUP_ARGPTR }, - { 0, FIXUP_ENTRYPOINT }, + { 0, FIXUP_ARGPTR_LO }, + { 0, FIXUP_ENTRYPOINT_LO }, { 0, FIXUP_TERMINATOR } }; @@ -174,8 +176,10 @@ static void write_bootloader(const char *name, hwaddr addr, break; case FIXUP_BOARDID: case FIXUP_BOARD_SETUP: - case FIXUP_ARGPTR: - case FIXUP_ENTRYPOINT: + case FIXUP_ARGPTR_LO: + case FIXUP_ARGPTR_HI: + case FIXUP_ENTRYPOINT_LO: + case FIXUP_ENTRYPOINT_HI: case FIXUP_GIC_CPU_IF: case FIXUP_BOOTREG: case FIXUP_DSB: @@ -1152,9 +1156,13 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) /* Place the DTB after the initrd in memory with alignment. */ info->dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, align); - fixupcontext[FIXUP_ARGPTR] = info->dtb_start; + fixupcontext[FIXUP_ARGPTR_LO] = info->dtb_start; + fixupcontext[FIXUP_ARGPTR_HI] = info->dtb_start >> 32; } else { - fixupcontext[FIXUP_ARGPTR] = info->loader_start + KERNEL_ARGS_ADDR; + fixupcontext[FIXUP_ARGPTR_LO] = + info->loader_start + KERNEL_ARGS_ADDR; + fixupcontext[FIXUP_ARGPTR_HI] = + (info->loader_start + KERNEL_ARGS_ADDR) >> 32; if (info->ram_size >= (1ULL << 32)) { error_report("RAM size must be less than 4GB to boot" " Linux kernel using ATAGS (try passing a device tree" @@ -1162,7 +1170,8 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) exit(1); } } - fixupcontext[FIXUP_ENTRYPOINT] = entry; + fixupcontext[FIXUP_ENTRYPOINT_LO] = entry; + fixupcontext[FIXUP_ENTRYPOINT_HI] = entry >> 32; write_bootloader("bootloader", info->loader_start, primary_loader, fixupcontext, as); From patchwork Thu Dec 13 14:54:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153656 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp897304ljp; Thu, 13 Dec 2018 06:57:51 -0800 (PST) X-Google-Smtp-Source: AFSGD/VzuF6XUOqG4iv8KxoOX4t7Utrd4YR4lvEIOA4F+z4YqowEhGkqLwdmk11U+qb65PTxCPxI X-Received: by 2002:aed:31c5:: with SMTP id 63mr24096024qth.385.1544713071764; Thu, 13 Dec 2018 06:57:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544713071; cv=none; d=google.com; s=arc-20160816; b=c/Mf8qyRbH/zN2DE5D2kLtsgquFFWx3+sb1DG39jeOgyzkvh93a92D3sDR4V631t3Z RrkHEsMQpQA/vO0hNhD+Wl34fBnHo1CbbR7j5xjaFFsk+8OyAEd6D/d37GWTuy1ES5y4 GwJLeGOOBx3+eUCGySMMw405PO9vHAWtP2Pcn6mw4Zr71fUM/bYh3upqubs2PKrQ4Z+t zt6/DRTAYcPah8cQzQE+lLfyzTZYHqU/OcvLHZQnVgFNr1VDTjARV4gH5oumk4LWoGTK 85Rsblr5k9lNeW9dXv4ehEaaReg6VCG/wucBWnoQsYxEXJu5M1lyOXmSMT9daqzuhprJ +xLw== ARC-Message-Signature: i=1; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id 14si1229964qka.176.2018.12.13.06.57.51 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 06:57:51 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53082 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSQx-0006P8-68 for patch@linaro.org; Thu, 13 Dec 2018 09:57:51 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35708) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSO2-0003vD-98 for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:54:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXSO1-0006zK-4c for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:54:50 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:53504) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gXSO0-0006w2-TY for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:54:49 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gXSNz-0007Fd-Eo for qemu-devel@nongnu.org; Thu, 13 Dec 2018 14:54:47 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 14:54:11 +0000 Message-Id: <20181213145445.17935-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213145445.17935-1-peter.maydell@linaro.org> References: <20181213145445.17935-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 03/37] musicpal: Convert sysbus init function to realize function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Mao Zhongyi Use DeviceClass rather than SysBusDeviceClass in mv88w8618_wlan_class_init(). Cc: jan.kiszka@web.de Cc: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org Signed-off-by: Mao Zhongyi Signed-off-by: Zhang Shengju Reviewed-by: Philippe Mathieu-Daudé Message-id: 20181130093852.20739-2-maozhongyi@cmss.chinamobile.com Signed-off-by: Peter Maydell --- hw/arm/musicpal.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) -- 2.19.2 diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index 726ae29394e..d22532a11c8 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -1147,14 +1147,13 @@ static const MemoryRegionOps mv88w8618_wlan_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -static int mv88w8618_wlan_init(SysBusDevice *dev) +static void mv88w8618_wlan_realize(DeviceState *dev, Error **errp) { MemoryRegion *iomem = g_new(MemoryRegion, 1); memory_region_init_io(iomem, OBJECT(dev), &mv88w8618_wlan_ops, NULL, "musicpal-wlan", MP_WLAN_SIZE); - sysbus_init_mmio(dev, iomem); - return 0; + sysbus_init_mmio(SYS_BUS_DEVICE(dev), iomem); } /* GPIO register offsets */ @@ -1720,9 +1719,9 @@ DEFINE_MACHINE("musicpal", musicpal_machine_init) static void mv88w8618_wlan_class_init(ObjectClass *klass, void *data) { - SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); - sdc->init = mv88w8618_wlan_init; + dc->realize = mv88w8618_wlan_realize; } static const TypeInfo mv88w8618_wlan_info = { From patchwork Thu Dec 13 14:54:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153663 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp903976ljp; Thu, 13 Dec 2018 07:03:16 -0800 (PST) X-Google-Smtp-Source: AFSGD/USrHsYuewHcs4eX2KA40NjOx/zqKpE3xBmPjXa9N3sr9bBaLbkTGqzc/qU7gbgdg+PxitY X-Received: by 2002:ae9:c20b:: with SMTP id j11mr23000809qkg.211.1544713396073; Thu, 13 Dec 2018 07:03:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544713396; cv=none; d=google.com; s=arc-20160816; b=orG9ji9IAm7BN0HJ98DL7/Hy7yUkcRl0Tv16vCo9pohmACLBiEUs63l/XwoIk0CydK OPh8QYWfL0a99XGShKUC5SPI+4Gsj1umAoA9h/+7edpZPOjxK3Dv2LGCS6vzSIrO2TvP ftRdtqL1/ii/Okko5uM7xVw4rBVmQkVKUnCtNTK5n7KRt2bOPRXAlrO9/kAh2IswDtpp eQxfGLFcRL0l3XDa2rW+n13X+1aSRSUsJOK5ZNJaLBONa+AwlTtQxMk08THT6btp7rbb 7THW/EcLZqHSPA/6EdpW6NvQ5+C+j1HhGTugQl8e/y2kR8AUrx2FkgHQrTPS4U0qv3tz ivug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=euBjYJOhqI2jgD4oyuDY0rjo5vmU0zdYL6s5prFCxQQ=; b=0zofx1dIyRDQ0yly/uZHW3XapbSJF2uikGunRBHH10lnoLDRc6SIF1jj9dCvRF6ljC dtoLONp31n714FvLZIHXdTC7AqJGvXHqnXJsW3rjvQlCAtVlN/2rZrokuNjtm8FuaFZK iMw5jd4TF4HNVGlnfnbQC2Q27H70kzcgWLCwK5OKtsaP1D7W10twlY4D/iCAjwoFrDPw OtjDesaYEqx8aI0JXnHGJpTwYfxArkzwbnFxBZoDpM0WnPhg9COpSsmq5KRYp0eeMKdl HTRR8hWnYURuM535mwjQ4HdqU/Dzw2n7pmLFvcGMyfQQ69vmOQil9NCMfMNm8/KhL86s FmKA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 04/37] block/noenand: Convert sysbus init function to realize function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Mao Zhongyi Use DeviceClass rather than SysBusDeviceClass in onenand_class_init(). Cc: kwolf@redhat.com Cc: mreitz@redhat.com Cc: qemu-block@nongnu.org Signed-off-by: Mao Zhongyi Signed-off-by: Zhang Shengju Reviewed-by: Philippe Mathieu-Daudé Message-id: 20181130093852.20739-3-maozhongyi@cmss.chinamobile.com Signed-off-by: Peter Maydell --- hw/block/onenand.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) -- 2.19.2 diff --git a/hw/block/onenand.c b/hw/block/onenand.c index 2b48609776d..f11118a6876 100644 --- a/hw/block/onenand.c +++ b/hw/block/onenand.c @@ -772,9 +772,9 @@ static const MemoryRegionOps onenand_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -static int onenand_initfn(SysBusDevice *sbd) +static void onenand_realize(DeviceState *dev, Error **errp) { - DeviceState *dev = DEVICE(sbd); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); OneNANDState *s = ONE_NAND(dev); uint32_t size = 1 << (24 + ((s->id.dev >> 4) & 7)); void *ram; @@ -794,14 +794,14 @@ static int onenand_initfn(SysBusDevice *sbd) 0xff, size + (size >> 5)); } else { if (blk_is_read_only(s->blk)) { - error_report("Can't use a read-only drive"); - return -1; + error_setg(errp, "Can't use a read-only drive"); + return; } blk_set_perm(s->blk, BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE, BLK_PERM_ALL, &local_err); if (local_err) { - error_report_err(local_err); - return -1; + error_propagate(errp, local_err); + return; } s->blk_cur = s->blk; } @@ -826,7 +826,6 @@ static int onenand_initfn(SysBusDevice *sbd) | ((s->id.dev & 0xff) << 8) | (s->id.ver & 0xff), &vmstate_onenand, s); - return 0; } static Property onenand_properties[] = { @@ -841,9 +840,8 @@ static Property onenand_properties[] = { static void onenand_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); - SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); - k->init = onenand_initfn; + dc->realize = onenand_realize; dc->reset = onenand_system_reset; dc->props = onenand_properties; } From patchwork Thu Dec 13 14:54:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153657 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp897412ljp; Thu, 13 Dec 2018 06:57:59 -0800 (PST) X-Google-Smtp-Source: AFSGD/UQWGPRnTOlCUQK9e7n3CXNvLxoLy5S/cDl/7ShKsxBiPcR2sqNxpIFkA29TWzKTGGMhnB0 X-Received: by 2002:ac8:2ccc:: with SMTP id 12mr23976207qtx.277.1544713079680; Thu, 13 Dec 2018 06:57:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544713079; cv=none; d=google.com; s=arc-20160816; b=chEUNQdyusCrTnGf977Vy3waS9VUpBxfh8eTMkKlOzBRY9xeWS6nAG+vpQwFeMe8un XQgVPaHbRcACWptFDOPNiaEZEWI6HVJ1Jy7SC3WtIhv8PhMWIoCMaOAY5GVSuONQ9ZPP lVxuUpxrovGPGJLXDdpBpPWa1vuoJKERO81oLKLIxGl8SCDOLaWztWrmnK/ky4EkCQAI vgORJ0OFx6pJJwweKoh2cEqHDLb5WDPu2miif+B5SmkLdAcOoBOS7ZGhrSLpMmgZLNw/ jVOu1XEMdb30gSYVsrBXChR5H+NeKAu0gYrGtS5A14SnP8Uysja7wMZPa3HdEYTnUw8X lRwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=EyWK+sanN5X9FQH7hBlVY/Xiuh7z59m+2VCIC4f67/w=; b=prxwkHi3/TlW/CZcCpKkBtdGClT/HrAmaQ+PKbjLoMMuGUZL1sAgRjLf8lQOghZdKV QFA05L7qnr9Tiu34orBg1TdObnq43Gq/VYGqttzqs5ySVXMNrAK4ykE6pJbBr27j02NZ WN5gbIKytmxryQ4SwjHrtGFGrtEAfXC5pcurPjHKBlHP6QARm9FfLoqjPoKjDwArDMBa +MRXJZsfwzWDMN4bTC43qn8xkAnCk23iunFWIWGNnS2JFfZtVaK2MPLTB5CWVfan3ME9 CfxTLslawTf6/bv3tClWkrj8wbmGiszivDhL5DhyHI0GSTQvMQd5sKwim7SdKF2Px4JS T9EA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id t1si1266895qkj.73.2018.12.13.06.57.59 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 06:57:59 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53085 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSR5-0006Vh-3v for patch@linaro.org; Thu, 13 Dec 2018 09:57:59 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35726) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSO2-0003vc-QS for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:54:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXSO1-00070O-SX for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:54:50 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:53506) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gXSO1-0006zA-Iv for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:54:49 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gXSO0-0007G8-LD for qemu-devel@nongnu.org; Thu, 13 Dec 2018 14:54:48 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 14:54:13 +0000 Message-Id: <20181213145445.17935-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213145445.17935-1-peter.maydell@linaro.org> References: <20181213145445.17935-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 05/37] char/grlib_apbuart: Convert sysbus init function to realize function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Mao Zhongyi Use DeviceClass rather than SysBusDeviceClass in grlib_apbuart_class_init(). Cc: chouteau@adacore.com Cc: marcandre.lureau@redhat.com Cc: pbonzini@redhat.com Signed-off-by: Mao Zhongyi Signed-off-by: Zhang Shengju Reviewed-by: Philippe Mathieu-Daudé Message-id: 20181130093852.20739-4-maozhongyi@cmss.chinamobile.com Signed-off-by: Peter Maydell --- hw/char/grlib_apbuart.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) -- 2.19.2 diff --git a/hw/char/grlib_apbuart.c b/hw/char/grlib_apbuart.c index bac11bec58d..e1d258b6112 100644 --- a/hw/char/grlib_apbuart.c +++ b/hw/char/grlib_apbuart.c @@ -239,9 +239,10 @@ static const MemoryRegionOps grlib_apbuart_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -static int grlib_apbuart_init(SysBusDevice *dev) +static void grlib_apbuart_realize(DeviceState *dev, Error **errp) { UART *uart = GRLIB_APB_UART(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); qemu_chr_fe_set_handlers(&uart->chr, grlib_apbuart_can_receive, @@ -249,14 +250,12 @@ static int grlib_apbuart_init(SysBusDevice *dev) grlib_apbuart_event, NULL, uart, NULL, true); - sysbus_init_irq(dev, &uart->irq); + sysbus_init_irq(sbd, &uart->irq); memory_region_init_io(&uart->iomem, OBJECT(uart), &grlib_apbuart_ops, uart, "uart", UART_REG_SIZE); - sysbus_init_mmio(dev, &uart->iomem); - - return 0; + sysbus_init_mmio(sbd, &uart->iomem); } static void grlib_apbuart_reset(DeviceState *d) @@ -280,9 +279,8 @@ static Property grlib_apbuart_properties[] = { static void grlib_apbuart_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); - SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); - k->init = grlib_apbuart_init; + dc->realize = grlib_apbuart_realize; dc->reset = grlib_apbuart_reset; dc->props = grlib_apbuart_properties; } From patchwork Thu Dec 13 14:54:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153654 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp894878ljp; Thu, 13 Dec 2018 06:55:19 -0800 (PST) X-Google-Smtp-Source: AFSGD/XgqaKFFb95GK+QUmTwy0CvaJCbjrStetmY1m5jm5xx9iXRp8tVCjSSrzUH+txVCH8wVD7G X-Received: by 2002:ac8:892:: with SMTP id v18mr23796653qth.297.1544712919536; Thu, 13 Dec 2018 06:55:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544712919; cv=none; d=google.com; s=arc-20160816; b=JN5H1sQGqkFysDQTfq7y0OST0D/a7HZOlckSoB78/CEDaJwd9PcBNOEBDzVSpfw+GM wzA9f11qH3DUFVZOoN6HOHm5Yimyiunf/3RPEYOrClo374Frp5e8IX/Hm+egHSzkowVR mSNIyEF15uMyFkus8j2t3OnM3tqI73r+Et6FrgwmC3KG9NBPCPhdvCxoSRITE0sUk7aX 6u82BrlEDffZWW6vQMRHzHhhHWlBoU9Ag886P2HgUTY4MOJfbEWEWlU16cbs3XFwp469 mxnGfBKoUxtw+8CORfrS4IhlWxLSy4X8fZR/rc/jwsNV6Am2p7e1cI/HVzaLqmLIyIsC Qe+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=8NfuPQQf5LLxQUgZx02cM4vl9TSzH4yyUbLPCQ6m1cg=; b=SJx38XC4jc9Af/7vC86tTprvXgg64Do61ztMXN+W3W7EX2+SMNGiFFiZ8PSLrfWBDd /oilvK32zLgl7OJxlaQ3URMxLFeL267DU1a4+DXKwVTZhJsnL9OCXyjNetGEpNVRxcuy iMJYCm1tRLdwzXBzjltUeSlLBdqN3YEv7hHBLxFvq9Iv5GeGXIWGGtLyOWXIX24T+36O josDEiyvxiTKIjNsK0lT6lypCseT1+duQ9+b4XC+x0yhsGUADxxKomWm7mwrv35Alrom oOKqnh/xxcd8chZTHcckvf3INjCCRgwyUP5ymBcw3FA5oK0xzzTXf2W0miUIVI0H6jKM 9zmA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id p27si1043342qvf.190.2018.12.13.06.55.19 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 06:55:19 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53063 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSOU-000425-Vy for patch@linaro.org; Thu, 13 Dec 2018 09:55:19 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35783) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSO4-0003z7-JJ for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:54:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXSO3-00072y-DW for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:54:52 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:53504) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gXSO3-0006w2-30 for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:54:51 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gXSO1-0007GM-65 for qemu-devel@nongnu.org; Thu, 13 Dec 2018 14:54:49 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 14:54:14 +0000 Message-Id: <20181213145445.17935-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213145445.17935-1-peter.maydell@linaro.org> References: <20181213145445.17935-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 06/37] core/empty_slot: Convert sysbus init function to realize function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Mao Zhongyi Use DeviceClass rather than SysBusDeviceClass in empty_slot_class_init(). Signed-off-by: Mao Zhongyi Signed-off-by: Zhang Shengju Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20181130093852.20739-5-maozhongyi@cmss.chinamobile.com Signed-off-by: Peter Maydell --- hw/core/empty_slot.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) -- 2.19.2 diff --git a/hw/core/empty_slot.c b/hw/core/empty_slot.c index c1b9c2b1041..239f78e2a77 100644 --- a/hw/core/empty_slot.c +++ b/hw/core/empty_slot.c @@ -71,21 +71,20 @@ void empty_slot_init(hwaddr addr, uint64_t slot_size) } } -static int empty_slot_init1(SysBusDevice *dev) +static void empty_slot_realize(DeviceState *dev, Error **errp) { EmptySlot *s = EMPTY_SLOT(dev); memory_region_init_io(&s->iomem, OBJECT(s), &empty_slot_ops, s, "empty-slot", s->size); - sysbus_init_mmio(dev, &s->iomem); - return 0; + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); } static void empty_slot_class_init(ObjectClass *klass, void *data) { - SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); - k->init = empty_slot_init1; + dc->realize = empty_slot_realize; } static const TypeInfo empty_slot_info = { From patchwork Thu Dec 13 14:54:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153661 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp902114ljp; Thu, 13 Dec 2018 07:02:02 -0800 (PST) X-Google-Smtp-Source: AFSGD/Xwyueq+t9DV41eDOFXKxQjDhrajAo5nqz13aawFP7JamoqQa60AdO3B2eZ8ZhMEcDvYQvm X-Received: by 2002:a37:3388:: with SMTP id z130mr21225865qkz.51.1544713322385; Thu, 13 Dec 2018 07:02:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544713322; cv=none; d=google.com; s=arc-20160816; b=xAiiPLGvA3kkP9qufFMnlCSNvJxlBMhkp+QS2vGB5PhABrf3P8PA9lpP6XWXU93lP9 y4OLrYA076mMLhDraqHXogwLsRmDBdvZa6wtgMLC/bJYfhj91HW3Y5T3mYbdKsE1EAPN UfWaRAi16QWviBe6eB3dwYexznHSyzsNaHZl/EQJN2k2sUV6URdeJY/0nsQjowaCZdmj nZbyAGSaQb53ckztZDCb2SH0r1i6iByjzxiSo3YbLrGVveHpU2MMpgnYcZ+DhE0yreb3 FVWJo1CcLiqLHztKMw7GD7Rq7NjKfGhYIXZLmCcKA42l/IvWYXxXLbJjb39yAZk8TpIo U0gA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=VFiJKTKfNqfA6q0ppGzY8naF1E6X1Mh2vn8xH92g2Lo=; b=OVWBM6TcHNtfLI7cZzNCHpJjoGcEwCvz3EcqrBQXGzxsBTS4xDoWxvSAE4XokW6w5P g9F/DxW3By8vqT9qeybrOBwxqk0UpZfLZM1ByS4AKt9ig1PCVO+KMNNtTaYToQPXxlqg nwFdgg9U0bP7jtNk61zAyUorRN+BQZqhjfjYeoWw8UZn92QyN3Xc+LQwR0CUdqP2TZwY 5ZKAxo6eXvsOVB0M7Ac8Opb+KQaHUDLcDqaAgouQWN4WcZ8jAJLuZQoTlNlRj5SVCg18 27hlzW/f4SWafPJB7y62ay+1i3Is7SQKZ2Yo8YkKPNGTbjFRS5IFzoKL2PWkC/Iu9bJ0 0BBA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 07/37] display/g364fb: Convert sysbus init function to realize function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Mao Zhongyi Use DeviceClass rather than SysBusDeviceClass in g364fb_sysbus_class_init(). Cc: pbonzini@redhat.com Cc: kraxel@redhat.com Cc: f4bug@amsat.org Cc: alistair.francis@wdc.com Signed-off-by: Mao Zhongyi Signed-off-by: Zhang Shengju Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-id: 20181130093852.20739-6-maozhongyi@cmss.chinamobile.com Signed-off-by: Peter Maydell --- hw/display/g364fb.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) -- 2.19.2 diff --git a/hw/display/g364fb.c b/hw/display/g364fb.c index 8ad7e5d8242..3407adf98d2 100644 --- a/hw/display/g364fb.c +++ b/hw/display/g364fb.c @@ -489,18 +489,16 @@ typedef struct { G364State g364; } G364SysBusState; -static int g364fb_sysbus_init(SysBusDevice *sbd) +static void g364fb_sysbus_realize(DeviceState *dev, Error **errp) { - DeviceState *dev = DEVICE(sbd); G364SysBusState *sbs = G364(dev); G364State *s = &sbs->g364; + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); g364fb_init(dev, s); sysbus_init_irq(sbd, &s->irq); sysbus_init_mmio(sbd, &s->mem_ctrl); sysbus_init_mmio(sbd, &s->mem_vram); - - return 0; } static void g364fb_sysbus_reset(DeviceState *d) @@ -518,9 +516,8 @@ static Property g364fb_sysbus_properties[] = { static void g364fb_sysbus_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); - SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); - k->init = g364fb_sysbus_init; + dc->realize = g364fb_sysbus_realize; set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); dc->desc = "G364 framebuffer"; dc->reset = g364fb_sysbus_reset; From patchwork Thu Dec 13 14:54:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153659 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp898502ljp; Thu, 13 Dec 2018 06:59:04 -0800 (PST) X-Google-Smtp-Source: AFSGD/XsBQUnYYIXPgmVdRvVN630rqo8goqWzv+jukAX7RyH0Va6/+Sqhl9zBsYHdE/Y/V+sDlQz X-Received: by 2002:aed:2e86:: with SMTP id k6mr23242905qtd.292.1544713144703; Thu, 13 Dec 2018 06:59:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544713144; cv=none; d=google.com; s=arc-20160816; b=jaM22t3ITC5ZBMfj5hYt/skgkzeiCf1NIKp5/C4Un9UjDUfFEnnFvHjI/6RIX68LIu 6ESTOLEug0CdG3Es/uogOXBo+NtKzxlSHjYWNm2PnTpA7HFoygkps1s8FGtZ2MvwXIwb WUtBwdVqlIVQJ2F8LxEZwwrLXnrMzRo9Qjvo5SeYURn43RTKV4fSx/0BvXJL6rE8h1A9 CMWPipN7J9McLFmGlqBMU+5+nj8dKs8SaJDr7iGIue0t7K8ZN3EijOX2+wZDWaAa47VF jQyK5nfz9KG7yhPqTq2W5iKWGzsFegHwloCMICEbNe/wfwrk80QDEmjJ12gyS7Nvg1FM IHNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=On+017VhBH8HLy3os1CwkMG5VxFviKFtE81GGwsowLU=; b=SNGzdtrldxLnnapGEXNEBlZaNh/CHITPwzSnIE66KzH0m6jVx+XuduFrcuCl8vTie9 XOft5zegMV5b21Rg1J4lO2WAds6zPQZ4MPn41Cd8r5fud9WDLFVGjPclWIyUnjSpFQQM F4MbEo2T0sNX/tjcc4bBepxGNvoKvsVcrDeSV8VBYhK2mD+utHF9/iXC0Sa0vD7kM+1r CaDYo8wid4vowvpELaaitw5bir8kHDdRACbSTa7SxWWgp21Dvx2hCr0FOUD2P7664vhV cEJUEArhRKTZU919hVbhOF52q8QwMkQ67wtaxp79wXmvb5TYfMBoMJmLPf5m4haPQaWO 4ezw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id l6si1132149qve.146.2018.12.13.06.59.04 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 06:59:04 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53090 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSS8-00087y-6V for patch@linaro.org; Thu, 13 Dec 2018 09:59:04 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35801) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSO5-0003zb-5B for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:54:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXSO3-00073L-L0 for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:54:52 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:53508) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gXSO3-00071P-C3 for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:54:51 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gXSO2-0007Gu-9J for qemu-devel@nongnu.org; Thu, 13 Dec 2018 14:54:50 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 14:54:16 +0000 Message-Id: <20181213145445.17935-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213145445.17935-1-peter.maydell@linaro.org> References: <20181213145445.17935-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 08/37] dma/puv3_dma: Convert sysbus init function to realize function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Mao Zhongyi Use DeviceClass rather than SysBusDeviceClass in puv3_dma_class_init(). Cc: gxt@mprc.pku.edu.cn Signed-off-by: Mao Zhongyi Signed-off-by: Zhang Shengju Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20181130093852.20739-7-maozhongyi@cmss.chinamobile.com Signed-off-by: Peter Maydell --- hw/dma/puv3_dma.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) -- 2.19.2 diff --git a/hw/dma/puv3_dma.c b/hw/dma/puv3_dma.c index b97a6c1767c..c89eade0292 100644 --- a/hw/dma/puv3_dma.c +++ b/hw/dma/puv3_dma.c @@ -76,7 +76,7 @@ static const MemoryRegionOps puv3_dma_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -static int puv3_dma_init(SysBusDevice *dev) +static void puv3_dma_realize(DeviceState *dev, Error **errp) { PUV3DMAState *s = PUV3_DMA(dev); int i; @@ -87,16 +87,14 @@ static int puv3_dma_init(SysBusDevice *dev) memory_region_init_io(&s->iomem, OBJECT(s), &puv3_dma_ops, s, "puv3_dma", PUV3_REGS_OFFSET); - sysbus_init_mmio(dev, &s->iomem); - - return 0; + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); } static void puv3_dma_class_init(ObjectClass *klass, void *data) { - SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); - sdc->init = puv3_dma_init; + dc->realize = puv3_dma_realize; } static const TypeInfo puv3_dma_info = { From patchwork Thu Dec 13 14:54:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153658 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp897422ljp; Thu, 13 Dec 2018 06:58:00 -0800 (PST) X-Google-Smtp-Source: AFSGD/UtKerbd9PxwdeummVuMZIP+UcExgRafdtoNrP8ICEqfj0XKS7UPBgH5/DlTkkkPBs1NwSJ X-Received: by 2002:a0c:da86:: with SMTP id z6mr23370371qvj.84.1544713080112; Thu, 13 Dec 2018 06:58:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544713080; cv=none; d=google.com; s=arc-20160816; b=VdLDFfn7/3vxyMot4RJjp8O59lSaRoxt986l49q4YYzzbPaEWXtDmUbdsVOCt+6jCc BZl3wqTT+EgAm/UriEJrUJv8oxZS5Svxe4hceqdDpag5RhBs9IrLjBZCMMMZLrjmCGAG URAiv+rjliEyP/07FMxkqawsjHcft1ewyijYFuVOLG5vypD7uI+Oi7cMJAu2PzFb6rd3 WiZmZKmf1i8kEoheLDLFm8oHG0LJfor2Pz+cLvEJoPsFNssbzGEvvVDIRejIrJrDd5et Tq5NctxrYa5e9tiOLiXIYI4lP6mjrhC9/Z9rqqA2pgunXUUpZds00OM7WsQQPJhnWtwq 6XGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=onALX4shB8Cj54MaKd8Q9LNXRKkz2xn2sWwDHwZShfk=; b=0MFMhX5I/6EkHGH8NgGe93fwokceAFt4VpVY/kCXeuq70Ec/N9MgxypBf/tISFnI4X 28wKrN7+ZpkyYByIOJ0A8ssECjUxEtYLnXa9djXK61IoTUB6+lw+3MW8rqZMcvHfczdg /sEi80no1Ku/TLNNec//6gbsO65v24s0N1u8Rpaelt5lzQomUh+SL6VpIS8iXJ0vsdwB Zk7XwbgdoDEXhiiuyHNT6/9HP9kcLuPFM5sfcexKNl60NlPgA2U/ojG05nJ+tXB/fWjQ qgmKMt4FhhOYe4Vqevx3yzx/Ou1FPmMeUm2oXmu9yj3wm6X/qBKiniupBJsKGMl0I7ef da6g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id n20si1182794qvh.47.2018.12.13.06.57.59 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 06:58:00 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53086 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSR5-0006Vv-Fd for patch@linaro.org; Thu, 13 Dec 2018 09:57:59 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35812) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSO5-000407-Fl for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:54:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXSO4-00074Q-Hl for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:54:53 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:53504) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gXSO4-0006w2-7L for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:54:52 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gXSO2-0007HC-QL for qemu-devel@nongnu.org; Thu, 13 Dec 2018 14:54:50 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 14:54:17 +0000 Message-Id: <20181213145445.17935-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213145445.17935-1-peter.maydell@linaro.org> References: <20181213145445.17935-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 09/37] gpio/puv3_gpio: Convert sysbus init function to realize function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Mao Zhongyi Use DeviceClass rather than SysBusDeviceClass in puv3_gpio_class_init(). Cc: gxt@mprc.pku.edu.cn Cc: peter.maydell@linaro.org Signed-off-by: Mao Zhongyi Signed-off-by: Zhang Shengju Reviewed-by: Philippe Mathieu-Daudé Message-id: 20181130093852.20739-8-maozhongyi@cmss.chinamobile.com Signed-off-by: Peter Maydell --- hw/gpio/puv3_gpio.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) -- 2.19.2 diff --git a/hw/gpio/puv3_gpio.c b/hw/gpio/puv3_gpio.c index 445afccf9f5..33241b8564c 100644 --- a/hw/gpio/puv3_gpio.c +++ b/hw/gpio/puv3_gpio.c @@ -99,36 +99,35 @@ static const MemoryRegionOps puv3_gpio_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -static int puv3_gpio_init(SysBusDevice *dev) +static void puv3_gpio_realize(DeviceState *dev, Error **errp) { PUV3GPIOState *s = PUV3_GPIO(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); s->reg_GPLR = 0; s->reg_GPDR = 0; /* FIXME: these irqs not handled yet */ - sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW0]); - sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW1]); - sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW2]); - sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW3]); - sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW4]); - sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW5]); - sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW6]); - sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW7]); - sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOHIGH]); + sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW0]); + sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW1]); + sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW2]); + sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW3]); + sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW4]); + sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW5]); + sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW6]); + sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW7]); + sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOHIGH]); memory_region_init_io(&s->iomem, OBJECT(s), &puv3_gpio_ops, s, "puv3_gpio", PUV3_REGS_OFFSET); - sysbus_init_mmio(dev, &s->iomem); - - return 0; + sysbus_init_mmio(sbd, &s->iomem); } static void puv3_gpio_class_init(ObjectClass *klass, void *data) { - SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); - sdc->init = puv3_gpio_init; + dc->realize = puv3_gpio_realize; } static const TypeInfo puv3_gpio_info = { From patchwork Thu Dec 13 14:54:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153662 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp903770ljp; Thu, 13 Dec 2018 07:03:07 -0800 (PST) X-Google-Smtp-Source: AFSGD/UtFmqZ0YnwLB94zkAovU8/ouI/vnMTpW3kzIXuOmNH5999JIUeEjel/BP9jDzPzKVRFkks X-Received: by 2002:a0c:c212:: with SMTP id l18mr24066556qvh.75.1544713387629; Thu, 13 Dec 2018 07:03:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544713387; cv=none; d=google.com; s=arc-20160816; b=N/nCmsRAz7atwiQiwvnm4JaJM/ut3BGNhubv2M0jZASAH1+pinId4QyNPof9bpX+7d oVxaGGyrcK8qy/t+UcIDFITwuemLluNZ9ArcHHqUA7OmBYRRAMM2hTUC6yPGQEH+ghlc 08V7Ks0jhCSBoQxKz8L8FWnaH6JCSA6Bo3Ht0cfQIpHG7I/K3RTO9Jsi3n4Dw3WXLJsU p/7BrfU38w9gnZ1PYsRRAr9h+9f48ePCBLjJifbcs8KogjjFY7TfbQmNXLs6wn3ftjIr yAHNldHMNHXoJKscIAX+YcQw4NOST69gEZET6Y3xhc8A9qVlZViSBX8JqsezV5nR4fu4 yQJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=VtWC0weJ6RR5Cn5pn30GLVAAPvjCjTdOXMIxQXyRHzg=; b=cmn05QZyjw6MOxgK9Up6lONvl2LDNt7FY63e5uk8Uk9KDt4CrihRMzYkzJmRchV76O XpsngaUy4G8Gaxq6mCFH4VcuhZwZ665ZjNCUhtN2mpT7dPlpXTdONhjAP2gXzWDO/Y7A NRTxg+P7PgkHrdPXcaFmatTYeKheqBHrCH9mYaHV8+5m+YNzjFQCAKhg3kqw6eQDW1lb wWh20zlQiGEMrY4Ujk+oLPqIoeBI5wB1nMN2lLVcXzRqapGcNwtd3/qhSt4y5nVQcj2N py9m86zj42Nk7pS+TWeoX8mBpHBDKPWyPsLV7zLWLDMHZNPtWZ5cG5qTpVxLimIaLq4y HhSg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 10/37] milkymist-softusb: Convert sysbus init function to realize function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Mao Zhongyi Use DeviceClass rather than SysBusDeviceClass in milkymist_softusb_class_init(). Cc: michael@walle.cc Signed-off-by: Mao Zhongyi Signed-off-by: Zhang Shengju Reviewed-by: Philippe Mathieu-Daudé Message-id: 20181130093852.20739-9-maozhongyi@cmss.chinamobile.com Signed-off-by: Peter Maydell --- hw/input/milkymist-softusb.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) -- 2.19.2 diff --git a/hw/input/milkymist-softusb.c b/hw/input/milkymist-softusb.c index ef8f47cd834..8766a17d9e0 100644 --- a/hw/input/milkymist-softusb.c +++ b/hw/input/milkymist-softusb.c @@ -245,32 +245,31 @@ static void milkymist_softusb_reset(DeviceState *d) s->regs[R_CTRL] = CTRL_RESET; } -static int milkymist_softusb_init(SysBusDevice *dev) +static void milkymist_softusb_realize(DeviceState *dev, Error **errp) { MilkymistSoftUsbState *s = MILKYMIST_SOFTUSB(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); - sysbus_init_irq(dev, &s->irq); + sysbus_init_irq(sbd, &s->irq); memory_region_init_io(&s->regs_region, OBJECT(s), &softusb_mmio_ops, s, "milkymist-softusb", R_MAX * 4); - sysbus_init_mmio(dev, &s->regs_region); + sysbus_init_mmio(sbd, &s->regs_region); /* register pmem and dmem */ memory_region_init_ram_nomigrate(&s->pmem, OBJECT(s), "milkymist-softusb.pmem", s->pmem_size, &error_fatal); vmstate_register_ram_global(&s->pmem); s->pmem_ptr = memory_region_get_ram_ptr(&s->pmem); - sysbus_init_mmio(dev, &s->pmem); + sysbus_init_mmio(sbd, &s->pmem); memory_region_init_ram_nomigrate(&s->dmem, OBJECT(s), "milkymist-softusb.dmem", s->dmem_size, &error_fatal); vmstate_register_ram_global(&s->dmem); s->dmem_ptr = memory_region_get_ram_ptr(&s->dmem); - sysbus_init_mmio(dev, &s->dmem); + sysbus_init_mmio(sbd, &s->dmem); hid_init(&s->hid_kbd, HID_KEYBOARD, softusb_kbd_hid_datain); hid_init(&s->hid_mouse, HID_MOUSE, softusb_mouse_hid_datain); - - return 0; } static const VMStateDescription vmstate_milkymist_softusb = { @@ -296,9 +295,8 @@ static Property milkymist_softusb_properties[] = { static void milkymist_softusb_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); - SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); - k->init = milkymist_softusb_init; + dc->realize = milkymist_softusb_realize; dc->reset = milkymist_softusb_reset; dc->vmsd = &vmstate_milkymist_softusb; dc->props = milkymist_softusb_properties; From patchwork Thu Dec 13 14:54:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153660 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp900318ljp; Thu, 13 Dec 2018 07:00:41 -0800 (PST) X-Google-Smtp-Source: AFSGD/UjyDuS7LKH8/q2mfEdc4MCOy6tb6wp1jGxhHaH+exa0Gk9mR4Dia04VC2iQflZn0MBVfw5 X-Received: by 2002:ac8:1414:: with SMTP id k20mr24374395qtj.298.1544713241834; Thu, 13 Dec 2018 07:00:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544713241; cv=none; d=google.com; s=arc-20160816; b=bBR9Rve869XLiQ426UA8rXrWgUEXRosYGbkAB41YW97LXx64mMfP4gvKFk6rP8DAjT vBKZGvkPGfXNR6lbGPwKBwJirLZqgfAG2DqO+PkDcfmd9mMy4hIE+uSVe27juA7fQHEO 5wwzVeOPczxW1rJmFveclNrYeui6nCA7G7Pk2UVd5OwpfA5DlpN/PTtih49J+ImI/Q03 EnkL9VZjpNvL3AXKpPYZe2X0QWxB8E7c170YH53NmrGCLdSDOk8YtWS2UyfnWrU0EEM7 HA65C9WDe9D4ERar0ETjWhKixeku8MsC9iF/S1h3LeQWafJdVJ4zLdtdPYPWGxs2XQKE jb1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=oCCYyNhJO1hdNFFAKs9QfigNFVG59GLBISHOhrzwt+A=; b=VlgBuCtVHqzwIRxL89sOmzVFtWHhQOzZUNldOQsXoJ3OVwNRqV6khyV2gxrYbRzLxf AfqOhkUxKQ9x3uZEg1juM4wr2QM61SLOYSmD3hv3CFX/ZoXR7qU59cMR08r4xkyzuKoT V78QoxnlCHltbOktRrvmLMYjQK7MnszZ232jCsxMrgFyvsXuzyI9FFECJEzF8B49wStY EkcJ/sQfrNag9Aqu/Ewk7lUC7zA3k50LJFNB4n9isETxyKLtcxw2QUfXdIawC7GPQCT/ LQQbp1bkhYXnw/O66PQbnqxkU78iDNbdeNFQi8aaHx3ezB2ZYxB8Oc+vD+xVY/JdVCb7 H9ng== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 11/37] input/pl050: Convert sysbus init function to realize function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Mao Zhongyi Use DeviceClass rather than SysBusDeviceClass in pl050_class_init(). Cc: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org Signed-off-by: Mao Zhongyi Signed-off-by: Zhang Shengju Reviewed-by: Philippe Mathieu-Daudé Message-id: 20181130093852.20739-10-maozhongyi@cmss.chinamobile.com Signed-off-by: Peter Maydell --- hw/input/pl050.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) -- 2.19.2 diff --git a/hw/input/pl050.c b/hw/input/pl050.c index be9cd57b177..15bffbfcadb 100644 --- a/hw/input/pl050.c +++ b/hw/input/pl050.c @@ -139,19 +139,19 @@ static const MemoryRegionOps pl050_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -static int pl050_initfn(SysBusDevice *dev) +static void pl050_realize(DeviceState *dev, Error **errp) { PL050State *s = PL050(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); memory_region_init_io(&s->iomem, OBJECT(s), &pl050_ops, s, "pl050", 0x1000); - sysbus_init_mmio(dev, &s->iomem); - sysbus_init_irq(dev, &s->irq); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq); if (s->is_mouse) { s->dev = ps2_mouse_init(pl050_update, s); } else { s->dev = ps2_kbd_init(pl050_update, s); } - return 0; } static void pl050_keyboard_init(Object *obj) @@ -183,9 +183,8 @@ static const TypeInfo pl050_mouse_info = { static void pl050_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); - SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(oc); - sdc->init = pl050_initfn; + dc->realize = pl050_realize; dc->vmsd = &vmstate_pl050; } From patchwork Thu Dec 13 14:54:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153665 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp906291ljp; Thu, 13 Dec 2018 07:05:01 -0800 (PST) X-Google-Smtp-Source: AFSGD/Vb/2Mjs3s1sJE1n09ZkOqApwa7PAyhP5CA+xanWYNKOJtRndrSbD+onyMA9wRpSe8fDeNL X-Received: by 2002:a37:291:: with SMTP id v17mr22406248qkg.208.1544713501004; Thu, 13 Dec 2018 07:05:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544713501; cv=none; d=google.com; s=arc-20160816; b=q8rMUAHHFKtoLUbbHzrIoptay/1vdzm4PfB9Zk7/m8ZLaZGITkI05cJAJ1M20AnBJH N4u9dic7qhFqQBjEyqLPmmrzj5AI/jkaMVZALY8lZEwjOz1BldCUDe13oLBHG2453IUD AkLmLtAc7ptChQcTS7xJusuudfH8XWlJ71ioDO3MwZYj9Av2pALItLJAejT1kIoTq1K1 fz8G7U95FQOS/Hs7WYF50uD2uGI1TLEGcVjasRXHSxkyd1UFsbsJa5qhOggdSkimik/w tEiUlcl+whCYMgvilW6xunFipKchPf2kAeTtHiiKG+FQSV/ufLvnQEThm/66jhAk0h0O 9VxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=2Ah6M7qX1CgX3pKhxiTaYJizg/D2cxQJIlnmMtBUFdE=; b=lOYWf8VqZeNh9Eep6hX69NraFatIEblWdvojZxVJk8FPl7OonOIgz79gYNcFCq7suw xcJXqhAGapizqodaEnhifPrIG8QYIUd2Ctj8Z6ukIRjigolMs8fJkaQNLoaFmu1Id2pf 6MpTBTBN/gUyuMACz6DH2EeUuBjVW93XDHBrFicwbpy6DZVSIt2bMZQWiIl4N5aILDHQ V5Qaa4mha3E3P57lf5wemQlXv4YdE5CzWxI/ARhQGaQisSNDPcH4clri8pFHy6PuBAx+ 6SASS9JfActmfKiIDhlV9PXB6XUvhbDLwwoXleREZl7zGb22mRspR6sARh7gc8QNDUdu 7pRw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id a127si815187qkf.126.2018.12.13.07.05.00 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 07:05:00 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53126 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSXs-00054x-F0 for patch@linaro.org; Thu, 13 Dec 2018 10:05:00 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35902) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSOG-0004B5-G7 for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXSOF-0007Ie-QD for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:04 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:53508) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gXSOF-00071P-JN for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:03 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gXSO4-0007I4-KE for qemu-devel@nongnu.org; Thu, 13 Dec 2018 14:54:52 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 14:54:20 +0000 Message-Id: <20181213145445.17935-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213145445.17935-1-peter.maydell@linaro.org> References: <20181213145445.17935-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 12/37] intc/puv3_intc: Convert sysbus init function to realize function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Mao Zhongyi Use DeviceClass rather than SysBusDeviceClass in puv3_intc_class_init(). Cc: gxt@mprc.pku.edu.cn Signed-off-by: Mao Zhongyi Signed-off-by: Zhang Shengju Reviewed-by: Philippe Mathieu-Daudé Message-id: 20181130093852.20739-11-maozhongyi@cmss.chinamobile.com Signed-off-by: Peter Maydell --- hw/intc/puv3_intc.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) -- 2.19.2 diff --git a/hw/intc/puv3_intc.c b/hw/intc/puv3_intc.c index ef8488aacc4..69ddc8c19ab 100644 --- a/hw/intc/puv3_intc.c +++ b/hw/intc/puv3_intc.c @@ -101,10 +101,10 @@ static const MemoryRegionOps puv3_intc_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -static int puv3_intc_init(SysBusDevice *sbd) +static void puv3_intc_realize(DeviceState *dev, Error **errp) { - DeviceState *dev = DEVICE(sbd); PUV3INTCState *s = PUV3_INTC(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); qdev_init_gpio_in(dev, puv3_intc_handler, PUV3_IRQS_NR); sysbus_init_irq(sbd, &s->parent_irq); @@ -115,15 +115,12 @@ static int puv3_intc_init(SysBusDevice *sbd) memory_region_init_io(&s->iomem, OBJECT(s), &puv3_intc_ops, s, "puv3_intc", PUV3_REGS_OFFSET); sysbus_init_mmio(sbd, &s->iomem); - - return 0; } static void puv3_intc_class_init(ObjectClass *klass, void *data) { - SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); - - sdc->init = puv3_intc_init; + DeviceClass *dc = DEVICE_CLASS(klass); + dc->realize = puv3_intc_realize; } static const TypeInfo puv3_intc_info = { From patchwork Thu Dec 13 14:54:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153674 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp917190ljp; Thu, 13 Dec 2018 07:13:41 -0800 (PST) X-Google-Smtp-Source: AFSGD/XW0e1xNd2MAx/9r917Vfa9zzdk9F+K6sJN50BxS2eUM4vh93fJ1mPdpZ+IE2F3p/qahGMC X-Received: by 2002:a37:a942:: with SMTP id s63mr21580133qke.331.1544714021720; Thu, 13 Dec 2018 07:13:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544714021; cv=none; d=google.com; s=arc-20160816; b=JTbd6aeyqExQ5/5TJTqd05nTaa7HFslCHsk64tkO9AMP99gdGChqmc2NvQ+CUEgL2W 6NKcn/yGQMhFV8Qq1/vLQJuvot+OGqt72+MB4pg8TXiJP35q3eoYA/h4KXZMns5bbszq wwzrFzBoVRiSbjc3ymx+1YspdoBUEEZl2/XgTgLbd5A+Nz51zr9mTAKSIXHIluUFjT44 25iUuyJ37kwH3ILlu3o4auteuDhvSeCYeekU7x2Kma6boG250wu8A6DVqEoEZhEXZ5jp fL57afqWs5HAAs3U3a1F5vcXEEFS7bkOuavEvGvmTEX8980glr6B5tKw4frUYiWgCm+z +p9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=8Hqgs29B0uLnia6mtCX/lKApySY/FjLhZnTidN/v7ZU=; b=Q70PzO28bJySQPMVELSgx9n4trFVZpH1lP5XwxaLm89j/9DRDFV2UaB5DkCBqzV7Ex zIsNnZAQiqcQetAFmsl+0RqQJreaG1z1qEWRharZfj0EEgzZY7MaROTVPsabajx1J4fa 1PNIIS1hDUthPeTq1SPk18sb/aqxSH00MLDhsg5840+BeSlK4jce3bDvhyH4HUpYZBrA /fAdmM/o0wAqm/aphqdXnAIWZdBvcjexFwKfR5LyTi/vuMVvi5qV8edGj0KimGtG9CqZ X2Ko1wfzd8JD3caNpZD7mvFld7vf65ANzn1P5lvKxkRlH42wUAmkwBXHN5hokzLRdDJ7 ChRw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 13/37] milkymist-hpdmc: Convert sysbus init function to realize function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Mao Zhongyi Use DeviceClass rather than SysBusDeviceClass in milkymist_hpdmc_class_init(). Cc: gxt@mprc.pku.edu.cn Cc: michael@walle.cc Signed-off-by: Mao Zhongyi Signed-off-by: Zhang Shengju Reviewed-by: Philippe Mathieu-Daudé Message-id: 20181130093852.20739-12-maozhongyi@cmss.chinamobile.com Signed-off-by: Peter Maydell --- hw/misc/milkymist-hpdmc.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) -- 2.19.2 diff --git a/hw/misc/milkymist-hpdmc.c b/hw/misc/milkymist-hpdmc.c index e6140eec6ba..44dc0698ec8 100644 --- a/hw/misc/milkymist-hpdmc.c +++ b/hw/misc/milkymist-hpdmc.c @@ -129,15 +129,13 @@ static void milkymist_hpdmc_reset(DeviceState *d) | IODELAY_PLL2_LOCKED; } -static int milkymist_hpdmc_init(SysBusDevice *dev) +static void milkymist_hpdmc_realize(DeviceState *dev, Error **errp) { MilkymistHpdmcState *s = MILKYMIST_HPDMC(dev); memory_region_init_io(&s->regs_region, OBJECT(dev), &hpdmc_mmio_ops, s, "milkymist-hpdmc", R_MAX * 4); - sysbus_init_mmio(dev, &s->regs_region); - - return 0; + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->regs_region); } static const VMStateDescription vmstate_milkymist_hpdmc = { @@ -153,9 +151,8 @@ static const VMStateDescription vmstate_milkymist_hpdmc = { static void milkymist_hpdmc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); - SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); - k->init = milkymist_hpdmc_init; + dc->realize = milkymist_hpdmc_realize; dc->reset = milkymist_hpdmc_reset; dc->vmsd = &vmstate_milkymist_hpdmc; } From patchwork Thu Dec 13 14:54:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153686 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp931932ljp; Thu, 13 Dec 2018 07:26:15 -0800 (PST) X-Google-Smtp-Source: AFSGD/Xvs0x8pGD9jExkZj0t5a0rZ4No3GCw8tT9qMAHfzG/wMmWT47/OcFbfKfO5i+8vtrswyV5 X-Received: by 2002:ac8:3466:: with SMTP id v35mr23953125qtb.231.1544714774972; Thu, 13 Dec 2018 07:26:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544714774; cv=none; d=google.com; s=arc-20160816; b=ISC+tGiF+wpoFZmS1p5CVtdvsErqCluSEsyhTiL2g3GjmiIWxCwDm5yUtZNcvAY8+Q Evdj0LoDY1TpzVimJn+SD8GR/Rmv0aXwXSi3IOs5kIPLYaLmmuhYemnJyfQF/F7xL5k/ 0DVTlHobq/Yh3W8oJfNduwtRfPwCOCrgfnNTakYuM/O857SqMBj/9l8lN4kbJO+7ralL xFlbZ3vUcXBOEv4/zLP3H091AchTdYKtDucjtkD4tPaNefOMMUKtTD6Nn9rVzwzVeRwC qNGsTiZ0xtpe66KHWKSsRKtDPJXJsy+xYN0lcJcmXROSzZzGQ1YP6i9ajW7YaWxoDpFG iaYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=toLLu4PyIPqunTJU6VCQspykUGlrUQhGoxVfwLu+2Ps=; b=aE1LahscGkywl5IsfvIq/dhHPxNy023455wJiBch/AvTo8DmFwpv7N3PptT73irJls mh+fJCNXDY/8f9epKjBmY/sFd/XfHKnBtghCEYu0aFqe1/1V+ZeC0brelThqJ66tgcIa 3ZD9Q4k6tO+txK8bAoKeDzVUjIlIF5TU3WjQClEcPcSqe7tcQZSL4aPa0dFkTzeHfipj L5HWjfxZfiIToL7ZwKptRxcjtKvy+muVTafCrP0y5EiBqyd5VL//Oxnj+S3/IJ4gGtSf Sv7JdTuBPXgUH6dtnFPy3x9TmQCOEddHoiAKZJU28M8OkgQhPEUMkx1UblRzo+4M4Ges uvqA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id j35si1258229qtc.137.2018.12.13.07.26.14 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 07:26:14 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53255 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSsQ-00071g-BX for patch@linaro.org; Thu, 13 Dec 2018 10:26:14 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36699) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSPV-0005Qb-Te for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:56:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXSPV-0000lE-1l for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:56:21 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:53508) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gXSPU-00071P-QK for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:56:20 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gXSO5-0007IZ-QA for qemu-devel@nongnu.org; Thu, 13 Dec 2018 14:54:53 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 14:54:22 +0000 Message-Id: <20181213145445.17935-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213145445.17935-1-peter.maydell@linaro.org> References: <20181213145445.17935-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 14/37] milkymist-pfpu: Convert sysbus init function to realize function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Mao Zhongyi Use DeviceClass rather than SysBusDeviceClass in milkymist_pfpu_class_init(). Cc: michael@walle.cc Signed-off-by: Mao Zhongyi Signed-off-by: Zhang Shengju Reviewed-by: Philippe Mathieu-Daudé Message-id: 20181130093852.20739-13-maozhongyi@cmss.chinamobile.com Signed-off-by: Peter Maydell --- hw/misc/milkymist-pfpu.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) -- 2.19.2 diff --git a/hw/misc/milkymist-pfpu.c b/hw/misc/milkymist-pfpu.c index 86f5e383b0f..4a03c7ee637 100644 --- a/hw/misc/milkymist-pfpu.c +++ b/hw/misc/milkymist-pfpu.c @@ -497,17 +497,16 @@ static void milkymist_pfpu_reset(DeviceState *d) } } -static int milkymist_pfpu_init(SysBusDevice *dev) +static void milkymist_pfpu_realize(DeviceState *dev, Error **errp) { MilkymistPFPUState *s = MILKYMIST_PFPU(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); - sysbus_init_irq(dev, &s->irq); + sysbus_init_irq(sbd, &s->irq); memory_region_init_io(&s->regs_region, OBJECT(dev), &pfpu_mmio_ops, s, "milkymist-pfpu", MICROCODE_END * 4); - sysbus_init_mmio(dev, &s->regs_region); - - return 0; + sysbus_init_mmio(sbd, &s->regs_region); } static const VMStateDescription vmstate_milkymist_pfpu = { @@ -527,9 +526,8 @@ static const VMStateDescription vmstate_milkymist_pfpu = { static void milkymist_pfpu_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); - SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); - k->init = milkymist_pfpu_init; + dc->realize = milkymist_pfpu_realize; dc->reset = milkymist_pfpu_reset; dc->vmsd = &vmstate_milkymist_pfpu; } From patchwork Thu Dec 13 14:54:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153683 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp928107ljp; Thu, 13 Dec 2018 07:22:42 -0800 (PST) X-Google-Smtp-Source: AFSGD/VWAY4PudPiMN8255sOuqH1l0qH/szb1bKXoK8xorxrZF5ZmZbVEtsQbZeidNMEr7EKT0b2 X-Received: by 2002:ac8:13c5:: with SMTP id i5mr24602099qtj.365.1544714562697; Thu, 13 Dec 2018 07:22:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544714562; cv=none; d=google.com; s=arc-20160816; b=Mxs3KylwhsDx/4ZEAwToSLRuw30mG40S8ZgsoFTpEJaMzPa2ByqyCG9GZ+cb/dX8/U Tnuk15X1HlS5iql/G8eS2HI5R4CgjFk/8XTtRQQyE3e8fehQq7/Slr7zV1VaYHR2vls5 KJwEp4UDvWNsai2U9Xkpyq1vB2Jk6Uu5wlFmCe4W7ft49p9OQfXyRpI1FRFViWZpoEeo Z4O0V+OymAlzcCxux/pHCLsjfXzps8JyNvoaS2RRr+GE9y+i/0exb+rP3B2kdRXE14U7 z+qEfP/yZ4/wPvtEAwSgKhdHql9Oin5Rin7+IX1omkBgJNIyHXO8l13sUwC3+UdBKMWo YTzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=AYiLijUzs5+ibqmU6j0YVZs6cke6g2Cdh6InunnZj5g=; b=HIUr4VtJyWewLLlqEWhUdeFBvFFLTF3zus4iqkM0iFQScvLfHFzK83G7CKkW3uejza s9MjKOufokrM0rHrupaKaNcwIzguFMN1wdQhl7gPIZqVjWDIGTJodEkv6BODI4maz6jm CI35oj6DWl95hcYXWVAw3CPQPggT4+PYcuv6Q7pPHgnF0E3/FHzkEgUO2EasePfhyTdK MtglYAorCDRHpW9x2OoBMtlKh3y0RA1LBtIRXs0wgdgq3jXKrHKL+KpH7x3ASCLGRicS 4n3I2+02U1Lyt2XO+P1mvdwRgTm+N59I0IT2Je3Rir0B+mFEn7FjibnrcpMA/KjoNr+F K7bg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 15/37] puv3_pm.c: Convert sysbus init function to realize function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Mao Zhongyi Use DeviceClass rather than SysBusDeviceClass in puv3_pm_class_init(). Cc: gxt@mprc.pku.edu.cn Signed-off-by: Mao Zhongyi Signed-off-by: Zhang Shengju Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20181130093852.20739-14-maozhongyi@cmss.chinamobile.com Signed-off-by: Peter Maydell --- hw/misc/puv3_pm.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) -- 2.19.2 diff --git a/hw/misc/puv3_pm.c b/hw/misc/puv3_pm.c index 577cebaac78..afe191fbe1f 100644 --- a/hw/misc/puv3_pm.c +++ b/hw/misc/puv3_pm.c @@ -119,7 +119,7 @@ static const MemoryRegionOps puv3_pm_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -static int puv3_pm_init(SysBusDevice *dev) +static void puv3_pm_realize(DeviceState *dev, Error **errp) { PUV3PMState *s = PUV3_PM(dev); @@ -127,16 +127,14 @@ static int puv3_pm_init(SysBusDevice *dev) memory_region_init_io(&s->iomem, OBJECT(s), &puv3_pm_ops, s, "puv3_pm", PUV3_REGS_OFFSET); - sysbus_init_mmio(dev, &s->iomem); - - return 0; + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); } static void puv3_pm_class_init(ObjectClass *klass, void *data) { - SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); - sdc->init = puv3_pm_init; + dc->realize = puv3_pm_realize; } static const TypeInfo puv3_pm_info = { From patchwork Thu Dec 13 14:54:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153685 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp931013ljp; Thu, 13 Dec 2018 07:25:22 -0800 (PST) X-Google-Smtp-Source: AFSGD/WwNB6ymtSBY8IhGjofeDHVNrhar0xmrea8q2kzj6h4sRSZ0p33+O2aSTWgRtDNWuUqB1vp X-Received: by 2002:ac8:738e:: with SMTP id t14mr24041162qtp.283.1544714721943; Thu, 13 Dec 2018 07:25:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544714721; cv=none; d=google.com; s=arc-20160816; b=Z8Fl8kFqqPGkmj5weaca5Remfv7aOZw7fQnkA8jh7CJrTYSdHaoUOvErxtGZnFjYnV WFrQAe32zofC/KjXkQibvT72+eZ1+pNCom7/L9gLTgJDzPxQgriB8krdE9FkX9NUdBqL 3k0RyscJD2APD2kOj5fDjD1BY1Xlncv0ZSIXeTAaZyUrN1jhbxSCo4ulAINCNA2zYsfY Y1snNelxel0rgMw0Wah0HZ+tSm1sah7C1dL2G4Zp5bXbpu6cbpSiqV1IkStkzbtI7mti 24BJ6Q1E0HHjq/R+WRt6lZxXOSsCZl95F3HSGyTrpg5tXrYNU5cWrnp46vJHgTFVrtf/ aQMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=Blse9F07cDIRB9nGRs4crMu0o5t1lNVy29LTOFfHAF8=; b=CvxyHfjy8hN0RfK4hW/4RuzVb8eGwU3rMSexKEkxzRYaWp2WOrb89/cMfnGpkunueu Sv8LjE4rn50fZLqWrdDuvlOeFyCvym/0SIG0tz63/Spdm2nDrC/OvF49yZIvd1kINFXa iL7U33NGDU85RoAZi7D5BlV0tFhqOkpvV1B3z+xYFdFL8WalP1WfxKUxJ4Kf00vJ62gq shFgvuBKRSsftpBtc+Qu4qeWQabM3So/rg+crF9xLau/oxhkXQNsxPbRdYGmDrRUoeqK nGq3g2GiQPjwIl4CiMEs8lWg+e27GjfkRWvCyT5468a7JB2XJyzjsxZp7UT/BKUkVN7H n8Qg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 16/37] nvram/ds1225y: Convert sysbus init function to realize function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Mao Zhongyi Use DeviceClass rather than SysBusDeviceClass in nvram_sysbus_class_init(). Cc: pbonzini@redhat.com Cc: marcandre.lureau@redhat.com Signed-off-by: Mao Zhongyi Signed-off-by: Zhang Shengju Reviewed-by: Philippe Mathieu-Daudé Message-id: 20181130093852.20739-15-maozhongyi@cmss.chinamobile.com Signed-off-by: Peter Maydell --- hw/nvram/ds1225y.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) -- 2.19.2 diff --git a/hw/nvram/ds1225y.c b/hw/nvram/ds1225y.c index ad7345f2882..b6ef463db0a 100644 --- a/hw/nvram/ds1225y.c +++ b/hw/nvram/ds1225y.c @@ -25,6 +25,7 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" #include "trace.h" +#include "qemu/error-report.h" typedef struct { MemoryRegion iomem; @@ -113,7 +114,7 @@ typedef struct { NvRamState nvram; } SysBusNvRamState; -static int nvram_sysbus_initfn(SysBusDevice *dev) +static void nvram_sysbus_realize(DeviceState *dev, Error **errp) { SysBusNvRamState *sys = DS1225Y(dev); NvRamState *s = &sys->nvram; @@ -123,20 +124,18 @@ static int nvram_sysbus_initfn(SysBusDevice *dev) memory_region_init_io(&s->iomem, OBJECT(s), &nvram_ops, s, "nvram", s->chip_size); - sysbus_init_mmio(dev, &s->iomem); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); /* Read current file */ file = s->filename ? fopen(s->filename, "rb") : NULL; if (file) { /* Read nvram contents */ if (fread(s->contents, s->chip_size, 1, file) != 1) { - printf("nvram_sysbus_initfn: short read\n"); + error_report("nvram_sysbus_realize: short read"); } fclose(file); } nvram_post_load(s, 0); - - return 0; } static Property nvram_sysbus_properties[] = { @@ -148,9 +147,8 @@ static Property nvram_sysbus_properties[] = { static void nvram_sysbus_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); - SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); - k->init = nvram_sysbus_initfn; + dc->realize = nvram_sysbus_realize; dc->vmsd = &vmstate_nvram; dc->props = nvram_sysbus_properties; } From patchwork Thu Dec 13 14:54:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153682 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp927527ljp; Thu, 13 Dec 2018 07:22:14 -0800 (PST) X-Google-Smtp-Source: AFSGD/Uz/z89AkDJogONSEFu/6fhqFtuy7dLTkjUl7Rqsjjg2OA0seemMHXYzqWXShaEYpq1T1zM X-Received: by 2002:ac8:31ed:: with SMTP id i42mr23747309qte.323.1544714533933; Thu, 13 Dec 2018 07:22:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544714533; cv=none; d=google.com; s=arc-20160816; b=Pw2L9apsbXXeyHCXHvh2j+jYsxbbVZz6hzbD21GCkEYyEuO0Ikk/XiF+Q74UAfMUeL 7HaaWQ2XVZmama41gSyQKNMz/nbZ8Nrqc6po6zUUQjMdYiSytck95d5R0usM1Xq0Nnj0 K3EMTFzNnhuNtPKjZgOSCw2DlqL6tCxWlDQtFTfc7Iuh4oFGaWr/7jzX3FEfdYd2XoRs 5dFVo4vEH+UArJpg5QpnbFBql0i9miJsR104dLjaG81I03gJkRHl3g7E1r7YntHimJLN GdocBbrdi8sYsCWVmPaJBeTefyGGNFKnUJdRMb3X3MhbNWpZntUhDpT5hVHIRCSowtw+ gj/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=4VehUEAZprzH67BsV4OIm0Vb7ao/w7+9683Vu9KFNng=; b=029fNcPh3cZKvWbUaUyebbyuIWyBJU3PmurRw1wxuxPneMPkeeiB83iNBfNn0RL0UB tyAVLTyK/0wHvFrtNSExsWMSLWgBRAGWoH3+r+pzZnvEuFymMEXD/7dTwsPECiY8HZe0 e1I2+RXU3eiewDzxCr/yuI6vVohYfzkCoOHUCXc0M10c7jHkh5rsTXJf1A8jPXUijHdS ru7ujPLsfJucfoGvjFUNbdDtY277jCemND3LVt+UGuUas5FMs+poLo74U57yCSAa/JMO 4Um3TkBNipnMAfAOX82VCiwnp7VPU53hymkLnQbYUGv8+PsU/1buDCJpIz8dUpmACg6a Ke8w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 17/37] pci-bridge/dec: Convert sysbus init function to realize function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Mao Zhongyi Use DeviceClass rather than SysBusDeviceClass in pci_dec_21154_device_class_init(). Cc: david@gibson.dropbear.id.au Cc: mst@redhat.com Cc: marcel.apfelbaum@gmail.com Cc: qemu-ppc@nongnu.org Signed-off-by: Mao Zhongyi Signed-off-by: Zhang Shengju Reviewed-by: David Gibson Acked-by: David Gibson Message-id: 20181130093852.20739-16-maozhongyi@cmss.chinamobile.com Signed-off-by: Peter Maydell --- hw/pci-bridge/dec.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) -- 2.19.2 diff --git a/hw/pci-bridge/dec.c b/hw/pci-bridge/dec.c index 84492d5e5f9..8484bfd4345 100644 --- a/hw/pci-bridge/dec.c +++ b/hw/pci-bridge/dec.c @@ -98,9 +98,10 @@ PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devfn) return pci_bridge_get_sec_bus(br); } -static int pci_dec_21154_device_init(SysBusDevice *dev) +static void pci_dec_21154_device_realize(DeviceState *dev, Error **errp) { PCIHostState *phb; + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); phb = PCI_HOST_BRIDGE(dev); @@ -108,9 +109,8 @@ static int pci_dec_21154_device_init(SysBusDevice *dev) dev, "pci-conf-idx", 0x1000); memory_region_init_io(&phb->data_mem, OBJECT(dev), &pci_host_data_le_ops, dev, "pci-data-idx", 0x1000); - sysbus_init_mmio(dev, &phb->conf_mem); - sysbus_init_mmio(dev, &phb->data_mem); - return 0; + sysbus_init_mmio(sbd, &phb->conf_mem); + sysbus_init_mmio(sbd, &phb->data_mem); } static void dec_21154_pci_host_realize(PCIDevice *d, Error **errp) @@ -150,9 +150,9 @@ static const TypeInfo dec_21154_pci_host_info = { static void pci_dec_21154_device_class_init(ObjectClass *klass, void *data) { - SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); - sdc->init = pci_dec_21154_device_init; + dc->realize = pci_dec_21154_device_realize; } static const TypeInfo pci_dec_21154_device_info = { From patchwork Thu Dec 13 14:54:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153693 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp944951ljp; Thu, 13 Dec 2018 07:38:43 -0800 (PST) X-Google-Smtp-Source: AFSGD/VImhMKpo6531BGI9DtjoSKL3favOvXAJmWM0xJFkw1TLYLkeG5aVTo6/KaLeF+/odMozlw X-Received: by 2002:a0c:d065:: with SMTP id d34mr23051445qvh.209.1544715523377; Thu, 13 Dec 2018 07:38:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544715523; cv=none; d=google.com; s=arc-20160816; b=qYXHvwJ6BrzYRpDJUIlDCfOVMhJ5TzaVZhJ9zE9ApG31BmIZqdbhhyw8aCG8UlZnSn xDS2fOvCLNugt/iKczdN+2+rTbERFPkf2xO3g/Cz1KDgIftd6Fm7VsEeSUDRngYIsuaG gTRL/8kVcNyu4nfaCkEHAA6f9umSKGgo6Qq5DHhsglZ1cyYt/RhckthRUND8UbviR2C1 H3fXskM/GxpV8+QRRud+O+TvluYvtlgVf6kHXHtLuuQqC1r0+58f7iyaPtAi5s2whB+C PcNbZC+dVsBIXDxQKeQPPB8hgZEmtLt4wD4U+zSQUS84AqiZsd1HgVCVij784Z1EJQDT aUEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=rtO2pDI+05A5wOuT3IWOefesImlEPjQG71gjbGxldsA=; b=JpmLxAjsnvcesQCeWXs7LsuBicReVm0RGUPRtXiN8v/InJDTG8uXUUfeLiGvKzfxU3 ShRuVddUFpd8gE9pdjR6/X0urnuzJ3aMr1BS5Cfb07FddWQICHvqCER9CinUsicX9BVE mZAUCWexQDWOpY9rWDOXTEvsi4oLDtc1C3xR8heh+ahjFO2Krg5woCyWFpT6i0I8B/Em GWW4DF+s/Ha2LMWQuOtcqdK2PZscPnGlC2jZN8aAveq/vnxrYcwl/REMQqLHF7mmczbL R3m2g759WieYFAWQjSD4ZBupW7nsHqOuZTpa/PsnPm6KaQivWIsL2aJJznzs63PSunht E/MQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id f10si820696qvf.139.2018.12.13.07.38.43 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 07:38:43 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53341 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXT4U-0001wm-JB for patch@linaro.org; Thu, 13 Dec 2018 10:38:42 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36597) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSPN-0005Hg-2V for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:56:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXSPJ-0000Uh-II for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:56:11 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:53508) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gXSPJ-00071P-80 for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:56:09 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gXSO7-0007JW-Ql for qemu-devel@nongnu.org; Thu, 13 Dec 2018 14:54:55 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 14:54:26 +0000 Message-Id: <20181213145445.17935-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213145445.17935-1-peter.maydell@linaro.org> References: <20181213145445.17935-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 18/37] timer/etraxfs_timer: Convert sysbus init function to realize function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Mao Zhongyi Use DeviceClass rather than SysBusDeviceClass in etraxfs_timer_class_init(). Cc: edgar.iglesias@gmail.com Signed-off-by: Mao Zhongyi Signed-off-by: Zhang Shengju Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias Message-id: 20181130093852.20739-17-maozhongyi@cmss.chinamobile.com Signed-off-by: Peter Maydell --- hw/timer/etraxfs_timer.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) -- 2.19.2 diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c index d13bc30b2d6..2280914b1d7 100644 --- a/hw/timer/etraxfs_timer.c +++ b/hw/timer/etraxfs_timer.c @@ -315,9 +315,10 @@ static void etraxfs_timer_reset(void *opaque) qemu_irq_lower(t->irq); } -static int etraxfs_timer_init(SysBusDevice *dev) +static void etraxfs_timer_realize(DeviceState *dev, Error **errp) { ETRAXTimerState *t = ETRAX_TIMER(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); t->bh_t0 = qemu_bh_new(timer0_hit, t); t->bh_t1 = qemu_bh_new(timer1_hit, t); @@ -326,21 +327,20 @@ static int etraxfs_timer_init(SysBusDevice *dev) t->ptimer_t1 = ptimer_init(t->bh_t1, PTIMER_POLICY_DEFAULT); t->ptimer_wd = ptimer_init(t->bh_wd, PTIMER_POLICY_DEFAULT); - sysbus_init_irq(dev, &t->irq); - sysbus_init_irq(dev, &t->nmi); + sysbus_init_irq(sbd, &t->irq); + sysbus_init_irq(sbd, &t->nmi); memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, "etraxfs-timer", 0x5c); - sysbus_init_mmio(dev, &t->mmio); + sysbus_init_mmio(sbd, &t->mmio); qemu_register_reset(etraxfs_timer_reset, t); - return 0; } static void etraxfs_timer_class_init(ObjectClass *klass, void *data) { - SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); - sdc->init = etraxfs_timer_init; + dc->realize = etraxfs_timer_realize; } static const TypeInfo etraxfs_timer_info = { From patchwork Thu Dec 13 14:54:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153673 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp916975ljp; Thu, 13 Dec 2018 07:13:31 -0800 (PST) X-Google-Smtp-Source: AFSGD/VqscJoXtIkJDyR5eu2GI9BMq8DEWjuXn5Lh+MoHQcCI+zbRMb4ypfbSwmbLIEfiST09wkM X-Received: by 2002:a0c:8b64:: with SMTP id d36mr22936802qvc.233.1544714011696; Thu, 13 Dec 2018 07:13:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544714011; cv=none; d=google.com; s=arc-20160816; b=Qoa24UPFqwWmB9+rNQRH2yDHYll3HXUOD0PZqlAOAST3eoJlFDSDJQNO3jAMYfm4EY rHH2U611RefNm4NnCn+rSRg2UWrGJqbEs0B4YpAGvVqTyWwhz/Xr+Dqf3zc0lsA+y70S 7c9muHPzhVJkstGV8I93469TD/zScYP9NXJDNsR/AhEdNRSkH5UFAneiku3sp/hfsnsX goAYX2bTPdSGWoKEUdUZhhaU8BrTj24FqQABKxLnrcosyCoB9mqUkMItlcRHhedqJqQ2 S6DAu0fnBrBhWX4n+YsnEQBiXe3n4JDU9Rf9sYS/1AS2+MmLu33Bbf0/2+OHuaeLiZFG hfJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=uAb58HKMytWsQlW7TVl9trf9xZXUAplpYiEbAPccYZU=; b=yCirJX3FvHM+LWlSd2DfEVrMIRS8s0y1cwQFMbMXEOlMc4s8WxGjd1cR84J3HDox/7 4ggaK948LCWq9lHqNyfBGtLn3AYu6CoG/fF5rq+fLJ1yoInwomW08Hr0SqDBRxlDVjGi A+It4ambZ8UubTt+GwrjCpJzmokKI28pm+C9WGP49yDxuvglpGdfjYPJv4hcZ7hwxzbR LqW0SkWuOEXDskHUCOGSNETBd7M5IbJDve5+TodhefG2ErS5OkiqTZXLCKuKns03wNHr kzeCjDFs7YGehtuARH2MTJ5UR4+HdG8adqfOj2rkDLG7bgy/7boxyuwOCTr5KTPaubeL OdMA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id x71si1360202qkx.198.2018.12.13.07.13.31 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 07:13:31 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53177 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSg7-0004fJ-2f for patch@linaro.org; Thu, 13 Dec 2018 10:13:31 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36576) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSPJ-0005Ed-Fj for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:56:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXSPI-0000T1-GS for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:56:09 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:53512) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gXSPI-0007J5-7p for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:56:08 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gXSO8-0007Jk-Af for qemu-devel@nongnu.org; Thu, 13 Dec 2018 14:54:56 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 14:54:27 +0000 Message-Id: <20181213145445.17935-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213145445.17935-1-peter.maydell@linaro.org> References: <20181213145445.17935-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 19/37] timer/grlib_gptimer: Convert sysbus init function to realize function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Mao Zhongyi Use DeviceClass rather than SysBusDeviceClass in grlib_gptimer_class_init(). Cc: chouteau@adacore.com Signed-off-by: Mao Zhongyi Signed-off-by: Zhang Shengju Reviewed-by: Philippe Mathieu-Daudé Message-id: 20181130093852.20739-18-maozhongyi@cmss.chinamobile.com Signed-off-by: Peter Maydell --- hw/timer/grlib_gptimer.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) -- 2.19.2 diff --git a/hw/timer/grlib_gptimer.c b/hw/timer/grlib_gptimer.c index 4ed96e970a7..183eddc0737 100644 --- a/hw/timer/grlib_gptimer.c +++ b/hw/timer/grlib_gptimer.c @@ -347,10 +347,11 @@ static void grlib_gptimer_reset(DeviceState *d) } } -static int grlib_gptimer_init(SysBusDevice *dev) +static void grlib_gptimer_realize(DeviceState *dev, Error **errp) { GPTimerUnit *unit = GRLIB_GPTIMER(dev); unsigned int i; + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); assert(unit->nr_timers > 0); assert(unit->nr_timers <= GPTIMER_MAX_TIMERS); @@ -366,7 +367,7 @@ static int grlib_gptimer_init(SysBusDevice *dev) timer->id = i; /* One IRQ line for each timer */ - sysbus_init_irq(dev, &timer->irq); + sysbus_init_irq(sbd, &timer->irq); ptimer_set_freq(timer->ptimer, unit->freq_hz); } @@ -375,8 +376,7 @@ static int grlib_gptimer_init(SysBusDevice *dev) unit, "gptimer", UNIT_REG_SIZE + GPTIMER_REG_SIZE * unit->nr_timers); - sysbus_init_mmio(dev, &unit->iomem); - return 0; + sysbus_init_mmio(sbd, &unit->iomem); } static Property grlib_gptimer_properties[] = { @@ -389,9 +389,8 @@ static Property grlib_gptimer_properties[] = { static void grlib_gptimer_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); - SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); - k->init = grlib_gptimer_init; + dc->realize = grlib_gptimer_realize; dc->reset = grlib_gptimer_reset; dc->props = grlib_gptimer_properties; } From patchwork Thu Dec 13 14:54:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153677 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp920627ljp; Thu, 13 Dec 2018 07:16:27 -0800 (PST) X-Google-Smtp-Source: AFSGD/WPTIg3tIJb6WZqJ8On1BqU/EzzjhkRZgd1xo3VjftMKfKhWvadj+EmmuwgcLfU9a4HKEnk X-Received: by 2002:a0c:ba24:: with SMTP id w36mr23209113qvf.60.1544714187550; Thu, 13 Dec 2018 07:16:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544714187; cv=none; d=google.com; s=arc-20160816; b=SJtO99a14sdh+G35EOaVGN+oMdRyjzoCJy+THvqU02LeqfL13ma/D9FNcuWCbm8FOI E0sthmwoGZpcRGfkXne7Yqc0iEKZ3UvWEukHwji8d5HqvT35ZuFYeu4ZE6TTAVn4/ESH 3SmjJ776KJf141C80SAbM1jFlvHszjiDIg8XbT33YO6RcvtrgkC58aCGkjhk9yXt/KDW q+vlfPvEnZ03oeOtXAmdpgx8b76nB6QtaPOCtFnvQRC12lbOieqLcWQmbOOOmRe2j+Dn FjdyF7Xyp3Jps1yKKyckJ93brF4UB0okyy4X3kNe2zWWR4Ku9kRkL4FMONkCFR6u4MGE wTxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=0G5WFk4mncHBvlcOWYPQJU/K+jy52lROaITj6hyBKyc=; b=fOcT/RBQw25rFZeMKOdYoK1vKOi4fjJpoZ9XfhVA24LPOlj78c0q3c8NX7OrlTE5H7 9p3In3aX1wVGgpNghQxDBlwq3mHMxLD16F5dDkhULE5ZCG0p4FOh1OeT8/sK2eMgdcLG TYtj4seg28oea2xQ7mXyoh9G2fwo5AUSzHYLCOgLFNG2ksnHEUV+SRFGzwq9tUrxewis S/xv/FzY1r3w6IjC4cUFbzEo3YyYAJ/xf9clJevZYAUARKddhFUapOk3jZxIaN6Za6wb Je/fRbbItjPMXGQ0wrJs7uGVDyx8qea+5znFYiSmGqCU+El7D0fmzt06LHRm3/nYrjuz l3YQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id c41si469800qtk.178.2018.12.13.07.16.27 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 07:16:27 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53197 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSiw-0007GZ-Tv for patch@linaro.org; Thu, 13 Dec 2018 10:16:27 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36574) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSPJ-0005EW-Bl for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:56:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXSPI-0000Sq-Ey for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:56:09 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:53506) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gXSPI-0006zA-5y for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:56:08 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gXSO8-0007Jy-Qm for qemu-devel@nongnu.org; Thu, 13 Dec 2018 14:54:56 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 14:54:28 +0000 Message-Id: <20181213145445.17935-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213145445.17935-1-peter.maydell@linaro.org> References: <20181213145445.17935-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 20/37] timer/puv3_ost: Convert sysbus init function to realize function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Mao Zhongyi Use DeviceClass rather than SysBusDeviceClass in puv3_ost_class_init(). Cc: gxt@mprc.pku.edu.cn Signed-off-by: Mao Zhongyi Signed-off-by: Zhang Shengju Reviewed-by: Philippe Mathieu-Daudé Message-id: 20181130093852.20739-19-maozhongyi@cmss.chinamobile.com Signed-off-by: Peter Maydell --- hw/timer/puv3_ost.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) -- 2.19.2 diff --git a/hw/timer/puv3_ost.c b/hw/timer/puv3_ost.c index 0b3d717e608..3be58c7fdd7 100644 --- a/hw/timer/puv3_ost.c +++ b/hw/timer/puv3_ost.c @@ -113,16 +113,17 @@ static void puv3_ost_tick(void *opaque) } } -static int puv3_ost_init(SysBusDevice *dev) +static void puv3_ost_realize(DeviceState *dev, Error **errp) { PUV3OSTState *s = PUV3_OST(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); s->reg_OIER = 0; s->reg_OSSR = 0; s->reg_OSMR0 = 0; s->reg_OSCR = 0; - sysbus_init_irq(dev, &s->irq); + sysbus_init_irq(sbd, &s->irq); s->bh = qemu_bh_new(puv3_ost_tick, s); s->ptimer = ptimer_init(s->bh, PTIMER_POLICY_DEFAULT); @@ -130,16 +131,14 @@ static int puv3_ost_init(SysBusDevice *dev) memory_region_init_io(&s->iomem, OBJECT(s), &puv3_ost_ops, s, "puv3_ost", PUV3_REGS_OFFSET); - sysbus_init_mmio(dev, &s->iomem); - - return 0; + sysbus_init_mmio(sbd, &s->iomem); } static void puv3_ost_class_init(ObjectClass *klass, void *data) { - SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); - sdc->init = puv3_ost_init; + dc->realize = puv3_ost_realize; } static const TypeInfo puv3_ost_info = { From patchwork Thu Dec 13 14:54:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153671 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp912784ljp; Thu, 13 Dec 2018 07:10:10 -0800 (PST) X-Google-Smtp-Source: AFSGD/XA6uW6qdG2B1grODRti/bVV7t2z89O+sseCV/9tbi/9JZ9lVLwXsqBzWDm2J8gLaIe19qk X-Received: by 2002:a37:3293:: with SMTP id y141mr20789193qky.132.1544713810247; Thu, 13 Dec 2018 07:10:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544713810; cv=none; d=google.com; s=arc-20160816; b=QeM22K13LwWsvbJv3pnHYI2b+pWjSY3O8a9/yxJP7HixJf4ae9m8jj9dBXYw7zevSW nk07yHq8PpEsmYi3KkrWouBsOvlcAHfryITpFk8md9ZCxCZAbiMsGcboE8Cv81hvo1g8 EsqfRAfg08vLSOozurdZCnl07+uoeLwbDQHcBR4rMHZ5PewsE5uYbiT9PBmmbGY9lBsj vjDZP9QZnStK6gCrzvU/FJ7ZHIEwGgF9OjSEBcC6Ut50M2Yi4uoJyonkHr6nm06SfZWd y0TEKqvgQPK/efwqjiw0kFNQitPv2eWuWIhxSlK4IjkSG1pqsOv8SqmhfMJXJaK1H2FW VcgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=MB8qNLIwvFS8bThpYGmOJQ53W4bijM4iOsOA/4ZQnYw=; b=O/3aAihQ/n3M6RaOPY7+DaLwiHUdYNjbq85YP4Q0GZrdNHKL6t8BIKq+t14iVKXSH6 tdVKhUwHsCfaa3PQ7+OoTFcSqk/Gpc52bZS5XhBdQ2mLWYbmEb3bI3p5enLHANijppTc mt/sE0sDwgY/eS01V/eyj6a0dh+bBxLkk4AetnRT1QAAav8sKXF7Cg9J0D46z/nxFjUK 9tT8AJm6i3fxf8sijMoJBhDnMUpfkG8NSMH0Q4C/omkmVdmLTi47niOfDHod2fTg5xOc ojXEh6Z6MEaWhpNoSkwIzgj04GOCKrw8w/o7wfhM2S8VsXjQ5W1EfX7NygLhuDFDiHia RxDw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id m43si1204790qvm.77.2018.12.13.07.10.10 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 07:10:10 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53157 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXScr-00014h-LK for patch@linaro.org; Thu, 13 Dec 2018 10:10:09 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36602) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSPP-0005Jb-3K for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:56:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXSPG-0000Pz-60 for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:56:13 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:53510) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gXSPF-000747-So for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:56:06 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gXSO9-0007KC-Am for qemu-devel@nongnu.org; Thu, 13 Dec 2018 14:54:57 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 14:54:29 +0000 Message-Id: <20181213145445.17935-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213145445.17935-1-peter.maydell@linaro.org> References: <20181213145445.17935-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 21/37] usb/tusb6010: Convert sysbus init function to realize function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Mao Zhongyi Use DeviceClass rather than SysBusDeviceClass in tusb6010_class_init(). Cc: kraxel@redhat.com Signed-off-by: Mao Zhongyi Signed-off-by: Zhang Shengju Message-id: 20181130093852.20739-20-maozhongyi@cmss.chinamobile.com Signed-off-by: Peter Maydell --- hw/usb/tusb6010.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) -- 2.19.2 diff --git a/hw/usb/tusb6010.c b/hw/usb/tusb6010.c index a2128024c11..501706e2b29 100644 --- a/hw/usb/tusb6010.c +++ b/hw/usb/tusb6010.c @@ -808,10 +808,10 @@ static void tusb6010_reset(DeviceState *dev) musb_reset(s->musb); } -static int tusb6010_init(SysBusDevice *sbd) +static void tusb6010_realize(DeviceState *dev, Error **errp) { - DeviceState *dev = DEVICE(sbd); TUSBState *s = TUSB(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); s->otg_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tusb_otg_tick, s); s->pwr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tusb_power_tick, s); @@ -822,15 +822,13 @@ static int tusb6010_init(SysBusDevice *sbd) sysbus_init_irq(sbd, &s->irq); qdev_init_gpio_in(dev, tusb6010_irq, musb_irq_max + 1); s->musb = musb_init(dev, 1); - return 0; } static void tusb6010_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); - SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); - k->init = tusb6010_init; + dc->realize = tusb6010_realize; dc->reset = tusb6010_reset; } From patchwork Thu Dec 13 14:54:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153692 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp944597ljp; Thu, 13 Dec 2018 07:38:20 -0800 (PST) X-Google-Smtp-Source: AFSGD/VbLAcOftjng5d0bk2DyFd7OmS4R3X8ORBXL39Xm0kJuCMt3o3j4BW7jID5jj0nnt0GERaC X-Received: by 2002:a0c:80a8:: with SMTP id 37mr24030935qvb.191.1544715500224; Thu, 13 Dec 2018 07:38:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544715500; cv=none; d=google.com; s=arc-20160816; b=CaSjOn1MWkX02zD2qiDHLxOoAyASpeyG5hb+HunjH7f4vnwf+7UznzvxpxWq6uwn77 vCQ5fsG078zJC5kVU622QHFUfvnpyV+kQXV1s/yuiKGoJNIQGN2x9rY2q8MdsjU+SXti kx4k9eqsLvXOR0EeJynAZrx8kV715+C98rWewFN+5TEHGSfcpipODE//u333J6IQXymn /smpaMXst5dCwydGYhP3c2AJ3MEkOHepsAMoDCUz+I0M98kSpB2HExYGAFhtjmEYrXOJ VCacXLVrcE6hocVLXUOpy/WeVnX24pCTy2dLOnuxXwK05HhwslDb2Np8UpSPVZYnQ4sk aPqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=CKKn6USr7T/SVXSSx92msJhnWHHzJAmn3GpsTDROoTY=; b=AxtwOGbxyzGk61go6ZIV0sslQpDcRY66WjQyDj8l/A6rH9nh8i/J+68EmorFXyG75d hzyldM2GApJcM8mF2G9GPUj6L2CYzOt9siFv3Mm1leiPftEAPozxI6nZvVMcak1DheNS MqfZVz+xGbVlOmB8hkDZLV5iRcoFTaBMpWwr8A3dPOENhCVNJSUFrpL/kcphYwSpc2qN an7saEvBu97sUBHeqRw6JYVvenLy1eorcMxs/qrvUl40AyaAfUlyfWPSiI3rzCDj2Lmr qMAIiouqGcNMBgzcXIVmufkEcqNQIjV+8GMss0GvO7DK+m9D3H/8Rf6YW5kke7dpdaya gHZg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id s29si1302931qth.384.2018.12.13.07.38.20 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 07:38:20 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53334 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXT47-0000gC-N5 for patch@linaro.org; Thu, 13 Dec 2018 10:38:19 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36463) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSP9-00055q-Cz for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:56:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXSP8-00008f-FV for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:59 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:53508) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gXSP8-00071P-7R for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:58 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gXSO9-0007KQ-RI for qemu-devel@nongnu.org; Thu, 13 Dec 2018 14:54:57 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 14:54:30 +0000 Message-Id: <20181213145445.17935-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213145445.17935-1-peter.maydell@linaro.org> References: <20181213145445.17935-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 22/37] xen_backend: remove xen_sysdev_init() function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Mao Zhongyi The init function doesn't do anything at all, so we just omit it. Cc: sstabellini@kernel.org Cc: anthony.perard@citrix.com Cc: xen-devel@lists.xenproject.org Cc: peter.maydell@linaro.org Signed-off-by: Mao Zhongyi Signed-off-by: Zhang Shengju Acked-by: Anthony PERARD Message-id: 20181130093852.20739-21-maozhongyi@cmss.chinamobile.com Signed-off-by: Peter Maydell --- hw/xen/xen_backend.c | 7 ------- 1 file changed, 7 deletions(-) -- 2.19.2 diff --git a/hw/xen/xen_backend.c b/hw/xen/xen_backend.c index 9a8e8771eca..0bc6b1de60f 100644 --- a/hw/xen/xen_backend.c +++ b/hw/xen/xen_backend.c @@ -809,11 +809,6 @@ static const TypeInfo xensysbus_info = { } }; -static int xen_sysdev_init(SysBusDevice *dev) -{ - return 0; -} - static Property xen_sysdev_properties[] = { {/* end of property list */}, }; @@ -821,9 +816,7 @@ static Property xen_sysdev_properties[] = { static void xen_sysdev_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); - SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); - k->init = xen_sysdev_init; dc->props = xen_sysdev_properties; dc->bus_type = TYPE_XENSYSBUS; } From patchwork Thu Dec 13 14:54:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153670 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp912171ljp; Thu, 13 Dec 2018 07:09:39 -0800 (PST) X-Google-Smtp-Source: AFSGD/WoF3IQjo8zHg0OxyAs80qOHDTzt8vN07bg6IzEAex1/07fRPqraHy3sH3rkNrKyZYvgxgY X-Received: by 2002:a37:a942:: with SMTP id s63mr21564290qke.331.1544713779384; Thu, 13 Dec 2018 07:09:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544713779; cv=none; d=google.com; s=arc-20160816; b=jEYvx+A/matLLZvQn9l8kyYwyck5jYjXeFVK9D0fLOrVjFTIlY1SKpS/N6Kr9PQnxI q1VLXMyHS41laKJDVAbGwgMoR/pZZ6y5saIyIJomRE0kXhP7ZOaKjY/TO+o7L4SjlM83 bxJ2kUX3lwW026CJNZbcxcbqJ+Ng5T5xb3xJoqq2r9D0d2EyUut43tbKyabMLwEaIUKS vWmTSo9+cwKVYn4s6VpCAKogEhWZIPC12gxkjvcDbZyw4nHOa1Ko+tqL0EdcAFvRZhmZ oHlDnGIkll1R3z2MbcXaDOsRh926ligDOYcbE96qiG1Tx6uF1uxm4hga2P/z2dQgl0/a vB/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=ISlnx0tOOeUGpWkgrfjbD0R+QX4AoUXoXztXmMfA20E=; b=lInnqFbfcMiA9ci06rAK5Vg0p7geU7ePswmK+fnzArlzQgnZJGHNl6/pW4AVnJcJKr Q+WZ1gMlpU60zCy4Muz6CNJSl5mec/Glxz+4YjxYeiGr/x6719PhvTR0WSXC9c9akqh7 QOmXj/YO8mFPQvcVmMlrGAJbRq7/T9wUyyPSzEdAo5YN3xnhfeiRTTqBdv7U4H7fxi4T czha7nmpVajYYczp9ZJWo1iY55OHP4CqsxePZBF5E4ucTJxZQtWRuQC0LGu86G18WPWv iTjWdiZVnWmichlHZAb4LZRxLFB5xzJeIoH1Rtu+Oyon6mGH17Bv5sn0RUF/wce5DZ76 m8ew== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id r2si1163648qvn.10.2018.12.13.07.09.37 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 07:09:39 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53154 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXScL-0000Hq-I2 for patch@linaro.org; Thu, 13 Dec 2018 10:09:37 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36418) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSP7-000541-Jk for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXSP6-0008Us-HR for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:57 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:53506) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gXSP6-0006zA-8Q for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:56 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gXSOA-0007Ke-B8 for qemu-devel@nongnu.org; Thu, 13 Dec 2018 14:54:58 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 14:54:31 +0000 Message-Id: <20181213145445.17935-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213145445.17935-1-peter.maydell@linaro.org> References: <20181213145445.17935-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 23/37] core/sysbus: remove the SysBusDeviceClass::init path X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Mao Zhongyi Currently, all sysbus devices have been converted to realize(), so remove this path. Cc: ehabkost@redhat.com Cc: thuth@redhat.com Cc: pbonzini@redhat.com Cc: armbru@redhat.com Cc: peter.maydell@linaro.org Cc: richard.henderson@linaro.org Cc: alistair.francis@wdc.com Signed-off-by: Mao Zhongyi Signed-off-by: Zhang Shengju Message-id: 20181130093852.20739-22-maozhongyi@cmss.chinamobile.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/sysbus.h | 3 --- hw/core/sysbus.c | 15 +++++---------- 2 files changed, 5 insertions(+), 13 deletions(-) -- 2.19.2 diff --git a/include/hw/sysbus.h b/include/hw/sysbus.h index 0b59a3b8d60..1aedcf05c92 100644 --- a/include/hw/sysbus.h +++ b/include/hw/sysbus.h @@ -38,9 +38,6 @@ typedef struct SysBusDevice SysBusDevice; typedef struct SysBusDeviceClass { /*< private >*/ DeviceClass parent_class; - /*< public >*/ - - int (*init)(SysBusDevice *dev); /* * Let the sysbus device format its own non-PIO, non-MMIO unit address. diff --git a/hw/core/sysbus.c b/hw/core/sysbus.c index 7ac36ad3e70..9f9edbcab96 100644 --- a/hw/core/sysbus.c +++ b/hw/core/sysbus.c @@ -201,18 +201,13 @@ void sysbus_init_ioports(SysBusDevice *dev, uint32_t ioport, uint32_t size) } } -/* TODO remove once all sysbus devices have been converted to realize */ +/* The purpose of preserving this empty realize function + * is to prevent the parent_realize field of some subclasses + * from being set to NULL to break the normal init/realize + * of some devices. + */ static void sysbus_realize(DeviceState *dev, Error **errp) { - SysBusDevice *sd = SYS_BUS_DEVICE(dev); - SysBusDeviceClass *sbc = SYS_BUS_DEVICE_GET_CLASS(sd); - - if (!sbc->init) { - return; - } - if (sbc->init(sd) < 0) { - error_setg(errp, "Device initialization failed"); - } } DeviceState *sysbus_create_varargs(const char *name, From patchwork Thu Dec 13 14:54:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153680 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp924804ljp; Thu, 13 Dec 2018 07:19:52 -0800 (PST) X-Google-Smtp-Source: AFSGD/XsFAx+9M4Ga/v52lX0PIkjWvYip1bOdRH8fNmw3jbMBju30dirzzJQf/KA9laNR785fbPx X-Received: by 2002:ac8:1308:: with SMTP id e8mr13344790qtj.201.1544714392143; Thu, 13 Dec 2018 07:19:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544714392; cv=none; d=google.com; s=arc-20160816; b=xdfH7ZSlXHDIczyklHIePCjvFBRBgDeCPINqTENB68JkX3Vk5cCaKpjFS4wzbOog8T 7Wl6UjD9MiR9F/Ok8GzBmeRVFKnrsJjTWbOa3TXZSQU93vn8zwPUyWixL+z85oXAHjB3 k6x9IWxPotHss8yiiiUlHrXVRgFOYJ+H20x+6g0UUAX8U+0bxKnjmFgvLqmWzKYrNFGm k7g7UUwQLvid86iM+Z9eJMGzoUffnCKFsJ816zbP0A3gtPrTHp2OXYzjnw8wwZxpP6lT vuJViDXy7ebYVqD8+HNBxI8b6SBQsyPQO8QnnN3i+keZnvn6vnM4B9ym9nWKPrOt8FTN DBbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=jxWrXNpw90PF6R+gvHVEFraCDqGN9cwquYp7/8+v8r8=; b=EF5vaYN/ba/d1b8vmrDa5iVcfcPtANH7OvJx+xkPocTYJFshj+u9KUVW0TO60L7NWR pC6G+Dpq+U7b2tkNpbmAcl+7ZV14wP3jLhM+fMHxTgg25Gb7297N/IhBWPx/4o55yjd9 clw3+YbCr/8/9bB/U51V3HDXtdJ3l+lCSCJsziyo9tolHwp4Jx1WsHuRD208qoGXWwsz eNTtjA3GXOzHQKES+tH/AEMa7IqO2KjXSwiuh0Y3gZqzoA47R4DL0CseC5Q2pzWaPp/9 +GGvKuBb13McuClGKuXYQz1bJaJU3sul14fOLR7KpubMRcXCwZgB0ztlEBD6z4Nv4G4e amrQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id w7si1096797qte.36.2018.12.13.07.19.51 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 07:19:52 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53213 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSmE-0001Xd-TF for patch@linaro.org; Thu, 13 Dec 2018 10:19:50 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36457) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSP9-00055U-0s for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXSP7-00005m-6m for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:58 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:53512) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gXSP6-0007J5-U0 for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:57 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gXSOA-0007Ks-R9 for qemu-devel@nongnu.org; Thu, 13 Dec 2018 14:54:58 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 14:54:32 +0000 Message-Id: <20181213145445.17935-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213145445.17935-1-peter.maydell@linaro.org> References: <20181213145445.17935-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 24/37] hw/arm: versal: Remove bogus virtio-mmio creation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Remove bogus virtio-mmio creation. This was an accidental left-over an experiment. Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Reviewed-by: Luc Michel Message-id: 20181129163655.20370-2-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- hw/arm/xlnx-versal-virt.c | 1 - 1 file changed, 1 deletion(-) -- 2.19.2 diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index 1e31a3f4429..41b8d801c89 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -364,7 +364,6 @@ static void create_virtio_regions(VersalVirt *s) sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq); mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); memory_region_add_subregion(&s->soc.mr_ps, base, mr); - sysbus_create_simple("virtio-mmio", base, pic_irq); } for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) { From patchwork Thu Dec 13 14:54:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153690 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp939868ljp; Thu, 13 Dec 2018 07:33:48 -0800 (PST) X-Google-Smtp-Source: AFSGD/WFgUdmrjsG/LWO1GzL00KLWF6XlEthD6OwWpAG5vU4PiBBgHfr9rWHaXAtH4DzFLr1TqQ8 X-Received: by 2002:a37:291:: with SMTP id v17mr22517121qkg.208.1544715227998; Thu, 13 Dec 2018 07:33:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544715227; cv=none; d=google.com; s=arc-20160816; b=QNLFGWpSIXPeRGikX+6d6o1QsDHRQb5najasqHUFWGAOMcZmZfFwSVqPoZ+k3kkRwY q6abFjTKjhbBNUDAjMMvo8WFdVnfItTUXepeqkC3an2nzJDpvDNm09CAMmp5LI1Nsi50 5pWXYwq56ieGGmJ6ZTZ7HzDtbrNUGXHSZtpJ0QItNsmqUaJIbfyIx3Wd8/4Q9VeoqAur fG2lyL44R5xrBd23Od28GI4kgtD5djnklwT5WO08aFSOmruC16lAoRaCw7HHB0qC7esj ISL1BzERblM4B2agCmb5h/2jg4lIPvZO6nrjzkFJyp7D5RMMNlhqxjHt1n712Bt5mnm4 ZXyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=IKXxuYbgfvBRjwiqU2m65v7RqYumYW0BSEEcETyUXsc=; b=VtACQQlUOtXt/BM9kze438xxg6SRBdrCsigNvgl1tUArDrOMw65aXW5d0s233EphM2 6ln+G/ZHDWYnNXLAD3sZ+kozg4KUbdFWIMaCDXFXLap8cQ6iKc7nIYvFer+H9d0Me5g6 IAFtEFeLhW0EWRmLryzkEWrlTpDnFpzLKVb/RelwDJ3iFmk3v3EEyBEwBA3d73eJoAbe fjPgLJx17gliGZ/QjcR3KVCM2ITitj9ccSWnwcmgnv1/p0cm5qn8dORoev0ZOJ5cRSct YE6qFfg95DF8ddGoRM/0/adAyeCaJmSBnONnU0p4RFzgOmeBtRnNI5ucvvdyw+YrGWf9 0ZnA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 25/37] hw/arm: versal: Reduce number of virtio-mmio instances X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Reduce number of virtio-mmio instances. This is in preparation for correcting the interrupt setup for Versal. Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Message-id: 20181129163655.20370-3-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- hw/arm/xlnx-versal-virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.19.2 diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index 41b8d801c89..2ed6ee9934d 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -342,7 +342,7 @@ static void *versal_virt_get_dtb(const struct arm_boot_info *binfo, return board->fdt; } -#define NUM_VIRTIO_TRANSPORT 32 +#define NUM_VIRTIO_TRANSPORT 8 static void create_virtio_regions(VersalVirt *s) { int virtio_mmio_size = 0x200; From patchwork Thu Dec 13 14:54:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153689 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp937166ljp; Thu, 13 Dec 2018 07:31:20 -0800 (PST) X-Google-Smtp-Source: AFSGD/W9DIbAeGht4DNC+tcfBhxZGjLz78MBwcJCWXz53KiRiODxkFCr0oMxoCymaaReMijQYfJy X-Received: by 2002:a0c:a545:: with SMTP id y63mr23185390qvy.119.1544715080648; Thu, 13 Dec 2018 07:31:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544715080; cv=none; d=google.com; s=arc-20160816; b=varuSqh0jHSKENKDnOEVYsHCRnvRb0F5M2jlHqbtjJRoAkNXfaOhDzY4nzYzbhGX57 +gzkBnckdukPPmArjKL+FwJBi7Z+9H3SM2dM4OJ0i5fwLBMXQnKR4EtFdDYTdB53RTMO lt0CmzQDD1YUgAoxPh6dfGr+SfGUCfvHRBJUv6nYhzcPk7L1+sEZBnZV1QkQ9qQikkaF /47BUDi6NFD1v4Ug2Om2fBcgRmFzuFYQRN73y8a/VJqvhxlXErYthAGytzqe3rnyF9xq bJi5IqGhdlu1jPLEq3NBQMJuMnadpX/xvqQPw0v8EsB3WeuGcnuBq8f/YcTOPxpSzsNK a5aw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=xUeNoQDPnpheuA9e8+NaYBzrBrIbpAjGj0XG+BHVs9I=; b=nhS7J5FJY5u4xDOfI0HaxCMFJe8zEe/KNqmIw6KzQNR2fTm3nIt5i11+iyvjz4gFQp GUz6DaIEG42btyxPHzOVSfEvuamBS0RlKsEypzv79QAu5jURBi1ArsK86+iInGW9DYTh BUIJvaJo+CY8jwDRr08WcL+dBznPJVMAUCJw+iqxrZM9Lq2uGbY3cpBzY3AhIi3fmqLc RmvljMmwOFX2jrOYsstdD6N5CcWMPinzDGV4V8RpyzkkT/67ct2Q4V+UzgKvSX7SDXcj VdgJdIKEHIAFA/bn0L6afd3j/70Mpu7KHAiMsILUuBwYjZH5F1FxpCLWnl+S7OWHLDCC YmhQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 49si1231284qty.142.2018.12.13.07.31.20 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 07:31:20 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53288 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSxI-0003yR-Hm for patch@linaro.org; Thu, 13 Dec 2018 10:31:16 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36325) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSP0-0004vH-4b for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXSOw-0008HM-AY for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:48 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:53508) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gXSOu-00071P-Cn for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:44 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gXSOB-0007LK-R0 for qemu-devel@nongnu.org; Thu, 13 Dec 2018 14:54:59 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 14:54:34 +0000 Message-Id: <20181213145445.17935-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213145445.17935-1-peter.maydell@linaro.org> References: <20181213145445.17935-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 26/37] hw/arm: versal: Use IRQs 111 - 118 for virtio-mmio X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Use IRQs 111 - 118 for virtio-mmio. The interrupts we're currently using 160+ are not available in the Versal GIC. Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Message-id: 20181129163655.20370-4-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-versal.h | 6 +++--- hw/arm/xlnx-versal-virt.c | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) -- 2.19.2 diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 9da621e4b68..76fb9de3918 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -75,9 +75,9 @@ typedef struct Versal { #define VERSAL_GEM1_IRQ_0 58 #define VERSAL_GEM1_WAKE_IRQ_0 59 -/* Architecturally eserved IRQs suitable for virtualization. */ -#define VERSAL_RSVD_HIGH_IRQ_FIRST 160 -#define VERSAL_RSVD_HIGH_IRQ_LAST 255 +/* Architecturally reserved IRQs suitable for virtualization. */ +#define VERSAL_RSVD_IRQ_FIRST 111 +#define VERSAL_RSVD_IRQ_LAST 118 #define MM_TOP_RSVD 0xa0000000U #define MM_TOP_RSVD_SIZE 0x4000000 diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index 2ed6ee9934d..c6feeac532f 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -351,7 +351,7 @@ static void create_virtio_regions(VersalVirt *s) for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) { char *name = g_strdup_printf("virtio%d", i);; hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size; - int irq = VERSAL_RSVD_HIGH_IRQ_FIRST + i; + int irq = VERSAL_RSVD_IRQ_FIRST + i; MemoryRegion *mr; DeviceState *dev; qemu_irq pic_irq; @@ -368,7 +368,7 @@ static void create_virtio_regions(VersalVirt *s) for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) { hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size; - int irq = VERSAL_RSVD_HIGH_IRQ_FIRST + i; + int irq = VERSAL_RSVD_IRQ_FIRST + i; char *name = g_strdup_printf("/virtio_mmio@%" PRIx64, base); qemu_fdt_add_subnode(s->fdt, name); From patchwork Thu Dec 13 14:54:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153667 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp908457ljp; Thu, 13 Dec 2018 07:06:40 -0800 (PST) X-Google-Smtp-Source: AFSGD/W+Vvr2QIykqPcU4MbzNrZGDYs+IQzKPCB2uea6W+Rme4eC7Zat4HgfKefcx3+MlS8NsMOx X-Received: by 2002:a0c:a2c5:: with SMTP id g63mr23586816qva.52.1544713600186; Thu, 13 Dec 2018 07:06:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544713600; cv=none; d=google.com; s=arc-20160816; b=TOuEomDsmVAGpjeX1Jucf4RiBdYlNcNrX1/KxMO5keAe85W37s//5feRUDLiZHHiOH g+uPUeqoiBwoQn0MFdfWqUnzbGtEGYYpmO9LkNyRkWgBrODr0QP6ymByUAADQdbEdtKe kW5TyHfuiu7030h+a0sMvGZgkRB/p4biHJHUIQYNdEDDshRc4HYXn2ugGvZZ10KCFuLc j2wy32qIvSbtGyJO/x16u5/16KCEGoc6UL7Mw5iSSrDtzNrwDkAowXjwaYqgmWAQwj8l 229ReOqu6ycWE/ElIAZTa0WXYhyNZIuymcQBNyfK/Xl8FUWLbf7RZwf+XJI9QB0H8zke 4wsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=uxirh3rCnoLD8OtwkAEe/a3vovHXC7MhOUEI7JNdUAk=; b=uFtbWaa0h6zO9Db3kvYQ7qW+3b0VhTNeSwtwXO0fC7ltgGqdLU4v4fGfAhhx8j4/OY mAs1cuY3DbeMCIieIPyDXsKPnbJ7ccekMyfQ6EkJ5h9Te2y/RT2uWS0Ik2XCcuN3BGSO Or0eio/Up9JdvzNWk0yjwCwWGIlM/OqJgu7XHRqnlpOv3ob1Gb2dFoFNxOxZJqmlKgPa Dq8xt76lSUa9muKI4LlnfBxA1GQVyiSAChGftHVJdBULGkeR9z0liDrLqb3p2nzcRgDy DWG4Ihkuo1NqQkjguEzy314isa+S5BsBakfhUYePFknQThH/Ku/0pOiGF3YYX/3nV2aq UPaA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id y12si1206989qth.357.2018.12.13.07.06.39 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 07:06:40 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53138 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSZT-0006Ol-IW for patch@linaro.org; Thu, 13 Dec 2018 10:06:39 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36306) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSOy-0004tL-6m for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXSOu-0008FG-Hd for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:46 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:53506) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gXSOs-0006zA-HN for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:44 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gXSOC-0007LY-At for qemu-devel@nongnu.org; Thu, 13 Dec 2018 14:55:00 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 14:54:35 +0000 Message-Id: <20181213145445.17935-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213145445.17935-1-peter.maydell@linaro.org> References: <20181213145445.17935-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 27/37] hw/arm: versal: Correct the nr of IRQs to 192 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Correct the nr of IRQs to 192. Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Message-id: 20181129163655.20370-5-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-versal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.19.2 diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 76fb9de3918..ec7c859d08c 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -22,7 +22,7 @@ #define XLNX_VERSAL_NR_ACPUS 2 #define XLNX_VERSAL_NR_UARTS 2 #define XLNX_VERSAL_NR_GEMS 2 -#define XLNX_VERSAL_NR_IRQS 256 +#define XLNX_VERSAL_NR_IRQS 192 typedef struct Versal { /*< private >*/ From patchwork Thu Dec 13 14:54:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153688 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp934458ljp; Thu, 13 Dec 2018 07:28:50 -0800 (PST) X-Google-Smtp-Source: AFSGD/XOeZYc4dQQltyxpUkVqcNcUcd8ATzlRKFAbyEkQ5pCtbsCZLum/5TGaJ2Vsx/HUU/Mlht4 X-Received: by 2002:ae9:f40b:: with SMTP id y11mr22257774qkl.228.1544714930387; Thu, 13 Dec 2018 07:28:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544714930; cv=none; d=google.com; s=arc-20160816; b=LPkyuPZPCBwJmloiUNjffiw0BpqGDRXE907HzV5OmqAlL7uOZtja6rA94KNDmhsV16 ZA6EQ4tbn5LcdGxtbZSuKFZABd8kEyV2fyGlK2JLqcYWYbEoCNVzgfhawaQVro2+k3c+ 8RYPoTNZwzoFYMBrN7jIFHK4Qt3AyLV04HGDUtxJry76AALyatNH8ubaU/aF9GFioyxC VGxk/silTPajfNierca0bcXDI/4vJLOFmgcD6WY1P6Rshk2a35rsJoVhyu1JwoKX3eRv wuIhD1Oa3q1ROR2iGOBHBAFNUJHAvSWSh+BQjhZarEb7FWDl4SG0tB7odDCrJ0/mKQwo BqsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=udkQUS+rmcweD6Pl5NHnookbTYLQgFazwcOeCxhOecY=; b=JQzQlkXHJin2/1bUYuyefxlr3Ctosxx7IxRMDrZN5mgLTZIj/Nz9Zkpb/rraK2JuLT jJd+NkTZ6P72GTn7NHFnRCHvRHyjMLhrdKk6v4s4uPUn0eWQJJd3r5JUzm3u6Yr4xFhS pyE7EPFWosQcViUW2JAICqQEJeDBFQ4qG5fwZBPD2U8mopQuE34jCbdGAwlo2Ut3vrB9 ebOsc0zDUKF8P5TpR5nrHhCo0a0yziF+LCnOeqsob/2oxSfM1ktH6zSG1N2rTYD8vpMQ fMZ9jdH9lcZXKDvPlIefQFKIRvmsuB36pEPgive0pcKGkvC8uRfxhcKg4YFuAG2ZZrdz sf3g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id j126si590461qka.14.2018.12.13.07.28.50 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 07:28:50 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53267 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSuv-0001Y4-Q9 for patch@linaro.org; Thu, 13 Dec 2018 10:28:49 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36308) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSOy-0004tP-8W for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXSOu-0008F6-Gx for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:46 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:53512) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gXSOs-0007J5-Ei for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:42 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gXSOC-0007Lm-Qu for qemu-devel@nongnu.org; Thu, 13 Dec 2018 14:55:00 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 14:54:36 +0000 Message-Id: <20181213145445.17935-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213145445.17935-1-peter.maydell@linaro.org> References: <20181213145445.17935-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 28/37] target/arm: Move id_aa64mmfr* to ARMISARegisters X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" At the same time, define the fields for these registers, and use those defines in arm_pamax(). Signed-off-by: Richard Henderson Message-id: 20181203203839.757-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell [PMM: fixed up typo (s/achf/ahcf/) belatedly spotted by RTH] Signed-off-by: Peter Maydell --- target/arm/cpu.h | 26 ++++++++++++++++++++++++-- target/arm/internals.h | 3 ++- target/arm/cpu64.c | 6 +++--- target/arm/helper.c | 4 ++-- target/arm/kvm64.c | 4 ++++ 5 files changed, 35 insertions(+), 8 deletions(-) -- 2.19.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2a73fed9a01..656a96a8f8f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -818,6 +818,8 @@ struct ARMCPU { uint64_t id_aa64isar1; uint64_t id_aa64pfr0; uint64_t id_aa64pfr1; + uint64_t id_aa64mmfr0; + uint64_t id_aa64mmfr1; } isar; uint32_t midr; uint32_t revidr; @@ -839,8 +841,6 @@ struct ARMCPU { uint64_t id_aa64dfr1; uint64_t id_aa64afr0; uint64_t id_aa64afr1; - uint64_t id_aa64mmfr0; - uint64_t id_aa64mmfr1; uint32_t dbgdidr; uint32_t clidr; uint64_t mp_affinity; /* MP ID without feature bits */ @@ -1557,6 +1557,28 @@ FIELD(ID_AA64PFR0, GIC, 24, 4) FIELD(ID_AA64PFR0, RAS, 28, 4) FIELD(ID_AA64PFR0, SVE, 32, 4) +FIELD(ID_AA64MMFR0, PARANGE, 0, 4) +FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) +FIELD(ID_AA64MMFR0, BIGEND, 8, 4) +FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) +FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) +FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) +FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) +FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) +FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) +FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) +FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) +FIELD(ID_AA64MMFR0, EXS, 44, 4) + +FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) +FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) +FIELD(ID_AA64MMFR1, VH, 8, 4) +FIELD(ID_AA64MMFR1, HPDS, 12, 4) +FIELD(ID_AA64MMFR1, LO, 16, 4) +FIELD(ID_AA64MMFR1, PAN, 20, 4) +FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) +FIELD(ID_AA64MMFR1, XNX, 28, 4) + QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); /* If adding a feature bit which corresponds to a Linux ELF diff --git a/target/arm/internals.h b/target/arm/internals.h index d208b70a64f..78e026d6e90 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -229,7 +229,8 @@ static inline unsigned int arm_pamax(ARMCPU *cpu) [4] = 44, [5] = 48, }; - unsigned int parange = extract32(cpu->id_aa64mmfr0, 0, 4); + unsigned int parange = + FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); /* id_aa64mmfr0 is a read-only register so values outside of the * supported mappings can be considered an implementation error. */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 873f059bf22..0babe483ac2 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -141,7 +141,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->pmceid0 = 0x00000000; cpu->pmceid1 = 0x00000000; cpu->isar.id_aa64isar0 = 0x00011120; - cpu->id_aa64mmfr0 = 0x00001124; + cpu->isar.id_aa64mmfr0 = 0x00001124; cpu->dbgdidr = 0x3516d000; cpu->clidr = 0x0a200023; cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ @@ -195,7 +195,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.id_aa64pfr0 = 0x00002222; cpu->id_aa64dfr0 = 0x10305106; cpu->isar.id_aa64isar0 = 0x00011120; - cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ + cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ cpu->dbgdidr = 0x3516d000; cpu->clidr = 0x0a200023; cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ @@ -249,7 +249,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->pmceid0 = 0x00000000; cpu->pmceid1 = 0x00000000; cpu->isar.id_aa64isar0 = 0x00011120; - cpu->id_aa64mmfr0 = 0x00001124; + cpu->isar.id_aa64mmfr0 = 0x00001124; cpu->dbgdidr = 0x3516d000; cpu->clidr = 0x0a200023; cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 0da1424f72d..04c4a91b04c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5207,11 +5207,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST, - .resetvalue = cpu->id_aa64mmfr0 }, + .resetvalue = cpu->isar.id_aa64mmfr0 }, { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, - .resetvalue = cpu->id_aa64mmfr1 }, + .resetvalue = cpu->isar.id_aa64mmfr1 }, { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST, diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 0a502091e76..089af9c5f02 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -538,6 +538,10 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) ARM64_SYS_REG(3, 0, 0, 6, 0)); err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, ARM64_SYS_REG(3, 0, 0, 6, 1)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0, + ARM64_SYS_REG(3, 0, 0, 7, 0)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, + ARM64_SYS_REG(3, 0, 0, 7, 1)); /* * Note that if AArch32 support is not present in the host, From patchwork Thu Dec 13 14:54:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153678 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp920914ljp; Thu, 13 Dec 2018 07:16:41 -0800 (PST) X-Google-Smtp-Source: AFSGD/U6EI8IkQZHxWXy+NGYGR/SSQqqLwGshv71MhqD1euUJSmMKFgxzHXUKL5p1b2WtUV/MqH7 X-Received: by 2002:a37:1909:: with SMTP id k9mr22321435qkh.61.1544714201868; Thu, 13 Dec 2018 07:16:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544714201; cv=none; d=google.com; s=arc-20160816; b=gnZ0gCyQRj2Kkegdb/K+OZXGLArDJ5BtrER9gRUts6y+HhInVm+sEIKpwVU/IhJgi9 NNuy7Cze3cFzOKrWlU/3cwbP6LzFLHv4gTXxj0w0o//dw3mlNPfl8VlVWgBmxBdOXJ6y X4llThP8I9d++GIwjeG9s/njLjb+sa3ZSRNth/3cOpU8da7NM7sMunXKQr5KuNr8pqBx DomLgFw8cR8mcR6qvjD/EpxnEhnca4T5MuKfet4RhijA7Gcw5md5L/OBlYntkiJUYTYz NTOhILpuR6vkEblv29xzHLwDTVHMzmInJ+JE03sVjaQjZW/OOqnEklfAUqH+e0MdMQTy +xzw== ARC-Message-Signature: i=1; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id h64si1192327qkd.110.2018.12.13.07.16.41 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 07:16:41 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53200 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSjB-0007QD-7X for patch@linaro.org; Thu, 13 Dec 2018 10:16:41 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36279) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSOu-0004py-LG for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXSOs-0008D7-KF for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:44 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:53510) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gXSOr-000747-Sr for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:42 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gXSOD-0007M0-B1 for qemu-devel@nongnu.org; Thu, 13 Dec 2018 14:55:01 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 14:54:37 +0000 Message-Id: <20181213145445.17935-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213145445.17935-1-peter.maydell@linaro.org> References: <20181213145445.17935-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 29/37] target/arm: Add HCR_EL2 bits up to ARMv8.5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Post v8.3 bits taken from SysReg_v85_xml-00bet8. Signed-off-by: Richard Henderson Message-id: 20181203203839.757-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) -- 2.19.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 656a96a8f8f..79d58978f7c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1249,7 +1249,7 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define HCR_TIDCP (1ULL << 20) #define HCR_TACR (1ULL << 21) #define HCR_TSW (1ULL << 22) -#define HCR_TPC (1ULL << 23) +#define HCR_TPCP (1ULL << 23) #define HCR_TPU (1ULL << 24) #define HCR_TTLB (1ULL << 25) #define HCR_TVM (1ULL << 26) @@ -1261,6 +1261,26 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define HCR_CD (1ULL << 32) #define HCR_ID (1ULL << 33) #define HCR_E2H (1ULL << 34) +#define HCR_TLOR (1ULL << 35) +#define HCR_TERR (1ULL << 36) +#define HCR_TEA (1ULL << 37) +#define HCR_MIOCNCE (1ULL << 38) +#define HCR_APK (1ULL << 40) +#define HCR_API (1ULL << 41) +#define HCR_NV (1ULL << 42) +#define HCR_NV1 (1ULL << 43) +#define HCR_AT (1ULL << 44) +#define HCR_NV2 (1ULL << 45) +#define HCR_FWB (1ULL << 46) +#define HCR_FIEN (1ULL << 47) +#define HCR_TID4 (1ULL << 49) +#define HCR_TICAB (1ULL << 50) +#define HCR_TOCU (1ULL << 52) +#define HCR_TTLBIS (1ULL << 54) +#define HCR_TTLBOS (1ULL << 55) +#define HCR_ATA (1ULL << 56) +#define HCR_DCT (1ULL << 57) + /* * When we actually implement ARMv8.1-VHE we should add HCR_E2H to * HCR_MASK and then clear it again if the feature bit is not set in From patchwork Thu Dec 13 14:54:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153679 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp920965ljp; Thu, 13 Dec 2018 07:16:44 -0800 (PST) X-Google-Smtp-Source: AFSGD/VlmTpGejdJVThZ7FID6wRFYlQ8V2iEDlyJMel2JLnSit87z+WNN2NK+HiXHteFXvAGaNtC X-Received: by 2002:ac8:7201:: with SMTP id a1mr24215135qtp.291.1544714204475; Thu, 13 Dec 2018 07:16:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544714204; cv=none; d=google.com; s=arc-20160816; b=R+zPknYJw7mpKJDrkNhnufHxL0iVd82ba01TPl08cARJUYoAzJo79qPYi86IhBlGHy ggcrTDbbet/CS3EObjVuniehCpMV6GbHdDs7cOE0+8PEIkYEJ1u+kpG6JF67E6PFQg4O u4SeFkvwIVD5H2pWUiTQtPzECA7jYNjatdc4SVZUTAX51xBKOVCQ1UAEtFT9NEwP2OSs V9YuWgIylYke1zDfJ80NaDg8IboA5K+svg2KZyJ5sQk6HnguPYrb2EYMgRv6dkwZSKDS sDB5bYmh0T1Uo2STy9eLdYGoX90VxMFqpvy0KyEtmsmLxjQfY83Bt/r7f/29uEerS4sF qkgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=+HqhJFdCbgMrAsL01OAoFdhJ7iusn0z04KMtvPnIpgU=; b=NIykTLuDWNx99Zfnmky/bZwremLQkYgeCg7xCtbDf9qZyXFJCwbO2lsl5CKO0Qaeua ZoJ3ggNGDtgmh+q4nnoeY4BpZMjp0Jvrf9A/fRz8+D+ZMrejgYDTZ+YbsxAaYH1JzrFh 7aYAjIU7zMJqmjf2dCTIPtK7TL5JginFgTp/pEYc30SrbK8ztOJGlMXldgETfnw2JYdS 92IE9ZtFi2J0OQEuJB/PZEI/nsjy4W13ap1sdM3iCVOEu9dTF47kWJcX3k//5KqwcXS8 PgRcYpoqEAy85UNpclMhcgAA+788DabKLi8MYpqR5fJAwGckecA/N30nsvEBLpXnEZNx 8cEA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id e25si1220201qvb.25.2018.12.13.07.16.44 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 07:16:44 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53201 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSjD-0007S1-Oi for patch@linaro.org; Thu, 13 Dec 2018 10:16:43 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36041) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSOW-0004TQ-3s for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXSOS-0007bB-1i for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:18 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:53506) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gXSOR-0006zA-NA for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:15 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gXSOE-0007ME-2V for qemu-devel@nongnu.org; Thu, 13 Dec 2018 14:55:02 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 14:54:38 +0000 Message-Id: <20181213145445.17935-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213145445.17935-1-peter.maydell@linaro.org> References: <20181213145445.17935-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 30/37] target/arm: Add SCR_EL3 bits up to ARMv8.5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Post v8.4 bits taken from SysReg_v85_xml-00bet8. Signed-off-by: Richard Henderson Message-id: 20181203203839.757-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.19.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 79d58978f7c..20d97b66def 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1302,6 +1302,16 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define SCR_ST (1U << 11) #define SCR_TWI (1U << 12) #define SCR_TWE (1U << 13) +#define SCR_TLOR (1U << 14) +#define SCR_TERR (1U << 15) +#define SCR_APK (1U << 16) +#define SCR_API (1U << 17) +#define SCR_EEL2 (1U << 18) +#define SCR_EASE (1U << 19) +#define SCR_NMEA (1U << 20) +#define SCR_FIEN (1U << 21) +#define SCR_ENSCXT (1U << 25) +#define SCR_ATA (1U << 26) #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST)) #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET) From patchwork Thu Dec 13 14:54:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153675 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp917244ljp; Thu, 13 Dec 2018 07:13:45 -0800 (PST) X-Google-Smtp-Source: AFSGD/WTuK77SswP9kMKixu9p7nvxuKLLa4hmBdssvKndY/dCrrqYrHTyvo5TvInLSPUIPtyCTzq X-Received: by 2002:ac8:2472:: with SMTP id d47mr24158132qtd.7.1544714025022; Thu, 13 Dec 2018 07:13:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544714025; cv=none; d=google.com; s=arc-20160816; b=uVzoYah4fivhOfbm/2Jhi2Gj/VHzwHIp7lUoQ/6mDHQ3lXKp/dkbqOYMIVMMXjKoWd e9C0Olpy4Urtnb3umuXLw2XSYFdYbPJPTvg5nAQdZae92JAJ0lejGqcYrOeGaMcWD85h 64guRYhIRgR39xNQ72hmaY7kTsFkPRaF7C8+ONSOvsSzjlIi7UF+3QLuwn/ey4W3dP1n bxpedGJlc+9V67Z+j4ZQl62QyX1zftbxKSYF5m9Lxfd1xXy87bcdZOynC8pYIAYANf3r etzm9UutvZvTV5sga5eQW+yDEz7OT7t2jPDr3wxH3owopwCs81JVMyS5qrYZyA2b2qv/ 9Z0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=OeCoORcMy1xERNPaVbFhLscnmdFAUVuVp0RuKrlRIZo=; b=XXQELU/+1Ttq2qQiqFD8tbF/j5aEMOnLT7rB+BL8/1/GiHznk8Sf1ezGnCztzSHS96 PTu9oMIVLPRCJkMXiR3I5rS4Zsm5fOf+brYQLcJWIB9L+Bzg/0SXimBUQIpEkC2981iS 2MAZApckF72ytKoKUqqVZdG0/fuUl4aspInyfXp1IsxtzSJ9j+m61yM4DaQ/POfbgdqs 2gMnAgI5SuiOacZTlK50KgvvjAsGeGVURxWu4CI8talHZkz/GNpB1C42JH6ss9TlPA43 5JPAx9WggGo1lWcpnuFrT7AGPr3Np7C427sRgDxIAEsBKOKkOmRreXtSTmqLmCuiq70R FCPA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id y52si1194942qty.161.2018.12.13.07.13.44 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 07:13:45 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53181 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSgK-00054j-EW for patch@linaro.org; Thu, 13 Dec 2018 10:13:44 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36039) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSOW-0004TP-3d for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXSOR-0007au-TH for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:18 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:53508) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gXSOR-00071P-3o for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:15 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gXSOE-0007MS-Id for qemu-devel@nongnu.org; Thu, 13 Dec 2018 14:55:02 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 14:54:39 +0000 Message-Id: <20181213145445.17935-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213145445.17935-1-peter.maydell@linaro.org> References: <20181213145445.17935-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 31/37] target/arm: Fix HCR_EL2.TGE check in arm_phys_excp_target_el X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The enable for TGE has already occurred within arm_hcr_el2_amo and friends. Moreover, when E2H is also set, the sense is supposed to be reversed, which has also already occurred within the helpers. Signed-off-by: Richard Henderson Message-id: 20181203203839.757-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 3 --- 1 file changed, 3 deletions(-) -- 2.19.2 diff --git a/target/arm/helper.c b/target/arm/helper.c index 04c4a91b04c..bf020364e1d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6537,9 +6537,6 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, break; }; - /* If HCR.TGE is set then HCR is treated as being 1 */ - hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE); - /* Perform a table-lookup for the target EL given the current state */ target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el]; From patchwork Thu Dec 13 14:54:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153672 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp913733ljp; Thu, 13 Dec 2018 07:10:56 -0800 (PST) X-Google-Smtp-Source: AFSGD/UdiPMoSJaz8tHogYYq+143zdI9Kh0YbTXorYiq+Ftai+Y4q2DIcyrKCb3C/k/O+jTpH+oy X-Received: by 2002:ac8:33b6:: with SMTP id c51mr24147307qtb.190.1544713856472; Thu, 13 Dec 2018 07:10:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544713856; cv=none; d=google.com; s=arc-20160816; b=X2njg+SmDmndyQrzvfQKXn/IcqtW8H4Q+20dh2WL8OEm1utDf8RXbwM60sZxMiyZnb lCz58RLVadUyFwSxKVwndGXckRbYAAZVzMnN65unPEao1/ongevfhtG5MUOKbW7EjP0l hhfcWX/9VKZeeqIrmIBAyCKLp7LYjuT/t3ivljyb2b8usSOUY5w3kUOASaVDCSSebaqF z/SiMo0dlOeg4FokLHTnKpgbGiY1OWA3W1CqzEi6S7SV063Z2sqxSnYxGoNO6ps0Kshr MnKc/nWUVzuk/dRBL6hawrctTcFnHrko+LFX6ebALrfnBDuO7HUMhaDceM13NXmSJ7ph CuSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=oaZRiLpgoIeq90J0GkTbFDkb63w7e9QEHsZHDkAg3EY=; b=ylXv9fXKkMIPbZ7KjBIlW/9JgfemW8sBqVZFYCugDwbNyRgjMRN5Tqe+DFdnTPfsk0 SnY5TB9fvBEBllTnWVcZ8aI3ZqoYxfAhWX7xSeyO2zSeXHJz4/tOFI7x4lE8lS7eFNm5 UZlZ95+E+/g5byQp2K5G7KMMFx4DpBNhGVGkVq7Os99MeXlVVQ4JIepgab/SjG4JVIUW +X3n6UEiOR0CAmsODDvQ9NdgisSKATrYQbJCCBXozwFJZjOfaqldE8ZyvlPIx0uZjZ0Z 0zawKPRq400D8yeATIGw1L6S7/te91zPhg8fYFYz8oEFNCI+AiqYSyTxOE8ZwTV9KYpE 9iNg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id a67si470134qkg.137.2018.12.13.07.10.56 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 07:10:56 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53166 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSdb-00024V-TS for patch@linaro.org; Thu, 13 Dec 2018 10:10:55 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36033) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSOU-0004RX-5p for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXSOR-0007aF-FE for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:16 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:53510) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gXSOQ-000747-I0 for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:14 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gXSOF-0007Mg-31 for qemu-devel@nongnu.org; Thu, 13 Dec 2018 14:55:03 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 14:54:40 +0000 Message-Id: <20181213145445.17935-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213145445.17935-1-peter.maydell@linaro.org> References: <20181213145445.17935-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 32/37] target/arm: Tidy scr_write X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Because EL3 has a fixed execution mode, we can properly decide which of the bits are RES{0,1}. Signed-off-by: Richard Henderson Message-id: 20181203203839.757-8-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 -- target/arm/helper.c | 14 +++++++++----- 2 files changed, 9 insertions(+), 7 deletions(-) -- 2.19.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 20d97b66def..b8dbdb5e014 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1312,8 +1312,6 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define SCR_FIEN (1U << 21) #define SCR_ENSCXT (1U << 25) #define SCR_ATA (1U << 26) -#define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST)) -#define SCR_AARCH64_MASK (0x3fff & ~SCR_NET) /* Return the current FPSCR value. */ uint32_t vfp_get_fpscr(CPUARMState *env); diff --git a/target/arm/helper.c b/target/arm/helper.c index bf020364e1d..1dad277804f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1279,11 +1279,15 @@ static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* We only mask off bits that are RES0 both for AArch64 and AArch32. - * For bits that vary between AArch32/64, code needs to check the - * current execution mode before directly using the feature bit. - */ - uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK; + /* Begin with base v8.0 state. */ + uint32_t valid_mask = 0x3fff; + + if (arm_el_is_aa64(env, 3)) { + value |= SCR_FW | SCR_AW; /* these two bits are RES1. */ + valid_mask &= ~SCR_NET; + } else { + valid_mask &= ~(SCR_RW | SCR_ST); + } if (!arm_feature(env, ARM_FEATURE_EL2)) { valid_mask &= ~SCR_HCE; From patchwork Thu Dec 13 14:54:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153681 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp924882ljp; Thu, 13 Dec 2018 07:19:55 -0800 (PST) X-Google-Smtp-Source: AFSGD/Ut2t51q5TkJ1PGNMwgeS0vUZ2ue4Iy73E2NRZCgc+3zSwXPUN9IljiQJ8S4ujs3XYSyE7f X-Received: by 2002:ae9:dc43:: with SMTP id q64mr21987639qkf.223.1544714395540; Thu, 13 Dec 2018 07:19:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544714395; cv=none; d=google.com; s=arc-20160816; b=MvOoqgy92DYZ4Hdy3UEQVUqJC1lRO1OESdmqo7YH/27j+ShHCnoSfOOnCMhnGTO0Mx Abxle3e9+iYMlxEBrjFgvsIfG0pMeweO13hijnyOumkxv3KSM/guIoBNFjs4OqUUOmdM uNLf0QqTOH2OMbs1m2J0pUZeZRGGlx5ih3lp2XIgPLdOxY+iaHB7LhIBzR+QusY7iPCG c6FbD7ZCYXhoTVdyMSaN3zj+gem823ds2syd4ZjAeZHhWIjZrMNiSbzdCv16C/x6G7Uj ikWab+vDYeYXBM13J0Z2S8rlNO7Dl+WNk5W0byr8wwxWiqV4wIB6mP/k9Eb7ljdIrjQf fhww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=8QpmqC/8wzMW5wO7z/UCaZfJvC755SSRCSY8iXvddw4=; b=s04NgKxEOG9Q1cVOP94WRzZVkr7XVjze/IDmmu0hTk2oBUc9SRQ1SA+wKkxubPwh6g sqUogiX8J7xG+/400lfLeH6t3mc9+wd8iO0R+XE7n2gi1R+O1FNYYVq3lJMuEK+maCAb HG2M9YkZ5QI5SWWrQurWCUZiy4rKZv4wz66cyPBi6jTf7Y31NkymfQQ1cG/CMJv1Ifww HmKz1+BzJwyfiVVKwfxGLojTsT3eUaUeGys0eSHSTh3J+N15LBJvbnjocBHwm4DCqOiL d515Hz5FZ8l9AoxtzSoo9tJZe6hYa7K3zYeOUX5Q4Qc6quDLt6INv8DKo2gW2zcuu7pS HVdw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id f42si1221762qkh.191.2018.12.13.07.19.55 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 07:19:55 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53214 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSmI-0001aA-V6 for patch@linaro.org; Thu, 13 Dec 2018 10:19:54 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36053) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSOX-0004Ux-K5 for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXSOS-0007bD-1d for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:18 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:53512) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gXSOR-0007J5-Dl for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:15 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gXSOF-0007Mw-T0 for qemu-devel@nongnu.org; Thu, 13 Dec 2018 14:55:03 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 14:54:41 +0000 Message-Id: <20181213145445.17935-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213145445.17935-1-peter.maydell@linaro.org> References: <20181213145445.17935-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 33/37] target/arm: Implement the ARMv8.1-HPD extension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Since the TCR_*.HPD bits were RES0 in ARMv8.0, we can simply interpret the bits as if ARMv8.1-HPD is present without checking. We will need a slightly different check for hpd for aarch32. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20181203203839.757-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu64.c | 4 ++++ target/arm/helper.c | 27 ++++++++++++++++++++------- 2 files changed, 24 insertions(+), 7 deletions(-) -- 2.19.2 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 0babe483ac2..1a4289c9dda 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -324,6 +324,10 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); cpu->isar.id_aa64pfr0 = t; + t = cpu->isar.id_aa64mmfr1; + t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ + cpu->isar.id_aa64mmfr1 = t; + /* Replicate the same data to the 32-bit id registers. */ u = cpu->isar.id_isar5; u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 1dad277804f..57af6b77a1b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9636,6 +9636,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, bool ttbr1_valid = true; uint64_t descaddrmask; bool aarch64 = arm_el_is_aa64(env, el); + bool hpd = false; /* TODO: * This code does not handle the different format TCR for VTCR_EL2. @@ -9750,6 +9751,13 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, if (tg == 2) { /* 16KB pages */ stride = 11; } + if (aarch64) { + if (el > 1) { + hpd = extract64(tcr->raw_tcr, 24, 1); + } else { + hpd = extract64(tcr->raw_tcr, 41, 1); + } + } } else { /* We should only be here if TTBR1 is valid */ assert(ttbr1_valid); @@ -9765,6 +9773,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, if (tg == 1) { /* 16KB pages */ stride = 11; } + if (aarch64) { + hpd = extract64(tcr->raw_tcr, 42, 1); + } } /* Here we should have set up all the parameters for the translation: @@ -9858,7 +9869,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, descaddr = descriptor & descaddrmask; if ((descriptor & 2) && (level < 3)) { - /* Table entry. The top five bits are attributes which may + /* Table entry. The top five bits are attributes which may * propagate down through lower levels of the table (and * which are all arranged so that 0 means "no effect", so * we can gather them up by ORing in the bits at each level). @@ -9883,15 +9894,17 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, break; } /* Merge in attributes from table descriptors */ - attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ - attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */ + attrs |= nstable << 3; /* NS */ + if (hpd) { + /* HPD disables all the table attributes except NSTable. */ + break; + } + attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 * means "force PL1 access only", which means forcing AP[1] to 0. */ - if (extract32(tableattrs, 2, 1)) { - attrs &= ~(1 << 4); - } - attrs |= nstable << 3; /* NS */ + attrs &= ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] => AP[1] */ + attrs |= extract32(tableattrs, 3, 1) << 5; /* APT[1] => AP[2] */ break; } /* Here descaddr is the final physical address, and attributes From patchwork Thu Dec 13 14:54:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153687 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp934061ljp; Thu, 13 Dec 2018 07:28:25 -0800 (PST) X-Google-Smtp-Source: AFSGD/Xjl+1Czhr7k7rYGKml7XaUvRsjObqaF6GUrhAU8SkE4xkIFEiISs4cMeAjyGscFGUeyQVM X-Received: by 2002:a37:5dc3:: with SMTP id r186mr22461567qkb.90.1544714905812; Thu, 13 Dec 2018 07:28:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544714905; cv=none; d=google.com; s=arc-20160816; b=urj40rU+maHfwqTEZYLqNUjMXRzSw40HCZ4cw1a5HufqrIMEmA87JimLC1ZQk7mwhq G12NeIuHDemhgrfIAX5zSvIQV8I2fNKvrTYzkX3Wq2Gs4na9hJB2OjJQO/knA9WpdxHB Ng3vJf7FHOHjzp8+u2Hox7v9fPOsNLq91dgC52ewwR/1wb3ZUkCUq3bhGYOXcAjc5Ppk dFg1YeRe+vnopOinwIvwDO3+qVga5EChhyqS9TMPNdtZsCG8eThb+llu6DYUQ3MlK8Va wGtGBf6/PLR2wmPOQlUbvagdpRVkHGAnaP4vH3IBVvqGAH5hjonlyzfk6Bnjn+sSgTpG jfYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=gP07tFLhrc+0d1viBB4kcKnMkkejzSVe2/nVouK6MHw=; b=DlCIDNCI/ZBvmXMKW9P+bo/FC7dA0MfK/r4zin5psj8uFEfb6gxTYzlb6PNnnPpGMB NV3QNjL8/VFTshDi4/DCLIXpd32dn5PpIYftFGZGdN4LcwkATcNMZmNdArx8wpgxJy5k qYaB7cBSvDGIU6OZphtbthD9CuOs/ddIEgjtjD5+eBH/jOmhw0NLj54QT1MWxHu0UV/f 3E7sJkhzZBLySTxVmXfQWt71AWWqmW3ls9tf1j1cy6Hh6w9y6A9p4odefOumulfogGl8 yiymtC15GQ18l0/VLBfEHQ8maLdBeJXvXvcv/u+S/f2Lak/h6W0Y5a2CYzkY/mFdTlWw zT+Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id p65si1211659qkf.138.2018.12.13.07.28.25 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 07:28:25 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53260 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSuX-00089H-7D for patch@linaro.org; Thu, 13 Dec 2018 10:28:25 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36189) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXSOi-0004ea-FK for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXSOg-0007up-Do for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:32 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:53506) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gXSOg-0006zA-2G for qemu-devel@nongnu.org; Thu, 13 Dec 2018 09:55:30 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gXSOG-0007NE-GR for qemu-devel@nongnu.org; Thu, 13 Dec 2018 14:55:04 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 14:54:42 +0000 Message-Id: <20181213145445.17935-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213145445.17935-1-peter.maydell@linaro.org> References: <20181213145445.17935-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 34/37] target/arm: Implement the ARMv8.2-AA32HPD extension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The bulk of the work here, beyond base HPD, is defining the TTBCR2 register. In addition we must check TTBCR.T2E, which is not present (RES0) for AArch64. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20181203203839.757-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 9 +++++++++ target/arm/cpu.c | 4 ++++ target/arm/helper.c | 37 +++++++++++++++++++++++++++++-------- 3 files changed, 42 insertions(+), 8 deletions(-) -- 2.19.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b8dbdb5e014..11ec2cce767 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1548,6 +1548,15 @@ FIELD(ID_ISAR6, FHM, 8, 4) FIELD(ID_ISAR6, SB, 12, 4) FIELD(ID_ISAR6, SPECRES, 16, 4) +FIELD(ID_MMFR4, SPECSEI, 0, 4) +FIELD(ID_MMFR4, AC2, 4, 4) +FIELD(ID_MMFR4, XNX, 8, 4) +FIELD(ID_MMFR4, CNP, 12, 4) +FIELD(ID_MMFR4, HPDS, 16, 4) +FIELD(ID_MMFR4, LSM, 20, 4) +FIELD(ID_MMFR4, CCIDX, 24, 4) +FIELD(ID_MMFR4, EVT, 28, 4) + FIELD(ID_AA64ISAR0, AES, 4, 4) FIELD(ID_AA64ISAR0, SHA1, 8, 4) FIELD(ID_AA64ISAR0, SHA2, 12, 4) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 60411f6bfe0..0b185f8d309 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1932,6 +1932,10 @@ static void arm_max_initfn(Object *obj) t = cpu->isar.id_isar6; t = FIELD_DP32(t, ID_ISAR6, DP, 1); cpu->isar.id_isar6 = t; + + t = cpu->id_mmfr4; + t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ + cpu->id_mmfr4 = t; } #endif } diff --git a/target/arm/helper.c b/target/arm/helper.c index 57af6b77a1b..037cece1334 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2728,6 +2728,7 @@ static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { ARMCPU *cpu = arm_env_get_cpu(env); + TCR *tcr = raw_ptr(env, ri); if (arm_feature(env, ARM_FEATURE_LPAE)) { /* With LPAE the TTBCR could result in a change of ASID @@ -2735,6 +2736,8 @@ static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, */ tlb_flush(CPU(cpu)); } + /* Preserve the high half of TCR_EL1, set via TTBCR2. */ + value = deposit64(tcr->raw_tcr, 0, 32, value); vmsa_ttbcr_raw_write(env, ri, value); } @@ -2837,6 +2840,16 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { REGINFO_SENTINEL }; +/* Note that unlike TTBCR, writing to TTBCR2 does not require flushing + * qemu tlbs nor adjusting cached masks. + */ +static const ARMCPRegInfo ttbcr2_reginfo = { + .name = "TTBCR2", .cp = 15, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 3, + .access = PL1_RW, .type = ARM_CP_ALIAS, + .bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.tcr_el[3]), + offsetofhigh32(CPUARMState, cp15.tcr_el[1]) }, +}; + static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -5437,6 +5450,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) } else { define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); define_arm_cp_regs(cpu, vmsa_cp_reginfo); + /* TTCBR2 is introduced with ARMv8.2-A32HPD. */ + if (FIELD_EX32(cpu->id_mmfr4, ID_MMFR4, HPDS) != 0) { + define_one_arm_cp_reg(cpu, &ttbcr2_reginfo); + } } if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { define_arm_cp_regs(cpu, t2ee_cp_reginfo); @@ -9751,12 +9768,14 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, if (tg == 2) { /* 16KB pages */ stride = 11; } - if (aarch64) { - if (el > 1) { - hpd = extract64(tcr->raw_tcr, 24, 1); - } else { - hpd = extract64(tcr->raw_tcr, 41, 1); - } + if (aarch64 && el > 1) { + hpd = extract64(tcr->raw_tcr, 24, 1); + } else { + hpd = extract64(tcr->raw_tcr, 41, 1); + } + if (!aarch64) { + /* For aarch32, hpd0 is not enabled without t2e as well. */ + hpd &= extract64(tcr->raw_tcr, 6, 1); } } else { /* We should only be here if TTBR1 is valid */ @@ -9773,8 +9792,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, if (tg == 1) { /* 16KB pages */ stride = 11; } - if (aarch64) { - hpd = extract64(tcr->raw_tcr, 42, 1); + hpd = extract64(tcr->raw_tcr, 42, 1); + if (!aarch64) { + /* For aarch32, hpd1 is not enabled without t2e as well. */ + hpd &= extract64(tcr->raw_tcr, 6, 1); } } From patchwork Thu Dec 13 14:54:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153669 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp909206ljp; Thu, 13 Dec 2018 07:07:13 -0800 (PST) X-Google-Smtp-Source: AFSGD/Wdro746o5ijbGOiTs/DSfdWUeNeXxv0gETZevCyEdPIN/j1VeQQ56VxvWOGSSbG1+kkNag X-Received: by 2002:ac8:1:: with SMTP id a1mr24184968qtg.366.1544713633648; Thu, 13 Dec 2018 07:07:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544713633; 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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 35/37] target/arm: Introduce arm_hcr_el2_eff X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Replace arm_hcr_el2_{fmo,imo,amo} with a more general routine that also takes SCR_EL3.NS (aka arm_is_secure_below_el3) into account, as documented for the plethora of bits in HCR_EL2. Signed-off-by: Richard Henderson Message-id: 20181210150501.7990-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 67 +++++++++------------------------------ hw/intc/arm_gicv3_cpuif.c | 21 ++++++------ target/arm/helper.c | 66 ++++++++++++++++++++++++++++++++------ 3 files changed, 83 insertions(+), 71 deletions(-) -- 2.19.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 11ec2cce767..05ac883b6be 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1729,6 +1729,14 @@ static inline bool arm_is_secure(CPUARMState *env) } #endif +/** + * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. + * E.g. when in secure state, fields in HCR_EL2 are suppressed, + * "for all purposes other than a direct read or write access of HCR_EL2." + * Not included here is HCR_RW. + */ +uint64_t arm_hcr_el2_eff(CPUARMState *env); + /* Return true if the specified exception level is running in AArch64 state. */ static inline bool arm_el_is_aa64(CPUARMState *env, int el) { @@ -2414,54 +2422,6 @@ bool write_cpustate_to_list(ARMCPU *cpu); # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif -/** - * arm_hcr_el2_imo(): Return the effective value of HCR_EL2.IMO. - * Depending on the values of HCR_EL2.E2H and TGE, this may be - * "behaves as 1 for all purposes other than direct read/write" or - * "behaves as 0 for all purposes other than direct read/write" - */ -static inline bool arm_hcr_el2_imo(CPUARMState *env) -{ - switch (env->cp15.hcr_el2 & (HCR_TGE | HCR_E2H)) { - case HCR_TGE: - return true; - case HCR_TGE | HCR_E2H: - return false; - default: - return env->cp15.hcr_el2 & HCR_IMO; - } -} - -/** - * arm_hcr_el2_fmo(): Return the effective value of HCR_EL2.FMO. - */ -static inline bool arm_hcr_el2_fmo(CPUARMState *env) -{ - switch (env->cp15.hcr_el2 & (HCR_TGE | HCR_E2H)) { - case HCR_TGE: - return true; - case HCR_TGE | HCR_E2H: - return false; - default: - return env->cp15.hcr_el2 & HCR_FMO; - } -} - -/** - * arm_hcr_el2_amo(): Return the effective value of HCR_EL2.AMO. - */ -static inline bool arm_hcr_el2_amo(CPUARMState *env) -{ - switch (env->cp15.hcr_el2 & (HCR_TGE | HCR_E2H)) { - case HCR_TGE: - return true; - case HCR_TGE | HCR_E2H: - return false; - default: - return env->cp15.hcr_el2 & HCR_AMO; - } -} - static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, unsigned int target_el) { @@ -2470,6 +2430,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, bool secure = arm_is_secure(env); bool pstate_unmasked; int8_t unmasked = 0; + uint64_t hcr_el2; /* Don't take exceptions if they target a lower EL. * This check should catch any exceptions that would not be taken but left @@ -2479,6 +2440,8 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, return false; } + hcr_el2 = arm_hcr_el2_eff(env); + switch (excp_idx) { case EXCP_FIQ: pstate_unmasked = !(env->daif & PSTATE_F); @@ -2489,13 +2452,13 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, break; case EXCP_VFIQ: - if (secure || !arm_hcr_el2_fmo(env) || (env->cp15.hcr_el2 & HCR_TGE)) { + if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { /* VFIQs are only taken when hypervized and non-secure. */ return false; } return !(env->daif & PSTATE_F); case EXCP_VIRQ: - if (secure || !arm_hcr_el2_imo(env) || (env->cp15.hcr_el2 & HCR_TGE)) { + if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { /* VIRQs are only taken when hypervized and non-secure. */ return false; } @@ -2534,7 +2497,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, * to the CPSR.F setting otherwise we further assess the state * below. */ - hcr = arm_hcr_el2_fmo(env); + hcr = hcr_el2 & HCR_FMO; scr = (env->cp15.scr_el3 & SCR_FIQ); /* When EL3 is 32-bit, the SCR.FW bit controls whether the @@ -2551,7 +2514,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, * when setting the target EL, so it does not have a further * affect here. */ - hcr = arm_hcr_el2_imo(env); + hcr = hcr_el2 & HCR_IMO; scr = false; break; default: diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 068a8e8e9b9..cbad6037f19 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -85,8 +85,8 @@ static bool icv_access(CPUARMState *env, int hcr_flags) * * access if NS EL1 and either IMO or FMO == 1: * CTLR, DIR, PMR, RPR */ - bool flagmatch = ((hcr_flags & HCR_IMO) && arm_hcr_el2_imo(env)) || - ((hcr_flags & HCR_FMO) && arm_hcr_el2_fmo(env)); + uint64_t hcr_el2 = arm_hcr_el2_eff(env); + bool flagmatch = hcr_el2 & hcr_flags & (HCR_IMO | HCR_FMO); return flagmatch && arm_current_el(env) == 1 && !arm_is_secure_below_el3(env); @@ -1552,8 +1552,9 @@ static void icc_dir_write(CPUARMState *env, const ARMCPRegInfo *ri, /* No need to include !IsSecure in route_*_to_el2 as it's only * tested in cases where we know !IsSecure is true. */ - route_fiq_to_el2 = arm_hcr_el2_fmo(env); - route_irq_to_el2 = arm_hcr_el2_imo(env); + uint64_t hcr_el2 = arm_hcr_el2_eff(env); + route_fiq_to_el2 = hcr_el2 & HCR_FMO; + route_irq_to_el2 = hcr_el2 & HCR_IMO; switch (arm_current_el(env)) { case 3: @@ -1895,8 +1896,8 @@ static CPAccessResult gicv3_irqfiq_access(CPUARMState *env, if ((env->cp15.scr_el3 & (SCR_FIQ | SCR_IRQ)) == (SCR_FIQ | SCR_IRQ)) { switch (el) { case 1: - if (arm_is_secure_below_el3(env) || - (arm_hcr_el2_imo(env) == 0 && arm_hcr_el2_fmo(env) == 0)) { + /* Note that arm_hcr_el2_eff takes secure state into account. */ + if ((arm_hcr_el2_eff(env) & (HCR_IMO | HCR_FMO)) == 0) { r = CP_ACCESS_TRAP_EL3; } break; @@ -1936,8 +1937,8 @@ static CPAccessResult gicv3_dir_access(CPUARMState *env, static CPAccessResult gicv3_sgi_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { - if ((arm_hcr_el2_imo(env) || arm_hcr_el2_fmo(env)) && - arm_current_el(env) == 1 && !arm_is_secure_below_el3(env)) { + if (arm_current_el(env) == 1 && + (arm_hcr_el2_eff(env) & (HCR_IMO | HCR_FMO)) != 0) { /* Takes priority over a possible EL3 trap */ return CP_ACCESS_TRAP_EL2; } @@ -1961,7 +1962,7 @@ static CPAccessResult gicv3_fiq_access(CPUARMState *env, if (env->cp15.scr_el3 & SCR_FIQ) { switch (el) { case 1: - if (arm_is_secure_below_el3(env) || !arm_hcr_el2_fmo(env)) { + if ((arm_hcr_el2_eff(env) & HCR_FMO) == 0) { r = CP_ACCESS_TRAP_EL3; } break; @@ -2000,7 +2001,7 @@ static CPAccessResult gicv3_irq_access(CPUARMState *env, if (env->cp15.scr_el3 & SCR_IRQ) { switch (el) { case 1: - if (arm_is_secure_below_el3(env) || !arm_hcr_el2_imo(env)) { + if ((arm_hcr_el2_eff(env) & HCR_IMO) == 0) { r = CP_ACCESS_TRAP_EL3; } break; diff --git a/target/arm/helper.c b/target/arm/helper.c index 037cece1334..95d59e07fb9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1331,9 +1331,10 @@ static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) { CPUState *cs = ENV_GET_CPU(env); + uint64_t hcr_el2 = arm_hcr_el2_eff(env); uint64_t ret = 0; - if (arm_hcr_el2_imo(env)) { + if (hcr_el2 & HCR_IMO) { if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { ret |= CPSR_I; } @@ -1343,7 +1344,7 @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) } } - if (arm_hcr_el2_fmo(env)) { + if (hcr_el2 & HCR_FMO) { if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { ret |= CPSR_F; } @@ -4008,6 +4009,51 @@ static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, hcr_write(env, NULL, value); } +/* + * Return the effective value of HCR_EL2. + * Bits that are not included here: + * RW (read from SCR_EL3.RW as needed) + */ +uint64_t arm_hcr_el2_eff(CPUARMState *env) +{ + uint64_t ret = env->cp15.hcr_el2; + + if (arm_is_secure_below_el3(env)) { + /* + * "This register has no effect if EL2 is not enabled in the + * current Security state". This is ARMv8.4-SecEL2 speak for + * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1). + * + * Prior to that, the language was "In an implementation that + * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves + * as if this field is 0 for all purposes other than a direct + * read or write access of HCR_EL2". With lots of enumeration + * on a per-field basis. In current QEMU, this is condition + * is arm_is_secure_below_el3. + * + * Since the v8.4 language applies to the entire register, and + * appears to be backward compatible, use that. + */ + ret = 0; + } else if (ret & HCR_TGE) { + /* These bits are up-to-date as of ARMv8.4. */ + if (ret & HCR_E2H) { + ret &= ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO | + HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE | + HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU | + HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE); + } else { + ret |= HCR_FMO | HCR_IMO | HCR_AMO; + } + ret &= ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE | + HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR | + HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM | + HCR_TLOR); + } + + return ret; +} + static const ARMCPRegInfo el2_cp_reginfo[] = { { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, .type = ARM_CP_IO, @@ -6526,12 +6572,13 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, uint32_t cur_el, bool secure) { CPUARMState *env = cs->env_ptr; - int rw; - int scr; - int hcr; + bool rw; + bool scr; + bool hcr; int target_el; /* Is the highest EL AArch64? */ - int is64 = arm_feature(env, ARM_FEATURE_AARCH64); + bool is64 = arm_feature(env, ARM_FEATURE_AARCH64); + uint64_t hcr_el2; if (arm_feature(env, ARM_FEATURE_EL3)) { rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW); @@ -6543,18 +6590,19 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, rw = is64; } + hcr_el2 = arm_hcr_el2_eff(env); switch (excp_idx) { case EXCP_IRQ: scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); - hcr = arm_hcr_el2_imo(env); + hcr = hcr_el2 & HCR_IMO; break; case EXCP_FIQ: scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); - hcr = arm_hcr_el2_fmo(env); + hcr = hcr_el2 & HCR_FMO; break; default: scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA); - hcr = arm_hcr_el2_amo(env); + hcr = hcr_el2 & HCR_AMO; break; }; From patchwork Thu Dec 13 14:54:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153668 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp908511ljp; Thu, 13 Dec 2018 07:06:43 -0800 (PST) X-Google-Smtp-Source: AFSGD/XrSz/HSdMCldf6YXXQ4hqTSHWPIijBK6TGpL//YYSx6grQDeQ8wtpGEMnXFG2Y18+cdz1Q X-Received: by 2002:a0c:baa8:: with SMTP id x40mr2280352qvf.18.1544713602945; Thu, 13 Dec 2018 07:06:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544713602; cv=none; d=google.com; s=arc-20160816; b=w/rblrbbigs4aH3mBoeq4ESbn6JxZ4i9QgWVeyfOHb3bZRT77gc23TThRfvB44HqDd F6xU3phxiCulZNtHyFqTebZr1eq+R9LdnyS4CaXbBsWc5wy/IpoWBGDurr9w+Pfrhs6a ve3HcIgo52lh+fVzV3rM0N+Go7G9ByVzwyRj1/AR007WOF6VjfCsWG4KmCx+XFW2zxpG QvY8r2hw5clli7jzUw3moD5y3VC9Vmp92JzPXoAEFsaiYVgIsGpjihMMUBfh/SVW+aOX DlFta+XgIjDOWuJ9ihBwBa3n5yyhZvKpsSxmfWOpRzhRJPUSoflGVIOXCxXHisT3MeDm 6prQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=lghSZVNxNluHDYgoW3AujLFvmTKMdydL28PYvWr956c=; b=KQiP+2ClDPXiZCUR/gpTNaeQeEbuaboVIzYAtsYiD5JDrpv9mRONDRZ/mMQ73uUIA2 Lwau/OmjWqCqNyYulHggA3Dc6FwxLna/bfSAZt9A3+tPv63kVSdjZQ8nWxr5/rjnQ3qU t2HfIXFUeGvRhTs4SvNSJrVnX+CiNGxlV8QndTqc3s85msoli0I47VeJZphypDiIUt2Y ec8PkayiW/ThlCA0IkttCKAm2e2ycU2aUnOAhLE7v9R3VPDpGW6QQOG2CRa4RXzhHmOP lm7of9PXks36jCBr3PXvIVBhu+VYc6LIpUJCZqqxTIZPrB9aM/MW0Bn4ZgXkDXMzxtZG 4a7w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 36/37] target/arm: Use arm_hcr_el2_eff more places X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Since arm_hcr_el2_eff includes a check against arm_is_secure_below_el3, we can often remove a nearby check against secure state. In some cases, sort the call to arm_hcr_el2_eff to the end of a short-circuit logical sequence. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20181210150501.7990-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 12 +++++------- target/arm/op_helper.c | 14 ++++++-------- 2 files changed, 11 insertions(+), 15 deletions(-) -- 2.19.2 diff --git a/target/arm/helper.c b/target/arm/helper.c index 95d59e07fb9..d6f8be9f4e1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -448,7 +448,7 @@ static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri, int el = arm_current_el(env); bool mdcr_el2_tdosa = (env->cp15.mdcr_el2 & MDCR_TDOSA) || (env->cp15.mdcr_el2 & MDCR_TDE) || - (env->cp15.hcr_el2 & HCR_TGE); + (arm_hcr_el2_eff(env) & HCR_TGE); if (el < 2 && mdcr_el2_tdosa && !arm_is_secure_below_el3(env)) { return CP_ACCESS_TRAP_EL2; @@ -468,7 +468,7 @@ static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, int el = arm_current_el(env); bool mdcr_el2_tdra = (env->cp15.mdcr_el2 & MDCR_TDRA) || (env->cp15.mdcr_el2 & MDCR_TDE) || - (env->cp15.hcr_el2 & HCR_TGE); + (arm_hcr_el2_eff(env) & HCR_TGE); if (el < 2 && mdcr_el2_tdra && !arm_is_secure_below_el3(env)) { return CP_ACCESS_TRAP_EL2; @@ -488,7 +488,7 @@ static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, int el = arm_current_el(env); bool mdcr_el2_tda = (env->cp15.mdcr_el2 & MDCR_TDA) || (env->cp15.mdcr_el2 & MDCR_TDE) || - (env->cp15.hcr_el2 & HCR_TGE); + (arm_hcr_el2_eff(env) & HCR_TGE); if (el < 2 && mdcr_el2_tda && !arm_is_secure_below_el3(env)) { return CP_ACCESS_TRAP_EL2; @@ -4566,8 +4566,7 @@ int sve_exception_el(CPUARMState *env, int el) if (disabled) { /* route_to_el2 */ return (arm_feature(env, ARM_FEATURE_EL2) - && !arm_is_secure(env) - && (env->cp15.hcr_el2 & HCR_TGE) ? 2 : 1); + && (arm_hcr_el2_eff(env) & HCR_TGE) ? 2 : 1); } /* Check CPACR.FPEN. */ @@ -6216,9 +6215,8 @@ static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type) * and CPS are treated as illegal mode changes. */ if (write_type == CPSRWriteByInstr && - (env->cp15.hcr_el2 & HCR_TGE) && (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON && - !arm_is_secure_below_el3(env)) { + (arm_hcr_el2_eff(env) & HCR_TGE)) { return 1; } return 0; diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 0d6e89e474a..ef72361a36d 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -33,8 +33,7 @@ void raise_exception(CPUARMState *env, uint32_t excp, { CPUState *cs = CPU(arm_env_get_cpu(env)); - if ((env->cp15.hcr_el2 & HCR_TGE) && - target_el == 1 && !arm_is_secure(env)) { + if (target_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { /* * Redirect NS EL1 exceptions to NS EL2. These are reported with * their original syndrome register value, with the exception of @@ -428,9 +427,9 @@ static inline int check_wfx_trap(CPUARMState *env, bool is_wfe) * No need for ARM_FEATURE check as if HCR_EL2 doesn't exist the * bits will be zero indicating no trap. */ - if (cur_el < 2 && !arm_is_secure(env)) { - mask = (is_wfe) ? HCR_TWE : HCR_TWI; - if (env->cp15.hcr_el2 & mask) { + if (cur_el < 2) { + mask = is_wfe ? HCR_TWE : HCR_TWI; + if (arm_hcr_el2_eff(env) & mask) { return 2; } } @@ -995,7 +994,7 @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome) exception_target_el(env)); } - if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) { + if (cur_el == 1 && (arm_hcr_el2_eff(env) & HCR_TSC)) { /* In NS EL1, HCR controlled routing to EL2 has priority over SMD. * We also want an EL2 guest to be able to forbid its EL1 from * making PSCI calls into QEMU's "firmware" via HCR.TSC. @@ -1098,8 +1097,7 @@ void HELPER(exception_return)(CPUARMState *env) goto illegal_return; } - if (new_el == 1 && (env->cp15.hcr_el2 & HCR_TGE) - && !arm_is_secure_below_el3(env)) { + if (new_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { goto illegal_return; } From patchwork Thu Dec 13 14:54:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153684 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp928458ljp; Thu, 13 Dec 2018 07:22:59 -0800 (PST) X-Google-Smtp-Source: AFSGD/VI/1bhLvfSZl8PUtU2PVnk131Xa4nbKYpnZ2Fje9ciBtgaTN+AkgiNqNiCkZwCcUt3Md53 X-Received: by 2002:a0c:f184:: with SMTP id m4mr22981310qvl.178.1544714579651; Thu, 13 Dec 2018 07:22:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544714579; cv=none; d=google.com; s=arc-20160816; b=G93iKZ1ASuDALoEQmRlncTqIKMwGrGiOCSDJoGp5ndwMI0znOlgB9zaADKembX7ZHK deNbRrbE+eMgkANaNgZXoGGSniboN9q8RSAMnmgpPCNFb4c7bLyfSOq7vqyOLuRzzhHX IyNIGEacZCJ7vNEpLSJPx6l63LYJ+2H6etJXs42YgoQTxOMDMELwdN1CgUjPV1fAPdyi TKPhFSTrtdEBopS4b5yR2TCIvOHr6oN8PXwILG9eOsnW3oc7+krLi8b7xEjFuz7YMrVz GDIdkUo4ZeLlM82eLr5ikiE2lFxqR0MuFl9ZOmu9xoLRW8MWLb7DMBTwfgz3vCi+05BB kpHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=MZHt2E+g3S7Luss9CV8t7ymR214qx8QaglVscaAQ/lg=; b=hwhcuZZ/UDz14/5z/L1ZlcT9AJdqwlWa9Aw7/GlbdH37flftppsM9bH6jbIV6XJDHR IIPXdVoubiC94YPmq0SY9GQVoqYAEBXuL2Ah7DUEhI/AOzP8OTAQzbyecu0oHTMNYaZg NQwIWutWqRfuzWhwVX9fl/QvcpmeAng1MfHc07jPqnwjEIO2e6yJrZOLDDwroUwXQtoR xzbChgwdhUi7UgQc9lo/80LmCBDYomYE+w9d0jbBQ8nUGn5BfvQWvrh/cZ58MzS8lBWR IE5qgWXPFopIwNHMzRyyX91mgliXXFTC2+VHPgErAIle2pL7JAtvsGdgrTH/WF7bn1md Sj8g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 37/37] target/arm: Implement the ARMv8.1-LOR extension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Provide a trivial implementation with zero limited ordering regions, which causes the LDLAR and STLLR instructions to devolve into the LDAR and STLR instructions from the base ARMv8.0 instruction set. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20181210150501.7990-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 5 +++ target/arm/cpu64.c | 1 + target/arm/helper.c | 75 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 12 ++++++ 4 files changed, 93 insertions(+) -- 2.19.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 05ac883b6be..c943f35dd92 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3340,6 +3340,11 @@ static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; } +static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1a4289c9dda..1d57be0c910 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -326,6 +326,7 @@ static void aarch64_max_initfn(Object *obj) t = cpu->isar.id_aa64mmfr1; t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ + t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); cpu->isar.id_aa64mmfr1 = t; /* Replicate the same data to the 32-bit id registers. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index d6f8be9f4e1..644599b29d6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1281,6 +1281,7 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Begin with base v8.0 state. */ uint32_t valid_mask = 0x3fff; + ARMCPU *cpu = arm_env_get_cpu(env); if (arm_el_is_aa64(env, 3)) { value |= SCR_FW | SCR_AW; /* these two bits are RES1. */ @@ -1303,6 +1304,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) valid_mask &= ~SCR_SMD; } } + if (cpu_isar_feature(aa64_lor, cpu)) { + valid_mask |= SCR_TLOR; + } /* Clear all-context RES0 bits. */ value &= valid_mask; @@ -3963,6 +3967,9 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) */ valid_mask &= ~HCR_TSC; } + if (cpu_isar_feature(aa64_lor, cpu)) { + valid_mask |= HCR_TLOR; + } /* Clear RES0 bits. */ value &= valid_mask; @@ -5018,6 +5025,42 @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) return pfr0; } +/* Shared logic between LORID and the rest of the LOR* registers. + * Secure state has already been delt with. + */ +static CPAccessResult access_lor_ns(CPUARMState *env) +{ + int el = arm_current_el(env); + + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TLOR)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static CPAccessResult access_lorid(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_is_secure_below_el3(env)) { + /* Access ok in secure mode. */ + return CP_ACCESS_OK; + } + return access_lor_ns(env); +} + +static CPAccessResult access_lor_other(CPUARMState *env, + const ARMCPRegInfo *ri, bool isread) +{ + if (arm_is_secure_below_el3(env)) { + /* Access denied in secure mode. */ + return CP_ACCESS_TRAP; + } + return access_lor_ns(env); +} + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -5759,6 +5802,38 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &sctlr); } + if (cpu_isar_feature(aa64_lor, cpu)) { + /* + * A trivial implementation of ARMv8.1-LOR leaves all of these + * registers fixed at 0, which indicates that there are zero + * supported Limited Ordering regions. + */ + static const ARMCPRegInfo lor_reginfo[] = { + { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0, + .access = PL1_RW, .accessfn = access_lor_other, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1, + .access = PL1_RW, .accessfn = access_lor_other, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2, + .access = PL1_RW, .accessfn = access_lor_other, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3, + .access = PL1_RW, .accessfn = access_lor_other, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7, + .access = PL1_R, .accessfn = access_lorid, + .type = ARM_CP_CONST, .resetvalue = 0 }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, lor_reginfo); + } + if (cpu_isar_feature(aa64_sve, cpu)) { define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); if (arm_feature(env, ARM_FEATURE_EL2)) { diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index fd36425f1ae..e1da1e4d6f5 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2290,6 +2290,12 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) } return; + case 0x8: /* STLLR */ + if (!dc_isar_feature(aa64_lor, s)) { + break; + } + /* StoreLORelease is the same as Store-Release for QEMU. */ + /* fall through */ case 0x9: /* STLR */ /* Generate ISS for non-exclusive accesses including LASR. */ if (rn == 31) { @@ -2301,6 +2307,12 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) disas_ldst_compute_iss_sf(size, false, 0), is_lasr); return; + case 0xc: /* LDLAR */ + if (!dc_isar_feature(aa64_lor, s)) { + break; + } + /* LoadLOAcquire is the same as Load-Acquire for QEMU. */ + /* fall through */ case 0xd: /* LDAR */ /* Generate ISS for non-exclusive accesses including LASR. */ if (rn == 31) {