From patchwork Tue Apr 12 21:51:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 560069 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D45EC433EF for ; Tue, 12 Apr 2022 23:36:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231315AbiDLXh1 (ORCPT ); Tue, 12 Apr 2022 19:37:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231553AbiDLXdG (ORCPT ); Tue, 12 Apr 2022 19:33:06 -0400 Received: from mail-yb1-xb2f.google.com (mail-yb1-xb2f.google.com [IPv6:2607:f8b0:4864:20::b2f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2A457C74BB for ; Tue, 12 Apr 2022 15:22:03 -0700 (PDT) Received: by mail-yb1-xb2f.google.com with SMTP id q19so549283ybd.6 for ; Tue, 12 Apr 2022 15:22:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=3XOuGcH/wzb0FYgSoZ3ZLszM8ApqvXfZibiV9sZrmLo=; b=BrZWrhT7dRr+kE0t7Xi6nrxSpqH0LQmZdssV43z4SicclN8Tn3VifKSVry7NmQ2EJ3 okiLxssg4prKI4KsFj+QRm3s30JBs1Jv6GS9t3CiXsdBAXQu2pakxq2SF8Viyatsdg5R hMQu5Ncy4zmG1rhEMyPLkUZk1NLX0w0s3zyh1t6pXBjw9OB7qg5EJhXTr72bXwOvNOF/ xSMB+iJS4dDoP/ID8V/rCNt1TRuCngozIwyoPaBralj/QsWvex4U2smIyrvgsvfTh+bS liBk3feRPaxU66p3pND9Akue7OjhgdL51f6JFFk1PtB//c2yfdzffk8u0fd5rORWxR95 KafA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=3XOuGcH/wzb0FYgSoZ3ZLszM8ApqvXfZibiV9sZrmLo=; b=l5VKv0qm2EHLz7vozKT5fI+kZb0qduWwPZTBK8O0+cYa9+tpHtnzUo8X7iviF7VjCd M2zURAPg+VBt0+9NLI3c/8bpclvMn1L89S3/0xVj9/pWcEYnFAslDsue39X03YYvVnlT 8Tcow0gfmcFkQUA3LQ9GghffZvT/7RJpLux4iGWfOQ8WXIfmdRDljuAdyROW4E9wTdap khYqBkmB6v5bixig4wwNWGhXeTwnJ1b4pOiOHgb2hqMYtVVvQ6T6IPJQOZRIZmuNin0o EEka96/zOodfXy8T1fBR/e7Pt2o6MJ9O5tiIpcBScTISd5dww7rHbR+DuczvPdnpfukz sCXQ== X-Gm-Message-State: AOAM531A4o1l23gqdyjlAuaBSxvZb0X7FaRJIK1vuuQknbril9VarBs7 9XlmamuShTkxbYbU3UeRTHar5MlanUBnQgXv X-Google-Smtp-Source: ABdhPJyeN23iMDpJktgvucYthMc8AZYrftz2ZdA12o8XfqUauG6+RIgnfH1cxRvAfFdqFtfDS439AA== X-Received: by 2002:a05:6830:1605:b0:5c9:4fde:ba63 with SMTP id g5-20020a056830160500b005c94fdeba63mr13729362otr.84.1649800163433; Tue, 12 Apr 2022 14:49:23 -0700 (PDT) Received: from ripper.. ([2600:1700:a0:3dc8:205:1bff:fec0:b9b3]) by smtp.gmail.com with ESMTPSA id k10-20020a4abd8a000000b00324907b406fsm12809059oop.21.2022.04.12.14.49.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Apr 2022 14:49:22 -0700 (PDT) From: Bjorn Andersson To: Bjorn Andersson , Vinod Koul Cc: Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] arm64: dts: qcom: sm8350: Define GPI DMA engines Date: Tue, 12 Apr 2022 14:51:35 -0700 Message-Id: <20220412215137.2385831-1-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The Qualcomm SM8350 has three GPI DMA engines, add definitions for these. Signed-off-by: Bjorn Andersson Reviewed-by: Vinod Koul Reviewed-by: Vinod Koul --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 73 ++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index a68231634da2..7e585d9e4c68 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2020, Linaro Limited */ +#include #include #include #include @@ -678,6 +679,28 @@ opp-120000000 { }; }; + gpi_dma2: dma-controller@800000 { + compatible = "qcom,sm8350-gpi-dma"; + reg = <0 0x00800000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <12>; + dma-channel-mask = <0xff>; + iommus = <&apps_smmu 0x5f6 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + qupv3_id_2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x008c0000 0x0 0x6000>; @@ -843,12 +866,37 @@ spi19: spi@894000 { interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, + <&gpi_dma2 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; + gpi_dma0: dma-controller@900000 { + compatible = "qcom,sm8350-gpi-dma"; + reg = <0 0x09800000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <12>; + dma-channel-mask = <0x7e>; + iommus = <&apps_smmu 0x5b6 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x009c0000 0x0 0x6000>; @@ -1081,12 +1129,37 @@ spi7: spi@99c000 { interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, + <&gpi_dma0 1 7 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,sm8350-gpi-dma"; + reg = <0 0x00a00000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <12>; + dma-channel-mask = <0xff>; + iommus = <&apps_smmu 0x56 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x00ac0000 0x0 0x6000>; From patchwork Tue Apr 12 21:51:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 560070 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1936C43217 for ; Tue, 12 Apr 2022 23:33:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231233AbiDLXgK (ORCPT ); Tue, 12 Apr 2022 19:36:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231469AbiDLXdC (ORCPT ); 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([2600:1700:a0:3dc8:205:1bff:fec0:b9b3]) by smtp.gmail.com with ESMTPSA id k10-20020a4abd8a000000b00324907b406fsm12809059oop.21.2022.04.12.14.49.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Apr 2022 14:49:23 -0700 (PDT) From: Bjorn Andersson To: Bjorn Andersson , Vinod Koul Cc: Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] arm64: dts: qcom: sm8350: Add GENI I2C/SPI DMA channels Date: Tue, 12 Apr 2022 14:51:36 -0700 Message-Id: <20220412215137.2385831-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220412215137.2385831-1-bjorn.andersson@linaro.org> References: <20220412215137.2385831-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The GENI I2C and SPI controllers may use the GPI DMA engine, define the rx and tx channels for these controllers to enable this. Signed-off-by: Bjorn Andersson Reviewed-by: Vinod Koul --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 108 +++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 7e585d9e4c68..8547c0b2f060 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -721,6 +721,9 @@ i2c14: i2c@880000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c14_default>; interrupts = ; + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -734,6 +737,9 @@ spi14: spi@880000 { interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -747,6 +753,9 @@ i2c15: i2c@884000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c15_default>; interrupts = ; + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -760,6 +769,9 @@ spi15: spi@884000 { interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -773,6 +785,9 @@ i2c16: i2c@888000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c16_default>; interrupts = ; + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -786,6 +801,9 @@ spi16: spi@888000 { interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -799,6 +817,9 @@ i2c17: i2c@88c000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c17_default>; interrupts = ; + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -812,6 +833,9 @@ spi17: spi@88c000 { interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, + <&gpi_dma2 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -827,6 +851,9 @@ spi18: spi@890000 { interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, + <&gpi_dma2 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -853,6 +880,9 @@ i2c19: i2c@894000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c19_default>; interrupts = ; + dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, + <&gpi_dma2 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -917,6 +947,9 @@ i2c0: i2c@980000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c0_default>; interrupts = ; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -930,6 +963,9 @@ spi0: spi@980000 { interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -943,6 +979,9 @@ i2c1: i2c@984000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c1_default>; interrupts = ; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -956,6 +995,9 @@ spi1: spi@984000 { interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -969,6 +1011,9 @@ i2c2: i2c@988000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c2_default>; interrupts = ; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -982,6 +1027,9 @@ spi2: spi@988000 { interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1012,6 +1060,9 @@ spi3: spi@98c000 { interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1025,6 +1076,9 @@ i2c4: i2c@990000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c4_default>; interrupts = ; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1038,6 +1092,9 @@ spi4: spi@990000 { interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1051,6 +1108,9 @@ i2c5: i2c@994000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c5_default>; interrupts = ; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1064,6 +1124,9 @@ spi5: spi@994000 { interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1077,6 +1140,9 @@ i2c6: i2c@998000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c6_default>; interrupts = ; + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1090,6 +1156,9 @@ spi6: spi@998000 { interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1116,6 +1185,9 @@ i2c7: i2c@99c000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c7_default>; interrupts = ; + dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, + <&gpi_dma0 1 7 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1180,6 +1252,9 @@ i2c8: i2c@a80000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c8_default>; interrupts = ; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1193,6 +1268,9 @@ spi8: spi@a80000 { interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1206,6 +1284,9 @@ i2c9: i2c@a84000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c9_default>; interrupts = ; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1219,6 +1300,9 @@ spi9: spi@a84000 { interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1232,6 +1316,9 @@ i2c10: i2c@a88000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c10_default>; interrupts = ; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1245,6 +1332,9 @@ spi10: spi@a88000 { interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1258,6 +1348,9 @@ i2c11: i2c@a8c000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c11_default>; interrupts = ; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1271,6 +1364,9 @@ spi11: spi@a8c000 { interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1284,6 +1380,9 @@ i2c12: i2c@a90000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c12_default>; interrupts = ; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1297,6 +1396,9 @@ spi12: spi@a90000 { interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1310,6 +1412,9 @@ i2c13: i2c@a94000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c13_default>; interrupts = ; + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1323,6 +1428,9 @@ spi13: spi@a94000 { interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled";