From patchwork Tue Apr 12 10:26:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 561147 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4117EC433F5 for ; Tue, 12 Apr 2022 11:44:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229716AbiDLLq2 (ORCPT ); Tue, 12 Apr 2022 07:46:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39274 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244507AbiDLLp5 (ORCPT ); Tue, 12 Apr 2022 07:45:57 -0400 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 576077C17B for ; Tue, 12 Apr 2022 03:26:29 -0700 (PDT) Received: by mail-ej1-x631.google.com with SMTP id s18so13930507ejr.0 for ; Tue, 12 Apr 2022 03:26:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=HXiKpkIadzd2P4u3JfwfuCOW4IhV2XdgM458yctU52E=; b=b4qGd9nSnM+PBhciYSzh5ZPM+HPgzALRXnb2cmHWSQDlxWlQYkUcZ1NOFrgfiOV3qP jqlXYWa8bh2QiSPURg0D0DoxyB0IfwepkJb7I9TTsa1iYzwalUGPwauHVgCa82MFld0Y OnWfmW7prnJX+r/8Xq6ycHz2ZNtihf2SDRp1t4+OcQ2XkGIspNF04B1+4kpyamsEI/nU q4trAbxc6D42GuMBSdzh2NG8k3msZ1uUxTPYYuMN59HDGtD08AaQ88z8KrcxviwSnz5e 0nDus2KnTqA6TDvUE+gO7ic09eU6RngSB5sq334yKUub/2Biysxt5/Fvj8rhKakdSJ4H RiYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=HXiKpkIadzd2P4u3JfwfuCOW4IhV2XdgM458yctU52E=; b=UfaluI1uSCneZU8f4vv5/jgipO2UF58l1p4dB6vgRIq4VXZbHSTww2cd2OpJ0v/+WJ A7vzbmYGTBggoUQmZsjpmTPadheqUHpnlseXBNPvgFhGRBckaX4rkXJ/IQT9hJmj32/K WFM0Xym4YcZ0no+rOdI1LC9xBbkjYBPATCijylqJRqNfzphU6jqbIaAIJ3vMm9w8Ky4C JZN6BuvW2k6BrSaZa0SCsYglJ1aeNYa1VoxLkdAwyQSa1IqKO4PFCGagV1WvGrV/+3qE OGNISOvHbtqoyv9jBKHtRrqyO91pN9zLuxxaZ4xt2VoK0c6hM5JlyJ/+r/LvGYw8vfAT XNZg== X-Gm-Message-State: AOAM530b2gYNfJ4F7g4sbDA0mBHqUCVVVW2yGEgl0uyVM0Zb3h7yGtDA rRg7Jq1gOk8OMlH2DK/E5jHaBQ== X-Google-Smtp-Source: ABdhPJxXr03utmF+YxUUq+UGPDVcVrCMHiSwonejxWoHCiI/qU5H2I5OMvirmeFdoOjoMuH+tXqZ+g== X-Received: by 2002:a17:906:d055:b0:6e8:6cc1:124c with SMTP id bo21-20020a170906d05500b006e86cc1124cmr15043383ejb.758.1649759187812; Tue, 12 Apr 2022 03:26:27 -0700 (PDT) Received: from localhost.localdomain (xdsl-188-155-201-27.adslplus.ch. [188.155.201.27]) by smtp.gmail.com with ESMTPSA id z21-20020a170906435500b006e8669fae36sm4468959ejm.189.2022.04.12.03.26.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Apr 2022 03:26:27 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Georgi Djakov , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 1/3] interconnect: qcom: constify qcom_icc_desc Date: Tue, 12 Apr 2022 12:26:21 +0200 Message-Id: <20220412102623.227607-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org struct qcom_icc_desc is not modified so it can be made const for safety. Signed-off-by: Krzysztof Kozlowski --- drivers/interconnect/qcom/msm8916.c | 6 +++--- drivers/interconnect/qcom/msm8939.c | 8 ++++---- drivers/interconnect/qcom/msm8974.c | 12 ++++++------ drivers/interconnect/qcom/qcm2290.c | 12 ++++++------ drivers/interconnect/qcom/qcs404.c | 6 +++--- drivers/interconnect/qcom/sc7180.c | 26 +++++++++++++------------- drivers/interconnect/qcom/sc7280.c | 24 ++++++++++++------------ drivers/interconnect/qcom/sdm660.c | 12 ++++++------ drivers/interconnect/qcom/sm8150.c | 22 +++++++++++----------- drivers/interconnect/qcom/sm8250.c | 22 +++++++++++----------- drivers/interconnect/qcom/sm8350.c | 20 ++++++++++---------- drivers/interconnect/qcom/sm8450.c | 22 +++++++++++----------- 12 files changed, 96 insertions(+), 96 deletions(-) diff --git a/drivers/interconnect/qcom/msm8916.c b/drivers/interconnect/qcom/msm8916.c index 2f397a7c3322..4dc122ce9805 100644 --- a/drivers/interconnect/qcom/msm8916.c +++ b/drivers/interconnect/qcom/msm8916.c @@ -1228,7 +1228,7 @@ static const struct regmap_config msm8916_snoc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc msm8916_snoc = { +static const struct qcom_icc_desc msm8916_snoc = { .type = QCOM_ICC_NOC, .nodes = msm8916_snoc_nodes, .num_nodes = ARRAY_SIZE(msm8916_snoc_nodes), @@ -1256,7 +1256,7 @@ static const struct regmap_config msm8916_bimc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc msm8916_bimc = { +static const struct qcom_icc_desc msm8916_bimc = { .type = QCOM_ICC_BIMC, .nodes = msm8916_bimc_nodes, .num_nodes = ARRAY_SIZE(msm8916_bimc_nodes), @@ -1325,7 +1325,7 @@ static const struct regmap_config msm8916_pcnoc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc msm8916_pcnoc = { +static const struct qcom_icc_desc msm8916_pcnoc = { .type = QCOM_ICC_NOC, .nodes = msm8916_pcnoc_nodes, .num_nodes = ARRAY_SIZE(msm8916_pcnoc_nodes), diff --git a/drivers/interconnect/qcom/msm8939.c b/drivers/interconnect/qcom/msm8939.c index f9c2d7d3100d..7838e332ee41 100644 --- a/drivers/interconnect/qcom/msm8939.c +++ b/drivers/interconnect/qcom/msm8939.c @@ -1281,7 +1281,7 @@ static const struct regmap_config msm8939_snoc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc msm8939_snoc = { +static const struct qcom_icc_desc msm8939_snoc = { .type = QCOM_ICC_NOC, .nodes = msm8939_snoc_nodes, .num_nodes = ARRAY_SIZE(msm8939_snoc_nodes), @@ -1301,7 +1301,7 @@ static struct qcom_icc_node *msm8939_snoc_mm_nodes[] = { [SNOC_MM_INT_2] = &mm_int_2, }; -static struct qcom_icc_desc msm8939_snoc_mm = { +static const struct qcom_icc_desc msm8939_snoc_mm = { .type = QCOM_ICC_NOC, .nodes = msm8939_snoc_mm_nodes, .num_nodes = ARRAY_SIZE(msm8939_snoc_mm_nodes), @@ -1329,7 +1329,7 @@ static const struct regmap_config msm8939_bimc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc msm8939_bimc = { +static const struct qcom_icc_desc msm8939_bimc = { .type = QCOM_ICC_BIMC, .nodes = msm8939_bimc_nodes, .num_nodes = ARRAY_SIZE(msm8939_bimc_nodes), @@ -1400,7 +1400,7 @@ static const struct regmap_config msm8939_pcnoc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc msm8939_pcnoc = { +static const struct qcom_icc_desc msm8939_pcnoc = { .type = QCOM_ICC_NOC, .nodes = msm8939_pcnoc_nodes, .num_nodes = ARRAY_SIZE(msm8939_pcnoc_nodes), diff --git a/drivers/interconnect/qcom/msm8974.c b/drivers/interconnect/qcom/msm8974.c index da68ce375a89..2eebe421f262 100644 --- a/drivers/interconnect/qcom/msm8974.c +++ b/drivers/interconnect/qcom/msm8974.c @@ -254,7 +254,7 @@ static struct msm8974_icc_node *msm8974_bimc_nodes[] = { [BIMC_SLV_AMPSS_L2] = &slv_ampss_l2, }; -static struct msm8974_icc_desc msm8974_bimc = { +static const struct msm8974_icc_desc msm8974_bimc = { .nodes = msm8974_bimc_nodes, .num_nodes = ARRAY_SIZE(msm8974_bimc_nodes), }; @@ -337,7 +337,7 @@ static struct msm8974_icc_node *msm8974_cnoc_nodes[] = { [CNOC_SLV_SERVICE_CNOC] = &slv_service_cnoc, }; -static struct msm8974_icc_desc msm8974_cnoc = { +static const struct msm8974_icc_desc msm8974_cnoc = { .nodes = msm8974_cnoc_nodes, .num_nodes = ARRAY_SIZE(msm8974_cnoc_nodes), }; @@ -390,7 +390,7 @@ static struct msm8974_icc_node *msm8974_mnoc_nodes[] = { [MNOC_SLV_SERVICE_MNOC] = &slv_service_mnoc, }; -static struct msm8974_icc_desc msm8974_mnoc = { +static const struct msm8974_icc_desc msm8974_mnoc = { .nodes = msm8974_mnoc_nodes, .num_nodes = ARRAY_SIZE(msm8974_mnoc_nodes), }; @@ -425,7 +425,7 @@ static struct msm8974_icc_node *msm8974_onoc_nodes[] = { [OCMEM_SLV_OCMEM] = &slv_ocmem, }; -static struct msm8974_icc_desc msm8974_onoc = { +static const struct msm8974_icc_desc msm8974_onoc = { .nodes = msm8974_onoc_nodes, .num_nodes = ARRAY_SIZE(msm8974_onoc_nodes), }; @@ -488,7 +488,7 @@ static struct msm8974_icc_node *msm8974_pnoc_nodes[] = { [PNOC_SLV_SERVICE_PNOC] = &slv_service_pnoc, }; -static struct msm8974_icc_desc msm8974_pnoc = { +static const struct msm8974_icc_desc msm8974_pnoc = { .nodes = msm8974_pnoc_nodes, .num_nodes = ARRAY_SIZE(msm8974_pnoc_nodes), }; @@ -545,7 +545,7 @@ static struct msm8974_icc_node *msm8974_snoc_nodes[] = { [SNOC_SLV_QDSS_STM] = &slv_qdss_stm, }; -static struct msm8974_icc_desc msm8974_snoc = { +static const struct msm8974_icc_desc msm8974_snoc = { .nodes = msm8974_snoc_nodes, .num_nodes = ARRAY_SIZE(msm8974_snoc_nodes), }; diff --git a/drivers/interconnect/qcom/qcm2290.c b/drivers/interconnect/qcom/qcm2290.c index 74404e0b2080..644dcd90e7ad 100644 --- a/drivers/interconnect/qcom/qcm2290.c +++ b/drivers/interconnect/qcom/qcm2290.c @@ -1193,7 +1193,7 @@ static const struct regmap_config qcm2290_bimc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc qcm2290_bimc = { +static const struct qcom_icc_desc qcm2290_bimc = { .type = QCOM_ICC_BIMC, .nodes = qcm2290_bimc_nodes, .num_nodes = ARRAY_SIZE(qcm2290_bimc_nodes), @@ -1248,7 +1248,7 @@ static const struct regmap_config qcm2290_cnoc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc qcm2290_cnoc = { +static const struct qcom_icc_desc qcm2290_cnoc = { .type = QCOM_ICC_NOC, .nodes = qcm2290_cnoc_nodes, .num_nodes = ARRAY_SIZE(qcm2290_cnoc_nodes), @@ -1289,7 +1289,7 @@ static const struct regmap_config qcm2290_snoc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc qcm2290_snoc = { +static const struct qcom_icc_desc qcm2290_snoc = { .type = QCOM_ICC_QNOC, .nodes = qcm2290_snoc_nodes, .num_nodes = ARRAY_SIZE(qcm2290_snoc_nodes), @@ -1303,7 +1303,7 @@ static struct qcom_icc_node *qcm2290_qup_virt_nodes[] = { [SLAVE_QUP_CORE_0] = &slv_qup_core_0 }; -static struct qcom_icc_desc qcm2290_qup_virt = { +static const struct qcom_icc_desc qcm2290_qup_virt = { .type = QCOM_ICC_QNOC, .nodes = qcm2290_qup_virt_nodes, .num_nodes = ARRAY_SIZE(qcm2290_qup_virt_nodes), @@ -1316,7 +1316,7 @@ static struct qcom_icc_node *qcm2290_mmnrt_virt_nodes[] = { [SLAVE_SNOC_BIMC_NRT] = &slv_snoc_bimc_nrt, }; -static struct qcom_icc_desc qcm2290_mmnrt_virt = { +static const struct qcom_icc_desc qcm2290_mmnrt_virt = { .type = QCOM_ICC_QNOC, .nodes = qcm2290_mmnrt_virt_nodes, .num_nodes = ARRAY_SIZE(qcm2290_mmnrt_virt_nodes), @@ -1330,7 +1330,7 @@ static struct qcom_icc_node *qcm2290_mmrt_virt_nodes[] = { [SLAVE_SNOC_BIMC_RT] = &slv_snoc_bimc_rt, }; -static struct qcom_icc_desc qcm2290_mmrt_virt = { +static const struct qcom_icc_desc qcm2290_mmrt_virt = { .type = QCOM_ICC_QNOC, .nodes = qcm2290_mmrt_virt_nodes, .num_nodes = ARRAY_SIZE(qcm2290_mmrt_virt_nodes), diff --git a/drivers/interconnect/qcom/qcs404.c b/drivers/interconnect/qcom/qcs404.c index 416c8bff8efa..d5020b2b2236 100644 --- a/drivers/interconnect/qcom/qcs404.c +++ b/drivers/interconnect/qcom/qcs404.c @@ -984,7 +984,7 @@ static struct qcom_icc_node *qcs404_bimc_nodes[] = { [SLAVE_BIMC_SNOC] = &slv_bimc_snoc, }; -static struct qcom_icc_desc qcs404_bimc = { +static const struct qcom_icc_desc qcs404_bimc = { .nodes = qcs404_bimc_nodes, .num_nodes = ARRAY_SIZE(qcs404_bimc_nodes), }; @@ -1038,7 +1038,7 @@ static struct qcom_icc_node *qcs404_pcnoc_nodes[] = { [SLAVE_PCNOC_SNOC] = &slv_pcnoc_snoc, }; -static struct qcom_icc_desc qcs404_pcnoc = { +static const struct qcom_icc_desc qcs404_pcnoc = { .nodes = qcs404_pcnoc_nodes, .num_nodes = ARRAY_SIZE(qcs404_pcnoc_nodes), }; @@ -1066,7 +1066,7 @@ static struct qcom_icc_node *qcs404_snoc_nodes[] = { [SLAVE_LPASS] = &slv_lpass, }; -static struct qcom_icc_desc qcs404_snoc = { +static const struct qcom_icc_desc qcs404_snoc = { .nodes = qcs404_snoc_nodes, .num_nodes = ARRAY_SIZE(qcs404_snoc_nodes), }; diff --git a/drivers/interconnect/qcom/sc7180.c b/drivers/interconnect/qcom/sc7180.c index 12d59c36df53..712b50d4b1c3 100644 --- a/drivers/interconnect/qcom/sc7180.c +++ b/drivers/interconnect/qcom/sc7180.c @@ -196,7 +196,7 @@ static struct qcom_icc_node *aggre1_noc_nodes[] = { [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, }; -static struct qcom_icc_desc sc7180_aggre1_noc = { +static const struct qcom_icc_desc sc7180_aggre1_noc = { .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -219,7 +219,7 @@ static struct qcom_icc_node *aggre2_noc_nodes[] = { [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, }; -static struct qcom_icc_desc sc7180_aggre2_noc = { +static const struct qcom_icc_desc sc7180_aggre2_noc = { .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -237,7 +237,7 @@ static struct qcom_icc_node *camnoc_virt_nodes[] = { [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp, }; -static struct qcom_icc_desc sc7180_camnoc_virt = { +static const struct qcom_icc_desc sc7180_camnoc_virt = { .nodes = camnoc_virt_nodes, .num_nodes = ARRAY_SIZE(camnoc_virt_nodes), .bcms = camnoc_virt_bcms, @@ -256,7 +256,7 @@ static struct qcom_icc_node *compute_noc_nodes[] = { [SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc, }; -static struct qcom_icc_desc sc7180_compute_noc = { +static const struct qcom_icc_desc sc7180_compute_noc = { .nodes = compute_noc_nodes, .num_nodes = ARRAY_SIZE(compute_noc_nodes), .bcms = compute_noc_bcms, @@ -324,7 +324,7 @@ static struct qcom_icc_node *config_noc_nodes[] = { [SLAVE_SERVICE_CNOC] = &srvc_cnoc, }; -static struct qcom_icc_desc sc7180_config_noc = { +static const struct qcom_icc_desc sc7180_config_noc = { .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -337,7 +337,7 @@ static struct qcom_icc_node *dc_noc_nodes[] = { [SLAVE_LLCC_CFG] = &qhs_llcc, }; -static struct qcom_icc_desc sc7180_dc_noc = { +static const struct qcom_icc_desc sc7180_dc_noc = { .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), }; @@ -365,7 +365,7 @@ static struct qcom_icc_node *gem_noc_nodes[] = { [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc, }; -static struct qcom_icc_desc sc7180_gem_noc = { +static const struct qcom_icc_desc sc7180_gem_noc = { .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -381,7 +381,7 @@ static struct qcom_icc_node *ipa_virt_nodes[] = { [SLAVE_IPA_CORE] = &ipa_core_slave, }; -static struct qcom_icc_desc sc7180_ipa_virt = { +static const struct qcom_icc_desc sc7180_ipa_virt = { .nodes = ipa_virt_nodes, .num_nodes = ARRAY_SIZE(ipa_virt_nodes), .bcms = ipa_virt_bcms, @@ -398,7 +398,7 @@ static struct qcom_icc_node *mc_virt_nodes[] = { [SLAVE_EBI1] = &ebi, }; -static struct qcom_icc_desc sc7180_mc_virt = { +static const struct qcom_icc_desc sc7180_mc_virt = { .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -425,7 +425,7 @@ static struct qcom_icc_node *mmss_noc_nodes[] = { [SLAVE_SERVICE_MNOC] = &srvc_mnoc, }; -static struct qcom_icc_desc sc7180_mmss_noc = { +static const struct qcom_icc_desc sc7180_mmss_noc = { .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -446,7 +446,7 @@ static struct qcom_icc_node *npu_noc_nodes[] = { [SLAVE_SERVICE_NPU_NOC] = &srvc_noc, }; -static struct qcom_icc_desc sc7180_npu_noc = { +static const struct qcom_icc_desc sc7180_npu_noc = { .nodes = npu_noc_nodes, .num_nodes = ARRAY_SIZE(npu_noc_nodes), }; @@ -462,7 +462,7 @@ static struct qcom_icc_node *qup_virt_nodes[] = { [SLAVE_QUP_CORE_1] = &qup_core_slave_2, }; -static struct qcom_icc_desc sc7180_qup_virt = { +static const struct qcom_icc_desc sc7180_qup_virt = { .nodes = qup_virt_nodes, .num_nodes = ARRAY_SIZE(qup_virt_nodes), .bcms = qup_virt_bcms, @@ -497,7 +497,7 @@ static struct qcom_icc_node *system_noc_nodes[] = { [SLAVE_TCU] = &xs_sys_tcu_cfg, }; -static struct qcom_icc_desc sc7180_system_noc = { +static const struct qcom_icc_desc sc7180_system_noc = { .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sc7280.c b/drivers/interconnect/qcom/sc7280.c index f8b34f6cbb0d..0464e5eb6a32 100644 --- a/drivers/interconnect/qcom/sc7280.c +++ b/drivers/interconnect/qcom/sc7280.c @@ -1500,7 +1500,7 @@ static struct qcom_icc_node *aggre1_noc_nodes[] = { [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, }; -static struct qcom_icc_desc sc7280_aggre1_noc = { +static const struct qcom_icc_desc sc7280_aggre1_noc = { .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1522,7 +1522,7 @@ static struct qcom_icc_node *aggre2_noc_nodes[] = { [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, }; -static struct qcom_icc_desc sc7280_aggre2_noc = { +static const struct qcom_icc_desc sc7280_aggre2_noc = { .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1541,7 +1541,7 @@ static struct qcom_icc_node *clk_virt_nodes[] = { [SLAVE_QUP_CORE_1] = &qup1_core_slave, }; -static struct qcom_icc_desc sc7280_clk_virt = { +static const struct qcom_icc_desc sc7280_clk_virt = { .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, @@ -1603,7 +1603,7 @@ static struct qcom_icc_node *cnoc2_nodes[] = { [SLAVE_SNOC_CFG] = &qns_snoc_cfg, }; -static struct qcom_icc_desc sc7280_cnoc2 = { +static const struct qcom_icc_desc sc7280_cnoc2 = { .nodes = cnoc2_nodes, .num_nodes = ARRAY_SIZE(cnoc2_nodes), .bcms = cnoc2_bcms, @@ -1635,7 +1635,7 @@ static struct qcom_icc_node *cnoc3_nodes[] = { [SLAVE_TCU] = &xs_sys_tcu_cfg, }; -static struct qcom_icc_desc sc7280_cnoc3 = { +static const struct qcom_icc_desc sc7280_cnoc3 = { .nodes = cnoc3_nodes, .num_nodes = ARRAY_SIZE(cnoc3_nodes), .bcms = cnoc3_bcms, @@ -1651,7 +1651,7 @@ static struct qcom_icc_node *dc_noc_nodes[] = { [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, }; -static struct qcom_icc_desc sc7280_dc_noc = { +static const struct qcom_icc_desc sc7280_dc_noc = { .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), .bcms = dc_noc_bcms, @@ -1687,7 +1687,7 @@ static struct qcom_icc_node *gem_noc_nodes[] = { [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc, }; -static struct qcom_icc_desc sc7280_gem_noc = { +static const struct qcom_icc_desc sc7280_gem_noc = { .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1707,7 +1707,7 @@ static struct qcom_icc_node *lpass_ag_noc_nodes[] = { [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, }; -static struct qcom_icc_desc sc7280_lpass_ag_noc = { +static const struct qcom_icc_desc sc7280_lpass_ag_noc = { .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), .bcms = lpass_ag_noc_bcms, @@ -1724,7 +1724,7 @@ static struct qcom_icc_node *mc_virt_nodes[] = { [SLAVE_EBI1] = &ebi, }; -static struct qcom_icc_desc sc7280_mc_virt = { +static const struct qcom_icc_desc sc7280_mc_virt = { .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1751,7 +1751,7 @@ static struct qcom_icc_node *mmss_noc_nodes[] = { [SLAVE_SERVICE_MNOC] = &srvc_mnoc, }; -static struct qcom_icc_desc sc7280_mmss_noc = { +static const struct qcom_icc_desc sc7280_mmss_noc = { .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1770,7 +1770,7 @@ static struct qcom_icc_node *nsp_noc_nodes[] = { [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, }; -static struct qcom_icc_desc sc7280_nsp_noc = { +static const struct qcom_icc_desc sc7280_nsp_noc = { .nodes = nsp_noc_nodes, .num_nodes = ARRAY_SIZE(nsp_noc_nodes), .bcms = nsp_noc_bcms, @@ -1795,7 +1795,7 @@ static struct qcom_icc_node *system_noc_nodes[] = { [SLAVE_SERVICE_SNOC] = &srvc_snoc, }; -static struct qcom_icc_desc sc7280_system_noc = { +static const struct qcom_icc_desc sc7280_system_noc = { .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sdm660.c b/drivers/interconnect/qcom/sdm660.c index 274a7139fe1a..5bfc724e4c16 100644 --- a/drivers/interconnect/qcom/sdm660.c +++ b/drivers/interconnect/qcom/sdm660.c @@ -1512,7 +1512,7 @@ static const struct regmap_config sdm660_a2noc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc sdm660_a2noc = { +static const struct qcom_icc_desc sdm660_a2noc = { .type = QCOM_ICC_NOC, .nodes = sdm660_a2noc_nodes, .num_nodes = ARRAY_SIZE(sdm660_a2noc_nodes), @@ -1540,7 +1540,7 @@ static const struct regmap_config sdm660_bimc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc sdm660_bimc = { +static const struct qcom_icc_desc sdm660_bimc = { .type = QCOM_ICC_BIMC, .nodes = sdm660_bimc_nodes, .num_nodes = ARRAY_SIZE(sdm660_bimc_nodes), @@ -1594,7 +1594,7 @@ static const struct regmap_config sdm660_cnoc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc sdm660_cnoc = { +static const struct qcom_icc_desc sdm660_cnoc = { .type = QCOM_ICC_NOC, .nodes = sdm660_cnoc_nodes, .num_nodes = ARRAY_SIZE(sdm660_cnoc_nodes), @@ -1615,7 +1615,7 @@ static const struct regmap_config sdm660_gnoc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc sdm660_gnoc = { +static const struct qcom_icc_desc sdm660_gnoc = { .type = QCOM_ICC_NOC, .nodes = sdm660_gnoc_nodes, .num_nodes = ARRAY_SIZE(sdm660_gnoc_nodes), @@ -1655,7 +1655,7 @@ static const struct regmap_config sdm660_mnoc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc sdm660_mnoc = { +static const struct qcom_icc_desc sdm660_mnoc = { .type = QCOM_ICC_NOC, .nodes = sdm660_mnoc_nodes, .num_nodes = ARRAY_SIZE(sdm660_mnoc_nodes), @@ -1692,7 +1692,7 @@ static const struct regmap_config sdm660_snoc_regmap_config = { .fast_io = true, }; -static struct qcom_icc_desc sdm660_snoc = { +static const struct qcom_icc_desc sdm660_snoc = { .type = QCOM_ICC_NOC, .nodes = sdm660_snoc_nodes, .num_nodes = ARRAY_SIZE(sdm660_snoc_nodes), diff --git a/drivers/interconnect/qcom/sm8150.c b/drivers/interconnect/qcom/sm8150.c index 745e3c36a61a..4f3bdc530dcf 100644 --- a/drivers/interconnect/qcom/sm8150.c +++ b/drivers/interconnect/qcom/sm8150.c @@ -202,7 +202,7 @@ static struct qcom_icc_node *aggre1_noc_nodes[] = { [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, }; -static struct qcom_icc_desc sm8150_aggre1_noc = { +static const struct qcom_icc_desc sm8150_aggre1_noc = { .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -237,7 +237,7 @@ static struct qcom_icc_node *aggre2_noc_nodes[] = { [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, }; -static struct qcom_icc_desc sm8150_aggre2_noc = { +static const struct qcom_icc_desc sm8150_aggre2_noc = { .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -255,7 +255,7 @@ static struct qcom_icc_node *camnoc_virt_nodes[] = { [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp, }; -static struct qcom_icc_desc sm8150_camnoc_virt = { +static const struct qcom_icc_desc sm8150_camnoc_virt = { .nodes = camnoc_virt_nodes, .num_nodes = ARRAY_SIZE(camnoc_virt_nodes), .bcms = camnoc_virt_bcms, @@ -272,7 +272,7 @@ static struct qcom_icc_node *compute_noc_nodes[] = { [SLAVE_CDSP_MEM_NOC] = &qns_cdsp_mem_noc, }; -static struct qcom_icc_desc sm8150_compute_noc = { +static const struct qcom_icc_desc sm8150_compute_noc = { .nodes = compute_noc_nodes, .num_nodes = ARRAY_SIZE(compute_noc_nodes), .bcms = compute_noc_bcms, @@ -340,7 +340,7 @@ static struct qcom_icc_node *config_noc_nodes[] = { [SLAVE_SERVICE_CNOC] = &srvc_cnoc, }; -static struct qcom_icc_desc sm8150_config_noc = { +static const struct qcom_icc_desc sm8150_config_noc = { .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -356,7 +356,7 @@ static struct qcom_icc_node *dc_noc_nodes[] = { [SLAVE_GEM_NOC_CFG] = &qhs_memnoc, }; -static struct qcom_icc_desc sm8150_dc_noc = { +static const struct qcom_icc_desc sm8150_dc_noc = { .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), .bcms = dc_noc_bcms, @@ -391,7 +391,7 @@ static struct qcom_icc_node *gem_noc_nodes[] = { [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc, }; -static struct qcom_icc_desc sm8150_gem_noc = { +static const struct qcom_icc_desc sm8150_gem_noc = { .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -407,7 +407,7 @@ static struct qcom_icc_node *ipa_virt_nodes[] = { [SLAVE_IPA_CORE] = &ipa_core_slave, }; -static struct qcom_icc_desc sm8150_ipa_virt = { +static const struct qcom_icc_desc sm8150_ipa_virt = { .nodes = ipa_virt_nodes, .num_nodes = ARRAY_SIZE(ipa_virt_nodes), .bcms = ipa_virt_bcms, @@ -424,7 +424,7 @@ static struct qcom_icc_node *mc_virt_nodes[] = { [SLAVE_EBI_CH0] = &ebi, }; -static struct qcom_icc_desc sm8150_mc_virt = { +static const struct qcom_icc_desc sm8150_mc_virt = { .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -454,7 +454,7 @@ static struct qcom_icc_node *mmss_noc_nodes[] = { [SLAVE_SERVICE_MNOC] = &srvc_mnoc, }; -static struct qcom_icc_desc sm8150_mmss_noc = { +static const struct qcom_icc_desc sm8150_mmss_noc = { .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -495,7 +495,7 @@ static struct qcom_icc_node *system_noc_nodes[] = { [SLAVE_TCU] = &xs_sys_tcu_cfg, }; -static struct qcom_icc_desc sm8150_system_noc = { +static const struct qcom_icc_desc sm8150_system_noc = { .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm8250.c b/drivers/interconnect/qcom/sm8250.c index aa707582ea01..b2e12b01a5e8 100644 --- a/drivers/interconnect/qcom/sm8250.c +++ b/drivers/interconnect/qcom/sm8250.c @@ -216,7 +216,7 @@ static struct qcom_icc_node *aggre1_noc_nodes[] = { [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, }; -static struct qcom_icc_desc sm8250_aggre1_noc = { +static const struct qcom_icc_desc sm8250_aggre1_noc = { .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -246,7 +246,7 @@ static struct qcom_icc_node *aggre2_noc_nodes[] = { [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, }; -static struct qcom_icc_desc sm8250_aggre2_noc = { +static const struct qcom_icc_desc sm8250_aggre2_noc = { .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -263,7 +263,7 @@ static struct qcom_icc_node *compute_noc_nodes[] = { [SLAVE_CDSP_MEM_NOC] = &qns_cdsp_mem_noc, }; -static struct qcom_icc_desc sm8250_compute_noc = { +static const struct qcom_icc_desc sm8250_compute_noc = { .nodes = compute_noc_nodes, .num_nodes = ARRAY_SIZE(compute_noc_nodes), .bcms = compute_noc_bcms, @@ -329,7 +329,7 @@ static struct qcom_icc_node *config_noc_nodes[] = { [SLAVE_SERVICE_CNOC] = &srvc_cnoc, }; -static struct qcom_icc_desc sm8250_config_noc = { +static const struct qcom_icc_desc sm8250_config_noc = { .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -345,7 +345,7 @@ static struct qcom_icc_node *dc_noc_nodes[] = { [SLAVE_GEM_NOC_CFG] = &qhs_memnoc, }; -static struct qcom_icc_desc sm8250_dc_noc = { +static const struct qcom_icc_desc sm8250_dc_noc = { .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), .bcms = dc_noc_bcms, @@ -379,7 +379,7 @@ static struct qcom_icc_node *gem_noc_nodes[] = { [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc, }; -static struct qcom_icc_desc sm8250_gem_noc = { +static const struct qcom_icc_desc sm8250_gem_noc = { .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -395,7 +395,7 @@ static struct qcom_icc_node *ipa_virt_nodes[] = { [SLAVE_IPA_CORE] = &ipa_core_slave, }; -static struct qcom_icc_desc sm8250_ipa_virt = { +static const struct qcom_icc_desc sm8250_ipa_virt = { .nodes = ipa_virt_nodes, .num_nodes = ARRAY_SIZE(ipa_virt_nodes), .bcms = ipa_virt_bcms, @@ -412,7 +412,7 @@ static struct qcom_icc_node *mc_virt_nodes[] = { [SLAVE_EBI_CH0] = &ebi, }; -static struct qcom_icc_desc sm8250_mc_virt = { +static const struct qcom_icc_desc sm8250_mc_virt = { .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -442,7 +442,7 @@ static struct qcom_icc_node *mmss_noc_nodes[] = { [SLAVE_SERVICE_MNOC] = &srvc_mnoc, }; -static struct qcom_icc_desc sm8250_mmss_noc = { +static const struct qcom_icc_desc sm8250_mmss_noc = { .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -468,7 +468,7 @@ static struct qcom_icc_node *npu_noc_nodes[] = { [SLAVE_SERVICE_NPU_NOC] = &srvc_noc, }; -static struct qcom_icc_desc sm8250_npu_noc = { +static const struct qcom_icc_desc sm8250_npu_noc = { .nodes = npu_noc_nodes, .num_nodes = ARRAY_SIZE(npu_noc_nodes), .bcms = npu_noc_bcms, @@ -511,7 +511,7 @@ static struct qcom_icc_node *system_noc_nodes[] = { [SLAVE_TCU] = &xs_sys_tcu_cfg, }; -static struct qcom_icc_desc sm8250_system_noc = { +static const struct qcom_icc_desc sm8250_system_noc = { .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm8350.c b/drivers/interconnect/qcom/sm8350.c index c79f93a1ac73..936164391d6a 100644 --- a/drivers/interconnect/qcom/sm8350.c +++ b/drivers/interconnect/qcom/sm8350.c @@ -213,7 +213,7 @@ static struct qcom_icc_node *aggre1_noc_nodes[] = { [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, }; -static struct qcom_icc_desc sm8350_aggre1_noc = { +static const struct qcom_icc_desc sm8350_aggre1_noc = { .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -244,7 +244,7 @@ static struct qcom_icc_node *aggre2_noc_nodes[] = { [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, }; -static struct qcom_icc_desc sm8350_aggre2_noc = { +static const struct qcom_icc_desc sm8350_aggre2_noc = { .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -323,7 +323,7 @@ static struct qcom_icc_node *config_noc_nodes[] = { [SLAVE_TCU] = &xs_sys_tcu_cfg, }; -static struct qcom_icc_desc sm8350_config_noc = { +static const struct qcom_icc_desc sm8350_config_noc = { .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -339,7 +339,7 @@ static struct qcom_icc_node *dc_noc_nodes[] = { [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, }; -static struct qcom_icc_desc sm8350_dc_noc = { +static const struct qcom_icc_desc sm8350_dc_noc = { .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), .bcms = dc_noc_bcms, @@ -379,7 +379,7 @@ static struct qcom_icc_node *gem_noc_nodes[] = { [SLAVE_LLCC_DISP] = &qns_llcc_disp, }; -static struct qcom_icc_desc sm8350_gem_noc = { +static const struct qcom_icc_desc sm8350_gem_noc = { .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -399,7 +399,7 @@ static struct qcom_icc_node *lpass_ag_noc_nodes[] = { [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, }; -static struct qcom_icc_desc sm8350_lpass_ag_noc = { +static const struct qcom_icc_desc sm8350_lpass_ag_noc = { .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), .bcms = lpass_ag_noc_bcms, @@ -420,7 +420,7 @@ static struct qcom_icc_node *mc_virt_nodes[] = { [SLAVE_EBI1_DISP] = &ebi_disp, }; -static struct qcom_icc_desc sm8350_mc_virt = { +static const struct qcom_icc_desc sm8350_mc_virt = { .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -459,7 +459,7 @@ static struct qcom_icc_node *mmss_noc_nodes[] = { [SLAVE_MNOC_SF_MEM_NOC_DISP] = &qns_mem_noc_sf_disp, }; -static struct qcom_icc_desc sm8350_mmss_noc = { +static const struct qcom_icc_desc sm8350_mmss_noc = { .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -478,7 +478,7 @@ static struct qcom_icc_node *nsp_noc_nodes[] = { [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, }; -static struct qcom_icc_desc sm8350_compute_noc = { +static const struct qcom_icc_desc sm8350_compute_noc = { .nodes = nsp_noc_nodes, .num_nodes = ARRAY_SIZE(nsp_noc_nodes), .bcms = nsp_noc_bcms, @@ -503,7 +503,7 @@ static struct qcom_icc_node *system_noc_nodes[] = { [SLAVE_SERVICE_SNOC] = &srvc_snoc, }; -static struct qcom_icc_desc sm8350_system_noc = { +static const struct qcom_icc_desc sm8350_system_noc = { .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, diff --git a/drivers/interconnect/qcom/sm8450.c b/drivers/interconnect/qcom/sm8450.c index 8d99ee6421df..dbec8228e2e4 100644 --- a/drivers/interconnect/qcom/sm8450.c +++ b/drivers/interconnect/qcom/sm8450.c @@ -1540,7 +1540,7 @@ static struct qcom_icc_node *aggre1_noc_nodes[] = { [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, }; -static struct qcom_icc_desc sm8450_aggre1_noc = { +static const struct qcom_icc_desc sm8450_aggre1_noc = { .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, @@ -1567,7 +1567,7 @@ static struct qcom_icc_node *aggre2_noc_nodes[] = { [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, }; -static struct qcom_icc_desc sm8450_aggre2_noc = { +static const struct qcom_icc_desc sm8450_aggre2_noc = { .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1589,7 +1589,7 @@ static struct qcom_icc_node *clk_virt_nodes[] = { [SLAVE_QUP_CORE_2] = &qup2_core_slave, }; -static struct qcom_icc_desc sm8450_clk_virt = { +static const struct qcom_icc_desc sm8450_clk_virt = { .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, @@ -1658,7 +1658,7 @@ static struct qcom_icc_node *config_noc_nodes[] = { [SLAVE_TCU] = &xs_sys_tcu_cfg, }; -static struct qcom_icc_desc sm8450_config_noc = { +static const struct qcom_icc_desc sm8450_config_noc = { .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1693,7 +1693,7 @@ static struct qcom_icc_node *gem_noc_nodes[] = { [SLAVE_LLCC_DISP] = &qns_llcc_disp, }; -static struct qcom_icc_desc sm8450_gem_noc = { +static const struct qcom_icc_desc sm8450_gem_noc = { .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1715,7 +1715,7 @@ static struct qcom_icc_node *lpass_ag_noc_nodes[] = { [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, }; -static struct qcom_icc_desc sm8450_lpass_ag_noc = { +static const struct qcom_icc_desc sm8450_lpass_ag_noc = { .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), .bcms = lpass_ag_noc_bcms, @@ -1736,7 +1736,7 @@ static struct qcom_icc_node *mc_virt_nodes[] = { [SLAVE_EBI1_DISP] = &ebi_disp, }; -static struct qcom_icc_desc sm8450_mc_virt = { +static const struct qcom_icc_desc sm8450_mc_virt = { .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, @@ -1771,7 +1771,7 @@ static struct qcom_icc_node *mmss_noc_nodes[] = { [SLAVE_MNOC_SF_MEM_NOC_DISP] = &qns_mem_noc_sf_disp, }; -static struct qcom_icc_desc sm8450_mmss_noc = { +static const struct qcom_icc_desc sm8450_mmss_noc = { .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1789,7 +1789,7 @@ static struct qcom_icc_node *nsp_noc_nodes[] = { [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, }; -static struct qcom_icc_desc sm8450_nsp_noc = { +static const struct qcom_icc_desc sm8450_nsp_noc = { .nodes = nsp_noc_nodes, .num_nodes = ARRAY_SIZE(nsp_noc_nodes), .bcms = nsp_noc_bcms, @@ -1808,7 +1808,7 @@ static struct qcom_icc_node *pcie_anoc_nodes[] = { [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc, }; -static struct qcom_icc_desc sm8450_pcie_anoc = { +static const struct qcom_icc_desc sm8450_pcie_anoc = { .nodes = pcie_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), .bcms = pcie_anoc_bcms, @@ -1836,7 +1836,7 @@ static struct qcom_icc_node *system_noc_nodes[] = { [SLAVE_SERVICE_SNOC] = &srvc_snoc, }; -static struct qcom_icc_desc sm8450_system_noc = { +static const struct qcom_icc_desc sm8450_system_noc = { .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, From patchwork Tue Apr 12 10:26:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 560169 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74EB8C433FE for ; Tue, 12 Apr 2022 11:44:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231328AbiDLLqa (ORCPT ); Tue, 12 Apr 2022 07:46:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39276 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345321AbiDLLp5 (ORCPT ); Tue, 12 Apr 2022 07:45:57 -0400 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 077967C17D for ; Tue, 12 Apr 2022 03:26:31 -0700 (PDT) Received: by mail-ej1-x629.google.com with SMTP id ks6so11749278ejb.1 for ; Tue, 12 Apr 2022 03:26:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qH9iZ4zus+cGXdlCs2yVJVv4Bkzzmqc57kTdn4lPc/0=; b=KDPV8FRtYR4NwDTwvqZKSqo7mquubvwJvA8LAc28XJNo9E3T/7Ute6O42G95q4OZ38 aQv7qh/QMKJA9+1iGRJbDtwaKIQxpgWCyuHYvYOp/AFLTOdanyDB8izQveVzQzCdgT4i pec7Ji/8pe3Y/o/9PONThczng1T5G9jvwe6yP+ohi811N+emu1yiel4yS+uDTNf7ZhAh 83b1jh5JAkJ2yticG5OjHgkNYFjnFBBeC9TOGGG+awXg1Mhl2Xfp5iH1uz8AHkQyCtwz MCGt3IIUNCaq94/b3QeaVHWeH5rxISj1fxTgA8QDLpT/mFq7RlZo51lci90JA2T9H0JS 5m4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qH9iZ4zus+cGXdlCs2yVJVv4Bkzzmqc57kTdn4lPc/0=; b=eluHETzB6def6fIUuLuQk0aTZ2GYc7XIj5YBmgaXvHDhadX6g8XBsdcJn+SmyDZonG gnPs2ohpoy4zo1QVz1D1rB6nldIAqqEZRksMhxT0HDwZFRXP+CzuYGY5x4erkktRxlcw YzWysBtyHOS8G2nV9RRDBmbKly+n+KGaDcWqHTMyWjzJbkUQqz4tDOtZzkCinwynTLf9 O9LJACOt/1tIpIGx42tZVOsBL+BKVhVru7/lpnPgO/D1H8weOVrwTZZfZumcJT1tpMim 9e7spMVBlKBfr0zY019H6jt5cVamcd3SP1DS8ealAAlXuEJPAzdSOz/9gG0O5anCXpbe t8HQ== X-Gm-Message-State: AOAM530YjMY8kImVnBVXm1Tr44od3NXuqnI0ZcSlQuA8DV6uG34CP8v6 Qkxh3tkzw3NaqS783Pf9Pznakw== X-Google-Smtp-Source: ABdhPJzVc/jAxTjQd43q+dsvx1UzKEmJiX0LiQHEVuexQ7qrNmVonFyA9Iu27ivuhNqsCwDOZEgU5A== X-Received: by 2002:a17:906:694f:b0:6e8:b720:594 with SMTP id c15-20020a170906694f00b006e8b7200594mr1445781ejs.404.1649759189255; Tue, 12 Apr 2022 03:26:29 -0700 (PDT) Received: from localhost.localdomain (xdsl-188-155-201-27.adslplus.ch. [188.155.201.27]) by smtp.gmail.com with ESMTPSA id z21-20020a170906435500b006e8669fae36sm4468959ejm.189.2022.04.12.03.26.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Apr 2022 03:26:28 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Georgi Djakov , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 2/3] interconnect: qcom: constify icc_node pointers Date: Tue, 12 Apr 2022 12:26:22 +0200 Message-Id: <20220412102623.227607-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220412102623.227607-1-krzysztof.kozlowski@linaro.org> References: <20220412102623.227607-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Pointers to struct qcom_icc_node (and similar structures) are not modified, so they can be made const for safety. The contents of struct qcom_icc_node must stay non-const. Signed-off-by: Krzysztof Kozlowski --- drivers/interconnect/qcom/icc-rpm.c | 2 +- drivers/interconnect/qcom/icc-rpm.h | 2 +- drivers/interconnect/qcom/icc-rpmh.c | 2 +- drivers/interconnect/qcom/icc-rpmh.h | 2 +- drivers/interconnect/qcom/msm8916.c | 6 +++--- drivers/interconnect/qcom/msm8939.c | 8 ++++---- drivers/interconnect/qcom/msm8974.c | 16 ++++++++-------- drivers/interconnect/qcom/msm8996.c | 16 ++++++++-------- drivers/interconnect/qcom/osm-l3.c | 16 ++++++++-------- drivers/interconnect/qcom/qcm2290.c | 12 ++++++------ drivers/interconnect/qcom/qcs404.c | 6 +++--- drivers/interconnect/qcom/sc7180.c | 26 +++++++++++++------------- drivers/interconnect/qcom/sc7280.c | 24 ++++++++++++------------ drivers/interconnect/qcom/sc8180x.c | 24 ++++++++++++------------ drivers/interconnect/qcom/sdm660.c | 12 ++++++------ drivers/interconnect/qcom/sdm845.c | 16 ++++++++-------- drivers/interconnect/qcom/sdx55.c | 8 ++++---- drivers/interconnect/qcom/sm8150.c | 22 +++++++++++----------- drivers/interconnect/qcom/sm8250.c | 22 +++++++++++----------- drivers/interconnect/qcom/sm8350.c | 20 ++++++++++---------- drivers/interconnect/qcom/sm8450.c | 24 ++++++++++++------------ 21 files changed, 143 insertions(+), 143 deletions(-) diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index 34125e8f8b60..874e65658a4f 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -301,7 +301,7 @@ int qnoc_probe(struct platform_device *pdev) const struct qcom_icc_desc *desc; struct icc_onecell_data *data; struct icc_provider *provider; - struct qcom_icc_node **qnodes; + struct qcom_icc_node * const *qnodes; struct qcom_icc_provider *qp; struct icc_node *node; size_t num_nodes, i; diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h index 26dad006034f..56cf97ec1159 100644 --- a/drivers/interconnect/qcom/icc-rpm.h +++ b/drivers/interconnect/qcom/icc-rpm.h @@ -81,7 +81,7 @@ struct qcom_icc_node { }; struct qcom_icc_desc { - struct qcom_icc_node **nodes; + struct qcom_icc_node * const *nodes; size_t num_nodes; const char * const *clocks; size_t num_clocks; diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c index 2c8e12549804..3c40076eb5fb 100644 --- a/drivers/interconnect/qcom/icc-rpmh.c +++ b/drivers/interconnect/qcom/icc-rpmh.c @@ -189,7 +189,7 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct icc_onecell_data *data; struct icc_provider *provider; - struct qcom_icc_node **qnodes, *qn; + struct qcom_icc_node * const *qnodes, *qn; struct qcom_icc_provider *qp; struct icc_node *node; size_t num_nodes, i, j; diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h index 4bfc060529ba..5dfc26072593 100644 --- a/drivers/interconnect/qcom/icc-rpmh.h +++ b/drivers/interconnect/qcom/icc-rpmh.h @@ -112,7 +112,7 @@ struct qcom_icc_fabric { }; struct qcom_icc_desc { - struct qcom_icc_node **nodes; + struct qcom_icc_node * const *nodes; size_t num_nodes; struct qcom_icc_bcm **bcms; size_t num_bcms; diff --git a/drivers/interconnect/qcom/msm8916.c b/drivers/interconnect/qcom/msm8916.c index 4dc122ce9805..5c4ba2f37c8e 100644 --- a/drivers/interconnect/qcom/msm8916.c +++ b/drivers/interconnect/qcom/msm8916.c @@ -1191,7 +1191,7 @@ static struct qcom_icc_node snoc_pcnoc_slv = { .links = snoc_pcnoc_slv_links, }; -static struct qcom_icc_node *msm8916_snoc_nodes[] = { +static struct qcom_icc_node * const msm8916_snoc_nodes[] = { [BIMC_SNOC_SLV] = &bimc_snoc_slv, [MASTER_JPEG] = &mas_jpeg, [MASTER_MDP_PORT0] = &mas_mdp, @@ -1236,7 +1236,7 @@ static const struct qcom_icc_desc msm8916_snoc = { .qos_offset = 0x7000, }; -static struct qcom_icc_node *msm8916_bimc_nodes[] = { +static struct qcom_icc_node * const msm8916_bimc_nodes[] = { [BIMC_SNOC_MAS] = &bimc_snoc_mas, [MASTER_AMPSS_M0] = &mas_apss, [MASTER_GRAPHICS_3D] = &mas_gfx, @@ -1264,7 +1264,7 @@ static const struct qcom_icc_desc msm8916_bimc = { .qos_offset = 0x8000, }; -static struct qcom_icc_node *msm8916_pcnoc_nodes[] = { +static struct qcom_icc_node * const msm8916_pcnoc_nodes[] = { [MASTER_BLSP_1] = &mas_blsp_1, [MASTER_DEHR] = &mas_dehr, [MASTER_LPASS] = &mas_audio, diff --git a/drivers/interconnect/qcom/msm8939.c b/drivers/interconnect/qcom/msm8939.c index 7838e332ee41..63b31deea722 100644 --- a/drivers/interconnect/qcom/msm8939.c +++ b/drivers/interconnect/qcom/msm8939.c @@ -1251,7 +1251,7 @@ static struct qcom_icc_node snoc_pcnoc_slv = { .links = snoc_pcnoc_slv_links, }; -static struct qcom_icc_node *msm8939_snoc_nodes[] = { +static struct qcom_icc_node * const msm8939_snoc_nodes[] = { [BIMC_SNOC_SLV] = &bimc_snoc_slv, [MASTER_QDSS_BAM] = &mas_qdss_bam, [MASTER_QDSS_ETR] = &mas_qdss_etr, @@ -1289,7 +1289,7 @@ static const struct qcom_icc_desc msm8939_snoc = { .qos_offset = 0x7000, }; -static struct qcom_icc_node *msm8939_snoc_mm_nodes[] = { +static struct qcom_icc_node * const msm8939_snoc_mm_nodes[] = { [MASTER_VIDEO_P0] = &mas_video, [MASTER_JPEG] = &mas_jpeg, [MASTER_VFE] = &mas_vfe, @@ -1309,7 +1309,7 @@ static const struct qcom_icc_desc msm8939_snoc_mm = { .qos_offset = 0x7000, }; -static struct qcom_icc_node *msm8939_bimc_nodes[] = { +static struct qcom_icc_node * const msm8939_bimc_nodes[] = { [BIMC_SNOC_MAS] = &bimc_snoc_mas, [MASTER_AMPSS_M0] = &mas_apss, [MASTER_GRAPHICS_3D] = &mas_gfx, @@ -1337,7 +1337,7 @@ static const struct qcom_icc_desc msm8939_bimc = { .qos_offset = 0x8000, }; -static struct qcom_icc_node *msm8939_pcnoc_nodes[] = { +static struct qcom_icc_node * const msm8939_pcnoc_nodes[] = { [MASTER_BLSP_1] = &mas_blsp_1, [MASTER_DEHR] = &mas_dehr, [MASTER_LPASS] = &mas_audio, diff --git a/drivers/interconnect/qcom/msm8974.c b/drivers/interconnect/qcom/msm8974.c index 2eebe421f262..6fa0ad90fc3d 100644 --- a/drivers/interconnect/qcom/msm8974.c +++ b/drivers/interconnect/qcom/msm8974.c @@ -220,7 +220,7 @@ struct msm8974_icc_node { }; struct msm8974_icc_desc { - struct msm8974_icc_node **nodes; + struct msm8974_icc_node * const *nodes; size_t num_nodes; }; @@ -244,7 +244,7 @@ DEFINE_QNODE(bimc_to_snoc, MSM8974_BIMC_TO_SNOC, 8, 3, 2, MSM8974_SNOC_TO_BIMC, DEFINE_QNODE(slv_ebi_ch0, MSM8974_BIMC_SLV_EBI_CH0, 8, -1, 0); DEFINE_QNODE(slv_ampss_l2, MSM8974_BIMC_SLV_AMPSS_L2, 8, -1, 1); -static struct msm8974_icc_node *msm8974_bimc_nodes[] = { +static struct msm8974_icc_node * const msm8974_bimc_nodes[] = { [BIMC_MAS_AMPSS_M0] = &mas_ampss_m0, [BIMC_MAS_AMPSS_M1] = &mas_ampss_m1, [BIMC_MAS_MSS_PROC] = &mas_mss_proc, @@ -297,7 +297,7 @@ DEFINE_QNODE(slv_ebi1_phy_cfg, MSM8974_CNOC_SLV_EBI1_PHY_CFG, 8, -1, 73); DEFINE_QNODE(slv_rpm, MSM8974_CNOC_SLV_RPM, 8, -1, 74); DEFINE_QNODE(slv_service_cnoc, MSM8974_CNOC_SLV_SERVICE_CNOC, 8, -1, 76); -static struct msm8974_icc_node *msm8974_cnoc_nodes[] = { +static struct msm8974_icc_node * const msm8974_cnoc_nodes[] = { [CNOC_MAS_RPM_INST] = &mas_rpm_inst, [CNOC_MAS_RPM_DATA] = &mas_rpm_data, [CNOC_MAS_RPM_SYS] = &mas_rpm_sys, @@ -365,7 +365,7 @@ DEFINE_QNODE(slv_mnoc_mpu_cfg, MSM8974_MNOC_SLV_MNOC_MPU_CFG, 16, -1, 14); DEFINE_QNODE(slv_onoc_mpu_cfg, MSM8974_MNOC_SLV_ONOC_MPU_CFG, 16, -1, 15); DEFINE_QNODE(slv_service_mnoc, MSM8974_MNOC_SLV_SERVICE_MNOC, 16, -1, 17); -static struct msm8974_icc_node *msm8974_mnoc_nodes[] = { +static struct msm8974_icc_node * const msm8974_mnoc_nodes[] = { [MNOC_MAS_GRAPHICS_3D] = &mas_graphics_3d, [MNOC_MAS_JPEG] = &mas_jpeg, [MNOC_MAS_MDP_PORT0] = &mas_mdp_port0, @@ -410,7 +410,7 @@ DEFINE_QNODE(ocmem_vnoc_to_onoc, MSM8974_OCMEM_VNOC_TO_OCMEM_NOC, 16, 56, 79, MS DEFINE_QNODE(ocmem_vnoc_to_snoc, MSM8974_OCMEM_VNOC_TO_SNOC, 8, 57, 80); DEFINE_QNODE(mas_v_ocmem_gfx3d, MSM8974_OCMEM_VNOC_MAS_GFX3D, 8, 55, -1, MSM8974_OCMEM_VNOC_TO_OCMEM_NOC); -static struct msm8974_icc_node *msm8974_onoc_nodes[] = { +static struct msm8974_icc_node * const msm8974_onoc_nodes[] = { [OCMEM_NOC_TO_OCMEM_VNOC] = &ocmem_noc_to_ocmem_vnoc, [OCMEM_MAS_JPEG_OCMEM] = &mas_jpeg_ocmem, [OCMEM_MAS_MDP_OCMEM] = &mas_mdp_ocmem, @@ -458,7 +458,7 @@ DEFINE_QNODE(slv_pnoc_mpu_cfg, MSM8974_PNOC_SLV_PNOC_MPU_CFG, 8, -1, 43); DEFINE_QNODE(slv_prng, MSM8974_PNOC_SLV_PRNG, 8, -1, 44, MSM8974_PNOC_TO_SNOC); DEFINE_QNODE(slv_service_pnoc, MSM8974_PNOC_SLV_SERVICE_PNOC, 8, -1, 46); -static struct msm8974_icc_node *msm8974_pnoc_nodes[] = { +static struct msm8974_icc_node * const msm8974_pnoc_nodes[] = { [PNOC_MAS_PNOC_CFG] = &mas_pnoc_cfg, [PNOC_MAS_SDCC_1] = &mas_sdcc_1, [PNOC_MAS_SDCC_3] = &mas_sdcc_3, @@ -518,7 +518,7 @@ DEFINE_QNODE(slv_snoc_ocmem, MSM8974_SNOC_SLV_SNOC_OCMEM, 8, -1, 27); DEFINE_QNODE(slv_service_snoc, MSM8974_SNOC_SLV_SERVICE_SNOC, 8, -1, 29); DEFINE_QNODE(slv_qdss_stm, MSM8974_SNOC_SLV_QDSS_STM, 8, -1, 30); -static struct msm8974_icc_node *msm8974_snoc_nodes[] = { +static struct msm8974_icc_node * const msm8974_snoc_nodes[] = { [SNOC_MAS_LPASS_AHB] = &mas_lpass_ahb, [SNOC_MAS_QDSS_BAM] = &mas_qdss_bam, [SNOC_MAS_SNOC_CFG] = &mas_snoc_cfg, @@ -648,7 +648,7 @@ static int msm8974_get_bw(struct icc_node *node, u32 *avg, u32 *peak) static int msm8974_icc_probe(struct platform_device *pdev) { const struct msm8974_icc_desc *desc; - struct msm8974_icc_node **qnodes; + struct msm8974_icc_node * const *qnodes; struct msm8974_icc_provider *qp; struct device *dev = &pdev->dev; struct icc_onecell_data *data; diff --git a/drivers/interconnect/qcom/msm8996.c b/drivers/interconnect/qcom/msm8996.c index 499e11fbbd2e..c2903ae3b3bc 100644 --- a/drivers/interconnect/qcom/msm8996.c +++ b/drivers/interconnect/qcom/msm8996.c @@ -1796,7 +1796,7 @@ static struct qcom_icc_node slv_srvc_snoc = { .qos.qos_mode = NOC_QOS_MODE_INVALID }; -static struct qcom_icc_node *a0noc_nodes[] = { +static struct qcom_icc_node * const a0noc_nodes[] = { [MASTER_PCIE_0] = &mas_pcie_0, [MASTER_PCIE_1] = &mas_pcie_1, [MASTER_PCIE_2] = &mas_pcie_2 @@ -1820,7 +1820,7 @@ static const struct qcom_icc_desc msm8996_a0noc = { .regmap_cfg = &msm8996_a0noc_regmap_config }; -static struct qcom_icc_node *a1noc_nodes[] = { +static struct qcom_icc_node * const a1noc_nodes[] = { [MASTER_CNOC_A1NOC] = &mas_cnoc_a1noc, [MASTER_CRYPTO_CORE0] = &mas_crypto_c0, [MASTER_PNOC_A1NOC] = &mas_pnoc_a1noc @@ -1841,7 +1841,7 @@ static const struct qcom_icc_desc msm8996_a1noc = { .regmap_cfg = &msm8996_a1noc_regmap_config }; -static struct qcom_icc_node *a2noc_nodes[] = { +static struct qcom_icc_node * const a2noc_nodes[] = { [MASTER_USB3] = &mas_usb3, [MASTER_IPA] = &mas_ipa, [MASTER_UFS] = &mas_ufs @@ -1862,7 +1862,7 @@ static const struct qcom_icc_desc msm8996_a2noc = { .regmap_cfg = &msm8996_a2noc_regmap_config }; -static struct qcom_icc_node *bimc_nodes[] = { +static struct qcom_icc_node * const bimc_nodes[] = { [MASTER_AMPSS_M0] = &mas_apps_proc, [MASTER_GRAPHICS_3D] = &mas_oxili, [MASTER_MNOC_BIMC] = &mas_mnoc_bimc, @@ -1888,7 +1888,7 @@ static const struct qcom_icc_desc msm8996_bimc = { .regmap_cfg = &msm8996_bimc_regmap_config }; -static struct qcom_icc_node *cnoc_nodes[] = { +static struct qcom_icc_node * const cnoc_nodes[] = { [MASTER_SNOC_CNOC] = &mas_snoc_cnoc, [MASTER_QDSS_DAP] = &mas_qdss_dap, [SLAVE_CNOC_A1NOC] = &slv_cnoc_a1noc, @@ -1946,7 +1946,7 @@ static const struct qcom_icc_desc msm8996_cnoc = { .regmap_cfg = &msm8996_cnoc_regmap_config }; -static struct qcom_icc_node *mnoc_nodes[] = { +static struct qcom_icc_node * const mnoc_nodes[] = { [MASTER_CNOC_MNOC_CFG] = &mas_cnoc_mnoc_cfg, [MASTER_CPP] = &mas_cpp, [MASTER_JPEG] = &mas_jpeg, @@ -2001,7 +2001,7 @@ static const struct qcom_icc_desc msm8996_mnoc = { .regmap_cfg = &msm8996_mnoc_regmap_config }; -static struct qcom_icc_node *pnoc_nodes[] = { +static struct qcom_icc_node * const pnoc_nodes[] = { [MASTER_SNOC_PNOC] = &mas_snoc_pnoc, [MASTER_SDCC_1] = &mas_sdcc_1, [MASTER_SDCC_2] = &mas_sdcc_2, @@ -2037,7 +2037,7 @@ static const struct qcom_icc_desc msm8996_pnoc = { .regmap_cfg = &msm8996_pnoc_regmap_config }; -static struct qcom_icc_node *snoc_nodes[] = { +static struct qcom_icc_node * const snoc_nodes[] = { [MASTER_HMSS] = &mas_hmss, [MASTER_QDSS_BAM] = &mas_qdss_bam, [MASTER_SNOC_CFG] = &mas_snoc_cfg, diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c index eec13099a6a3..4198656f4e59 100644 --- a/drivers/interconnect/qcom/osm-l3.c +++ b/drivers/interconnect/qcom/osm-l3.c @@ -67,7 +67,7 @@ struct qcom_osm_l3_node { }; struct qcom_osm_l3_desc { - const struct qcom_osm_l3_node **nodes; + const struct qcom_osm_l3_node * const *nodes; size_t num_nodes; unsigned int lut_row_size; unsigned int reg_freq_lut; @@ -86,7 +86,7 @@ struct qcom_osm_l3_desc { DEFINE_QNODE(sdm845_osm_apps_l3, SDM845_MASTER_OSM_L3_APPS, 16, SDM845_SLAVE_OSM_L3); DEFINE_QNODE(sdm845_osm_l3, SDM845_SLAVE_OSM_L3, 16); -static const struct qcom_osm_l3_node *sdm845_osm_l3_nodes[] = { +static const struct qcom_osm_l3_node * const sdm845_osm_l3_nodes[] = { [MASTER_OSM_L3_APPS] = &sdm845_osm_apps_l3, [SLAVE_OSM_L3] = &sdm845_osm_l3, }; @@ -102,7 +102,7 @@ static const struct qcom_osm_l3_desc sdm845_icc_osm_l3 = { DEFINE_QNODE(sc7180_osm_apps_l3, SC7180_MASTER_OSM_L3_APPS, 16, SC7180_SLAVE_OSM_L3); DEFINE_QNODE(sc7180_osm_l3, SC7180_SLAVE_OSM_L3, 16); -static const struct qcom_osm_l3_node *sc7180_osm_l3_nodes[] = { +static const struct qcom_osm_l3_node * const sc7180_osm_l3_nodes[] = { [MASTER_OSM_L3_APPS] = &sc7180_osm_apps_l3, [SLAVE_OSM_L3] = &sc7180_osm_l3, }; @@ -118,7 +118,7 @@ static const struct qcom_osm_l3_desc sc7180_icc_osm_l3 = { DEFINE_QNODE(sc7280_epss_apps_l3, SC7280_MASTER_EPSS_L3_APPS, 32, SC7280_SLAVE_EPSS_L3); DEFINE_QNODE(sc7280_epss_l3, SC7280_SLAVE_EPSS_L3, 32); -static const struct qcom_osm_l3_node *sc7280_epss_l3_nodes[] = { +static const struct qcom_osm_l3_node * const sc7280_epss_l3_nodes[] = { [MASTER_EPSS_L3_APPS] = &sc7280_epss_apps_l3, [SLAVE_EPSS_L3_SHARED] = &sc7280_epss_l3, }; @@ -134,7 +134,7 @@ static const struct qcom_osm_l3_desc sc7280_icc_epss_l3 = { DEFINE_QNODE(sc8180x_osm_apps_l3, SC8180X_MASTER_OSM_L3_APPS, 32, SC8180X_SLAVE_OSM_L3); DEFINE_QNODE(sc8180x_osm_l3, SC8180X_SLAVE_OSM_L3, 32); -static const struct qcom_osm_l3_node *sc8180x_osm_l3_nodes[] = { +static const struct qcom_osm_l3_node * const sc8180x_osm_l3_nodes[] = { [MASTER_OSM_L3_APPS] = &sc8180x_osm_apps_l3, [SLAVE_OSM_L3] = &sc8180x_osm_l3, }; @@ -150,7 +150,7 @@ static const struct qcom_osm_l3_desc sc8180x_icc_osm_l3 = { DEFINE_QNODE(sm8150_osm_apps_l3, SM8150_MASTER_OSM_L3_APPS, 32, SM8150_SLAVE_OSM_L3); DEFINE_QNODE(sm8150_osm_l3, SM8150_SLAVE_OSM_L3, 32); -static const struct qcom_osm_l3_node *sm8150_osm_l3_nodes[] = { +static const struct qcom_osm_l3_node * const sm8150_osm_l3_nodes[] = { [MASTER_OSM_L3_APPS] = &sm8150_osm_apps_l3, [SLAVE_OSM_L3] = &sm8150_osm_l3, }; @@ -166,7 +166,7 @@ static const struct qcom_osm_l3_desc sm8150_icc_osm_l3 = { DEFINE_QNODE(sm8250_epss_apps_l3, SM8250_MASTER_EPSS_L3_APPS, 32, SM8250_SLAVE_EPSS_L3); DEFINE_QNODE(sm8250_epss_l3, SM8250_SLAVE_EPSS_L3, 32); -static const struct qcom_osm_l3_node *sm8250_epss_l3_nodes[] = { +static const struct qcom_osm_l3_node * const sm8250_epss_l3_nodes[] = { [MASTER_EPSS_L3_APPS] = &sm8250_epss_apps_l3, [SLAVE_EPSS_L3_SHARED] = &sm8250_epss_l3, }; @@ -228,7 +228,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) const struct qcom_osm_l3_desc *desc; struct icc_onecell_data *data; struct icc_provider *provider; - const struct qcom_osm_l3_node **qnodes; + const struct qcom_osm_l3_node * const *qnodes; struct icc_node *node; size_t num_nodes; struct clk *clk; diff --git a/drivers/interconnect/qcom/qcm2290.c b/drivers/interconnect/qcom/qcm2290.c index 644dcd90e7ad..0da612d6398c 100644 --- a/drivers/interconnect/qcom/qcm2290.c +++ b/drivers/interconnect/qcom/qcm2290.c @@ -1174,7 +1174,7 @@ static struct qcom_icc_node slv_anoc_snoc = { }; /* NoC descriptors */ -static struct qcom_icc_node *qcm2290_bimc_nodes[] = { +static struct qcom_icc_node * const qcm2290_bimc_nodes[] = { [MASTER_APPSS_PROC] = &mas_appss_proc, [MASTER_SNOC_BIMC_RT] = &mas_snoc_bimc_rt, [MASTER_SNOC_BIMC_NRT] = &mas_snoc_bimc_nrt, @@ -1202,7 +1202,7 @@ static const struct qcom_icc_desc qcm2290_bimc = { .qos_offset = 0x8000, }; -static struct qcom_icc_node *qcm2290_cnoc_nodes[] = { +static struct qcom_icc_node * const qcm2290_cnoc_nodes[] = { [MASTER_SNOC_CNOC] = &mas_snoc_cnoc, [MASTER_QDSS_DAP] = &mas_qdss_dap, [SLAVE_BIMC_CFG] = &slv_bimc_cfg, @@ -1255,7 +1255,7 @@ static const struct qcom_icc_desc qcm2290_cnoc = { .regmap_cfg = &qcm2290_cnoc_regmap_config, }; -static struct qcom_icc_node *qcm2290_snoc_nodes[] = { +static struct qcom_icc_node * const qcm2290_snoc_nodes[] = { [MASTER_CRYPTO_CORE0] = &mas_crypto_core0, [MASTER_SNOC_CFG] = &mas_snoc_cfg, [MASTER_TIC] = &mas_tic, @@ -1298,7 +1298,7 @@ static const struct qcom_icc_desc qcm2290_snoc = { .qos_offset = 0x15000, }; -static struct qcom_icc_node *qcm2290_qup_virt_nodes[] = { +static struct qcom_icc_node * const qcm2290_qup_virt_nodes[] = { [MASTER_QUP_CORE_0] = &mas_qup_core_0, [SLAVE_QUP_CORE_0] = &slv_qup_core_0 }; @@ -1309,7 +1309,7 @@ static const struct qcom_icc_desc qcm2290_qup_virt = { .num_nodes = ARRAY_SIZE(qcm2290_qup_virt_nodes), }; -static struct qcom_icc_node *qcm2290_mmnrt_virt_nodes[] = { +static struct qcom_icc_node * const qcm2290_mmnrt_virt_nodes[] = { [MASTER_CAMNOC_SF] = &mas_camnoc_sf, [MASTER_VIDEO_P0] = &mas_video_p0, [MASTER_VIDEO_PROC] = &mas_video_proc, @@ -1324,7 +1324,7 @@ static const struct qcom_icc_desc qcm2290_mmnrt_virt = { .qos_offset = 0x15000, }; -static struct qcom_icc_node *qcm2290_mmrt_virt_nodes[] = { +static struct qcom_icc_node * const qcm2290_mmrt_virt_nodes[] = { [MASTER_CAMNOC_HF] = &mas_camnoc_hf, [MASTER_MDP0] = &mas_mdp0, [SLAVE_SNOC_BIMC_RT] = &slv_snoc_bimc_rt, diff --git a/drivers/interconnect/qcom/qcs404.c b/drivers/interconnect/qcom/qcs404.c index d5020b2b2236..fae155344332 100644 --- a/drivers/interconnect/qcom/qcs404.c +++ b/drivers/interconnect/qcom/qcs404.c @@ -974,7 +974,7 @@ static struct qcom_icc_node slv_lpass = { .slv_rpm_id = -1, }; -static struct qcom_icc_node *qcs404_bimc_nodes[] = { +static struct qcom_icc_node * const qcs404_bimc_nodes[] = { [MASTER_AMPSS_M0] = &mas_apps_proc, [MASTER_OXILI] = &mas_oxili, [MASTER_MDP_PORT0] = &mas_mdp, @@ -989,7 +989,7 @@ static const struct qcom_icc_desc qcs404_bimc = { .num_nodes = ARRAY_SIZE(qcs404_bimc_nodes), }; -static struct qcom_icc_node *qcs404_pcnoc_nodes[] = { +static struct qcom_icc_node * const qcs404_pcnoc_nodes[] = { [MASTER_SPDM] = &mas_spdm, [MASTER_BLSP_1] = &mas_blsp_1, [MASTER_BLSP_2] = &mas_blsp_2, @@ -1043,7 +1043,7 @@ static const struct qcom_icc_desc qcs404_pcnoc = { .num_nodes = ARRAY_SIZE(qcs404_pcnoc_nodes), }; -static struct qcom_icc_node *qcs404_snoc_nodes[] = { +static struct qcom_icc_node * const qcs404_snoc_nodes[] = { [MASTER_QDSS_BAM] = &mas_qdss_bam, [MASTER_BIMC_SNOC] = &mas_bimc_snoc, [MASTER_PCNOC_SNOC] = &mas_pcnoc_snoc, diff --git a/drivers/interconnect/qcom/sc7180.c b/drivers/interconnect/qcom/sc7180.c index 712b50d4b1c3..11e221edbd1c 100644 --- a/drivers/interconnect/qcom/sc7180.c +++ b/drivers/interconnect/qcom/sc7180.c @@ -185,7 +185,7 @@ static struct qcom_icc_bcm *aggre1_noc_bcms[] = { &bcm_cn1, }; -static struct qcom_icc_node *aggre1_noc_nodes[] = { +static struct qcom_icc_node * const aggre1_noc_nodes[] = { [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, [MASTER_QSPI] = &qhm_qspi, [MASTER_QUP_0] = &qhm_qup_0, @@ -207,7 +207,7 @@ static struct qcom_icc_bcm *aggre2_noc_bcms[] = { &bcm_ce0, }; -static struct qcom_icc_node *aggre2_noc_nodes[] = { +static struct qcom_icc_node * const aggre2_noc_nodes[] = { [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, [MASTER_QDSS_BAM] = &qhm_qdss_bam, [MASTER_QUP_1] = &qhm_qup_1, @@ -230,7 +230,7 @@ static struct qcom_icc_bcm *camnoc_virt_bcms[] = { &bcm_mm1, }; -static struct qcom_icc_node *camnoc_virt_nodes[] = { +static struct qcom_icc_node * const camnoc_virt_nodes[] = { [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp, [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp, [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp, @@ -250,7 +250,7 @@ static struct qcom_icc_bcm *compute_noc_bcms[] = { &bcm_co3, }; -static struct qcom_icc_node *compute_noc_nodes[] = { +static struct qcom_icc_node * const compute_noc_nodes[] = { [MASTER_NPU] = &qnm_npu, [MASTER_NPU_PROC] = &qxm_npu_dsp, [SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc, @@ -268,7 +268,7 @@ static struct qcom_icc_bcm *config_noc_bcms[] = { &bcm_cn1, }; -static struct qcom_icc_node *config_noc_nodes[] = { +static struct qcom_icc_node * const config_noc_nodes[] = { [MASTER_SNOC_CNOC] = &qnm_snoc, [MASTER_QDSS_DAP] = &xm_qdss_dap, [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg, @@ -331,7 +331,7 @@ static const struct qcom_icc_desc sc7180_config_noc = { .num_bcms = ARRAY_SIZE(config_noc_bcms), }; -static struct qcom_icc_node *dc_noc_nodes[] = { +static struct qcom_icc_node * const dc_noc_nodes[] = { [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc, [SLAVE_GEM_NOC_CFG] = &qhs_gemnoc, [SLAVE_LLCC_CFG] = &qhs_llcc, @@ -349,7 +349,7 @@ static struct qcom_icc_bcm *gem_noc_bcms[] = { &bcm_sh4, }; -static struct qcom_icc_node *gem_noc_nodes[] = { +static struct qcom_icc_node * const gem_noc_nodes[] = { [MASTER_APPSS_PROC] = &acm_apps0, [MASTER_SYS_TCU] = &acm_sys_tcu, [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg, @@ -376,7 +376,7 @@ static struct qcom_icc_bcm *ipa_virt_bcms[] = { &bcm_ip0, }; -static struct qcom_icc_node *ipa_virt_nodes[] = { +static struct qcom_icc_node * const ipa_virt_nodes[] = { [MASTER_IPA_CORE] = &ipa_core_master, [SLAVE_IPA_CORE] = &ipa_core_slave, }; @@ -393,7 +393,7 @@ static struct qcom_icc_bcm *mc_virt_bcms[] = { &bcm_mc0, }; -static struct qcom_icc_node *mc_virt_nodes[] = { +static struct qcom_icc_node * const mc_virt_nodes[] = { [MASTER_LLCC] = &llcc_mc, [SLAVE_EBI1] = &ebi, }; @@ -411,7 +411,7 @@ static struct qcom_icc_bcm *mmss_noc_bcms[] = { &bcm_mm2, }; -static struct qcom_icc_node *mmss_noc_nodes[] = { +static struct qcom_icc_node * const mmss_noc_nodes[] = { [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0, [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1, @@ -432,7 +432,7 @@ static const struct qcom_icc_desc sc7180_mmss_noc = { .num_bcms = ARRAY_SIZE(mmss_noc_bcms), }; -static struct qcom_icc_node *npu_noc_nodes[] = { +static struct qcom_icc_node * const npu_noc_nodes[] = { [MASTER_NPU_SYS] = &amm_npu_sys, [MASTER_NPU_NOC_CFG] = &qhm_npu_cfg, [SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0, @@ -455,7 +455,7 @@ static struct qcom_icc_bcm *qup_virt_bcms[] = { &bcm_qup0, }; -static struct qcom_icc_node *qup_virt_nodes[] = { +static struct qcom_icc_node * const qup_virt_nodes[] = { [MASTER_QUP_CORE_0] = &qup_core_master_1, [MASTER_QUP_CORE_1] = &qup_core_master_2, [SLAVE_QUP_CORE_0] = &qup_core_slave_1, @@ -480,7 +480,7 @@ static struct qcom_icc_bcm *system_noc_bcms[] = { &bcm_sn12, }; -static struct qcom_icc_node *system_noc_nodes[] = { +static struct qcom_icc_node * const system_noc_nodes[] = { [MASTER_SNOC_CFG] = &qhm_snoc_cfg, [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, diff --git a/drivers/interconnect/qcom/sc7280.c b/drivers/interconnect/qcom/sc7280.c index 0464e5eb6a32..d969bc6c4610 100644 --- a/drivers/interconnect/qcom/sc7280.c +++ b/drivers/interconnect/qcom/sc7280.c @@ -1482,7 +1482,7 @@ static struct qcom_icc_bcm *aggre1_noc_bcms[] = { &bcm_sn14, }; -static struct qcom_icc_node *aggre1_noc_nodes[] = { +static struct qcom_icc_node * const aggre1_noc_nodes[] = { [MASTER_QSPI_0] = &qhm_qspi, [MASTER_QUP_0] = &qhm_qup0, [MASTER_QUP_1] = &qhm_qup1, @@ -1511,7 +1511,7 @@ static struct qcom_icc_bcm *aggre2_noc_bcms[] = { &bcm_ce0, }; -static struct qcom_icc_node *aggre2_noc_nodes[] = { +static struct qcom_icc_node * const aggre2_noc_nodes[] = { [MASTER_QDSS_BAM] = &qhm_qdss_bam, [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg, [MASTER_CNOC_A2NOC] = &qnm_cnoc_datapath, @@ -1534,7 +1534,7 @@ static struct qcom_icc_bcm *clk_virt_bcms[] = { &bcm_qup1, }; -static struct qcom_icc_node *clk_virt_nodes[] = { +static struct qcom_icc_node * const clk_virt_nodes[] = { [MASTER_QUP_CORE_0] = &qup0_core_master, [MASTER_QUP_CORE_1] = &qup1_core_master, [SLAVE_QUP_CORE_0] = &qup0_core_slave, @@ -1553,7 +1553,7 @@ static struct qcom_icc_bcm *cnoc2_bcms[] = { &bcm_cn2, }; -static struct qcom_icc_node *cnoc2_nodes[] = { +static struct qcom_icc_node * const cnoc2_nodes[] = { [MASTER_CNOC3_CNOC2] = &qnm_cnoc3_cnoc2, [MASTER_QDSS_DAP] = &xm_qdss_dap, [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, @@ -1617,7 +1617,7 @@ static struct qcom_icc_bcm *cnoc3_bcms[] = { &bcm_sn4, }; -static struct qcom_icc_node *cnoc3_nodes[] = { +static struct qcom_icc_node * const cnoc3_nodes[] = { [MASTER_CNOC2_CNOC3] = &qnm_cnoc2_cnoc3, [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, @@ -1645,7 +1645,7 @@ static const struct qcom_icc_desc sc7280_cnoc3 = { static struct qcom_icc_bcm *dc_noc_bcms[] = { }; -static struct qcom_icc_node *dc_noc_nodes[] = { +static struct qcom_icc_node * const dc_noc_nodes[] = { [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc, [SLAVE_LLCC_CFG] = &qhs_llcc, [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, @@ -1665,7 +1665,7 @@ static struct qcom_icc_bcm *gem_noc_bcms[] = { &bcm_sh4, }; -static struct qcom_icc_node *gem_noc_nodes[] = { +static struct qcom_icc_node * const gem_noc_nodes[] = { [MASTER_GPU_TCU] = &alm_gpu_tcu, [MASTER_SYS_TCU] = &alm_sys_tcu, [MASTER_APPSS_PROC] = &chm_apps, @@ -1697,7 +1697,7 @@ static const struct qcom_icc_desc sc7280_gem_noc = { static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = { }; -static struct qcom_icc_node *lpass_ag_noc_nodes[] = { +static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, @@ -1719,7 +1719,7 @@ static struct qcom_icc_bcm *mc_virt_bcms[] = { &bcm_mc0, }; -static struct qcom_icc_node *mc_virt_nodes[] = { +static struct qcom_icc_node * const mc_virt_nodes[] = { [MASTER_LLCC] = &llcc_mc, [SLAVE_EBI1] = &ebi, }; @@ -1738,7 +1738,7 @@ static struct qcom_icc_bcm *mmss_noc_bcms[] = { &bcm_mm5, }; -static struct qcom_icc_node *mmss_noc_nodes[] = { +static struct qcom_icc_node * const mmss_noc_nodes[] = { [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg, [MASTER_VIDEO_P0] = &qnm_video0, [MASTER_VIDEO_PROC] = &qnm_video_cpu, @@ -1763,7 +1763,7 @@ static struct qcom_icc_bcm *nsp_noc_bcms[] = { &bcm_co3, }; -static struct qcom_icc_node *nsp_noc_nodes[] = { +static struct qcom_icc_node * const nsp_noc_nodes[] = { [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, [MASTER_CDSP_PROC] = &qxm_nsp, [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, @@ -1784,7 +1784,7 @@ static struct qcom_icc_bcm *system_noc_bcms[] = { &bcm_sn8, }; -static struct qcom_icc_node *system_noc_nodes[] = { +static struct qcom_icc_node * const system_noc_nodes[] = { [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, [MASTER_SNOC_CFG] = &qnm_snoc_cfg, diff --git a/drivers/interconnect/qcom/sc8180x.c b/drivers/interconnect/qcom/sc8180x.c index e9adf05b9330..f6b69b9df410 100644 --- a/drivers/interconnect/qcom/sc8180x.c +++ b/drivers/interconnect/qcom/sc8180x.c @@ -249,7 +249,7 @@ static struct qcom_icc_bcm *system_noc_bcms[] = { &bcm_sn15, }; -static struct qcom_icc_node *aggre1_noc_nodes[] = { +static struct qcom_icc_node * const aggre1_noc_nodes[] = { [MASTER_A1NOC_CFG] = &mas_qhm_a1noc_cfg, [MASTER_UFS_CARD] = &mas_xm_ufs_card, [MASTER_UFS_GEN4] = &mas_xm_ufs_g4, @@ -261,7 +261,7 @@ static struct qcom_icc_node *aggre1_noc_nodes[] = { [SLAVE_SERVICE_A1NOC] = &slv_srvc_aggre1_noc, }; -static struct qcom_icc_node *aggre2_noc_nodes[] = { +static struct qcom_icc_node * const aggre2_noc_nodes[] = { [MASTER_A2NOC_CFG] = &mas_qhm_a2noc_cfg, [MASTER_QDSS_BAM] = &mas_qhm_qdss_bam, [MASTER_QSPI_0] = &mas_qhm_qspi, @@ -285,19 +285,19 @@ static struct qcom_icc_node *aggre2_noc_nodes[] = { [SLAVE_SERVICE_A2NOC] = &slv_srvc_aggre2_noc, }; -static struct qcom_icc_node *camnoc_virt_nodes[] = { +static struct qcom_icc_node * const camnoc_virt_nodes[] = { [MASTER_CAMNOC_HF0_UNCOMP] = &mas_qxm_camnoc_hf0_uncomp, [MASTER_CAMNOC_HF1_UNCOMP] = &mas_qxm_camnoc_hf1_uncomp, [MASTER_CAMNOC_SF_UNCOMP] = &mas_qxm_camnoc_sf_uncomp, [SLAVE_CAMNOC_UNCOMP] = &slv_qns_camnoc_uncomp, }; -static struct qcom_icc_node *compute_noc_nodes[] = { +static struct qcom_icc_node * const compute_noc_nodes[] = { [MASTER_NPU] = &mas_qnm_npu, [SLAVE_CDSP_MEM_NOC] = &slv_qns_cdsp_mem_noc, }; -static struct qcom_icc_node *config_noc_nodes[] = { +static struct qcom_icc_node * const config_noc_nodes[] = { [SNOC_CNOC_MAS] = &mas_qnm_snoc, [SLAVE_A1NOC_CFG] = &slv_qhs_a1_noc_cfg, [SLAVE_A2NOC_CFG] = &slv_qhs_a2_noc_cfg, @@ -357,13 +357,13 @@ static struct qcom_icc_node *config_noc_nodes[] = { [SLAVE_SERVICE_CNOC] = &slv_srvc_cnoc, }; -static struct qcom_icc_node *dc_noc_nodes[] = { +static struct qcom_icc_node * const dc_noc_nodes[] = { [MASTER_CNOC_DC_NOC] = &mas_qhm_cnoc_dc_noc, [SLAVE_GEM_NOC_CFG] = &slv_qhs_gemnoc, [SLAVE_LLCC_CFG] = &slv_qhs_llcc, }; -static struct qcom_icc_node *gem_noc_nodes[] = { +static struct qcom_icc_node * const gem_noc_nodes[] = { [MASTER_AMPSS_M0] = &mas_acm_apps, [MASTER_GPU_TCU] = &mas_acm_gpu_tcu, [MASTER_SYS_TCU] = &mas_acm_sys_tcu, @@ -384,17 +384,17 @@ static struct qcom_icc_node *gem_noc_nodes[] = { [SLAVE_SERVICE_GEM_NOC_1] = &slv_srvc_gemnoc1, }; -static struct qcom_icc_node *ipa_virt_nodes[] = { +static struct qcom_icc_node * const ipa_virt_nodes[] = { [MASTER_IPA_CORE] = &mas_ipa_core_master, [SLAVE_IPA_CORE] = &slv_ipa_core_slave, }; -static struct qcom_icc_node *mc_virt_nodes[] = { +static struct qcom_icc_node * const mc_virt_nodes[] = { [MASTER_LLCC] = &mas_llcc_mc, [SLAVE_EBI_CH0] = &slv_ebi, }; -static struct qcom_icc_node *mmss_noc_nodes[] = { +static struct qcom_icc_node * const mmss_noc_nodes[] = { [MASTER_CNOC_MNOC_CFG] = &mas_qhm_mnoc_cfg, [MASTER_CAMNOC_HF0] = &mas_qxm_camnoc_hf0, [MASTER_CAMNOC_HF1] = &mas_qxm_camnoc_hf1, @@ -410,7 +410,7 @@ static struct qcom_icc_node *mmss_noc_nodes[] = { [SLAVE_SERVICE_MNOC] = &slv_srvc_mnoc, }; -static struct qcom_icc_node *system_noc_nodes[] = { +static struct qcom_icc_node * const system_noc_nodes[] = { [MASTER_SNOC_CFG] = &mas_qhm_snoc_cfg, [A1NOC_SNOC_MAS] = &mas_qnm_aggre1_noc, [A2NOC_SNOC_MAS] = &mas_qnm_aggre2_noc, @@ -508,7 +508,7 @@ static int qnoc_probe(struct platform_device *pdev) const struct qcom_icc_desc *desc; struct icc_onecell_data *data; struct icc_provider *provider; - struct qcom_icc_node **qnodes; + struct qcom_icc_node * const *qnodes; struct qcom_icc_provider *qp; struct icc_node *node; size_t num_nodes, i; diff --git a/drivers/interconnect/qcom/sdm660.c b/drivers/interconnect/qcom/sdm660.c index 5bfc724e4c16..8d879b0bcabc 100644 --- a/drivers/interconnect/qcom/sdm660.c +++ b/drivers/interconnect/qcom/sdm660.c @@ -1490,7 +1490,7 @@ static struct qcom_icc_node slv_srvc_snoc = { .slv_rpm_id = 29, }; -static struct qcom_icc_node *sdm660_a2noc_nodes[] = { +static struct qcom_icc_node * const sdm660_a2noc_nodes[] = { [MASTER_IPA] = &mas_ipa, [MASTER_CNOC_A2NOC] = &mas_cnoc_a2noc, [MASTER_SDCC_1] = &mas_sdcc_1, @@ -1521,7 +1521,7 @@ static const struct qcom_icc_desc sdm660_a2noc = { .regmap_cfg = &sdm660_a2noc_regmap_config, }; -static struct qcom_icc_node *sdm660_bimc_nodes[] = { +static struct qcom_icc_node * const sdm660_bimc_nodes[] = { [MASTER_GNOC_BIMC] = &mas_gnoc_bimc, [MASTER_OXILI] = &mas_oxili, [MASTER_MNOC_BIMC] = &mas_mnoc_bimc, @@ -1547,7 +1547,7 @@ static const struct qcom_icc_desc sdm660_bimc = { .regmap_cfg = &sdm660_bimc_regmap_config, }; -static struct qcom_icc_node *sdm660_cnoc_nodes[] = { +static struct qcom_icc_node * const sdm660_cnoc_nodes[] = { [MASTER_SNOC_CNOC] = &mas_snoc_cnoc, [MASTER_QDSS_DAP] = &mas_qdss_dap, [SLAVE_CNOC_A2NOC] = &slv_cnoc_a2noc, @@ -1601,7 +1601,7 @@ static const struct qcom_icc_desc sdm660_cnoc = { .regmap_cfg = &sdm660_cnoc_regmap_config, }; -static struct qcom_icc_node *sdm660_gnoc_nodes[] = { +static struct qcom_icc_node * const sdm660_gnoc_nodes[] = { [MASTER_APSS_PROC] = &mas_apss_proc, [SLAVE_GNOC_BIMC] = &slv_gnoc_bimc, [SLAVE_GNOC_SNOC] = &slv_gnoc_snoc, @@ -1622,7 +1622,7 @@ static const struct qcom_icc_desc sdm660_gnoc = { .regmap_cfg = &sdm660_gnoc_regmap_config, }; -static struct qcom_icc_node *sdm660_mnoc_nodes[] = { +static struct qcom_icc_node * const sdm660_mnoc_nodes[] = { [MASTER_CPP] = &mas_cpp, [MASTER_JPEG] = &mas_jpeg, [MASTER_MDP_P0] = &mas_mdp_p0, @@ -1664,7 +1664,7 @@ static const struct qcom_icc_desc sdm660_mnoc = { .regmap_cfg = &sdm660_mnoc_regmap_config, }; -static struct qcom_icc_node *sdm660_snoc_nodes[] = { +static struct qcom_icc_node * const sdm660_snoc_nodes[] = { [MASTER_QDSS_ETR] = &mas_qdss_etr, [MASTER_QDSS_BAM] = &mas_qdss_bam, [MASTER_SNOC_CFG] = &mas_snoc_cfg, diff --git a/drivers/interconnect/qcom/sdm845.c b/drivers/interconnect/qcom/sdm845.c index d2195079c228..1af0e6972bad 100644 --- a/drivers/interconnect/qcom/sdm845.c +++ b/drivers/interconnect/qcom/sdm845.c @@ -180,7 +180,7 @@ static struct qcom_icc_bcm *aggre1_noc_bcms[] = { &bcm_qup0, }; -static struct qcom_icc_node *aggre1_noc_nodes[] = { +static struct qcom_icc_node * const aggre1_noc_nodes[] = { [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, [MASTER_TSIF] = &qhm_tsif, [MASTER_SDCC_2] = &xm_sdc2, @@ -207,7 +207,7 @@ static struct qcom_icc_bcm *aggre2_noc_bcms[] = { &bcm_qup0, }; -static struct qcom_icc_node *aggre2_noc_nodes[] = { +static struct qcom_icc_node * const aggre2_noc_nodes[] = { [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, [MASTER_QDSS_BAM] = &qhm_qdss_bam, [MASTER_CNOC_A2NOC] = &qnm_cnoc, @@ -234,7 +234,7 @@ static struct qcom_icc_bcm *config_noc_bcms[] = { &bcm_cn0, }; -static struct qcom_icc_node *config_noc_nodes[] = { +static struct qcom_icc_node * const config_noc_nodes[] = { [MASTER_SPDM] = &qhm_spdm, [MASTER_TIC] = &qhm_tic, [MASTER_SNOC_CNOC] = &qnm_snoc, @@ -294,7 +294,7 @@ static const struct qcom_icc_desc sdm845_config_noc = { static struct qcom_icc_bcm *dc_noc_bcms[] = { }; -static struct qcom_icc_node *dc_noc_nodes[] = { +static struct qcom_icc_node * const dc_noc_nodes[] = { [MASTER_CNOC_DC_NOC] = &qhm_cnoc, [SLAVE_LLCC_CFG] = &qhs_llcc, [SLAVE_MEM_NOC_CFG] = &qhs_memnoc, @@ -310,7 +310,7 @@ static const struct qcom_icc_desc sdm845_dc_noc = { static struct qcom_icc_bcm *gladiator_noc_bcms[] = { }; -static struct qcom_icc_node *gladiator_noc_nodes[] = { +static struct qcom_icc_node * const gladiator_noc_nodes[] = { [MASTER_APPSS_PROC] = &acm_l3, [MASTER_GNOC_CFG] = &pm_gnoc_cfg, [SLAVE_GNOC_SNOC] = &qns_gladiator_sodv, @@ -335,7 +335,7 @@ static struct qcom_icc_bcm *mem_noc_bcms[] = { &bcm_sh5, }; -static struct qcom_icc_node *mem_noc_nodes[] = { +static struct qcom_icc_node * const mem_noc_nodes[] = { [MASTER_TCU_0] = &acm_tcu, [MASTER_MEM_NOC_CFG] = &qhm_memnoc_cfg, [MASTER_GNOC_MEM_NOC] = &qnm_apps, @@ -367,7 +367,7 @@ static struct qcom_icc_bcm *mmss_noc_bcms[] = { &bcm_mm3, }; -static struct qcom_icc_node *mmss_noc_nodes[] = { +static struct qcom_icc_node * const mmss_noc_nodes[] = { [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0, [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1, @@ -411,7 +411,7 @@ static struct qcom_icc_bcm *system_noc_bcms[] = { &bcm_sn15, }; -static struct qcom_icc_node *system_noc_nodes[] = { +static struct qcom_icc_node * const system_noc_nodes[] = { [MASTER_SNOC_CFG] = &qhm_snoc_cfg, [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, diff --git a/drivers/interconnect/qcom/sdx55.c b/drivers/interconnect/qcom/sdx55.c index 03d604f84cc5..74ebf107d62f 100644 --- a/drivers/interconnect/qcom/sdx55.c +++ b/drivers/interconnect/qcom/sdx55.c @@ -106,7 +106,7 @@ static struct qcom_icc_bcm *mc_virt_bcms[] = { &bcm_mc0, }; -static struct qcom_icc_node *mc_virt_nodes[] = { +static struct qcom_icc_node * const mc_virt_nodes[] = { [MASTER_LLCC] = &llcc_mc, [SLAVE_EBI_CH0] = &ebi, }; @@ -124,7 +124,7 @@ static struct qcom_icc_bcm *mem_noc_bcms[] = { &bcm_sh4, }; -static struct qcom_icc_node *mem_noc_nodes[] = { +static struct qcom_icc_node * const mem_noc_nodes[] = { [MASTER_TCU_0] = &acm_tcu, [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, [MASTER_AMPSS_M0] = &xm_apps_rdwr, @@ -159,7 +159,7 @@ static struct qcom_icc_bcm *system_noc_bcms[] = { &bcm_sn11, }; -static struct qcom_icc_node *system_noc_nodes[] = { +static struct qcom_icc_node * const system_noc_nodes[] = { [MASTER_AUDIO] = &qhm_audio, [MASTER_BLSP_1] = &qhm_blsp1, [MASTER_QDSS_BAM] = &qhm_qdss_bam, @@ -223,7 +223,7 @@ static struct qcom_icc_bcm *ipa_virt_bcms[] = { &bcm_ip0, }; -static struct qcom_icc_node *ipa_virt_nodes[] = { +static struct qcom_icc_node * const ipa_virt_nodes[] = { [MASTER_IPA_CORE] = &ipa_core_master, [SLAVE_IPA_CORE] = &ipa_core_slave, }; diff --git a/drivers/interconnect/qcom/sm8150.c b/drivers/interconnect/qcom/sm8150.c index 4f3bdc530dcf..5e08f2fba2a8 100644 --- a/drivers/interconnect/qcom/sm8150.c +++ b/drivers/interconnect/qcom/sm8150.c @@ -191,7 +191,7 @@ static struct qcom_icc_bcm *aggre1_noc_bcms[] = { &bcm_sn3, }; -static struct qcom_icc_node *aggre1_noc_nodes[] = { +static struct qcom_icc_node * const aggre1_noc_nodes[] = { [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, [MASTER_QUP_0] = &qhm_qup0, [MASTER_EMAC] = &xm_emac, @@ -216,7 +216,7 @@ static struct qcom_icc_bcm *aggre2_noc_bcms[] = { &bcm_sn3, }; -static struct qcom_icc_node *aggre2_noc_nodes[] = { +static struct qcom_icc_node * const aggre2_noc_nodes[] = { [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, [MASTER_QDSS_BAM] = &qhm_qdss_bam, [MASTER_QSPI] = &qhm_qspi, @@ -248,7 +248,7 @@ static struct qcom_icc_bcm *camnoc_virt_bcms[] = { &bcm_mm1, }; -static struct qcom_icc_node *camnoc_virt_nodes[] = { +static struct qcom_icc_node * const camnoc_virt_nodes[] = { [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp, [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp, [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp, @@ -267,7 +267,7 @@ static struct qcom_icc_bcm *compute_noc_bcms[] = { &bcm_co1, }; -static struct qcom_icc_node *compute_noc_nodes[] = { +static struct qcom_icc_node * const compute_noc_nodes[] = { [MASTER_NPU] = &qnm_npu, [SLAVE_CDSP_MEM_NOC] = &qns_cdsp_mem_noc, }; @@ -283,7 +283,7 @@ static struct qcom_icc_bcm *config_noc_bcms[] = { &bcm_cn0, }; -static struct qcom_icc_node *config_noc_nodes[] = { +static struct qcom_icc_node * const config_noc_nodes[] = { [MASTER_SPDM] = &qhm_spdm, [SNOC_CNOC_MAS] = &qnm_snoc, [MASTER_QDSS_DAP] = &xm_qdss_dap, @@ -350,7 +350,7 @@ static const struct qcom_icc_desc sm8150_config_noc = { static struct qcom_icc_bcm *dc_noc_bcms[] = { }; -static struct qcom_icc_node *dc_noc_nodes[] = { +static struct qcom_icc_node * const dc_noc_nodes[] = { [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc, [SLAVE_LLCC_CFG] = &qhs_llcc, [SLAVE_GEM_NOC_CFG] = &qhs_memnoc, @@ -371,7 +371,7 @@ static struct qcom_icc_bcm *gem_noc_bcms[] = { &bcm_sh5, }; -static struct qcom_icc_node *gem_noc_nodes[] = { +static struct qcom_icc_node * const gem_noc_nodes[] = { [MASTER_AMPSS_M0] = &acm_apps, [MASTER_GPU_TCU] = &acm_gpu_tcu, [MASTER_SYS_TCU] = &acm_sys_tcu, @@ -402,7 +402,7 @@ static struct qcom_icc_bcm *ipa_virt_bcms[] = { &bcm_ip0, }; -static struct qcom_icc_node *ipa_virt_nodes[] = { +static struct qcom_icc_node * const ipa_virt_nodes[] = { [MASTER_IPA_CORE] = &ipa_core_master, [SLAVE_IPA_CORE] = &ipa_core_slave, }; @@ -419,7 +419,7 @@ static struct qcom_icc_bcm *mc_virt_bcms[] = { &bcm_mc0, }; -static struct qcom_icc_node *mc_virt_nodes[] = { +static struct qcom_icc_node * const mc_virt_nodes[] = { [MASTER_LLCC] = &llcc_mc, [SLAVE_EBI_CH0] = &ebi, }; @@ -438,7 +438,7 @@ static struct qcom_icc_bcm *mmss_noc_bcms[] = { &bcm_mm3, }; -static struct qcom_icc_node *mmss_noc_nodes[] = { +static struct qcom_icc_node * const mmss_noc_nodes[] = { [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0, [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1, @@ -475,7 +475,7 @@ static struct qcom_icc_bcm *system_noc_bcms[] = { &bcm_sn9, }; -static struct qcom_icc_node *system_noc_nodes[] = { +static struct qcom_icc_node * const system_noc_nodes[] = { [MASTER_SNOC_CFG] = &qhm_snoc_cfg, [A1NOC_SNOC_MAS] = &qnm_aggre1_noc, [A2NOC_SNOC_MAS] = &qnm_aggre2_noc, diff --git a/drivers/interconnect/qcom/sm8250.c b/drivers/interconnect/qcom/sm8250.c index b2e12b01a5e8..b186a76493ba 100644 --- a/drivers/interconnect/qcom/sm8250.c +++ b/drivers/interconnect/qcom/sm8250.c @@ -200,7 +200,7 @@ static struct qcom_icc_bcm *aggre1_noc_bcms[] = { &bcm_sn12, }; -static struct qcom_icc_node *aggre1_noc_nodes[] = { +static struct qcom_icc_node * const aggre1_noc_nodes[] = { [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, [MASTER_QSPI_0] = &qhm_qspi, [MASTER_QUP_1] = &qhm_qup1, @@ -229,7 +229,7 @@ static struct qcom_icc_bcm *aggre2_noc_bcms[] = { &bcm_sn12, }; -static struct qcom_icc_node *aggre2_noc_nodes[] = { +static struct qcom_icc_node * const aggre2_noc_nodes[] = { [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, [MASTER_QDSS_BAM] = &qhm_qdss_bam, [MASTER_QUP_0] = &qhm_qup0, @@ -258,7 +258,7 @@ static struct qcom_icc_bcm *compute_noc_bcms[] = { &bcm_co2, }; -static struct qcom_icc_node *compute_noc_nodes[] = { +static struct qcom_icc_node * const compute_noc_nodes[] = { [MASTER_NPU] = &qnm_npu, [SLAVE_CDSP_MEM_NOC] = &qns_cdsp_mem_noc, }; @@ -274,7 +274,7 @@ static struct qcom_icc_bcm *config_noc_bcms[] = { &bcm_cn0, }; -static struct qcom_icc_node *config_noc_nodes[] = { +static struct qcom_icc_node * const config_noc_nodes[] = { [SNOC_CNOC_MAS] = &qnm_snoc, [MASTER_QDSS_DAP] = &xm_qdss_dap, [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg, @@ -339,7 +339,7 @@ static const struct qcom_icc_desc sm8250_config_noc = { static struct qcom_icc_bcm *dc_noc_bcms[] = { }; -static struct qcom_icc_node *dc_noc_nodes[] = { +static struct qcom_icc_node * const dc_noc_nodes[] = { [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc, [SLAVE_LLCC_CFG] = &qhs_llcc, [SLAVE_GEM_NOC_CFG] = &qhs_memnoc, @@ -359,7 +359,7 @@ static struct qcom_icc_bcm *gem_noc_bcms[] = { &bcm_sh4, }; -static struct qcom_icc_node *gem_noc_nodes[] = { +static struct qcom_icc_node * const gem_noc_nodes[] = { [MASTER_GPU_TCU] = &alm_gpu_tcu, [MASTER_SYS_TCU] = &alm_sys_tcu, [MASTER_AMPSS_M0] = &chm_apps, @@ -390,7 +390,7 @@ static struct qcom_icc_bcm *ipa_virt_bcms[] = { &bcm_ip0, }; -static struct qcom_icc_node *ipa_virt_nodes[] = { +static struct qcom_icc_node * const ipa_virt_nodes[] = { [MASTER_IPA_CORE] = &ipa_core_master, [SLAVE_IPA_CORE] = &ipa_core_slave, }; @@ -407,7 +407,7 @@ static struct qcom_icc_bcm *mc_virt_bcms[] = { &bcm_mc0, }; -static struct qcom_icc_node *mc_virt_nodes[] = { +static struct qcom_icc_node * const mc_virt_nodes[] = { [MASTER_LLCC] = &llcc_mc, [SLAVE_EBI_CH0] = &ebi, }; @@ -426,7 +426,7 @@ static struct qcom_icc_bcm *mmss_noc_bcms[] = { &bcm_mm3, }; -static struct qcom_icc_node *mmss_noc_nodes[] = { +static struct qcom_icc_node * const mmss_noc_nodes[] = { [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, @@ -452,7 +452,7 @@ static const struct qcom_icc_desc sm8250_mmss_noc = { static struct qcom_icc_bcm *npu_noc_bcms[] = { }; -static struct qcom_icc_node *npu_noc_nodes[] = { +static struct qcom_icc_node * const npu_noc_nodes[] = { [MASTER_NPU_SYS] = &amm_npu_sys, [MASTER_NPU_CDP] = &amm_npu_sys_cdp_w, [MASTER_NPU_NOC_CFG] = &qhm_cfg, @@ -489,7 +489,7 @@ static struct qcom_icc_bcm *system_noc_bcms[] = { &bcm_sn9, }; -static struct qcom_icc_node *system_noc_nodes[] = { +static struct qcom_icc_node * const system_noc_nodes[] = { [MASTER_SNOC_CFG] = &qhm_snoc_cfg, [A1NOC_SNOC_MAS] = &qnm_aggre1_noc, [A2NOC_SNOC_MAS] = &qnm_aggre2_noc, diff --git a/drivers/interconnect/qcom/sm8350.c b/drivers/interconnect/qcom/sm8350.c index 936164391d6a..dd0809f08388 100644 --- a/drivers/interconnect/qcom/sm8350.c +++ b/drivers/interconnect/qcom/sm8350.c @@ -201,7 +201,7 @@ DEFINE_QBCM(bcm_sh0_disp, "SH0", false, &qns_llcc_disp); static struct qcom_icc_bcm *aggre1_noc_bcms[] = { }; -static struct qcom_icc_node *aggre1_noc_nodes[] = { +static struct qcom_icc_node * const aggre1_noc_nodes[] = { [MASTER_QSPI_0] = &qhm_qspi, [MASTER_QUP_1] = &qhm_qup1, [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg, @@ -227,7 +227,7 @@ static struct qcom_icc_bcm *aggre2_noc_bcms[] = { &bcm_sn14, }; -static struct qcom_icc_node *aggre2_noc_nodes[] = { +static struct qcom_icc_node * const aggre2_noc_nodes[] = { [MASTER_QDSS_BAM] = &qhm_qdss_bam, [MASTER_QUP_0] = &qhm_qup0, [MASTER_QUP_2] = &qhm_qup2, @@ -259,7 +259,7 @@ static struct qcom_icc_bcm *config_noc_bcms[] = { &bcm_sn4, }; -static struct qcom_icc_node *config_noc_nodes[] = { +static struct qcom_icc_node * const config_noc_nodes[] = { [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, [MASTER_QDSS_DAP] = &xm_qdss_dap, @@ -333,7 +333,7 @@ static const struct qcom_icc_desc sm8350_config_noc = { static struct qcom_icc_bcm *dc_noc_bcms[] = { }; -static struct qcom_icc_node *dc_noc_nodes[] = { +static struct qcom_icc_node * const dc_noc_nodes[] = { [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc, [SLAVE_LLCC_CFG] = &qhs_llcc, [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, @@ -354,7 +354,7 @@ static struct qcom_icc_bcm *gem_noc_bcms[] = { &bcm_sh0_disp, }; -static struct qcom_icc_node *gem_noc_nodes[] = { +static struct qcom_icc_node * const gem_noc_nodes[] = { [MASTER_GPU_TCU] = &alm_gpu_tcu, [MASTER_SYS_TCU] = &alm_sys_tcu, [MASTER_APPSS_PROC] = &chm_apps, @@ -389,7 +389,7 @@ static const struct qcom_icc_desc sm8350_gem_noc = { static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = { }; -static struct qcom_icc_node *lpass_ag_noc_nodes[] = { +static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, @@ -413,7 +413,7 @@ static struct qcom_icc_bcm *mc_virt_bcms[] = { &bcm_mc0_disp, }; -static struct qcom_icc_node *mc_virt_nodes[] = { +static struct qcom_icc_node * const mc_virt_nodes[] = { [MASTER_LLCC] = &llcc_mc, [SLAVE_EBI1] = &ebi, [MASTER_LLCC_DISP] = &llcc_mc_disp, @@ -438,7 +438,7 @@ static struct qcom_icc_bcm *mmss_noc_bcms[] = { &bcm_mm5_disp, }; -static struct qcom_icc_node *mmss_noc_nodes[] = { +static struct qcom_icc_node * const mmss_noc_nodes[] = { [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, @@ -471,7 +471,7 @@ static struct qcom_icc_bcm *nsp_noc_bcms[] = { &bcm_co3, }; -static struct qcom_icc_node *nsp_noc_nodes[] = { +static struct qcom_icc_node * const nsp_noc_nodes[] = { [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, [MASTER_CDSP_PROC] = &qxm_nsp, [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, @@ -492,7 +492,7 @@ static struct qcom_icc_bcm *system_noc_bcms[] = { &bcm_sn8, }; -static struct qcom_icc_node *system_noc_nodes[] = { +static struct qcom_icc_node * const system_noc_nodes[] = { [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, [MASTER_SNOC_CFG] = &qnm_snoc_cfg, diff --git a/drivers/interconnect/qcom/sm8450.c b/drivers/interconnect/qcom/sm8450.c index dbec8228e2e4..71fc31f59407 100644 --- a/drivers/interconnect/qcom/sm8450.c +++ b/drivers/interconnect/qcom/sm8450.c @@ -1529,7 +1529,7 @@ static struct qcom_icc_bcm bcm_sh1_disp = { static struct qcom_icc_bcm *aggre1_noc_bcms[] = { }; -static struct qcom_icc_node *aggre1_noc_nodes[] = { +static struct qcom_icc_node * const aggre1_noc_nodes[] = { [MASTER_QSPI_0] = &qhm_qspi, [MASTER_QUP_1] = &qhm_qup1, [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg, @@ -1551,7 +1551,7 @@ static struct qcom_icc_bcm *aggre2_noc_bcms[] = { &bcm_ce0, }; -static struct qcom_icc_node *aggre2_noc_nodes[] = { +static struct qcom_icc_node * const aggre2_noc_nodes[] = { [MASTER_QDSS_BAM] = &qhm_qdss_bam, [MASTER_QUP_0] = &qhm_qup0, [MASTER_QUP_2] = &qhm_qup2, @@ -1580,7 +1580,7 @@ static struct qcom_icc_bcm *clk_virt_bcms[] = { &bcm_qup2, }; -static struct qcom_icc_node *clk_virt_nodes[] = { +static struct qcom_icc_node * const clk_virt_nodes[] = { [MASTER_QUP_CORE_0] = &qup0_core_master, [MASTER_QUP_CORE_1] = &qup1_core_master, [MASTER_QUP_CORE_2] = &qup2_core_master, @@ -1600,7 +1600,7 @@ static struct qcom_icc_bcm *config_noc_bcms[] = { &bcm_cn0, }; -static struct qcom_icc_node *config_noc_nodes[] = { +static struct qcom_icc_node * const config_noc_nodes[] = { [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, @@ -1672,7 +1672,7 @@ static struct qcom_icc_bcm *gem_noc_bcms[] = { &bcm_sh1_disp, }; -static struct qcom_icc_node *gem_noc_nodes[] = { +static struct qcom_icc_node * const gem_noc_nodes[] = { [MASTER_GPU_TCU] = &alm_gpu_tcu, [MASTER_SYS_TCU] = &alm_sys_tcu, [MASTER_APPSS_PROC] = &chm_apps, @@ -1703,7 +1703,7 @@ static const struct qcom_icc_desc sm8450_gem_noc = { static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = { }; -static struct qcom_icc_node *lpass_ag_noc_nodes[] = { +static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, [MASTER_LPASS_PROC] = &qxm_lpass_dsp, [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, @@ -1729,7 +1729,7 @@ static struct qcom_icc_bcm *mc_virt_bcms[] = { &bcm_mc0_disp, }; -static struct qcom_icc_node *mc_virt_nodes[] = { +static struct qcom_icc_node * const mc_virt_nodes[] = { [MASTER_LLCC] = &llcc_mc, [SLAVE_EBI1] = &ebi, [MASTER_LLCC_DISP] = &llcc_mc_disp, @@ -1750,7 +1750,7 @@ static struct qcom_icc_bcm *mmss_noc_bcms[] = { &bcm_mm1_disp, }; -static struct qcom_icc_node *mmss_noc_nodes[] = { +static struct qcom_icc_node * const mmss_noc_nodes[] = { [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, @@ -1782,7 +1782,7 @@ static struct qcom_icc_bcm *nsp_noc_bcms[] = { &bcm_co0, }; -static struct qcom_icc_node *nsp_noc_nodes[] = { +static struct qcom_icc_node * const nsp_noc_nodes[] = { [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, [MASTER_CDSP_PROC] = &qxm_nsp, [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, @@ -1800,7 +1800,7 @@ static struct qcom_icc_bcm *pcie_anoc_bcms[] = { &bcm_sn7, }; -static struct qcom_icc_node *pcie_anoc_nodes[] = { +static struct qcom_icc_node * const pcie_anoc_nodes[] = { [MASTER_PCIE_ANOC_CFG] = &qnm_pcie_anoc_cfg, [MASTER_PCIE_0] = &xm_pcie3_0, [MASTER_PCIE_1] = &xm_pcie3_1, @@ -1823,7 +1823,7 @@ static struct qcom_icc_bcm *system_noc_bcms[] = { &bcm_sn4, }; -static struct qcom_icc_node *system_noc_nodes[] = { +static struct qcom_icc_node * const system_noc_nodes[] = { [MASTER_GIC_AHB] = &qhm_gic, [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, @@ -1848,7 +1848,7 @@ static int qnoc_probe(struct platform_device *pdev) const struct qcom_icc_desc *desc; struct icc_onecell_data *data; struct icc_provider *provider; - struct qcom_icc_node **qnodes; + struct qcom_icc_node * const *qnodes; struct qcom_icc_provider *qp; struct icc_node *node; size_t num_nodes, i; From patchwork Tue Apr 12 10:26:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 561146 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40282C433EF for ; Tue, 12 Apr 2022 11:44:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244507AbiDLLqj (ORCPT ); Tue, 12 Apr 2022 07:46:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35504 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235979AbiDLLqA (ORCPT ); Tue, 12 Apr 2022 07:46:00 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D25EB7C782 for ; Tue, 12 Apr 2022 03:26:31 -0700 (PDT) Received: by mail-ej1-x635.google.com with SMTP id p15so36373534ejc.7 for ; Tue, 12 Apr 2022 03:26:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jrW/94cAa5hNSk55rAAwC9rYait37O4q4k3EokURmfk=; b=iAgiRWQdZyFos/TNNKR/PiDgndtsLB14oCW9Ap6BCQTuXAMLDNRKR+HEipBoV5j/RS rkaPVykP16ohiNJUwOcR8EVYzEb9rnwLUeLyJ9Mt4JxtcqrgqzKSe/5FCXr9B7jxlzGy NUA8BSXqE3wEaDP1U33TJogDAqq+dIHSLoyZcqBnri3Y8l0KtqB+kWSu5dBCEYRxbtUw PhULvB0uy7QNVggp+nanvQozu2dB1XUgTX1a+6hxk5X6dy5bAPX/M8UZf0A6VRjokkq9 QF/yCuFIWp7BewrBNPiQgEW4leQZNbQseA4NoO8hiJPyIjWiF/HGlpuvHcHEdKbNV7IM z3ZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jrW/94cAa5hNSk55rAAwC9rYait37O4q4k3EokURmfk=; b=fJXlHZ+KnZyfYcVw+lkUGqPe1FSZWfbVLJNyxgIZrU5Mwu5L3uNULLGfvh/lq431Zq qxjvdOChTy2LR0CkvTrHLpbGWiEJeYJ6DnpH/i3Qhp6CFfIM3zDBRxzsM5pw9nWoNUHg JbJBvtwHDzFACjI+pGuzLgv7jUuEnrEJIIgdM5p2iKImYkQ3cQwMS2THOP42D8ZGVV6h lNhrfgH42bM7T9I4huEz6KgUSj/uaUndr3EWHbm7nl+pkLqNqYQSR95jLBZqmd/884XM 7uV3hmSXjYf6/VJ6wVFV+aIBNszFTFeHwrue7BmRorTc54I3WW7Oz/ePQ5FEvD9ESAMb xn3A== X-Gm-Message-State: AOAM530KgSv4J1wLLVx91oIqKxzhFPEqWANp7AXZRvZrhBrVV0bbP7og XpsW5xTJCfJZjysPZH+OCLSGIA== X-Google-Smtp-Source: ABdhPJxQ0DFgtHdPc7npkD3wNC7QSKrKJsMeJGJez/mZHjEuG4i7/jCS+AcT2gEVgn28sGKCD8b45Q== X-Received: by 2002:a17:906:3ecc:b0:6e7:f3f1:ea8b with SMTP id d12-20020a1709063ecc00b006e7f3f1ea8bmr13281643ejj.725.1649759190303; Tue, 12 Apr 2022 03:26:30 -0700 (PDT) Received: from localhost.localdomain (xdsl-188-155-201-27.adslplus.ch. [188.155.201.27]) by smtp.gmail.com with ESMTPSA id z21-20020a170906435500b006e8669fae36sm4468959ejm.189.2022.04.12.03.26.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Apr 2022 03:26:29 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Georgi Djakov , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 3/3] interconnect: qcom: constify qcom_icc_bcm pointers Date: Tue, 12 Apr 2022 12:26:23 +0200 Message-Id: <20220412102623.227607-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220412102623.227607-1-krzysztof.kozlowski@linaro.org> References: <20220412102623.227607-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Pointers to struct qcom_icc_bcm are not modified, so they can be made const for safety. The contents of struct qcom_icc_bcm must stay non-const. Signed-off-by: Krzysztof Kozlowski --- drivers/interconnect/qcom/icc-rpmh.h | 4 ++-- drivers/interconnect/qcom/sc7180.c | 22 +++++++++++----------- drivers/interconnect/qcom/sc7280.c | 24 ++++++++++++------------ drivers/interconnect/qcom/sc8180x.c | 20 ++++++++++---------- drivers/interconnect/qcom/sdm845.c | 16 ++++++++-------- drivers/interconnect/qcom/sdx55.c | 8 ++++---- drivers/interconnect/qcom/sm8150.c | 22 +++++++++++----------- drivers/interconnect/qcom/sm8250.c | 22 +++++++++++----------- drivers/interconnect/qcom/sm8350.c | 20 ++++++++++---------- drivers/interconnect/qcom/sm8450.c | 22 +++++++++++----------- 10 files changed, 90 insertions(+), 90 deletions(-) diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h index 5dfc26072593..d29929461c17 100644 --- a/drivers/interconnect/qcom/icc-rpmh.h +++ b/drivers/interconnect/qcom/icc-rpmh.h @@ -22,7 +22,7 @@ struct qcom_icc_provider { struct icc_provider provider; struct device *dev; - struct qcom_icc_bcm **bcms; + struct qcom_icc_bcm * const *bcms; size_t num_bcms; struct bcm_voter *voter; }; @@ -114,7 +114,7 @@ struct qcom_icc_fabric { struct qcom_icc_desc { struct qcom_icc_node * const *nodes; size_t num_nodes; - struct qcom_icc_bcm **bcms; + struct qcom_icc_bcm * const *bcms; size_t num_bcms; }; diff --git a/drivers/interconnect/qcom/sc7180.c b/drivers/interconnect/qcom/sc7180.c index 11e221edbd1c..67191230f05b 100644 --- a/drivers/interconnect/qcom/sc7180.c +++ b/drivers/interconnect/qcom/sc7180.c @@ -181,7 +181,7 @@ DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc); DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_aggre2_noc); DEFINE_QBCM(bcm_sn12, "SN12", false, &qnm_gemnoc); -static struct qcom_icc_bcm *aggre1_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { &bcm_cn1, }; @@ -203,7 +203,7 @@ static const struct qcom_icc_desc sc7180_aggre1_noc = { .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), }; -static struct qcom_icc_bcm *aggre2_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { &bcm_ce0, }; @@ -226,7 +226,7 @@ static const struct qcom_icc_desc sc7180_aggre2_noc = { .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), }; -static struct qcom_icc_bcm *camnoc_virt_bcms[] = { +static struct qcom_icc_bcm * const camnoc_virt_bcms[] = { &bcm_mm1, }; @@ -244,7 +244,7 @@ static const struct qcom_icc_desc sc7180_camnoc_virt = { .num_bcms = ARRAY_SIZE(camnoc_virt_bcms), }; -static struct qcom_icc_bcm *compute_noc_bcms[] = { +static struct qcom_icc_bcm * const compute_noc_bcms[] = { &bcm_co0, &bcm_co2, &bcm_co3, @@ -263,7 +263,7 @@ static const struct qcom_icc_desc sc7180_compute_noc = { .num_bcms = ARRAY_SIZE(compute_noc_bcms), }; -static struct qcom_icc_bcm *config_noc_bcms[] = { +static struct qcom_icc_bcm * const config_noc_bcms[] = { &bcm_cn0, &bcm_cn1, }; @@ -342,7 +342,7 @@ static const struct qcom_icc_desc sc7180_dc_noc = { .num_nodes = ARRAY_SIZE(dc_noc_nodes), }; -static struct qcom_icc_bcm *gem_noc_bcms[] = { +static struct qcom_icc_bcm * const gem_noc_bcms[] = { &bcm_sh0, &bcm_sh2, &bcm_sh3, @@ -372,7 +372,7 @@ static const struct qcom_icc_desc sc7180_gem_noc = { .num_bcms = ARRAY_SIZE(gem_noc_bcms), }; -static struct qcom_icc_bcm *ipa_virt_bcms[] = { +static struct qcom_icc_bcm * const ipa_virt_bcms[] = { &bcm_ip0, }; @@ -388,7 +388,7 @@ static const struct qcom_icc_desc sc7180_ipa_virt = { .num_bcms = ARRAY_SIZE(ipa_virt_bcms), }; -static struct qcom_icc_bcm *mc_virt_bcms[] = { +static struct qcom_icc_bcm * const mc_virt_bcms[] = { &bcm_acv, &bcm_mc0, }; @@ -405,7 +405,7 @@ static const struct qcom_icc_desc sc7180_mc_virt = { .num_bcms = ARRAY_SIZE(mc_virt_bcms), }; -static struct qcom_icc_bcm *mmss_noc_bcms[] = { +static struct qcom_icc_bcm * const mmss_noc_bcms[] = { &bcm_mm0, &bcm_mm1, &bcm_mm2, @@ -451,7 +451,7 @@ static const struct qcom_icc_desc sc7180_npu_noc = { .num_nodes = ARRAY_SIZE(npu_noc_nodes), }; -static struct qcom_icc_bcm *qup_virt_bcms[] = { +static struct qcom_icc_bcm * const qup_virt_bcms[] = { &bcm_qup0, }; @@ -469,7 +469,7 @@ static const struct qcom_icc_desc sc7180_qup_virt = { .num_bcms = ARRAY_SIZE(qup_virt_bcms), }; -static struct qcom_icc_bcm *system_noc_bcms[] = { +static struct qcom_icc_bcm * const system_noc_bcms[] = { &bcm_sn0, &bcm_sn1, &bcm_sn2, diff --git a/drivers/interconnect/qcom/sc7280.c b/drivers/interconnect/qcom/sc7280.c index d969bc6c4610..971f538bc98a 100644 --- a/drivers/interconnect/qcom/sc7280.c +++ b/drivers/interconnect/qcom/sc7280.c @@ -1476,7 +1476,7 @@ static struct qcom_icc_bcm bcm_sn14 = { .nodes = { &qns_pcie_mem_noc }, }; -static struct qcom_icc_bcm *aggre1_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { &bcm_sn5, &bcm_sn6, &bcm_sn14, @@ -1507,7 +1507,7 @@ static const struct qcom_icc_desc sc7280_aggre1_noc = { .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), }; -static struct qcom_icc_bcm *aggre2_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { &bcm_ce0, }; @@ -1529,7 +1529,7 @@ static const struct qcom_icc_desc sc7280_aggre2_noc = { .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), }; -static struct qcom_icc_bcm *clk_virt_bcms[] = { +static struct qcom_icc_bcm * const clk_virt_bcms[] = { &bcm_qup0, &bcm_qup1, }; @@ -1548,7 +1548,7 @@ static const struct qcom_icc_desc sc7280_clk_virt = { .num_bcms = ARRAY_SIZE(clk_virt_bcms), }; -static struct qcom_icc_bcm *cnoc2_bcms[] = { +static struct qcom_icc_bcm * const cnoc2_bcms[] = { &bcm_cn1, &bcm_cn2, }; @@ -1610,7 +1610,7 @@ static const struct qcom_icc_desc sc7280_cnoc2 = { .num_bcms = ARRAY_SIZE(cnoc2_bcms), }; -static struct qcom_icc_bcm *cnoc3_bcms[] = { +static struct qcom_icc_bcm * const cnoc3_bcms[] = { &bcm_cn0, &bcm_cn1, &bcm_sn3, @@ -1642,7 +1642,7 @@ static const struct qcom_icc_desc sc7280_cnoc3 = { .num_bcms = ARRAY_SIZE(cnoc3_bcms), }; -static struct qcom_icc_bcm *dc_noc_bcms[] = { +static struct qcom_icc_bcm * const dc_noc_bcms[] = { }; static struct qcom_icc_node * const dc_noc_nodes[] = { @@ -1658,7 +1658,7 @@ static const struct qcom_icc_desc sc7280_dc_noc = { .num_bcms = ARRAY_SIZE(dc_noc_bcms), }; -static struct qcom_icc_bcm *gem_noc_bcms[] = { +static struct qcom_icc_bcm * const gem_noc_bcms[] = { &bcm_sh0, &bcm_sh2, &bcm_sh3, @@ -1694,7 +1694,7 @@ static const struct qcom_icc_desc sc7280_gem_noc = { .num_bcms = ARRAY_SIZE(gem_noc_bcms), }; -static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = { +static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { }; static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { @@ -1714,7 +1714,7 @@ static const struct qcom_icc_desc sc7280_lpass_ag_noc = { .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), }; -static struct qcom_icc_bcm *mc_virt_bcms[] = { +static struct qcom_icc_bcm * const mc_virt_bcms[] = { &bcm_acv, &bcm_mc0, }; @@ -1731,7 +1731,7 @@ static const struct qcom_icc_desc sc7280_mc_virt = { .num_bcms = ARRAY_SIZE(mc_virt_bcms), }; -static struct qcom_icc_bcm *mmss_noc_bcms[] = { +static struct qcom_icc_bcm * const mmss_noc_bcms[] = { &bcm_mm0, &bcm_mm1, &bcm_mm4, @@ -1758,7 +1758,7 @@ static const struct qcom_icc_desc sc7280_mmss_noc = { .num_bcms = ARRAY_SIZE(mmss_noc_bcms), }; -static struct qcom_icc_bcm *nsp_noc_bcms[] = { +static struct qcom_icc_bcm * const nsp_noc_bcms[] = { &bcm_co0, &bcm_co3, }; @@ -1777,7 +1777,7 @@ static const struct qcom_icc_desc sc7280_nsp_noc = { .num_bcms = ARRAY_SIZE(nsp_noc_bcms), }; -static struct qcom_icc_bcm *system_noc_bcms[] = { +static struct qcom_icc_bcm * const system_noc_bcms[] = { &bcm_sn0, &bcm_sn2, &bcm_sn7, diff --git a/drivers/interconnect/qcom/sc8180x.c b/drivers/interconnect/qcom/sc8180x.c index f6b69b9df410..136c62afb3b2 100644 --- a/drivers/interconnect/qcom/sc8180x.c +++ b/drivers/interconnect/qcom/sc8180x.c @@ -191,53 +191,53 @@ DEFINE_QBCM(bcm_sn11, "SN11", false, &mas_qnm_aggre2_noc); DEFINE_QBCM(bcm_sn14, "SN14", false, &slv_qns_pcie_mem_noc); DEFINE_QBCM(bcm_sn15, "SN15", false, &mas_qnm_gemnoc); -static struct qcom_icc_bcm *aggre1_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { &bcm_sn3, &bcm_ce0, &bcm_qup0, }; -static struct qcom_icc_bcm *aggre2_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { &bcm_sn14, &bcm_ce0, &bcm_qup0, }; -static struct qcom_icc_bcm *camnoc_virt_bcms[] = { +static struct qcom_icc_bcm * const camnoc_virt_bcms[] = { &bcm_mm1, }; -static struct qcom_icc_bcm *compute_noc_bcms[] = { +static struct qcom_icc_bcm * const compute_noc_bcms[] = { &bcm_co0, &bcm_co2, }; -static struct qcom_icc_bcm *config_noc_bcms[] = { +static struct qcom_icc_bcm * const config_noc_bcms[] = { &bcm_cn0, }; -static struct qcom_icc_bcm *gem_noc_bcms[] = { +static struct qcom_icc_bcm * const gem_noc_bcms[] = { &bcm_sh0, &bcm_sh2, &bcm_sh3, }; -static struct qcom_icc_bcm *ipa_virt_bcms[] = { +static struct qcom_icc_bcm * const ipa_virt_bcms[] = { &bcm_ip0, }; -static struct qcom_icc_bcm *mc_virt_bcms[] = { +static struct qcom_icc_bcm * const mc_virt_bcms[] = { &bcm_mc0, &bcm_acv, }; -static struct qcom_icc_bcm *mmss_noc_bcms[] = { +static struct qcom_icc_bcm * const mmss_noc_bcms[] = { &bcm_mm0, &bcm_mm1, &bcm_mm2, }; -static struct qcom_icc_bcm *system_noc_bcms[] = { +static struct qcom_icc_bcm * const system_noc_bcms[] = { &bcm_sn0, &bcm_sn1, &bcm_sn2, diff --git a/drivers/interconnect/qcom/sdm845.c b/drivers/interconnect/qcom/sdm845.c index 1af0e6972bad..954e7bd13fc4 100644 --- a/drivers/interconnect/qcom/sdm845.c +++ b/drivers/interconnect/qcom/sdm845.c @@ -175,7 +175,7 @@ DEFINE_QBCM(bcm_sn12, "SN12", false, &qnm_gladiator_sodv, &xm_gic); DEFINE_QBCM(bcm_sn14, "SN14", false, &qnm_pcie_anoc); DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_memnoc); -static struct qcom_icc_bcm *aggre1_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { &bcm_sn9, &bcm_qup0, }; @@ -201,7 +201,7 @@ static const struct qcom_icc_desc sdm845_aggre1_noc = { .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), }; -static struct qcom_icc_bcm *aggre2_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { &bcm_ce0, &bcm_sn11, &bcm_qup0, @@ -230,7 +230,7 @@ static const struct qcom_icc_desc sdm845_aggre2_noc = { .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), }; -static struct qcom_icc_bcm *config_noc_bcms[] = { +static struct qcom_icc_bcm * const config_noc_bcms[] = { &bcm_cn0, }; @@ -291,7 +291,7 @@ static const struct qcom_icc_desc sdm845_config_noc = { .num_bcms = ARRAY_SIZE(config_noc_bcms), }; -static struct qcom_icc_bcm *dc_noc_bcms[] = { +static struct qcom_icc_bcm * const dc_noc_bcms[] = { }; static struct qcom_icc_node * const dc_noc_nodes[] = { @@ -307,7 +307,7 @@ static const struct qcom_icc_desc sdm845_dc_noc = { .num_bcms = ARRAY_SIZE(dc_noc_bcms), }; -static struct qcom_icc_bcm *gladiator_noc_bcms[] = { +static struct qcom_icc_bcm * const gladiator_noc_bcms[] = { }; static struct qcom_icc_node * const gladiator_noc_nodes[] = { @@ -325,7 +325,7 @@ static const struct qcom_icc_desc sdm845_gladiator_noc = { .num_bcms = ARRAY_SIZE(gladiator_noc_bcms), }; -static struct qcom_icc_bcm *mem_noc_bcms[] = { +static struct qcom_icc_bcm * const mem_noc_bcms[] = { &bcm_mc0, &bcm_acv, &bcm_sh0, @@ -360,7 +360,7 @@ static const struct qcom_icc_desc sdm845_mem_noc = { .num_bcms = ARRAY_SIZE(mem_noc_bcms), }; -static struct qcom_icc_bcm *mmss_noc_bcms[] = { +static struct qcom_icc_bcm * const mmss_noc_bcms[] = { &bcm_mm0, &bcm_mm1, &bcm_mm2, @@ -394,7 +394,7 @@ static const struct qcom_icc_desc sdm845_mmss_noc = { .num_bcms = ARRAY_SIZE(mmss_noc_bcms), }; -static struct qcom_icc_bcm *system_noc_bcms[] = { +static struct qcom_icc_bcm * const system_noc_bcms[] = { &bcm_sn0, &bcm_sn1, &bcm_sn2, diff --git a/drivers/interconnect/qcom/sdx55.c b/drivers/interconnect/qcom/sdx55.c index 74ebf107d62f..3477e7094718 100644 --- a/drivers/interconnect/qcom/sdx55.c +++ b/drivers/interconnect/qcom/sdx55.c @@ -102,7 +102,7 @@ DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_memnoc); DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_memnoc_pcie); DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_ipa, &xm_ipa2pcie_slv); -static struct qcom_icc_bcm *mc_virt_bcms[] = { +static struct qcom_icc_bcm * const mc_virt_bcms[] = { &bcm_mc0, }; @@ -118,7 +118,7 @@ static const struct qcom_icc_desc sdx55_mc_virt = { .num_bcms = ARRAY_SIZE(mc_virt_bcms), }; -static struct qcom_icc_bcm *mem_noc_bcms[] = { +static struct qcom_icc_bcm * const mem_noc_bcms[] = { &bcm_sh0, &bcm_sh3, &bcm_sh4, @@ -140,7 +140,7 @@ static const struct qcom_icc_desc sdx55_mem_noc = { .num_bcms = ARRAY_SIZE(mem_noc_bcms), }; -static struct qcom_icc_bcm *system_noc_bcms[] = { +static struct qcom_icc_bcm * const system_noc_bcms[] = { &bcm_ce0, &bcm_pn0, &bcm_pn1, @@ -219,7 +219,7 @@ static const struct qcom_icc_desc sdx55_system_noc = { .num_bcms = ARRAY_SIZE(system_noc_bcms), }; -static struct qcom_icc_bcm *ipa_virt_bcms[] = { +static struct qcom_icc_bcm * const ipa_virt_bcms[] = { &bcm_ip0, }; diff --git a/drivers/interconnect/qcom/sm8150.c b/drivers/interconnect/qcom/sm8150.c index 5e08f2fba2a8..1d04a4bfea80 100644 --- a/drivers/interconnect/qcom/sm8150.c +++ b/drivers/interconnect/qcom/sm8150.c @@ -186,7 +186,7 @@ DEFINE_QBCM(bcm_sn12, "SN12", false, &qxm_pimem, &xm_gic); DEFINE_QBCM(bcm_sn14, "SN14", false, &qns_pcie_mem_noc); DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_gemnoc); -static struct qcom_icc_bcm *aggre1_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { &bcm_qup0, &bcm_sn3, }; @@ -209,7 +209,7 @@ static const struct qcom_icc_desc sm8150_aggre1_noc = { .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), }; -static struct qcom_icc_bcm *aggre2_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { &bcm_ce0, &bcm_qup0, &bcm_sn14, @@ -244,7 +244,7 @@ static const struct qcom_icc_desc sm8150_aggre2_noc = { .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), }; -static struct qcom_icc_bcm *camnoc_virt_bcms[] = { +static struct qcom_icc_bcm * const camnoc_virt_bcms[] = { &bcm_mm1, }; @@ -262,7 +262,7 @@ static const struct qcom_icc_desc sm8150_camnoc_virt = { .num_bcms = ARRAY_SIZE(camnoc_virt_bcms), }; -static struct qcom_icc_bcm *compute_noc_bcms[] = { +static struct qcom_icc_bcm * const compute_noc_bcms[] = { &bcm_co0, &bcm_co1, }; @@ -279,7 +279,7 @@ static const struct qcom_icc_desc sm8150_compute_noc = { .num_bcms = ARRAY_SIZE(compute_noc_bcms), }; -static struct qcom_icc_bcm *config_noc_bcms[] = { +static struct qcom_icc_bcm * const config_noc_bcms[] = { &bcm_cn0, }; @@ -347,7 +347,7 @@ static const struct qcom_icc_desc sm8150_config_noc = { .num_bcms = ARRAY_SIZE(config_noc_bcms), }; -static struct qcom_icc_bcm *dc_noc_bcms[] = { +static struct qcom_icc_bcm * const dc_noc_bcms[] = { }; static struct qcom_icc_node * const dc_noc_nodes[] = { @@ -363,7 +363,7 @@ static const struct qcom_icc_desc sm8150_dc_noc = { .num_bcms = ARRAY_SIZE(dc_noc_bcms), }; -static struct qcom_icc_bcm *gem_noc_bcms[] = { +static struct qcom_icc_bcm * const gem_noc_bcms[] = { &bcm_sh0, &bcm_sh2, &bcm_sh3, @@ -398,7 +398,7 @@ static const struct qcom_icc_desc sm8150_gem_noc = { .num_bcms = ARRAY_SIZE(gem_noc_bcms), }; -static struct qcom_icc_bcm *ipa_virt_bcms[] = { +static struct qcom_icc_bcm * const ipa_virt_bcms[] = { &bcm_ip0, }; @@ -414,7 +414,7 @@ static const struct qcom_icc_desc sm8150_ipa_virt = { .num_bcms = ARRAY_SIZE(ipa_virt_bcms), }; -static struct qcom_icc_bcm *mc_virt_bcms[] = { +static struct qcom_icc_bcm * const mc_virt_bcms[] = { &bcm_acv, &bcm_mc0, }; @@ -431,7 +431,7 @@ static const struct qcom_icc_desc sm8150_mc_virt = { .num_bcms = ARRAY_SIZE(mc_virt_bcms), }; -static struct qcom_icc_bcm *mmss_noc_bcms[] = { +static struct qcom_icc_bcm * const mmss_noc_bcms[] = { &bcm_mm0, &bcm_mm1, &bcm_mm2, @@ -461,7 +461,7 @@ static const struct qcom_icc_desc sm8150_mmss_noc = { .num_bcms = ARRAY_SIZE(mmss_noc_bcms), }; -static struct qcom_icc_bcm *system_noc_bcms[] = { +static struct qcom_icc_bcm * const system_noc_bcms[] = { &bcm_sn0, &bcm_sn1, &bcm_sn11, diff --git a/drivers/interconnect/qcom/sm8250.c b/drivers/interconnect/qcom/sm8250.c index b186a76493ba..5cdb058fa095 100644 --- a/drivers/interconnect/qcom/sm8250.c +++ b/drivers/interconnect/qcom/sm8250.c @@ -195,7 +195,7 @@ DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_gemnoc_pcie); DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gemnoc); DEFINE_QBCM(bcm_sn12, "SN12", false, &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc); -static struct qcom_icc_bcm *aggre1_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { &bcm_qup0, &bcm_sn12, }; @@ -223,7 +223,7 @@ static const struct qcom_icc_desc sm8250_aggre1_noc = { .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), }; -static struct qcom_icc_bcm *aggre2_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { &bcm_ce0, &bcm_qup0, &bcm_sn12, @@ -253,7 +253,7 @@ static const struct qcom_icc_desc sm8250_aggre2_noc = { .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), }; -static struct qcom_icc_bcm *compute_noc_bcms[] = { +static struct qcom_icc_bcm * const compute_noc_bcms[] = { &bcm_co0, &bcm_co2, }; @@ -270,7 +270,7 @@ static const struct qcom_icc_desc sm8250_compute_noc = { .num_bcms = ARRAY_SIZE(compute_noc_bcms), }; -static struct qcom_icc_bcm *config_noc_bcms[] = { +static struct qcom_icc_bcm * const config_noc_bcms[] = { &bcm_cn0, }; @@ -336,7 +336,7 @@ static const struct qcom_icc_desc sm8250_config_noc = { .num_bcms = ARRAY_SIZE(config_noc_bcms), }; -static struct qcom_icc_bcm *dc_noc_bcms[] = { +static struct qcom_icc_bcm * const dc_noc_bcms[] = { }; static struct qcom_icc_node * const dc_noc_nodes[] = { @@ -352,7 +352,7 @@ static const struct qcom_icc_desc sm8250_dc_noc = { .num_bcms = ARRAY_SIZE(dc_noc_bcms), }; -static struct qcom_icc_bcm *gem_noc_bcms[] = { +static struct qcom_icc_bcm * const gem_noc_bcms[] = { &bcm_sh0, &bcm_sh2, &bcm_sh3, @@ -386,7 +386,7 @@ static const struct qcom_icc_desc sm8250_gem_noc = { .num_bcms = ARRAY_SIZE(gem_noc_bcms), }; -static struct qcom_icc_bcm *ipa_virt_bcms[] = { +static struct qcom_icc_bcm * const ipa_virt_bcms[] = { &bcm_ip0, }; @@ -402,7 +402,7 @@ static const struct qcom_icc_desc sm8250_ipa_virt = { .num_bcms = ARRAY_SIZE(ipa_virt_bcms), }; -static struct qcom_icc_bcm *mc_virt_bcms[] = { +static struct qcom_icc_bcm * const mc_virt_bcms[] = { &bcm_acv, &bcm_mc0, }; @@ -419,7 +419,7 @@ static const struct qcom_icc_desc sm8250_mc_virt = { .num_bcms = ARRAY_SIZE(mc_virt_bcms), }; -static struct qcom_icc_bcm *mmss_noc_bcms[] = { +static struct qcom_icc_bcm * const mmss_noc_bcms[] = { &bcm_mm0, &bcm_mm1, &bcm_mm2, @@ -449,7 +449,7 @@ static const struct qcom_icc_desc sm8250_mmss_noc = { .num_bcms = ARRAY_SIZE(mmss_noc_bcms), }; -static struct qcom_icc_bcm *npu_noc_bcms[] = { +static struct qcom_icc_bcm * const npu_noc_bcms[] = { }; static struct qcom_icc_node * const npu_noc_nodes[] = { @@ -475,7 +475,7 @@ static const struct qcom_icc_desc sm8250_npu_noc = { .num_bcms = ARRAY_SIZE(npu_noc_bcms), }; -static struct qcom_icc_bcm *system_noc_bcms[] = { +static struct qcom_icc_bcm * const system_noc_bcms[] = { &bcm_sn0, &bcm_sn1, &bcm_sn11, diff --git a/drivers/interconnect/qcom/sm8350.c b/drivers/interconnect/qcom/sm8350.c index dd0809f08388..5398e7c8d826 100644 --- a/drivers/interconnect/qcom/sm8350.c +++ b/drivers/interconnect/qcom/sm8350.c @@ -198,7 +198,7 @@ DEFINE_QBCM(bcm_mm4_disp, "MM4", false, &qns_mem_noc_sf_disp); DEFINE_QBCM(bcm_mm5_disp, "MM5", false, &qxm_rot_disp); DEFINE_QBCM(bcm_sh0_disp, "SH0", false, &qns_llcc_disp); -static struct qcom_icc_bcm *aggre1_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { }; static struct qcom_icc_node * const aggre1_noc_nodes[] = { @@ -220,7 +220,7 @@ static const struct qcom_icc_desc sm8350_aggre1_noc = { .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), }; -static struct qcom_icc_bcm *aggre2_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { &bcm_ce0, &bcm_sn5, &bcm_sn6, @@ -251,7 +251,7 @@ static const struct qcom_icc_desc sm8350_aggre2_noc = { .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), }; -static struct qcom_icc_bcm *config_noc_bcms[] = { +static struct qcom_icc_bcm * const config_noc_bcms[] = { &bcm_cn0, &bcm_cn1, &bcm_cn2, @@ -330,7 +330,7 @@ static const struct qcom_icc_desc sm8350_config_noc = { .num_bcms = ARRAY_SIZE(config_noc_bcms), }; -static struct qcom_icc_bcm *dc_noc_bcms[] = { +static struct qcom_icc_bcm * const dc_noc_bcms[] = { }; static struct qcom_icc_node * const dc_noc_nodes[] = { @@ -346,7 +346,7 @@ static const struct qcom_icc_desc sm8350_dc_noc = { .num_bcms = ARRAY_SIZE(dc_noc_bcms), }; -static struct qcom_icc_bcm *gem_noc_bcms[] = { +static struct qcom_icc_bcm * const gem_noc_bcms[] = { &bcm_sh0, &bcm_sh2, &bcm_sh3, @@ -386,7 +386,7 @@ static const struct qcom_icc_desc sm8350_gem_noc = { .num_bcms = ARRAY_SIZE(gem_noc_bcms), }; -static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = { +static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { }; static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { @@ -406,7 +406,7 @@ static const struct qcom_icc_desc sm8350_lpass_ag_noc = { .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), }; -static struct qcom_icc_bcm *mc_virt_bcms[] = { +static struct qcom_icc_bcm * const mc_virt_bcms[] = { &bcm_acv, &bcm_mc0, &bcm_acv_disp, @@ -427,7 +427,7 @@ static const struct qcom_icc_desc sm8350_mc_virt = { .num_bcms = ARRAY_SIZE(mc_virt_bcms), }; -static struct qcom_icc_bcm *mmss_noc_bcms[] = { +static struct qcom_icc_bcm * const mmss_noc_bcms[] = { &bcm_mm0, &bcm_mm1, &bcm_mm4, @@ -466,7 +466,7 @@ static const struct qcom_icc_desc sm8350_mmss_noc = { .num_bcms = ARRAY_SIZE(mmss_noc_bcms), }; -static struct qcom_icc_bcm *nsp_noc_bcms[] = { +static struct qcom_icc_bcm * const nsp_noc_bcms[] = { &bcm_co0, &bcm_co3, }; @@ -485,7 +485,7 @@ static const struct qcom_icc_desc sm8350_compute_noc = { .num_bcms = ARRAY_SIZE(nsp_noc_bcms), }; -static struct qcom_icc_bcm *system_noc_bcms[] = { +static struct qcom_icc_bcm * const system_noc_bcms[] = { &bcm_sn0, &bcm_sn2, &bcm_sn7, diff --git a/drivers/interconnect/qcom/sm8450.c b/drivers/interconnect/qcom/sm8450.c index 71fc31f59407..7e3d372b712f 100644 --- a/drivers/interconnect/qcom/sm8450.c +++ b/drivers/interconnect/qcom/sm8450.c @@ -1526,7 +1526,7 @@ static struct qcom_icc_bcm bcm_sh1_disp = { .nodes = { &qnm_pcie_disp }, }; -static struct qcom_icc_bcm *aggre1_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { }; static struct qcom_icc_node * const aggre1_noc_nodes[] = { @@ -1547,7 +1547,7 @@ static const struct qcom_icc_desc sm8450_aggre1_noc = { .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), }; -static struct qcom_icc_bcm *aggre2_noc_bcms[] = { +static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { &bcm_ce0, }; @@ -1574,7 +1574,7 @@ static const struct qcom_icc_desc sm8450_aggre2_noc = { .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), }; -static struct qcom_icc_bcm *clk_virt_bcms[] = { +static struct qcom_icc_bcm * const clk_virt_bcms[] = { &bcm_qup0, &bcm_qup1, &bcm_qup2, @@ -1596,7 +1596,7 @@ static const struct qcom_icc_desc sm8450_clk_virt = { .num_bcms = ARRAY_SIZE(clk_virt_bcms), }; -static struct qcom_icc_bcm *config_noc_bcms[] = { +static struct qcom_icc_bcm * const config_noc_bcms[] = { &bcm_cn0, }; @@ -1665,7 +1665,7 @@ static const struct qcom_icc_desc sm8450_config_noc = { .num_bcms = ARRAY_SIZE(config_noc_bcms), }; -static struct qcom_icc_bcm *gem_noc_bcms[] = { +static struct qcom_icc_bcm * const gem_noc_bcms[] = { &bcm_sh0, &bcm_sh1, &bcm_sh0_disp, @@ -1700,7 +1700,7 @@ static const struct qcom_icc_desc sm8450_gem_noc = { .num_bcms = ARRAY_SIZE(gem_noc_bcms), }; -static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = { +static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { }; static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { @@ -1722,7 +1722,7 @@ static const struct qcom_icc_desc sm8450_lpass_ag_noc = { .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), }; -static struct qcom_icc_bcm *mc_virt_bcms[] = { +static struct qcom_icc_bcm * const mc_virt_bcms[] = { &bcm_acv, &bcm_mc0, &bcm_acv_disp, @@ -1743,7 +1743,7 @@ static const struct qcom_icc_desc sm8450_mc_virt = { .num_bcms = ARRAY_SIZE(mc_virt_bcms), }; -static struct qcom_icc_bcm *mmss_noc_bcms[] = { +static struct qcom_icc_bcm * const mmss_noc_bcms[] = { &bcm_mm0, &bcm_mm1, &bcm_mm0_disp, @@ -1778,7 +1778,7 @@ static const struct qcom_icc_desc sm8450_mmss_noc = { .num_bcms = ARRAY_SIZE(mmss_noc_bcms), }; -static struct qcom_icc_bcm *nsp_noc_bcms[] = { +static struct qcom_icc_bcm * const nsp_noc_bcms[] = { &bcm_co0, }; @@ -1796,7 +1796,7 @@ static const struct qcom_icc_desc sm8450_nsp_noc = { .num_bcms = ARRAY_SIZE(nsp_noc_bcms), }; -static struct qcom_icc_bcm *pcie_anoc_bcms[] = { +static struct qcom_icc_bcm * const pcie_anoc_bcms[] = { &bcm_sn7, }; @@ -1815,7 +1815,7 @@ static const struct qcom_icc_desc sm8450_pcie_anoc = { .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), }; -static struct qcom_icc_bcm *system_noc_bcms[] = { +static struct qcom_icc_bcm * const system_noc_bcms[] = { &bcm_sn0, &bcm_sn1, &bcm_sn2,