From patchwork Thu Apr 21 10:20:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 564546 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62BD7C43217 for ; Thu, 21 Apr 2022 10:23:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1388329AbiDUK01 (ORCPT ); Thu, 21 Apr 2022 06:26:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51006 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1388293AbiDUK0Y (ORCPT ); Thu, 21 Apr 2022 06:26:24 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9A3822284; Thu, 21 Apr 2022 03:23:34 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 6930061A22; Thu, 21 Apr 2022 10:23:34 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AE0D7C385AA; Thu, 21 Apr 2022 10:23:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1650536613; bh=T0g7oH9T8F9azL6LKlPOPO75OxevOofYsR6P8ncZbYk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Sjhfo6VNTDpkzhkc2Up1PFcDw/DHSTsVHcJ4Ll3Z0zChECKHpksxcfRah1WmZ2Cv3 wBVTslcHLypYztFiNr/1xnoGX62XZqBgSn5eKYYoRFvPmyC6vRR49UP0ftyJJbsOPg UubAggDvpqrckUnFtkcbuZEnf9kV0wpzauNvZVd+5sd5drZdqgdbEE5Taks3MCTP5D d/CXS55dTSWACW73Jgm9w2567n9igwW90RtIQr7aPo3JVSZJe2ClDhRg8W6VgZ+VFZ YYZ/4p0KY8vbwVvWoSWTbRed2fj6+hGQVqUX5s+1OJMQDJT8QufOPf6Buzl8SZ5xSv AiNa6gq5W4j6A== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1nhTyB-0004Xe-9v; Thu, 21 Apr 2022 12:23:27 +0200 From: Johan Hovold To: Andy Gross , Bjorn Andersson , Lorenzo Pieralisi , Kishon Vijay Abraham I , Vinod Koul , "Stephen Boyd" Cc: Rob Herring , Krzysztof Kozlowski , Stanimir Varbanov , =?utf-8?q?Krzysztof_Wilczy=C5=84s?= =?utf-8?q?ki?= , Bjorn Helgaas , Dmitry Baryshkov , Prasad Malisetty , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, Johan Hovold Subject: [PATCH RFC 1/5] phy: qcom-qmp: add support for pipe clock muxing Date: Thu, 21 Apr 2022 12:20:37 +0200 Message-Id: <20220421102041.17345-2-johan+linaro@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421102041.17345-1-johan+linaro@kernel.org> References: <20220421102041.17345-1-johan+linaro@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some QMP PHYs need to remux to their pipe clock input to the pipe clock output generated by the PHY before powering on the PHY and restore the default source during power down. Add support for an optional pipe clock mux which will be reparented to the generated pipe clock before powering on the PHY and restored to the default reference source on power off. Signed-off-by: Johan Hovold --- drivers/phy/qualcomm/phy-qcom-qmp.c | 71 ++++++++++++++++++++++++++--- 1 file changed, 65 insertions(+), 6 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 7d2d1ab061f7..bc6db9670291 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -3292,6 +3292,8 @@ struct qmp_phy_combo_cfg { * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) * @pcs_misc: iomapped memory space for lane's pcs_misc * @pipe_clk: pipe clock + * @pipemux_clk: pipe clock source mux + * @piperef_clk: pipe clock default reference source * @index: lane index * @qmp: QMP phy to which this lane belongs * @lane_rst: lane's reset controller @@ -3311,6 +3313,8 @@ struct qmp_phy { void __iomem *rx2; void __iomem *pcs_misc; struct clk *pipe_clk; + struct clk *pipemux_clk; + struct clk *piperef_clk; unsigned int index; struct qcom_qmp *qmp; struct reset_control *lane_rst; @@ -3346,6 +3350,7 @@ struct qcom_qmp { void __iomem *dp_com; struct clk_bulk_data *clks; + struct clk *pipe_clksrc; struct reset_control **resets; struct regulator_bulk_data *vregs; @@ -5355,6 +5360,42 @@ static int qcom_qmp_phy_init(struct phy *phy) return 0; } +static int qcom_qmp_phy_pipe_clk_enable(struct qmp_phy *qphy) +{ + struct qcom_qmp *qmp = qphy->qmp; + int ret; + + ret = clk_set_parent(qphy->pipemux_clk, qmp->pipe_clksrc); + if (ret) + dev_err(qmp->dev, "failed to reparent pipe clock: %d\n", ret); + + + ret = clk_prepare_enable(qphy->pipe_clk); + if (ret) { + dev_err(qmp->dev, "failed to enable pipe clock: %d\n", ret); + goto err_restore_parent; + } + + return 0; + +err_restore_parent: + clk_set_parent(qphy->pipemux_clk, qphy->piperef_clk); + + return ret; +} + +static void qcom_qmp_phy_pipe_clk_disable(struct qmp_phy *qphy) +{ + struct qcom_qmp *qmp = qphy->qmp; + int ret; + + clk_disable_unprepare(qphy->pipe_clk); + + ret = clk_set_parent(qphy->pipemux_clk, qphy->piperef_clk); + if (ret) + dev_err(qmp->dev, "failed to reparent pipe clock: %d\n", ret); +} + static int qcom_qmp_phy_power_on(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); @@ -5379,11 +5420,9 @@ static int qcom_qmp_phy_power_on(struct phy *phy) } } - ret = clk_prepare_enable(qphy->pipe_clk); - if (ret) { - dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); + ret = qcom_qmp_phy_pipe_clk_enable(qphy); + if (ret) goto err_reset_lane; - } /* Tx, Rx, and PCS configurations */ qcom_qmp_phy_configure_lane(tx, cfg->regs, @@ -5478,7 +5517,7 @@ static int qcom_qmp_phy_power_on(struct phy *phy) return 0; err_disable_pipe_clk: - clk_disable_unprepare(qphy->pipe_clk); + qcom_qmp_phy_pipe_clk_disable(qphy); err_reset_lane: if (cfg->has_lane_rst) reset_control_assert(qphy->lane_rst); @@ -5491,7 +5530,7 @@ static int qcom_qmp_phy_power_off(struct phy *phy) struct qmp_phy *qphy = phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg = qphy->cfg; - clk_disable_unprepare(qphy->pipe_clk); + qcom_qmp_phy_pipe_clk_disable(qphy); if (cfg->type == PHY_TYPE_DP) { /* Assert DP PHY power down */ @@ -5777,6 +5816,8 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) if (ret) return ret; + qmp->pipe_clksrc = fixed->hw.clk; + ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); if (ret) return ret; @@ -6091,6 +6132,24 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, qphy->pipe_clk = NULL; } + /* Get optional pipe clock mux and default reference source clock. */ + qphy->pipemux_clk = of_clk_get_by_name(np, "mux"); + if (IS_ERR(qphy->pipemux_clk)) { + ret = PTR_ERR(qphy->pipemux_clk); + if (ret == -EPROBE_DEFER) + return ret; + + qphy->pipemux_clk = NULL; + } else { + qphy->piperef_clk = of_clk_get_by_name(np, "ref"); + if (IS_ERR(qphy->piperef_clk)) { + ret = PTR_ERR(qphy->piperef_clk); + return dev_err_probe(dev, ret, + "failed to get lane%d piperef_clk\n", + id); + } + } + /* Get lane reset, if any */ if (cfg->has_lane_rst) { snprintf(prop_name, sizeof(prop_name), "lane%d", id); From patchwork Thu Apr 21 10:20:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 564545 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72F5CC433F5 for ; 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s=k20201202; t=1650536613; bh=mHz5AgVnSrTaGOXojcB9hqQaqAnullRbzrWC0LxA+34=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Kf4bONYIYSzcRnbOsffSWTKg0KeT6uacWY5b7ltg3atcuxm8YaZbk3QeXhQMtW3QJ VzAGHV1kO03iO43dr9ete/OH+Dbq9rl54qLBZQ5Tbx5uTJWWcCiZaSz7KNTzrCq0Jm sFec/tTzfFT3zYvOWqaV4TgZDfPPYUgrAF5FanPFBY4+CFJpedG3GpDtRx/HlkncWw +Nex6h1hUgDbKNgexjx8VJjtBHLdjcdAWf1tBAD6jMPRLMpcT4ZXyPnnv0s9g/59M+ W115TExH4IGGSKrQAQdARgPSwCYKDKfJuz5HTt0dTFBcNQKlU5e4JCjpex28Sl8mAW onPCbXwZCe28g== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1nhTyB-0004Xg-D9; Thu, 21 Apr 2022 12:23:27 +0200 From: Johan Hovold To: Andy Gross , Bjorn Andersson , Lorenzo Pieralisi , Kishon Vijay Abraham I , Vinod Koul , "Stephen Boyd" Cc: Rob Herring , Krzysztof Kozlowski , Stanimir Varbanov , =?utf-8?q?Krzysztof_Wilczy=C5=84s?= =?utf-8?q?ki?= , Bjorn Helgaas , Dmitry Baryshkov , Prasad Malisetty , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, Johan Hovold Subject: [PATCH RFC 2/5] arm64: dts: qcom: sc7280: move pipe mux handling to phy Date: Thu, 21 Apr 2022 12:20:38 +0200 Message-Id: <20220421102041.17345-3-johan+linaro@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421102041.17345-1-johan+linaro@kernel.org> References: <20220421102041.17345-1-johan+linaro@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The QMP PHY pipe clock remuxing is part of the PHY, which is both the producer and the consumer of the pipe clock. Update the PCIe controller and PHY node to reflect the new binding. Signed-off-by: Johan Hovold --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index c07765df9303..b3a9630262dc 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1837,11 +1837,7 @@ pcie1: pci@1c08000 { <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, - <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, - <&pcie1_lane 0>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_PCIE_1_AUX_CLK>, + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_AXI_CLK>, @@ -1849,11 +1845,7 @@ pcie1: pci@1c08000 { <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, <&gcc GCC_DDRSS_PCIE_SF_CLK>; - clock-names = "pipe", - "pipe_mux", - "phy_pipe", - "ref", - "aux", + clock-names = "aux", "cfg", "bus_master", "bus_slave", @@ -1910,8 +1902,10 @@ pcie1_lane: lanes@1c0e200 { <0 0x01c0e600 0 0x170>, <0 0x01c0e800 0 0x200>, <0 0x01c0ee00 0 0xf4>; - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; - clock-names = "pipe0"; + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "pipe0", "mux", "ref"; #phy-cells = <0>; #clock-cells = <1>; From patchwork Thu Apr 21 10:20:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 564547 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D04E8C433FE for ; Thu, 21 Apr 2022 10:23:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1388303AbiDUK0Z (ORCPT ); Thu, 21 Apr 2022 06:26:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50996 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1388282AbiDUK0Y (ORCPT ); Thu, 21 Apr 2022 06:26:24 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D43CA15710; Thu, 21 Apr 2022 03:23:34 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 5ADC661A14; Thu, 21 Apr 2022 10:23:34 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A53C7C385A1; Thu, 21 Apr 2022 10:23:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1650536613; bh=7GtaheXDo0Wz45oqsEBVEP7Qvw6FlqTw7YTi2BpvukQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DgodGQmB62XI0kG3Z+hJsbIUpXQxppBmzHlQezGqeNDA39jYkelcUjFxqSr3WKd6K 75pVa95DjrWIdQ8DRHN5P3LJ0C37uKFnZ1rG4NNeOojx2dzc1K0nPbA/CYrN3OnktH Bz2q84RGOwD8fghdDfKM9mlCh+SggDJol+JRUa2sRcJlKWQsvcbE7zkgtPvc5pvyH6 PEUO+2KDSvaADGy6i/5GqQZp1P51Zs+xoNG5O+aF2Qxn+gnMQ4niLZAZzOYbXgph76 0Cc2S8VeMJnQak7q6/LhXCWcSERc9V3If/o9firUGi8Rmk64efPs3GCANR6/6sl/MJ kovzwkFcKpI7w== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1nhTyB-0004Xi-Fj; Thu, 21 Apr 2022 12:23:27 +0200 From: Johan Hovold To: Andy Gross , Bjorn Andersson , Lorenzo Pieralisi , Kishon Vijay Abraham I , Vinod Koul , "Stephen Boyd" Cc: Rob Herring , Krzysztof Kozlowski , Stanimir Varbanov , =?utf-8?q?Krzysztof_Wilczy=C5=84s?= =?utf-8?q?ki?= , Bjorn Helgaas , Dmitry Baryshkov , Prasad Malisetty , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, Johan Hovold Subject: [PATCH RFC 3/5] PCI: qcom: Remove unnecessary pipe_clk handling Date: Thu, 21 Apr 2022 12:20:39 +0200 Message-Id: <20220421102041.17345-4-johan+linaro@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421102041.17345-1-johan+linaro@kernel.org> References: <20220421102041.17345-1-johan+linaro@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Dmitry Baryshkov QMP PHY driver already does clk_prepare_enable()/_disable() pipe_clk. Remove extra calls to enable/disable this clock from the PCIe driver, so that the PHY driver can manage the clock on its own. Reviewed-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov Signed-off-by: Johan Hovold --- drivers/pci/controller/dwc/pcie-qcom.c | 44 ++------------------------ 1 file changed, 3 insertions(+), 41 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 774d486bf2f7..6e6e40fbfc13 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -128,7 +128,6 @@ struct qcom_pcie_resources_2_3_2 { struct clk *master_clk; struct clk *slave_clk; struct clk *cfg_clk; - struct clk *pipe_clk; struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY]; }; @@ -165,7 +164,6 @@ struct qcom_pcie_resources_2_7_0 { int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; - struct clk *pipe_clk; struct clk *pipe_clk_src; struct clk *phy_pipe_clk; struct clk *ref_clk_src; @@ -597,8 +595,7 @@ static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) if (IS_ERR(res->slave_clk)) return PTR_ERR(res->slave_clk); - res->pipe_clk = devm_clk_get(dev, "pipe"); - return PTR_ERR_OR_ZERO(res->pipe_clk); + return 0; } static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) @@ -613,13 +610,6 @@ static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } -static void qcom_pcie_post_deinit_2_3_2(struct qcom_pcie *pcie) -{ - struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; - - clk_disable_unprepare(res->pipe_clk); -} - static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; @@ -694,22 +684,6 @@ static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) return ret; } -static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) -{ - struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; - struct dw_pcie *pci = pcie->pci; - struct device *dev = pci->dev; - int ret; - - ret = clk_prepare_enable(res->pipe_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable pipe clock\n"); - return ret; - } - - return 0; -} - static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; @@ -1198,8 +1172,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) return PTR_ERR(res->ref_clk_src); } - res->pipe_clk = devm_clk_get(dev, "pipe"); - return PTR_ERR_OR_ZERO(res->pipe_clk); + return 0; } static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) @@ -1292,14 +1265,7 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) if (pcie->cfg->pipe_clk_need_muxing) clk_set_parent(res->pipe_clk_src, res->phy_pipe_clk); - return clk_prepare_enable(res->pipe_clk); -} - -static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie) -{ - struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; - - clk_disable_unprepare(res->pipe_clk); + return 0; } static int qcom_pcie_link_up(struct dw_pcie *pci) @@ -1449,9 +1415,7 @@ static const struct qcom_pcie_ops ops_1_0_0 = { static const struct qcom_pcie_ops ops_2_3_2 = { .get_resources = qcom_pcie_get_resources_2_3_2, .init = qcom_pcie_init_2_3_2, - .post_init = qcom_pcie_post_init_2_3_2, .deinit = qcom_pcie_deinit_2_3_2, - .post_deinit = qcom_pcie_post_deinit_2_3_2, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, }; @@ -1478,7 +1442,6 @@ static const struct qcom_pcie_ops ops_2_7_0 = { .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, .post_init = qcom_pcie_post_init_2_7_0, - .post_deinit = qcom_pcie_post_deinit_2_7_0, }; /* Qcom IP rev.: 1.9.0 */ @@ -1488,7 +1451,6 @@ static const struct qcom_pcie_ops ops_1_9_0 = { .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, .post_init = qcom_pcie_post_init_2_7_0, - .post_deinit = qcom_pcie_post_deinit_2_7_0, .config_sid = qcom_pcie_config_sid_sm8250, };