From patchwork Fri Apr 22 16:51:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564842 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp658076map; Fri, 22 Apr 2022 09:58:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzzfvtGKnOJxQJW5kIJ+4QEn60vcSOa3r6UMiJkJ21WS0X3IQBdTSxXhhugLFBCRgvRG0tu X-Received: by 2002:a05:620a:219d:b0:69e:8ab0:dd22 with SMTP id g29-20020a05620a219d00b0069e8ab0dd22mr3349243qka.33.1650646688148; Fri, 22 Apr 2022 09:58:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650646688; cv=none; d=google.com; s=arc-20160816; b=IkSuC9H8MTMbDfwOnFMHYpU+zBWJ4RuyWCBthN/8zwzVLqlBSMAbHzLThm2VO1deSZ hxcCDa4LwKNIo2RT61M0uX7ONuwb7lTMlutK87aMWk1qGMjPj8iT76ehKTmm9+Ky5fxt +mrAgReTAwwoHXaq8WYhiP+XqSM/NDAyHVEe3QcgQ8jeVcjZeY+Bc/VkgU1XhfKBrwDR XnwBLp7misnd2qxJUPUKbvaNhVB+1Eo2VpOrHt+SRPaRxuE7guJuzib9D/G2XIdJALzt xdxcCNJCFe+K0y+U86JFrifg8AfAe3R90+k0UCOkegM7nA+ESX3dtDqjNk5k664UOX/1 M4jQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=meOXfrn2PD5m0Qh1cBNLkWBSrBP+MRPsiz/DUB3aYZo=; b=Ut33l7sUJM5qcQ+r8A4O5qLVttspkyyafi6CFPpyrF5dlGGSXGXmX+ecT5YdGuLMzo mgKYjFt/cw4kXvpcCyifgW0Ci00uVSXFAFyLLe9n5zziILiBxtr2Z8WiIGDpmCuSCJ1S 3Jsil3n23C432DPDiWsdXNxT1TDTZ10mBbyWy4HzREHGQoiwbtxbGU9b/NSxciqV6dFw ahlJkx0+8gv5oTWqdsHyuSUZG32bpyPbk+FBRGxbAzYDihyQAFuSoZuQTlWJr0hRZobO rL2TPTdq4DHt3SDG3+u+XgYJ3mDsI7mHhN8BkSPIpvysfEj3PXi4Wla9VjjGA1DSZfiS spjg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tbqVPiUI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s8-20020a05620a0bc800b0067e4be23aa3si2543894qki.744.2022.04.22.09.58.08 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Apr 2022 09:58:08 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tbqVPiUI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:58074 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhwbf-0007fy-Nv for patch@linaro.org; Fri, 22 Apr 2022 12:58:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48404) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhwWW-0008Sl-Pg for qemu-devel@nongnu.org; Fri, 22 Apr 2022 12:52:48 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]:40787) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nhwWV-0007Cw-5w for qemu-devel@nongnu.org; Fri, 22 Apr 2022 12:52:48 -0400 Received: by mail-pl1-x62c.google.com with SMTP id k4so544507plk.7 for ; Fri, 22 Apr 2022 09:52:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=meOXfrn2PD5m0Qh1cBNLkWBSrBP+MRPsiz/DUB3aYZo=; b=tbqVPiUImFnthQK0yo86Pwsk9/imCz2d90C1cP3trX1+76OjpzqOerbEx5INy91u3p ywqaQzbIG2d+dXdLWY6ZAKitIAvFrB/rUInmYG+Xr7b1PjYJPw+MvTLKMuMXtlN9Rk5m 3+Ya7e3bGnTRiO2FlLi7/diAZYklHsUhLigu6XnKEiWIWkni88SJxlqeyykrcvAhkpqu /PoBv9RC7D9k69pS9AtcR20/7HRAlumI4OyGAw72Jg19ZoK3vpTgMdfcvLNvHmhkFKvc Fp+iz7CUumVIv0w2B7opNMf8h7eZAev8lxZuYJDzAS3eCPKOfSPuQqLuVcjRHl5Xq4JU 9q6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=meOXfrn2PD5m0Qh1cBNLkWBSrBP+MRPsiz/DUB3aYZo=; b=5iJDQAAxiL1Prtlwsd1HFMQyif85wzjm9H2xHyAsM3dmYAnI3CFJK8aAxhAp/u4VaX pC9A7iK0Ni0pmQBLRElOSObAoNqNzOUM8ZictjjwpN+WW2ebxt/5uJlwB0U1OjzhW8oP mQqnIc7sI3c50Seu1x4plj8DJYPQHZLT2G1E5GjB8+mw8eVeNrFgkdXwCM8j9feP2Wsn K0VXH0PCH5soqyv+mBjGURFNRf4qsIozCBXIafLN41FVeS8ukmHAyTSacmuMAG3w4FKa h1z+lYKB0gwVoo6Z/NYP4pAoDDZfWdzjVun+OVjG9LAqvBMKs1zbYcDvYye1eXyEx/Mi ytXg== X-Gm-Message-State: AOAM533sIGacSIq4YuLFn3kgDmkA5Elonl4KO+svFitvfw5wzNpLbUXD +YHBY2bzeBHwjN7G9Ix+cyD0g4Oq8waUtxfX X-Received: by 2002:a17:90b:3b8f:b0:1d2:86e1:6e4d with SMTP id pc15-20020a17090b3b8f00b001d286e16e4dmr16965403pjb.186.1650646364241; Fri, 22 Apr 2022 09:52:44 -0700 (PDT) Received: from stoup.. ([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.52.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:52:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 01/68] linux-user/nios2: Hoist pc advance to the top of EXCP_TRAP Date: Fri, 22 Apr 2022 09:51:31 -0700 Message-Id: <20220422165238.1971496-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Note that this advance *should* be done by the translator, as that's the pc value that's supposed to be generated by hardware. However, that's a much larger change across sysemu as well. In the meantime, produce the correct PC for any signals raised by the trap instruction. Note the special case of TRAP_BRKPT, which itself is special cased within the kernel. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-2-richard.henderson@linaro.org> --- linux-user/nios2/cpu_loop.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index 1e93ef34e6..2e9296750d 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -40,6 +40,12 @@ void cpu_loop(CPUNios2State *env) break; case EXCP_TRAP: + /* + * TODO: This advance should be done in the translator, as + * hardware produces an advanced pc as part of all exceptions. + */ + env->regs[R_PC] += 4; + switch (env->error_code) { case 0: qemu_log_mask(CPU_LOG_INT, "\nSyscall\n"); @@ -56,7 +62,6 @@ void cpu_loop(CPUNios2State *env) env->regs[2] = abs(ret); /* Return value is 0..4096 */ env->regs[7] = ret > 0xfffff000u; - env->regs[R_PC] += 4; break; case 1: @@ -69,6 +74,8 @@ void cpu_loop(CPUNios2State *env) break; case 31: qemu_log_mask(CPU_LOG_INT, "\nTrap 31\n"); + /* Match kernel's breakpoint_c(). */ + env->regs[R_PC] -= 4; force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->regs[R_PC]); break; default: @@ -99,7 +106,6 @@ void cpu_loop(CPUNios2State *env) o = env->regs[5]; n = env->regs[6]; env->regs[2] = qatomic_cmpxchg(h, o, n) - o; - env->regs[R_PC] += 4; } break; } From patchwork Fri Apr 22 16:51:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564836 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp655273map; Fri, 22 Apr 2022 09:54:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx6/fH/0RpRThEdYL1WG1wzU654XwHTh0j4PVZEJLq0xmzDFWEWB2wBSxa6t5j8hKzNMetm X-Received: by 2002:a05:6902:726:b0:644:e5cc:3353 with SMTP id l6-20020a056902072600b00644e5cc3353mr5193840ybt.219.1650646455245; Fri, 22 Apr 2022 09:54:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650646455; cv=none; d=google.com; s=arc-20160816; b=lF6UL8SYdU+qtNlvUIqsAFDBfGtceDi98qYhvSyURS8NwGEVsNINC09BfwMzWbDKb/ Pi/wH7vJvLvC13W3wup4IcMK42SX6GIrs18n+4QIGqKVJzvYfq7kbW3C1scJKA4vGr2H uY+ucEU+ldewu7Cp2u3G6WdbZRD06ODCftBcDlEkeXouFtoJf1gl+iws66zETt0WddNB Iuyjci9fNBeWOy7kUWgs8ULItQZG83wgETpx0r9UynSmAGTk8hUaI88vLjHvhfGPs4eP g4H51qfD0BNc8IXcwosgKt5PyzP9DK2Q08VTpESTpPVlNKvO7IyCDCSfSkLS+U3bEyCy d29Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Kt2BBU1GUjUG3/EJVuAysOFujg46su8Ylz5CGCHbv4o=; b=SI52Sy9Z0Ukq1JkYCj91EdhVhpcGJAI+YpyxXrXvpoAP9H+u60p5uyu/kxfcgrbrpr k2eArzGM1qzZEjMrcXzDsgcn1Mz7Kf8QtqwQ4SZX5D5bAtCTX1paGTOSUpaQryK4JXMl J5ZiJExcTDOkRpB5cCRoipCm8tBLTiebtHGeexO0oWQoIAWLND/lW1YuYB+M6ZcY3d8n WRkpm70FUg0pGqtEsmGdCryH37sk004B7YLJgkGXnDPxr4rKX9oA/Biz09rbXRM8/VjY BdWFYIJyO4B9QaYlZ8j1XIKNcATKUUDqgz6xP9Nq6YwDOuMPrSteQRxwIl2ON8gsmWwL 6oEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jStOSJ2b; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.52.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:52:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 02/68] linux-user/nios2: Fix clone child return Date: Fri, 22 Apr 2022 09:51:32 -0700 Message-Id: <20220422165238.1971496-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The child side of clone needs to set the secondary syscall return value, r7, to indicate syscall success. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-3-richard.henderson@linaro.org> --- linux-user/nios2/target_cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/linux-user/nios2/target_cpu.h b/linux-user/nios2/target_cpu.h index 2d2008f002..830b4c0741 100644 --- a/linux-user/nios2/target_cpu.h +++ b/linux-user/nios2/target_cpu.h @@ -27,6 +27,7 @@ static inline void cpu_clone_regs_child(CPUNios2State *env, target_ulong newsp, env->regs[R_SP] = newsp; } env->regs[R_RET0] = 0; + env->regs[7] = 0; } static inline void cpu_clone_regs_parent(CPUNios2State *env, unsigned flags) From patchwork Fri Apr 22 16:51:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564837 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp655437map; Fri, 22 Apr 2022 09:54:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw68wKLRFETJNSdl8hiUQXvupvOqcw4yBAG5l05i1hbgAkusooap+Xju4GkxajLUel/0v23 X-Received: by 2002:a81:af0a:0:b0:2ef:380d:6ea2 with SMTP id n10-20020a81af0a000000b002ef380d6ea2mr5756527ywh.147.1650646468929; Fri, 22 Apr 2022 09:54:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650646468; cv=none; d=google.com; s=arc-20160816; b=cnaI0uvM2FCh5lCao1YxdYcmTyANmSZHGE7+Y8pYURzAAiMvNVul5+3SUSqkNkU3gi k/pF0d+ZptWDNsnK3FhHy0eLfZi/8P9VyHKMcHZGCo+AK92rGSjpK6aGdrn3U2PYIZxG QVi6192N2IOlvxpAQCzrIqNsk4rpNOEzgiCJ9sLbvE37LJUNC9F1uRWeR348aOc2ntnQ wrbsfusTQk6xtM3HdO3mVLxEKKtEfdbcCOWN4i6HQOPwRBTpeIgss4jTec61FPN84jAH yy8LnthQf7HAUjeIguNIAbQYUe2ffGhx5e9sXGfRBXydFzsruOUvIXRwn3x8v0AOfeTK hEWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Zx3qhK8H+v+NAZcjuR7FBLrFsz8zqhmn66xWRsawstk=; b=lcDS5azqNufubRzmkLtNsN5waXpFs8rjN+MX2Q87DgF8L8KC9o7J1lcUB9OvgX+xkJ FGFMl5VKqnwE1MxTWlIyzLx8wmWFzytndb8QrCuBLCRFSIQxbR/bfJCw1nVXNJm5+qhE gd5aIG7g+1hwZR6B9KMFH4QUo2ycJM7IGRD2VLn4o8GVinQBWLsklepGBKuz9ixL0VtV 70PzxOe6MbsWqKMFuGuy7XvvgtXWOUi1Ah4GaNktO0VjC6ylnGS71AX07kVFrN9NlSRX zyG2tF3uL3wO9uqpjm4A01MDg9zzwahRnH6IhLr2IWHa0lVxf3zEX1Oy2LOZ6nDwOpzB /3Qg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Pfx6xKA5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.52.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:52:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 03/68] linux-user/nios2: Drop syscall 0 "workaround" Date: Fri, 22 Apr 2022 09:51:33 -0700 Message-Id: <20220422165238.1971496-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Syscall 0 is __NR_io_setup for this target; there is nothing to work around. Reviewed-by: Peter Maydell Fixes: a0a839b65b6 ("nios2: Add usermode binaries emulation") Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-4-richard.henderson@linaro.org> --- linux-user/nios2/cpu_loop.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index 2e9296750d..91737c568f 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -55,10 +55,6 @@ void cpu_loop(CPUNios2State *env) env->regs[7], env->regs[8], env->regs[9], 0, 0); - if (env->regs[2] == 0) { /* FIXME: syscall 0 workaround */ - ret = 0; - } - env->regs[2] = abs(ret); /* Return value is 0..4096 */ env->regs[7] = ret > 0xfffff000u; From patchwork Fri Apr 22 16:51:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564840 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp657582map; Fri, 22 Apr 2022 09:57:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxKZRDVFGAPOBJi1vAbgDuogNUG5Bc0dZslKoioTbPCI54K0ybeNZLw7RmG/pwmep7ajbeA X-Received: by 2002:a05:6214:d69:b0:446:5206:85e1 with SMTP id 9-20020a0562140d6900b00446520685e1mr4107333qvs.73.1650646647934; Fri, 22 Apr 2022 09:57:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650646647; cv=none; d=google.com; s=arc-20160816; b=0esz+rJjqbaL7wrlgFaTMH6OQkyfo+RKmHdH3RLUiJfHbz6dv2IMV6VOurQyIkRK8e TvrGWV7CGia7hYJMpctj58fI2YsekGL4ifSbREstE3oGQ4arA4pWyv6PZ/nZg+ucWczw 8pGrw/rzbrgTM0ZTlgR55jI88LFa2G+I9y40PxAES9ILm0t2wPEpDTUp7AfqwpJZ27Pt JtzpWhdjiOZf1hHWJS98tE1/uRXB59ivoRxiVwE+g+xEUWqGbIaeXvClDjMk0toKpSfy QKzNXkpos1zncU+8WIeYj6U8aVHRBaiWmBVy9MKLb+7HMgBY5AELJMSKObutiGFbVjXm YFpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Cz85jXXNTXB185MIdFgmydKGclnlgZjRARJ6+y2fc4Y=; b=mq/v7nKEU1T0iQkqEM6fGMZUBATE9sR5beB4SThotZ6FLnOG06XyTJIA0dTjOQJVUe JyX1VeMAVHaXxQbDpRI99qXlRakDRKowe8wOuWusT4iY3UabbywNW+4NdpS+FQrLcJuj xQYYUGWRiOQlKMicP8Y4YFfSepVoF7ZmByYi0l/jJkVrol1LJomccMjHcekBNyypCyy7 hvKyx/39N300w3nZtdIX6oyR0qNIdghHPgrDw44gFuQ9dGOA0UjQ22LAhjGV6MtCaYRN v4kKYgqPnBl49pwEjRA4+mzsIsRgU0//6ziXGGRy6SjGM5Kq6e1zbi0iAiyXVYQrXf6B yYew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=X+2ySwRt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.52.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:52:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 04/68] linux-user/nios2: Adjust error return Date: Fri, 22 Apr 2022 09:51:34 -0700 Message-Id: <20220422165238.1971496-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Follow the kernel assembly, which considers all negative return values to be errors. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-5-richard.henderson@linaro.org> --- linux-user/nios2/cpu_loop.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index 91737c568f..63afba5862 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -55,9 +55,14 @@ void cpu_loop(CPUNios2State *env) env->regs[7], env->regs[8], env->regs[9], 0, 0); + /* + * See the code after translate_rc_and_ret: all negative + * values are errors (aided by userspace restricted to 2G), + * errno is returned positive in r2, and error indication + * is a boolean in r7. + */ env->regs[2] = abs(ret); - /* Return value is 0..4096 */ - env->regs[7] = ret > 0xfffff000u; + env->regs[7] = ret < 0; break; case 1: From patchwork Fri Apr 22 16:51:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564846 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp661824map; Fri, 22 Apr 2022 10:02:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwmEzJrs00fi5+AKYH4QlC4lYWw2vtab5ZbmLHBrAxxLTMeKRDvjCqWcOVR2e0wgVa76COY X-Received: by 2002:a05:6214:c21:b0:443:a2d2:a685 with SMTP id a1-20020a0562140c2100b00443a2d2a685mr4330472qvd.52.1650646954170; Fri, 22 Apr 2022 10:02:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650646954; cv=none; d=google.com; s=arc-20160816; b=lBtZbIbd+6k/K/23QYgRrB4i2g/4MhYiwGWQkcVuQcL+/oUYZ9x3QNDy7K5aBj8rYw m9MBMSq8zv5ZBj7DSOl4yemxXj2ak5qk0UUyoH9Cs5yx74+aCzLtWt9BSCcFLI5RIAwl mw9itrpDBG9+NvWpzbAsf8mx+vtjeMPUh/bte1BC9cnFkUf9bpVUOYna84taBNt6uWrC L3lMfI0d9DLqpn9wzkv067XgYdkNxB1pi+O8da2Ia2p17+qsCL/K3XlcDXj6WhVJ211o Zg38h5TxA8+Ih6VETOaU/8KtjQD6wcb+aibXEzRSjIkg+1/bDppJ06q3SMIY0Sy7ZyaO 64Og== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=BaXzjQ4uHQf8aegyrwpNgla1ibfyULSXvI/9Vr/sAxc=; b=FaT2u/cDPikB43ldXZ2dCca1oPZ181UePzgGNPnLshl3pF48N7RCy5en6CyMD4yXu4 yl7qlAOHruy3GeBjYfBALwl9nZ803XcS81/U15zUNviKLcjQlO2r2MrG+zn13wrWcW7+ gSrpiFDRCOZodLnO2Egh2MzftCZIUcAnvKhFhTfDfz3/tM+o/0e+NqslXsvbhs6TNJ/y mSekxYGuKzIUaSe+gTUsyS+XVX1Jq2mN6TT9Hs0/xVrgkK1kf270BWXgLVDyngHnNZEU lF3R+DP9tXxaCfLyHukcym2tavfH9heH0hhn+q7XKkn3JQ3Lc6RqxXkOefZZNhtUXn+M DlrQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uzvq1Mmx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.52.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:52:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 05/68] linux-user/nios2: Handle special qemu syscall return values Date: Fri, 22 Apr 2022 09:51:35 -0700 Message-Id: <20220422165238.1971496-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Honor QEMU_ESIGRETURN and QEMU_ERESTARTSYS. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-6-richard.henderson@linaro.org> --- linux-user/nios2/cpu_loop.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index 63afba5862..2963fc62b4 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -55,6 +55,14 @@ void cpu_loop(CPUNios2State *env) env->regs[7], env->regs[8], env->regs[9], 0, 0); + if (ret == -QEMU_ESIGRETURN) { + /* rt_sigreturn has set all state. */ + break; + } + if (ret == -QEMU_ERESTARTSYS) { + env->regs[R_PC] -= 4; + break; + } /* * See the code after translate_rc_and_ret: all negative * values are errors (aided by userspace restricted to 2G), From patchwork Fri Apr 22 16:51:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564839 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp657558map; Fri, 22 Apr 2022 09:57:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwjPNqb8dhBPn2Hr0Rq1+8NzpDUWGdZxSKd/4Rro2lxbRWy6oQqtiROtnh6oeCNHNwnzyRv X-Received: by 2002:a05:620a:1a01:b0:69c:fda:7404 with SMTP id bk1-20020a05620a1a0100b0069c0fda7404mr3331442qkb.522.1650646646795; Fri, 22 Apr 2022 09:57:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650646646; cv=none; d=google.com; s=arc-20160816; b=sstJIzVEnHHWLF49dVslvJ71eY+14oQCBjXRNhZCLufjdF1TvvYuFY++QDWSQBirgg cr4MCKeRitztHIZYiFBH82agHYdYn0GscsFzb1RK5m9h5nMT9TEFsF9JkHCGngdkpFWr jHqkmRfnmy1nDQlgCsZ5pBP+2k2no3RHrQPS4YQJ+wBsbmpeaLk4NEAZiy5qoWTLHr8t xA62aDtPMYoFONcp+cJMTtJRZK+OzmgJv0ZArxyHd87iR2kAj9/yOwyoXcMClgTpByxJ AegVXC4/oA5xrmn55Ziv4M268Zek5B9NBqVBznzsT9RiHqh9ZemeUiVav6lgkNnkaq0o MFcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=nqaKUgAiXbPVN3N+PzEnaP4AnWTK8+75oezV6iZmBrU=; b=SqSJ6l0C1ptOf3mmmAh2tHu1vP9q/IiO03AvQSKVnYxWibOrz15nQBzAtmgAOcYD5Z WG4T98RCWEkTM8oULWOmeWdwdJoWQgFbxrQP8YL6a+vLXPsANiVQ6NcmYCHJ08tKfMNR i8ernXjZS/SBHFY8T5kx7x0SRd+NqjNoCfD6foaBluvqS5j2DppRLGZyZGNAUESuBxmn 7Fh1roC4HTXHQIASci9CccGdEaoxe4gXZNO2+CHbXS14ilbkFyU1nQ06rNwITYDnX1mt h4HlUtT9yBdKanW38jPUdY5amTBfwrgPp6pFz2ZxmEp4w7p3aa8Ea1WdgcZFqqWMKyHX +b/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Dr5UbS8J; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.52.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:52:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 06/68] linux-user/nios2: Remove do_sigreturn Date: Fri, 22 Apr 2022 09:51:36 -0700 Message-Id: <20220422165238.1971496-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There is no sigreturn syscall, only rt_sigreturn. This function is unused. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-7-richard.henderson@linaro.org> --- linux-user/nios2/signal.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/linux-user/nios2/signal.c b/linux-user/nios2/signal.c index 517cd39270..133bc05673 100644 --- a/linux-user/nios2/signal.c +++ b/linux-user/nios2/signal.c @@ -185,13 +185,6 @@ void setup_rt_frame(int sig, struct target_sigaction *ka, unlock_user_struct(frame, frame_addr, 1); } -long do_sigreturn(CPUNios2State *env) -{ - trace_user_do_sigreturn(env, 0); - qemu_log_mask(LOG_UNIMP, "do_sigreturn: not implemented\n"); - return -TARGET_ENOSYS; -} - long do_rt_sigreturn(CPUNios2State *env) { /* Verify, can we follow the stack back */ From patchwork Fri Apr 22 16:51:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564843 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp660330map; Fri, 22 Apr 2022 10:01:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyVFG7e/ZlIU6jal7SkXMAqKdUZavREkIBavMhMySUbZBh5o1EWapeEpx851d3VgN1SI93I X-Received: by 2002:a25:7187:0:b0:643:3426:2500 with SMTP id m129-20020a257187000000b0064334262500mr5206654ybc.588.1650646869521; Fri, 22 Apr 2022 10:01:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650646869; cv=none; d=google.com; s=arc-20160816; b=HMhy7uLbxCJLV6Puyvax4l/VbLbnPihRomZLLx8UvfiM39mQrvVoPNm1p5mZ1Zr2Q3 qgtCfohvpcO2ERCpk7FrtSxwSA9vGLqvIpPapuIHf4hgGYryRdbX4S6pmM90llD6xI7S SIt1m+5hHxrR/LRb3INY36t8bTvWcDf81akPn9941ds19MOH8aRc4g57dX8pvsspXY4d FAihHojmGuokPuKbGrCPheryIvXzcjq1lIiXYhfZKumBApYFp3rQRhQybr0ynG9aivWZ q4s/bQ6uuXattINRvUMPb4Sf07njgCgyDs9CTyNLdC6VjaO2tVkA1SwsRxZZ3IAHLIPb C/Ow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=YXPXvIKScv4pzB3hV1PnW5pSW1FWM2CG8BhQI6zsA0g=; b=ljcu5UsUABGdVZ3cF+eiZQds8WPy4BsSZ2GhvqBlTlRywJ7ZOmqbLmtUmmqgPv/kLi m8YgGnCX0bQX6Ad+/ooSZXDaDIAUhLxXre7va/+uIGczrYbJUn73geVTiuM9L+h61a8l JphHoAcL3sxTUDUuPZa5rQy1AvIa6pRjpE2LIWcAbcrX/poJ8BGkFjbHX5AgbO3AQvqX dvkvuDASHo0by8/YezQSz/Nt4LHMoeVptrOSHFzu0SyEvPa2iQELVgwPpzBR7tiYuIsk QYYXJLPRtyaupkU3QcjJXZEbBqcHPKU1kDR518qZU3MwnwVod8VdvmZOV7bgrehZSmeq Lq7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=olbmeYTd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.52.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:52:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 07/68] linux-user/nios2: Use QEMU_ESIGRETURN from do_rt_sigreturn Date: Fri, 22 Apr 2022 09:51:37 -0700 Message-Id: <20220422165238.1971496-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Drop the kernel-specific "pr2" code structure and use the qemu-specific error return value. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-8-richard.henderson@linaro.org> --- linux-user/nios2/signal.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/linux-user/nios2/signal.c b/linux-user/nios2/signal.c index 133bc05673..9aa525e723 100644 --- a/linux-user/nios2/signal.c +++ b/linux-user/nios2/signal.c @@ -77,8 +77,7 @@ static void rt_setup_ucontext(struct target_ucontext *uc, CPUNios2State *env) __put_user(env->regs[R_SP], &gregs[28]); } -static int rt_restore_ucontext(CPUNios2State *env, struct target_ucontext *uc, - int *pr2) +static int rt_restore_ucontext(CPUNios2State *env, struct target_ucontext *uc) { int temp; unsigned long *gregs = uc->tuc_mcontext.gregs; @@ -128,8 +127,6 @@ static int rt_restore_ucontext(CPUNios2State *env, struct target_ucontext *uc, __get_user(env->regs[R_SP], &gregs[28]); target_restore_altstack(&uc->tuc_stack, env); - - *pr2 = env->regs[2]; return 0; } @@ -191,7 +188,6 @@ long do_rt_sigreturn(CPUNios2State *env) abi_ulong frame_addr = env->regs[R_SP]; struct target_rt_sigframe *frame; sigset_t set; - int rval; if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1)) { goto badframe; @@ -200,15 +196,15 @@ long do_rt_sigreturn(CPUNios2State *env) target_to_host_sigset(&set, &frame->uc.tuc_sigmask); set_sigmask(&set); - if (rt_restore_ucontext(env, &frame->uc, &rval)) { + if (rt_restore_ucontext(env, &frame->uc)) { goto badframe; } unlock_user_struct(frame, frame_addr, 0); - return rval; + return -QEMU_ESIGRETURN; badframe: unlock_user_struct(frame, frame_addr, 0); force_sig(TARGET_SIGSEGV); - return 0; + return -QEMU_ESIGRETURN; } From patchwork Fri Apr 22 16:51:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564838 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp655694map; Fri, 22 Apr 2022 09:54:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzchhQGKuBHRvxNwLNURpWH2dqB19KuI6hTsi+dYOk+Yf7ztdLZ/j3slm0BCuMtCsG5xSw0 X-Received: by 2002:a05:6214:e47:b0:44f:9f5c:a1f3 with SMTP id o7-20020a0562140e4700b0044f9f5ca1f3mr4250623qvc.14.1650646490651; Fri, 22 Apr 2022 09:54:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650646490; cv=none; d=google.com; s=arc-20160816; b=Bvzo0I6BcbpL0+PA8GhNz93VoZ9KMTBjiMs2P73yH3UO+xbOnMVHx7Nmic3OlROVWL KBC6nc4D35uL4l8d05FySwj3Uuz2z82tjiBcVbHR4AEsk4Htow18RIm5H3F/kKkzFw2T ETonOMDN+7Nm6oEBV2/dyjospjw9f9skcWT26kYzLE7TcagOKbf6yPUTgKx7h9WdgZe4 UulqRjXd0cCYtNaGqMMxiqqHL+XmzWa9rDFJURtgfJ2rR75N6169BjYksvZDzG863xge b5S438pIdzo93OCkL7qGMXV0esl3w6Iw0p9+YUIypg022jyZKFPac81Zb60gooVy8xkG Uh/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=CrNW1rK4WiXSB4GD2xVRHyjJx/JGJkz3Qq1JReZmp+g=; b=jxoFB4krTd+8KNNUQ41NuES1lsfGMLJdxd/TbExbebW/dlr49+Q5Iu7I/985r9KoBN YpxVcBTtgNEOoNZ78ecVRqFN6q8FwWxQ3Ck6z4iSv0srbVQgPEfyXVZoPEHZ1h1PGBlY JlSOUmiDKsJRuLKvZYHwuMLYb08jvtp7FXrgSE+J5GW4CV5VlBMyDmQ61mj/ykuKBcaT 3DxE6IcWdmiMBAbENT1mwUEGPJ3gY0m0x467VBkW5jczpvpVzno/lXAO7jwqM1JDATpf HVs+BnijB1XfowvGY1RMd6vJ/Ap+Z+oQwXFB3W/S1wpQXVLERQhcOkW61YZA61YS6ScS Oh5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PoIpBbb5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.52.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:52:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 08/68] tests/tcg/nios2: Re-enable linux-user tests Date: Fri, 22 Apr 2022 09:51:38 -0700 Message-Id: <20220422165238.1971496-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that threads and signals have been fixed, re-enable tests. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-9-richard.henderson@linaro.org> --- tests/tcg/nios2/Makefile.target | 11 ----------- 1 file changed, 11 deletions(-) delete mode 100644 tests/tcg/nios2/Makefile.target diff --git a/tests/tcg/nios2/Makefile.target b/tests/tcg/nios2/Makefile.target deleted file mode 100644 index b38e2352b7..0000000000 --- a/tests/tcg/nios2/Makefile.target +++ /dev/null @@ -1,11 +0,0 @@ -# nios2 specific test tweaks - -# Currently nios2 signal handling is broken -run-signals: signals - $(call skip-test, $<, "BROKEN") -run-plugin-signals-with-%: - $(call skip-test, $<, "BROKEN") -run-linux-test: linux-test - $(call skip-test, $<, "BROKEN") -run-plugin-linux-test-with-%: - $(call skip-test, $<, "BROKEN") From patchwork Fri Apr 22 16:51:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564850 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp665116map; Fri, 22 Apr 2022 10:05:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzlHRCtZQ75LA8c6br+CpDCCGxjpjdHzKPLQDMHv1piOnDA+FLLmNnR9OSdTGcxocHG7CMz X-Received: by 2002:a05:622a:104c:b0:2f2:4e4a:fcf with SMTP id f12-20020a05622a104c00b002f24e4a0fcfmr3959018qte.663.1650647158582; Fri, 22 Apr 2022 10:05:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650647158; cv=none; d=google.com; s=arc-20160816; b=VCC8XH9X8MZSyccUq2qmgB8mYbc3vuZTzIe+a+8MSWQI9zEX5VnxHfUkZCQEAdbMhR xTvy92YI3jN4eeYP0r2mJthR15g1DoZmuXJCfl9T8ehcsojfpn/EDB7NmwChPViGszAL sLXY+16VWnW7FsVPRwDAZZkIeQOeqECnAON32bza90ZA7T4vVUyUY/fWOe+OfzJwpYp0 hN2lfdGhqtEeSdMpSqNGIEVBKtUvKX81/IFT4lwAo+u45bLxtSBRGbMohOo3lytLZLd8 h2fO4dyqc4gW9GGf3Wh/rGXRVxcJwpgjEEowKgibKOViD+OxwdhYSdvU/nIG0cIvjmMY t/Rw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=oKKUu+zNBC8As9SImKOzVlpqPHOufT8qoTmRma0rBy0=; b=LhJEkFe+pcQV9uVMTWz+OrlqZ/GE1Lmic2NrMYdTbKWghVjVfmkCohPNJyG6zV2Qiu WvusklHFnCGOZUiuLxkkh02cWZ5kVJaQc0gxnuHtMG6WXsZ+bHUHvqbEQzgzCJAuRZ/S Qa7ieAqjRcJIpdsk8SBZVtZxLODcVL+mymaJ1qdfoyoTt4kdbgZkVOwGyza6CyFNzncS X0ARMwcMDsOCrtdEnpknwT/04Rt2HdVS90JE4hVeq7xxqAjPUM6GJZ5/M6rfWEmEwn4g 3fxM7ZZyQR8ze8uPWsJBrUAUfc83faXxEh+PnHdos+Xw82FU1tqq3w1oNWwxGkO7emAl D8CA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zmrNMlzk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.52.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:52:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 09/68] target/nios2: Remove user-only nios2_cpu_do_interrupt Date: Fri, 22 Apr 2022 09:51:39 -0700 Message-Id: <20220422165238.1971496-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since 78271684719, this function is unused for user-only, when the TCGCPUOps.do_interrupt hook itself became system-only. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20220421151735.31996-10-richard.henderson@linaro.org> --- target/nios2/helper.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index e5c98650e1..678fd96c4e 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -30,14 +30,6 @@ #if defined(CONFIG_USER_ONLY) -void nios2_cpu_do_interrupt(CPUState *cs) -{ - Nios2CPU *cpu = NIOS2_CPU(cs); - CPUNios2State *env = &cpu->env; - cs->exception_index = -1; - env->regs[R_EA] = env->regs[R_PC] + 4; -} - void nios2_cpu_record_sigsegv(CPUState *cs, vaddr addr, MMUAccessType access_type, bool maperr, uintptr_t retaddr) From patchwork Fri Apr 22 16:51:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564847 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp664050map; Fri, 22 Apr 2022 10:04:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwQVjMNz5ock/Y5SK+F4syg7TeaMsfjaZLHGwCgrqRYeEYAEBBXiY39KrTig/x4rVct4hlj X-Received: by 2002:ad4:5d69:0:b0:446:3d44:2fbe with SMTP id fn9-20020ad45d69000000b004463d442fbemr4283604qvb.16.1650647093172; Fri, 22 Apr 2022 10:04:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650647093; cv=none; d=google.com; s=arc-20160816; b=ybm1EpDnr/ROt16dIxoclcH9GbWlKjScBxH/HVuGVTKyYN3+IzTRlO/KDj14rFhBH9 KVrPuQR4JVX1tz1j9G6F8+LD4jephiJRjg3weOZM3SCfxw6Z/xP3HquloiGn17/ekwWN qUoniJI5jQBFJewZx1MUh3eU+IjFDBP9mbJaV+3uSbspiMrVkjqkWvLHo6CR+XIj91Vv MyRnbyUfWFZ/X7fjfU8t7rVScBLWsGZFVjvMjd/WfBfS5NrResNLkadRP/4VW4An7RQB NwbAce43NB/bR1vzQ3iBneOY7hLIMqpq2Mh/f2LOjUUmeXDBjXVjDpIRr5Q6yk1WRPiP l1aQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=tSluLj2R1JhZMB4God4i50Z4RRfFTHgwIiUmh8NzNww=; b=ItTOpl1agZbqdBVjT11brEV8ZRpMNiSbUYt375BRqu2dFoEKuBPas0wIGRFihB9z3G skEV8LUvUyqUoK8F3PmqHk0aFjMxsrPw0IsZc+Q3hC0H/AQbh0L7ZZAHezAmCXN43wzy 0Mo05Myf++rXbC693IMAOdQzr2gxv6dkRi3xG19mDELauKLJQOrWCw6I8imJQjk8hK7w evR9ynKArkT3Wj/jHeq2Du8jZtjMvrvmybuFVNCxVFh9yJV3/wr5Vo/1SG2+JK6MnJXn mwJDbBEyuqUtCPp/3Tqw9me8bINGihsecNTskgpbAvWud9pPVZ5cKT+LyLreOUI+vhx2 KizQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RLCp3TyZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.52.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:52:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 10/68] target/nios2: Remove nios2_cpu_record_sigsegv Date: Fri, 22 Apr 2022 09:51:40 -0700 Message-Id: <20220422165238.1971496-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since f5ef0e518d0, we have a real page mapped for kuser, which means the special casing for SIGSEGV can go away. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20220421151735.31996-11-richard.henderson@linaro.org> --- target/nios2/cpu.h | 6 +----- linux-user/nios2/cpu_loop.c | 10 ---------- target/nios2/cpu.c | 4 +--- target/nios2/helper.c | 14 +------------- 4 files changed, 3 insertions(+), 31 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 1bab805bb0..3198c17213 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -216,11 +216,7 @@ static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch) MMU_SUPERVISOR_IDX; } -#ifdef CONFIG_USER_ONLY -void nios2_cpu_record_sigsegv(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - bool maperr, uintptr_t ra); -#else +#ifndef CONFIG_USER_ONLY bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index 2963fc62b4..f37850fe81 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -126,16 +126,6 @@ void cpu_loop(CPUNios2State *env) info.si_code = TARGET_TRAP_BRKPT; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case 0xaa: - { - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - /* TODO: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->regs[R_PC]; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; default: EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n", trapnr); diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index b0877cb39e..9774a3b8a4 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -210,9 +210,7 @@ static const struct SysemuCPUOps nios2_sysemu_ops = { static const struct TCGCPUOps nios2_tcg_ops = { .initialize = nios2_tcg_init, -#ifdef CONFIG_USER_ONLY - .record_sigsegv = nios2_cpu_record_sigsegv, -#else +#ifndef CONFIG_USER_ONLY .tlb_fill = nios2_cpu_tlb_fill, .cpu_exec_interrupt = nios2_cpu_exec_interrupt, .do_interrupt = nios2_cpu_do_interrupt, diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 678fd96c4e..55b8fb0bcb 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -28,19 +28,7 @@ #include "exec/helper-proto.h" #include "semihosting/semihost.h" -#if defined(CONFIG_USER_ONLY) - -void nios2_cpu_record_sigsegv(CPUState *cs, vaddr addr, - MMUAccessType access_type, - bool maperr, uintptr_t retaddr) -{ - /* FIXME: Disentangle kuser page from linux-user sigsegv handling. */ - cs->exception_index = 0xaa; - cpu_loop_exit_restore(cs, retaddr); -} - -#else /* !CONFIG_USER_ONLY */ - +#if !defined(CONFIG_USER_ONLY) void nios2_cpu_do_interrupt(CPUState *cs) { Nios2CPU *cpu = NIOS2_CPU(cs); From patchwork Fri Apr 22 16:51:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564851 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp666838map; Fri, 22 Apr 2022 10:07:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx8LnjDx/R1uLE0G7vdPuklM1G1Tg4fmKrWPIzjEtD4zVXi7D5KMvsFqBJnNB02IeYOA+Gp X-Received: by 2002:a05:620a:2a13:b0:69e:d327:6f7a with SMTP id o19-20020a05620a2a1300b0069ed3276f7amr3266872qkp.331.1650647269269; Fri, 22 Apr 2022 10:07:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650647269; cv=none; d=google.com; s=arc-20160816; b=vsVGCekGQtm7NQ7eDDoFah2vUEZ37qg8PUTZRkptYijc07iDAOTDsoYG34hDVAslZA 8MPpKpncE6qLhpU93zyYY5IRnhrveMWDLQ6oCi10o0ZCZ5GXoBMG0xujNjwRoyI25ILw Zww269Z8HGsiNYRwmNYsiyi/mMMHyEijJVD+37T05ftED8nWCZ6QYxdE1y2opg+wy7Vc 1ThUWsM5po9Qg2B5xS54rdWBrTdsjFCBpAO0fIGOl0NCCJRpi13HOVhFykscIbi3oQXq lhZARqgHlv769kQ6CZB9oywMK/DRhQ+u7AcU+bPwruvd6J4Kdq+nC1rbrtyuPl9Mi9AA RnGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=aSCpXgZFYrLKFx9z48EM2Iny/HfNa5ePJRFMiB+lNrQ=; b=zpKqAZCVr7TB6L1EkdscUT+r5q7yc2WqLTUvAlDBHMcoP3sprv10gwB/BRf8jR3XB2 svLcAwilmbqqw1xvTspBqfvcv+x7M9hBOBjHFF5brXxYv71uRs1f6d4p/5Jt4pZuDGkw gxUQyiYRWPR2YL8Sk2/FSPQ0oKwwIbG0lDdVosiJfFRJHPpmfnXLXFuu+HpslqA9hFJ1 3TW9sV4CBO1zkdhVWEr1hXvkSseDgaww85GpkiRfFy32ICOm2jlDzMbB2TYSMeD5g8e0 3KaemlF/q2YEMNZjrKey2smreIoqYZU+AcDBnO8GSa9qbAGkw7PiUQMqixHBCs9bTBR+ /NYA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LByxlg54; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.52.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:52:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 11/68] target/nios2: Build helper.c for system only Date: Fri, 22 Apr 2022 09:51:41 -0700 Message-Id: <20220422165238.1971496-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remove the #ifdef !defined(CONFIG_USER_ONLY) that surrounds the whole file, and move helper.c to nios2_softmmu_ss. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20220421151735.31996-12-richard.henderson@linaro.org> --- target/nios2/helper.c | 3 +-- target/nios2/meson.build | 7 +++++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 55b8fb0bcb..04a8831443 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -28,7 +28,7 @@ #include "exec/helper-proto.h" #include "semihosting/semihost.h" -#if !defined(CONFIG_USER_ONLY) + void nios2_cpu_do_interrupt(CPUState *cs) { Nios2CPU *cpu = NIOS2_CPU(cs); @@ -292,4 +292,3 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, env->regs[CR_BADADDR] = address; cpu_loop_exit_restore(cs, retaddr); } -#endif /* !CONFIG_USER_ONLY */ diff --git a/target/nios2/meson.build b/target/nios2/meson.build index 62b384702d..2bd60ba306 100644 --- a/target/nios2/meson.build +++ b/target/nios2/meson.build @@ -1,14 +1,17 @@ nios2_ss = ss.source_set() nios2_ss.add(files( 'cpu.c', - 'helper.c', 'nios2-semi.c', 'op_helper.c', 'translate.c', )) nios2_softmmu_ss = ss.source_set() -nios2_softmmu_ss.add(files('monitor.c', 'mmu.c')) +nios2_softmmu_ss.add(files( + 'helper.c', + 'monitor.c', + 'mmu.c' +)) target_arch += {'nios2': nios2_ss} target_softmmu_arch += {'nios2': nios2_softmmu_ss} From patchwork Fri Apr 22 16:51:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564841 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp657928map; Fri, 22 Apr 2022 09:57:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzv9q7pmgdu4RAHHZT8UCtms2NtcXwI7RoFVMR0lwQH1z3ljx/Q5FexvAjuz05Zy5tdD5F4 X-Received: by 2002:a05:622a:6206:b0:2f1:e40e:41b3 with SMTP id hj6-20020a05622a620600b002f1e40e41b3mr3984663qtb.196.1650646674384; Fri, 22 Apr 2022 09:57:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650646674; cv=none; d=google.com; s=arc-20160816; b=igJfc0Vg8/iRaRkJJi1ve2gsqTJZq7lauJMQ2TtNB3RQJHvYB+HJIune3CIpMdNuES /9LRiRw1nDzlpGhq4Xv4tTPM/uTAPf0FSz0a6MaIRwSsJj6LAGrcgBwRa2PQBsdNVEqq SFSA8bVSB5HnEqnzh9tWBsqqFsHhdL+bw+mqNZTkcL84vRIwZdGFogxRcCLfmyubhW0r JwL4oqutelQIhPnGxm2z2/hC8NDEqBYL+oT9TNyKEl1iS2Z4WBRPBnquaNoPoqa84x3B Vk8Ns8lIwgY1NAtZQ1CQk309X5R3qpwtlCdRTa9mZV0C+XAJaDI5Iqo+1SxvapXsMJhl 0uYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=RtRmXlsOxeVOyDOQBenqjq06keYpCIdFa3N3ui9g9FQ=; b=ZNy4X87hrbnB3hJNr8CUjOGsYjWnjAzD6WW4dDl1OunZz7UjpCa2zAoxmY0I71wHZc QPrgJfF/qcQjq8j+rA2LIxEQ9XXJlMhkh31q/knKbBZMat30Fm6jh78epCdKRiH88BOl z89/DNq5xNd6/sFMBGa/xaLhh9p3vYp+wNG/QxTmuWw8cjCeTFHPnqr7h6rdPnX4b/3y +rK8cIGWwv/vmzwpiSl4JOtbPhdwaW6v+fZTUlXCFKFnM8XqFKCgeHbllXDRzNrMDu6E d3tFdGVAi/pvr1b9+HMiwUlq1iUrbwAbQ7b8JdpOBCf029iZv8+wSSd+7uxuPWmcbrwx lrhA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CDpliTbH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 12/68] linux-user/nios2: Use force_sig_fault for EXCP_DEBUG Date: Fri, 22 Apr 2022 09:51:42 -0700 Message-Id: <20220422165238.1971496-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use the simpler signal interface, which forces us to supply the missing PC value to si_addr. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20220421151735.31996-13-richard.henderson@linaro.org> --- linux-user/nios2/cpu_loop.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index f37850fe81..e725036628 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -26,7 +26,6 @@ void cpu_loop(CPUNios2State *env) { CPUState *cs = env_cpu(env); - target_siginfo_t info; int trapnr, ret; for (;;) { @@ -121,10 +120,7 @@ void cpu_loop(CPUNios2State *env) break; case EXCP_DEBUG: - info.si_signo = TARGET_SIGTRAP; - info.si_errno = 0; - info.si_code = TARGET_TRAP_BRKPT; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->regs[R_PC]); break; default: EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n", From patchwork Fri Apr 22 16:51:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564854 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp668672map; Fri, 22 Apr 2022 10:09:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzj5OxR1pak2saZ35dPRDfXs9Is1f6M3BXpDwqdRMYv0GOtfTiFE3Yn/dOfNElo2nWGoW1s X-Received: by 2002:a05:620a:15ec:b0:69e:98c6:aed5 with SMTP id p12-20020a05620a15ec00b0069e98c6aed5mr3395457qkm.120.1650647392808; Fri, 22 Apr 2022 10:09:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650647392; cv=none; d=google.com; s=arc-20160816; b=AbQeP9JbbeA/+4k8NfVvtKytn0rwLifiiVXDz/jd8pDsM2OIjsNa2O6UZm/vMQ6rcu KMUc53RxpRmKDWvyB5fv6PBwXrmpsAQEDxvbm3JXh1h2mRwaNKCsbO5cc55FwpluOjvJ rngmTFULOC4l6IQ0C2R9fg0h3V586KRMvS8t+7pXWeF/G0gRK/yrmbgMpOKrSLVsmX90 vbi+jj5yUdxKYrlyHmShx86H80kFtIrGTLT0R1cDgLxmArX0frNymj5wOF2xrZLrS3pZ ELUigH2fJJkm5XlZVpS3G4ylZVYpxqeMLshzeVQASVK1wjGsyJza93Pj82Kr9Sx94xZP nohQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6UYSlRGZfhDryiA9u1wA9vZSGmpcy5aRg3TaG0SXLQ4=; b=y0nm57is3EwbJM+2TE0cQNUILUgDXiVwgCHInFT8KzyUt1MIo09eQoiSPgZAK+rrOg hENLG1EnWoLNZC54CFQhoBKWVItZGaQ/bD/dCjazMIx6tub2Jzua+hkpnnXXTYaeFjX4 ia6ZWwjgQ1SsEKVlBJKJbW8FduRWLREMj/LlTY6z72gWGRHOwqoWa12JThVQrBOyfKfq UXZmkOIAGBqFNiS2hslzk718LKEvrgZG9TvPEf0PCPhLoYp9QABwuJELUXBhW6qcQwFq Iysg5ybYLBGS+I32+sfYfB8GcuSjrgXQvzOVXXJeWZVfUQqAa5NUY5Yg8GxhGHhRSNXg FjIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PZfOO4AM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 13/68] target/nios2: Check supervisor on eret Date: Fri, 22 Apr 2022 09:51:43 -0700 Message-Id: <20220422165238.1971496-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Amir Gonnen Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Amir Gonnen eret instruction is only allowed in supervisor mode. Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Signed-off-by: Amir Gonnen Message-Id: <20220303153906.2024748-2-amir.gonnen@neuroblade.ai> Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-14-richard.henderson@linaro.org> --- target/nios2/translate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 89b97ef520..eb97e13feb 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -384,6 +384,8 @@ static const Nios2Instruction i_type_instructions[] = { */ static void eret(DisasContext *dc, uint32_t code, uint32_t flags) { + gen_check_supervisor(dc); + tcg_gen_mov_tl(cpu_R[CR_STATUS], cpu_R[CR_ESTATUS]); tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_EA]); From patchwork Fri Apr 22 16:51:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564845 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp660977map; Fri, 22 Apr 2022 10:01:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxRGARN3dJRu8fOQUUrwGwDTtK8B6EWOMJxSwzxCpXNdBsmULqp+vWBB9BHqzB6EWj1im0F X-Received: by 2002:a05:622a:4c8:b0:2f3:5809:dcd with SMTP id q8-20020a05622a04c800b002f358090dcdmr3076629qtx.222.1650646903601; Fri, 22 Apr 2022 10:01:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650646903; cv=none; d=google.com; s=arc-20160816; b=xnud2fgnhfpEZ9YBtAPJJAx4Zz5Q0PICGUfy4IiBgofDt59Te/PYThcYJFcAW14N5k O9pgEnlTQpeBFLeoX5DX26lBs/hg7lPfakxKKV5SCYFJFar6jDbXAzW81aiYgRr0Dm5c Wr2woF9l2bJgRV+LZhcsgWluxD+rpVamVZ+sLSY3nSQ9vAMY/xOMV/3fzByl3w+1wfPT wVtzJap3d/uAnwQpIhvqjcF3d9znIJda329CsKtYkXRRsh7+IxLPcP5fbF9wHZPPJEoF bnYG8y3hgE5UK0MwypPL0kS8WefvghjVCvJKgvnHqkGZYsfZFdWz1kCmheuflX26Q9F8 +v7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4LG2ggGa5J5Lu4I1wse39Ww5a8efRD9iZexWoAzkdh0=; b=ShNrA612odUozTepuwyxZWioAtaFI1omOmABqO1x7l9ude8jNw3ezE8FRBJAwcGD7/ Sq6ZL012QKzbk5LNTy9cae3uNNqw5z1w7FYb5SmZvWmnWv2w0MQo5iKBRl3p5um4TSkT Jh8Gl1nRDYmHpy1LWqlzKlcX4NWQZKIjp0phhvBgY5SpeQG3/Kie9VoGV7HzFAod2Ydp stwoG/dEjmenfPQ6FcpAl1J9hcpbXdf6eVkvg2G636K9cj9RmtYNi96le21NHvsA6LrD ssI8DygaH4OMjqfq0BLWB0elfHBFVDyntue9LsC435OjkunlAH1MbuTRNha1LToaWeLu H2qQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=F3UQuPkY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 14/68] target/nios2: Stop generating code if gen_check_supervisor fails Date: Fri, 22 Apr 2022 09:51:44 -0700 Message-Id: <20220422165238.1971496-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Whether the cpu is in user-mode or not is something that we know at translation-time. We do not need to generate code after having raised an exception. Suggested-by: Peter Maydell Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-15-richard.henderson@linaro.org> --- target/nios2/translate.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index eb97e13feb..d61e349207 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -169,12 +169,14 @@ static void gen_excp(DisasContext *dc, uint32_t code, uint32_t flags) t_gen_helper_raise_exception(dc, flags); } -static void gen_check_supervisor(DisasContext *dc) +static bool gen_check_supervisor(DisasContext *dc) { if (dc->base.tb->flags & CR_STATUS_U) { /* CPU in user mode, privileged instruction called, stop. */ t_gen_helper_raise_exception(dc, EXCP_SUPERI); + return false; } + return true; } /* @@ -384,7 +386,9 @@ static const Nios2Instruction i_type_instructions[] = { */ static void eret(DisasContext *dc, uint32_t code, uint32_t flags) { - gen_check_supervisor(dc); + if (!gen_check_supervisor(dc)) { + return; + } tcg_gen_mov_tl(cpu_R[CR_STATUS], cpu_R[CR_ESTATUS]); tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_EA]); @@ -447,7 +451,9 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, code); - gen_check_supervisor(dc); + if (!gen_check_supervisor(dc)) { + return; + } if (unlikely(instr.c == R_ZERO)) { return; @@ -474,9 +480,13 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) /* ctlN <- rA */ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags) { - gen_check_supervisor(dc); + if (!gen_check_supervisor(dc)) { + return; + } -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else R_TYPE(instr, code); TCGv v = load_gpr(dc, instr.a); From patchwork Fri Apr 22 16:51:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564855 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp670339map; Fri, 22 Apr 2022 10:11:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzzbg0AkeMlfJSv2n2B1pB3X56oMOxkMGcWU28PbI2r3AvvgvEXpJrP8MJSU8Zr32QWQoBD X-Received: by 2002:a37:ba45:0:b0:69b:e728:34b7 with SMTP id k66-20020a37ba45000000b0069be72834b7mr3297050qkf.606.1650647508006; Fri, 22 Apr 2022 10:11:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650647508; cv=none; d=google.com; s=arc-20160816; b=OuDn1LctG5jkiPLOeCOX9BGJsdj+ErvFeP5+fypqRKXBFrkVzRgff28X0yWT7tdImO Hx6ra74cDhTgRCoK8bckTwFBKGxNRPrVe232arqdOuGGEuh5fw7Ur5B/fYlaCoOlLrFr ljASUciE0kkSusgS5aLnfE3whfP6PuIjutDSejkAM+QfgWoSkYrLlGxrvBapHEo+qDrQ ULugBS8jyZ1h8HvAReo4rFAR+jJC6T2UcKOkjGC3aEhFZ7RNeEU1806idLy+/w1jkvE3 kHGLMpB+3E3445V6ge5rD7dTeW0TzroVKCw4JpsXmmADU7/6iSX3r4Vv1ZBzbJKsP3h7 ZOuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=oxknAb8WZp8/c3OBXmugT+dPS7TU38e5j5a7fcIuSm4=; b=iT3iNMw8YTl0Hh65sE+zhsy1XZ+ZoLte44mLa0Dbb5ifoNHOlGabDrDnvd4fg+WzOq MMdQLuXohKBW/hu/w+2WCTK1RWcYDySUFvTyuy7ZG871leGBOLYmHA4G/UlKcfhOLoe5 QxccHzZBgME3yglze4daqe/NtZHSt9A7NmG8jDUghhfKoxBblLSb2zhyNlaa2bpzza4w vUNOL4qteESTZhaqSZ+KKKsenzIjetGsPPzOVAIJnLV0fUieaI75f2SxapC3p2Cmqe1I 0GXRT0swVbi6NzGa/Kba5PwzQo5TrOR3maxQKhVv7SqmrJ4NtKsAEJRRTw7zU6iJFgP3 dC4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IoymGMka; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 15/68] target/nios2: Add NUM_GP_REGS and NUM_CP_REGS Date: Fri, 22 Apr 2022 09:51:45 -0700 Message-Id: <20220422165238.1971496-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Amir Gonnen Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Amir Gonnen Split NUM_CORE_REGS into components that can be used elsewhere. Reviewed-by: Peter Maydell Signed-off-by: Amir Gonnen Message-Id: <20220303153906.2024748-3-amir.gonnen@neuroblade.ai> [rth: Split out of a larger patch for shadow register sets.] Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-16-richard.henderson@linaro.org> --- target/nios2/cpu.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 3198c17213..09dc38a4e7 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -56,9 +56,11 @@ struct Nios2CPUClass { #define EXCEPTION_ADDRESS 0x00000004 #define FAST_TLB_MISS_ADDRESS 0x00000008 +#define NUM_GP_REGS 32 +#define NUM_CR_REGS 32 /* GP regs + CR regs + PC */ -#define NUM_CORE_REGS (32 + 32 + 1) +#define NUM_CORE_REGS (NUM_GP_REGS + NUM_CR_REGS + 1) /* General purpose register aliases */ #define R_ZERO 0 @@ -79,7 +81,7 @@ struct Nios2CPUClass { #define R_RA 31 /* Control register aliases */ -#define CR_BASE 32 +#define CR_BASE NUM_GP_REGS #define CR_STATUS (CR_BASE + 0) #define CR_STATUS_PIE (1 << 0) #define CR_STATUS_U (1 << 1) From patchwork Fri Apr 22 16:51:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564848 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp664634map; Fri, 22 Apr 2022 10:05:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxNgdky5zqldV1xax7/IpPK7ojeu+Qx9v/cLoRYyLRggCQJpOSa4jnyYXPdMcZr1UOHgC2L X-Received: by 2002:ac8:1487:0:b0:2ef:ca47:89c1 with SMTP id l7-20020ac81487000000b002efca4789c1mr4044209qtj.646.1650647130477; Fri, 22 Apr 2022 10:05:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650647130; cv=none; d=google.com; s=arc-20160816; b=IJQ4Qo01J3N/vYxLgh8+kyyw2a3B/VBgc9gquYjCiqRnwtnYCbVxlFNDqdimyUzH2x C/raWP3KvILl5XDUlXeXQXgr4EmjQMz/brYth0jfDL9EwYrXYnMOj9i16E1VJYz+bQ5Z Nnk1qW9QVBWNtGAIVR2S8IN/MBGYVEpPoLfGLDcvtQVv2iVc8gyQjtkteWrk+NF/ELfb 9YXUtYYjs/0sJ68mzB/FzWZ+Oc07HBrZDwCGNNuPEuT1t1T5N5hYejVUiBY4Mz6kJZMC hDcQXmcjLP6hcg0AdiVdW0VJuA2o5WrRWtWjgupJqejIZAnqwqHiTa92z+25/xCLuosI WoAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=i6tK1AeH5jwbz3jIl7FB7GUKXxYdrLeMzRjc3oifIdk=; b=SvrD6JPr7z9dve2+M+N3lDIgsiCu1t5/hY8Pv8vChTvApH55qtYV57vpO6Lu9pEDHd ziA9c6yfb6zkFPW6QeBLe/dJoRqdu7a/rnEUMtu2gqBcRmCLpHpJzirSXwttY/lt5g0q aZusJjVuIUee3L/EJUlLxzMFHqj5FVmWtT/4shngxf5w0essw1LJGsHgZ1PxPbdGl0qd aj3+m69F9tIGF3YzWao4WNgnVjrqPVWsYu3q7fokJ4zUD03LiT+OYJ6wkx3D5DdAZRBT b1BCeZyJLzQRputa/CWiNVieuwJbcl7PNokaRHcy38SwJtwHHeZgCjsPGorUGm9PDRTE 7wsQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vuRkr3I3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 16/68] target/nios2: Split PC out of env->regs[] Date: Fri, 22 Apr 2022 09:51:46 -0700 Message-Id: <20220422165238.1971496-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" It is cleaner to have a separate name for this variable. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-17-richard.henderson@linaro.org> --- target/nios2/cpu.h | 10 +++----- linux-user/elfload.c | 2 +- linux-user/nios2/cpu_loop.c | 19 +++++++------- linux-user/nios2/signal.c | 6 ++--- target/nios2/cpu.c | 8 +++--- target/nios2/helper.c | 49 +++++++++++++++++-------------------- target/nios2/translate.c | 29 +++++++++++----------- 7 files changed, 58 insertions(+), 65 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 09dc38a4e7..7c48b3452f 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -59,8 +59,8 @@ struct Nios2CPUClass { #define NUM_GP_REGS 32 #define NUM_CR_REGS 32 -/* GP regs + CR regs + PC */ -#define NUM_CORE_REGS (NUM_GP_REGS + NUM_CR_REGS + 1) +/* GP regs + CR regs */ +#define NUM_CORE_REGS (NUM_GP_REGS + NUM_CR_REGS) /* General purpose register aliases */ #define R_ZERO 0 @@ -130,9 +130,6 @@ struct Nios2CPUClass { #define CR_MPUBASE (CR_BASE + 14) #define CR_MPUACC (CR_BASE + 15) -/* Other registers */ -#define R_PC 64 - /* Exceptions */ #define EXCP_BREAK 0x1000 #define EXCP_RESET 0 @@ -158,6 +155,7 @@ struct Nios2CPUClass { struct CPUArchState { uint32_t regs[NUM_CORE_REGS]; + uint32_t pc; #if !defined(CONFIG_USER_ONLY) Nios2MMU mmu; @@ -237,7 +235,7 @@ typedef Nios2CPU ArchCPU; static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) { - *pc = env->regs[R_PC]; + *pc = env->pc; *cs_base = 0; *flags = (env->regs[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U)); } diff --git a/linux-user/elfload.c b/linux-user/elfload.c index d6bb1fc7ca..397dec5eb8 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1170,7 +1170,7 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, (*regs)[30] = -1; /* R_SSTATUS */ (*regs)[31] = tswapreg(env->regs[R_RA]); - (*regs)[32] = tswapreg(env->regs[R_PC]); + (*regs)[32] = tswapreg(env->pc); (*regs)[33] = -1; /* R_STATUS */ (*regs)[34] = tswapreg(env->regs[CR_ESTATUS]); diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index e725036628..a941f9032e 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -43,7 +43,7 @@ void cpu_loop(CPUNios2State *env) * TODO: This advance should be done in the translator, as * hardware produces an advanced pc as part of all exceptions. */ - env->regs[R_PC] += 4; + env->pc += 4; switch (env->error_code) { case 0: @@ -59,7 +59,7 @@ void cpu_loop(CPUNios2State *env) break; } if (ret == -QEMU_ERESTARTSYS) { - env->regs[R_PC] -= 4; + env->pc -= 4; break; } /* @@ -74,22 +74,21 @@ void cpu_loop(CPUNios2State *env) case 1: qemu_log_mask(CPU_LOG_INT, "\nTrap 1\n"); - force_sig_fault(TARGET_SIGUSR1, 0, env->regs[R_PC]); + force_sig_fault(TARGET_SIGUSR1, 0, env->pc); break; case 2: qemu_log_mask(CPU_LOG_INT, "\nTrap 2\n"); - force_sig_fault(TARGET_SIGUSR2, 0, env->regs[R_PC]); + force_sig_fault(TARGET_SIGUSR2, 0, env->pc); break; case 31: qemu_log_mask(CPU_LOG_INT, "\nTrap 31\n"); /* Match kernel's breakpoint_c(). */ - env->regs[R_PC] -= 4; - force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->regs[R_PC]); + env->pc -= 4; + force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc); break; default: qemu_log_mask(CPU_LOG_INT, "\nTrap %d\n", env->error_code); - force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLTRP, - env->regs[R_PC]); + force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLTRP, env->pc); break; case 16: /* QEMU specific, for __kuser_cmpxchg */ @@ -120,7 +119,7 @@ void cpu_loop(CPUNios2State *env) break; case EXCP_DEBUG: - force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->regs[R_PC]); + force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc); break; default: EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n", @@ -156,6 +155,6 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) env->regs[R_SP] = regs->sp; env->regs[R_GP] = regs->gp; env->regs[CR_ESTATUS] = regs->estatus; - env->regs[R_PC] = regs->ea; + env->pc = regs->ea; /* TODO: unsigned long orig_r7; */ } diff --git a/linux-user/nios2/signal.c b/linux-user/nios2/signal.c index 9aa525e723..32b3dc99c6 100644 --- a/linux-user/nios2/signal.c +++ b/linux-user/nios2/signal.c @@ -73,7 +73,7 @@ static void rt_setup_ucontext(struct target_ucontext *uc, CPUNios2State *env) __put_user(env->regs[R_RA], &gregs[23]); __put_user(env->regs[R_FP], &gregs[24]); __put_user(env->regs[R_GP], &gregs[25]); - __put_user(env->regs[R_PC], &gregs[27]); + __put_user(env->pc, &gregs[27]); __put_user(env->regs[R_SP], &gregs[28]); } @@ -121,7 +121,7 @@ static int rt_restore_ucontext(CPUNios2State *env, struct target_ucontext *uc) __get_user(env->regs[R_GP], &gregs[25]); /* Not really necessary no user settable bits */ __get_user(temp, &gregs[26]); - __get_user(env->regs[R_PC], &gregs[27]); + __get_user(env->pc, &gregs[27]); __get_user(env->regs[R_RA], &gregs[23]); __get_user(env->regs[R_SP], &gregs[28]); @@ -177,7 +177,7 @@ void setup_rt_frame(int sig, struct target_sigaction *ka, env->regs[4] = sig; env->regs[5] = frame_addr + offsetof(struct target_rt_sigframe, info); env->regs[6] = frame_addr + offsetof(struct target_rt_sigframe, uc); - env->regs[R_PC] = ka->_sa_handler; + env->pc = ka->_sa_handler; unlock_user_struct(frame, frame_addr, 1); } diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 9774a3b8a4..dc1551241e 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -31,7 +31,7 @@ static void nios2_cpu_set_pc(CPUState *cs, vaddr value) Nios2CPU *cpu = NIOS2_CPU(cs); CPUNios2State *env = &cpu->env; - env->regs[R_PC] = value; + env->pc = value; } static bool nios2_cpu_has_work(CPUState *cs) @@ -49,7 +49,7 @@ static void nios2_cpu_reset(DeviceState *dev) ncc->parent_reset(dev); memset(env->regs, 0, sizeof(uint32_t) * NUM_CORE_REGS); - env->regs[R_PC] = cpu->reset_addr; + env->pc = cpu->reset_addr; #if defined(CONFIG_USER_ONLY) /* Start in user mode with interrupts enabled. */ @@ -156,7 +156,7 @@ static int nios2_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) if (n < 32) { /* GP regs */ return gdb_get_reg32(mem_buf, env->regs[n]); } else if (n == 32) { /* PC */ - return gdb_get_reg32(mem_buf, env->regs[R_PC]); + return gdb_get_reg32(mem_buf, env->pc); } else if (n < 49) { /* Status regs */ return gdb_get_reg32(mem_buf, env->regs[n - 1]); } @@ -178,7 +178,7 @@ static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) if (n < 32) { /* GP regs */ env->regs[n] = ldl_p(mem_buf); } else if (n == 32) { /* PC */ - env->regs[R_PC] = ldl_p(mem_buf); + env->pc = ldl_p(mem_buf); } else if (n < 49) { /* Status regs */ env->regs[n - 1] = ldl_p(mem_buf); } diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 04a8831443..34b3e18e37 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -38,7 +38,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_IRQ: assert(env->regs[CR_STATUS] & CR_STATUS_PIE); - qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%x\n", env->regs[R_PC]); + qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%x\n", env->pc); env->regs[CR_ESTATUS] = env->regs[CR_STATUS]; env->regs[CR_STATUS] |= CR_STATUS_IH; @@ -47,14 +47,13 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[CR_EXCEPTION] &= ~(0x1F << 2); env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; - env->regs[R_EA] = env->regs[R_PC] + 4; - env->regs[R_PC] = cpu->exception_addr; + env->regs[R_EA] = env->pc + 4; + env->pc = cpu->exception_addr; break; case EXCP_TLBD: if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) { - qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=%x\n", - env->regs[R_PC]); + qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=%x\n", env->pc); /* Fast TLB miss */ /* Variation from the spec. Table 3-35 of the cpu reference shows @@ -70,11 +69,10 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[CR_TLBMISC] &= ~CR_TLBMISC_DBL; env->regs[CR_TLBMISC] |= CR_TLBMISC_WR; - env->regs[R_EA] = env->regs[R_PC] + 4; - env->regs[R_PC] = cpu->fast_tlb_miss_addr; + env->regs[R_EA] = env->pc + 4; + env->pc = cpu->fast_tlb_miss_addr; } else { - qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=%x\n", - env->regs[R_PC]); + qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=%x\n", env->pc); /* Double TLB miss */ env->regs[CR_STATUS] |= CR_STATUS_EH; @@ -85,14 +83,14 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[CR_TLBMISC] |= CR_TLBMISC_DBL; - env->regs[R_PC] = cpu->exception_addr; + env->pc = cpu->exception_addr; } break; case EXCP_TLBR: case EXCP_TLBW: case EXCP_TLBX: - qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=%x\n", env->regs[R_PC]); + qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=%x\n", env->pc); env->regs[CR_ESTATUS] = env->regs[CR_STATUS]; env->regs[CR_STATUS] |= CR_STATUS_EH; @@ -105,19 +103,18 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[CR_TLBMISC] |= CR_TLBMISC_WR; } - env->regs[R_EA] = env->regs[R_PC] + 4; - env->regs[R_PC] = cpu->exception_addr; + env->regs[R_EA] = env->pc + 4; + env->pc = cpu->exception_addr; break; case EXCP_SUPERA: case EXCP_SUPERI: case EXCP_SUPERD: - qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=%x\n", - env->regs[R_PC]); + qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=%x\n", env->pc); if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) { env->regs[CR_ESTATUS] = env->regs[CR_STATUS]; - env->regs[R_EA] = env->regs[R_PC] + 4; + env->regs[R_EA] = env->pc + 4; } env->regs[CR_STATUS] |= CR_STATUS_EH; @@ -126,17 +123,16 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[CR_EXCEPTION] &= ~(0x1F << 2); env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; - env->regs[R_PC] = cpu->exception_addr; + env->pc = cpu->exception_addr; break; case EXCP_ILLEGAL: case EXCP_TRAP: - qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=%x\n", - env->regs[R_PC]); + qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=%x\n", env->pc); if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) { env->regs[CR_ESTATUS] = env->regs[CR_STATUS]; - env->regs[R_EA] = env->regs[R_PC] + 4; + env->regs[R_EA] = env->pc + 4; } env->regs[CR_STATUS] |= CR_STATUS_EH; @@ -145,24 +141,23 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[CR_EXCEPTION] &= ~(0x1F << 2); env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; - env->regs[R_PC] = cpu->exception_addr; + env->pc = cpu->exception_addr; break; case EXCP_BREAK: - qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=%x\n", - env->regs[R_PC]); + qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=%x\n", env->pc); /* The semihosting instruction is "break 1". */ if (semihosting_enabled() && - cpu_ldl_code(env, env->regs[R_PC]) == 0x003da07a) { + cpu_ldl_code(env, env->pc) == 0x003da07a) { qemu_log_mask(CPU_LOG_INT, "Entering semihosting\n"); - env->regs[R_PC] += 4; + env->pc += 4; do_nios2_semihosting(env); break; } if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) { env->regs[CR_BSTATUS] = env->regs[CR_STATUS]; - env->regs[R_BA] = env->regs[R_PC] + 4; + env->regs[R_BA] = env->pc + 4; } env->regs[CR_STATUS] |= CR_STATUS_EH; @@ -171,7 +166,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[CR_EXCEPTION] &= ~(0x1F << 2); env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; - env->regs[R_PC] = cpu->exception_addr; + env->pc = cpu->exception_addr; break; default: diff --git a/target/nios2/translate.c b/target/nios2/translate.c index d61e349207..226bd9e30b 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -104,6 +104,7 @@ typedef struct DisasContext { } DisasContext; static TCGv cpu_R[NUM_CORE_REGS]; +static TCGv cpu_pc; typedef struct Nios2Instruction { void (*handler)(DisasContext *dc, uint32_t code, uint32_t flags); @@ -144,7 +145,7 @@ static void t_gen_helper_raise_exception(DisasContext *dc, { TCGv_i32 tmp = tcg_const_i32(index); - tcg_gen_movi_tl(cpu_R[R_PC], dc->pc); + tcg_gen_movi_tl(cpu_pc, dc->pc); gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); dc->base.is_jmp = DISAS_NORETURN; @@ -156,10 +157,10 @@ static void gen_goto_tb(DisasContext *dc, int n, uint32_t dest) if (translator_use_goto_tb(&dc->base, dest)) { tcg_gen_goto_tb(n); - tcg_gen_movi_tl(cpu_R[R_PC], dest); + tcg_gen_movi_tl(cpu_pc, dest); tcg_gen_exit_tb(tb, n); } else { - tcg_gen_movi_tl(cpu_R[R_PC], dest); + tcg_gen_movi_tl(cpu_pc, dest); tcg_gen_exit_tb(NULL, 0); } } @@ -391,7 +392,7 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags) } tcg_gen_mov_tl(cpu_R[CR_STATUS], cpu_R[CR_ESTATUS]); - tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_EA]); + tcg_gen_mov_tl(cpu_pc, cpu_R[R_EA]); dc->base.is_jmp = DISAS_JUMP; } @@ -399,7 +400,7 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags) /* PC <- ra */ static void ret(DisasContext *dc, uint32_t code, uint32_t flags) { - tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_RA]); + tcg_gen_mov_tl(cpu_pc, cpu_R[R_RA]); dc->base.is_jmp = DISAS_JUMP; } @@ -407,7 +408,7 @@ static void ret(DisasContext *dc, uint32_t code, uint32_t flags) /* PC <- ba */ static void bret(DisasContext *dc, uint32_t code, uint32_t flags) { - tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_BA]); + tcg_gen_mov_tl(cpu_pc, cpu_R[R_BA]); dc->base.is_jmp = DISAS_JUMP; } @@ -417,7 +418,7 @@ static void jmp(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, code); - tcg_gen_mov_tl(cpu_R[R_PC], load_gpr(dc, instr.a)); + tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a)); dc->base.is_jmp = DISAS_JUMP; } @@ -440,7 +441,7 @@ static void callr(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, code); - tcg_gen_mov_tl(cpu_R[R_PC], load_gpr(dc, instr.a)); + tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a)); tcg_gen_movi_tl(cpu_R[R_RA], dc->base.pc_next); dc->base.is_jmp = DISAS_JUMP; @@ -742,7 +743,7 @@ illegal_op: t_gen_helper_raise_exception(dc, EXCP_ILLEGAL); } -static const char * const regnames[] = { +static const char * const regnames[NUM_CORE_REGS] = { "zero", "at", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", @@ -759,7 +760,6 @@ static const char * const regnames[] = { "reserved6", "reserved7", "reserved8", "reserved9", "reserved10", "reserved11", "reserved12", "reserved13", "reserved14", "reserved15", "reserved16", "reserved17", - "rpc" }; #include "exec/gen-icount.h" @@ -827,7 +827,7 @@ static void nios2_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) case DISAS_TOO_MANY: case DISAS_UPDATE: /* Save the current PC back into the CPU register */ - tcg_gen_movi_tl(cpu_R[R_PC], dc->base.pc_next); + tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); tcg_gen_exit_tb(NULL, 0); break; @@ -877,8 +877,7 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags) return; } - qemu_fprintf(f, "IN: PC=%x %s\n", - env->regs[R_PC], lookup_symbol(env->regs[R_PC])); + qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc)); for (i = 0; i < NUM_CORE_REGS; i++) { qemu_fprintf(f, "%9s=%8.8x ", regnames[i], env->regs[i]); @@ -904,10 +903,12 @@ void nios2_tcg_init(void) offsetof(CPUNios2State, regs[i]), regnames[i]); } + cpu_pc = tcg_global_mem_new(cpu_env, + offsetof(CPUNios2State, pc), "pc"); } void restore_state_to_opc(CPUNios2State *env, TranslationBlock *tb, target_ulong *data) { - env->regs[R_PC] = data[0]; + env->pc = data[0]; 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 17/68] target/nios2: Split out helper for eret instruction Date: Fri, 22 Apr 2022 09:51:47 -0700 Message-Id: <20220422165238.1971496-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Amir Gonnen Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Amir Gonnen The implementation of eret will become much more complex with the introduction of shadow registers. [rth: Split out of a larger patch for shadow register sets. Directly exit to the cpu loop from the helper.] Reviewed-by: Peter Maydell Signed-off-by: Amir Gonnen Message-Id: <20220303153906.2024748-3-amir.gonnen@neuroblade.ai> Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-18-richard.henderson@linaro.org> --- target/nios2/helper.h | 1 + target/nios2/op_helper.c | 9 +++++++++ target/nios2/translate.c | 10 ++++++---- 3 files changed, 16 insertions(+), 4 deletions(-) diff --git a/target/nios2/helper.h b/target/nios2/helper.h index a44ecfdf7a..525b6b685b 100644 --- a/target/nios2/helper.h +++ b/target/nios2/helper.h @@ -21,6 +21,7 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) #if !defined(CONFIG_USER_ONLY) +DEF_HELPER_3(eret, noreturn, env, i32, i32) DEF_HELPER_2(mmu_write_tlbacc, void, env, i32) DEF_HELPER_2(mmu_write_tlbmisc, void, env, i32) DEF_HELPER_2(mmu_write_pteaddr, void, env, i32) diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index caa885f7b4..ee5ad8b23f 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -30,3 +30,12 @@ void helper_raise_exception(CPUNios2State *env, uint32_t index) cs->exception_index = index; cpu_loop_exit(cs); } + +#ifndef CONFIG_USER_ONLY +void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc) +{ + env->regs[CR_STATUS] = new_status; + env->pc = new_pc; + cpu_loop_exit(env_cpu(env)); +} +#endif /* !CONFIG_USER_ONLY */ diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 226bd9e30b..53699ee088 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -391,10 +391,12 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags) return; } - tcg_gen_mov_tl(cpu_R[CR_STATUS], cpu_R[CR_ESTATUS]); - tcg_gen_mov_tl(cpu_pc, cpu_R[R_EA]); - - dc->base.is_jmp = DISAS_JUMP; +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + gen_helper_eret(cpu_env, cpu_R[CR_ESTATUS], cpu_R[R_EA]); + dc->base.is_jmp = DISAS_NORETURN; +#endif } /* PC <- ra */ From patchwork Fri Apr 22 16:51:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564858 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp672924map; Fri, 22 Apr 2022 10:14:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxKCNC+iXyesPrMiRmaTRpZcBLnWL1o9dPlhM9hD//u29KmTNX9kqHLYjgwXfWIVuoDcc4v X-Received: by 2002:a05:6214:5282:b0:443:e161:ef4a with SMTP id kj2-20020a056214528200b00443e161ef4amr4483684qvb.23.1650647676222; Fri, 22 Apr 2022 10:14:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650647676; cv=none; d=google.com; s=arc-20160816; b=wQzpqFdvX4lbDBnQQGLLYhT/NAp5UccjaVgmZsH9BoPFlEXzcJ6hdcmD3ovGFtnLkc +dtnmZjcA1M5PYxKi1QejaAGTqeLNs2htF1x2Agvbi5FyOhxPN1u2/DQbojC+lM6jnKR H+N5ekpQ6i+on43So2/rLyQ8Hl1YsXdki7Tku1z9JJH+dVbFDrUDNoODjAYyjvevxFSs lPoCvUk7hmzc2ESpjjWv/d/tAWD2hHuy/1GxALIOm89nxvCyi2/wjxDi8iByTR8L1c9g kxgiass1zJSJuneLSPGw08g76cewxSrbLYZCL/QuOFOlPY/W6FkxyKe1BOLt6rB7OsQk nkXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=i+pIlq3Zf7Ct4aEs80TxFQjBRjx+ntMdX+PCJRolBhs=; b=vBhvaaZdxX3vJNL/yCSJnVV5bcNvcXZkwSNmC0JDoXy89wMSZk3SflixBoWJcZhVcq HD/OBnIgHTIiOA29UiwtHwm5VrltWhDvbAKSnNAl42mH/w8YViD1BkHJfvYtx1cnvyi9 Lq/o42ojhIuKr+FDGfSIqol+QuRxNSgkH8w10izYwm709hpK994FsYUmBP+55ltJCXyY aAdAIk0AQ4rvCoeyzvtQD0/cS+MPDEYReR1+yoigOkEjw5rXHU4DYMz+L0Vk40HyisSh 05X9eMl6hWcq9RsDuxD8pB5LRcBYPTjdUyA6+vRGkIn1Xm9F7aK5iHs7OEp0xjObLjn1 2dWw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dlRi35B6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 18/68] target/nios2: Fix BRET instruction Date: Fri, 22 Apr 2022 09:51:48 -0700 Message-Id: <20220422165238.1971496-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We had failed to copy BSTATUS back to STATUS, and diagnose supervisor-only. The spec is light on the specifics of the implementation of bret, but it is an easy assumption that the restore into STATUS should work the same as eret. Therefore, reuse the existing helper_eret. Reviewed-by: Peter Maydell Reported-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-19-richard.henderson@linaro.org> --- target/nios2/translate.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 53699ee088..3694f2503b 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -407,12 +407,22 @@ static void ret(DisasContext *dc, uint32_t code, uint32_t flags) dc->base.is_jmp = DISAS_JUMP; } -/* PC <- ba */ +/* + * status <- bstatus + * PC <- ba + */ static void bret(DisasContext *dc, uint32_t code, uint32_t flags) { - tcg_gen_mov_tl(cpu_pc, cpu_R[R_BA]); + if (!gen_check_supervisor(dc)) { + return; + } - dc->base.is_jmp = DISAS_JUMP; +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + gen_helper_eret(cpu_env, cpu_R[CR_BSTATUS], cpu_R[R_BA]); + dc->base.is_jmp = DISAS_NORETURN; +#endif } /* PC <- rA */ From patchwork Fri Apr 22 16:51:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564862 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp676543map; Fri, 22 Apr 2022 10:18:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwznJTL3OrO9wLqKL+DQtnaE2v8EjA6f4pTI6nr38r3m8VcKq95VTFhQ/mBi0X1vY+OBkCh X-Received: by 2002:ac8:5cc7:0:b0:2f3:5996:7667 with SMTP id s7-20020ac85cc7000000b002f359967667mr2467920qta.2.1650647909559; Fri, 22 Apr 2022 10:18:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650647909; cv=none; d=google.com; s=arc-20160816; b=V43N59i2dc8U2G2nsofx+OkST0LYCadxa0ZyB5y2Jzy+8VpU5oNRzymuypl1WGEGjg EIonxqMCQ8sali1okiqTpsTCwiUTCScSZrMjmXD7Ob7DnizzDpOeLpYr8JbNxaA6RNXC lOOmIRcCGxKvIN/+9bMxDirALuvvjEBqCCh3eqBQzj8+D9MmWujeQUsDlXmiUUrr27JQ cn8PgBk1J1avnznh6/MdWmynB5zEqMlC3m+1fi0UsUyTXKCXGW9TsPDuz6XX8wE3+CVC muj0GFKKutOQtBs0odjZFBY6gkXdOzbqm4M5xoysrtK+SyVG7jhJo4JRn5ictneUUegF aYpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=r8f+qzpvdgvny2fiqiDe7wZJGOpE02k47NFtBiJd8Y4=; b=TOTSr9tU94iGgLQ11JJvJmApx1L4aAm5MPtNZn4xsC0MmcgVDVLsUsbIC09VSTfgLn PJ0LVZfu74zlojU2MPyIhAkKgdmJqd4SzltgMOZdAUw3uiAQQZFDHT94LMA4ajTbBr74 ZAUA6XjR2yZZRmEc4gV/HJysQ6R+wS3C9sMKB0PyYkgQXCE7zElFJEJ2VacLPSJ6IVPg ZF7rX3jPcAt6PeoG//UJjv8ieAkRiopaAZBG8wH0WNm8Xb9wQA5x31cU7EXO2o/AkGIo 0sBVd4bnjnwU0cgBccOU1fToqc52H6D8hEcO+sI4NxFeN8fUvV591N1NDAW9ZVijUpP8 Xiwg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Av8Ebfbq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 19/68] target/nios2: Do not create TCGv for control registers Date: Fri, 22 Apr 2022 09:51:49 -0700 Message-Id: <20220422165238.1971496-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We don't need to reference them often, and when we do it is just as easy to load/store from cpu_env directly. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-20-richard.henderson@linaro.org> --- target/nios2/translate.c | 33 ++++++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 7 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 3694f2503b..6c739bfa5e 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -103,7 +103,7 @@ typedef struct DisasContext { int mem_idx; } DisasContext; -static TCGv cpu_R[NUM_CORE_REGS]; +static TCGv cpu_R[NUM_GP_REGS]; static TCGv cpu_pc; typedef struct Nios2Instruction { @@ -394,7 +394,11 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags) #ifdef CONFIG_USER_ONLY g_assert_not_reached(); #else - gen_helper_eret(cpu_env, cpu_R[CR_ESTATUS], cpu_R[R_EA]); + TCGv tmp = tcg_temp_new(); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, regs[CR_ESTATUS])); + gen_helper_eret(cpu_env, tmp, cpu_R[R_EA]); + tcg_temp_free(tmp); + dc->base.is_jmp = DISAS_NORETURN; #endif } @@ -420,7 +424,11 @@ static void bret(DisasContext *dc, uint32_t code, uint32_t flags) #ifdef CONFIG_USER_ONLY g_assert_not_reached(); #else - gen_helper_eret(cpu_env, cpu_R[CR_BSTATUS], cpu_R[R_BA]); + TCGv tmp = tcg_temp_new(); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, regs[CR_BSTATUS])); + gen_helper_eret(cpu_env, tmp, cpu_R[R_BA]); + tcg_temp_free(tmp); + dc->base.is_jmp = DISAS_NORETURN; #endif } @@ -463,6 +471,7 @@ static void callr(DisasContext *dc, uint32_t code, uint32_t flags) static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, code); + TCGv t1, t2; if (!gen_check_supervisor(dc)) { return; @@ -482,10 +491,19 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) * must perform the AND here, and anywhere else we need the * guest value of ipending. */ - tcg_gen_and_tl(cpu_R[instr.c], cpu_R[CR_IPENDING], cpu_R[CR_IENABLE]); + t1 = tcg_temp_new(); + t2 = tcg_temp_new(); + tcg_gen_ld_tl(t1, cpu_env, + offsetof(CPUNios2State, regs[CR_IPENDING])); + tcg_gen_ld_tl(t2, cpu_env, + offsetof(CPUNios2State, regs[CR_IENABLE])); + tcg_gen_and_tl(cpu_R[instr.c], t1, t2); + tcg_temp_free(t1); + tcg_temp_free(t2); break; default: - tcg_gen_mov_tl(cpu_R[instr.c], cpu_R[instr.imm5 + CR_BASE]); + tcg_gen_ld_tl(cpu_R[instr.c], cpu_env, + offsetof(CPUNios2State, regs[instr.imm5 + CR_BASE])); break; } } @@ -522,7 +540,8 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags) dc->base.is_jmp = DISAS_UPDATE; /* fall through */ default: - tcg_gen_mov_tl(cpu_R[instr.imm5 + CR_BASE], v); + tcg_gen_st_tl(v, cpu_env, + offsetof(CPUNios2State, regs[instr.imm5 + CR_BASE])); break; } #endif @@ -910,7 +929,7 @@ void nios2_tcg_init(void) { int i; - for (i = 0; i < NUM_CORE_REGS; i++) { + for (i = 0; i < NUM_GP_REGS; i++) { cpu_R[i] = tcg_global_mem_new(cpu_env, offsetof(CPUNios2State, regs[i]), regnames[i]); From patchwork Fri Apr 22 16:51:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564859 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp674167map; 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 20/68] linux-user/nios2: Only initialize SP and PC in target_cpu_copy_regs Date: Fri, 22 Apr 2022 09:51:50 -0700 Message-Id: <20220422165238.1971496-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Drop the set of estatus in init_thread; it was clearly intended to be setting the value of CR_STATUS for the application, but we never actually performed that copy. However, the proper value is set in nios2_cpu_reset so we don't need to do anything here. We only initialize SP and EA in init_thread, there's no value in copying other uninitialized data into ENV. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-21-richard.henderson@linaro.org> --- linux-user/elfload.c | 1 - linux-user/nios2/cpu_loop.c | 22 ---------------------- 2 files changed, 23 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 397dec5eb8..61063fd974 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1096,7 +1096,6 @@ static void init_thread(struct target_pt_regs *regs, struct image_info *infop) { regs->ea = infop->entry; regs->sp = infop->start_stack; - regs->estatus = 0x3; } #define LO_COMMPAGE TARGET_PAGE_SIZE diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index a941f9032e..c5e68ac048 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -133,28 +133,6 @@ void cpu_loop(CPUNios2State *env) void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { - env->regs[0] = 0; - env->regs[1] = regs->r1; - env->regs[2] = regs->r2; - env->regs[3] = regs->r3; - env->regs[4] = regs->r4; - env->regs[5] = regs->r5; - env->regs[6] = regs->r6; - env->regs[7] = regs->r7; - env->regs[8] = regs->r8; - env->regs[9] = regs->r9; - env->regs[10] = regs->r10; - env->regs[11] = regs->r11; - env->regs[12] = regs->r12; - env->regs[13] = regs->r13; - env->regs[14] = regs->r14; - env->regs[15] = regs->r15; - /* TODO: unsigned long orig_r2; */ - env->regs[R_RA] = regs->ra; - env->regs[R_FP] = regs->fp; env->regs[R_SP] = regs->sp; - env->regs[R_GP] = regs->gp; - env->regs[CR_ESTATUS] = regs->estatus; env->pc = regs->ea; - /* TODO: unsigned long orig_r7; */ } From patchwork Fri Apr 22 16:51:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564863 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp677333map; Fri, 22 Apr 2022 10:19:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyOBOj9yGKCDNWBcjEw31Ngfzq+Q4IAPbWP4qAMAUQ80+R8TPRfgrvtkLQDtSFl+nV4mLuA X-Received: by 2002:a05:620a:2681:b0:67e:909f:d5ac with SMTP id c1-20020a05620a268100b0067e909fd5acmr3351115qkp.125.1650647973104; Fri, 22 Apr 2022 10:19:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650647973; cv=none; d=google.com; s=arc-20160816; b=YzKP1ptgOHL9uwh1zSrjzjq3Ao1gIioMNQOLRn8j5AbJ4icLvZUVT7/PgsozMEO81H rvsgFpegxQt28/rs7VoindInYe+M9ivY8PkO6GzO44CJ/YINO5cxvhxQvmna7MgncjP6 sSMjIc3XJTOj9m9HXIQxJ58NFRD+jBDbLHrnXjiFBXLs2CvMWz+eMvo4KlJJo+ZgQ6wV W7FNPEebklpLof04A8rTcXxjDopY9MinaxCTlLiw9tFZZa15LAQuou/5dbrmcNrNh8DX Ol3LHIsiWPZ8Eno81HhZk+c4smWUrxd/P3Z8tYI2LZVO5yrR9pm9waK4NXaX21p9+Gw0 ebUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WDgeHzUdOULYKlRg869VIeEkdCFXvvv6jSBdC5RVE7o=; b=qn6+4xIt1gnLlshn+0zT8ZfGvH2ofSWBVvxYw6+TqS/8/khqo838dcCwl0T55KJ73c tq0hMGKN6rj8A27/j5c4b+blonsg4L2t2dsJyHEn0lsyrtoYUukodOrvWHR0FK+rOitf SSXgnh/O6GQyCMC09iizE+kP2dIGR0jya6uV4MUja7DRe2xrf/dazy50W+3TZ94zMLTY IRLIYTj+Uvv6q2tFXbBL3WlXRW5J/TZnQIrUl0L3cAkEdaTjwe7P/StA6pFuiSmrsUGF t1FiI71IDuTn/XKWmk+uqqudJIUDf3fsyS5nCfYBqN/YXxYZuK2LHiubisouHm/E8iMD ldjg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="r7A70/zu"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 21/68] target/nios2: Remove cpu_interrupts_enabled Date: Fri, 22 Apr 2022 09:51:51 -0700 Message-Id: <20220422165238.1971496-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This function is unused. The real computation of this value is located in nios2_cpu_exec_interrupt. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-22-richard.henderson@linaro.org> --- target/nios2/cpu.h | 5 ----- 1 file changed, 5 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 7c48b3452f..6bd8367eb8 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -222,11 +222,6 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, bool probe, uintptr_t retaddr); #endif -static inline int cpu_interrupts_enabled(CPUNios2State *env) -{ - return env->regs[CR_STATUS] & CR_STATUS_PIE; -} - typedef CPUNios2State CPUArchState; typedef Nios2CPU ArchCPU; From patchwork Fri Apr 22 16:51:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564866 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp678363map; Fri, 22 Apr 2022 10:21:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwZ8e9Ujm+pEy5whMk8BUvZHdXQdYb2XNhtLd2+UzhcGFyf0+N4dznvkEWdJZFbbuod0pvH X-Received: by 2002:a05:620a:2405:b0:69f:2238:989d with SMTP id d5-20020a05620a240500b0069f2238989dmr1473080qkn.318.1650648063021; Fri, 22 Apr 2022 10:21:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650648063; cv=none; d=google.com; s=arc-20160816; b=sZ7GFKAoYQ2u+Wn0sMh2rZ4MJq/EOzsDzZJHXFqYFm+PDpYN1/on0oH0hupYCG5nYJ N+3G3tX4hNHOKe0RpqTDvjB27vyqM2OaEovxKjVcE01TyBzqUBrA8p24HFwf3j+8FvIh Nn2L3ab/mxnkDfMOxKPHkAQgwZXmlZP9hReKEBcXoYqb0+uj41sOTUwn7WVBxcy/K2jF Omr/rCuq7Nx4xVVOL3DP4eoh80mxMT2Cue/pe2BxIQG3uV6Cca5EdYRyg90Q6W89Lsk6 Jx+WwW4XzNz3nBLQAt6L+qq1m+xKkiuYR/qpg/QYF3RhXpt+3BGCzO/czpGye5gsEJDa U3Rg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xcpq8OTysx50Lw5Wv3QQ4NLDXZZZLcnn9tCqlnHYPYo=; b=gpZUbi7eM0cD0DamG2bvmtG+Wyu8Dn0u0YtfPOgsQwc0J2e+8FNoPMxHIRU0vOrwoI YjOkRyfrT+oQTpF6Uy9k2vIDoWuFMQ/JZg5TrnLcF30oc7BaIxR3NReS9aPOBIAhIMFm /WNQgAXpeNDZ4J5aSgxhovcwOtRxLsmbpzQMFfe+MIiqSvcZeSzgloGtTlJFBKsbYhJA owd3uZsp1v7oGb5+f7TVp3VZYrjPujpwk+HD6o5B4m4SuZzHOQLXX3KFXYuThm/jxkFB 4VDKcX/A4lZ/0XPS51/9tA6+r2N4CIrksCEWL+GXvGbVwr/77c2yR9QO55sf6/VhYq+B Ma1g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KhPam7lA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 22/68] target/nios2: Split control registers away from general registers Date: Fri, 22 Apr 2022 09:51:52 -0700 Message-Id: <20220422165238.1971496-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Place the control registers into their own array, env->ctrl[]. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-23-richard.henderson@linaro.org> --- target/nios2/cpu.h | 43 ++++++++-------- target/nios2/cpu.c | 19 +++---- target/nios2/helper.c | 106 +++++++++++++++++++-------------------- target/nios2/mmu.c | 26 +++++----- target/nios2/op_helper.c | 2 +- target/nios2/translate.c | 35 +++++++------ 6 files changed, 118 insertions(+), 113 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 6bd8367eb8..68ff8033b6 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -59,9 +59,6 @@ struct Nios2CPUClass { #define NUM_GP_REGS 32 #define NUM_CR_REGS 32 -/* GP regs + CR regs */ -#define NUM_CORE_REGS (NUM_GP_REGS + NUM_CR_REGS) - /* General purpose register aliases */ #define R_ZERO 0 #define R_AT 1 @@ -81,8 +78,7 @@ struct Nios2CPUClass { #define R_RA 31 /* Control register aliases */ -#define CR_BASE NUM_GP_REGS -#define CR_STATUS (CR_BASE + 0) +#define CR_STATUS 0 #define CR_STATUS_PIE (1 << 0) #define CR_STATUS_U (1 << 1) #define CR_STATUS_EH (1 << 2) @@ -92,19 +88,19 @@ struct Nios2CPUClass { #define CR_STATUS_PRS (63 << 16) #define CR_STATUS_NMI (1 << 22) #define CR_STATUS_RSIE (1 << 23) -#define CR_ESTATUS (CR_BASE + 1) -#define CR_BSTATUS (CR_BASE + 2) -#define CR_IENABLE (CR_BASE + 3) -#define CR_IPENDING (CR_BASE + 4) -#define CR_CPUID (CR_BASE + 5) -#define CR_CTL6 (CR_BASE + 6) -#define CR_EXCEPTION (CR_BASE + 7) -#define CR_PTEADDR (CR_BASE + 8) +#define CR_ESTATUS 1 +#define CR_BSTATUS 2 +#define CR_IENABLE 3 +#define CR_IPENDING 4 +#define CR_CPUID 5 +#define CR_CTL6 6 +#define CR_EXCEPTION 7 +#define CR_PTEADDR 8 #define CR_PTEADDR_PTBASE_SHIFT 22 #define CR_PTEADDR_PTBASE_MASK (0x3FF << CR_PTEADDR_PTBASE_SHIFT) #define CR_PTEADDR_VPN_SHIFT 2 #define CR_PTEADDR_VPN_MASK (0xFFFFF << CR_PTEADDR_VPN_SHIFT) -#define CR_TLBACC (CR_BASE + 9) +#define CR_TLBACC 9 #define CR_TLBACC_IGN_SHIFT 25 #define CR_TLBACC_IGN_MASK (0x7F << CR_TLBACC_IGN_SHIFT) #define CR_TLBACC_C (1 << 24) @@ -113,7 +109,7 @@ struct Nios2CPUClass { #define CR_TLBACC_X (1 << 21) #define CR_TLBACC_G (1 << 20) #define CR_TLBACC_PFN_MASK 0x000FFFFF -#define CR_TLBMISC (CR_BASE + 10) +#define CR_TLBMISC 10 #define CR_TLBMISC_WAY_SHIFT 20 #define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT) #define CR_TLBMISC_RD (1 << 19) @@ -124,11 +120,11 @@ struct Nios2CPUClass { #define CR_TLBMISC_BAD (1 << 2) #define CR_TLBMISC_PERM (1 << 1) #define CR_TLBMISC_D (1 << 0) -#define CR_ENCINJ (CR_BASE + 11) -#define CR_BADADDR (CR_BASE + 12) -#define CR_CONFIG (CR_BASE + 13) -#define CR_MPUBASE (CR_BASE + 14) -#define CR_MPUACC (CR_BASE + 15) +#define CR_ENCINJ 11 +#define CR_BADADDR 12 +#define CR_CONFIG 13 +#define CR_MPUBASE 14 +#define CR_MPUACC 15 /* Exceptions */ #define EXCP_BREAK 0x1000 @@ -154,7 +150,8 @@ struct Nios2CPUClass { #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 struct CPUArchState { - uint32_t regs[NUM_CORE_REGS]; + uint32_t regs[NUM_GP_REGS]; + uint32_t ctrl[NUM_CR_REGS]; uint32_t pc; #if !defined(CONFIG_USER_ONLY) @@ -212,7 +209,7 @@ void do_nios2_semihosting(CPUNios2State *env); static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch) { - return (env->regs[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX : + return (env->ctrl[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX : MMU_SUPERVISOR_IDX; } @@ -232,7 +229,7 @@ static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *pc, { *pc = env->pc; *cs_base = 0; - *flags = (env->regs[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U)); + *flags = env->ctrl[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U); } #endif /* NIOS2_CPU_H */ diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index dc1551241e..fce16a2e77 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -48,14 +48,15 @@ static void nios2_cpu_reset(DeviceState *dev) ncc->parent_reset(dev); - memset(env->regs, 0, sizeof(uint32_t) * NUM_CORE_REGS); + memset(env->regs, 0, sizeof(env->regs)); + memset(env->ctrl, 0, sizeof(env->ctrl)); env->pc = cpu->reset_addr; #if defined(CONFIG_USER_ONLY) /* Start in user mode with interrupts enabled. */ - env->regs[CR_STATUS] = CR_STATUS_U | CR_STATUS_PIE; + env->ctrl[CR_STATUS] = CR_STATUS_U | CR_STATUS_PIE; #else - env->regs[CR_STATUS] = 0; + env->ctrl[CR_STATUS] = 0; #endif } @@ -66,9 +67,9 @@ static void nios2_cpu_set_irq(void *opaque, int irq, int level) CPUNios2State *env = &cpu->env; CPUState *cs = CPU(cpu); - env->regs[CR_IPENDING] = deposit32(env->regs[CR_IPENDING], irq, 1, !!level); + env->ctrl[CR_IPENDING] = deposit32(env->ctrl[CR_IPENDING], irq, 1, !!level); - if (env->regs[CR_IPENDING]) { + if (env->ctrl[CR_IPENDING]) { cpu_interrupt(cs, CPU_INTERRUPT_HARD); } else { cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); @@ -126,8 +127,8 @@ static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request) CPUNios2State *env = &cpu->env; if ((interrupt_request & CPU_INTERRUPT_HARD) && - (env->regs[CR_STATUS] & CR_STATUS_PIE) && - (env->regs[CR_IPENDING] & env->regs[CR_IENABLE])) { + (env->ctrl[CR_STATUS] & CR_STATUS_PIE) && + (env->ctrl[CR_IPENDING] & env->ctrl[CR_IENABLE])) { cs->exception_index = EXCP_IRQ; nios2_cpu_do_interrupt(cs); return true; @@ -158,7 +159,7 @@ static int nios2_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) } else if (n == 32) { /* PC */ return gdb_get_reg32(mem_buf, env->pc); } else if (n < 49) { /* Status regs */ - return gdb_get_reg32(mem_buf, env->regs[n - 1]); + return gdb_get_reg32(mem_buf, env->ctrl[n - 33]); } /* Invalid regs */ @@ -180,7 +181,7 @@ static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) } else if (n == 32) { /* PC */ env->pc = ldl_p(mem_buf); } else if (n < 49) { /* Status regs */ - env->regs[n - 1] = ldl_p(mem_buf); + env->ctrl[n - 33] = ldl_p(mem_buf); } return 4; diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 34b3e18e37..2e5f5b8b54 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -36,38 +36,38 @@ void nios2_cpu_do_interrupt(CPUState *cs) switch (cs->exception_index) { case EXCP_IRQ: - assert(env->regs[CR_STATUS] & CR_STATUS_PIE); + assert(env->ctrl[CR_STATUS] & CR_STATUS_PIE); qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%x\n", env->pc); - env->regs[CR_ESTATUS] = env->regs[CR_STATUS]; - env->regs[CR_STATUS] |= CR_STATUS_IH; - env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); + env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS]; + env->ctrl[CR_STATUS] |= CR_STATUS_IH; + env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->regs[CR_EXCEPTION] &= ~(0x1F << 2); - env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2); + env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; env->regs[R_EA] = env->pc + 4; env->pc = cpu->exception_addr; break; case EXCP_TLBD: - if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) { + if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=%x\n", env->pc); /* Fast TLB miss */ /* Variation from the spec. Table 3-35 of the cpu reference shows * estatus not being changed for TLB miss but this appears to * be incorrect. */ - env->regs[CR_ESTATUS] = env->regs[CR_STATUS]; - env->regs[CR_STATUS] |= CR_STATUS_EH; - env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); + env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS]; + env->ctrl[CR_STATUS] |= CR_STATUS_EH; + env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->regs[CR_EXCEPTION] &= ~(0x1F << 2); - env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2); + env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; - env->regs[CR_TLBMISC] &= ~CR_TLBMISC_DBL; - env->regs[CR_TLBMISC] |= CR_TLBMISC_WR; + env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_DBL; + env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WR; env->regs[R_EA] = env->pc + 4; env->pc = cpu->fast_tlb_miss_addr; @@ -75,13 +75,13 @@ void nios2_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=%x\n", env->pc); /* Double TLB miss */ - env->regs[CR_STATUS] |= CR_STATUS_EH; - env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); + env->ctrl[CR_STATUS] |= CR_STATUS_EH; + env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->regs[CR_EXCEPTION] &= ~(0x1F << 2); - env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2); + env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; - env->regs[CR_TLBMISC] |= CR_TLBMISC_DBL; + env->ctrl[CR_TLBMISC] |= CR_TLBMISC_DBL; env->pc = cpu->exception_addr; } @@ -92,15 +92,15 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_TLBX: qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=%x\n", env->pc); - env->regs[CR_ESTATUS] = env->regs[CR_STATUS]; - env->regs[CR_STATUS] |= CR_STATUS_EH; - env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); + env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS]; + env->ctrl[CR_STATUS] |= CR_STATUS_EH; + env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->regs[CR_EXCEPTION] &= ~(0x1F << 2); - env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2); + env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; - if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) { - env->regs[CR_TLBMISC] |= CR_TLBMISC_WR; + if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { + env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WR; } env->regs[R_EA] = env->pc + 4; @@ -112,16 +112,16 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_SUPERD: qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=%x\n", env->pc); - if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) { - env->regs[CR_ESTATUS] = env->regs[CR_STATUS]; + if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { + env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS]; env->regs[R_EA] = env->pc + 4; } - env->regs[CR_STATUS] |= CR_STATUS_EH; - env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); + env->ctrl[CR_STATUS] |= CR_STATUS_EH; + env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->regs[CR_EXCEPTION] &= ~(0x1F << 2); - env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2); + env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; env->pc = cpu->exception_addr; break; @@ -130,16 +130,16 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_TRAP: qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=%x\n", env->pc); - if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) { - env->regs[CR_ESTATUS] = env->regs[CR_STATUS]; + if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { + env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS]; env->regs[R_EA] = env->pc + 4; } - env->regs[CR_STATUS] |= CR_STATUS_EH; - env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); + env->ctrl[CR_STATUS] |= CR_STATUS_EH; + env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->regs[CR_EXCEPTION] &= ~(0x1F << 2); - env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2); + env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; env->pc = cpu->exception_addr; break; @@ -155,16 +155,16 @@ void nios2_cpu_do_interrupt(CPUState *cs) break; } - if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) { - env->regs[CR_BSTATUS] = env->regs[CR_STATUS]; + if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { + env->ctrl[CR_BSTATUS] = env->ctrl[CR_STATUS]; env->regs[R_BA] = env->pc + 4; } - env->regs[CR_STATUS] |= CR_STATUS_EH; - env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); + env->ctrl[CR_STATUS] |= CR_STATUS_EH; + env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->regs[CR_EXCEPTION] &= ~(0x1F << 2); - env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2); + env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; env->pc = cpu->exception_addr; break; @@ -207,8 +207,8 @@ void nios2_cpu_do_unaligned_access(CPUState *cs, vaddr addr, Nios2CPU *cpu = NIOS2_CPU(cs); CPUNios2State *env = &cpu->env; - env->regs[CR_BADADDR] = addr; - env->regs[CR_EXCEPTION] = EXCP_UNALIGN << 2; + env->ctrl[CR_BADADDR] = addr; + env->ctrl[CR_EXCEPTION] = EXCP_UNALIGN << 2; helper_raise_exception(env, EXCP_UNALIGN); } @@ -246,7 +246,7 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, return false; } cs->exception_index = EXCP_SUPERA; - env->regs[CR_BADADDR] = address; + env->ctrl[CR_BADADDR] = address; cpu_loop_exit_restore(cs, retaddr); } } @@ -275,15 +275,15 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } if (access_type == MMU_INST_FETCH) { - env->regs[CR_TLBMISC] &= ~CR_TLBMISC_D; + env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_D; } else { - env->regs[CR_TLBMISC] |= CR_TLBMISC_D; + env->ctrl[CR_TLBMISC] |= CR_TLBMISC_D; } - env->regs[CR_PTEADDR] &= CR_PTEADDR_PTBASE_MASK; - env->regs[CR_PTEADDR] |= (address >> 10) & CR_PTEADDR_VPN_MASK; - env->mmu.pteaddr_wr = env->regs[CR_PTEADDR]; + env->ctrl[CR_PTEADDR] &= CR_PTEADDR_PTBASE_MASK; + env->ctrl[CR_PTEADDR] |= (address >> 10) & CR_PTEADDR_VPN_MASK; + env->mmu.pteaddr_wr = env->ctrl[CR_PTEADDR]; cs->exception_index = excp; - env->regs[CR_BADADDR] = address; + env->ctrl[CR_BADADDR] = address; cpu_loop_exit_restore(cs, retaddr); } diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 4daab2a7ab..95900724e8 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -95,8 +95,8 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v) v & CR_TLBACC_PFN_MASK); /* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */ - if (env->regs[CR_TLBMISC] & CR_TLBMISC_WR) { - int way = (env->regs[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT); + if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WR) { + int way = (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT); int vpn = (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2; int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; int g = (v & CR_TLBACC_G) ? 1 : 0; @@ -117,8 +117,8 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v) entry->data = newData; } /* Auto-increment tlbmisc.WAY */ - env->regs[CR_TLBMISC] = - (env->regs[CR_TLBMISC] & ~CR_TLBMISC_WAY_MASK) | + env->ctrl[CR_TLBMISC] = + (env->ctrl[CR_TLBMISC] & ~CR_TLBMISC_WAY_MASK) | (((way + 1) & (cpu->tlb_num_ways - 1)) << CR_TLBMISC_WAY_SHIFT); } @@ -153,17 +153,17 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v) &env->mmu.tlb[(way * cpu->tlb_num_ways) + (vpn & env->mmu.tlb_entry_mask)]; - env->regs[CR_TLBACC] &= CR_TLBACC_IGN_MASK; - env->regs[CR_TLBACC] |= entry->data; - env->regs[CR_TLBACC] |= (entry->tag & (1 << 11)) ? CR_TLBACC_G : 0; - env->regs[CR_TLBMISC] = + env->ctrl[CR_TLBACC] &= CR_TLBACC_IGN_MASK; + env->ctrl[CR_TLBACC] |= entry->data; + env->ctrl[CR_TLBACC] |= (entry->tag & (1 << 11)) ? CR_TLBACC_G : 0; + env->ctrl[CR_TLBMISC] = (v & ~CR_TLBMISC_PID_MASK) | ((entry->tag & ((1 << cpu->pid_num_bits) - 1)) << CR_TLBMISC_PID_SHIFT); - env->regs[CR_PTEADDR] &= ~CR_PTEADDR_VPN_MASK; - env->regs[CR_PTEADDR] |= (entry->tag >> 12) << CR_PTEADDR_VPN_SHIFT; + env->ctrl[CR_PTEADDR] &= ~CR_PTEADDR_VPN_MASK; + env->ctrl[CR_PTEADDR] |= (entry->tag >> 12) << CR_PTEADDR_VPN_SHIFT; } else { - env->regs[CR_TLBMISC] = v; + env->ctrl[CR_TLBMISC] = v; } env->mmu.tlbmisc_wr = v; @@ -175,8 +175,8 @@ void helper_mmu_write_pteaddr(CPUNios2State *env, uint32_t v) (v & CR_PTEADDR_VPN_MASK) >> CR_PTEADDR_VPN_SHIFT); /* Writes to PTEADDR don't change the read-back VPN value */ - env->regs[CR_PTEADDR] = (v & ~CR_PTEADDR_VPN_MASK) | - (env->regs[CR_PTEADDR] & CR_PTEADDR_VPN_MASK); + env->ctrl[CR_PTEADDR] = ((v & ~CR_PTEADDR_VPN_MASK) | + (env->ctrl[CR_PTEADDR] & CR_PTEADDR_VPN_MASK)); env->mmu.pteaddr_wr = v; } diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index ee5ad8b23f..08ed3b4598 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -34,7 +34,7 @@ void helper_raise_exception(CPUNios2State *env, uint32_t index) #ifndef CONFIG_USER_ONLY void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc) { - env->regs[CR_STATUS] = new_status; + env->ctrl[CR_STATUS] = new_status; env->pc = new_pc; cpu_loop_exit(env_cpu(env)); } diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 6c739bfa5e..308da8057c 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -395,7 +395,7 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags) g_assert_not_reached(); #else TCGv tmp = tcg_temp_new(); - tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, regs[CR_ESTATUS])); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_ESTATUS])); gen_helper_eret(cpu_env, tmp, cpu_R[R_EA]); tcg_temp_free(tmp); @@ -425,7 +425,7 @@ static void bret(DisasContext *dc, uint32_t code, uint32_t flags) g_assert_not_reached(); #else TCGv tmp = tcg_temp_new(); - tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, regs[CR_BSTATUS])); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_BSTATUS])); gen_helper_eret(cpu_env, tmp, cpu_R[R_BA]); tcg_temp_free(tmp); @@ -481,7 +481,7 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) return; } - switch (instr.imm5 + CR_BASE) { + switch (instr.imm5) { case CR_IPENDING: /* * The value of the ipending register is synthetic. @@ -493,17 +493,15 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) */ t1 = tcg_temp_new(); t2 = tcg_temp_new(); - tcg_gen_ld_tl(t1, cpu_env, - offsetof(CPUNios2State, regs[CR_IPENDING])); - tcg_gen_ld_tl(t2, cpu_env, - offsetof(CPUNios2State, regs[CR_IENABLE])); + tcg_gen_ld_tl(t1, cpu_env, offsetof(CPUNios2State, ctrl[CR_IPENDING])); + tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUNios2State, ctrl[CR_IENABLE])); tcg_gen_and_tl(cpu_R[instr.c], t1, t2); tcg_temp_free(t1); tcg_temp_free(t2); break; default: tcg_gen_ld_tl(cpu_R[instr.c], cpu_env, - offsetof(CPUNios2State, regs[instr.imm5 + CR_BASE])); + offsetof(CPUNios2State, ctrl[instr.imm5])); break; } } @@ -521,7 +519,7 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags) R_TYPE(instr, code); TCGv v = load_gpr(dc, instr.a); - switch (instr.imm5 + CR_BASE) { + switch (instr.imm5) { case CR_PTEADDR: gen_helper_mmu_write_pteaddr(cpu_env, v); break; @@ -541,7 +539,7 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags) /* fall through */ default: tcg_gen_st_tl(v, cpu_env, - offsetof(CPUNios2State, regs[instr.imm5 + CR_BASE])); + offsetof(CPUNios2State, ctrl[instr.imm5])); break; } #endif @@ -774,7 +772,7 @@ illegal_op: t_gen_helper_raise_exception(dc, EXCP_ILLEGAL); } -static const char * const regnames[NUM_CORE_REGS] = { +static const char * const gr_regnames[NUM_GP_REGS] = { "zero", "at", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", @@ -783,6 +781,9 @@ static const char * const regnames[NUM_CORE_REGS] = { "r20", "r21", "r22", "r23", "et", "bt", "gp", "sp", "fp", "ea", "ba", "ra", +}; + +static const char * const cr_regnames[NUM_CR_REGS] = { "status", "estatus", "bstatus", "ienable", "ipending", "cpuid", "reserved0", "exception", "pteaddr", "tlbacc", "tlbmisc", "reserved1", @@ -910,8 +911,14 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc)); - for (i = 0; i < NUM_CORE_REGS; i++) { - qemu_fprintf(f, "%9s=%8.8x ", regnames[i], env->regs[i]); + for (i = 0; i < NUM_GP_REGS; i++) { + qemu_fprintf(f, "%9s=%8.8x ", gr_regnames[i], env->regs[i]); + if ((i + 1) % 4 == 0) { + qemu_fprintf(f, "\n"); + } + } + for (i = 0; i < NUM_CR_REGS; i++) { + qemu_fprintf(f, "%9s=%8.8x ", cr_regnames[i], env->ctrl[i]); if ((i + 1) % 4 == 0) { qemu_fprintf(f, "\n"); } @@ -932,7 +939,7 @@ void nios2_tcg_init(void) for (i = 0; i < NUM_GP_REGS; i++) { cpu_R[i] = tcg_global_mem_new(cpu_env, offsetof(CPUNios2State, regs[i]), - regnames[i]); + gr_regnames[i]); } cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPUNios2State, pc), "pc"); From patchwork Fri Apr 22 16:51:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564867 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp679489map; Fri, 22 Apr 2022 10:22:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwW7bzzq3tC4n5yeYCfVjZ/ARQDBOwhBKzazZqNQTwdX0IiOVBWDFMF2F+uE2U7e79D2arW X-Received: by 2002:a37:a196:0:b0:69e:b207:16ee with SMTP id k144-20020a37a196000000b0069eb20716eemr3357422qke.321.1650648153378; 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 23/68] target/nios2: Clean up nios2_cpu_dump_state Date: Fri, 22 Apr 2022 09:51:53 -0700 Message-Id: <20220422165238.1971496-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Do not print control registers for user-only mode. Rename reserved control registers to "resN", where N is the control register index. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-24-richard.henderson@linaro.org> --- target/nios2/translate.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 308da8057c..fc49a7101f 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -783,16 +783,18 @@ static const char * const gr_regnames[NUM_GP_REGS] = { "fp", "ea", "ba", "ra", }; +#ifndef CONFIG_USER_ONLY static const char * const cr_regnames[NUM_CR_REGS] = { "status", "estatus", "bstatus", "ienable", - "ipending", "cpuid", "reserved0", "exception", + "ipending", "cpuid", "res6", "exception", "pteaddr", "tlbacc", "tlbmisc", "reserved1", "badaddr", "config", "mpubase", "mpuacc", - "reserved2", "reserved3", "reserved4", "reserved5", - "reserved6", "reserved7", "reserved8", "reserved9", - "reserved10", "reserved11", "reserved12", "reserved13", - "reserved14", "reserved15", "reserved16", "reserved17", + "res16", "res17", "res18", "res19", + "res20", "res21", "res22", "res23", + "res24", "res25", "res26", "res27", + "res28", "res29", "res30", "res31", }; +#endif #include "exec/gen-icount.h" @@ -905,10 +907,6 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags) CPUNios2State *env = &cpu->env; int i; - if (!env) { - return; - } - qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc)); for (i = 0; i < NUM_GP_REGS; i++) { @@ -917,13 +915,14 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "\n"); } } + +#if !defined(CONFIG_USER_ONLY) for (i = 0; i < NUM_CR_REGS; i++) { qemu_fprintf(f, "%9s=%8.8x ", cr_regnames[i], env->ctrl[i]); if ((i + 1) % 4 == 0) { qemu_fprintf(f, "\n"); } } -#if !defined(CONFIG_USER_ONLY) qemu_fprintf(f, " mmu write: VPN=%05X PID %02X TLBACC %08X\n", env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK, (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4, From patchwork Fri Apr 22 16:51:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564870 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp681122map; Fri, 22 Apr 2022 10:24:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwUooqgpt4N97k+P/k0BFSGAaZxvGRawbxxlWNFJQVw3G1iBWeoefwL0MTqd6JQmrVaj6Xp X-Received: by 2002:a05:622a:144c:b0:2f3:4799:164b with SMTP id v12-20020a05622a144c00b002f34799164bmr4045074qtx.438.1650648298434; Fri, 22 Apr 2022 10:24:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650648298; cv=none; d=google.com; s=arc-20160816; b=bNDqMpebrMwT501l0z4f5e+d67Yl1ZmfylIHN8GH4EPyWCB0gl6EohKIXIGEJeGDTF V8urtUt7Q7AaC1OgLrQyisZmYsuN9SuICzAEYGKdUdC4PTb/QVEwyAuNePasGD9NxZLp P2rw0hYqxiu0Oa9+lZV3Qy/0aFKgT+SDXpUZadaVP5BSDTwNuZLtmOeHTqjgvyN0VTeo OcKpyEx0rbOqUkplzPpOIcDicPdvlHD65a6Lmn1L84/AKk3wqo7m1zuXeWmuZ6xyrYVJ DQb4JbCxp4JHo/2iE2GxRzeChkbxy5Bzfb/3riVrSmXK2tD63Kel1jj3IZvA7ovV7HXa dmCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=E+4Qd4E9HIFHi1BwjZ85dNcwW/a/s3TNOGQFzvuAjJM=; b=hLGW78FYjIK6WL+GGBXg8KiFyE7YYFxYtch95qtraG8zPxQUIOdznogY8kO013qojh r3piMvNPMcr/ni6KFdMpMeZntFvNvdC3QfUMcGYfRxWzZwTXo5NzEauHyWuEbUxkEfqw MAzCEvENspe36dnSaGerPO5xHH4EnfYwNTjaq6Sq0b/a1t29f/l1qx4fXm2xRIu4cauc 59qit5nFLOIv9ft2t5eIf1xR9xsxMpXFLNSGt6ZqYFRbj1I6t1TQ/2puxJhTasyqZJHO jUiNCFfIJBuwQqN7GYEBlVG/CIKpSKkWsogtedcu55IrSdzh+jVJ+L/tosnEELRp+pcO iNgg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=R6u2YNiX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 24/68] target/nios2: Use hw/registerfields.h for CR_STATUS fields Date: Fri, 22 Apr 2022 09:51:54 -0700 Message-Id: <20220422165238.1971496-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add all fields; retain the helper macros for single bit fields. So far there are no uses of the multi-bit status fields. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-25-richard.henderson@linaro.org> --- target/nios2/cpu.h | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 68ff8033b6..562dca8195 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -23,6 +23,7 @@ #include "exec/cpu-defs.h" #include "hw/core/cpu.h" +#include "hw/registerfields.h" #include "qom/object.h" typedef struct CPUArchState CPUNios2State; @@ -79,15 +80,24 @@ struct Nios2CPUClass { /* Control register aliases */ #define CR_STATUS 0 -#define CR_STATUS_PIE (1 << 0) -#define CR_STATUS_U (1 << 1) -#define CR_STATUS_EH (1 << 2) -#define CR_STATUS_IH (1 << 3) -#define CR_STATUS_IL (63 << 4) -#define CR_STATUS_CRS (63 << 10) -#define CR_STATUS_PRS (63 << 16) -#define CR_STATUS_NMI (1 << 22) -#define CR_STATUS_RSIE (1 << 23) + +FIELD(CR_STATUS, PIE, 0, 1) +FIELD(CR_STATUS, U, 1, 1) +FIELD(CR_STATUS, EH, 2, 1) +FIELD(CR_STATUS, IH, 3, 1) +FIELD(CR_STATUS, IL, 4, 6) +FIELD(CR_STATUS, CRS, 10, 6) +FIELD(CR_STATUS, PRS, 16, 6) +FIELD(CR_STATUS, NMI, 22, 1) +FIELD(CR_STATUS, RSIE, 23, 1) + +#define CR_STATUS_PIE R_CR_STATUS_PIE_MASK +#define CR_STATUS_U R_CR_STATUS_U_MASK +#define CR_STATUS_EH R_CR_STATUS_EH_MASK +#define CR_STATUS_IH R_CR_STATUS_IH_MASK +#define CR_STATUS_NMI R_CR_STATUS_NMI_MASK +#define CR_STATUS_RSIE R_CR_STATUS_RSIE_MASK + #define CR_ESTATUS 1 #define CR_BSTATUS 2 #define CR_IENABLE 3 From patchwork Fri Apr 22 16:51:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564857 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp670573map; Fri, 22 Apr 2022 10:12:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzYVDwEoTZtkNsxiIfHnq83iGLuBiVtlFU7n/+RxyylaTTrOT0ZBwoB93SDv/kj/wME+C4R X-Received: by 2002:ac8:5d89:0:b0:2e2:74e:f1bb with SMTP id d9-20020ac85d89000000b002e2074ef1bbmr4005218qtx.219.1650647525896; Fri, 22 Apr 2022 10:12:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650647525; cv=none; d=google.com; s=arc-20160816; b=eX7ZTRwUUMGpMztraz8xM8HvlVczFV2Ceq7Sw/BkSdI2Oa88Y73yr+smql7pWDM98w na+t/a/pk+L7nZGFMlgx34+zzoG3RsNr1+htNCKeqdfcpm+Px5pAWl+aBpWv2IMChblZ TRIooQQZHGoq66w90MvFRsgMF5fJ90V0SITWd2IWvvZ9r3X8AVlG+rfvgZhWJgujfhiW UzE9kZBdrHdJ/UtwzZzAX8Q7MamWhX54CsSrgHI3XHQvK7PVe/bdRX+nFlwXaIqaH6HI sdeTmUgCY/WAHOnYYo3U8EndlaCw5Ql6S1LKPx4k1RJ+2n08/4/cTegniVUjGeRsEMWR thBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=7/HOE2e7ynTg66W4PjhgIMT/dmI++JIVfa+aDY4ajpE=; b=gzvq8oY4OWc4IaqTg4uF6FtU94ER4GJBGi6pAJ9iKH9f78Ko5lt1l1G49XpAqXJ9z4 VySm961ABxQB0E15laVbKzC9f999Pgj6waX6R4TvJ4jd5QvrYn969B0MwQETT1pF40ID jS5vWR2ykUgAz8mYEXaeTPGOTmCm6+y3vqVjMjE7gFttj3+vlpDwUv3CItpJn++8GcIO 2P4NU24LZgSJ5cQyAe0xPWGj8Wz6FLUXDZDvHg3pEfCU52TrDqM7JzwHzrrqq28Pi3NC kD4OR272llwRyoDLzoCLCDnYZ9udKVWm02sKCPdIGTcDtYUItqojXngBmCmrJK0LCsk/ nrfg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ssZXYMh1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 25/68] target/nios2: Use hw/registerfields.h for CR_EXCEPTION fields Date: Fri, 22 Apr 2022 09:51:55 -0700 Message-Id: <20220422165238.1971496-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use FIELD_DP32 instead of manual shifting and masking. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-26-richard.henderson@linaro.org> --- target/nios2/cpu.h | 4 ++++ target/nios2/helper.c | 37 ++++++++++++++++++++++--------------- 2 files changed, 26 insertions(+), 15 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 562dca8195..f8cd5dc218 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -105,6 +105,10 @@ FIELD(CR_STATUS, RSIE, 23, 1) #define CR_CPUID 5 #define CR_CTL6 6 #define CR_EXCEPTION 7 + +FIELD(CR_EXCEPTION, CAUSE, 2, 5) +FIELD(CR_EXCEPTION, ECCFTL, 31, 1) + #define CR_PTEADDR 8 #define CR_PTEADDR_PTBASE_SHIFT 22 #define CR_PTEADDR_PTBASE_MASK (0x3FF << CR_PTEADDR_PTBASE_SHIFT) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 2e5f5b8b54..b30740824c 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -44,8 +44,9 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->ctrl[CR_STATUS] |= CR_STATUS_IH; env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2); - env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], + CR_EXCEPTION, CAUSE, + cs->exception_index); env->regs[R_EA] = env->pc + 4; env->pc = cpu->exception_addr; @@ -63,8 +64,9 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->ctrl[CR_STATUS] |= CR_STATUS_EH; env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2); - env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], + CR_EXCEPTION, CAUSE, + cs->exception_index); env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_DBL; env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WR; @@ -78,8 +80,9 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->ctrl[CR_STATUS] |= CR_STATUS_EH; env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2); - env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], + CR_EXCEPTION, CAUSE, + cs->exception_index); env->ctrl[CR_TLBMISC] |= CR_TLBMISC_DBL; @@ -96,8 +99,9 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->ctrl[CR_STATUS] |= CR_STATUS_EH; env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2); - env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], + CR_EXCEPTION, CAUSE, + cs->exception_index); if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WR; @@ -120,8 +124,9 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->ctrl[CR_STATUS] |= CR_STATUS_EH; env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2); - env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], + CR_EXCEPTION, CAUSE, + cs->exception_index); env->pc = cpu->exception_addr; break; @@ -138,8 +143,9 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->ctrl[CR_STATUS] |= CR_STATUS_EH; env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2); - env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], + CR_EXCEPTION, CAUSE, + cs->exception_index); env->pc = cpu->exception_addr; break; @@ -163,8 +169,9 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->ctrl[CR_STATUS] |= CR_STATUS_EH; env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2); - env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], + CR_EXCEPTION, CAUSE, + cs->exception_index); env->pc = cpu->exception_addr; break; @@ -208,7 +215,7 @@ void nios2_cpu_do_unaligned_access(CPUState *cs, vaddr addr, CPUNios2State *env = &cpu->env; env->ctrl[CR_BADADDR] = addr; - env->ctrl[CR_EXCEPTION] = EXCP_UNALIGN << 2; + env->ctrl[CR_EXCEPTION] = FIELD_DP32(0, CR_EXCEPTION, CAUSE, EXCP_UNALIGN); helper_raise_exception(env, EXCP_UNALIGN); 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 26/68] target/nios2: Use hw/registerfields.h for CR_TLBADDR fields Date: Fri, 22 Apr 2022 09:51:56 -0700 Message-Id: <20220422165238.1971496-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use FIELD_EX32 and FIELD_DP32 instead of manual manipulation of the fields. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-27-richard.henderson@linaro.org> --- target/nios2/cpu.h | 8 ++++---- target/nios2/helper.c | 4 ++-- target/nios2/mmu.c | 17 +++++++++-------- target/nios2/translate.c | 2 +- 4 files changed, 16 insertions(+), 15 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index f8cd5dc218..a6811ff7ea 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -110,10 +110,10 @@ FIELD(CR_EXCEPTION, CAUSE, 2, 5) FIELD(CR_EXCEPTION, ECCFTL, 31, 1) #define CR_PTEADDR 8 -#define CR_PTEADDR_PTBASE_SHIFT 22 -#define CR_PTEADDR_PTBASE_MASK (0x3FF << CR_PTEADDR_PTBASE_SHIFT) -#define CR_PTEADDR_VPN_SHIFT 2 -#define CR_PTEADDR_VPN_MASK (0xFFFFF << CR_PTEADDR_VPN_SHIFT) + +FIELD(CR_PTEADDR, VPN, 2, 20) +FIELD(CR_PTEADDR, PTBASE, 22, 10) + #define CR_TLBACC 9 #define CR_TLBACC_IGN_SHIFT 25 #define CR_TLBACC_IGN_MASK (0x7F << CR_TLBACC_IGN_SHIFT) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index b30740824c..c2d0afe1b6 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -286,8 +286,8 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } else { env->ctrl[CR_TLBMISC] |= CR_TLBMISC_D; } - env->ctrl[CR_PTEADDR] &= CR_PTEADDR_PTBASE_MASK; - env->ctrl[CR_PTEADDR] |= (address >> 10) & CR_PTEADDR_VPN_MASK; + env->ctrl[CR_PTEADDR] = FIELD_DP32(env->ctrl[CR_PTEADDR], CR_PTEADDR, VPN, + address >> TARGET_PAGE_BITS); env->mmu.pteaddr_wr = env->ctrl[CR_PTEADDR]; cs->exception_index = excp; diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 95900724e8..75afc56daf 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -97,7 +97,7 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v) /* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */ if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WR) { int way = (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT); - int vpn = (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2; + int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; int g = (v & CR_TLBACC_G) ? 1 : 0; int valid = ((vpn & CR_TLBACC_PFN_MASK) < 0xC0000) ? 1 : 0; @@ -148,7 +148,7 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v) /* if tlbmisc.RD == 1 then trigger a TLB read on writes to TLBMISC */ if (v & CR_TLBMISC_RD) { int way = (v >> CR_TLBMISC_WAY_SHIFT); - int vpn = (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2; + int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); Nios2TLBEntry *entry = &env->mmu.tlb[(way * cpu->tlb_num_ways) + (vpn & env->mmu.tlb_entry_mask)]; @@ -160,8 +160,9 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v) (v & ~CR_TLBMISC_PID_MASK) | ((entry->tag & ((1 << cpu->pid_num_bits) - 1)) << CR_TLBMISC_PID_SHIFT); - env->ctrl[CR_PTEADDR] &= ~CR_PTEADDR_VPN_MASK; - env->ctrl[CR_PTEADDR] |= (entry->tag >> 12) << CR_PTEADDR_VPN_SHIFT; + env->ctrl[CR_PTEADDR] = FIELD_DP32(env->ctrl[CR_PTEADDR], + CR_PTEADDR, VPN, + entry->tag >> TARGET_PAGE_BITS); } else { env->ctrl[CR_TLBMISC] = v; } @@ -171,12 +172,12 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v) void helper_mmu_write_pteaddr(CPUNios2State *env, uint32_t v) { - trace_nios2_mmu_write_pteaddr(v >> CR_PTEADDR_PTBASE_SHIFT, - (v & CR_PTEADDR_VPN_MASK) >> CR_PTEADDR_VPN_SHIFT); + trace_nios2_mmu_write_pteaddr(FIELD_EX32(v, CR_PTEADDR, PTBASE), + FIELD_EX32(v, CR_PTEADDR, VPN)); /* Writes to PTEADDR don't change the read-back VPN value */ - env->ctrl[CR_PTEADDR] = ((v & ~CR_PTEADDR_VPN_MASK) | - (env->ctrl[CR_PTEADDR] & CR_PTEADDR_VPN_MASK)); + env->ctrl[CR_PTEADDR] = ((v & ~R_CR_PTEADDR_VPN_MASK) | + (env->ctrl[CR_PTEADDR] & R_CR_PTEADDR_VPN_MASK)); env->mmu.pteaddr_wr = v; } diff --git a/target/nios2/translate.c b/target/nios2/translate.c index fc49a7101f..baa22c5101 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -924,7 +924,7 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags) } } qemu_fprintf(f, " mmu write: VPN=%05X PID %02X TLBACC %08X\n", - env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK, + env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK, (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4, env->mmu.tlbacc_wr); #endif From patchwork Fri Apr 22 16:51:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564844 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp660459map; Fri, 22 Apr 2022 10:01:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz6Vr/2PqyG6uzzmiO0hIJEsSRG3ZO54MLmqv0IRpNvRpzjOhvR3bPwKNnBvmflUpcb/2s/ X-Received: by 2002:a25:d354:0:b0:645:d617:560a with SMTP id e81-20020a25d354000000b00645d617560amr2956767ybf.247.1650646875948; Fri, 22 Apr 2022 10:01:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650646875; cv=none; d=google.com; s=arc-20160816; b=SV3vRVnRdPoWeS9JNOF8VZ7VHdkE0g0IkwoVl72IZKPVo7mJtk3OSCBzty94J+bULt Sh8xxLashJ4Qi6vGztHuM7tsYF2xVyyhXWplA9WaNnrPZGUIACAPKKlqsIZTXeaWMbTF anlzRuNbly6xsn0UBf4ifT54ENOYOjPRJRXzg/DUb8GW9V8zmJyjn3nQCWTc3QcfLCxX 9aNpBCTHW7b01TAdWfYQLjvwTtcAAWmk9A43XNCb0UDjemPxDYn8+Fqyh/5s5N32mhMS AVxEwLY9M8Thmfi0IMZ8TJ6t55wN6iLG4HIlHiCUVCVlg4EeNhV2osBhpSFGrUAnaCTy vGVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=JmB13VTyuzzFASmlJJ9jmm7vtSLnsoUw3SQpc47Yi90=; b=aJIEobI9o+T/PcRIebMW0Wog7z2vR29SzT6EKMBRqwzRhA02QHlUgJMj5xLj6czRsM 7Cb8Cqn3gf9nlQHlkUkRqfG8MvEIvIV6/l8FN1haTiwhtsWTnAzrtqiG/279rjrTTuqz OFB0+XZLpv0np0UBhY9AeWwr8e0zIlGlVixlxuYPxhKYLgNBGuNdknfFttZls+NUSiCB x5we7xqO557DZlejiXoAfeDyk5neHPwNOeHQs1n05IBSGmJX5tH0OfG1ntQxbESyKNgD d4F6SKPkuzCDxmQwSywRdvsvLI+KUX6DGjUfnsE8E0kuR9QxwJIsHDS0tHs345Vji9Fo Jazw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=D6JguGtI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 27/68] target/nios2: Use hw/registerfields.h for CR_TLBACC fields Date: Fri, 22 Apr 2022 09:51:57 -0700 Message-Id: <20220422165238.1971496-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Retain the helper macros for single bit fields as aliases to the longer R_*_MASK names. Use FIELD_EX32 and FIELD_DP32 instead of manually manipulating the fields. Since we're rewriting the references to CR_TLBACC_IGN_* anyway, we correct the name of this field to IG, which is its name in the official CPU documentation. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-28-richard.henderson@linaro.org> --- target/nios2/cpu.h | 23 +++++++++++++++-------- target/nios2/mmu.c | 16 ++++++++-------- 2 files changed, 23 insertions(+), 16 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index a6811ff7ea..bfa86edd97 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -115,14 +115,21 @@ FIELD(CR_PTEADDR, VPN, 2, 20) FIELD(CR_PTEADDR, PTBASE, 22, 10) #define CR_TLBACC 9 -#define CR_TLBACC_IGN_SHIFT 25 -#define CR_TLBACC_IGN_MASK (0x7F << CR_TLBACC_IGN_SHIFT) -#define CR_TLBACC_C (1 << 24) -#define CR_TLBACC_R (1 << 23) -#define CR_TLBACC_W (1 << 22) -#define CR_TLBACC_X (1 << 21) -#define CR_TLBACC_G (1 << 20) -#define CR_TLBACC_PFN_MASK 0x000FFFFF + +FIELD(CR_TLBACC, PFN, 0, 20) +FIELD(CR_TLBACC, G, 20, 1) +FIELD(CR_TLBACC, X, 21, 1) +FIELD(CR_TLBACC, W, 22, 1) +FIELD(CR_TLBACC, R, 23, 1) +FIELD(CR_TLBACC, C, 24, 1) +FIELD(CR_TLBACC, IG, 25, 7) + +#define CR_TLBACC_C R_CR_TLBACC_C_MASK +#define CR_TLBACC_R R_CR_TLBACC_R_MASK +#define CR_TLBACC_W R_CR_TLBACC_W_MASK +#define CR_TLBACC_X R_CR_TLBACC_X_MASK +#define CR_TLBACC_G R_CR_TLBACC_G_MASK + #define CR_TLBMISC 10 #define CR_TLBMISC_WAY_SHIFT 20 #define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT) diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 75afc56daf..826cd2afb4 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -49,7 +49,7 @@ unsigned int mmu_translate(CPUNios2State *env, } lu->vaddr = vaddr & TARGET_PAGE_MASK; - lu->paddr = (entry->data & CR_TLBACC_PFN_MASK) << TARGET_PAGE_BITS; + lu->paddr = FIELD_EX32(entry->data, CR_TLBACC, PFN) << TARGET_PAGE_BITS; lu->prot = ((entry->data & CR_TLBACC_R) ? PAGE_READ : 0) | ((entry->data & CR_TLBACC_W) ? PAGE_WRITE : 0) | ((entry->data & CR_TLBACC_X) ? PAGE_EXEC : 0); @@ -86,27 +86,27 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v) CPUState *cs = env_cpu(env); Nios2CPU *cpu = env_archcpu(env); - trace_nios2_mmu_write_tlbacc(v >> CR_TLBACC_IGN_SHIFT, + trace_nios2_mmu_write_tlbacc(FIELD_EX32(v, CR_TLBACC, IG), (v & CR_TLBACC_C) ? 'C' : '.', (v & CR_TLBACC_R) ? 'R' : '.', (v & CR_TLBACC_W) ? 'W' : '.', (v & CR_TLBACC_X) ? 'X' : '.', (v & CR_TLBACC_G) ? 'G' : '.', - v & CR_TLBACC_PFN_MASK); + FIELD_EX32(v, CR_TLBACC, PFN)); /* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */ if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WR) { int way = (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT); int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; - int g = (v & CR_TLBACC_G) ? 1 : 0; - int valid = ((vpn & CR_TLBACC_PFN_MASK) < 0xC0000) ? 1 : 0; + int g = FIELD_EX32(v, CR_TLBACC, G); + int valid = FIELD_EX32(vpn, CR_TLBACC, PFN) < 0xC0000; Nios2TLBEntry *entry = &env->mmu.tlb[(way * cpu->tlb_num_ways) + (vpn & env->mmu.tlb_entry_mask)]; uint32_t newTag = (vpn << 12) | (g << 11) | (valid << 10) | pid; uint32_t newData = v & (CR_TLBACC_C | CR_TLBACC_R | CR_TLBACC_W | - CR_TLBACC_X | CR_TLBACC_PFN_MASK); + CR_TLBACC_X | R_CR_TLBACC_PFN_MASK); if ((entry->tag != newTag) || (entry->data != newData)) { if (entry->tag & (1 << 10)) { @@ -153,7 +153,7 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v) &env->mmu.tlb[(way * cpu->tlb_num_ways) + (vpn & env->mmu.tlb_entry_mask)]; - env->ctrl[CR_TLBACC] &= CR_TLBACC_IGN_MASK; + env->ctrl[CR_TLBACC] &= R_CR_TLBACC_IG_MASK; env->ctrl[CR_TLBACC] |= entry->data; env->ctrl[CR_TLBACC] |= (entry->tag & (1 << 11)) ? CR_TLBACC_G : 0; env->ctrl[CR_TLBMISC] = @@ -208,7 +208,7 @@ void dump_mmu(CPUNios2State *env) entry->tag >> 12, entry->tag & ((1 << cpu->pid_num_bits) - 1), (entry->tag & (1 << 11)) ? 'G' : '-', - entry->data & CR_TLBACC_PFN_MASK, + FIELD_EX32(entry->data, CR_TLBACC, PFN), (entry->data & CR_TLBACC_C) ? 'C' : '-', (entry->data & CR_TLBACC_R) ? 'R' : '-', (entry->data & CR_TLBACC_W) ? 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 28/68] target/nios2: Rename CR_TLBMISC_WR to CR_TLBMISC_WE Date: Fri, 22 Apr 2022 09:51:58 -0700 Message-Id: <20220422165238.1971496-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" WE is the architectural name of the field, not WR. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-29-richard.henderson@linaro.org> --- target/nios2/cpu.h | 2 +- target/nios2/helper.c | 4 ++-- target/nios2/mmu.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index bfa86edd97..54bb6cd9be 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -134,7 +134,7 @@ FIELD(CR_TLBACC, IG, 25, 7) #define CR_TLBMISC_WAY_SHIFT 20 #define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT) #define CR_TLBMISC_RD (1 << 19) -#define CR_TLBMISC_WR (1 << 18) +#define CR_TLBMISC_WE (1 << 18) #define CR_TLBMISC_PID_SHIFT 4 #define CR_TLBMISC_PID_MASK (0x3FFF << CR_TLBMISC_PID_SHIFT) #define CR_TLBMISC_DBL (1 << 3) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index c2d0afe1b6..31d83e0291 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -69,7 +69,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) cs->exception_index); env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_DBL; - env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WR; + env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE; env->regs[R_EA] = env->pc + 4; env->pc = cpu->fast_tlb_miss_addr; @@ -104,7 +104,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) cs->exception_index); if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { - env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WR; + env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE; } env->regs[R_EA] = env->pc + 4; diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 826cd2afb4..0f33ea5e04 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -95,7 +95,7 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v) FIELD_EX32(v, CR_TLBACC, PFN)); /* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */ - if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WR) { + if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WE) { int way = (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT); int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; @@ -133,7 +133,7 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v) trace_nios2_mmu_write_tlbmisc(v >> CR_TLBMISC_WAY_SHIFT, (v & CR_TLBMISC_RD) ? 'R' : '.', - (v & CR_TLBMISC_WR) ? 'W' : '.', + (v & CR_TLBMISC_WE) ? 'W' : '.', (v & CR_TLBMISC_DBL) ? '2' : '.', (v & CR_TLBMISC_BAD) ? 'B' : '.', (v & CR_TLBMISC_PERM) ? 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 29/68] target/nios2: Use hw/registerfields.h for CR_TLBMISC fields Date: Fri, 22 Apr 2022 09:51:59 -0700 Message-Id: <20220422165238.1971496-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use FIELD_EX32 and FIELD_DP32 instead of managing the masking by hand. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-30-richard.henderson@linaro.org> --- target/nios2/cpu.h | 29 +++++++++++++++++++---------- target/nios2/helper.c | 7 ++----- target/nios2/mmu.c | 35 +++++++++++++++++------------------ target/nios2/translate.c | 2 +- 4 files changed, 39 insertions(+), 34 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 54bb6cd9be..f312050ecd 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -131,16 +131,25 @@ FIELD(CR_TLBACC, IG, 25, 7) #define CR_TLBACC_G R_CR_TLBACC_G_MASK #define CR_TLBMISC 10 -#define CR_TLBMISC_WAY_SHIFT 20 -#define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT) -#define CR_TLBMISC_RD (1 << 19) -#define CR_TLBMISC_WE (1 << 18) -#define CR_TLBMISC_PID_SHIFT 4 -#define CR_TLBMISC_PID_MASK (0x3FFF << CR_TLBMISC_PID_SHIFT) -#define CR_TLBMISC_DBL (1 << 3) -#define CR_TLBMISC_BAD (1 << 2) -#define CR_TLBMISC_PERM (1 << 1) -#define CR_TLBMISC_D (1 << 0) + +FIELD(CR_TLBMISC, D, 0, 1) +FIELD(CR_TLBMISC, PERM, 1, 1) +FIELD(CR_TLBMISC, BAD, 2, 1) +FIELD(CR_TLBMISC, DBL, 3, 1) +FIELD(CR_TLBMISC, PID, 4, 14) +FIELD(CR_TLBMISC, WE, 18, 1) +FIELD(CR_TLBMISC, RD, 19, 1) +FIELD(CR_TLBMISC, WAY, 20, 4) +FIELD(CR_TLBMISC, EE, 24, 1) + +#define CR_TLBMISC_EE R_CR_TLBMISC_EE_MASK +#define CR_TLBMISC_RD R_CR_TLBMISC_RD_MASK +#define CR_TLBMISC_WE R_CR_TLBMISC_WE_MASK +#define CR_TLBMISC_DBL R_CR_TLBMISC_DBL_MASK +#define CR_TLBMISC_BAD R_CR_TLBMISC_BAD_MASK +#define CR_TLBMISC_PERM R_CR_TLBMISC_PERM_MASK +#define CR_TLBMISC_D R_CR_TLBMISC_D_MASK + #define CR_ENCINJ 11 #define CR_BADADDR 12 #define CR_CONFIG 13 diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 31d83e0291..a56aaaea18 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -281,11 +281,8 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, return false; } - if (access_type == MMU_INST_FETCH) { - env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_D; - } else { - env->ctrl[CR_TLBMISC] |= CR_TLBMISC_D; - } + env->ctrl[CR_TLBMISC] = FIELD_DP32(env->ctrl[CR_TLBMISC], CR_TLBMISC, D, + access_type != MMU_INST_FETCH); env->ctrl[CR_PTEADDR] = FIELD_DP32(env->ctrl[CR_PTEADDR], CR_PTEADDR, VPN, address >> TARGET_PAGE_BITS); env->mmu.pteaddr_wr = env->ctrl[CR_PTEADDR]; diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 0f33ea5e04..d9b690b78e 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -33,7 +33,7 @@ unsigned int mmu_translate(CPUNios2State *env, target_ulong vaddr, int rw, int mmu_idx) { Nios2CPU *cpu = env_archcpu(env); - int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; + int pid = FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID); int vpn = vaddr >> 12; int way, n_ways = cpu->tlb_num_ways; @@ -96,9 +96,9 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v) /* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */ if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WE) { - int way = (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT); + int way = FIELD_EX32(env->ctrl[CR_TLBMISC], CR_TLBMISC, WAY); int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); - int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; + int pid = FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID); int g = FIELD_EX32(v, CR_TLBACC, G); int valid = FIELD_EX32(vpn, CR_TLBACC, PFN) < 0xC0000; Nios2TLBEntry *entry = @@ -117,10 +117,9 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v) entry->data = newData; } /* Auto-increment tlbmisc.WAY */ - env->ctrl[CR_TLBMISC] = - (env->ctrl[CR_TLBMISC] & ~CR_TLBMISC_WAY_MASK) | - (((way + 1) & (cpu->tlb_num_ways - 1)) << - CR_TLBMISC_WAY_SHIFT); + env->ctrl[CR_TLBMISC] = FIELD_DP32(env->ctrl[CR_TLBMISC], + CR_TLBMISC, WAY, + (way + 1) & (cpu->tlb_num_ways - 1)); } /* Writes to TLBACC don't change the read-back value */ @@ -130,24 +129,25 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v) void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v) { Nios2CPU *cpu = env_archcpu(env); + uint32_t new_pid = FIELD_EX32(v, CR_TLBMISC, PID); + uint32_t old_pid = FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID); + uint32_t way = FIELD_EX32(v, CR_TLBMISC, WAY); - trace_nios2_mmu_write_tlbmisc(v >> CR_TLBMISC_WAY_SHIFT, + trace_nios2_mmu_write_tlbmisc(way, (v & CR_TLBMISC_RD) ? 'R' : '.', (v & CR_TLBMISC_WE) ? 'W' : '.', (v & CR_TLBMISC_DBL) ? '2' : '.', (v & CR_TLBMISC_BAD) ? 'B' : '.', (v & CR_TLBMISC_PERM) ? 'P' : '.', (v & CR_TLBMISC_D) ? 'D' : '.', - (v & CR_TLBMISC_PID_MASK) >> 4); + new_pid); - if ((v & CR_TLBMISC_PID_MASK) != - (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK)) { - mmu_flush_pid(env, (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> - CR_TLBMISC_PID_SHIFT); + if (new_pid != old_pid) { + mmu_flush_pid(env, old_pid); } + /* if tlbmisc.RD == 1 then trigger a TLB read on writes to TLBMISC */ if (v & CR_TLBMISC_RD) { - int way = (v >> CR_TLBMISC_WAY_SHIFT); int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); Nios2TLBEntry *entry = &env->mmu.tlb[(way * cpu->tlb_num_ways) + @@ -156,10 +156,9 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v) env->ctrl[CR_TLBACC] &= R_CR_TLBACC_IG_MASK; env->ctrl[CR_TLBACC] |= entry->data; env->ctrl[CR_TLBACC] |= (entry->tag & (1 << 11)) ? CR_TLBACC_G : 0; - env->ctrl[CR_TLBMISC] = - (v & ~CR_TLBMISC_PID_MASK) | - ((entry->tag & ((1 << cpu->pid_num_bits) - 1)) << - CR_TLBMISC_PID_SHIFT); + env->ctrl[CR_TLBMISC] = FIELD_DP32(v, CR_TLBMISC, PID, + entry->tag & + ((1 << cpu->pid_num_bits) - 1)); env->ctrl[CR_PTEADDR] = FIELD_DP32(env->ctrl[CR_PTEADDR], CR_PTEADDR, VPN, entry->tag >> TARGET_PAGE_BITS); diff --git a/target/nios2/translate.c b/target/nios2/translate.c index baa22c5101..4191db1342 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -925,7 +925,7 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags) } qemu_fprintf(f, " mmu write: VPN=%05X PID %02X TLBACC %08X\n", env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK, - (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4, + FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID), env->mmu.tlbacc_wr); #endif qemu_fprintf(f, "\n\n"); From patchwork Fri Apr 22 16:52:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564860 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp674602map; Fri, 22 Apr 2022 10:16:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz2fJnklXI9HNeRVa/GpPaB7gy5Gw894uGIlMHV/F03yz+FNWXKJpJSy3s35GumzB5/3FmF X-Received: by 2002:a05:6214:202f:b0:432:4810:1b34 with SMTP id 15-20020a056214202f00b0043248101b34mr4575353qvf.35.1650647779081; Fri, 22 Apr 2022 10:16:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650647779; cv=none; d=google.com; s=arc-20160816; b=Plans2nsDss8IielgwBko1C+V8Sd/H5Lza/IJXeYcx0yxo+wROQMfJ9ublZPhKZsC/ /sdjTqZMm0+ywM2nRCSGsxQCanb9oAU8pHjHB3Zy69EnwGOoTG9OB4KyIGGPJk5os7cY f4nz/i+H6Qktefo9FWx4AfwNFSzq8Ubdx93r9MqKMbE3Te1Zelf+HjOtzKblTZVlI6ui 7NiXRJ11mLVCTfhso5C2LVjuX61sBoiCu+ALFQJgfRei1UTCSUEiHMU+ybV7VvKyoe86 4ewe2Z37nhRjrcrm4VyB5pD0oFuv8Vk+eOht3mJs/agtATqs2pI8c0jRKc/ZRAfsHUKa RBNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Ye00+f937DzjmYFcQBAIIaxN5ODYSNdMuba5fZB95Nk=; b=JCzs/ccZplMxjQPHNGAsTH7mak6ShleeJ41JMAipY83uA2/nDHaV6DUip421BMkuOq XpT1XRtUOBojhHUVqurJFu7XGAE1bW7hLOOl7KT/Idd2VaL0MTMnsL7/sF/vTqWu2HYi U1o724bQn7j8s4q8GLv8ctDe9gLvrEtYnAJ6p4gYXHEfNZ8dEMF3D2Mx8J2Xk5mdaS92 hzVBpsvJvZW9XSRHdDaqaSqnbpvdEfV0JkMQcTrcAceEznj6V5jwfgmDjjYZcLFOCRW7 br20Fgc9Xi/fi6Oktr1z1rX6dzBMfAVM8kVA6Krc1hzPHUt4Pw0N1w+uXwI+wd/OzOp3 ukiw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Q4dLW93I; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 30/68] target/nios2: Move R_FOO and CR_BAR into enumerations Date: Fri, 22 Apr 2022 09:52:00 -0700 Message-Id: <20220422165238.1971496-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These symbols become available to the debugger. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-31-richard.henderson@linaro.org> --- target/nios2/cpu.h | 72 ++++++++++++++++++++++------------------------ 1 file changed, 35 insertions(+), 37 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index f312050ecd..65bcc5fc0e 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -61,25 +61,43 @@ struct Nios2CPUClass { #define NUM_CR_REGS 32 /* General purpose register aliases */ -#define R_ZERO 0 -#define R_AT 1 -#define R_RET0 2 -#define R_RET1 3 -#define R_ARG0 4 -#define R_ARG1 5 -#define R_ARG2 6 -#define R_ARG3 7 -#define R_ET 24 -#define R_BT 25 -#define R_GP 26 -#define R_SP 27 -#define R_FP 28 -#define R_EA 29 -#define R_BA 30 -#define R_RA 31 +enum { + R_ZERO = 0, + R_AT = 1, + R_RET0 = 2, + R_RET1 = 3, + R_ARG0 = 4, + R_ARG1 = 5, + R_ARG2 = 6, + R_ARG3 = 7, + R_ET = 24, + R_BT = 25, + R_GP = 26, + R_SP = 27, + R_FP = 28, + R_EA = 29, + R_BA = 30, + R_RA = 31, +}; /* Control register aliases */ -#define CR_STATUS 0 +enum { + CR_STATUS = 0, + CR_ESTATUS = 1, + CR_BSTATUS = 2, + CR_IENABLE = 3, + CR_IPENDING = 4, + CR_CPUID = 5, + CR_EXCEPTION = 7, + CR_PTEADDR = 8, + CR_TLBACC = 9, + CR_TLBMISC = 10, + CR_ENCINJ = 11, + CR_BADADDR = 12, + CR_CONFIG = 13, + CR_MPUBASE = 14, + CR_MPUACC = 15, +}; FIELD(CR_STATUS, PIE, 0, 1) FIELD(CR_STATUS, U, 1, 1) @@ -98,24 +116,12 @@ FIELD(CR_STATUS, RSIE, 23, 1) #define CR_STATUS_NMI R_CR_STATUS_NMI_MASK #define CR_STATUS_RSIE R_CR_STATUS_RSIE_MASK -#define CR_ESTATUS 1 -#define CR_BSTATUS 2 -#define CR_IENABLE 3 -#define CR_IPENDING 4 -#define CR_CPUID 5 -#define CR_CTL6 6 -#define CR_EXCEPTION 7 - FIELD(CR_EXCEPTION, CAUSE, 2, 5) FIELD(CR_EXCEPTION, ECCFTL, 31, 1) -#define CR_PTEADDR 8 - FIELD(CR_PTEADDR, VPN, 2, 20) FIELD(CR_PTEADDR, PTBASE, 22, 10) -#define CR_TLBACC 9 - FIELD(CR_TLBACC, PFN, 0, 20) FIELD(CR_TLBACC, G, 20, 1) FIELD(CR_TLBACC, X, 21, 1) @@ -130,8 +136,6 @@ FIELD(CR_TLBACC, IG, 25, 7) #define CR_TLBACC_X R_CR_TLBACC_X_MASK #define CR_TLBACC_G R_CR_TLBACC_G_MASK -#define CR_TLBMISC 10 - FIELD(CR_TLBMISC, D, 0, 1) FIELD(CR_TLBMISC, PERM, 1, 1) FIELD(CR_TLBMISC, BAD, 2, 1) @@ -150,12 +154,6 @@ FIELD(CR_TLBMISC, EE, 24, 1) #define CR_TLBMISC_PERM R_CR_TLBMISC_PERM_MASK #define CR_TLBMISC_D R_CR_TLBMISC_D_MASK -#define CR_ENCINJ 11 -#define CR_BADADDR 12 -#define CR_CONFIG 13 -#define CR_MPUBASE 14 -#define CR_MPUACC 15 - /* Exceptions */ #define EXCP_BREAK 0x1000 #define EXCP_RESET 0 From patchwork Fri Apr 22 16:52:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564878 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp687178map; Fri, 22 Apr 2022 10:33:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwso7cSPD1To1Kut4zjmw4+mJxOsBNNVaWUS2ysx1G7TZ2KwTY2TCIZ1GwwyUmA8ZHTE8aT X-Received: by 2002:a05:6902:84:b0:63d:4a3d:eb5 with SMTP id h4-20020a056902008400b0063d4a3d0eb5mr5841315ybs.145.1650648800440; Fri, 22 Apr 2022 10:33:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650648800; cv=none; d=google.com; s=arc-20160816; b=bM8pzDtOWZfJAPNlEHybrql56JnyXuXnYo6iHuHOOVEO4h5FZKvIB8bfSXd9K7ATY5 JsmQ9RTL5ybniAWOpvgO/Qvay6c5gZneotGcQPZECi8zAOFWCMhuAZMV2Q6Dz4eghRX7 4vwDqiRgnLqcqzHIEonCS9SDgyf7B2m+eZTUoVrd25w5EW3lP4kePGCkJ+BLwZ4Y7Jjs GftJ9MTdy7ghcEAayxjnc7Lwqr2VAD75Jq9FARPbyV371dYVkOtz4qkwGQCgosgu2cA3 SN5C4yA7qJE1pdxYAJpOzMMTy4opBlWfPgBrnqdtVJ7dHjPh4FHMsY8HMjQnpd/aLjG8 2bWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=JGG1SeKnuAT2QHCjae7Ts/IpHjmxbOVPlNo/xG2utBk=; b=e/2shtJLFOO0gWuWrQATOuN9FC6IJwGo9FMvt3eIQwat17Q2dnfayvDQ2xzMFPYx3X gWY6sABMnuGT9L0mSy0n5iH97AfTGBF3AD8oOd6H4wZCUDLv7S0eLcFQquLrzc6fKSHR GVrU9zFOchbfebX0fdgNNpdXBDW9ypGTvuljftLSTnW6QgAbTsQPgUqB2620IjRBg3cX F5B9DSXJMrVb6qX+HFyQe8oj0GBfcZVSxBc/JTNT1wtXi4jQrlZLUpK4cVgLchnE6DX0 RJpj2nRFc+Wr+Y+cj7W6jIKHNLc/p/mL0eO9UGKa1XiRmSTjJ5sjgMwSZe2A4CwNPDew 6Jfg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qUL4PHVK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 31/68] target/nios2: Create EXCP_SEMIHOST for semi-hosting Date: Fri, 22 Apr 2022 09:52:01 -0700 Message-Id: <20220422165238.1971496-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Decode 'break 1' during translation, rather than doing it again during exception processing. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-32-richard.henderson@linaro.org> --- target/nios2/cpu.h | 1 + target/nios2/helper.c | 14 ++++++-------- target/nios2/translate.c | 17 ++++++++++++++++- 3 files changed, 23 insertions(+), 9 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 65bcc5fc0e..01cead5502 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -156,6 +156,7 @@ FIELD(CR_TLBMISC, EE, 24, 1) /* Exceptions */ #define EXCP_BREAK 0x1000 +#define EXCP_SEMIHOST 0x1001 #define EXCP_RESET 0 #define EXCP_PRESET 1 #define EXCP_IRQ 2 diff --git a/target/nios2/helper.c b/target/nios2/helper.c index a56aaaea18..1d17c0379f 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -152,14 +152,6 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_BREAK: qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=%x\n", env->pc); - /* The semihosting instruction is "break 1". */ - if (semihosting_enabled() && - cpu_ldl_code(env, env->pc) == 0x003da07a) { - qemu_log_mask(CPU_LOG_INT, "Entering semihosting\n"); - env->pc += 4; - do_nios2_semihosting(env); - break; - } if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { env->ctrl[CR_BSTATUS] = env->ctrl[CR_STATUS]; @@ -176,6 +168,12 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->pc = cpu->exception_addr; break; + case EXCP_SEMIHOST: + qemu_log_mask(CPU_LOG_INT, "BREAK semihosting at pc=%x\n", env->pc); + env->pc += 4; + do_nios2_semihosting(env); + break; + default: cpu_abort(cs, "unhandled exception type=%d\n", cs->exception_index); diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 4191db1342..97e531529f 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -33,6 +33,7 @@ #include "exec/translator.h" #include "qemu/qemu-print.h" #include "exec/gen-icount.h" +#include "semihosting/semihost.h" /* is_jmp field values */ #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ @@ -686,6 +687,20 @@ static void trap(DisasContext *dc, uint32_t code, uint32_t flags) t_gen_helper_raise_exception(dc, EXCP_TRAP); } +static void gen_break(DisasContext *dc, uint32_t code, uint32_t flags) +{ +#ifndef CONFIG_USER_ONLY + /* The semihosting instruction is "break 1". */ + R_TYPE(instr, code); + if (semihosting_enabled() && instr.imm5 == 1) { + t_gen_helper_raise_exception(dc, EXCP_SEMIHOST); + return; + } +#endif + + t_gen_helper_raise_exception(dc, EXCP_BREAK); +} + static const Nios2Instruction r_type_instructions[] = { INSTRUCTION_ILLEGAL(), INSTRUCTION(eret), /* eret */ @@ -739,7 +754,7 @@ static const Nios2Instruction r_type_instructions[] = { INSTRUCTION(add), /* add */ INSTRUCTION_ILLEGAL(), INSTRUCTION_ILLEGAL(), - INSTRUCTION_FLG(gen_excp, EXCP_BREAK), /* break */ + INSTRUCTION(gen_break), /* break */ INSTRUCTION_ILLEGAL(), INSTRUCTION(nop), /* nop */ INSTRUCTION_ILLEGAL(), From patchwork Fri Apr 22 16:52:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564856 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp670518map; 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 32/68] target/nios2: Clean up nios2_cpu_do_interrupt Date: Fri, 22 Apr 2022 09:52:02 -0700 Message-Id: <20220422165238.1971496-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split out do_exception and do_iic_irq to handle bulk of the interrupt and exception processing. Parameterize the changes required to cpu state. The status.EH bit, which protects some data against double-faults, is only present with the MMU. Several exception cases did not check for status.EH being set, as required. The status.IH bit, which had been set by EXCP_IRQ, is exclusive to the external interrupt controller, which we do not yet implement. The internal interrupt controller, when the MMU is also present, sets the status.EH bit. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-33-richard.henderson@linaro.org> --- target/nios2/helper.c | 141 +++++++++++++----------------------------- 1 file changed, 44 insertions(+), 97 deletions(-) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 1d17c0379f..63971a8b3c 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -29,6 +29,42 @@ #include "semihosting/semihost.h" +static void do_exception(Nios2CPU *cpu, uint32_t exception_addr, bool is_break) +{ + CPUNios2State *env = &cpu->env; + CPUState *cs = CPU(cpu); + uint32_t old_status = env->ctrl[CR_STATUS]; + uint32_t new_status = old_status; + + if ((old_status & CR_STATUS_EH) == 0) { + int r_ea = R_EA, cr_es = CR_ESTATUS; + + if (is_break) { + r_ea = R_BA; + cr_es = CR_BSTATUS; + } + env->ctrl[cr_es] = old_status; + env->regs[r_ea] = env->pc + 4; + + if (cpu->mmu_present) { + new_status |= CR_STATUS_EH; + } + } + + new_status &= ~(CR_STATUS_PIE | CR_STATUS_U); + + env->ctrl[CR_STATUS] = new_status; + env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], + CR_EXCEPTION, CAUSE, + cs->exception_index); + env->pc = exception_addr; +} + +static void do_iic_irq(Nios2CPU *cpu) +{ + do_exception(cpu, cpu->exception_addr, false); +} + void nios2_cpu_do_interrupt(CPUState *cs) { Nios2CPU *cpu = NIOS2_CPU(cs); @@ -36,57 +72,20 @@ void nios2_cpu_do_interrupt(CPUState *cs) switch (cs->exception_index) { case EXCP_IRQ: - assert(env->ctrl[CR_STATUS] & CR_STATUS_PIE); - qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%x\n", env->pc); - - env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS]; - env->ctrl[CR_STATUS] |= CR_STATUS_IH; - env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - - env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], - CR_EXCEPTION, CAUSE, - cs->exception_index); - - env->regs[R_EA] = env->pc + 4; - env->pc = cpu->exception_addr; + do_iic_irq(cpu); break; case EXCP_TLBD: if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=%x\n", env->pc); - - /* Fast TLB miss */ - /* Variation from the spec. Table 3-35 of the cpu reference shows - * estatus not being changed for TLB miss but this appears to - * be incorrect. */ - env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS]; - env->ctrl[CR_STATUS] |= CR_STATUS_EH; - env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - - env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], - CR_EXCEPTION, CAUSE, - cs->exception_index); - env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_DBL; env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE; - - env->regs[R_EA] = env->pc + 4; - env->pc = cpu->fast_tlb_miss_addr; + do_exception(cpu, cpu->fast_tlb_miss_addr, false); } else { qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=%x\n", env->pc); - - /* Double TLB miss */ - env->ctrl[CR_STATUS] |= CR_STATUS_EH; - env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - - env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], - CR_EXCEPTION, CAUSE, - cs->exception_index); - env->ctrl[CR_TLBMISC] |= CR_TLBMISC_DBL; - - env->pc = cpu->exception_addr; + do_exception(cpu, cpu->exception_addr, false); } break; @@ -94,78 +93,28 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_TLBW: case EXCP_TLBX: qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=%x\n", env->pc); - - env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS]; - env->ctrl[CR_STATUS] |= CR_STATUS_EH; - env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - - env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], - CR_EXCEPTION, CAUSE, - cs->exception_index); - if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE; } - - env->regs[R_EA] = env->pc + 4; - env->pc = cpu->exception_addr; + do_exception(cpu, cpu->exception_addr, false); break; case EXCP_SUPERA: case EXCP_SUPERI: case EXCP_SUPERD: qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=%x\n", env->pc); - - if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { - env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS]; - env->regs[R_EA] = env->pc + 4; - } - - env->ctrl[CR_STATUS] |= CR_STATUS_EH; - env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - - env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], - CR_EXCEPTION, CAUSE, - cs->exception_index); - - env->pc = cpu->exception_addr; + do_exception(cpu, cpu->exception_addr, false); break; case EXCP_ILLEGAL: case EXCP_TRAP: qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=%x\n", env->pc); - - if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { - env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS]; - env->regs[R_EA] = env->pc + 4; - } - - env->ctrl[CR_STATUS] |= CR_STATUS_EH; - env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - - env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], - CR_EXCEPTION, CAUSE, - cs->exception_index); - - env->pc = cpu->exception_addr; + do_exception(cpu, cpu->exception_addr, false); break; case EXCP_BREAK: qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=%x\n", env->pc); - - if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { - env->ctrl[CR_BSTATUS] = env->ctrl[CR_STATUS]; - env->regs[R_BA] = env->pc + 4; - } - - env->ctrl[CR_STATUS] |= CR_STATUS_EH; - env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U); - - env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], - CR_EXCEPTION, CAUSE, - cs->exception_index); - - env->pc = cpu->exception_addr; + do_exception(cpu, cpu->exception_addr, true); break; case EXCP_SEMIHOST: @@ -175,9 +124,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) break; default: - cpu_abort(cs, "unhandled exception type=%d\n", - cs->exception_index); - break; + cpu_abort(cs, "unhandled exception type=%d\n", cs->exception_index); } } From patchwork Fri Apr 22 16:52:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564871 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp682406map; Fri, 22 Apr 2022 10:26:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxBQeD3urWyibs1pb3s3kFPdav5ezaTBmH7r85ZFzhxD52Bq0qZkCLJadZwTqkv35om2+98 X-Received: by 2002:ae9:de02:0:b0:69b:7aae:83f1 with SMTP id s2-20020ae9de02000000b0069b7aae83f1mr3407386qkf.473.1650648419322; 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[209.51.188.17]) by mx.google.com with ESMTPS id eo11-20020ad4594b000000b004462a228634si1318566qvb.569.2022.04.22.10.26.59 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Apr 2022 10:26:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gwn7mI3S; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40420 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhx3a-0008CJ-Rk for patch@linaro.org; Fri, 22 Apr 2022 13:26:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48974) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhwXO-00023C-BO for qemu-devel@nongnu.org; Fri, 22 Apr 2022 12:53:42 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]:37883) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nhwXM-0007Ls-NE for qemu-devel@nongnu.org; Fri, 22 Apr 2022 12:53:42 -0400 Received: by mail-pf1-x433.google.com with SMTP id bo5so8537556pfb.4 for ; Fri, 22 Apr 2022 09:53:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=A1+hFfX+YJ+rRNsAMYCjA2Q5J7nLgy08oqJtBrD3bio=; b=gwn7mI3SpA4lgqr3U0Sh7ULf/XSM9M0nr5l3IRxsNWDX8qTeVE8cPm9Hpwwf2CPgBd awS2JaGmmp0lSTlBTMjaIGjWvapKXd+MtSsvAFdp9I8NQ+SmtTecfbjQIdTqiPxqRN2j mDki866BlRD5uKjz9WDS3gt7N13Ywzl1Qqyk2V1PVDkYX3IrUP58nJpfs+scufd0d1XQ IuW+veU2uOLBRKTkcpTYDwBu9YX/z1yM8TW1Aox3wt1zpcpDIDkpmp3Ju2ch6kMtz/2W sU0dKjSEQ8Z9a2YKkYY3ltbZ/eeOVoKcPwB2YsYICZGVFqb40k5nmpgKhhbbxpTUKeNw 6fag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A1+hFfX+YJ+rRNsAMYCjA2Q5J7nLgy08oqJtBrD3bio=; b=s5+nfqnOMxqn5o9UdVj/j4MJ5m8eW9Fo9Ev//U3SGN3fYan4bc9+XMy4WL6i5tpoK3 MP0Qs/d3o08Os+S+M70W8OvwVp1G0H6OIM68cJfDAakY3zKoB1nofBpVTKSZr2MkFns2 3iJM9AJQpTjIqBfQq0N8cL/bQrsmRSfjRBTu4pYXTIuhDj39VQuLW7QF09sPXx9ll5oL sK0Pd+7yOOU4c0qfGQU9xiPCoKuHQPh5ZwN631KjFpXMNtSxpR3oVbCQfXEOkWgTHXAh Q8RcHE8wW7nJr6IBMmnZYwBAPkM3IXuf8B5OyqKgVd2j/87SHzzdt6HNB6jeu3DDn9PA DPHg== X-Gm-Message-State: AOAM5335eqLul/FNO60b+iJcr+ACg+EdSl0mZoe/DDk5VUcwCETvRYCx eDIztPWrQqBDjiTG77y6brZ1PcHGiVyEZWUG X-Received: by 2002:a63:e315:0:b0:3a9:efa0:18a with SMTP id f21-20020a63e315000000b003a9efa0018amr4566002pgh.33.1650646419405; Fri, 22 Apr 2022 09:53:39 -0700 (PDT) Received: from stoup.. ([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 33/68] target/nios2: Hoist CPU_LOG_INT logging Date: Fri, 22 Apr 2022 09:52:03 -0700 Message-Id: <20220422165238.1971496-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Performing this early means that we can merge more cases within the non-logging switch statement. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-34-richard.henderson@linaro.org> --- target/nios2/helper.c | 58 +++++++++++++++++++++++++++++++++++-------- 1 file changed, 47 insertions(+), 11 deletions(-) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 63971a8b3c..c57ffd64e0 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -70,20 +70,64 @@ void nios2_cpu_do_interrupt(CPUState *cs) Nios2CPU *cpu = NIOS2_CPU(cs); CPUNios2State *env = &cpu->env; + if (qemu_loglevel_mask(CPU_LOG_INT)) { + const char *name = NULL; + + switch (cs->exception_index) { + case EXCP_IRQ: + name = "interrupt"; + break; + case EXCP_TLBD: + if (env->ctrl[CR_STATUS] & CR_STATUS_EH) { + name = "TLB MISS (double)"; + } else { + name = "TLB MISS (fast)"; + } + break; + case EXCP_TLBR: + case EXCP_TLBW: + case EXCP_TLBX: + name = "TLB PERM"; + break; + case EXCP_SUPERA: + case EXCP_SUPERD: + name = "SUPERVISOR (address)"; + break; + case EXCP_SUPERI: + name = "SUPERVISOR (insn)"; + break; + case EXCP_ILLEGAL: + name = "ILLEGAL insn"; + break; + case EXCP_TRAP: + name = "TRAP insn"; + break; + case EXCP_BREAK: + name = "BREAK insn"; + break; + case EXCP_SEMIHOST: + name = "SEMIHOST insn"; + break; + } + if (name) { + qemu_log("%s at pc=0x%08x\n", name, env->pc); + } else { + qemu_log("Unknown exception %d at pc=0x%08x\n", + cs->exception_index, env->pc); + } + } + switch (cs->exception_index) { case EXCP_IRQ: - qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%x\n", env->pc); do_iic_irq(cpu); break; case EXCP_TLBD: if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { - qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=%x\n", env->pc); env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_DBL; env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE; do_exception(cpu, cpu->fast_tlb_miss_addr, false); } else { - qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=%x\n", env->pc); env->ctrl[CR_TLBMISC] |= CR_TLBMISC_DBL; do_exception(cpu, cpu->exception_addr, false); } @@ -92,7 +136,6 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_TLBR: case EXCP_TLBW: case EXCP_TLBX: - qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=%x\n", env->pc); if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE; } @@ -102,23 +145,16 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_SUPERA: case EXCP_SUPERI: case EXCP_SUPERD: - qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=%x\n", env->pc); - do_exception(cpu, cpu->exception_addr, false); - break; - case EXCP_ILLEGAL: case EXCP_TRAP: - qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=%x\n", env->pc); do_exception(cpu, cpu->exception_addr, false); break; case EXCP_BREAK: - qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=%x\n", env->pc); do_exception(cpu, cpu->exception_addr, true); break; case EXCP_SEMIHOST: - qemu_log_mask(CPU_LOG_INT, "BREAK semihosting at pc=%x\n", env->pc); env->pc += 4; do_nios2_semihosting(env); break; From patchwork Fri Apr 22 16:52:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564864 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp677427map; 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 34/68] target/nios2: Handle EXCP_UNALIGN and EXCP_UNALIGND Date: Fri, 22 Apr 2022 09:52:04 -0700 Message-Id: <20220422165238.1971496-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" While some of the plumbing for misaligned data is present, in the form of nios2_cpu_do_unaligned_access, the hook will not be called because TARGET_ALIGNED_ONLY is not set in configs/targets/nios2-softmmu.mak. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20220421151735.31996-35-richard.henderson@linaro.org> --- target/nios2/helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index c57ffd64e0..25a89724d0 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -99,6 +99,12 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_ILLEGAL: name = "ILLEGAL insn"; break; + case EXCP_UNALIGN: + name = "Misaligned (data)"; + break; + case EXCP_UNALIGND: + name = "Misaligned (destination)"; + break; case EXCP_TRAP: name = "TRAP insn"; break; @@ -147,6 +153,8 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_SUPERD: case EXCP_ILLEGAL: case EXCP_TRAP: + case EXCP_UNALIGN: + case EXCP_UNALIGND: do_exception(cpu, cpu->exception_addr, false); break; From patchwork Fri Apr 22 16:52:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564861 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp674610map; Fri, 22 Apr 2022 10:16:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyv/mxk0X1xrAfQE62TzPw3AhVAcmw86PiUs9fqOS+TYpbGtQSAYUsZ5TC3m9c2FjWe7vFJ X-Received: by 2002:a05:620a:424d:b0:67d:2bad:4450 with SMTP id w13-20020a05620a424d00b0067d2bad4450mr3339831qko.171.1650647779377; Fri, 22 Apr 2022 10:16:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650647779; cv=none; d=google.com; s=arc-20160816; b=bbc3tBnkmBO6/9ZTQDrpQKMa+osHpjpHBfvlgFtl2M2fXFnKrJz4CNW0y81/1ULBBJ E84LwTSXjsox+VpnOwwGPWEgaNqwcU2i90lS9IDyT4Ru4Bip7HaUV5ihc768fZyxj/VB Aj4POFD7R8mAV34RfAiymRH3w1rDbVB6bjzqhd0NFLjBNKm++5Ca6M2qxlR5hkkj3GST jNIsav+OckJFDcQ+m7znNMjo/daKlbQVawaeoxzzxwD8VZ8t4vQuU4KzBRQm2rFUlITY gGU4b+cD9kOcq9eGnr6gWgmJobZ10NvLVZgubhL/KPy05iUWSC7qHcJd/K+lsywgokkk gUKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ysJZrdf3qEL6SmyFziC5eyUqxmIxqoso+UNr/N0Gtr8=; b=cwASBwHe93/4iUGEQxMSXgx4xhXHSOmhqTFx8puQsrPUs9Kkig1QNt/dd/Io1Kw0AL TA38ynSvSIKdqwHkeUcGIv6bdOU2+tg9oC8OMSC3CKM9QaJwsWcKCvFZWF7kGLYPbK7A SzUZhE9/EscZ4CwuFWfUBZmjZqH9wwiZk6ojChcVxvsdMllL1+BIumkekbNf8qqlIw+R q71wZ0DDfQKbfnAmaHSAxY6vKx01uSD/vwhpsyysruLM7d+7lu9JKRR4AKsxrk7wkDRw /uZ9qmxYwKRUMqwJ7uyQQ1ddAOJdSfD10Fv6JeZZi5i7NLl1u6g8WhUi/wjzg/4j+++D Tslw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ev1zUGXG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 35/68] target/nios2: Cleanup set of CR_EXCEPTION for do_interrupt Date: Fri, 22 Apr 2022 09:52:05 -0700 Message-Id: <20220422165238.1971496-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The register is entirely read-only for software, and we do not implement ECC, so we need not deposit the cause into an existing value; just create a new value from scratch. Furthermore, exception.CAUSE is not written for break exceptions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-36-richard.henderson@linaro.org> --- target/nios2/helper.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 25a89724d0..3d9869453b 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -54,9 +54,10 @@ static void do_exception(Nios2CPU *cpu, uint32_t exception_addr, bool is_break) new_status &= ~(CR_STATUS_PIE | CR_STATUS_U); env->ctrl[CR_STATUS] = new_status; - env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION], - CR_EXCEPTION, CAUSE, - cs->exception_index); + if (!is_break) { + env->ctrl[CR_EXCEPTION] = FIELD_DP32(0, CR_EXCEPTION, CAUSE, + cs->exception_index); + } env->pc = exception_addr; } From patchwork Fri Apr 22 16:52:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564868 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp679942map; Fri, 22 Apr 2022 10:23:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw+gIgHKoli8TGbqqKwPJGGd0L9Fyip2C6vijZTQ3bWt4wtu/Npw3MiURmOaA7sDaVqOJes X-Received: by 2002:a05:622a:296:b0:2f2:4a5:a03c with SMTP id z22-20020a05622a029600b002f204a5a03cmr4097768qtw.368.1650648193018; Fri, 22 Apr 2022 10:23:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650648193; cv=none; d=google.com; s=arc-20160816; b=QBb6rKzA0lIUZF6DqUul/+A21AZgZjVB61DRxIZ4Dao+VKc/CX4RMAj6fXl0yl8f2M DYPDSfz8yu00+6aGygTYBE4FlgLpstkHuiTxmLPVKIVtm1tydgqDArZgGBlu215uCF4X nIMyQ5kwIF7LhDqR+sUMeGPkz3YBo2fKkVKiqDUtGjWsH2vy1lrYCn0FxUMXViDXyQZz Rws1IH/IUr+KdZ8EQSK1qGTRFu7P/HPIhAlGvqnT7bA3BZYdbYWoeR5Up5FHHVOGsB33 ck5PSRtwK/izWXBHe+crp35pA7g2Bh7MXGfTjyZMQAsLYzdAiPoNfe6EKm7JTAKEi3Et pNaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xHxvfyaHHNAh6ZFog8b1i7xhm5MEp5/7nB+TsCbtI6Y=; b=GqYLVF9D3D9BbIig8cUCzC1E73vM/KnOP8/DNsDuNOu2X/I0Wm4Q7/xBo+wvZgOgZ8 iRWPjU7YxRqmiIntTzsR01LxpBT8H+qOkLopngrNuNOnJ0vne8a+eapivK9UArdDjsxD Q8+c8DB33eBE6WDbhEYPZlSAHlJzEqReez/97wAqlRrHBARQiSEGVaTy4Y004McHHSV7 yx8mKxSXCCwsGhmJulO3UpxiElmsHW5nlI3Q0Ho7hGF7wfu1QsP2F8tvjyUlwOzRA4P3 wmY83q/Vn6pOVnKF57pQJ2WuJG1sXsoxi8c/5408fsxsllJKHlPD8v1lTwVwayRXo38U K6YA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Xoi/hpBs"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 36/68] target/nios2: Clean up handling of tlbmisc in do_exception Date: Fri, 22 Apr 2022 09:52:06 -0700 Message-Id: <20220422165238.1971496-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The 4 lower bits, D, PERM, BAD, DBL, are unconditionally set on any exception with EH=0, or so says Table 42 (Processor Status After Taking Exception). We currently do not set PERM or BAD at all, and only set/clear DBL for tlb miss, and do not clear DBL for any other exception. It is a bit confusing to set D in tlb_fill and the rest during do_interrupt, so move the setting of D to do_interrupt as well. To do this, split EXP_TLBD into two cases, EXCP_TLB_X and EXCP_TLB_D, which allows us to distinguish them during do_interrupt. Choose a value for EXCP_TLB_D such that when truncated it produces the correct value for exception.CAUSE. Rename EXCP_TLB[RWX] to EXCP_PERM_[RWX], to emphasize that the exception is permissions related. Rename EXCP_SUPER[AD] to EXCP_SUPERA_[DX] to emphasize that they are both "supervisor address" exceptions, data and execute. Retain the setting of tlbmisc.WE for the fast-tlb-miss path, as it is being relied upon, but remove it from the permission path. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-37-richard.henderson@linaro.org> --- target/nios2/cpu.h | 13 +++--- target/nios2/helper.c | 97 +++++++++++++++++++++++++++++-------------- 2 files changed, 73 insertions(+), 37 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 01cead5502..0027416742 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -166,13 +166,14 @@ FIELD(CR_TLBMISC, EE, 24, 1) #define EXCP_UNALIGN 6 #define EXCP_UNALIGND 7 #define EXCP_DIV 8 -#define EXCP_SUPERA 9 +#define EXCP_SUPERA_X 9 #define EXCP_SUPERI 10 -#define EXCP_SUPERD 11 -#define EXCP_TLBD 12 -#define EXCP_TLBX 13 -#define EXCP_TLBR 14 -#define EXCP_TLBW 15 +#define EXCP_SUPERA_D 11 +#define EXCP_TLB_X 12 +#define EXCP_TLB_D (0x1000 | EXCP_TLB_X) +#define EXCP_PERM_X 13 +#define EXCP_PERM_R 14 +#define EXCP_PERM_W 15 #define EXCP_MPUI 16 #define EXCP_MPUD 17 diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 3d9869453b..4d9085f22f 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -29,7 +29,8 @@ #include "semihosting/semihost.h" -static void do_exception(Nios2CPU *cpu, uint32_t exception_addr, bool is_break) +static void do_exception(Nios2CPU *cpu, uint32_t exception_addr, + uint32_t tlbmisc_set, bool is_break) { CPUNios2State *env = &cpu->env; CPUState *cs = CPU(cpu); @@ -48,6 +49,16 @@ static void do_exception(Nios2CPU *cpu, uint32_t exception_addr, bool is_break) if (cpu->mmu_present) { new_status |= CR_STATUS_EH; + + /* + * There are 4 bits that are always written. + * Explicitly clear them, to be set via the argument. + */ + env->ctrl[CR_TLBMISC] &= ~(CR_TLBMISC_D | + CR_TLBMISC_PERM | + CR_TLBMISC_BAD | + CR_TLBMISC_DBL); + env->ctrl[CR_TLBMISC] |= tlbmisc_set; } } @@ -63,13 +74,14 @@ static void do_exception(Nios2CPU *cpu, uint32_t exception_addr, bool is_break) static void do_iic_irq(Nios2CPU *cpu) { - do_exception(cpu, cpu->exception_addr, false); + do_exception(cpu, cpu->exception_addr, 0, false); } void nios2_cpu_do_interrupt(CPUState *cs) { Nios2CPU *cpu = NIOS2_CPU(cs); CPUNios2State *env = &cpu->env; + uint32_t tlbmisc_set = 0; if (qemu_loglevel_mask(CPU_LOG_INT)) { const char *name = NULL; @@ -78,20 +90,21 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_IRQ: name = "interrupt"; break; - case EXCP_TLBD: + case EXCP_TLB_X: + case EXCP_TLB_D: if (env->ctrl[CR_STATUS] & CR_STATUS_EH) { name = "TLB MISS (double)"; } else { name = "TLB MISS (fast)"; } break; - case EXCP_TLBR: - case EXCP_TLBW: - case EXCP_TLBX: + case EXCP_PERM_R: + case EXCP_PERM_W: + case EXCP_PERM_X: name = "TLB PERM"; break; - case EXCP_SUPERA: - case EXCP_SUPERD: + case EXCP_SUPERA_X: + case EXCP_SUPERA_D: name = "SUPERVISOR (address)"; break; case EXCP_SUPERI: @@ -129,38 +142,57 @@ void nios2_cpu_do_interrupt(CPUState *cs) do_iic_irq(cpu); break; - case EXCP_TLBD: - if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { - env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_DBL; - env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE; - do_exception(cpu, cpu->fast_tlb_miss_addr, false); + case EXCP_TLB_D: + tlbmisc_set = CR_TLBMISC_D; + /* fall through */ + case EXCP_TLB_X: + if (env->ctrl[CR_STATUS] & CR_STATUS_EH) { + tlbmisc_set |= CR_TLBMISC_DBL; + /* + * Normally, we don't write to tlbmisc unless !EH, + * so do it manually for the double-tlb miss exception. + */ + env->ctrl[CR_TLBMISC] &= ~(CR_TLBMISC_D | + CR_TLBMISC_PERM | + CR_TLBMISC_BAD); + env->ctrl[CR_TLBMISC] |= tlbmisc_set; + do_exception(cpu, cpu->exception_addr, 0, false); } else { - env->ctrl[CR_TLBMISC] |= CR_TLBMISC_DBL; - do_exception(cpu, cpu->exception_addr, false); + tlbmisc_set |= CR_TLBMISC_WE; + do_exception(cpu, cpu->fast_tlb_miss_addr, tlbmisc_set, false); } break; - case EXCP_TLBR: - case EXCP_TLBW: - case EXCP_TLBX: - if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { - env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE; + case EXCP_PERM_R: + case EXCP_PERM_W: + tlbmisc_set = CR_TLBMISC_D; + /* fall through */ + case EXCP_PERM_X: + tlbmisc_set |= CR_TLBMISC_PERM; + if (!(env->ctrl[CR_STATUS] & CR_STATUS_EH)) { + tlbmisc_set |= CR_TLBMISC_WE; } - do_exception(cpu, cpu->exception_addr, false); + do_exception(cpu, cpu->exception_addr, tlbmisc_set, false); + break; + + case EXCP_SUPERA_D: + case EXCP_UNALIGN: + tlbmisc_set = CR_TLBMISC_D; + /* fall through */ + case EXCP_SUPERA_X: + case EXCP_UNALIGND: + tlbmisc_set |= CR_TLBMISC_BAD; + do_exception(cpu, cpu->exception_addr, tlbmisc_set, false); break; - case EXCP_SUPERA: case EXCP_SUPERI: - case EXCP_SUPERD: case EXCP_ILLEGAL: case EXCP_TRAP: - case EXCP_UNALIGN: - case EXCP_UNALIGND: - do_exception(cpu, cpu->exception_addr, false); + do_exception(cpu, cpu->exception_addr, 0, false); break; case EXCP_BREAK: - do_exception(cpu, cpu->exception_addr, true); + do_exception(cpu, cpu->exception_addr, 0, true); break; case EXCP_SEMIHOST: @@ -215,7 +247,7 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, { Nios2CPU *cpu = NIOS2_CPU(cs); CPUNios2State *env = &cpu->env; - unsigned int excp = EXCP_TLBD; + unsigned int excp; target_ulong vaddr, paddr; Nios2MMULookup lu; unsigned int hit; @@ -242,7 +274,8 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, if (probe) { return false; } - cs->exception_index = EXCP_SUPERA; + cs->exception_index = (access_type == MMU_INST_FETCH + ? EXCP_SUPERA_X : EXCP_SUPERA_D); env->ctrl[CR_BADADDR] = address; cpu_loop_exit_restore(cs, retaddr); } @@ -263,8 +296,10 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } /* Permission violation */ - excp = (access_type == MMU_DATA_LOAD ? EXCP_TLBR : - access_type == MMU_DATA_STORE ? EXCP_TLBW : EXCP_TLBX); + excp = (access_type == MMU_DATA_LOAD ? EXCP_PERM_R : + access_type == MMU_DATA_STORE ? EXCP_PERM_W : EXCP_PERM_X); + } else { + excp = (access_type == MMU_INST_FETCH ? EXCP_TLB_X: EXCP_TLB_D); } if (probe) { From patchwork Fri Apr 22 16:52:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564865 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp677441map; Fri, 22 Apr 2022 10:19:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwGYEUBboInLDsMFSmzhnV6LkP9OVeUL39hFVeupPsNXaeJAGo2TT0JDr3C2OAmj/zqVxQe X-Received: by 2002:a05:620a:748:b0:69c:a57:c6c8 with SMTP id i8-20020a05620a074800b0069c0a57c6c8mr3321083qki.361.1650647982113; Fri, 22 Apr 2022 10:19:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650647982; cv=none; d=google.com; s=arc-20160816; b=XnLKifq9ikjCCXHF/XfdUHld2U6iK9gJUQLX4cQAPzkY15AE4G89AIVex+pyLdiez0 5mnSheJw6omNSEXcYJBbOt1xc9M+DF1+V9/SQ6mSDJvJBPOassZ9Jzy6pcNODUhuQiMn G2oemELQaL2lyedmqoyDmGT0i/8MI7aW01gEEs/WgujBaRw7QFROqWTBBUw1E60cgjaL nDk3FE/K83DlzBmnUIIaP6yRQSqPLMUy+qj5gUwnpbqLtigIA9MHb3T8gR5wo6WduDE9 jiywrbpff7b8HzaVYCEcnNXpVNLPUsUmzQi2FmDyQp6cvjz1qYTOWSJ2ClICXPlUNFCY XLfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=b91HmxjG0u6CLiTBN86Gl9ydinvbPQB9WXtZ8LXqaK4=; b=mjDhW32zZR7QIUw+k4FxIQ6g7u1QYJK9P2qL8HVUfCtERFKy32m+KoczKDy+rTWbUf zDZNOPiRxFVJzBXQfWhL2P/VVD8Hxo63soM34E9jFBI5Cp5ng2Ms/1jAZ7c8eLZueH8q 9aythZAo805VUe8zXuDfONRDTa4NlyaDnHJAq3pM+uLBySUHcStEFbe2U1PCBEtTcuAm R8f/mAGUI7kEO+DtZh9vxdyPNgpkp3azuuPhtK3d8Usk+x2esZLmvxljrDd4875z1es6 vljAUwcvXS6nG4V71FtCQZefk4rEnUxxTaBlIk853ilTskXkVaZ1vVvYZQ7AxmdRuclP uNUg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rlf3kvE1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 37/68] target/nios2: Prevent writes to read-only or reserved control fields Date: Fri, 22 Apr 2022 09:52:07 -0700 Message-Id: <20220422165238.1971496-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create an array of masks which detail the writable and readonly bits for each control register. Apply them when writing to control registers, including the write to status during eret. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20220421151735.31996-38-richard.henderson@linaro.org> --- target/nios2/cpu.h | 13 +++++ target/nios2/cpu.c | 100 +++++++++++++++++++++++++++++++++------ target/nios2/op_helper.c | 9 ++++ target/nios2/translate.c | 80 ++++++++++++++++++++++++------- 4 files changed, 171 insertions(+), 31 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 0027416742..da85d82faa 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -190,6 +190,11 @@ struct CPUArchState { int error_code; }; +typedef struct { + uint32_t writable; + uint32_t readonly; +} ControlRegState; + /** * Nios2CPU: * @env: #CPUNios2State @@ -213,9 +218,17 @@ struct ArchCPU { uint32_t reset_addr; uint32_t exception_addr; uint32_t fast_tlb_miss_addr; + + /* Bits within each control register which are reserved or readonly. */ + ControlRegState cr_state[NUM_CR_REGS]; }; +static inline bool nios2_cr_reserved(const ControlRegState *s) +{ + return (s->writable | s->readonly) == 0; +} + void nios2_tcg_init(void); void nios2_cpu_do_interrupt(CPUState *cs); void dump_mmu(CPUNios2State *env); diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index fce16a2e77..b3c5ae681c 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -102,6 +102,64 @@ static ObjectClass *nios2_cpu_class_by_name(const char *cpu_model) return object_class_by_name(TYPE_NIOS2_CPU); } +static void realize_cr_status(CPUState *cs) +{ + Nios2CPU *cpu = NIOS2_CPU(cs); + + /* Begin with all fields of all registers are reserved. */ + memset(cpu->cr_state, 0, sizeof(cpu->cr_state)); + + /* + * The combination of writable and readonly is the set of all + * non-reserved fields. We apply writable as a mask to bits, + * and merge in existing readonly bits, before storing. + */ +#define WR_REG(C) cpu->cr_state[C].writable = -1 +#define RO_REG(C) cpu->cr_state[C].readonly = -1 +#define WR_FIELD(C, F) cpu->cr_state[C].writable |= R_##C##_##F##_MASK +#define RO_FIELD(C, F) cpu->cr_state[C].readonly |= R_##C##_##F##_MASK + + WR_FIELD(CR_STATUS, PIE); + WR_REG(CR_ESTATUS); + WR_REG(CR_BSTATUS); + RO_REG(CR_CPUID); + RO_REG(CR_EXCEPTION); + WR_REG(CR_BADADDR); + + /* TODO: These control registers are not present with the EIC. */ + WR_REG(CR_IENABLE); + RO_REG(CR_IPENDING); + + if (cpu->mmu_present) { + WR_FIELD(CR_STATUS, U); + WR_FIELD(CR_STATUS, EH); + + WR_FIELD(CR_PTEADDR, VPN); + WR_FIELD(CR_PTEADDR, PTBASE); + + RO_FIELD(CR_TLBMISC, D); + RO_FIELD(CR_TLBMISC, PERM); + RO_FIELD(CR_TLBMISC, BAD); + RO_FIELD(CR_TLBMISC, DBL); + WR_FIELD(CR_TLBMISC, PID); + WR_FIELD(CR_TLBMISC, WE); + WR_FIELD(CR_TLBMISC, RD); + WR_FIELD(CR_TLBMISC, WAY); + + WR_REG(CR_TLBACC); + } + + /* + * TODO: ECC (config, eccinj) and MPU (config, mpubase, mpuacc) are + * unimplemented, so their corresponding control regs remain reserved. + */ + +#undef WR_REG +#undef RO_REG +#undef WR_FIELD +#undef RO_FIELD +} + static void nios2_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -114,6 +172,7 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp) return; } + realize_cr_status(cs); qemu_init_vcpu(cs); cpu_reset(cs); @@ -147,23 +206,26 @@ static void nios2_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) static int nios2_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { Nios2CPU *cpu = NIOS2_CPU(cs); - CPUClass *cc = CPU_GET_CLASS(cs); CPUNios2State *env = &cpu->env; + uint32_t val; - if (n > cc->gdb_num_core_regs) { + if (n < 32) { /* GP regs */ + val = env->regs[n]; + } else if (n == 32) { /* PC */ + val = env->pc; + } else if (n < 49) { /* Status regs */ + unsigned cr = n - 33; + if (nios2_cr_reserved(&cpu->cr_state[cr])) { + val = 0; + } else { + val = env->ctrl[n - 33]; + } + } else { + /* Invalid regs */ return 0; } - if (n < 32) { /* GP regs */ - return gdb_get_reg32(mem_buf, env->regs[n]); - } else if (n == 32) { /* PC */ - return gdb_get_reg32(mem_buf, env->pc); - } else if (n < 49) { /* Status regs */ - return gdb_get_reg32(mem_buf, env->ctrl[n - 33]); - } - - /* Invalid regs */ - return 0; + return gdb_get_reg32(mem_buf, val); } static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) @@ -171,17 +233,25 @@ static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) Nios2CPU *cpu = NIOS2_CPU(cs); CPUClass *cc = CPU_GET_CLASS(cs); CPUNios2State *env = &cpu->env; + uint32_t val; if (n > cc->gdb_num_core_regs) { return 0; } + val = ldl_p(mem_buf); if (n < 32) { /* GP regs */ - env->regs[n] = ldl_p(mem_buf); + env->regs[n] = val; } else if (n == 32) { /* PC */ - env->pc = ldl_p(mem_buf); + env->pc = val; } else if (n < 49) { /* Status regs */ - env->ctrl[n - 33] = ldl_p(mem_buf); + unsigned cr = n - 33; + /* ??? Maybe allow the debugger to write to readonly fields. */ + val &= cpu->cr_state[cr].writable; + val |= cpu->cr_state[cr].readonly & env->ctrl[cr]; + env->ctrl[cr] = val; + } else { + g_assert_not_reached(); } return 4; diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index 08ed3b4598..49fccf2c2c 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -34,6 +34,15 @@ void helper_raise_exception(CPUNios2State *env, uint32_t index) #ifndef CONFIG_USER_ONLY void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc) { + Nios2CPU *cpu = env_archcpu(env); + + /* + * Both estatus and bstatus have no constraints on write; + * do not allow reserved fields in status to be set. + * TODO: more than this is required for shadow registers. + */ + new_status &= cpu->cr_state[CR_STATUS].writable; + env->ctrl[CR_STATUS] = new_status; env->pc = new_pc; cpu_loop_exit(env_cpu(env)); diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 97e531529f..b8d75207a4 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -102,6 +102,7 @@ typedef struct DisasContext { TCGv_i32 zero; target_ulong pc; int mem_idx; + const ControlRegState *cr_state; } DisasContext; static TCGv cpu_R[NUM_GP_REGS]; @@ -471,17 +472,26 @@ static void callr(DisasContext *dc, uint32_t code, uint32_t flags) /* rC <- ctlN */ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) { - R_TYPE(instr, code); - TCGv t1, t2; - if (!gen_check_supervisor(dc)) { return; } +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + R_TYPE(instr, code); + TCGv t1, t2; + if (unlikely(instr.c == R_ZERO)) { return; } + /* Reserved registers read as zero. */ + if (nios2_cr_reserved(&dc->cr_state[instr.imm5])) { + tcg_gen_movi_tl(cpu_R[instr.c], 0); + return; + } + switch (instr.imm5) { case CR_IPENDING: /* @@ -505,6 +515,7 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) offsetof(CPUNios2State, ctrl[instr.imm5])); break; } +#endif } /* ctlN <- rA */ @@ -519,6 +530,14 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags) #else R_TYPE(instr, code); TCGv v = load_gpr(dc, instr.a); + uint32_t ofs = offsetof(CPUNios2State, ctrl[instr.imm5]); + uint32_t wr = dc->cr_state[instr.imm5].writable; + uint32_t ro = dc->cr_state[instr.imm5].readonly; + + /* Skip reserved or readonly registers. */ + if (wr == 0) { + return; + } switch (instr.imm5) { case CR_PTEADDR: @@ -530,17 +549,35 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags) case CR_TLBMISC: gen_helper_mmu_write_tlbmisc(cpu_env, v); break; - case CR_IPENDING: - /* ipending is read only, writes ignored. */ - break; case CR_STATUS: case CR_IENABLE: /* If interrupts were enabled using WRCTL, trigger them. */ dc->base.is_jmp = DISAS_UPDATE; /* fall through */ default: - tcg_gen_st_tl(v, cpu_env, - offsetof(CPUNios2State, ctrl[instr.imm5])); + if (wr == -1) { + /* The register is entirely writable. */ + tcg_gen_st_tl(v, cpu_env, ofs); + } else { + /* + * The register is partially read-only or reserved: + * merge the value. + */ + TCGv n = tcg_temp_new(); + + tcg_gen_andi_tl(n, v, wr); + + if (ro != 0) { + TCGv o = tcg_temp_new(); + tcg_gen_ld_tl(o, cpu_env, ofs); + tcg_gen_andi_tl(o, o, ro); + tcg_gen_or_tl(n, n, o); + tcg_temp_free(o); + } + + tcg_gen_st_tl(n, cpu_env, ofs); + tcg_temp_free(n); + } break; } #endif @@ -818,9 +855,11 @@ static void nios2_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); CPUNios2State *env = cs->env_ptr; + Nios2CPU *cpu = env_archcpu(env); int page_insns; dc->mem_idx = cpu_mmu_index(env, false); + dc->cr_state = cpu->cr_state; /* Bound the number of insns to execute to those left on the page. */ page_insns = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; @@ -932,16 +971,25 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags) } #if !defined(CONFIG_USER_ONLY) - for (i = 0; i < NUM_CR_REGS; i++) { - qemu_fprintf(f, "%9s=%8.8x ", cr_regnames[i], env->ctrl[i]); - if ((i + 1) % 4 == 0) { - qemu_fprintf(f, "\n"); + int j; + + for (i = j = 0; i < NUM_CR_REGS; i++) { + if (!nios2_cr_reserved(&cpu->cr_state[i])) { + qemu_fprintf(f, "%9s=%8.8x ", cr_regnames[i], env->ctrl[i]); + if (++j % 4 == 0) { + qemu_fprintf(f, "\n"); + } } } - qemu_fprintf(f, " mmu write: VPN=%05X PID %02X TLBACC %08X\n", - env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK, - FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID), - env->mmu.tlbacc_wr); + if (j % 4 != 0) { + qemu_fprintf(f, "\n"); + } + if (cpu->mmu_present) { + qemu_fprintf(f, " mmu write: VPN=%05X PID %02X TLBACC %08X\n", + env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK, + FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID), + env->mmu.tlbacc_wr); + } #endif qemu_fprintf(f, "\n\n"); } From patchwork Fri Apr 22 16:52:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564869 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp679947map; Fri, 22 Apr 2022 10:23:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxe5mIIUcSy6KL+XxnMA+Pd7DK3fq0rPE1OoOyX72r5HsR7qExe7FY6dcvSgDYhTZ4FZC27 X-Received: by 2002:ac8:7f0e:0:b0:2f2:672:29b4 with SMTP id f14-20020ac87f0e000000b002f2067229b4mr3975071qtk.592.1650648193361; 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 38/68] target/nios2: Implement cpuid Date: Fri, 22 Apr 2022 09:52:08 -0700 Message-Id: <20220422165238.1971496-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Copy the existing cpu_index into the space reserved for CR_CPUID. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-39-richard.henderson@linaro.org> --- target/nios2/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index b3c5ae681c..a0c3e97d72 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -163,6 +163,7 @@ static void realize_cr_status(CPUState *cs) static void nios2_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); + Nios2CPU *cpu = NIOS2_CPU(cs); Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(dev); Error *local_err = NULL; @@ -176,6 +177,9 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp) qemu_init_vcpu(cs); cpu_reset(cs); + /* We have reserved storage for cpuid; might as well use it. */ + cpu->env.ctrl[CR_CPUID] = cs->cpu_index; + ncc->parent_realize(dev, errp); } From patchwork Fri Apr 22 16:52:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564882 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp690386map; Fri, 22 Apr 2022 10:37:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz9GMibAeOVEcrVuSqr2dTb5vqLXZef8IUsWWvNei9iol0aeV+FQyfpmHWwG55JcE/G8/ME X-Received: by 2002:a81:2d82:0:b0:2f4:d2b6:1864 with SMTP id t124-20020a812d82000000b002f4d2b61864mr6027794ywt.342.1650649064043; Fri, 22 Apr 2022 10:37:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650649064; cv=none; d=google.com; s=arc-20160816; b=Jrml380pMIt15yj7Y/VtYk+DC7afg04GhVtprRgLL1oC5Blt3/wwBThrpKWnrEr2rk bKFnD4xPBNffr4aAx4OS2zBod5ay5WkORghAW2oZbh8Hw+S8qRsqcDoAAbRwm4OuP9gO d264DxDZskIh3Q9XBpppTPakDc5s0VlYrJKowc8KP5A7e8xa68kzfzFRjxaEiLOUB5lf VG/8Otu8jGoMTJ8SNEO1qySuY82U9cIOEq/7QdWRpnY6xGQ7GtZAKHG75RvCm6lV4XSD VEM0RrU1MKa6YQlY/WOqd22Qx1aDryDyRNf/cccBU9pLqLyZi+pxveVKPl/BNZkcICEI HkPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xZiQ5sI/cjyhT5QWt0cEWlmc3OyTlqSds1eKWRRIBd0=; b=M8yDYh+1TDAeqONSkYrLje4ZdpG7F+puVpYfX21pe7kznByflIDIp83jkGc1VLMwAf wNXgSN0OJixoSRgWZBe1IZeUB1D4QKtKPHetYNeTrMo8RbEqAMeIQWwdSA0ppg7nOH8b VNblsFbRS+5bTLS+cx9oj/Le0Z3FIaI81KdAkXvzRiyn1RHOt4zeekdSq7DB7qSi72o7 jKL37fyXg+XZhp3GWS3JytX1Skt/wWI5CWdUelNKk3ctvL5XozrKF7Hb27ZNP+U5c3RG 6MUea5f3aibVjmGy25r+b8gNdNq3+K1URWi4M7CY2FI5dNj7kck7Zm1rPN944237mewt s0ig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Y6lOq6ZS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 39/68] target/nios2: Implement CR_STATUS.RSIE Date: Fri, 22 Apr 2022 09:52:09 -0700 Message-Id: <20220422165238.1971496-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Without EIC, this bit is RES1. So set the bit at reset, and add it to the readonly fields of CR_STATUS. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-40-richard.henderson@linaro.org> --- target/nios2/cpu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index a0c3e97d72..7d734280d1 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -54,9 +54,9 @@ static void nios2_cpu_reset(DeviceState *dev) #if defined(CONFIG_USER_ONLY) /* Start in user mode with interrupts enabled. */ - env->ctrl[CR_STATUS] = CR_STATUS_U | CR_STATUS_PIE; + env->ctrl[CR_STATUS] = CR_STATUS_RSIE | CR_STATUS_U | CR_STATUS_PIE; #else - env->ctrl[CR_STATUS] = 0; + env->ctrl[CR_STATUS] = CR_STATUS_RSIE; #endif } @@ -127,6 +127,7 @@ static void realize_cr_status(CPUState *cs) WR_REG(CR_BADADDR); /* TODO: These control registers are not present with the EIC. */ + RO_FIELD(CR_STATUS, RSIE); WR_REG(CR_IENABLE); RO_REG(CR_IPENDING); From patchwork Fri Apr 22 16:52:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564872 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp682573map; Fri, 22 Apr 2022 10:27:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwO008RRGyH9izOhbmhvYRtGMlzNgjeL9w7eA0U1s1NREUNkjbPdNojV3pFqqZxel6c9rx6 X-Received: by 2002:a81:1242:0:b0:2f7:bb8c:55a3 with SMTP id 63-20020a811242000000b002f7bb8c55a3mr2077260yws.492.1650648432018; Fri, 22 Apr 2022 10:27:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650648432; cv=none; d=google.com; s=arc-20160816; b=KGjBvWD3j5uUqJY3LRx3iWNQNQezwHr6S4NEAT9f+d+s0ks75evQPonV6Gls3ZK7Lp nFizuvbqehCAmPYDtJEcmIMGdE6F/6QcpuTjJqjmoW3f9KOzTvHG5an7O9xkAtYchUv9 GS13U7YumxCL4VTumPkWBpQQErdkzQ/j7BIuqeGb5lTFw0rrsxhQBeHr+KanorwC9nSZ LrvX6/v62rzKBnymlMnkE8M06tUC4psVaGHPTviT/B/h+XzEXj6bmX9qDJwYyxzlJEeY koHO1GfTAORMApHxyJAT3JCk9Av3QU6dxgXTxkf2msXupWMWIdCZPDfrSbu+15SJQ4wF T4Ng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=uxB1TVMzBFwMcUq22tF+jwRMYyOH+mG1cEPhaGtvWVM=; b=t76N2xCr1gNBLOajgdr7pODCBQUgeITAgRq+Zi9Df9J72oW8ZW4M51FEVFKPYQwlMn 71SAEtb/eIjCdtMyX4sfK6KbdI+Djms+pRDPbGySAO+orU4IK+zH5hdK5ixlvDvEGkev EGJ2ef176l7M60vOuRmjwT10E6+ZTWJbLtMFjplfs7aHCEFvunNKMEw3HeFLvj+mrRUT u/L/TyK9R15dKJU6+LiQ47oJcT3X2yDVEJVs231ZtY4OP5nTqTBuRsoEpB51073WfO/j p70coEFeAqHQZb0iRHHwOLcnMu1AyihzYB5yTTurLexxtOEUs849ijp+S/dOh1gt2reH Y4gQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=g0EnqH8q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.56.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:56:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 40/68] target/nios2: Remove CPU_INTERRUPT_NMI Date: Fri, 22 Apr 2022 09:52:10 -0700 Message-Id: <20220422165238.1971496-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d30; envelope-from=richard.henderson@linaro.org; helo=mail-io1-xd30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This interrupt bit is never set, so testing it in nios2_cpu_has_work is pointless. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-41-richard.henderson@linaro.org> --- target/nios2/cpu.h | 2 -- target/nios2/cpu.c | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index da85d82faa..08284d7927 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -177,8 +177,6 @@ FIELD(CR_TLBMISC, EE, 24, 1) #define EXCP_MPUI 16 #define EXCP_MPUD 17 -#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 - struct CPUArchState { uint32_t regs[NUM_GP_REGS]; uint32_t ctrl[NUM_CR_REGS]; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 7d734280d1..58e6ad0462 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -36,7 +36,7 @@ static void nios2_cpu_set_pc(CPUState *cs, vaddr value) static bool nios2_cpu_has_work(CPUState *cs) { - return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); + return cs->interrupt_request & CPU_INTERRUPT_HARD; } static void nios2_cpu_reset(DeviceState *dev) From patchwork Fri Apr 22 16:52:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564876 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp685364map; Fri, 22 Apr 2022 10:31:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzET3dJuDz5cjsWz9/USIs/GFLJ5ig8VYsOWek2mK6Gv0IjoufFuuo+c+lC6GGDDgheukgt X-Received: by 2002:a25:cdca:0:b0:633:c810:6ca with SMTP id d193-20020a25cdca000000b00633c81006camr5578019ybf.261.1650648661044; Fri, 22 Apr 2022 10:31:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650648661; cv=none; d=google.com; s=arc-20160816; b=Mgv90w/hfvrIXpez2xgfPj8MxDqnfaIR0ZJ0HpdaLP+B3jfyc6txlAsKeQciJuvEwg bYPkyI/cJjKGU6T5wtOGFbCFFXh9SCRIED4SyVQl8hOlQxTSBd7gIsRM+1abLn5WZv+b okaxkLQ19mx7jJc9fbBtMdTuUrjA8cMTHrlBl852/rc/km7KHXt8zrq4qEZYQd4shg0E MP4/qDxjXcXIkzDIw5Cs6g+ZfUtc0lT54OaG2efJJz/h7mHrUH91hfD+mUvuh8puzZwG mh7zXcVwDRn02roPMyU4abaUFgqeEkWOrACkmb06Fu2CPEdKD2gNOTVGqfIt+yEKukfa Zsrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6QGUpYO4ZAdRmNsQF40A07J1Y/QTqFdfV+kNvg7ol84=; b=pvT5TIBvBjV0J3p+HGzy6tzYNr1w6wsY+reVg9D55E9P8H5fCsnP1HAaBkiYA0AGn3 6+Y7xWDxbC5Hq0ROJbD0K3Flj/1RmaloCGu9gckA1YCx58NcUB1NDOY7LHUO5MM1YNY/ q5HBuHthsnuIq0fE4tKcG3uHRzdYRjlRZFSZyQS+dlUVt9mF0OnXixLuup1MXlemGVFL Ig8AFaoKEUILmY8EnBZ8my8BvO7629dGfMz9PwXh/cYSMp9uvBwbsTT+IcHk1RpwEctt O5HfGmvmPsX3J1yd+ZCFLAfKNR07r1ysgDIFs1D0oqiPly1ngwy/ar2jgsU8ls/OtA2A UcMw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gQPHBAwB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.56.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:56:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 41/68] target/nios2: Support division error exception Date: Fri, 22 Apr 2022 09:52:11 -0700 Message-Id: <20220422165238.1971496-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::136; envelope-from=richard.henderson@linaro.org; helo=mail-il1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Division may (optionally) raise a division exception. Since the linux kernel has been prepared for this for some time, enable it by default. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-42-richard.henderson@linaro.org> --- target/nios2/cpu.h | 2 ++ target/nios2/helper.h | 2 ++ linux-user/nios2/cpu_loop.c | 4 +++ target/nios2/cpu.c | 1 + target/nios2/helper.c | 4 +++ target/nios2/op_helper.c | 29 ++++++++++++++++++ target/nios2/translate.c | 60 +++++++++++++------------------------ 7 files changed, 62 insertions(+), 40 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 08284d7927..4d63006ffe 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -207,7 +207,9 @@ struct ArchCPU { CPUNegativeOffsetState neg; CPUNios2State env; + bool diverr_present; bool mmu_present; + uint32_t pid_num_bits; uint32_t tlb_num_ways; uint32_t tlb_num_entries; diff --git a/target/nios2/helper.h b/target/nios2/helper.h index 525b6b685b..6f5ec60b0d 100644 --- a/target/nios2/helper.h +++ b/target/nios2/helper.h @@ -19,6 +19,8 @@ */ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) +DEF_HELPER_FLAGS_3(divs, TCG_CALL_NO_WG, s32, env, s32, s32) +DEF_HELPER_FLAGS_3(divu, TCG_CALL_NO_WG, i32, env, i32, i32) #if !defined(CONFIG_USER_ONLY) DEF_HELPER_3(eret, noreturn, env, i32, i32) diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index c5e68ac048..11ecb71843 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -38,6 +38,10 @@ void cpu_loop(CPUNios2State *env) /* just indicate that signals should be handled asap */ break; + case EXCP_DIV: + force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->pc); + break; + case EXCP_TRAP: /* * TODO: This advance should be done in the translator, as diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 58e6ad0462..54e7071907 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -263,6 +263,7 @@ static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) } static Property nios2_properties[] = { + DEFINE_PROP_BOOL("diverr_present", Nios2CPU, diverr_present, true), DEFINE_PROP_BOOL("mmu_present", Nios2CPU, mmu_present, true), /* ALTR,pid-num-bits */ DEFINE_PROP_UINT32("mmu_pid_num_bits", Nios2CPU, pid_num_bits, 8), diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 4d9085f22f..c5a2dd65b1 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -119,6 +119,9 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_UNALIGND: name = "Misaligned (destination)"; break; + case EXCP_DIV: + name = "DIV error"; + break; case EXCP_TRAP: name = "TRAP insn"; break; @@ -187,6 +190,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_SUPERI: case EXCP_ILLEGAL: + case EXCP_DIV: case EXCP_TRAP: do_exception(cpu, cpu->exception_addr, 0, false); break; diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index 49fccf2c2c..a19b504b0e 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -31,6 +31,35 @@ void helper_raise_exception(CPUNios2State *env, uint32_t index) cpu_loop_exit(cs); } +static void maybe_raise_div(CPUNios2State *env, uintptr_t ra) +{ + Nios2CPU *cpu = env_archcpu(env); + CPUState *cs = env_cpu(env); + + if (cpu->diverr_present) { + cs->exception_index = EXCP_DIV; + cpu_loop_exit_restore(cs, ra); + } +} + +int32_t helper_divs(CPUNios2State *env, int32_t num, int32_t den) +{ + if (unlikely(den == 0) || unlikely(den == -1 && num == INT32_MIN)) { + maybe_raise_div(env, GETPC()); + return num; /* undefined */ + } + return num / den; +} + +uint32_t helper_divu(CPUNios2State *env, uint32_t num, uint32_t den) +{ + if (unlikely(den == 0)) { + maybe_raise_div(env, GETPC()); + return num; /* undefined */ + } + return num / den; +} + #ifndef CONFIG_USER_ONLY void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc) { diff --git a/target/nios2/translate.c b/target/nios2/translate.c index b8d75207a4..b27269bf08 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -654,59 +654,39 @@ gen_r_shift_s(ror, rotr_tl) static void divs(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, (code)); + TCGv dest; - /* Stores into R_ZERO are ignored */ - if (unlikely(instr.c == R_ZERO)) { - return; + if (instr.c == R_ZERO) { + dest = tcg_temp_new(); + } else { + dest = cpu_R[instr.c]; } - TCGv t0 = tcg_temp_new(); - TCGv t1 = tcg_temp_new(); - TCGv t2 = tcg_temp_new(); - TCGv t3 = tcg_temp_new(); + gen_helper_divs(dest, cpu_env, + load_gpr(dc, instr.a), load_gpr(dc, instr.b)); - tcg_gen_ext32s_tl(t0, load_gpr(dc, instr.a)); - tcg_gen_ext32s_tl(t1, load_gpr(dc, instr.b)); - tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN); - tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); - tcg_gen_and_tl(t2, t2, t3); - tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); - tcg_gen_or_tl(t2, t2, t3); - tcg_gen_movi_tl(t3, 0); - tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); - tcg_gen_div_tl(cpu_R[instr.c], t0, t1); - tcg_gen_ext32s_tl(cpu_R[instr.c], cpu_R[instr.c]); - - tcg_temp_free(t3); - tcg_temp_free(t2); - tcg_temp_free(t1); - tcg_temp_free(t0); + if (instr.c == R_ZERO) { + tcg_temp_free(dest); + } } static void divu(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, (code)); + TCGv dest; - /* Stores into R_ZERO are ignored */ - if (unlikely(instr.c == R_ZERO)) { - return; + if (instr.c == R_ZERO) { + dest = tcg_temp_new(); + } else { + dest = cpu_R[instr.c]; } - TCGv t0 = tcg_temp_new(); - TCGv t1 = tcg_temp_new(); - TCGv t2 = tcg_const_tl(0); - TCGv t3 = tcg_const_tl(1); + gen_helper_divu(dest, cpu_env, + load_gpr(dc, instr.a), load_gpr(dc, instr.b)); - tcg_gen_ext32u_tl(t0, load_gpr(dc, instr.a)); - tcg_gen_ext32u_tl(t1, load_gpr(dc, instr.b)); - tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); - tcg_gen_divu_tl(cpu_R[instr.c], t0, t1); - tcg_gen_ext32s_tl(cpu_R[instr.c], cpu_R[instr.c]); - - tcg_temp_free(t3); - tcg_temp_free(t2); - tcg_temp_free(t1); - tcg_temp_free(t0); + if (instr.c == R_ZERO) { + tcg_temp_free(dest); + } } static void trap(DisasContext *dc, uint32_t code, uint32_t flags) From patchwork Fri Apr 22 16:52:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564880 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp688131map; Fri, 22 Apr 2022 10:34:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyurYW2T/3NCUqlN4T1bM98r7C2BjrZR7yEYPAjWGWEHshgDFnJXczf3fj6aRCsxcHdfeCr X-Received: by 2002:a25:fe0c:0:b0:641:2884:2c7e with SMTP id k12-20020a25fe0c000000b0064128842c7emr5392077ybe.382.1650648874393; Fri, 22 Apr 2022 10:34:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650648874; cv=none; d=google.com; s=arc-20160816; b=O0fn+lk/FF57AxNsXjkNrmCEvEYg7Mi98AJ6iYBIxwe/8hyZRYqoZ3y1FFNqm8A74W JI8bui55dx/utJwj/id9jBsYRkGDbfVMBFQ7BH3TIIqJMf6q9YgjQfliSvSJyNBdbkVC AWhjBoo/G9rvNRT7efZjt/LiX/ISEbdH6vnQ7vWcQJ6Iv+BmtAIFgrx+L+oAx1URrxJV VyWyYY+1MSykiyv2p/v7XpJSvq0+RKi8gFFTaMgxQhhndJjuwwLUMiMYPEn4Srm2X7zR Ds2iR075zoFS+NslI366h2fMNVuCQ5Mg7uiMRP44NemxQHjkbSfZ9PxzcW62Pc8NkDQS m11g== ARC-Message-Signature: i=1; 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.56.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:56:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 42/68] target/nios2: Use tcg_constant_tl Date: Fri, 22 Apr 2022 09:52:12 -0700 Message-Id: <20220422165238.1971496-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d34; envelope-from=richard.henderson@linaro.org; helo=mail-io1-xd34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Replace current uses of tcg_const_tl, and remove the frees. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-43-richard.henderson@linaro.org> --- target/nios2/translate.c | 30 ++++++------------------------ 1 file changed, 6 insertions(+), 24 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index b27269bf08..f33015f942 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -99,7 +99,6 @@ typedef struct DisasContext { DisasContextBase base; - TCGv_i32 zero; target_ulong pc; int mem_idx; const ControlRegState *cr_state; @@ -125,31 +124,20 @@ static uint8_t get_opxcode(uint32_t code) return instr.opx; } -static TCGv load_zero(DisasContext *dc) +static TCGv load_gpr(DisasContext *dc, unsigned reg) { - if (!dc->zero) { - dc->zero = tcg_const_i32(0); - } - return dc->zero; -} - -static TCGv load_gpr(DisasContext *dc, uint8_t reg) -{ - if (likely(reg != R_ZERO)) { - return cpu_R[reg]; - } else { - return load_zero(dc); + assert(reg < NUM_GP_REGS); + if (unlikely(reg == R_ZERO)) { + return tcg_constant_tl(0); } + return cpu_R[reg]; } static void t_gen_helper_raise_exception(DisasContext *dc, uint32_t index) { - TCGv_i32 tmp = tcg_const_i32(index); - tcg_gen_movi_tl(cpu_pc, dc->pc); - gen_helper_raise_exception(cpu_env, tmp); - tcg_temp_free_i32(tmp); + gen_helper_raise_exception(cpu_env, tcg_constant_i32(index)); dc->base.is_jmp = DISAS_NORETURN; } @@ -876,14 +864,8 @@ static void nios2_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) return; } - dc->zero = NULL; - instr = &i_type_instructions[op]; instr->handler(dc, code, instr->flags); - - if (dc->zero) { - tcg_temp_free(dc->zero); - } } static void nios2_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) From patchwork Fri Apr 22 16:52:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564875 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp684404map; Fri, 22 Apr 2022 10:29:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzgA04Ih97AOsTz+xtHe46CptAXtv+eI2W5g8wd4EdWdfrgAFdk36edhINRj25pWiMJzCgZ X-Received: by 2002:a25:e044:0:b0:645:682b:24fd with SMTP id x65-20020a25e044000000b00645682b24fdmr5193607ybg.159.1650648582699; Fri, 22 Apr 2022 10:29:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650648582; cv=none; d=google.com; s=arc-20160816; b=FryfvQwhrza6etRrTnr2m4XiSC++IlXdN7cVZalC/UsTnE7rCNQ80MNGuytJ81/v1/ Znh1ayTW9R61oBd9ZdD1HxB+w8YFzFc0t+MKHrjO8Ifowmx0sPfNqIttRaKWqQIziWE1 mNvAt2vNH5D8VOjzp8imtOPG9ciFijRHgLUD/UwrIOaNblETOBS+oDFH8B0eZrDaNuAt ruRlcdWbuRnWBgjc2nLwB4BA5DXhnN7XYjcyNIPHXIsyvW4kMN0g04d1j2DpejvWLs1X xwKRbjwqZ6FXoTNc/A6BqKVQ3xMeAnZrFanmfK/aUVxDDLicxx1AYGhP2BukEvRLRLI/ aGMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1DWNIJERXpZmtblRaXcb0XPGH7uKHZT6j2hdc+1VfWU=; b=sUFhEW89AOVloq7hnA9OwQStKpzXGuTAR3eFmjx5jwi1ArNbSDLL7c3KstwW/eTV6T 4thC7f30UNLQo8CX9r/j4Dy+IQmpZUSLUHvdWp3NkDkJIvgAbFwjBUlwjGY85Hx4qWvE hFT2B8uzcTWMZYwAcPx78eek0aahdLW+gOqRAfuWaOt95T+Ljap3DYAHxTpN/KzwL3o6 rvzxsFbbqGu/Yv5mIRsWqk/K8ef/+KqeeJQxfLJkBGCfGOuCE2vwQEwZLdccSg9MxgMC NAHieL5nYxlnY4+wYxIgxKy2D0WIKn3Ky+GkGwPQ15RSDtU3kIEbcEL59Bl1hVbjp1pb gWLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GayDKhGp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.56.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:56:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 43/68] target/nios2: Split out named structs for [IRJ]_TYPE Date: Fri, 22 Apr 2022 09:52:13 -0700 Message-Id: <20220422165238.1971496-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d2c; envelope-from=richard.henderson@linaro.org; helo=mail-io1-xd2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Currently the structures are anonymous within the macro. Pull them out to standalone types. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20220421151735.31996-44-richard.henderson@linaro.org> --- target/nios2/translate.c | 48 ++++++++++++++++++++++------------------ 1 file changed, 27 insertions(+), 21 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index f33015f942..a3c63dbbbd 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -53,16 +53,18 @@ #define INSN_R_TYPE 0x3A /* I-Type instruction parsing */ +typedef struct { + uint8_t op; + union { + uint16_t u; + int16_t s; + } imm16; + uint8_t b; + uint8_t a; +} InstrIType; + #define I_TYPE(instr, code) \ - struct { \ - uint8_t op; \ - union { \ - uint16_t u; \ - int16_t s; \ - } imm16; \ - uint8_t b; \ - uint8_t a; \ - } (instr) = { \ + InstrIType (instr) = { \ .op = extract32((code), 0, 6), \ .imm16.u = extract32((code), 6, 16), \ .b = extract32((code), 22, 5), \ @@ -70,15 +72,17 @@ } /* R-Type instruction parsing */ +typedef struct { + uint8_t op; + uint8_t imm5; + uint8_t opx; + uint8_t c; + uint8_t b; + uint8_t a; +} InstrRType; + #define R_TYPE(instr, code) \ - struct { \ - uint8_t op; \ - uint8_t imm5; \ - uint8_t opx; \ - uint8_t c; \ - uint8_t b; \ - uint8_t a; \ - } (instr) = { \ + InstrRType (instr) = { \ .op = extract32((code), 0, 6), \ .imm5 = extract32((code), 6, 5), \ .opx = extract32((code), 11, 6), \ @@ -88,11 +92,13 @@ } /* J-Type instruction parsing */ +typedef struct { + uint8_t op; + uint32_t imm26; +} InstrJType; + #define J_TYPE(instr, code) \ - struct { \ - uint8_t op; \ - uint32_t imm26; \ - } (instr) = { \ + InstrJType (instr) = { \ .op = extract32((code), 0, 6), \ .imm26 = extract32((code), 6, 26), \ } From patchwork Fri Apr 22 16:52:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564873 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp683538map; Fri, 22 Apr 2022 10:28:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxT3igkthWS+Z9LQhPmZ0eQ83TAH2Qu9+FyyIP96C+xl5tSM1YJqDXDX/EWHyCadWFuUz2r X-Received: by 2002:a0d:eb4e:0:b0:2f4:dbd9:6e64 with SMTP id u75-20020a0deb4e000000b002f4dbd96e64mr5911161ywe.486.1650648499748; Fri, 22 Apr 2022 10:28:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650648499; cv=none; d=google.com; s=arc-20160816; b=bO+0tlAZuKKKxhNiMZC/fUAnuXpfuI/lj0JOOg74mXrNt8ZDaTdq4s8/pCqiyyA/IS yu538pGA9teqbWbklsoIVZE0jA0rylkbscx83IsSNAVaUhrBklI9NUe4/R89If6GX1/n BSD773rCzSj6zsdA4wH4GzFgU6z1tO060UZrN2c7Jea3KGCMKhSoYnBDKJOFRF5gBPQo xsEWFSPRpbH1BuLoSVFOwcbMmDPJ8vWGdZMXRvCJi3YSz+c86PJQLLN6kY2eQMGn1JhA AaTZklPQvatu/a0LKR10IeJ52/o0pT5LHZbL7wBcn4mg3cJ/QyvIjhqJ37fzoJtZK/as OCHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=zCoM+nxCW+KhPaK3jdR/NXDiI5y1zUCOgbetADXQNIY=; b=Z5cSdn1lPNOE+FAb10AkiLvCWGweSp/Ckss/Q7ba0bNfeK3wNHYALc7gRaBC/z7Lji DyA/gSP2uPyMufcCRDghK1k7W5xkGvCv/8AEZs+U9CgtWnpdY05lAdRFJihzWPi6ufRL /qGem+OsjAnk1AC+cnFfN+Njlb0Cz84SkUXzubfQI3OFBIU6eU43py7DF8E+6YMO1AFC 7ZeF3q7FQsMfxAWnVadafnNLnnwFR2a9A+bTMs/QAlkyyZDbkhjOGucFtHiqZFfIAt42 RHEFzuSfZAiOmz6Pm/U1I93pIA3PnpfrTmHCjcd94ph0cSPN/DaQM0dQ3Bpc2m2PdNKy p7hQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uS1aPitE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.56.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:57:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 44/68] target/nios2: Split out helpers for gen_i_cmpxx Date: Fri, 22 Apr 2022 09:52:14 -0700 Message-Id: <20220422165238.1971496-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::131; envelope-from=richard.henderson@linaro.org; helo=mail-il1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Do as little work as possible within the macro. Split out helper functions and pass in arguments instead. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/translate.c | 34 +++++++++++++++++++++++++++------- 1 file changed, 27 insertions(+), 7 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index a3c63dbbbd..86978ba47a 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -71,6 +71,18 @@ typedef struct { .a = extract32((code), 27, 5), \ } +typedef target_ulong ImmFromIType(const InstrIType *); + +static target_ulong imm_unsigned(const InstrIType *i) +{ + return i->imm16.u; +} + +static target_ulong imm_signed(const InstrIType *i) +{ + return i->imm16.s; +} + /* R-Type instruction parsing */ typedef struct { uint8_t op; @@ -268,15 +280,23 @@ static void gen_bxx(DisasContext *dc, uint32_t code, uint32_t flags) } /* Comparison instructions */ -#define gen_i_cmpxx(fname, op3) \ -static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \ -{ \ - I_TYPE(instr, (code)); \ - tcg_gen_setcondi_tl(flags, cpu_R[instr.b], cpu_R[instr.a], (op3)); \ +static void do_i_cmpxx(DisasContext *dc, uint32_t insn, + TCGCond cond, ImmFromIType *imm) +{ + I_TYPE(instr, insn); + + if (likely(instr.b != R_ZERO)) { + tcg_gen_setcondi_tl(cond, cpu_R[instr.b], + load_gpr(dc, instr.a), imm(&instr)); + } } -gen_i_cmpxx(gen_cmpxxsi, instr.imm16.s) -gen_i_cmpxx(gen_cmpxxui, instr.imm16.u) +#define gen_i_cmpxx(fname, imm) \ + static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \ + { do_i_cmpxx(dc, code, flags, imm); } + +gen_i_cmpxx(gen_cmpxxsi, imm_signed) +gen_i_cmpxx(gen_cmpxxui, imm_unsigned) /* Math/logic instructions */ #define gen_i_math_logic(fname, insn, resimm, op3) \ From patchwork Fri Apr 22 16:52:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564879 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp687732map; Fri, 22 Apr 2022 10:34:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxOIX2Uh7z9/hs1Rm3gjq0/gjerJGn9xtpzN0EqMasP/jlh/tuDOekcHXIVtj91SuVPYb0W X-Received: by 2002:a25:af4e:0:b0:645:1658:e1a7 with SMTP id c14-20020a25af4e000000b006451658e1a7mr5737986ybj.642.1650648844539; Fri, 22 Apr 2022 10:34:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650648844; cv=none; d=google.com; s=arc-20160816; b=LGlk1rPaMq5lINJqExmdtT6tEhl+6V2pEcNGm1iTbBjLF6FqI1eTZep0w1zG90lbD6 kMxIbzjrslMeJhQTNPa9RzJZ24ORpDTtiXTVg83m9zQkISpJ+l24ufCGbJPa4yX2kCNt peuC9VOMlBmUBIRQg/NIBQ4ZAcNvJfLUxjvRii9Em1/WKqb7AvqFgTKs+vrXJ8TNB99V 7mailzmkO1mEIhk7sR5wQFc9OL+Q7AjsPqoEF7C9gPq3OVi8/vrmeCdoaTVVaLpUNm/H sBAZXFoTBWzdaIbJy/tf7Rfg71YAcbTtSIhLYQ2J+S6ovWqDLt8v20Md0HCRP7xcCKZt WdfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=GcYpZGanzuGeVbXLR1g1V1bbBLnv47df/wapXgxg8sU=; b=fsc064JB/VND0i/JQOin+vQxYvgZMbX8iER++IDdngAThyyMEkKoAXftMfZwhyMc7R x9jyrOXktqQJPm30AJ3mHfkm61IEjANrxkurMBcucfjADA3AmdoNCu8MwlEVvOoGS+X7 /K2lERyLYJoLWm1QK6n9CuIe2BU9bfS8R/qmCM+i+mOvuwhwfvE42VmgxUSkemCNMchD L/W6aQFbG/rHRj0birk7bP/CL7+UVWdUYLAW45aqKeR4PKno6srcDyhvD54e3/i4xvab dwz8PKSK0pTFVRry96yJaRMiwXYEKNqZp+2DvPz6J/moJq3otoueAXAvk14i5d0SIZH0 S5Tg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dfKfu7+0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.57.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:57:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 45/68] target/nios2: Split out helpers for gen_i_math_logic Date: Fri, 22 Apr 2022 09:52:15 -0700 Message-Id: <20220422165238.1971496-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d2d; envelope-from=richard.henderson@linaro.org; helo=mail-io1-xd2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Do as little work as possible within the macro. Split out helper functions and pass in arguments instead. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/translate.c | 58 +++++++++++++++++++++++++++------------- 1 file changed, 39 insertions(+), 19 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 86978ba47a..aa570b6d79 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -83,6 +83,11 @@ static target_ulong imm_signed(const InstrIType *i) return i->imm16.s; } +static target_ulong imm_shifted(const InstrIType *i) +{ + return i->imm16.u << 16; +} + /* R-Type instruction parsing */ typedef struct { uint8_t op; @@ -115,6 +120,8 @@ typedef struct { .imm26 = extract32((code), 6, 26), \ } +typedef void GenFn2i(TCGv, TCGv, target_long); + typedef struct DisasContext { DisasContextBase base; target_ulong pc; @@ -299,29 +306,42 @@ gen_i_cmpxx(gen_cmpxxsi, imm_signed) gen_i_cmpxx(gen_cmpxxui, imm_unsigned) /* Math/logic instructions */ -#define gen_i_math_logic(fname, insn, resimm, op3) \ -static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \ -{ \ - I_TYPE(instr, (code)); \ - if (unlikely(instr.b == R_ZERO)) { /* Store to R_ZERO is ignored */ \ - return; \ - } else if (instr.a == R_ZERO) { /* MOVxI optimizations */ \ - tcg_gen_movi_tl(cpu_R[instr.b], (resimm) ? (op3) : 0); \ - } else { \ - tcg_gen_##insn##_tl(cpu_R[instr.b], cpu_R[instr.a], (op3)); \ - } \ +static void do_i_math_logic(DisasContext *dc, uint32_t insn, + GenFn2i *fn, ImmFromIType *imm, + bool x_op_0_eq_x) +{ + I_TYPE(instr, insn); + target_ulong val; + + if (unlikely(instr.b == R_ZERO)) { + /* Store to R_ZERO is ignored -- this catches the canonical NOP. */ + return; + } + + val = imm(&instr); + + if (instr.a == R_ZERO) { + /* This catches the canonical expansions of movi and movhi. */ + tcg_gen_movi_tl(cpu_R[instr.b], x_op_0_eq_x ? val : 0); + } else { + fn(cpu_R[instr.b], cpu_R[instr.a], val); + } } -gen_i_math_logic(addi, addi, 1, instr.imm16.s) -gen_i_math_logic(muli, muli, 0, instr.imm16.s) +#define gen_i_math_logic(fname, insn, x_op_0, imm) \ + static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \ + { do_i_math_logic(dc, code, tcg_gen_##insn##_tl, imm, x_op_0); } -gen_i_math_logic(andi, andi, 0, instr.imm16.u) -gen_i_math_logic(ori, ori, 1, instr.imm16.u) -gen_i_math_logic(xori, xori, 1, instr.imm16.u) +gen_i_math_logic(addi, addi, 1, imm_signed) +gen_i_math_logic(muli, muli, 0, imm_signed) -gen_i_math_logic(andhi, andi, 0, instr.imm16.u << 16) -gen_i_math_logic(orhi , ori, 1, instr.imm16.u << 16) -gen_i_math_logic(xorhi, xori, 1, instr.imm16.u << 16) +gen_i_math_logic(andi, andi, 0, imm_unsigned) +gen_i_math_logic(ori, ori, 1, imm_unsigned) +gen_i_math_logic(xori, xori, 1, imm_unsigned) + +gen_i_math_logic(andhi, andi, 0, imm_shifted) +gen_i_math_logic(orhi , ori, 1, imm_shifted) +gen_i_math_logic(xorhi, xori, 1, imm_shifted) /* Prototype only, defined below */ static void handle_r_type_instr(DisasContext *dc, uint32_t code, From patchwork Fri Apr 22 16:52:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564883 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp690803map; Fri, 22 Apr 2022 10:38:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw0I3aKqzQCSlgMxTnwGQGoae8pyTjdgH8/w9c51lY4jVoLn4/jIDfPbV7f0BoWcxQ9yX9K X-Received: by 2002:a81:dc3:0:b0:2ec:33e8:49dd with SMTP id 186-20020a810dc3000000b002ec33e849ddmr5928518ywn.214.1650649097124; Fri, 22 Apr 2022 10:38:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650649097; cv=none; d=google.com; s=arc-20160816; b=YF24K+Srj1/k39euyK1RSFWSJzQtcgin5HSg/Y/SqF1r4GXD5qeW0nbgGpRSVhzLzA YL5zxzHdlPGBUYciZXRWeWEw2xcsweZn8ivp18QM/m4RVuYMlNlpsahMfQWz7oOJxuP7 u7XupMC8nc205cDY24mip2nfhU/FjpfvUCj9aqDN7oNqWgp3D987Yjccum7215isMJ5q R8Z1EWVu8giD9EeiAc1DkJqY4mOJdJ1D0tIzqzpHysdxlKsD5sMlG1xjuLoqO1T8707/ 0fK9217Krf7MK3HFulqKAoNi6sv8/AFxpfn0tjrD/QeLir8qbP+pp7e239dGg5WAAo8G B9sw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3+xpTVDecc7cNEyZfsWnLhG5F+1r9PluCtiZXsENmzo=; b=0NJgQ8yDmAArJyMTJF/ytSPGSSBqGL0oJDGq6mHhukRbO7rPquOCdy0m8ca1lftj98 aNAurYnVEvrh6Xi7DWAfozGgaz09NqAHWmamSBx4z6i4XjZ5DWHkw8KjGXS8FkqqgUI1 Pa+g0RnpNErL8ssgBmpscVnvcODHgZXPAsO5p86goqDVrM6ZkiRL9hL8VwQDAviN1nvV /sG6DpIqegwvpEM2oK8y0a5UMyNEdOoODDuMfGHLhTts2+X3yzWMqXv1R756EItoyZ27 vS7h99TMLWh9SHKvJ6y78G3uTiW3ywqL3BY5RCq2x55SBUoRDnR2JSebwZxBXyhnre93 2eOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=r2RBbBg+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.57.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:57:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 46/68] target/nios2: Split out helpers for gen_r_math_logic Date: Fri, 22 Apr 2022 09:52:16 -0700 Message-Id: <20220422165238.1971496-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d29; envelope-from=richard.henderson@linaro.org; helo=mail-io1-xd29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split the macro in two, one for reg/imm and one for reg/reg. Do as little work as possible within the macros; split out helper functions and pass in arguments instead. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/translate.c | 54 ++++++++++++++++++++++++++-------------- 1 file changed, 36 insertions(+), 18 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index aa570b6d79..4f52606516 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -121,6 +121,7 @@ typedef struct { } typedef void GenFn2i(TCGv, TCGv, target_long); +typedef void GenFn3(TCGv, TCGv, TCGv); typedef struct DisasContext { DisasContextBase base; @@ -628,28 +629,45 @@ static void gen_cmpxx(DisasContext *dc, uint32_t code, uint32_t flags) } /* Math/logic instructions */ -#define gen_r_math_logic(fname, insn, op3) \ -static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \ -{ \ - R_TYPE(instr, (code)); \ - if (likely(instr.c != R_ZERO)) { \ - tcg_gen_##insn(cpu_R[instr.c], load_gpr((dc), instr.a), (op3)); \ - } \ +static void do_ri_math_logic(DisasContext *dc, uint32_t insn, GenFn2i *fn) +{ + R_TYPE(instr, insn); + + if (likely(instr.c != R_ZERO)) { + fn(cpu_R[instr.c], load_gpr(dc, instr.a), instr.imm5); + } } -gen_r_math_logic(add, add_tl, load_gpr(dc, instr.b)) -gen_r_math_logic(sub, sub_tl, load_gpr(dc, instr.b)) -gen_r_math_logic(mul, mul_tl, load_gpr(dc, instr.b)) +static void do_rr_math_logic(DisasContext *dc, uint32_t insn, GenFn3 *fn) +{ + R_TYPE(instr, insn); -gen_r_math_logic(and, and_tl, load_gpr(dc, instr.b)) -gen_r_math_logic(or, or_tl, load_gpr(dc, instr.b)) -gen_r_math_logic(xor, xor_tl, load_gpr(dc, instr.b)) -gen_r_math_logic(nor, nor_tl, load_gpr(dc, instr.b)) + if (likely(instr.c != R_ZERO)) { + fn(cpu_R[instr.c], load_gpr(dc, instr.a), load_gpr(dc, instr.b)); + } +} -gen_r_math_logic(srai, sari_tl, instr.imm5) -gen_r_math_logic(srli, shri_tl, instr.imm5) -gen_r_math_logic(slli, shli_tl, instr.imm5) -gen_r_math_logic(roli, rotli_tl, instr.imm5) +#define gen_ri_math_logic(fname, insn) \ + static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \ + { do_ri_math_logic(dc, code, tcg_gen_##insn##_tl); } + +#define gen_rr_math_logic(fname, insn) \ + static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \ + { do_rr_math_logic(dc, code, tcg_gen_##insn##_tl); } + +gen_rr_math_logic(add, add) +gen_rr_math_logic(sub, sub) +gen_rr_math_logic(mul, mul) + +gen_rr_math_logic(and, and) +gen_rr_math_logic(or, or) +gen_rr_math_logic(xor, xor) +gen_rr_math_logic(nor, nor) + +gen_ri_math_logic(srai, sari) +gen_ri_math_logic(srli, shri) +gen_ri_math_logic(slli, shli) +gen_ri_math_logic(roli, rotli) #define gen_r_mul(fname, insn) \ static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \ From patchwork Fri Apr 22 16:52:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564884 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp691921map; Fri, 22 Apr 2022 10:39:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxTajn6Q1N36igiHPgfQwI3m4cyoQjSg2PUcKiaaBDYuP41EA5riIb0ZfpqmY6eirHj0Qqz X-Received: by 2002:a05:620a:2886:b0:699:bab7:ae78 with SMTP id j6-20020a05620a288600b00699bab7ae78mr3369773qkp.618.1650649192121; Fri, 22 Apr 2022 10:39:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650649192; cv=none; d=google.com; s=arc-20160816; b=J6sal1OynqHmbHng1wN4wgHPSFrWl6WZoLApd2nSEMXqlHX5jjtlFSv5hVmKaTTMkY 4gx/e97w8ao8YQBDkuC2cuRmZ5sJ1xZtmjZuNsj0q/GUsCiGDajarC+3VyqiZ3SRuujn 94+GmDwGNx8rWjOCJmSgpDuIihqMaL3oRj51/OK+xgxdR1p0trBDQ6zXijeZNQ4jlLJt vvvwSlzwiKzAgawKACXU6UYO+vy4eO8tA+j0OkodIPpuPbLU3Buo3C/ohY6C1PMFnOiA Ei5ojYG1yz/jrJnsDxLrPahNUwmcjP1iyL/H4tZFaUS9edCDd+1wXh6plElZmVcFbxoC kbIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=yLnKk6KeXtnOdH9WAfFyAEdKebgTI3uohXWuThUdcek=; b=Rki7F/94NI00Tlmy4x/KrGoFC08cgk0seSWmKzQ6aAIYx/k6q3m+KZYu0pgEdCpE0I Os1kinhll4cDHWU5TRF4+lsem3OiJxl47ETtMpo7uv2W0sIUJlUwrk8JTXGnIR+eqkPp 1IGxTjefFrIwsDoOl2e716sOUyYj7C8D6uhWwLGGK1mfc/omCIFX7H0VIbshyGbI0WcN CRjF3lSggfXJOv/68sc5gCzpn2lxSZREX51o14olyJesOZKY6DMy1e6CTnmsf/X8R3CG ZwNsA+On/hEeiAoxsgNQgzq1oby6+Pzoq+ZCLAMIYwWg5oKOgdNcOk5FUFPhy3qRcJoJ B/nw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FVxODr7q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.57.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:57:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 47/68] target/nios2: Split out helpers for gen_rr_mul_high Date: Fri, 22 Apr 2022 09:52:17 -0700 Message-Id: <20220422165238.1971496-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::134; envelope-from=richard.henderson@linaro.org; helo=mail-il1-x134.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rename the macro from gen_r_mul, because these are the multiply variants that produce a high-part result. Do as little work as possible within the macro; split out helper functions and pass in arguments instead. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/translate.c | 31 ++++++++++++++++++------------- 1 file changed, 18 insertions(+), 13 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 4f52606516..5979427c8e 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -122,6 +122,7 @@ typedef struct { typedef void GenFn2i(TCGv, TCGv, target_long); typedef void GenFn3(TCGv, TCGv, TCGv); +typedef void GenFn4(TCGv, TCGv, TCGv, TCGv); typedef struct DisasContext { DisasContextBase base; @@ -669,21 +670,25 @@ gen_ri_math_logic(srli, shri) gen_ri_math_logic(slli, shli) gen_ri_math_logic(roli, rotli) -#define gen_r_mul(fname, insn) \ -static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \ -{ \ - R_TYPE(instr, (code)); \ - if (likely(instr.c != R_ZERO)) { \ - TCGv t0 = tcg_temp_new(); \ - tcg_gen_##insn(t0, cpu_R[instr.c], \ - load_gpr(dc, instr.a), load_gpr(dc, instr.b)); \ - tcg_temp_free(t0); \ - } \ +static void do_rr_mul_high(DisasContext *dc, uint32_t insn, GenFn4 *fn) +{ + R_TYPE(instr, insn); + + if (likely(instr.c != R_ZERO)) { + TCGv discard = tcg_temp_new(); + fn(discard, cpu_R[instr.c], load_gpr(dc, instr.a), + load_gpr(dc, instr.b)); + tcg_temp_free(discard); + } } -gen_r_mul(mulxss, muls2_tl) -gen_r_mul(mulxuu, mulu2_tl) -gen_r_mul(mulxsu, mulsu2_tl) +#define gen_rr_mul_high(fname, insn) \ + static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \ + { do_rr_mul_high(dc, code, tcg_gen_##insn##_tl); } + +gen_rr_mul_high(mulxss, muls2) +gen_rr_mul_high(mulxuu, mulu2) +gen_rr_mul_high(mulxsu, mulsu2) #define gen_r_shift_s(fname, insn) \ static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \ From patchwork Fri Apr 22 16:52:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564887 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp696290map; Fri, 22 Apr 2022 10:45:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyt/HTmW0y0xQtQvnED1sFqUE1I4RCj2pK35IXPB2HaAWniNJCa6hKTJjBWvEmRp+uAOJNw X-Received: by 2002:a25:4904:0:b0:642:22e:7440 with SMTP id w4-20020a254904000000b00642022e7440mr5551526yba.635.1650649546306; Fri, 22 Apr 2022 10:45:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650649546; cv=none; d=google.com; s=arc-20160816; b=z2/M+pgPV4mbSAuO0DHz+ocnl0hLycp5P1ZSmo6IQ0xJ8b7yTnp7PAx0iLDtfv29o6 cai+DDfuSVnZ7J9NujD8hAOV0YxIMGJ8ho6EvAjyF8gadWGswLQWj5YQaUIKaRz06U5k ip5f9NAsQcC3KhN+zCAM+eSXaVqwRCtSobFWZn/Qspz0RBPOqsPGgssYBUFJ9QSP0ibn +pl587hpXKuRFT2Qqtqamzw9skGSjNdM7CBGzU5faxfP0v4kBsY5ICZmBISdRM9WxZHe PVYcSWGYifnd2CTmHzmKFUxbo/dWSzz/FG/Zop9e3ZAZztoC9GWDuJWwR7NinC8yV6mv jInQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=PLNGcYz2iEfQ9Yx39pQmGnFw0rJ+PViSHW2oP88vmqI=; b=gQSFRlcwRxlqrNRaB2XtUOlXSV5chCfFlKXy2u6hkvI0XsH+jSx/w7pxKIbUQCOz88 5CyP6baWSlocJj23bPBtf4fHHtE0YIPw6jAunYorp/52AN6zO+6YwxI2x4lcKMKEmG8j tmzB7zhvL1OTNcoVKzUwWztoFdrWI7EBrNQgpUgaaL0+tIe4DtyL4rRSyNwPxvOSXsmu Wn+VIxjuAXMWQP9y6fa136EzmOL8k6kY+HNqcXfbGK3oeAOGw9az3fUvrdFs9fp1v+yJ /9c+N4J47D02gYKYeJ+9ySAytqzM/aH3ZP71EC/qNnOgBmEJBAqRALpgmT2jh8Tc+s2v NqbA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=s2r8JQcg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.57.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:57:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 48/68] target/nios2: Split out helpers for gen_rr_shift Date: Fri, 22 Apr 2022 09:52:18 -0700 Message-Id: <20220422165238.1971496-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d32; envelope-from=richard.henderson@linaro.org; helo=mail-io1-xd32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Do as little work as possible within the macro. Split out helper functions and pass in arguments instead. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/translate.c | 35 ++++++++++++++++++++--------------- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 5979427c8e..f2dcaa3fbb 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -690,23 +690,28 @@ gen_rr_mul_high(mulxss, muls2) gen_rr_mul_high(mulxuu, mulu2) gen_rr_mul_high(mulxsu, mulsu2) -#define gen_r_shift_s(fname, insn) \ -static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \ -{ \ - R_TYPE(instr, (code)); \ - if (likely(instr.c != R_ZERO)) { \ - TCGv t0 = tcg_temp_new(); \ - tcg_gen_andi_tl(t0, load_gpr((dc), instr.b), 31); \ - tcg_gen_##insn(cpu_R[instr.c], load_gpr((dc), instr.a), t0); \ - tcg_temp_free(t0); \ - } \ +static void do_rr_shift(DisasContext *dc, uint32_t insn, GenFn3 *fn) +{ + R_TYPE(instr, insn); + + if (likely(instr.c != R_ZERO)) { + TCGv sh = tcg_temp_new(); + + tcg_gen_andi_tl(sh, load_gpr(dc, instr.b), 31); + fn(cpu_R[instr.c], load_gpr(dc, instr.a), sh); + tcg_temp_free(sh); + } } -gen_r_shift_s(sra, sar_tl) -gen_r_shift_s(srl, shr_tl) -gen_r_shift_s(sll, shl_tl) -gen_r_shift_s(rol, rotl_tl) -gen_r_shift_s(ror, rotr_tl) +#define gen_rr_shift(fname, insn) \ + static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \ + { do_rr_shift(dc, code, tcg_gen_##insn##_tl); } + +gen_rr_shift(sra, sar) +gen_rr_shift(srl, shr) +gen_rr_shift(sll, shl) +gen_rr_shift(rol, rotl) +gen_rr_shift(ror, rotr) static void divs(DisasContext *dc, uint32_t code, uint32_t flags) { From patchwork Fri Apr 22 16:52:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564891 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp698692map; Fri, 22 Apr 2022 10:49:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJybxUJxvmKBDpD/RDNrmwHgozMimga7hKEHIH9JqPoDpjGZ32m4MruJOBuZXNhsENAaimr3 X-Received: by 2002:a81:8507:0:b0:2eb:9715:78d3 with SMTP id v7-20020a818507000000b002eb971578d3mr6100763ywf.304.1650649762295; Fri, 22 Apr 2022 10:49:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650649762; cv=none; d=google.com; s=arc-20160816; b=OvgsQ6YN6cMwjGyJ9Pdg/YgzH9cHzHJWPvjoZGPtUkxtdAUI5ichmG3rdsOy5pjmzg 9IPejjhZO5hLIGD7U+3aH0s+HTnze7se/Kc2o+OIBOhb1kFKjpmxpiUMHSVCYXutCXZj wbUuw0itZPaQGN8GvhFckNLKQ4fGl5AOQpP6IyFN4Xj9u6Q98d9w+G9pXGn8J8mXS6/Z ajkvEQOa0HBaQL9+MtseeV5M+873WtoJT25How5hVOUfa4++cv2F5JIH+a8IGw99OigE Z8RIoo3GrfMfMjHC9EwjnFhN4kBSgHFpSZDaYJxEBi2YB2YFCQZ4YNcvbWWTHXXrRLI8 RmoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=uR4zZV3657JN1hsGHyvkuesYvOqGujxYVfmhutLiFKw=; b=oGfPCuGhwfX7loZ/nOatls+UugmgzDRB/IYF5vhYr467B64fHyopjP1+7jPGJU5yDV PQIlpgcmOppai9YlrexS8Wj3D20JduA4fGFGlTUCHzU8gWxy789BZCdfXkjABWZHsX19 M8dBCJQ44fZhHlxB33F+0UJGtGYS+ZqhHBn2bRrGtpEX3YHnzcgTbVEd98tyJSRRLlt2 NjeWyR0bVLVUq2SMDeCOxTSwN5tigvfZHmWqFLoyNpPlKYwSoSAP362fhygpFS/qC90K ZB0YGLr5Ipc6YRmUMMeZLMBJdRMunV2AujJwSkb1ScakeTzS0x6neVRSij7RYTTlkBSF WYpg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GsVX2O5j; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.57.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:57:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 49/68] target/nios2: Introduce dest_gpr Date: Fri, 22 Apr 2022 09:52:19 -0700 Message-Id: <20220422165238.1971496-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::131; envelope-from=richard.henderson@linaro.org; helo=mail-il1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Constrain all references to cpu_R[] to load_gpr and dest_gpr. This will be required for supporting shadow register sets. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-46-richard.henderson@linaro.org> --- target/nios2/translate.c | 144 +++++++++++++-------------------------- 1 file changed, 49 insertions(+), 95 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index f2dcaa3fbb..e2742a8556 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -128,6 +128,7 @@ typedef struct DisasContext { DisasContextBase base; target_ulong pc; int mem_idx; + TCGv sink; const ControlRegState *cr_state; } DisasContext; @@ -160,6 +161,18 @@ static TCGv load_gpr(DisasContext *dc, unsigned reg) return cpu_R[reg]; } +static TCGv dest_gpr(DisasContext *dc, unsigned reg) +{ + assert(reg < NUM_GP_REGS); + if (unlikely(reg == R_ZERO)) { + if (dc->sink == NULL) { + dc->sink = tcg_temp_new(); + } + return dc->sink; + } + return cpu_R[reg]; +} + static void t_gen_helper_raise_exception(DisasContext *dc, uint32_t index) { @@ -218,7 +231,7 @@ static void jmpi(DisasContext *dc, uint32_t code, uint32_t flags) static void call(DisasContext *dc, uint32_t code, uint32_t flags) { - tcg_gen_movi_tl(cpu_R[R_RA], dc->base.pc_next); + tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next); jmpi(dc, code, flags); } @@ -231,27 +244,10 @@ static void gen_ldx(DisasContext *dc, uint32_t code, uint32_t flags) I_TYPE(instr, code); TCGv addr = tcg_temp_new(); - TCGv data; - - /* - * WARNING: Loads into R_ZERO are ignored, but we must generate the - * memory access itself to emulate the CPU precisely. Load - * from a protected page to R_ZERO will cause SIGSEGV on - * the Nios2 CPU. - */ - if (likely(instr.b != R_ZERO)) { - data = cpu_R[instr.b]; - } else { - data = tcg_temp_new(); - } + TCGv data = dest_gpr(dc, instr.b); tcg_gen_addi_tl(addr, load_gpr(dc, instr.a), instr.imm16.s); tcg_gen_qemu_ld_tl(data, addr, dc->mem_idx, flags); - - if (unlikely(instr.b == R_ZERO)) { - tcg_temp_free(data); - } - tcg_temp_free(addr); } @@ -281,7 +277,7 @@ static void gen_bxx(DisasContext *dc, uint32_t code, uint32_t flags) I_TYPE(instr, code); TCGLabel *l1 = gen_new_label(); - tcg_gen_brcond_tl(flags, cpu_R[instr.a], cpu_R[instr.b], l1); + tcg_gen_brcond_tl(flags, load_gpr(dc, instr.a), load_gpr(dc, instr.b), l1); gen_goto_tb(dc, 0, dc->base.pc_next); gen_set_label(l1); gen_goto_tb(dc, 1, dc->base.pc_next + (instr.imm16.s & -4)); @@ -293,11 +289,8 @@ static void do_i_cmpxx(DisasContext *dc, uint32_t insn, TCGCond cond, ImmFromIType *imm) { I_TYPE(instr, insn); - - if (likely(instr.b != R_ZERO)) { - tcg_gen_setcondi_tl(cond, cpu_R[instr.b], - load_gpr(dc, instr.a), imm(&instr)); - } + tcg_gen_setcondi_tl(cond, dest_gpr(dc, instr.b), + load_gpr(dc, instr.a), imm(&instr)); } #define gen_i_cmpxx(fname, imm) \ @@ -324,9 +317,9 @@ static void do_i_math_logic(DisasContext *dc, uint32_t insn, if (instr.a == R_ZERO) { /* This catches the canonical expansions of movi and movhi. */ - tcg_gen_movi_tl(cpu_R[instr.b], x_op_0_eq_x ? val : 0); + tcg_gen_movi_tl(dest_gpr(dc, instr.b), x_op_0_eq_x ? val : 0); } else { - fn(cpu_R[instr.b], cpu_R[instr.a], val); + fn(dest_gpr(dc, instr.b), load_gpr(dc, instr.a), val); } } @@ -434,7 +427,7 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags) #else TCGv tmp = tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_ESTATUS])); - gen_helper_eret(cpu_env, tmp, cpu_R[R_EA]); + gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_EA)); tcg_temp_free(tmp); dc->base.is_jmp = DISAS_NORETURN; @@ -444,8 +437,7 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags) /* PC <- ra */ static void ret(DisasContext *dc, uint32_t code, uint32_t flags) { - tcg_gen_mov_tl(cpu_pc, cpu_R[R_RA]); - + tcg_gen_mov_tl(cpu_pc, load_gpr(dc, R_RA)); dc->base.is_jmp = DISAS_JUMP; } @@ -464,7 +456,7 @@ static void bret(DisasContext *dc, uint32_t code, uint32_t flags) #else TCGv tmp = tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_BSTATUS])); - gen_helper_eret(cpu_env, tmp, cpu_R[R_BA]); + gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_BA)); tcg_temp_free(tmp); dc->base.is_jmp = DISAS_NORETURN; @@ -477,7 +469,6 @@ static void jmp(DisasContext *dc, uint32_t code, uint32_t flags) R_TYPE(instr, code); tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a)); - dc->base.is_jmp = DISAS_JUMP; } @@ -486,9 +477,7 @@ static void nextpc(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, code); - if (likely(instr.c != R_ZERO)) { - tcg_gen_movi_tl(cpu_R[instr.c], dc->base.pc_next); - } + tcg_gen_movi_tl(dest_gpr(dc, instr.c), dc->base.pc_next); } /* @@ -500,7 +489,7 @@ static void callr(DisasContext *dc, uint32_t code, uint32_t flags) R_TYPE(instr, code); tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a)); - tcg_gen_movi_tl(cpu_R[R_RA], dc->base.pc_next); + tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next); dc->base.is_jmp = DISAS_JUMP; } @@ -516,15 +505,11 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) g_assert_not_reached(); #else R_TYPE(instr, code); - TCGv t1, t2; - - if (unlikely(instr.c == R_ZERO)) { - return; - } + TCGv t1, t2, dest = dest_gpr(dc, instr.c); /* Reserved registers read as zero. */ if (nios2_cr_reserved(&dc->cr_state[instr.imm5])) { - tcg_gen_movi_tl(cpu_R[instr.c], 0); + tcg_gen_movi_tl(dest, 0); return; } @@ -542,12 +527,12 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) t2 = tcg_temp_new(); tcg_gen_ld_tl(t1, cpu_env, offsetof(CPUNios2State, ctrl[CR_IPENDING])); tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUNios2State, ctrl[CR_IENABLE])); - tcg_gen_and_tl(cpu_R[instr.c], t1, t2); + tcg_gen_and_tl(dest, t1, t2); tcg_temp_free(t1); tcg_temp_free(t2); break; default: - tcg_gen_ld_tl(cpu_R[instr.c], cpu_env, + tcg_gen_ld_tl(dest, cpu_env, offsetof(CPUNios2State, ctrl[instr.imm5])); break; } @@ -623,29 +608,21 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags) static void gen_cmpxx(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, code); - if (likely(instr.c != R_ZERO)) { - tcg_gen_setcond_tl(flags, cpu_R[instr.c], cpu_R[instr.a], - cpu_R[instr.b]); - } + tcg_gen_setcond_tl(flags, dest_gpr(dc, instr.c), + load_gpr(dc, instr.a), load_gpr(dc, instr.b)); } /* Math/logic instructions */ static void do_ri_math_logic(DisasContext *dc, uint32_t insn, GenFn2i *fn) { R_TYPE(instr, insn); - - if (likely(instr.c != R_ZERO)) { - fn(cpu_R[instr.c], load_gpr(dc, instr.a), instr.imm5); - } + fn(dest_gpr(dc, instr.c), load_gpr(dc, instr.a), instr.imm5); } static void do_rr_math_logic(DisasContext *dc, uint32_t insn, GenFn3 *fn) { R_TYPE(instr, insn); - - if (likely(instr.c != R_ZERO)) { - fn(cpu_R[instr.c], load_gpr(dc, instr.a), load_gpr(dc, instr.b)); - } + fn(dest_gpr(dc, instr.c), load_gpr(dc, instr.a), load_gpr(dc, instr.b)); } #define gen_ri_math_logic(fname, insn) \ @@ -673,13 +650,11 @@ gen_ri_math_logic(roli, rotli) static void do_rr_mul_high(DisasContext *dc, uint32_t insn, GenFn4 *fn) { R_TYPE(instr, insn); + TCGv discard = tcg_temp_new(); - if (likely(instr.c != R_ZERO)) { - TCGv discard = tcg_temp_new(); - fn(discard, cpu_R[instr.c], load_gpr(dc, instr.a), - load_gpr(dc, instr.b)); - tcg_temp_free(discard); - } + fn(discard, dest_gpr(dc, instr.c), + load_gpr(dc, instr.a), load_gpr(dc, instr.b)); + tcg_temp_free(discard); } #define gen_rr_mul_high(fname, insn) \ @@ -693,14 +668,11 @@ gen_rr_mul_high(mulxsu, mulsu2) static void do_rr_shift(DisasContext *dc, uint32_t insn, GenFn3 *fn) { R_TYPE(instr, insn); + TCGv sh = tcg_temp_new(); - if (likely(instr.c != R_ZERO)) { - TCGv sh = tcg_temp_new(); - - tcg_gen_andi_tl(sh, load_gpr(dc, instr.b), 31); - fn(cpu_R[instr.c], load_gpr(dc, instr.a), sh); - tcg_temp_free(sh); - } + tcg_gen_andi_tl(sh, load_gpr(dc, instr.b), 31); + fn(dest_gpr(dc, instr.c), load_gpr(dc, instr.a), sh); + tcg_temp_free(sh); } #define gen_rr_shift(fname, insn) \ @@ -716,39 +688,15 @@ gen_rr_shift(ror, rotr) static void divs(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, (code)); - TCGv dest; - - if (instr.c == R_ZERO) { - dest = tcg_temp_new(); - } else { - dest = cpu_R[instr.c]; - } - - gen_helper_divs(dest, cpu_env, + gen_helper_divs(dest_gpr(dc, instr.c), cpu_env, load_gpr(dc, instr.a), load_gpr(dc, instr.b)); - - if (instr.c == R_ZERO) { - tcg_temp_free(dest); - } } static void divu(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, (code)); - TCGv dest; - - if (instr.c == R_ZERO) { - dest = tcg_temp_new(); - } else { - dest = cpu_R[instr.c]; - } - - gen_helper_divu(dest, cpu_env, + gen_helper_divu(dest_gpr(dc, instr.c), cpu_env, load_gpr(dc, instr.a), load_gpr(dc, instr.b)); - - if (instr.c == R_ZERO) { - tcg_temp_free(dest); - } } static void trap(DisasContext *dc, uint32_t code, uint32_t flags) @@ -938,8 +886,14 @@ static void nios2_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) return; } + dc->sink = NULL; + instr = &i_type_instructions[op]; instr->handler(dc, code, instr->flags); + + if (dc->sink) { + tcg_temp_free(dc->sink); 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.57.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:57:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 50/68] target/nios2: Drop CR_STATUS_EH from tb->flags Date: Fri, 22 Apr 2022 09:52:20 -0700 Message-Id: <20220422165238.1971496-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d33; envelope-from=richard.henderson@linaro.org; helo=mail-io1-xd33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There's nothing about EH that affects translation, so there's no need to include it in tb->flags. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-47-richard.henderson@linaro.org> --- target/nios2/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 4d63006ffe..477a661f17 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -272,7 +272,7 @@ static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *pc, { *pc = env->pc; *cs_base = 0; - *flags = env->ctrl[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U); + *flags = env->ctrl[CR_STATUS] & CR_STATUS_U; } #endif /* NIOS2_CPU_H */ From patchwork Fri Apr 22 16:52:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564898 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp702835map; Fri, 22 Apr 2022 10:55:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwAanAmCOYw8uAfbyRHZlKXWABXrQknk1BXG+LCSoJj7GPEiLIxPUsEytDpHvlZi+KdyDfX X-Received: by 2002:a05:620a:2401:b0:69f:c66:10d2 with SMTP id d1-20020a05620a240100b0069f0c6610d2mr3429789qkn.229.1650650100872; Fri, 22 Apr 2022 10:55:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650650100; cv=none; d=google.com; s=arc-20160816; b=QAa5qUWRbziwVd0qMlXqn9iaNg+EBxAwfr6z/ECxQZYNcaYB2yKPp8DsscviRlmmB2 zQagydml/gFLQVMEHbJyEGxAzmJPIdQrI7omgWASeaTiUG8m3lOaz7cg4GsOplVLtzMQ yTPgfMGJZnEwBWZuSY+A9G95bE6EXSgDLpWc5oiWA3anBfwzxgZw2slA2U/kMXTETlcK gmv/K1YaRs6qvRIbZO/WNfMxIWoV4zkIiQ10qpM4sMZhDCDVIfw4n8P78u6ci74ReZow 6BeRZYg9fc/OzwkWyaEID7Cdq2Sixo9mi/o7fbrtJhTDUTRI0MXsZuOXhuFj3LVYYXos b47Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=SrtdhebFHwQH2QuEUcsrlEhP5p9ppqhl2VFXayXosos=; b=sy5/trvCbTfrsJpTH6hiONGMnVpIGtLGsOCvsKgA1JnCvw6mbTb+2U8bY3JtsPWcX+ SGJGYC7cH1KElbQP862vPo33c97T9jvE5dc31jTokNKfeVXZ8UHMdEXVVccQr9eU4+47 7e83fnwh89xloQyIij+msgN9Zl23wR1jj6gyccPqqrVONaSk143w5vsD3J+KUk2Mfx+Q k3hAs7KS8ey75jSeJYu668GOBDkc09EcbsL+fziHO/pb9oege4R/NhgnU9gy1+oYrFS4 O8oiPY4gZOPgn4DABL9KmjSomqI2quy8tXxeIHVBoLQZ0USyYD42CwEqBkltayVAC3+v MjRQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=y9eTBHoS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.57.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:57:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 51/68] target/nios2: Enable unaligned traps for system mode Date: Fri, 22 Apr 2022 09:52:21 -0700 Message-Id: <20220422165238.1971496-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d32; envelope-from=richard.henderson@linaro.org; helo=mail-io1-xd32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Unaligned traps are optional, but required with an mmu. Turn them on always, because the fallback behaviour undefined. Enable alignment checks in the config file. Unwind the guest pc properly from do_unaligned_access. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-48-richard.henderson@linaro.org> --- target/nios2/helper.c | 4 ++-- configs/targets/nios2-softmmu.mak | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index c5a2dd65b1..2e9fea4a01 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -241,8 +241,8 @@ void nios2_cpu_do_unaligned_access(CPUState *cs, vaddr addr, CPUNios2State *env = &cpu->env; env->ctrl[CR_BADADDR] = addr; - env->ctrl[CR_EXCEPTION] = FIELD_DP32(0, CR_EXCEPTION, CAUSE, EXCP_UNALIGN); - helper_raise_exception(env, EXCP_UNALIGN); + cs->exception_index = EXCP_UNALIGN; + cpu_loop_exit_restore(cs, retaddr); } bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, diff --git a/configs/targets/nios2-softmmu.mak b/configs/targets/nios2-softmmu.mak index 9a372f0717..1e93b54cd1 100644 --- a/configs/targets/nios2-softmmu.mak +++ b/configs/targets/nios2-softmmu.mak @@ -1 +1,2 @@ TARGET_ARCH=nios2 +TARGET_ALIGNED_ONLY=y From patchwork Fri Apr 22 16:52:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564901 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp705036map; Fri, 22 Apr 2022 10:58:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyACo5SHMfiQAiVuX5WAxj1VfhENAkzsgv18SIcyMJr70PxBttJvciIsMJyu3mXls0M+nlV X-Received: by 2002:a0d:dd91:0:b0:2f7:bf1c:80a3 with SMTP id g139-20020a0ddd91000000b002f7bf1c80a3mr1356618ywe.234.1650650309373; Fri, 22 Apr 2022 10:58:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650650309; cv=none; d=google.com; s=arc-20160816; b=zikotIsZ9yRW9IrKXFP69o/sgUG6+rd0gk/kbiQWgc4Mvx18EggfWAEvgSTzVI3Zlo wJsxnQC2n6mCZslX2vUNeevnpuccbdy8dyHw+2+F8nJOeA5s4bH9ssBX9Z+rYrzBzPNm CrASCwxun10iAmoE/8bV71AjTiwtg5KS+REYlU5uPHFxdEJAykaQobTV+3+Xjkq69uW3 ln4aDEo/kf7XPZJzPUNPeY3im8zyWvyjmvbdgZ7V+u3iEXkK4veboOYBD6Vad1dc7nMb Ay91l3zojaF5K/2SSORibiTAaBLQv7etebaSfGvS2ynygXSlHYAM0ViplMprcQZZ4Usd 49Yw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=FydhLHa4yRdKoi+QMZFm3ACoytrW9DGPCspIkMaQe9I=; b=Ac0sRm7ZQbw487JfvitQh2BW1eZBsEUqIRp0mcw8CovXA5nfunFdrVyEp0+fAqDzMb o74Cu+U7SoHyIQagnOI0gZwPl2N1QLt7RH1J6+wgeAQC1kj3jRPStdjf8QTKS3iJ3ifs Pif1jvP05S1uq2Fof5pdTe6eBcwBq8yXNn8pXMlyn8H+TOFDGPXlPxi80zveav4zs59f p+tGmtOZ87FjLySAGGFN7eASLArhgY65IBR166BP3+ez7sX99y5M8j+klamPtsEBhtX5 9xiM0DBklTz1zAAhGHMSYjkk7YiUsmzgJdMlF5KnGbdcyxnyi30/QmDdrCSUsNBEGuwx pw9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jS3qgQle; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.57.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:57:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 52/68] target/nios2: Create gen_jumpr Date: Fri, 22 Apr 2022 09:52:22 -0700 Message-Id: <20220422165238.1971496-53-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d2b; envelope-from=richard.henderson@linaro.org; helo=mail-io1-xd2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split out a function to perform an indirect branch. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-49-richard.henderson@linaro.org> --- target/nios2/translate.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index e2742a8556..8616813365 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -36,7 +36,6 @@ #include "semihosting/semihost.h" /* is_jmp field values */ -#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ #define INSTRUCTION_FLG(func, flags) { (func), (flags) } @@ -195,6 +194,16 @@ static void gen_goto_tb(DisasContext *dc, int n, uint32_t dest) } } +static void gen_jumpr(DisasContext *dc, int regno, bool is_call) +{ + tcg_gen_mov_tl(cpu_pc, load_gpr(dc, regno)); + if (is_call) { + tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next); + } + tcg_gen_exit_tb(NULL, 0); + dc->base.is_jmp = DISAS_NORETURN; +} + static void gen_excp(DisasContext *dc, uint32_t code, uint32_t flags) { t_gen_helper_raise_exception(dc, flags); @@ -437,8 +446,7 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags) /* PC <- ra */ static void ret(DisasContext *dc, uint32_t code, uint32_t flags) { - tcg_gen_mov_tl(cpu_pc, load_gpr(dc, R_RA)); - dc->base.is_jmp = DISAS_JUMP; + gen_jumpr(dc, R_RA, false); } /* @@ -468,8 +476,7 @@ static void jmp(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, code); - tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a)); - dc->base.is_jmp = DISAS_JUMP; + gen_jumpr(dc, instr.a, false); } /* rC <- PC + 4 */ @@ -488,10 +495,7 @@ static void callr(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, code); - tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a)); - tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next); - - dc->base.is_jmp = DISAS_JUMP; + gen_jumpr(dc, instr.a, true); } /* rC <- ctlN */ @@ -909,11 +913,6 @@ static void nios2_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) tcg_gen_exit_tb(NULL, 0); break; - case DISAS_JUMP: - /* The jump will already have updated the PC register */ - tcg_gen_exit_tb(NULL, 0); - break; - case DISAS_NORETURN: /* nothing more to generate */ break; From patchwork Fri Apr 22 16:52:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564877 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp686181map; Fri, 22 Apr 2022 10:31:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwTPDZJcY4h5ObtHTBqrUK4pwa5DKZrVyVzr9M4Fg2vv4GtdP0qvJrRGb+gGTNHzqCTC7ZI X-Received: by 2002:a25:dc7:0:b0:641:329b:5914 with SMTP id 190-20020a250dc7000000b00641329b5914mr5653385ybn.425.1650648719137; Fri, 22 Apr 2022 10:31:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650648719; cv=none; d=google.com; s=arc-20160816; b=TJ7mvhOGhzJS2LWybev8sWqWIGs0bgggjLeOPzOUFVafp7qkuobKjqWpGhmLfc8dgj ZDqpk8BI0MBeJx7gH6YGRFGI4wXvM/x4bopMV0zMcKT6vbqLj6XSdFDlR4Dcn/fYYJDl tWGVzQ1XkwaIodvAlVSGzNHxYb9cUcnbKE256H0tUydQrXWUiHYLzPtWhS9kEe9WP3+E Mta8mYBegCWxg6KI4A5jZ98PZAbjCAkyXalByMaWqgmTLyaXBoOVPR32amjMCjK+AFlV A2sXhlMBbQznFRqnMFN1aTkHErzT6dYGXl6TS83S/SCUBtZR2hB+gLScMvw0uJMMMCdX nCLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ECkUiferYymqY4Z15uQTs5z/1lpHpfnUwzpraAW+MmE=; b=iObdQHKU6ufFuXLN7memyKU5XMdRsjU+okk71a73SR+M8Fy1Kv21goFh/akv3wJvcQ N/X3t0LIfZKS+ELD15gSx3iyAX1aecS6bWTUbgKQlBsiZ9ttOK6useZtmYOROkmL5pq2 NttGE9evRk0xy+FccNPWzw4eaIq+murBMw+kduwptdeSWlT6sxv3tFzuwnWeyLXNicDu ngVv7755e8UutsRGqPGlzsHS6fyO3CINPAzwjNMPBoGpVtFi77yXigYIAA37nNCIDx/9 BdOrrAlU+u+o/ATy8kOVcoWTprKik0Uf75fz6WRQ+rPAKhNHEfCMQ5O2L2eBxrXHbr8C /eeA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sy9rN8wM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.57.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:57:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 53/68] target/nios2: Hoist set of is_jmp into gen_goto_tb Date: Fri, 22 Apr 2022 09:52:23 -0700 Message-Id: <20220422165238.1971496-54-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::12e; envelope-from=richard.henderson@linaro.org; helo=mail-il1-x12e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rather than force all callers to set this, do it within the subroutine. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-50-richard.henderson@linaro.org> --- target/nios2/translate.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 8616813365..a55270cefa 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -192,6 +192,7 @@ static void gen_goto_tb(DisasContext *dc, int n, uint32_t dest) tcg_gen_movi_tl(cpu_pc, dest); tcg_gen_exit_tb(NULL, 0); } + dc->base.is_jmp = DISAS_NORETURN; } static void gen_jumpr(DisasContext *dc, int regno, bool is_call) @@ -235,7 +236,6 @@ static void jmpi(DisasContext *dc, uint32_t code, uint32_t flags) { J_TYPE(instr, code); gen_goto_tb(dc, 0, (dc->pc & 0xF0000000) | (instr.imm26 << 2)); - dc->base.is_jmp = DISAS_NORETURN; } static void call(DisasContext *dc, uint32_t code, uint32_t flags) @@ -278,7 +278,6 @@ static void br(DisasContext *dc, uint32_t code, uint32_t flags) I_TYPE(instr, code); gen_goto_tb(dc, 0, dc->base.pc_next + (instr.imm16.s & -4)); - dc->base.is_jmp = DISAS_NORETURN; } static void gen_bxx(DisasContext *dc, uint32_t code, uint32_t flags) @@ -290,7 +289,6 @@ static void gen_bxx(DisasContext *dc, uint32_t code, uint32_t flags) gen_goto_tb(dc, 0, dc->base.pc_next); gen_set_label(l1); gen_goto_tb(dc, 1, dc->base.pc_next + (instr.imm16.s & -4)); - dc->base.is_jmp = DISAS_NORETURN; } /* Comparison instructions */ From patchwork Fri Apr 22 16:52:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564881 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp688360map; Fri, 22 Apr 2022 10:34:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwzK207yynqmv/8M3YJnfDwCGEDlOeDZAj9UssYVcy2wkOtlom4h0Fp2SwL5OvD18wYC/6f X-Received: by 2002:a81:2d82:0:b0:2f4:d2b6:1864 with SMTP id t124-20020a812d82000000b002f4d2b61864mr6014852ywt.342.1650648891402; Fri, 22 Apr 2022 10:34:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650648891; cv=none; d=google.com; s=arc-20160816; b=Qhi0hL+SyD7wBXB32Mppn52E0Cxk75DKdvrnFPKv6ahnnwDU0CfjExVLqJthZzHWQ0 KufZzoGwaajQc4OY4GG2bM8ukHmsaMX9WzAOV6vz1pPLHU9dhD/puCXj1pG0Q7ZXHgFX b1OmtDJA2yenXWhoaF6MVJACFL3Ia3uFGbQJZrRG+P9/LQ4WGgn8JiWDobvDORkKIKKb 3KLVb1rLuQSD9gdHDrIT39r9EFEVXl+f3OaJqFL1qdm73ApxJuPOodws5VldZJn1mLdH tRREerxsPB1ABGkp4M2eF1Awaug53fwQ6LPxXHc5ZIYWmw1TtqFjSFGqmPGxkiMQUQYc ywMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Q5lQ3QQmzEghJch5edn2tjFgDaTVnAJ5/vXlb5qvEBk=; b=UYUVxmrXhV4X7hkrmQu6BFztWQQ2UIc1xL5+7fEWOtU7mwHRIB4BywDBCHZbSn+m/j GCLX6FrlUn3GnlFY228Atud8I4qyRCeHNC27yK/xAia7hy+4ew5PUWjlgCoyIIrG8QXA Cz+l9nOUMk0/+7rcKDHlbiwd/1VbtvCeM075ksuhzCjsSSXyk+DXRO7SDz6m1DlkwOqy BdWeYS52kr6RCctNdZRmSbmUGDrMJoNbGLhWR71tImxaOcHxuFJ9m4rsGsB8d3DnBA4J PsMXK9qhfmhT9kA7SNW8505NOcI7DCaMqxjtNDLi+69zTZeeUCwK1mHNB+8GLkm7uVHx 3rdQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kIY0Qtz9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.57.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:57:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 54/68] target/nios2: Use gen_goto_tb for DISAS_TOO_MANY Date: Fri, 22 Apr 2022 09:52:24 -0700 Message-Id: <20220422165238.1971496-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d2e; envelope-from=richard.henderson@linaro.org; helo=mail-io1-xd2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Depending on the reason for ending the TB, we can chain to the next TB because the PC is constant. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-51-richard.henderson@linaro.org> --- target/nios2/translate.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index a55270cefa..87f3e57d4c 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -905,8 +905,11 @@ static void nios2_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) /* Indicate where the next block should start */ switch (dc->base.is_jmp) { case DISAS_TOO_MANY: + gen_goto_tb(dc, 0, dc->base.pc_next); + break; + case DISAS_UPDATE: - /* Save the current PC back into the CPU register */ + /* Save the current PC, and return to the main loop. */ tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); tcg_gen_exit_tb(NULL, 0); break; From patchwork Fri Apr 22 16:52:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564885 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp692615map; Fri, 22 Apr 2022 10:40:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz2lweC1oS084P3g4mdzcadZIMpAYYtMHRhbjgy4Z2CZ4+IsyssZSoESrmeR3cnXoiujI8L X-Received: by 2002:a25:6b09:0:b0:641:6bd2:4ba0 with SMTP id g9-20020a256b09000000b006416bd24ba0mr5570460ybc.319.1650649250849; Fri, 22 Apr 2022 10:40:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650649250; cv=none; d=google.com; s=arc-20160816; b=O/1K2k7H4bc53d2vI/u9d7cVXvy9o9itCgOl1UKyfzfIOCc0I1kLir6gAunpvRvSUR gb6JIBhQeCQE0F9/OS+HILl3sNkQ3flofn4CF6Qby3PjQzwpGcoNyeacPL3Zihzs3emY RmOrqmySV0Su5US3kP4pJikCpoTj4SjiK0Rn8M13O+2zBw0+Ux8tfwvRTb6fAg1ulZtU iRLt2RWH90PMVi4zr03m5hm46o28RcaeZBMSejVzx0Cy41ZANbS+v+FeY9yf1X1ojIVr QsNopBtbay7y002zm01+QUqXpDdzrOvx2ptLl9d/g3phHgW5HGuEuI8bCeZ32zHh+B3e 8iaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=RUgiA6Oi5P+ooqWxIlZ6MCSz3k6th6h8Ep/asqMDiZk=; b=LJ3IIvwJxKOXTirTjU9UGv4TKZaTIZfW/dk88C7zbZ9TOTsrqS5mc5twRg9T/oPTw8 7QFWWzajVFiU/JOBetoXrrYtYD76tZbkfLzou8ksUnkOSQrvlUFUEAggmYWrcZKrogGn RUjHiQGZxkQ2jJPtvDjJvI2ye6PcjSTPQ0NLb2TzorDPSHciWKtaoxlo2GC7ScXmZeoy 5OvWLzjRhHCCkc7xsoSbfHwN9oYiBpz+CcqMbtWcAt4ft3Ewmp/2rtzKL/gUvfS/2sYT V+0vnrSJoDI2QZ+3mlsvkx+JXkBBBK5UbUvW7b1yxx07Kjcj5gYaliY2L3S2mxhjO+BZ MKHg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=B77CmztI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.57.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:57:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 55/68] target/nios2: Use tcg_gen_lookup_and_goto_ptr Date: Fri, 22 Apr 2022 09:52:25 -0700 Message-Id: <20220422165238.1971496-56-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d33; envelope-from=richard.henderson@linaro.org; helo=mail-io1-xd33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use lookup_and_goto_ptr for indirect chaining between TBs. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-52-richard.henderson@linaro.org> --- target/nios2/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 87f3e57d4c..a3e87beba4 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -190,7 +190,7 @@ static void gen_goto_tb(DisasContext *dc, int n, uint32_t dest) tcg_gen_exit_tb(tb, n); } else { tcg_gen_movi_tl(cpu_pc, dest); - tcg_gen_exit_tb(NULL, 0); + tcg_gen_lookup_and_goto_ptr(); } dc->base.is_jmp = DISAS_NORETURN; } @@ -201,7 +201,7 @@ static void gen_jumpr(DisasContext *dc, int regno, bool is_call) if (is_call) { tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next); } - tcg_gen_exit_tb(NULL, 0); + tcg_gen_lookup_and_goto_ptr(); dc->base.is_jmp = DISAS_NORETURN; } From patchwork Fri Apr 22 16:52:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564886 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp695388map; Fri, 22 Apr 2022 10:44:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyeE4gOxsrAdy0eKIXM80JFnkKbh093s6RSj4R2Yq5Oo8Y6RWoH7H2lP0vwKzS7c/Q+nvL+ X-Received: by 2002:a81:2492:0:b0:2eb:250d:9cd8 with SMTP id k140-20020a812492000000b002eb250d9cd8mr5828985ywk.238.1650649476508; Fri, 22 Apr 2022 10:44:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650649476; cv=none; d=google.com; s=arc-20160816; b=MExpJ9Nxg9kQnszBUqSqMjQ3ttbgcowffjkxBIVkWagogAYpef3Sh2obEo26LLcRJl gposlvyYS299hOcNf9W/m9b4i6zFVUse7ges7FfldS3L6n6sgl3WO3+jiZSvUsNQErs0 JIUpHCaUQLxxZv4x66xnHxkYOxvFVe7ezz2+zLp3CObiAyc3x/+qA69mtNlc5SIwznWq 10Xx6LRLiUQPt6iCY0tANdl5Tid6QKa4vEWjEddvJ7hkSE/NKyQoZAXgmNLdXaO6GZhB wEXvZkE2zvoX0caW6225xvK6jQj7FGqMQLiBSEBQ8uqEnQcOez1w0WfONBDz/Who6N6r +oUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=EjEvoq47mgxbhwOkPjY+lzICTw8tSYJC5nzrZvKsO9E=; b=0C8L5erop6YixdibqA64cxIKeMqlskMkFUeLqnmKnJa/RLYTM/RpnO1KvVknKEA9GK uiH+Gw8xZzWRN6i6qCq/zD308sBpRec6O9QTqWbtS0NOk5jyDKKP/RmeEZv2NqEoCV4l AxbNSYKw+D/ipWeHavH3QD/GBgtROp41unPVmSafF1k/vblssvTNy7LehY33MPdxMwLy /i2hD4tKRoA1xDfy1ZmtLj8epVHKqvPp0iK1k0Uly7yanyyqtwXZ66VVgii5Zkfdcoqm 9EYNL2EHYwj79rCQm/686RpM0mYGJqXE7DI6EfhNcaa/nbYrtj+n2X2j0g1gevNo286H 2fwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FalRuS1Y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.57.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:57:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 56/68] target/nios2: Implement Misaligned destination exception Date: Fri, 22 Apr 2022 09:52:26 -0700 Message-Id: <20220422165238.1971496-57-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::12a; envelope-from=richard.henderson@linaro.org; helo=mail-il1-x12a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Indirect branches, plus eret and bret optionally raise an exception when branching to a misaligned address. The exception is required when an mmu is enabled, but enable it always because the fallback behaviour is not documented (though presumably it discards low bits). For the purposes of the linux-user cpu loop, if EXCP_UNALIGN (misaligned data) were to arrive, it would be treated the same as EXCP_UNALIGND (misaligned destination). See the !defined(CONFIG_NIOS2_ALIGNMENT_TRAP) block in kernel/traps.c. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-53-richard.henderson@linaro.org> --- linux-user/nios2/cpu_loop.c | 6 ++++++ target/nios2/op_helper.c | 9 ++++++++- target/nios2/translate.c | 15 ++++++++++++++- 3 files changed, 28 insertions(+), 2 deletions(-) diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index 11ecb71843..30a27f252b 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -42,6 +42,12 @@ void cpu_loop(CPUNios2State *env) force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->pc); break; + case EXCP_UNALIGN: + case EXCP_UNALIGND: + force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN, + env->ctrl[CR_BADADDR]); + break; + case EXCP_TRAP: /* * TODO: This advance should be done in the translator, as diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index a19b504b0e..38a71a1f2d 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -64,6 +64,13 @@ uint32_t helper_divu(CPUNios2State *env, uint32_t num, uint32_t den) void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc) { Nios2CPU *cpu = env_archcpu(env); + CPUState *cs = env_cpu(env); + + if (unlikely(new_pc & 3)) { + env->ctrl[CR_BADADDR] = new_pc; + cs->exception_index = EXCP_UNALIGND; + cpu_loop_exit_restore(cs, GETPC()); + } /* * Both estatus and bstatus have no constraints on write; @@ -74,6 +81,6 @@ void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc) env->ctrl[CR_STATUS] = new_status; env->pc = new_pc; - cpu_loop_exit(env_cpu(env)); + cpu_loop_exit(cs); } #endif /* !CONFIG_USER_ONLY */ diff --git a/target/nios2/translate.c b/target/nios2/translate.c index a3e87beba4..794b763d8a 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -197,11 +197,24 @@ static void gen_goto_tb(DisasContext *dc, int n, uint32_t dest) static void gen_jumpr(DisasContext *dc, int regno, bool is_call) { - tcg_gen_mov_tl(cpu_pc, load_gpr(dc, regno)); + TCGLabel *l = gen_new_label(); + TCGv test = tcg_temp_new(); + TCGv dest = load_gpr(dc, regno); + + tcg_gen_andi_tl(test, dest, 3); + tcg_gen_brcondi_tl(TCG_COND_NE, test, 0, l); + tcg_temp_free(test); + + tcg_gen_mov_tl(cpu_pc, dest); if (is_call) { tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next); } tcg_gen_lookup_and_goto_ptr(); + + gen_set_label(l); + tcg_gen_st_tl(dest, cpu_env, offsetof(CPUNios2State, ctrl[CR_BADADDR])); + t_gen_helper_raise_exception(dc, EXCP_UNALIGND); + dc->base.is_jmp = DISAS_NORETURN; } From patchwork Fri Apr 22 16:52:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564890 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp698283map; Fri, 22 Apr 2022 10:48:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzD0cw4jUMUC3ewRSiQ93gVfhLW0nwsyL8WgiYP01XkzSIEX1fJWtMilhHjgOafmt/+jF2+ X-Received: by 2002:a25:378a:0:b0:645:7945:c1b6 with SMTP id e132-20020a25378a000000b006457945c1b6mr5528781yba.436.1650649728836; Fri, 22 Apr 2022 10:48:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650649728; cv=none; d=google.com; s=arc-20160816; b=Dp9WMPMGYaZtjTv3RcaJQuv5126fhPn5EqW4GKnItORgyCS1SIAsxtH/SWm3OHFxge 3rCM22OPcUfpF9chRmdquatpRZk8yAeB1yYPgjXBSaqzLvcNhZKj4Hl2Ewx2s0ljB1Ou RW/1H/8Hf5iR9y7I026iTA1IhKhtbHi11g4MDrnRKzNcIk9aULxWYZDcCEUoY4EES+ck Uv7lWt+JMBXekfQNkDoupXo7K9Rmob447uKh+VDwRJQzly/1EgNA5ylEyrz8qkKQ/BnD q2wfFoTpRpknI7L48IV402GrsPJ9sOyNBoK8hNkMOrCly+h7njtC3gmxCga4CloyDNvF 2CJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WyhHAN4kOdv5SP0UNYKZ/8CoTfSLfS0tLNbV671G8UI=; b=NnYbKHvfLo1+idIZHhiDqozvFT9z8VRIoO3Atq1+oGKyurCOpu0Z4SLslKWNYDdx70 96Zxwaq3MmQ46XII5IHSD7FWSO4EJzqGssFBoNboePUbVI0zUAWkNfiRA5ABNukcO7JR o7m8yJfA3GjzawO4E7OX5+9hGn3cfGrDSz+H6ztRnR+xuul7925DYMLKpL5ASOyiU4jy EuAOZ8WTRthbAcIOIZmG0uPNq2574DGrzNU4VOvYwhs38gZ23U/BO4sak3wEUIuHIL0q Sb5O4Vn1WW+xcGR8QPYT+9fnBzgaeVaURWxgNtVKFTTigXu9aaBy3KtgGcMLljgstzFP iwlg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=J9IxX2zi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.57.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:57:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 57/68] target/nios2: Introduce shadow register sets Date: Fri, 22 Apr 2022 09:52:27 -0700 Message-Id: <20220422165238.1971496-58-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d29; envelope-from=richard.henderson@linaro.org; helo=mail-io1-xd29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Do not actually enable them so far, in terms of being able to change the current register set, but add all of the plumbing to address them. Do not enable them for user-only. Add an env->regs pointer that handles the indirection to the current register set. The naming of the pointer hides the difference between old and new, user-only and sysemu. >From the notes on wrprs, which states that r0 must be initialized before use in shadow register sets, infer that R_ZERO is *not* hardwired to zero in shadow register sets, but that it is still read-only. Introduce tbflags bit R0_0 to track that it has been properly set to zero. Adjust load_gpr to reflect this. At the same time we might as well special case crs == 0 to avoid the indirection through env->regs during translation as well; this is intended to be the most common case for non-interrupt handlers. Init env->regs at reset. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20220421151735.31996-54-richard.henderson@linaro.org> --- target/nios2/cpu.h | 29 ++++++++++++++++++- target/nios2/cpu.c | 4 ++- target/nios2/translate.c | 61 ++++++++++++++++++++++++++++++++++------ 3 files changed, 83 insertions(+), 11 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 477a661f17..f6efaa79b3 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -60,6 +60,11 @@ struct Nios2CPUClass { #define NUM_GP_REGS 32 #define NUM_CR_REGS 32 +#ifndef CONFIG_USER_ONLY +/* 63 shadow register sets; index 0 is the primary register set. */ +#define NUM_REG_SETS 64 +#endif + /* General purpose register aliases */ enum { R_ZERO = 0, @@ -178,7 +183,13 @@ FIELD(CR_TLBMISC, EE, 24, 1) #define EXCP_MPUD 17 struct CPUArchState { +#ifdef CONFIG_USER_ONLY uint32_t regs[NUM_GP_REGS]; +#else + uint32_t shadow_regs[NUM_REG_SETS][NUM_GP_REGS]; + /* Pointer into shadow_regs for the current register set. */ + uint32_t *regs; +#endif uint32_t ctrl[NUM_CR_REGS]; uint32_t pc; @@ -229,6 +240,14 @@ static inline bool nios2_cr_reserved(const ControlRegState *s) return (s->writable | s->readonly) == 0; } +static inline void nios2_update_crs(CPUNios2State *env) +{ +#ifndef CONFIG_USER_ONLY + unsigned crs = FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, CRS); + env->regs = env->shadow_regs[crs]; +#endif +} + void nios2_tcg_init(void); void nios2_cpu_do_interrupt(CPUState *cs); void dump_mmu(CPUNios2State *env); @@ -267,12 +286,20 @@ typedef Nios2CPU ArchCPU; #include "exec/cpu-all.h" +FIELD(TBFLAGS, CRS0, 0, 1) /* Set if CRS == 0. */ +FIELD(TBFLAGS, U, 1, 1) /* Overlaps CR_STATUS_U */ +FIELD(TBFLAGS, R0_0, 2, 1) /* Set if R0 == 0. */ + static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) { + unsigned crs = FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, CRS); + *pc = env->pc; *cs_base = 0; - *flags = env->ctrl[CR_STATUS] & CR_STATUS_U; + *flags = (env->ctrl[CR_STATUS] & CR_STATUS_U) + | (crs ? 0 : R_TBFLAGS_CRS0_MASK) + | (env->regs[0] ? 0 : R_TBFLAGS_R0_0_MASK); } #endif /* NIOS2_CPU_H */ diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 54e7071907..d043c02fcd 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -48,15 +48,17 @@ static void nios2_cpu_reset(DeviceState *dev) ncc->parent_reset(dev); - memset(env->regs, 0, sizeof(env->regs)); memset(env->ctrl, 0, sizeof(env->ctrl)); env->pc = cpu->reset_addr; #if defined(CONFIG_USER_ONLY) /* Start in user mode with interrupts enabled. */ env->ctrl[CR_STATUS] = CR_STATUS_RSIE | CR_STATUS_U | CR_STATUS_PIE; + memset(env->regs, 0, sizeof(env->regs)); #else env->ctrl[CR_STATUS] = CR_STATUS_RSIE; + nios2_update_crs(env); + memset(env->shadow_regs, 0, sizeof(env->shadow_regs)); #endif } diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 794b763d8a..363f2ea3ca 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -127,12 +127,16 @@ typedef struct DisasContext { DisasContextBase base; target_ulong pc; int mem_idx; + uint32_t tb_flags; TCGv sink; const ControlRegState *cr_state; } DisasContext; static TCGv cpu_R[NUM_GP_REGS]; static TCGv cpu_pc; +#ifndef CONFIG_USER_ONLY +static TCGv cpu_crs_R[NUM_GP_REGS]; +#endif typedef struct Nios2Instruction { void (*handler)(DisasContext *dc, uint32_t code, uint32_t flags); @@ -154,22 +158,47 @@ static uint8_t get_opxcode(uint32_t code) static TCGv load_gpr(DisasContext *dc, unsigned reg) { assert(reg < NUM_GP_REGS); - if (unlikely(reg == R_ZERO)) { + + /* + * With shadow register sets, register r0 does not necessarily contain 0, + * but it is overwhelmingly likely that it does -- software is supposed + * to have set r0 to 0 in every shadow register set before use. + */ + if (unlikely(reg == R_ZERO) && FIELD_EX32(dc->tb_flags, TBFLAGS, R0_0)) { return tcg_constant_tl(0); } - return cpu_R[reg]; + if (FIELD_EX32(dc->tb_flags, TBFLAGS, CRS0)) { + return cpu_R[reg]; + } +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + return cpu_crs_R[reg]; +#endif } static TCGv dest_gpr(DisasContext *dc, unsigned reg) { assert(reg < NUM_GP_REGS); + + /* + * The spec for shadow register sets isn't clear, but we assume that + * writes to r0 are discarded regardless of CRS. + */ if (unlikely(reg == R_ZERO)) { if (dc->sink == NULL) { dc->sink = tcg_temp_new(); } return dc->sink; } - return cpu_R[reg]; + if (FIELD_EX32(dc->tb_flags, TBFLAGS, CRS0)) { + return cpu_R[reg]; + } +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + return cpu_crs_R[reg]; +#endif } static void t_gen_helper_raise_exception(DisasContext *dc, @@ -225,7 +254,7 @@ static void gen_excp(DisasContext *dc, uint32_t code, uint32_t flags) static bool gen_check_supervisor(DisasContext *dc) { - if (dc->base.tb->flags & CR_STATUS_U) { + if (FIELD_EX32(dc->tb_flags, TBFLAGS, U)) { /* CPU in user mode, privileged instruction called, stop. */ t_gen_helper_raise_exception(dc, EXCP_SUPERI); return false; @@ -335,7 +364,7 @@ static void do_i_math_logic(DisasContext *dc, uint32_t insn, val = imm(&instr); - if (instr.a == R_ZERO) { + if (instr.a == R_ZERO && FIELD_EX32(dc->tb_flags, TBFLAGS, R0_0)) { /* This catches the canonical expansions of movi and movhi. */ tcg_gen_movi_tl(dest_gpr(dc, instr.b), x_op_0_eq_x ? val : 0); } else { @@ -865,6 +894,7 @@ static void nios2_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->mem_idx = cpu_mmu_index(env, false); dc->cr_state = cpu->cr_state; + dc->tb_flags = dc->base.tb->flags; /* Bound the number of insns to execute to those left on the page. */ page_insns = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; @@ -999,13 +1029,26 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags) void nios2_tcg_init(void) { - int i; +#ifndef CONFIG_USER_ONLY + TCGv_ptr crs = tcg_global_mem_new_ptr(cpu_env, + offsetof(CPUNios2State, regs), "crs"); - for (i = 0; i < NUM_GP_REGS; i++) { - cpu_R[i] = tcg_global_mem_new(cpu_env, - offsetof(CPUNios2State, regs[i]), + for (int i = 0; i < NUM_GP_REGS; i++) { + cpu_crs_R[i] = tcg_global_mem_new(crs, 4 * i, gr_regnames[i]); + } + +#define offsetof_regs0(N) offsetof(CPUNios2State, shadow_regs[0][N]) +#else +#define offsetof_regs0(N) offsetof(CPUNios2State, regs[N]) +#endif + + for (int i = 0; i < NUM_GP_REGS; i++) { + cpu_R[i] = tcg_global_mem_new(cpu_env, offsetof_regs0(i), gr_regnames[i]); } + +#undef offsetof_regs0 + cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPUNios2State, pc), "pc"); } From patchwork Fri Apr 22 16:52:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564902 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp707353map; Fri, 22 Apr 2022 11:01:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxfzfyeUJl6FpfFsdnesQG4+J5zqvD5lGOvNbabZq4oUm+I8+cC7rFisgPh7vY7EabVuASy X-Received: by 2002:a05:6902:1247:b0:644:afb0:a40c with SMTP id t7-20020a056902124700b00644afb0a40cmr5748976ybu.419.1650650487200; Fri, 22 Apr 2022 11:01:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650650487; cv=none; d=google.com; s=arc-20160816; b=Fi/vCNV+KAmlwcvQQidrpaQMRPXyJmDH4S1kl54Eu2KHaGmYkIRR1N2E3XUQhUtzFz cU222FedCGZ87y6Bsx96+BvATGUYo57RLeTpZowcBaz1qcZ16wZeZNiWXU4Zy6Jlcrtj 87CLerl8G94QfX3/lD1ITSP5Exa+bSe2lvUSVbSUedzNotByJ4yh7f/QlwZpPgI/2VVS Eyxw9kkjwE1lw9sl1dkkUpHGG9Hky5UKceqmWOx7Qh7HVH3caiqRnDdWIKmGVcS4BiZe 87nyqxMCvN1rKCZw0TvdtPS5dW10s29q3F3zpCeeDaA8oHeedaNKIZJIWCkIZUaICi4f dX1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=LKJfP1L1JthCk9j8S3dyGmOEwjYZHFg6bDruhwKHIGY=; b=Ni1/P3RixgwkzDM8MF4udRJklm7rNYP5w4MTbQHGYhS9pbG9m1t+5M1Ui+RQdN4JPy OjxzH0x2fqm2jgvJOekxlNRh4gEGRN+YtgY+EYSyFPVGtHt+J7UuoHDGuhMzaPP8q/8l w5Uc/WMFYIALEo9Eszytnv9sWAoptjWrC/VraITlCDNKFZEWNYbRr5S1Gt1MyiZ65tv1 I3SKDqbM1gf2iSrFO8J2f2yTBbPHRlJRGyIPVeaWF1IvvlRaIWUKhW18QhYZu0Z7iPya QmoJcbpZuMsSdahsfZ8yCvByqoFOxUPRdPNYUfFJOqrBM1HijsqX5OBV60tY6S4a4VPL 9CxA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="r4qh/tR1"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.57.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:57:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 58/68] target/nios2: Implement rdprs, wrprs Date: Fri, 22 Apr 2022 09:52:28 -0700 Message-Id: <20220422165238.1971496-59-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::12a; envelope-from=richard.henderson@linaro.org; helo=mail-il1-x12a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Implement these out of line, so that tcg global temps (aka the architectural registers) are synced back to tcg storage as required. This makes sure that we get the proper results when status.PRS == status.CRS. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-55-richard.henderson@linaro.org> --- target/nios2/cpu.h | 1 + target/nios2/helper.h | 2 ++ target/nios2/op_helper.c | 16 +++++++++++ target/nios2/translate.c | 57 ++++++++++++++++++++++++++++++++++++++-- 4 files changed, 74 insertions(+), 2 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index f6efaa79b3..cca821cf80 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -220,6 +220,7 @@ struct ArchCPU { bool diverr_present; bool mmu_present; + bool eic_present; uint32_t pid_num_bits; uint32_t tlb_num_ways; diff --git a/target/nios2/helper.h b/target/nios2/helper.h index 6f5ec60b0d..1648d76ade 100644 --- a/target/nios2/helper.h +++ b/target/nios2/helper.h @@ -24,6 +24,8 @@ DEF_HELPER_FLAGS_3(divu, TCG_CALL_NO_WG, i32, env, i32, i32) #if !defined(CONFIG_USER_ONLY) DEF_HELPER_3(eret, noreturn, env, i32, i32) +DEF_HELPER_FLAGS_2(rdprs, TCG_CALL_NO_WG, i32, env, i32) +DEF_HELPER_3(wrprs, void, env, i32, i32) DEF_HELPER_2(mmu_write_tlbacc, void, env, i32) DEF_HELPER_2(mmu_write_tlbmisc, void, env, i32) DEF_HELPER_2(mmu_write_pteaddr, void, env, i32) diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index 38a71a1f2d..a3164f5356 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -83,4 +83,20 @@ void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc) env->pc = new_pc; cpu_loop_exit(cs); } + +/* + * RDPRS and WRPRS are implemented out of line so that if PRS == CRS, + * all of the tcg global temporaries are synced back to ENV. + */ +uint32_t helper_rdprs(CPUNios2State *env, uint32_t regno) +{ + unsigned prs = FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, PRS); + return env->shadow_regs[prs][regno]; +} + +void helper_wrprs(CPUNios2State *env, uint32_t regno, uint32_t val) +{ + unsigned prs = FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, PRS); + env->shadow_regs[prs][regno] = val; +} #endif /* !CONFIG_USER_ONLY */ diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 363f2ea3ca..e566175db5 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -130,6 +130,7 @@ typedef struct DisasContext { uint32_t tb_flags; TCGv sink; const ControlRegState *cr_state; + bool eic_present; } DisasContext; static TCGv cpu_R[NUM_GP_REGS]; @@ -387,6 +388,27 @@ gen_i_math_logic(andhi, andi, 0, imm_shifted) gen_i_math_logic(orhi , ori, 1, imm_shifted) gen_i_math_logic(xorhi, xori, 1, imm_shifted) +/* rB <- prs.rA + sigma(IMM16) */ +static void rdprs(DisasContext *dc, uint32_t code, uint32_t flags) +{ + if (!dc->eic_present) { + t_gen_helper_raise_exception(dc, EXCP_ILLEGAL); + return; + } + if (!gen_check_supervisor(dc)) { + return; + } + +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + I_TYPE(instr, code); + TCGv dest = dest_gpr(dc, instr.b); + gen_helper_rdprs(dest, cpu_env, tcg_constant_i32(instr.a)); + tcg_gen_addi_tl(dest, dest, instr.imm16.s); +#endif +} + /* Prototype only, defined below */ static void handle_r_type_instr(DisasContext *dc, uint32_t code, uint32_t flags); @@ -448,7 +470,7 @@ static const Nios2Instruction i_type_instructions[] = { INSTRUCTION_FLG(gen_stx, MO_SL), /* stwio */ INSTRUCTION_FLG(gen_bxx, TCG_COND_LTU), /* bltu */ INSTRUCTION_FLG(gen_ldx, MO_UL), /* ldwio */ - INSTRUCTION_UNIMPLEMENTED(), /* rdprs */ + INSTRUCTION(rdprs), /* rdprs */ INSTRUCTION_ILLEGAL(), INSTRUCTION_FLG(handle_r_type_instr, 0), /* R-Type */ INSTRUCTION_NOP(), /* flushd */ @@ -648,6 +670,36 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags) #endif } +/* prs.rC <- rA */ +static void wrprs(DisasContext *dc, uint32_t code, uint32_t flags) +{ + if (!dc->eic_present) { + t_gen_helper_raise_exception(dc, EXCP_ILLEGAL); + return; + } + if (!gen_check_supervisor(dc)) { + return; + } + +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + R_TYPE(instr, code); + gen_helper_wrprs(cpu_env, tcg_constant_i32(instr.c), + load_gpr(dc, instr.a)); + /* + * The expected write to PRS[r0] is 0, from CRS[r0]. + * If not, and CRS == PRS (which we cannot tell from here), + * we may now have a non-zero value in our current r0. + * By ending the TB, we re-evaluate tb_flags and find out. + */ + if (instr.c == 0 + && (instr.a != 0 || !FIELD_EX32(dc->tb_flags, TBFLAGS, R0_0))) { + dc->base.is_jmp = DISAS_UPDATE; + } +#endif +} + /* Comparison instructions */ static void gen_cmpxx(DisasContext *dc, uint32_t code, uint32_t flags) { @@ -793,7 +845,7 @@ static const Nios2Instruction r_type_instructions[] = { INSTRUCTION_ILLEGAL(), INSTRUCTION(slli), /* slli */ INSTRUCTION(sll), /* sll */ - INSTRUCTION_UNIMPLEMENTED(), /* wrprs */ + INSTRUCTION(wrprs), /* wrprs */ INSTRUCTION_ILLEGAL(), INSTRUCTION(or), /* or */ INSTRUCTION(mulxsu), /* mulxsu */ @@ -895,6 +947,7 @@ static void nios2_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->mem_idx = cpu_mmu_index(env, false); dc->cr_state = cpu->cr_state; dc->tb_flags = dc->base.tb->flags; + dc->eic_present = cpu->eic_present; /* Bound the number of insns to execute to those left on the page. */ page_insns = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; From patchwork Fri Apr 22 16:52:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564888 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp697180map; Fri, 22 Apr 2022 10:47:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw7XdtVpvRmy6UJJbU9qTu+U1KT7YEwUz78UhBTM5fVvi1Z8aISmPdyX/tDOgiDSQxEAmqK X-Received: by 2002:ad4:5cac:0:b0:446:4417:c0be with SMTP id q12-20020ad45cac000000b004464417c0bemr4281464qvh.10.1650649625146; Fri, 22 Apr 2022 10:47:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650649625; cv=none; d=google.com; s=arc-20160816; b=yplOfictBuCdoLFxn0BbXgmGfKeOoekkvKuj6Rgvy8Cb7IDEv2Zc2VFbvouorLBWNg dNlARpg31DyauZr8/yu/FoBsBgwUrWloXcsOZrUngEuiriGJu2xjigadjJehnnFYUG8h 12bRpsvehrPV0dttNy2UYoh0Bc+GM2F/72EftTFAc3nCl1bFbNH7AG8XkaJThEzbd/Un S4okB8yHMcgZZNldILV6jQmYhOKFkiAIzG4KLQIiVTtKgXvd04r/PZ48652Mwxvs2p3z ASgUADVv85lkTKoRQ4EQwsWbC1ylJkoZsFoxbuCdiIT++I3mmEXrQyGsznuIBnxTfxua Lfbg== ARC-Message-Signature: i=1; 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.57.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:57:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 59/68] target/nios2: Update helper_eret for shadow registers Date: Fri, 22 Apr 2022 09:52:29 -0700 Message-Id: <20220422165238.1971496-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::12f; envelope-from=richard.henderson@linaro.org; helo=mail-il1-x12f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When CRS = 0, we restore from estatus; otherwise from sstatus. Update for the new CRS. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-56-richard.henderson@linaro.org> --- target/nios2/cpu.h | 1 + target/nios2/op_helper.c | 10 +++++++--- target/nios2/translate.c | 13 ++++++++----- 3 files changed, 16 insertions(+), 8 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index cca821cf80..eb171a33e6 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -82,6 +82,7 @@ enum { R_FP = 28, R_EA = 29, R_BA = 30, + R_SSTATUS = 30, R_RA = 31, }; diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index a3164f5356..94040102f4 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -73,14 +73,18 @@ void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc) } /* - * Both estatus and bstatus have no constraints on write; + * None of estatus, bstatus, or sstatus have constraints on write; * do not allow reserved fields in status to be set. - * TODO: more than this is required for shadow registers. + * When shadow registers are enabled, eret *does* restore CRS. + * Rather than testing eic_present to decide, mask CRS out of + * the set of readonly fields. */ - new_status &= cpu->cr_state[CR_STATUS].writable; + new_status &= cpu->cr_state[CR_STATUS].writable | + (cpu->cr_state[CR_STATUS].readonly & R_CR_STATUS_CRS_MASK); env->ctrl[CR_STATUS] = new_status; env->pc = new_pc; + nios2_update_crs(env); cpu_loop_exit(cs); } diff --git a/target/nios2/translate.c b/target/nios2/translate.c index e566175db5..b52f98180d 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -496,11 +496,14 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags) #ifdef CONFIG_USER_ONLY g_assert_not_reached(); #else - TCGv tmp = tcg_temp_new(); - tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_ESTATUS])); - gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_EA)); - tcg_temp_free(tmp); - + if (FIELD_EX32(dc->tb_flags, TBFLAGS, CRS0)) { + TCGv tmp = tcg_temp_new(); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_ESTATUS])); + gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_EA)); + tcg_temp_free(tmp); + } else { + gen_helper_eret(cpu_env, load_gpr(dc, R_SSTATUS), load_gpr(dc, R_EA)); + } dc->base.is_jmp = DISAS_NORETURN; #endif } From patchwork Fri Apr 22 16:52:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564894 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp700844map; Fri, 22 Apr 2022 10:52:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyb8p68Chq6NvhROTzrUADdKDcdNrrJQ9jPx3rZjQfuElu7aTbD+Ih7E1Fn7FalzLTAtJEi X-Received: by 2002:ac8:7d55:0:b0:2f3:458f:236f with SMTP id h21-20020ac87d55000000b002f3458f236fmr4206994qtb.251.1650649925707; Fri, 22 Apr 2022 10:52:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650649925; cv=none; d=google.com; s=arc-20160816; b=HPXFthAwELL+awpTFw/aRM28gJK+kKk3FiHXHME2ndDHg95LlFPg4nu+VQozdZ+S8H jIknfrU+XK2h9kdt0a0dV7r8jcogZ96oqu6UuIqZ6XPoqCUD0T66FqI3skebFzc58otH e3SWYhZeJ+swvl092nn8tFUooydB8CyNd6RVy1cx+ThcBlZApQlFssNDZ9ISJQF9efAA RtRJX/ii8WyxyQniaAS43DvVsKl5xqXeweOELCCfNBltnN79GY40ynM+XLQvFvklE3mO vO1BGkUWreKhvQYf2Ff3B2wUAj2z4iCweCSZTfroyj5AFLvgzbI4s44mVSK2mu/TkpjO EiUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=gvOrFvBE98DeoM6VCwJFK5z8shR3DGS8mknWCcWIlII=; b=QABi0NWnPRSWZkf2xSYtau4HJ5RlYmChD2XjTcS8lHNMeVRpGjJvyH4qiwJ767DfMq rdRCA8fTxXojWKu50+CtCJhoAmYUM1tuhNWGFWgA01+VfVJ6KQdNkYEwqGuoqKA7uf5t 18uPhUSFWotIwfIJTzgCdnTvxqvAu0wqPnAjztMH/ToQPn/v+Hsv19rrkQIVZSqV4w0A 8hnt+O3pnDZgVN3d4loDqQ5SXw3HyS7C32MUh13UK5XkCJp889qStUuSdBeSnEOl+OVW 4sVyKnOKOrewVc6C51Hz7dXeecJVCs1wBGI6B5L19ENxbmW5ZTC+22ddbcu69yCOWZ7W nD1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xXH3qR4X; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.57.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:57:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 60/68] target/nios2: Implement EIC interrupt processing Date: Fri, 22 Apr 2022 09:52:30 -0700 Message-Id: <20220422165238.1971496-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::12e; envelope-from=richard.henderson@linaro.org; helo=mail-il1-x12e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is the cpu side of the operation. Register one irq line, called EIC. Split out the rather different processing to a separate function. Delay initialization of gpio irqs until realize. We need to provide a window after init in which the board can set eic_present. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20220421151735.31996-57-richard.henderson@linaro.org> --- target/nios2/cpu.h | 8 ++++ target/nios2/cpu.c | 92 +++++++++++++++++++++++++++++++++---------- target/nios2/helper.c | 51 +++++++++++++++++++++++- 3 files changed, 129 insertions(+), 22 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index eb171a33e6..5474b1c404 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -114,6 +114,7 @@ FIELD(CR_STATUS, CRS, 10, 6) FIELD(CR_STATUS, PRS, 16, 6) FIELD(CR_STATUS, NMI, 22, 1) FIELD(CR_STATUS, RSIE, 23, 1) +FIELD(CR_STATUS, SRS, 31, 1) /* only in sstatus */ #define CR_STATUS_PIE R_CR_STATUS_PIE_MASK #define CR_STATUS_U R_CR_STATUS_U_MASK @@ -121,6 +122,7 @@ FIELD(CR_STATUS, RSIE, 23, 1) #define CR_STATUS_IH R_CR_STATUS_IH_MASK #define CR_STATUS_NMI R_CR_STATUS_NMI_MASK #define CR_STATUS_RSIE R_CR_STATUS_RSIE_MASK +#define CR_STATUS_SRS R_CR_STATUS_SRS_MASK FIELD(CR_EXCEPTION, CAUSE, 2, 5) FIELD(CR_EXCEPTION, ECCFTL, 31, 1) @@ -234,6 +236,12 @@ struct ArchCPU { /* Bits within each control register which are reserved or readonly. */ ControlRegState cr_state[NUM_CR_REGS]; + + /* External Interrupt Controller Interface */ + uint32_t rha; /* Requested handler address */ + uint32_t ril; /* Requested interrupt level */ + uint32_t rrs; /* Requested register set */ + bool rnmi; /* Requested nonmaskable interrupt */ }; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index d043c02fcd..19b2409974 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -63,7 +63,19 @@ static void nios2_cpu_reset(DeviceState *dev) } #ifndef CONFIG_USER_ONLY -static void nios2_cpu_set_irq(void *opaque, int irq, int level) +static void eic_set_irq(void *opaque, int irq, int level) +{ + Nios2CPU *cpu = opaque; + CPUState *cs = CPU(cpu); + + if (level) { + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } +} + +static void iic_set_irq(void *opaque, int irq, int level) { Nios2CPU *cpu = opaque; CPUNios2State *env = &cpu->env; @@ -87,15 +99,6 @@ static void nios2_cpu_initfn(Object *obj) #if !defined(CONFIG_USER_ONLY) mmu_init(&cpu->env); - - /* - * These interrupt lines model the IIC (internal interrupt - * controller). QEMU does not currently support the EIC - * (external interrupt controller) -- if we did it would be - * a separate device in hw/intc with a custom interface to - * the CPU, and boards using it would not wire up these IRQ lines. - */ - qdev_init_gpio_in_named(DEVICE(cpu), nios2_cpu_set_irq, "IRQ", 32); #endif } @@ -128,10 +131,18 @@ static void realize_cr_status(CPUState *cs) RO_REG(CR_EXCEPTION); WR_REG(CR_BADADDR); - /* TODO: These control registers are not present with the EIC. */ - RO_FIELD(CR_STATUS, RSIE); - WR_REG(CR_IENABLE); - RO_REG(CR_IPENDING); + if (cpu->eic_present) { + WR_FIELD(CR_STATUS, RSIE); + RO_FIELD(CR_STATUS, NMI); + WR_FIELD(CR_STATUS, PRS); + RO_FIELD(CR_STATUS, CRS); + WR_FIELD(CR_STATUS, IL); + WR_FIELD(CR_STATUS, IH); + } else { + RO_FIELD(CR_STATUS, RSIE); + WR_REG(CR_IENABLE); + RO_REG(CR_IPENDING); + } if (cpu->mmu_present) { WR_FIELD(CR_STATUS, U); @@ -170,6 +181,14 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp) Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(dev); Error *local_err = NULL; +#ifndef CONFIG_USER_ONLY + if (cpu->eic_present) { + qdev_init_gpio_in_named(DEVICE(cpu), eic_set_irq, "EIC", 1); + } else { + qdev_init_gpio_in_named(DEVICE(cpu), iic_set_irq, "IRQ", 32); + } +#endif + cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); @@ -187,17 +206,48 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp) } #ifndef CONFIG_USER_ONLY +static bool eic_take_interrupt(Nios2CPU *cpu) +{ + CPUNios2State *env = &cpu->env; + const uint32_t status = env->ctrl[CR_STATUS]; + + if (cpu->rnmi) { + return !(status & CR_STATUS_NMI); + } + if (!(status & CR_STATUS_PIE)) { + return false; + } + if (cpu->ril <= FIELD_EX32(status, CR_STATUS, IL)) { + return false; + } + if (cpu->rrs != FIELD_EX32(status, CR_STATUS, CRS)) { + return true; + } + return status & CR_STATUS_RSIE; +} + +static bool iic_take_interrupt(Nios2CPU *cpu) +{ + CPUNios2State *env = &cpu->env; + + if (!(env->ctrl[CR_STATUS] & CR_STATUS_PIE)) { + return false; + } + return env->ctrl[CR_IPENDING] & env->ctrl[CR_IENABLE]; +} + static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { Nios2CPU *cpu = NIOS2_CPU(cs); - CPUNios2State *env = &cpu->env; - if ((interrupt_request & CPU_INTERRUPT_HARD) && - (env->ctrl[CR_STATUS] & CR_STATUS_PIE) && - (env->ctrl[CR_IPENDING] & env->ctrl[CR_IENABLE])) { - cs->exception_index = EXCP_IRQ; - nios2_cpu_do_interrupt(cs); - return true; + if (interrupt_request & CPU_INTERRUPT_HARD) { + if (cpu->eic_present + ? eic_take_interrupt(cpu) + : iic_take_interrupt(cpu)) { + cs->exception_index = EXCP_IRQ; + nios2_cpu_do_interrupt(cs); + return true; + } } return false; } diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 2e9fea4a01..e256d1528e 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -37,6 +37,10 @@ static void do_exception(Nios2CPU *cpu, uint32_t exception_addr, uint32_t old_status = env->ctrl[CR_STATUS]; uint32_t new_status = old_status; + /* With shadow regs, exceptions are always taken into CRS 0. */ + new_status &= ~R_CR_STATUS_CRS_MASK; + env->regs = env->shadow_regs[0]; + if ((old_status & CR_STATUS_EH) == 0) { int r_ea = R_EA, cr_es = CR_ESTATUS; @@ -60,6 +64,14 @@ static void do_exception(Nios2CPU *cpu, uint32_t exception_addr, CR_TLBMISC_DBL); env->ctrl[CR_TLBMISC] |= tlbmisc_set; } + + /* + * With shadow regs, and EH == 0, PRS is set from CRS. + * At least, so says Table 3-9, and some other text, + * though Table 3-38 says otherwise. + */ + new_status = FIELD_DP32(new_status, CR_STATUS, PRS, + FIELD_EX32(old_status, CR_STATUS, CRS)); } new_status &= ~(CR_STATUS_PIE | CR_STATUS_U); @@ -77,6 +89,39 @@ static void do_iic_irq(Nios2CPU *cpu) do_exception(cpu, cpu->exception_addr, 0, false); } +static void do_eic_irq(Nios2CPU *cpu) +{ + CPUNios2State *env = &cpu->env; + uint32_t old_status = env->ctrl[CR_STATUS]; + uint32_t new_status = old_status; + uint32_t old_rs = FIELD_EX32(old_status, CR_STATUS, CRS); + uint32_t new_rs = cpu->rrs; + + new_status = FIELD_DP32(new_status, CR_STATUS, CRS, new_rs); + new_status = FIELD_DP32(new_status, CR_STATUS, IL, cpu->ril); + new_status = FIELD_DP32(new_status, CR_STATUS, NMI, cpu->rnmi); + new_status &= ~(CR_STATUS_RSIE | CR_STATUS_U); + new_status |= CR_STATUS_IH; + + if (!(new_status & CR_STATUS_EH)) { + new_status = FIELD_DP32(new_status, CR_STATUS, PRS, old_rs); + if (new_rs == 0) { + env->ctrl[CR_ESTATUS] = old_status; + } else { + if (new_rs != old_rs) { + old_status |= CR_STATUS_SRS; + } + env->shadow_regs[new_rs][R_SSTATUS] = old_status; + } + env->shadow_regs[new_rs][R_EA] = env->pc + 4; + } + + env->ctrl[CR_STATUS] = new_status; + nios2_update_crs(env); + + env->pc = cpu->rha; +} + void nios2_cpu_do_interrupt(CPUState *cs) { Nios2CPU *cpu = NIOS2_CPU(cs); @@ -142,7 +187,11 @@ void nios2_cpu_do_interrupt(CPUState *cs) switch (cs->exception_index) { case EXCP_IRQ: - do_iic_irq(cpu); + if (cpu->eic_present) { + do_eic_irq(cpu); + } else { + do_iic_irq(cpu); + } break; case EXCP_TLB_D: From patchwork Fri Apr 22 16:52:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564892 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp699391map; Fri, 22 Apr 2022 10:50:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzMKn7pwhjU/qxFLTi6YKOd29tqGA5FNgpnOEe1/2fdKcFe8MHpjzmddPRV31I61xYrOprf X-Received: by 2002:a05:6214:c26:b0:446:63cb:35eb with SMTP id a6-20020a0562140c2600b0044663cb35ebmr4336036qvd.63.1650649818772; Fri, 22 Apr 2022 10:50:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650649818; cv=none; d=google.com; s=arc-20160816; b=Rfjdp8xnBgYv1FpvOvWOk8pc28DVEX57Xggw3uoY8yLJvmMx2hBv7AREzLF76kFcA1 K/nqu6olszMrwVNOA13mvxRjEeGCZUTN1G+zG7dxOK2HT9DmEoIqkWfjGMeEf5QcyO/+ BQfbA1YbjDvKIHfsiWoHutfOnoDjoXrmOBJg7JrRMC7FzIPXG7s9hAl/ilhMOBM1nwlF IY0R3ZdE8oqf3iHWTqhqb90DqlQtkDLwOr1D2aVh49z/dVNYqquo68Ggw57MsEpa1yAL RtTYfhjSPfowGnjBd/RZLo0UjlfE7fL1YXOpNSkRVywKSe3Bi27nbGxI73Tup3o3xLt3 /6eg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=yl/OU+S3BuL9gmKdF4oRGlZZLlU0MEz8InOzJS1D9S0=; b=ufEMbc2W0kVlwWm93XPYQg/ATGvT5IZQA/dk6+ogSTbMaAH6cUUvhN/AxPNIYjABee qwPRj6igkuAxJ7XlZnRTMutW7yfff2D3X+O59WXfHXNusThYU3I1EN0y8wpdKg2kTNXs EMbYzuOD4akQxcPu6wNNxYjpqzYGhr9hTnJUOveN8ybh9/u0q4vGsRG63Dnv5jo/+BvU 6oKrUfChdDBdrt/7U2X/xb7ALfKSDZmYFtSPYqLrYA8WIkoDhpvD8hCRximUr+/YlxbR 9nBWH1XY/rdnr1pUoEwkUbiortAoYn+oUTPb2hctqm2VOC4M1Z8DmiT8c+BXRUSxot7/ LMEg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="T/zEIHtO"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.57.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:57:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 61/68] target/nios2: Advance pc when raising exceptions Date: Fri, 22 Apr 2022 09:52:31 -0700 Message-Id: <20220422165238.1971496-62-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::12a; envelope-from=richard.henderson@linaro.org; helo=mail-il1-x12a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The exception return address for nios2 is the instruction after the one that was executing at the time of the exception. We have so far implemented this by advancing the pc during the process of raising the exception. It is perhaps a little less confusing to do this advance in the translator (and helpers) when raising the exception in the first place, so that we may more closely match kernel sources. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20220421151735.31996-58-richard.henderson@linaro.org> --- target/nios2/cpu.h | 2 ++ linux-user/nios2/cpu_loop.c | 8 ++------ target/nios2/helper.c | 13 +++++++------ target/nios2/op_helper.c | 18 ++++++++++++++++-- target/nios2/translate.c | 6 +++--- 5 files changed, 30 insertions(+), 17 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 5474b1c404..f85581ee56 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -266,6 +266,8 @@ hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); G_NORETURN void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); +G_NORETURN void nios2_cpu_loop_exit_advance(CPUNios2State *env, + uintptr_t retaddr); void do_nios2_semihosting(CPUNios2State *env); diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index 30a27f252b..a5e86990e2 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -39,6 +39,8 @@ void cpu_loop(CPUNios2State *env) break; case EXCP_DIV: + /* Match kernel's handle_diverror_c(). */ + env->pc -= 4; force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->pc); break; @@ -49,12 +51,6 @@ void cpu_loop(CPUNios2State *env) break; case EXCP_TRAP: - /* - * TODO: This advance should be done in the translator, as - * hardware produces an advanced pc as part of all exceptions. - */ - env->pc += 4; - switch (env->error_code) { case 0: qemu_log_mask(CPU_LOG_INT, "\nSyscall\n"); diff --git a/target/nios2/helper.c b/target/nios2/helper.c index e256d1528e..bb3b09e5a7 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -49,7 +49,7 @@ static void do_exception(Nios2CPU *cpu, uint32_t exception_addr, cr_es = CR_BSTATUS; } env->ctrl[cr_es] = old_status; - env->regs[r_ea] = env->pc + 4; + env->regs[r_ea] = env->pc; if (cpu->mmu_present) { new_status |= CR_STATUS_EH; @@ -113,7 +113,7 @@ static void do_eic_irq(Nios2CPU *cpu) } env->shadow_regs[new_rs][R_SSTATUS] = old_status; } - env->shadow_regs[new_rs][R_EA] = env->pc + 4; + env->shadow_regs[new_rs][R_EA] = env->pc; } env->ctrl[CR_STATUS] = new_status; @@ -187,6 +187,8 @@ void nios2_cpu_do_interrupt(CPUState *cs) switch (cs->exception_index) { case EXCP_IRQ: + /* Note that PC is advanced for interrupts as well. */ + env->pc += 4; if (cpu->eic_present) { do_eic_irq(cpu); } else { @@ -249,7 +251,6 @@ void nios2_cpu_do_interrupt(CPUState *cs) break; case EXCP_SEMIHOST: - env->pc += 4; do_nios2_semihosting(env); break; @@ -291,7 +292,7 @@ void nios2_cpu_do_unaligned_access(CPUState *cs, vaddr addr, env->ctrl[CR_BADADDR] = addr; cs->exception_index = EXCP_UNALIGN; - cpu_loop_exit_restore(cs, retaddr); + nios2_cpu_loop_exit_advance(env, retaddr); } bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, @@ -330,7 +331,7 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, cs->exception_index = (access_type == MMU_INST_FETCH ? EXCP_SUPERA_X : EXCP_SUPERA_D); env->ctrl[CR_BADADDR] = address; - cpu_loop_exit_restore(cs, retaddr); + nios2_cpu_loop_exit_advance(env, retaddr); } } @@ -367,5 +368,5 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, cs->exception_index = excp; env->ctrl[CR_BADADDR] = address; - cpu_loop_exit_restore(cs, retaddr); + nios2_cpu_loop_exit_advance(env, retaddr); } diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index 94040102f4..2e30d0a908 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -31,6 +31,20 @@ void helper_raise_exception(CPUNios2State *env, uint32_t index) cpu_loop_exit(cs); } +void nios2_cpu_loop_exit_advance(CPUNios2State *env, uintptr_t retaddr) +{ + CPUState *cs = env_cpu(env); + + /* + * Note that PC is advanced for all hardware exceptions. + * Do this here, rather than in restore_state_to_opc(), + * lest we affect QEMU internal exceptions, like EXCP_DEBUG. + */ + cpu_restore_state(cs, retaddr, true); + env->pc += 4; + cpu_loop_exit(cs); +} + static void maybe_raise_div(CPUNios2State *env, uintptr_t ra) { Nios2CPU *cpu = env_archcpu(env); @@ -38,7 +52,7 @@ static void maybe_raise_div(CPUNios2State *env, uintptr_t ra) if (cpu->diverr_present) { cs->exception_index = EXCP_DIV; - cpu_loop_exit_restore(cs, ra); + nios2_cpu_loop_exit_advance(env, ra); } } @@ -69,7 +83,7 @@ void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc) if (unlikely(new_pc & 3)) { env->ctrl[CR_BADADDR] = new_pc; cs->exception_index = EXCP_UNALIGND; - cpu_loop_exit_restore(cs, GETPC()); + nios2_cpu_loop_exit_advance(env, GETPC()); } /* diff --git a/target/nios2/translate.c b/target/nios2/translate.c index b52f98180d..3a037a68cc 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -202,10 +202,10 @@ static TCGv dest_gpr(DisasContext *dc, unsigned reg) #endif } -static void t_gen_helper_raise_exception(DisasContext *dc, - uint32_t index) +static void t_gen_helper_raise_exception(DisasContext *dc, uint32_t index) { - tcg_gen_movi_tl(cpu_pc, dc->pc); + /* Note that PC is advanced for all hardware exceptions. */ + tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); gen_helper_raise_exception(cpu_env, tcg_constant_i32(index)); dc->base.is_jmp = DISAS_NORETURN; } From patchwork Fri Apr 22 16:52:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564889 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp698225map; Fri, 22 Apr 2022 10:48:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxQr34bqtSE9o6z92QLeIQHFPWG5i7Ntt3S7wvhh/SYXcUhQQ0KCJWlsxvkj7zqV/Zg7fKZ X-Received: by 2002:a5b:482:0:b0:646:b85:ad4a with SMTP id n2-20020a5b0482000000b006460b85ad4amr1068025ybp.89.1650649723871; Fri, 22 Apr 2022 10:48:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650649723; cv=none; d=google.com; s=arc-20160816; b=lSb4X30Wnz8X/R+Q/lqfi7wfjTDNPMBW8fXQ88PMBPWpOO5c792tthvn2uDC0Slx3F c5TfJoD+xLR2xcOTfSM9kUs+egtmV1EK2xKdMBA0R4euy0kyjejFeGhXxRVvB2xtpjah mQ43YKtgblb35rD+qW1M9DRWMJ1yFSX/6RlLfmYtXj2ZwEY/NmQckn4NPGo3LSH9eWPO MfoJAaa24fFkBCXgM8DHAW7HMhZ3kCwfcTCcf45HZtIgvCLdasT66UsENU9nm0n2Jiov Iggq8w89eedmaHFPHJviI9IfWpUrpzRkNGCT++oDZwotl20Yh5w6RkCm4DQTop2+E88i PrGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=KOjXySDL0Ufzbbr9M/xH36yPYqmTAVv3+nLLoSnWdKg=; b=AbBMkLA7zslirHmlG10r0NCMUgDAO3yGEP4DO9Fk0X0V1Fc7cspZfKXyWi5SsnCV/G rMF9rDPU6LK0IhcNzqPPBfkJt/DTKcMKzb2WNSUumwON58SxHIr8d5ESGojDX5z7WSSy WIpF9a1txeC1PCgz88zJVfoJFnuaoOeViokIyfoZUUksW+/iIP2n2Ifvv+IEezvmcSsf +tBCAynj3tGdPEP+X96c5opTRHnXJMf+xX8OtAc/igKog0n/No6HpvHaV+G3aCSAMvAR lPQL3gkohvCU9OQYPJZUUgctlUd/Pz0hA2Ig8x2gWUYIJy2WRSFkOxWB87W+Am+u6B0G BYdg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AiRXOo49; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.57.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:57:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 62/68] linux-user/nios2: Handle various SIGILL exceptions Date: Fri, 22 Apr 2022 09:52:32 -0700 Message-Id: <20220422165238.1971496-63-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d30; envelope-from=richard.henderson@linaro.org; helo=mail-io1-xd30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We missed out on a couple of exception types that may legitimately be raised by a userland program. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-59-richard.henderson@linaro.org> --- linux-user/nios2/cpu_loop.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index a5e86990e2..da77ede76b 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -50,6 +50,18 @@ void cpu_loop(CPUNios2State *env) env->ctrl[CR_BADADDR]); break; + case EXCP_ILLEGAL: + case EXCP_UNIMPL: + /* Match kernel's handle_illegal_c(). */ + env->pc -= 4; + force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->pc); + break; + case EXCP_SUPERI: + /* Match kernel's handle_supervisor_instr(). */ + env->pc -= 4; + force_sig_fault(TARGET_SIGILL, TARGET_ILL_PRVOPC, env->pc); + break; + case EXCP_TRAP: switch (env->error_code) { case 0: From patchwork Fri Apr 22 16:52:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564903 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp710450map; Fri, 22 Apr 2022 11:04:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwIyc5VQBIsmYygRP81OzwpXkItEKU95sDDwBS+GHRHlyoITIBqXMWkesWonu3VCQH+Gbzh X-Received: by 2002:a81:4e11:0:b0:2f1:47a0:5972 with SMTP id c17-20020a814e11000000b002f147a05972mr6387740ywb.469.1650650669718; Fri, 22 Apr 2022 11:04:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650650669; cv=none; d=google.com; s=arc-20160816; b=NUbkB76ln7d5H52UnzwtBubmcTk5z3AqxUGUc1YWyJWRchXsygW+nmuNAgxe9ALlx7 43daviG8geERgocJRRxVvEgovRC9WQSum0zIaMnDtBBz7WSwoegjXGZNeC+OCoJsICci H0zkOAYpue1rjEaGfrkbowDhCI2RCAc9j59GHFBK3g9cITY12b4ww89hzkTHGFeHsIBC hX7cRd5CV/TsUWKo3Aq+/9qs/QnRdogybRGEmLcFhT+L0rxl/sLm1MNaGTC7RL1SQyCb +7w0a4G7v2nWpYQ0MRa5/TQvG7miqpTARoPN3p7V0n4WXCyX6FijfGwuaYW/3wexI4xL 0a8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=P3V+FtoVYZUI41p0htZymMgazIyPkYC70RlRxt6vbn8=; b=CnqfAOnMWUFcWbYUBPYhSaRtq15Bp1ZtImJl3QpiZNaMemZcPBgu6XECMP9vLNrJJ7 /ls4ajDBCBr18dz10BMLRNyADw6oCMQPX4VoEM+WXEA0KLpuweY8xp6Bwh1TS7QrjnCU 3xmQ2wNySDFCQW5Ghyss2ljkGZkZWwqCtviVFkYBzVitpBJ4qytD+GiC4xzDArhXZMAt pL724zA0h2S/DwnVsdHbIEpTcrw58+Zge4+EJ36a2y2jncr5rqDb7dGJgw8udINU4etr y1vREvwajln7OVgsGOCzEYNJgAB3CvkNtWIWRfBnWP81YbD2O6jAR9RhYWTEN9wtNdCi q4Zg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SEp70tXR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.57.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:57:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 63/68] hw/intc: Vectored Interrupt Controller (VIC) Date: Fri, 22 Apr 2022 09:52:33 -0700 Message-Id: <20220422165238.1971496-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d31; envelope-from=richard.henderson@linaro.org; helo=mail-io1-xd31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Amir Gonnen Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Amir Gonnen Implement nios2 Vectored Interrupt Controller (VIC). VIC is connected to EIC. It needs to update rha, ril, rrs and rnmi fields on Nios2CPU before raising an IRQ. For that purpose, VIC has a "cpu" property which should refer to the nios2 cpu and set by the board that connects VIC. Reviewed-by: Peter Maydell Signed-off-by: Amir Gonnen Message-Id: <20220303153906.2024748-5-amir.gonnen@neuroblade.ai> [rth: Split out nios2_vic.h] Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-60-richard.henderson@linaro.org> --- include/hw/intc/nios2_vic.h | 64 ++++++++ hw/intc/nios2_vic.c | 313 ++++++++++++++++++++++++++++++++++++ hw/intc/Kconfig | 3 + hw/intc/meson.build | 1 + 4 files changed, 381 insertions(+) create mode 100644 include/hw/intc/nios2_vic.h create mode 100644 hw/intc/nios2_vic.c diff --git a/include/hw/intc/nios2_vic.h b/include/hw/intc/nios2_vic.h new file mode 100644 index 0000000000..af1517a967 --- /dev/null +++ b/include/hw/intc/nios2_vic.h @@ -0,0 +1,64 @@ +/* + * Vectored Interrupt Controller for nios2 processor + * + * Copyright (c) 2022 Neuroblade + * + * Interface: + * QOM property "cpu": link to the Nios2 CPU (must be set) + * Unnamed GPIO inputs 0..NIOS2_VIC_MAX_IRQ-1: input IRQ lines + * IRQ should be connected to nios2 IRQ0. + * + * Reference: "Embedded Peripherals IP User Guide + * for Intel® Quartus® Prime Design Suite: 21.4" + * Chapter 38 "Vectored Interrupt Controller Core" + * See: https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/vectored-interrupt-controller-core.html + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HW_INTC_NIOS2_VIC +#define HW_INTC_NIOS2_VIC + +#define TYPE_NIOS2_VIC "nios2-vic" +OBJECT_DECLARE_SIMPLE_TYPE(Nios2VIC, NIOS2_VIC) + +#define NIOS2_VIC_MAX_IRQ 32 + +struct Nios2VIC { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + qemu_irq output_int; + + /* properties */ + CPUState *cpu; + MemoryRegion csr; + + uint32_t int_config[NIOS2_VIC_MAX_IRQ]; + uint32_t vic_config; + uint32_t int_raw_status; + uint32_t int_enable; + uint32_t sw_int; + uint32_t vic_status; + uint32_t vec_tbl_base; + uint32_t vec_tbl_addr; +}; + +#endif /* HW_INTC_NIOS2_VIC */ diff --git a/hw/intc/nios2_vic.c b/hw/intc/nios2_vic.c new file mode 100644 index 0000000000..cf63212a88 --- /dev/null +++ b/hw/intc/nios2_vic.c @@ -0,0 +1,313 @@ +/* + * Vectored Interrupt Controller for nios2 processor + * + * Copyright (c) 2022 Neuroblade + * + * Interface: + * QOM property "cpu": link to the Nios2 CPU (must be set) + * Unnamed GPIO inputs 0..NIOS2_VIC_MAX_IRQ-1: input IRQ lines + * IRQ should be connected to nios2 IRQ0. + * + * Reference: "Embedded Peripherals IP User Guide + * for Intel® Quartus® Prime Design Suite: 21.4" + * Chapter 38 "Vectored Interrupt Controller Core" + * See: https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/vectored-interrupt-controller-core.html + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" + +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qapi/error.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qom/object.h" +#include "hw/intc/nios2_vic.h" +#include "cpu.h" + + +enum { + INT_CONFIG0 = 0, + INT_CONFIG31 = 31, + INT_ENABLE = 32, + INT_ENABLE_SET = 33, + INT_ENABLE_CLR = 34, + INT_PENDING = 35, + INT_RAW_STATUS = 36, + SW_INTERRUPT = 37, + SW_INTERRUPT_SET = 38, + SW_INTERRUPT_CLR = 39, + VIC_CONFIG = 40, + VIC_STATUS = 41, + VEC_TBL_BASE = 42, + VEC_TBL_ADDR = 43, + CSR_COUNT /* Last! */ +}; + +/* Requested interrupt level (INT_CONFIG[0:5]) */ +static inline uint32_t vic_int_config_ril(const Nios2VIC *vic, int irq_num) +{ + return extract32(vic->int_config[irq_num], 0, 6); +} + +/* Requested NMI (INT_CONFIG[6]) */ +static inline uint32_t vic_int_config_rnmi(const Nios2VIC *vic, int irq_num) +{ + return extract32(vic->int_config[irq_num], 6, 1); +} + +/* Requested register set (INT_CONFIG[7:12]) */ +static inline uint32_t vic_int_config_rrs(const Nios2VIC *vic, int irq_num) +{ + return extract32(vic->int_config[irq_num], 7, 6); +} + +static inline uint32_t vic_config_vec_size(const Nios2VIC *vic) +{ + return 1 << (2 + extract32(vic->vic_config, 0, 3)); +} + +static inline uint32_t vic_int_pending(const Nios2VIC *vic) +{ + return (vic->int_raw_status | vic->sw_int) & vic->int_enable; +} + +static void vic_update_irq(Nios2VIC *vic) +{ + Nios2CPU *cpu = NIOS2_CPU(vic->cpu); + uint32_t pending = vic_int_pending(vic); + int irq = -1; + int max_ril = 0; + /* Note that if RIL is 0 for an interrupt it is effectively disabled */ + + vic->vec_tbl_addr = 0; + vic->vic_status = 0; + + if (pending == 0) { + qemu_irq_lower(vic->output_int); + return; + } + + for (int i = 0; i < NIOS2_VIC_MAX_IRQ; i++) { + if (pending & BIT(i)) { + int ril = vic_int_config_ril(vic, i); + if (ril > max_ril) { + irq = i; + max_ril = ril; + } + } + } + + if (irq < 0) { + qemu_irq_lower(vic->output_int); + return; + } + + vic->vec_tbl_addr = irq * vic_config_vec_size(vic) + vic->vec_tbl_base; + vic->vic_status = irq | BIT(31); + + /* + * In hardware, the interface between the VIC and the CPU is via the + * External Interrupt Controller interface, where the interrupt controller + * presents the CPU with a packet of data containing: + * - Requested Handler Address (RHA): 32 bits + * - Requested Register Set (RRS) : 6 bits + * - Requested Interrupt Level (RIL) : 6 bits + * - Requested NMI flag (RNMI) : 1 bit + * In our emulation, we implement this by writing the data directly to + * fields in the CPU object and then raising the IRQ line to tell + * the CPU that we've done so. + */ + + cpu->rha = vic->vec_tbl_addr; + cpu->ril = max_ril; + cpu->rrs = vic_int_config_rrs(vic, irq); + cpu->rnmi = vic_int_config_rnmi(vic, irq); + + qemu_irq_raise(vic->output_int); +} + +static void vic_set_irq(void *opaque, int irq_num, int level) +{ + Nios2VIC *vic = opaque; + + vic->int_raw_status = deposit32(vic->int_raw_status, irq_num, 1, !!level); + vic_update_irq(vic); +} + +static void nios2_vic_reset(DeviceState *dev) +{ + Nios2VIC *vic = NIOS2_VIC(dev); + + memset(&vic->int_config, 0, sizeof(vic->int_config)); + vic->vic_config = 0; + vic->int_raw_status = 0; + vic->int_enable = 0; + vic->sw_int = 0; + vic->vic_status = 0; + vic->vec_tbl_base = 0; + vic->vec_tbl_addr = 0; +} + +static uint64_t nios2_vic_csr_read(void *opaque, hwaddr offset, unsigned size) +{ + Nios2VIC *vic = opaque; + int index = offset / 4; + + switch (index) { + case INT_CONFIG0 ... INT_CONFIG31: + return vic->int_config[index - INT_CONFIG0]; + case INT_ENABLE: + return vic->int_enable; + case INT_PENDING: + return vic_int_pending(vic); + case INT_RAW_STATUS: + return vic->int_raw_status; + case SW_INTERRUPT: + return vic->sw_int; + case VIC_CONFIG: + return vic->vic_config; + case VIC_STATUS: + return vic->vic_status; + case VEC_TBL_BASE: + return vic->vec_tbl_base; + case VEC_TBL_ADDR: + return vic->vec_tbl_addr; + default: + return 0; + } +} + +static void nios2_vic_csr_write(void *opaque, hwaddr offset, uint64_t value, + unsigned size) +{ + Nios2VIC *vic = opaque; + int index = offset / 4; + + switch (index) { + case INT_CONFIG0 ... INT_CONFIG31: + vic->int_config[index - INT_CONFIG0] = value; + break; + case INT_ENABLE: + vic->int_enable = value; + break; + case INT_ENABLE_SET: + vic->int_enable |= value; + break; + case INT_ENABLE_CLR: + vic->int_enable &= ~value; + break; + case SW_INTERRUPT: + vic->sw_int = value; + break; + case SW_INTERRUPT_SET: + vic->sw_int |= value; + break; + case SW_INTERRUPT_CLR: + vic->sw_int &= ~value; + break; + case VIC_CONFIG: + vic->vic_config = value; + break; + case VEC_TBL_BASE: + vic->vec_tbl_base = value; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "nios2-vic: write to invalid CSR address %#" + HWADDR_PRIx "\n", offset); + } + + vic_update_irq(vic); +} + +static const MemoryRegionOps nios2_vic_csr_ops = { + .read = nios2_vic_csr_read, + .write = nios2_vic_csr_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { .min_access_size = 4, .max_access_size = 4 } +}; + +static void nios2_vic_realize(DeviceState *dev, Error **errp) +{ + Nios2VIC *vic = NIOS2_VIC(dev); + + if (!vic->cpu) { + /* This is a programming error in the code using this device */ + error_setg(errp, "nios2-vic 'cpu' link property was not set"); + return; + } + + sysbus_init_irq(SYS_BUS_DEVICE(dev), &vic->output_int); + qdev_init_gpio_in(dev, vic_set_irq, NIOS2_VIC_MAX_IRQ); + + memory_region_init_io(&vic->csr, OBJECT(dev), &nios2_vic_csr_ops, vic, + "nios2.vic.csr", CSR_COUNT * sizeof(uint32_t)); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &vic->csr); +} + +static Property nios2_vic_properties[] = { + DEFINE_PROP_LINK("cpu", Nios2VIC, cpu, TYPE_CPU, CPUState *), + DEFINE_PROP_END_OF_LIST() +}; + +static const VMStateDescription nios2_vic_vmstate = { + .name = "nios2-vic", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]){ + VMSTATE_UINT32_ARRAY(int_config, Nios2VIC, 32), + VMSTATE_UINT32(vic_config, Nios2VIC), + VMSTATE_UINT32(int_raw_status, Nios2VIC), + VMSTATE_UINT32(int_enable, Nios2VIC), + VMSTATE_UINT32(sw_int, Nios2VIC), + VMSTATE_UINT32(vic_status, Nios2VIC), + VMSTATE_UINT32(vec_tbl_base, Nios2VIC), + VMSTATE_UINT32(vec_tbl_addr, Nios2VIC), + VMSTATE_END_OF_LIST() + }, +}; + +static void nios2_vic_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = nios2_vic_reset; + dc->realize = nios2_vic_realize; + dc->vmsd = &nios2_vic_vmstate; + device_class_set_props(dc, nios2_vic_properties); +} + +static const TypeInfo nios2_vic_info = { + .name = TYPE_NIOS2_VIC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(Nios2VIC), + .class_init = nios2_vic_class_init, +}; + +static void nios2_vic_register_types(void) +{ + type_register_static(&nios2_vic_info); +} + +type_init(nios2_vic_register_types); diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index a7cf301eab..eded1b557e 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -84,3 +84,6 @@ config GOLDFISH_PIC config M68K_IRQC bool + +config NIOS2_VIC + bool diff --git a/hw/intc/meson.build b/hw/intc/meson.build index d6d012fb26..8b35139f82 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -62,3 +62,4 @@ specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'], if_true: files('spapr_xive_kvm.c')) specific_ss.add(when: 'CONFIG_GOLDFISH_PIC', if_true: files('goldfish_pic.c')) specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c')) +specific_ss.add(when: 'CONFIG_NIOS2_VIC', if_true: files('nios2_vic.c')) From patchwork Fri Apr 22 16:52:34 2022 Content-Type: text/plain; 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.57.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:57:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 64/68] hw/nios2: Introduce Nios2MachineState Date: Fri, 22 Apr 2022 09:52:34 -0700 Message-Id: <20220422165238.1971496-65-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::132; envelope-from=richard.henderson@linaro.org; helo=mail-il1-x132.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We want to move data from the heap into Nios2MachineState, which is not possible with DEFINE_MACHINE. Reviewed-by: Mark Cave-Ayland Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-61-richard.henderson@linaro.org> --- hw/nios2/10m50_devboard.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c index 3d1205b8bd..bdc3ffd50d 100644 --- a/hw/nios2/10m50_devboard.c +++ b/hw/nios2/10m50_devboard.c @@ -36,6 +36,13 @@ #include "boot.h" +struct Nios2MachineState { + MachineState parent_obj; +}; + +#define TYPE_NIOS2_MACHINE MACHINE_TYPE_NAME("10m50-ghrd") +OBJECT_DECLARE_TYPE(Nios2MachineState, MachineClass, NIOS2_MACHINE) + #define BINARY_DEVICE_TREE_FILE "10m50-devboard.dtb" static void nios2_10m50_ghrd_init(MachineState *machine) @@ -105,11 +112,24 @@ static void nios2_10m50_ghrd_init(MachineState *machine) BINARY_DEVICE_TREE_FILE, NULL); } -static void nios2_10m50_ghrd_machine_init(struct MachineClass *mc) +static void nios2_10m50_ghrd_class_init(ObjectClass *oc, void *data) { + MachineClass *mc = MACHINE_CLASS(oc); + mc->desc = "Altera 10M50 GHRD Nios II design"; mc->init = nios2_10m50_ghrd_init; mc->is_default = true; } -DEFINE_MACHINE("10m50-ghrd", nios2_10m50_ghrd_machine_init); +static const TypeInfo nios2_10m50_ghrd_type_info = { + .name = TYPE_NIOS2_MACHINE, + .parent = TYPE_MACHINE, + .instance_size = sizeof(Nios2MachineState), + .class_init = nios2_10m50_ghrd_class_init, +}; + +static void nios2_10m50_ghrd_type_init(void) +{ + type_register_static(&nios2_10m50_ghrd_type_info); +} +type_init(nios2_10m50_ghrd_type_init); From patchwork Fri Apr 22 16:52:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564896 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp701726map; Fri, 22 Apr 2022 10:53:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJykUEKFZj2DLuo5GMpF5TnO8Myzb+urFKMhbQQt7QipgWUSBd2hNZyMHlJhgUs4Tg3+6oXa X-Received: by 2002:a05:622a:144:b0:2f3:3bbd:3db5 with SMTP id v4-20020a05622a014400b002f33bbd3db5mr4234810qtw.95.1650650000807; Fri, 22 Apr 2022 10:53:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650650000; cv=none; d=google.com; s=arc-20160816; b=g6IUf1i3liSi6h9QNSKYJ6UrA6KmR+ay9owIZaGbP8i+show5wwa0moXubq9HhVI8s 1AkvEwXOhjf15fxyihKKFR0BrX2AWt1kd6cRfbja1SrlqTNLtIbzU7CVL3CHSKrS8jxg R78vrJvh9U5LabDySR8YML+JiaCVSWRFERYp5THvLYP9luDYIDw41uSY0N2NrOcpqJFk P58CbbnYpaZ0fqYeO5Jks8ol1+1krqGOxdJgklu7LlvJWhOiqXb6YVJm9FsGUmViHv+x ivlRTvEcRgymOW76i8OEd6vDt2fCZPwEbkAL5Ys26osj26Mkl0Am5LAHfeK04l1NwGXx tUQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=zhY6IsLbZViijjLfLFhbBpoo7RTXZotmcRSvMZEYx1c=; b=zCagSGzFkX+2ZFKaor09PIwgA043wErc+tpBln+Nyx7MRHmXwhHmO5Oy+KFGiKniyR vClC23Ppn5QgI7DTdUl9X6jgqYWSOzEQ4fATk/iKbdRYwqAJQt68fojYvDLp8lcgE0Bi xJpmZHQrHXGH4tcJiwqF76arg99fYTh7hbKkihrfkqdf2YNit5CcCTGIQT7LhSy+FUfj rLAlh/Yde+mGQT+fDcXdbeih2alwZ7N67K0zLPTnntp/p5FOXqC7oBvs3Ilo0JFSUysL 1Q+FKpfTkHq2pjSmr408RHjmdP4LdIg6WpFGg4HX/IrnmhXz0tNfhKCq0OkxWoSNQJga RU3A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NKcDwOEr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.57.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:57:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 65/68] hw/nios2: Move memory regions into Nios2Machine Date: Fri, 22 Apr 2022 09:52:35 -0700 Message-Id: <20220422165238.1971496-66-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::12d; envelope-from=richard.henderson@linaro.org; helo=mail-il1-x12d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert to contiguous allocation, as much as possible so far. The two timer objects are not exposed for subobject allocation. Reviewed-by: Mark Cave-Ayland Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-62-richard.henderson@linaro.org> --- hw/nios2/10m50_devboard.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c index bdc3ffd50d..dda4ab2bf5 100644 --- a/hw/nios2/10m50_devboard.c +++ b/hw/nios2/10m50_devboard.c @@ -38,6 +38,11 @@ struct Nios2MachineState { MachineState parent_obj; + + MemoryRegion phys_tcm; + MemoryRegion phys_tcm_alias; + MemoryRegion phys_ram; + MemoryRegion phys_ram_alias; }; #define TYPE_NIOS2_MACHINE MACHINE_TYPE_NAME("10m50-ghrd") @@ -47,13 +52,10 @@ OBJECT_DECLARE_TYPE(Nios2MachineState, MachineClass, NIOS2_MACHINE) static void nios2_10m50_ghrd_init(MachineState *machine) { + Nios2MachineState *nms = NIOS2_MACHINE(machine); Nios2CPU *cpu; DeviceState *dev; MemoryRegion *address_space_mem = get_system_memory(); - MemoryRegion *phys_tcm = g_new(MemoryRegion, 1); - MemoryRegion *phys_tcm_alias = g_new(MemoryRegion, 1); - MemoryRegion *phys_ram = g_new(MemoryRegion, 1); - MemoryRegion *phys_ram_alias = g_new(MemoryRegion, 1); ram_addr_t tcm_base = 0x0; ram_addr_t tcm_size = 0x1000; /* 1 kiB, but QEMU limit is 4 kiB */ ram_addr_t ram_base = 0x08000000; @@ -62,22 +64,22 @@ static void nios2_10m50_ghrd_init(MachineState *machine) int i; /* Physical TCM (tb_ram_1k) with alias at 0xc0000000 */ - memory_region_init_ram(phys_tcm, NULL, "nios2.tcm", tcm_size, + memory_region_init_ram(&nms->phys_tcm, NULL, "nios2.tcm", tcm_size, &error_abort); - memory_region_init_alias(phys_tcm_alias, NULL, "nios2.tcm.alias", - phys_tcm, 0, tcm_size); - memory_region_add_subregion(address_space_mem, tcm_base, phys_tcm); + memory_region_init_alias(&nms->phys_tcm_alias, NULL, "nios2.tcm.alias", + &nms->phys_tcm, 0, tcm_size); + memory_region_add_subregion(address_space_mem, tcm_base, &nms->phys_tcm); memory_region_add_subregion(address_space_mem, 0xc0000000 + tcm_base, - phys_tcm_alias); + &nms->phys_tcm_alias); /* Physical DRAM with alias at 0xc0000000 */ - memory_region_init_ram(phys_ram, NULL, "nios2.ram", ram_size, + memory_region_init_ram(&nms->phys_ram, NULL, "nios2.ram", ram_size, &error_abort); - memory_region_init_alias(phys_ram_alias, NULL, "nios2.ram.alias", - phys_ram, 0, ram_size); - memory_region_add_subregion(address_space_mem, ram_base, phys_ram); + memory_region_init_alias(&nms->phys_ram_alias, NULL, "nios2.ram.alias", + &nms->phys_ram, 0, ram_size); + memory_region_add_subregion(address_space_mem, ram_base, &nms->phys_ram); memory_region_add_subregion(address_space_mem, 0xc0000000 + ram_base, - phys_ram_alias); + &nms->phys_ram_alias); /* Create CPU -- FIXME */ cpu = NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU)); From patchwork Fri Apr 22 16:52:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564900 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp704926map; Fri, 22 Apr 2022 10:58:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx9qrPf0DaWzFhB2P5k8n8IjDq6XdfIzESszubyPJ/CdIbFxVum0WBBU2IwRnNckPq2xlwU X-Received: by 2002:a81:5210:0:b0:2ef:21e3:54dd with SMTP id g16-20020a815210000000b002ef21e354ddmr6071061ywb.438.1650650298971; Fri, 22 Apr 2022 10:58:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650650298; cv=none; d=google.com; s=arc-20160816; b=BhpTcp/GupiHeDYaq63Qh3fK7s0c9gbQEesdYtK9raEBvj995rlaKlF8Ezc6YyOd+d 6CWcHxATJFtpI2B82iR8MuCME7e7g2mZrxigHpL85ASWZWFJ1gJcaqudtJHi6UvO7wwC HpDuCqpa/yIxkFu10euaLpUatXMhzlWWOkDdQN1we6l55hqHaYII7ebYmc8MVNPXzh0G dlf9qOT5uXGK8ouL5uHtZHVVcxITC8O4n9xce3V3s1dgiZTOGM/Lg70R+zrsPrUCLoTZ +fGXbEgzHlBIKopsKb92DqnVnrMtUKOcbO4DPD4SQV51Kr753ROkbLKxbQnFnmfFrXB+ z0dw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=I9okil5+kJgTqcKaRaU/YcxpruIY39QBJzH8pAf+TqE=; b=gE0h4I/7dxh+eb1ErFA/QQ+kxOuvjggWheoVJy6R0sVErIBM45eOfBPtWFpMR4NCfB 9NMzHlhZ8MZTKC2nCR0IOSTJQUpaUCjmCeRsYHnTTsEQCI18WwDGtvsjHklOXpXQMAW9 8cR0HuBrPzbcxo6gOcuaO8PiE10zxhMje8CN2rfXfPCQnjTA3Csy1tY24a51V1U5N+/R mU3fsVSvM1DuR0TGQN1T/VO9/SYpXv++EjcJ/BWUgo0Y6PgD8khJGWmj8ILu5jNtAVMp k39rEGwpWtYgJtKQbDqpmGtymnQMu1d96dyREDnAtbEa8v0UGz/aVdS/r3MBy7QbEssp hoUg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yl7adnp9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.57.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:57:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 66/68] hw/nios2: Machine with a Vectored Interrupt Controller Date: Fri, 22 Apr 2022 09:52:36 -0700 Message-Id: <20220422165238.1971496-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::130; envelope-from=richard.henderson@linaro.org; helo=mail-il1-x130.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Amir Gonnen , Mark Cave-Ayland Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Amir Gonnen Demonstrate how to use nios2 VIC on a machine. Introduce a new machine property to attach a VIC. When VIC is present, let the CPU know that it should use the External Interrupt Interface instead of the Internal Interrupt Interface. The devices on the machine are attached to the VIC and not directly to cpu. To allow VIC update EIC fields, we set the "cpu" property of the VIC with a reference to the nios2 cpu. [rth: Put a property on the 10m50-ghrd machine, rather than create a new machine class.] Reviewed-by: Mark Cave-Ayland Signed-off-by: Amir Gonnen Message-Id: <20220303153906.2024748-6-amir.gonnen@neuroblade.ai> Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-63-richard.henderson@linaro.org> --- hw/nios2/10m50_devboard.c | 61 +++++++++++++++++++++++++++++++++------ hw/nios2/Kconfig | 1 + 2 files changed, 53 insertions(+), 9 deletions(-) diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c index dda4ab2bf5..91383fb097 100644 --- a/hw/nios2/10m50_devboard.c +++ b/hw/nios2/10m50_devboard.c @@ -27,6 +27,7 @@ #include "hw/sysbus.h" #include "hw/char/serial.h" +#include "hw/intc/nios2_vic.h" #include "hw/qdev-properties.h" #include "sysemu/sysemu.h" #include "hw/boards.h" @@ -43,6 +44,8 @@ struct Nios2MachineState { MemoryRegion phys_tcm_alias; MemoryRegion phys_ram; MemoryRegion phys_ram_alias; + + bool vic; }; #define TYPE_NIOS2_MACHINE MACHINE_TYPE_NAME("10m50-ghrd") @@ -81,10 +84,39 @@ static void nios2_10m50_ghrd_init(MachineState *machine) memory_region_add_subregion(address_space_mem, 0xc0000000 + ram_base, &nms->phys_ram_alias); - /* Create CPU -- FIXME */ - cpu = NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU)); - for (i = 0; i < 32; i++) { - irq[i] = qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i); + /* Create CPU. We need to set eic_present between init and realize. */ + cpu = NIOS2_CPU(object_new(TYPE_NIOS2_CPU)); + + /* Enable the External Interrupt Controller within the CPU. */ + cpu->eic_present = nms->vic; + + /* Configure new exception vectors. */ + cpu->reset_addr = 0xd4000000; + cpu->exception_addr = 0xc8000120; + cpu->fast_tlb_miss_addr = 0xc0000100; + + qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal); + + if (nms->vic) { + DeviceState *dev = qdev_new(TYPE_NIOS2_VIC); + MemoryRegion *dev_mr; + qemu_irq cpu_irq; + + object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_fatal); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + cpu_irq = qdev_get_gpio_in_named(DEVICE(cpu), "EIC", 0); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq); + for (int i = 0; i < 32; i++) { + irq[i] = qdev_get_gpio_in(dev, i); + } + + dev_mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + memory_region_add_subregion(address_space_mem, 0x18002000, dev_mr); + } else { + for (i = 0; i < 32; i++) { + irq[i] = qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i); + } } /* Register: Altera 16550 UART */ @@ -105,15 +137,22 @@ static void nios2_10m50_ghrd_init(MachineState *machine) sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xe0000880); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[5]); - /* Configure new exception vectors and reset CPU for it to take effect. */ - cpu->reset_addr = 0xd4000000; - cpu->exception_addr = 0xc8000120; - cpu->fast_tlb_miss_addr = 0xc0000100; - nios2_load_kernel(cpu, ram_base, ram_size, machine->initrd_filename, BINARY_DEVICE_TREE_FILE, NULL); } +static bool get_vic(Object *obj, Error **errp) +{ + Nios2MachineState *nms = NIOS2_MACHINE(obj); + return nms->vic; +} + +static void set_vic(Object *obj, bool value, Error **errp) +{ + Nios2MachineState *nms = NIOS2_MACHINE(obj); + nms->vic = value; +} + static void nios2_10m50_ghrd_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -121,6 +160,10 @@ static void nios2_10m50_ghrd_class_init(ObjectClass *oc, void *data) mc->desc = "Altera 10M50 GHRD Nios II design"; mc->init = nios2_10m50_ghrd_init; mc->is_default = true; + + object_class_property_add_bool(oc, "vic", get_vic, set_vic); + object_class_property_set_description(oc, "vic", + "Set on/off to enable/disable the Vectored Interrupt Controller"); } static const TypeInfo nios2_10m50_ghrd_type_info = { diff --git a/hw/nios2/Kconfig b/hw/nios2/Kconfig index b10ea640da..4748ae27b6 100644 --- a/hw/nios2/Kconfig +++ b/hw/nios2/Kconfig @@ -3,6 +3,7 @@ config NIOS2_10M50 select NIOS2 select SERIAL select ALTERA_TIMER + select NIOS2_VIC config NIOS2_GENERIC_NOMMU bool From patchwork Fri Apr 22 16:52:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564893 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp700644map; Fri, 22 Apr 2022 10:51:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzMUMEBgkeQ7cvQ31PuxCCOoUwhbkH7ypBCQ21CthFsBFCPLK643zzrB9AW9Ll/CadgRwwI X-Received: by 2002:a25:b94a:0:b0:644:db14:ff10 with SMTP id s10-20020a25b94a000000b00644db14ff10mr5591274ybm.648.1650649908980; Fri, 22 Apr 2022 10:51:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650649908; cv=none; d=google.com; s=arc-20160816; b=HWHCb5Y3FMMGjtPk0kbHm+dayTHjCJJ5NB2+oDgg7E4xkI05O8/Mhr2ZkoaOitw7Vt BAq6uPpKYZDDTL3QXw5P/TcVRsQ9KlHsYKpGBSwLlRdel9qSmJGbH8rUmCClBwIeFh6J M/exhY9Z6sjhHVy94hmW945cS0GzsxQaAp4P6TXHoFgXnvkYg1yvrzqY0c8V1saMrxHQ F9EUjHTNzPfSo66EG0eCtTzTZyGUqtDMq+BziXsRV2/D9A/pgu7k1Heh9wppZRQWcn4z zvbCiqjRJRpkrNmWCedueVnDaqyFjaeD81w+1+xFJqouNUaTezmEh8VWuts6f6iPsxsR 5B8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=7xB33tWvW42qeEWj8nObMBV2LFMTDSEz/odcRi0ytnc=; b=oZQkCCexQ4zxf2HfMmNADpi/xwFdeq4c6m2qTBobpZiXRGKuUKXDHnd+9NrLFSxCEd n+Juw3lnX3dCvBng6FeOzYRz6n3oPy+bu3Npyt6JgJ8Y/1HpUvfuGRJow92Kow1qHAvh z/zAOKfPISPe8G3uqLbT15B2B51dqFXRL/i0n9DWYHNMkIjHdvQ3qpVkxJUPVkDfYS72 /NG6g2RlybjIga800SkSVPLrc6m0k71aUWCSoGiaoSzqb3BvufTDRbAc8Mz6h4p6mAog aBN6mBJzlXDo9DWZPGxYY7Oc6VmUUlBsPb48tx7lzWsfMmSidh79YLZeBOi7lCcfQzfd w3Mw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ev87aBEF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.57.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:57:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 67/68] tests/tcg/nios2: Add semihosting multiarch tests Date: Fri, 22 Apr 2022 09:52:37 -0700 Message-Id: <20220422165238.1971496-68-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::130; envelope-from=richard.henderson@linaro.org; helo=mail-il1-x130.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add runtime supporting the nios2-semi.c interface. Execute the hello and memory multiarch tests. Cc: Alex Bennée Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-64-richard.henderson@linaro.org> Reviewed-by: Peter Maydell --- tests/tcg/nios2/semicall.h | 28 +++ tests/tcg/nios2/10m50-ghrd.ld | 66 +++++++ tests/tcg/nios2/Makefile.softmmu-target | 32 ++++ tests/tcg/nios2/boot.S | 218 ++++++++++++++++++++++++ tests/tcg/nios2/intr.S | 31 ++++ 5 files changed, 375 insertions(+) create mode 100644 tests/tcg/nios2/semicall.h create mode 100644 tests/tcg/nios2/10m50-ghrd.ld create mode 100644 tests/tcg/nios2/Makefile.softmmu-target create mode 100644 tests/tcg/nios2/boot.S create mode 100644 tests/tcg/nios2/intr.S diff --git a/tests/tcg/nios2/semicall.h b/tests/tcg/nios2/semicall.h new file mode 100644 index 0000000000..6ad4978099 --- /dev/null +++ b/tests/tcg/nios2/semicall.h @@ -0,0 +1,28 @@ +/* + * Nios2 semihosting interface. + * + * Copyright Linaro Ltd 2022 + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef SEMICALL_H +#define SEMICALL_H + +#define HOSTED_EXIT 0 +#define HOSTED_INIT_SIM 1 +#define HOSTED_OPEN 2 +#define HOSTED_CLOSE 3 +#define HOSTED_READ 4 +#define HOSTED_WRITE 5 +#define HOSTED_LSEEK 6 +#define HOSTED_RENAME 7 +#define HOSTED_UNLINK 8 +#define HOSTED_STAT 9 +#define HOSTED_FSTAT 10 +#define HOSTED_GETTIMEOFDAY 11 +#define HOSTED_ISATTY 12 +#define HOSTED_SYSTEM 13 + +#define semihosting_call break 1 + +#endif /* SEMICALL_H */ diff --git a/tests/tcg/nios2/10m50-ghrd.ld b/tests/tcg/nios2/10m50-ghrd.ld new file mode 100644 index 0000000000..7db0d59ad7 --- /dev/null +++ b/tests/tcg/nios2/10m50-ghrd.ld @@ -0,0 +1,66 @@ +/* + * Link script for the Nios2 10m50-ghrd board. + * + * Copyright Linaro Ltd 2022 + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +MEMORY +{ + tpf (rx) : ORIGIN = 0xc0000000, LENGTH = 1K + ram (rwx) : ORIGIN = 0xc8000000, LENGTH = 128M +} + +PHDRS +{ + RAM PT_LOAD; +} + +ENTRY(_start) +EXTERN(_start) +EXTERN(_interrupt) +EXTERN(_fast_tlb_miss) + +SECTIONS +{ + /* Begin at the (hardcoded) _interrupt entry point. */ + .text 0xc8000120 : { + *(.text.intr) + *(.text .text.* .gnu.linkonce.t.*) + } >ram :RAM + + .rodata : ALIGN(4) { + *(.rodata .rodata.* .gnu.linkonce.r.*) + } > ram :RAM + + .eh_frame_hdr : ALIGN (4) { + KEEP (*(.eh_frame_hdr)) + *(.eh_frame_entry .eh_frame_entry.*) + } >ram :RAM + .eh_frame : ALIGN (4) { + KEEP (*(.eh_frame)) *(.eh_frame.*) + } >ram :RAM + + .data : ALIGN(4) { + *(.shdata) + *(.data .data.* .gnu.linkonce.d.*) + . = ALIGN(4); + _gp = ABSOLUTE(. + 0x8000); + *(.got.plt) *(.got) + *(.lit8) + *(.lit4) + *(.sdata .sdata.* .gnu.linkonce.s.*) + } >ram :RAM + + .bss : ALIGN(4) { + __bss_start = ABSOLUTE(.); + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + __bss_end = ABSOLUTE(.); + } >ram :RAM + + __stack = ORIGIN(ram) + LENGTH(ram); +} diff --git a/tests/tcg/nios2/Makefile.softmmu-target b/tests/tcg/nios2/Makefile.softmmu-target new file mode 100644 index 0000000000..cea27472a6 --- /dev/null +++ b/tests/tcg/nios2/Makefile.softmmu-target @@ -0,0 +1,32 @@ +# +# Nios2 system tests +# +# Copyright Linaro Ltd 2022 +# SPDX-License-Identifier: GPL-2.0-or-later +# + +NIOS2_SYSTEM_SRC = $(SRC_PATH)/tests/tcg/nios2 +VPATH += $(NIOS2_SYSTEM_SRC) + +# These objects provide the basic boot code and helper functions for all tests +CRT_OBJS = boot.o intr.o $(MINILIB_OBJS) +LINK_SCRIPT = $(NIOS2_SYSTEM_SRC)/10m50-ghrd.ld + +CFLAGS += -nostdlib -g -O0 $(MINILIB_INC) +LDFLAGS += -Wl,-T$(LINK_SCRIPT) -static -nostdlib $(CRT_OBJS) -lgcc + +%.o: %.S + $(call quiet-command, $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -x assembler-with-cpp -c $< -o $@, AS, $@) + +%.o: %.c + $(call quiet-command, $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@, CC, $@) + +# Build and link the tests +%: %.o $(LINK_SCRIPT) $(CRT_OBJS) + $(call quiet-command, $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS), LD, $@) + +# FIXME: nios2 semihosting writes to stdout, not a chardev +QEMU_OPTS = -M 10m50-ghrd,vic=on -semihosting >$@.out -kernel + +memory: CFLAGS+=-DCHECK_UNALIGNED=0 +TESTS += $(MULTIARCH_TESTS) diff --git a/tests/tcg/nios2/boot.S b/tests/tcg/nios2/boot.S new file mode 100644 index 0000000000..f6771cbc81 --- /dev/null +++ b/tests/tcg/nios2/boot.S @@ -0,0 +1,218 @@ +/* + * Minimal Nios2 system boot code. + * + * Copyright Linaro Ltd 2022 + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "semicall.h" + + .text + .set noat + +_start: + /* Linker script defines stack at end of ram. */ + movia sp, __stack + + /* Install trampoline to _fast_tlb_miss at hardcoded vector. */ + movia r4, 0xc0000100 + movia r5, _ftm_tramp + movi r6, .L__ftm_end - _ftm_tramp + call memcpy + + /* Zero the bss to satisfy C. */ + movia r4, __bss_start + movia r6, __bss_end + sub r6, r6, r4 + movi r5, 0 + call memset + + /* Test! */ + call main + + /* Exit with main's return value. */ + movi r4, HOSTED_EXIT + mov r5, r2 + semihosting_call + + .globl _start + .type _start, @function + .size _start, . - _start + +_ftm_tramp: + movia et, _fast_tlb_miss + jmp et +.L__ftm_end: + + .type _ftm_tramp, @function + .size _ftm_tramp, . - _ftm_tramp + +#define dst r4 +#define src r5 +#define len r6 + +memcpy: + /* Store return value right away, per API */ + mov r2, dst + + /* Check for both dst and src aligned. */ + or at, dst, src + andi at, at, 3 + bne at, zero, .L_mc_test1 + + /* Copy blocks of 8. */ + + movi at, 8 + bltu len, at, .L_mc_test4 + +.L_mc_loop8: + ldw r8, 0(src) + ldw r9, 4(src) + addi src, src, 8 + addi dst, dst, 8 + subi len, len, 8 + stw r8, -8(dst) + stw r9, -4(dst) + bgeu len, at, .L_mc_loop8 + + /* Copy final aligned block of 4. */ + +.L_mc_test4: + movi at, 4 + bltu len, at, .L_mc_test1 + + ldw r8, 0(src) + addi src, src, 4 + addi dst, dst, 4 + subi len, len, 4 + stw r8, -4(dst) + + /* Copy single bytes to finish. */ + +.L_mc_test1: + beq len, zero, .L_mc_done + +.L_mc_loop1: + ldb r8, 0(src) + addi src, src, 1 + addi dst, dst, 1 + subi len, len, 1 + stb r8, -1(dst) + bne len, zero, .L_mc_loop1 + +.L_mc_done: + ret + +#undef dst +#undef src +#undef len + + .global memcpy + .type memcpy, @function + .size memcpy, . - memcpy + +#define dst r4 +#define val r5 +#define len r6 + +memset: + /* Store return value right away, per API */ + mov r2, dst + + /* Check for small blocks; fall back to bytewise. */ + movi r3, 8 + bltu len, r3, .L_ms_test1 + + /* Replicate the byte across the word. */ + andi val, val, 0xff + slli at, val, 8 + or val, val, at + slli at, val, 16 + or val, val, at + + /* Check for destination alignment; realign if needed. */ + andi at, dst, 3 + bne at, zero, .L_ms_align + + /* Set blocks of 8. */ + +.L_ms_loop8: + stw val, 0(dst) + stw val, 4(dst) + addi dst, dst, 8 + subi len, len, 8 + bgeu len, r3, .L_ms_loop8 + + /* Set final aligned block of 4. */ + +.L_ms_test4: + movi at, 4 + bltu len, at, .L_ms_test1 + + stw r8, 0(dst) + addi dst, dst, 4 + subi len, len, 4 + stw r8, -4(dst) + + /* Set single bytes to finish. */ + +.L_ms_test1: + beq len, zero, .L_ms_done + +.L_ms_loop1: + stb r8, 0(dst) + addi dst, dst, 1 + subi len, len, 1 + bne len, zero, .L_ms_loop1 + +.L_ms_done: + ret + + /* Realign for a large block, len >= 8. */ +.L_ms_align: + andi at, dst, 1 + beq at, zero, 2f + + stb val, 0(dst) + addi dst, dst, 1 + subi len, len, 1 + +2: andi at, dst, 2 + beq at, zero, 4f + + sth val, 0(dst) + addi dst, dst, 2 + subi len, len, 2 + +4: bgeu len, r3, .L_ms_loop8 + br .L_ms_test4 + +#undef dst +#undef val +#undef len + + .global memset + .type memset, @function + .size memset, . - memset + +/* + * void __sys_outc(char c); + */ +__sys_outc: + subi sp, sp, 16 + stb r4, 0(sp) /* buffer[0] = c */ + movi at, 1 + stw at, 4(sp) /* STDOUT_FILENO */ + stw sp, 8(sp) /* buffer */ + stw at, 12(sp) /* len */ + + movi r4, HOSTED_WRITE + addi r5, sp, 4 + semihosting_call + + addi sp, sp, 16 + ret + + .global __sys_outc + .type __sys_outc, @function + .size __sys_outc, . - __sys_outc diff --git a/tests/tcg/nios2/intr.S b/tests/tcg/nios2/intr.S new file mode 100644 index 0000000000..c1730692ba --- /dev/null +++ b/tests/tcg/nios2/intr.S @@ -0,0 +1,31 @@ +/* + * Minimal Nios2 system boot code -- exit on interrupt. + * + * Copyright Linaro Ltd 2022 + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "semicall.h" + + .section .text.intr, "ax" + .global _interrupt + .type _interrupt, @function + +_interrupt: + rdctl r5, exception /* extract exception.CAUSE */ + srli r5, r5, 2 + movi r4, HOSTED_EXIT + semihosting_call + + .size _interrupt, . - _interrupt + + .text + .global _fast_tlb_miss + .type _fast_tlb_miss, @function + +_fast_tlb_miss: + movi r5, 32 + movi r4, HOSTED_EXIT + semihosting_call + + .size _fast_tlb_miss, . - _fast_tlb_miss From patchwork Fri Apr 22 16:52:38 2022 Content-Type: text/plain; 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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id n23-20020a6b8b17000000b00649a2634725sm816380iod.17.2022.04.22.09.57.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:57:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 68/68] tests/tcg/nios2: Add test-shadow-1 Date: Fri, 22 Apr 2022 09:52:38 -0700 Message-Id: <20220422165238.1971496-69-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d29; envelope-from=richard.henderson@linaro.org; helo=mail-io1-xd29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add a regression test for tcg indirect global lowering. This appeared with nios2, with cps != 0, so that we use indirection into the shadow register set. An indirect call verifies alignment of rA. The use of rA was live across the brcond leading to a tcg_debug_assert failure. Cc: Alex Bennée Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20220421151735.31996-65-richard.henderson@linaro.org> --- tests/tcg/nios2/Makefile.softmmu-target | 1 + tests/tcg/nios2/test-shadow-1.S | 40 +++++++++++++++++++++++++ 2 files changed, 41 insertions(+) create mode 100644 tests/tcg/nios2/test-shadow-1.S diff --git a/tests/tcg/nios2/Makefile.softmmu-target b/tests/tcg/nios2/Makefile.softmmu-target index cea27472a6..c3d0594a39 100644 --- a/tests/tcg/nios2/Makefile.softmmu-target +++ b/tests/tcg/nios2/Makefile.softmmu-target @@ -30,3 +30,4 @@ QEMU_OPTS = -M 10m50-ghrd,vic=on -semihosting >$@.out -kernel memory: CFLAGS+=-DCHECK_UNALIGNED=0 TESTS += $(MULTIARCH_TESTS) +TESTS += test-shadow-1 diff --git a/tests/tcg/nios2/test-shadow-1.S b/tests/tcg/nios2/test-shadow-1.S new file mode 100644 index 0000000000..79ef69db12 --- /dev/null +++ b/tests/tcg/nios2/test-shadow-1.S @@ -0,0 +1,40 @@ +/* + * Regression test for TCG indirect global lowering. + * + * Copyright Linaro Ltd 2022 + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "semicall.h" + + .text + .set noat + .align 2 + .globl main + .type main, @function + +main: + /* Initialize r0 in shadow register set 1. */ + movhi at, 1 /* PRS=1, CRS=0, RSIE=0, PIE=0 */ + wrctl status, at + wrprs zero, zero + + /* Change current register set to 1. */ + movi at, 1 << 10 /* PRS=0, CRS=1, RSIE=0, PIE=0 */ + wrctl estatus, at + movia ea, 1f + eret + + /* Load address for callr, then end TB. */ +1: movia at, 3f + br 2f + + /* Test case! TCG abort on indirect lowering across brcond. */ +2: callr at + + /* exit(0) */ +3: movi r4, HOSTED_EXIT + movi r5, 0 + semihosting_call + + .size main, . - main