From patchwork Tue Dec 18 21:28:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 154178 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4202770ljp; Tue, 18 Dec 2018 13:29:14 -0800 (PST) X-Google-Smtp-Source: AFSGD/UvfWU1so9HgcLA/7lbLF5GNQumrjOlNNbRkcz017efNNbuApg4fZg+DoPW9dVaUsQ1iSQv X-Received: by 2002:a63:9b11:: with SMTP id r17mr17365185pgd.416.1545168554314; Tue, 18 Dec 2018 13:29:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545168554; cv=none; d=google.com; s=arc-20160816; b=CyX9j2MIk8W++gUXLi1G6EmalpbMhN1onVsUZZ45MHSFCxFqRrGdCSVp0hnGDKTjbZ 6I0Z9yXuqkZiotOLVmbgWqruVHRneLbHbHb446BMviefFA1+kemNl1y0etIK+j+nKv4g CVoUeOiGDenAcanQNwRDgmGrNNDkne2pbv06wy4gcWcJk56GUfukqEocsIQKBwfZsnjZ jssmsFNZATElTqEcNyPlnJoZje2zL/NseXkTsrtTo1XlAtw6av375vzxL7u6USItk7M1 IxJs1nuPtyJj2/3ivKneHvEqBtOKGrJoAaIN83bROfqXfryuW/LDiFaZlUi+9ITnkMwU uXKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=ilQ0qqZNQydQTJlGafIg3unftBFJ87HWUKycWJC64gY=; b=Ns1aoFpI9hexvw0bOTXnVN53TrGvcciSyREvpqUEOMN23ZRzFnINk2o2Oq2hSAidIM 47R22yB7J5vjpCzaHaZU4oWhjXvFlAnY4JBBRgyR5iEDi//L/DgMZzIQQxeUMuzGWhXR BNAg/b4u4gvLLCoz8PxL3noGd8yGZuRlVJY9ZjFofrBWRkzuu7iDErn6wRe88ttsk2Pq ISEiXGjzf1hfXe4rmVVG67ZBQR2XNljxKKNq2IYPRALy4OjToOOfB8jlpDUldyfcH/ij ukKGvpE0uwy5sF7RIUewamOLfOj5j2M1o0rbdQNW0AoLwFuV3BGKnQTkS6xpXa/QhNfE Rc9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kBLJFBXy; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.92.50.105]) by smtp.gmail.com with ESMTPSA id o4sm4153485wrq.66.2018.12.18.13.29.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Dec 2018 13:29:09 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dan Carpenter , Tony Prisk , linux-arm-kernel@lists.infradead.org (moderated list:ARM/VT8500 ARM ARCHITECTURE) Subject: [PATCH 01/25] clocksource/drivers/timer-vt8500: Remove duplicate function name Date: Tue, 18 Dec 2018 22:28:19 +0100 Message-Id: <20181218212844.30445-1-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dan Carpenter We print the function name twice in a row in the error message so I've removed one. Signed-off-by: Dan Carpenter Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-vt8500.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/clocksource/timer-vt8500.c b/drivers/clocksource/timer-vt8500.c index e0f7489cfc8e..c3aff1a8f7d5 100644 --- a/drivers/clocksource/timer-vt8500.c +++ b/drivers/clocksource/timer-vt8500.c @@ -145,7 +145,7 @@ static int __init vt8500_timer_init(struct device_node *np) ret = clocksource_register_hz(&clocksource, VT8500_TIMER_HZ); if (ret) { - pr_err("%s: vt8500_timer_init: clocksource_register failed for %s\n", + pr_err("%s: clocksource_register failed for %s\n", __func__, clocksource.name); return ret; } From patchwork Tue Dec 18 21:28:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 154179 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4202794ljp; Tue, 18 Dec 2018 13:29:17 -0800 (PST) X-Google-Smtp-Source: AFSGD/Ub0WxZ2355ZV/ud36mgwjiH9Z7cCqY7l7u9IsmwT6fJEhgLgpSLfCrjYHpOIAEZJTkoyq/ X-Received: by 2002:a17:902:76cb:: with SMTP id j11mr18395355plt.179.1545168557083; Tue, 18 Dec 2018 13:29:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545168557; cv=none; d=google.com; s=arc-20160816; b=aQFVvxVdgrKCbxl4qUXvtSSNJuMS/yf3Zu8PRI5Uvng9gH7G+u+KJaENR0smgXlHaF ZJJEV2kA8dNkUPASoZzr9D0uVzTTWYR96oBwanE09wcE+oCMBAHAOuRlrolqGZAiIKa3 KPUmIEWH23jbpdxoKt+Xs/70OCuSVjbvW7lwbFTQcXnb+mRLvNoJrB+Wh5Ow/NwmACu/ EXeVkuPQ46uPka1kd/T3P5NUpawjEvnxulD/WOYZ0K43t2BjAkEkWu3cpkjAt4OFvmiP bg6B05aLnDqPTX7k5xK8GDc1N21qWTUlbuapy9NCntBg1vWBIIlzlheP0cXfqRrDqvSy alPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=Nqyu5M43GadzwCnPRoa+RxuMcREhWjlFWdJLqMc9jGQ=; b=AL4CqsoqSjxGLOluREXoPPBIdrfC6niDc9EQ4P4MbNHWQipoTL1RapVRrwbl8hQWju 7I6rUAW12Xzn5XiQasmRDgRwbAEBd5cbSftpmEIS87+CWkYa2uQx068S0DWedapAGzKV vu2eAZOMjQbmg3tLUpdmKFzpCiZ1uMK8LPijZTac7c8exeD+HvW7gLMfW+lRYAjzIpv1 oif5r8dE31Ssl55GbKcGwYgvoLCM+njFC5zFpdi7dulIyTUN3JrO+jr38+XiUC7DEE77 xMDdmxrUFUQhP1947Wt1wHO425r88PF6GBWUqFoY+nGFQUGqd0AMwHI5SnElhA9KyOji qgKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=j2atdPES; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.92.50.105]) by smtp.gmail.com with ESMTPSA id o4sm4153485wrq.66.2018.12.18.13.29.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Dec 2018 13:29:11 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Linus Walleij , Baolin Wang , linux-arm-kernel@lists.infradead.org (moderated list:ARM/NOMADIK/U300/Ux500 ARCHITECTURES) Subject: [PATCH 02/25] clocksource/drivers/dbx500: Demote dbx500 PRCMU clocksource Date: Tue, 18 Dec 2018 22:28:20 +0100 Message-Id: <20181218212844.30445-2-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181218212844.30445-1-daniel.lezcano@linaro.org> References: <20181218212844.30445-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Linus Walleij Demote the DBx500 PRCMU clocksource to quality 100 and mark it as NONSTOP so it will still be used for timekeeping across suspend/resume. The Nomadik MTU timer which has higher precision will be used when the system is up and running, thanks to the recent changes properly utilizing the suspend clocksources. This was discussed back in 2011 when the driver was written, but the infrastructure was not available upstream to use this timer properly. Now the infrastructure is there, so let's finalize the work. Cc: Baolin Wang Signed-off-by: Linus Walleij Reviewed-by: Baolin Wang Signed-off-by: Daniel Lezcano --- drivers/clocksource/clksrc-dbx500-prcmu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/clksrc-dbx500-prcmu.c b/drivers/clocksource/clksrc-dbx500-prcmu.c index c1b96dc5f444..4054539fe066 100644 --- a/drivers/clocksource/clksrc-dbx500-prcmu.c +++ b/drivers/clocksource/clksrc-dbx500-prcmu.c @@ -46,10 +46,10 @@ static u64 notrace clksrc_dbx500_prcmu_read(struct clocksource *cs) static struct clocksource clocksource_dbx500_prcmu = { .name = "dbx500-prcmu-timer", - .rating = 300, + .rating = 100, .read = clksrc_dbx500_prcmu_read, .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, + .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP, }; #ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK From patchwork Tue Dec 18 21:28:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 154180 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4202838ljp; Tue, 18 Dec 2018 13:29:20 -0800 (PST) X-Google-Smtp-Source: AFSGD/V+s89Yux/ezAyvUfT6i/5jx5BlNkRuMaiS4C6YhY9+jsvVA/QcBVoGLENR3mVGDh62Nsy0 X-Received: by 2002:a17:902:6b09:: with SMTP id o9mr17886044plk.208.1545168560389; Tue, 18 Dec 2018 13:29:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545168560; cv=none; d=google.com; s=arc-20160816; b=M1d2po8ht76FvkmbpJFaABVGSuZNTPoLnb3CO26tm3p04FFNLYts+sLHhQvwxWldt8 MhHv/eTjHeZV2ER/2iyjQmsUvCxg4Q/wvDP5mGCF4/9tpPM2OK4uc+EY0xPPey2YN6O1 T3q0dm09HyFYUqSr0vtR687OZgi38vwZuWU6Hup58TF2K/xx11Z8MEcG+WTF6Nlg+Vju PjQL/qpMASshs6vSJjkYrbjIzCbByXiYVyQEdsViZZizIS/PRgiHgZwAQqhKry83aiNx 5GN6zqayeTA+mP0glcLeASENti9ACyU8S3KUQnaQ5Z3U6AL8jKdKRCC27qBmeSo2gl4+ 5yTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=QXQVukJ1aLtElpReoZ9tNrJAaaXhnuBSyD1Rl2WDJl4=; b=jIu0Tz4sSf2vGmK1Zx4UEjkbAU3ImI27pSLdb9oXtIidy8T6hmxAVTWyUxQooqTsXk 7jLIsiZUV531dcY9MyAKLPgpaBAamfGioEcV/ZivLwBb6vvGpLeH58PcOU2CJPWkZTb2 RR6aeqjCK0HPk2rVOY90ghlBNRUH3kun/VYIRNufdSQvk9CnkRvvZp+m0JJJRjzPTe5z UGI+rj82yXvbsL9MzEmT6drsurbB3cW3Kh1D5EO2plAfOPrBaZYAvLtBKdKTz10CsLUv sFpZLKOxVpkEVFETDOxku7JCTd2VZL1yAc9rEBAIAYRSBOuaoIBeEw7+nPIqwhALyurE Le8g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="k2jKzaF/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.92.50.105]) by smtp.gmail.com with ESMTPSA id o4sm4153485wrq.66.2018.12.18.13.29.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Dec 2018 13:29:13 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Linus Walleij , Baolin Wang , linux-arm-kernel@lists.infradead.org (moderated list:ARM/NOMADIK/U300/Ux500 ARCHITECTURES) Subject: [PATCH 03/25] clocksource/drivers/ux500: Drop Ux500 custom SCHED_CLOCK Date: Tue, 18 Dec 2018 22:28:21 +0100 Message-Id: <20181218212844.30445-3-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181218212844.30445-1-daniel.lezcano@linaro.org> References: <20181218212844.30445-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Linus Walleij The two drivers used for Ux500 sched_clock use two Kconfig symbols to select which of the two gets used as sched_clock. This isn't right: the workaround is trying to make sure that the NONSTOP timer is used for sched_clock in order to keep that clock ticking consistently over a suspend/resume cycle. (Otherwise sched_clock simply stops during suspend and continues after resume). This will notably affect any timetstamped debug prints, so that they show the absolute number of seconds since the system was booted and does not loose wall-clock time during suspend and resume as if time stood still. The real way to fix this problem is to make sched_clock take advantage of any NONSTOP clock source on the system and adjust accordingly, not to try to work around this by using a different sched_clock depending on what system we are compiling for. This can solve the problem for everyone instead of providing a local solution. Cc: Baolin Wang Signed-off-by: Linus Walleij Signed-off-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 13 ------------- drivers/clocksource/clksrc-dbx500-prcmu.c | 18 ------------------ drivers/clocksource/nomadik-mtu.c | 4 ---- 3 files changed, 35 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 55c77e44bb2d..64d5759ddf0e 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -163,12 +163,6 @@ config CLKSRC_NOMADIK_MTU to multiple interrupt generating programmable 32-bit free running decrementing counters. -config CLKSRC_NOMADIK_MTU_SCHED_CLOCK - bool - depends on CLKSRC_NOMADIK_MTU - help - Use the Multi Timer Unit as the sched_clock. - config CLKSRC_DBX500_PRCMU bool "Clocksource PRCMU Timer" if COMPILE_TEST depends on HAS_IOMEM @@ -226,13 +220,6 @@ config INTEGRATOR_AP_TIMER help Enables support for the Integrator-ap timer. -config CLKSRC_DBX500_PRCMU_SCHED_CLOCK - bool "Clocksource PRCMU Timer sched_clock" - depends on (CLKSRC_DBX500_PRCMU && !CLKSRC_NOMADIK_MTU_SCHED_CLOCK) - default y - help - Use the always on PRCMU Timer as sched_clock - config CLKSRC_EFM32 bool "Clocksource for Energy Micro's EFM32 SoCs" if !ARCH_EFM32 depends on OF && ARM && (ARCH_EFM32 || COMPILE_TEST) diff --git a/drivers/clocksource/clksrc-dbx500-prcmu.c b/drivers/clocksource/clksrc-dbx500-prcmu.c index 4054539fe066..51d53c4e646f 100644 --- a/drivers/clocksource/clksrc-dbx500-prcmu.c +++ b/drivers/clocksource/clksrc-dbx500-prcmu.c @@ -15,7 +15,6 @@ #include #include #include -#include #define RATE_32K 32768 @@ -26,8 +25,6 @@ #define PRCMU_TIMER_DOWNCOUNT 0x4 #define PRCMU_TIMER_MODE 0x8 -#define SCHED_CLOCK_MIN_WRAP 131072 /* 2^32 / 32768 */ - static void __iomem *clksrc_dbx500_timer_base; static u64 notrace clksrc_dbx500_prcmu_read(struct clocksource *cs) @@ -52,18 +49,6 @@ static struct clocksource clocksource_dbx500_prcmu = { .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP, }; -#ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK - -static u64 notrace dbx500_prcmu_sched_clock_read(void) -{ - if (unlikely(!clksrc_dbx500_timer_base)) - return 0; - - return clksrc_dbx500_prcmu_read(&clocksource_dbx500_prcmu); -} - -#endif - static int __init clksrc_dbx500_prcmu_init(struct device_node *node) { clksrc_dbx500_timer_base = of_iomap(node, 0); @@ -81,9 +66,6 @@ static int __init clksrc_dbx500_prcmu_init(struct device_node *node) writel(TIMER_DOWNCOUNT_VAL, clksrc_dbx500_timer_base + PRCMU_TIMER_REF); } -#ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK - sched_clock_register(dbx500_prcmu_sched_clock_read, 32, RATE_32K); -#endif return clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K); } TIMER_OF_DECLARE(dbx500_prcmu, "stericsson,db8500-prcmu-timer-4", diff --git a/drivers/clocksource/nomadik-mtu.c b/drivers/clocksource/nomadik-mtu.c index 8e4ddb9420c6..19b336c9b417 100644 --- a/drivers/clocksource/nomadik-mtu.c +++ b/drivers/clocksource/nomadik-mtu.c @@ -69,7 +69,6 @@ static u32 clk_prescale; static u32 nmdk_cycle; /* write-once */ static struct delay_timer mtu_delay_timer; -#ifdef CONFIG_CLKSRC_NOMADIK_MTU_SCHED_CLOCK /* * Override the global weak sched_clock symbol with this * local implementation which uses the clocksource to get some @@ -82,7 +81,6 @@ static u64 notrace nomadik_read_sched_clock(void) return -readl(mtu_base + MTU_VAL(0)); } -#endif static unsigned long nmdk_timer_read_current_timer(void) { @@ -234,9 +232,7 @@ static int __init nmdk_timer_init(void __iomem *base, int irq, return ret; } -#ifdef CONFIG_CLKSRC_NOMADIK_MTU_SCHED_CLOCK sched_clock_register(nomadik_read_sched_clock, 32, rate); -#endif /* Timer 1 is used for events, register irq and clockevents */ setup_irq(irq, &nmdk_timer_irq); From patchwork Tue Dec 18 21:28:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 154202 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4204523ljp; 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[92.92.50.105]) by smtp.gmail.com with ESMTPSA id o4sm4153485wrq.66.2018.12.18.13.29.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Dec 2018 13:29:14 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH 04/25] clocksource/drivers/timer-ti-dm: Remove the early platform driver registration Date: Tue, 18 Dec 2018 22:28:22 +0100 Message-Id: <20181218212844.30445-4-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181218212844.30445-1-daniel.lezcano@linaro.org> References: <20181218212844.30445-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Bartosz Golaszewski This driver is no longer used as an early platform driver. Remove the registration macro. Signed-off-by: Bartosz Golaszewski Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-ti-dm.c | 1 - 1 file changed, 1 deletion(-) -- 2.17.1 diff --git a/drivers/clocksource/timer-ti-dm.c b/drivers/clocksource/timer-ti-dm.c index 4cce6b224b87..595124074821 100644 --- a/drivers/clocksource/timer-ti-dm.c +++ b/drivers/clocksource/timer-ti-dm.c @@ -991,7 +991,6 @@ static struct platform_driver omap_dm_timer_driver = { }, }; -early_platform_init("earlytimer", &omap_dm_timer_driver); module_platform_driver(omap_dm_timer_driver); MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver"); From patchwork Tue Dec 18 21:28:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 154181 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4202879ljp; Tue, 18 Dec 2018 13:29:23 -0800 (PST) X-Google-Smtp-Source: AFSGD/X0s90iwkM9Mn3G0PRfPVJN6JZNMTkm4oajVQq/+3Zz3kd85CpQ1t7kK4a1o/6Dw8bXn8+O X-Received: by 2002:a17:902:ba89:: with SMTP id k9mr18161647pls.189.1545168562926; Tue, 18 Dec 2018 13:29:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545168562; cv=none; d=google.com; s=arc-20160816; b=LIhGl1jZHITZWbngrEfPIMstVB4dfoyOU8nVRutEBHkB20sAiFJCpx4z558yS8sRTp Jq1bSK7euJlUBZTYzHrnfBSS8pAwy+EJMMy9KInuA+aH4dywvVjJlJ/NFmvinNBRA8gJ eHta2uXbDFbSuThTMwXR2dhtfeL1a3mogl4cmDMjg9VBgD571yMJVBPYK5Tx+d6DwQv7 dajWgxejOKuz6kwdcfPk0+oolXu23fblC5xSWwlVC+EpHaWFi+UdgmcUSYoSC6zwAD1P uLexokK73iCVdCB4u+Ac1wBJRjIk9qMPGCiNCtZykv4p7tNS5K9JYiMPPOs0c0kgmGQ/ Mfuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=Rr8ilS5R2vpccRIsS+2N6f0DuRbVwp+GBmj6taBD1mY=; b=BSmEcrqGheds69wSEzDpCX1L+X6AYCe8VvlwdZhpRtLbLe4q5zFsJc5gOaZeJRzt+m 3Q1ACfs08+K811NUYKTM6P/DdJOeEsXCOQ1D4qqYap/NtUKrjbgZVx6lzSANME33QBk3 yJa7xHIGhR7Iv1TtI0HXXZcbKrzZrRM+FUuutWSuB7DAI49/DtExHzVTZzhO1MfezULG 4vENjALcJ7/TA/w3C5XJSCpHn6vm5PyhIUjeMhaqMho9BCU3Po74orC//lmw9RJ84Tdy B2EZfz/E5sgUOy/+mLP3BeRj0APquxEXcOMwvibfu90EmtIfiFqfRbvr3VGcLpm3V/FU pzig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O5rY8VCF; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.92.50.105]) by smtp.gmail.com with ESMTPSA id o4sm4153485wrq.66.2018.12.18.13.29.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Dec 2018 13:29:16 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Geert Uytterhoeven , Thierry Reding , Thierry Reding , Jonathan Hunter , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 05/25] clockevents/drivers/tegra20: Remove obsolete inclusion of Date: Tue, 18 Dec 2018 22:28:23 +0100 Message-Id: <20181218212844.30445-5-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181218212844.30445-1-daniel.lezcano@linaro.org> References: <20181218212844.30445-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Geert Uytterhoeven As of commit da4a686a2cfb077a ("ARM: smp_twd: convert to use CLKSRC_OF init"), this header file is no longer used. Signed-off-by: Geert Uytterhoeven Acked-by: Thierry Reding Signed-off-by: Daniel Lezcano --- drivers/clocksource/tegra20_timer.c | 1 - 1 file changed, 1 deletion(-) -- 2.17.1 diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c index aa624885e0e2..4293943f4e2b 100644 --- a/drivers/clocksource/tegra20_timer.c +++ b/drivers/clocksource/tegra20_timer.c @@ -30,7 +30,6 @@ #include #include -#include #define RTC_SECONDS 0x08 #define RTC_SHADOW_SECONDS 0x0c From patchwork Tue Dec 18 21:28:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 154201 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4204395ljp; Tue, 18 Dec 2018 13:31:08 -0800 (PST) X-Google-Smtp-Source: AFSGD/Xz7vLSJm75c6v9jM185sS2UtKKS3RCjAxIOBX5ZszIwjTNO1XV+0JyjSKZNLFstRI6d2Xn X-Received: by 2002:a63:b24a:: with SMTP id t10mr15903617pgo.223.1545168668037; Tue, 18 Dec 2018 13:31:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545168668; cv=none; d=google.com; s=arc-20160816; b=OuvKFgH5ulsK6ld9oFGM9lyZHgPLGQIuhvePfI4lyOZZAmzowsAyz0r8rwJ4r6xlQ8 WsX4j+10KlKv7REBkO0k9RSLBQrGaJVYg7O74xeYTMECNqZKU3y5LLIng27YQeQq6yB6 RiSxjMAAl7tBiFO2pNWyerD/V/sUPVXdGF/r8MrcfZdIXV6ntZgQJD4+x+Sgaow3n8Uk Y1H/+S5f8jKSSd+zBKsL1FN7a3D+kMDbzaQNkwK/0Leg78F6/5764/tGjHt5ik6RCv4Q H8AzenzoeT7MBTWAu47hQ2ftd6LhLyXZ946JoVc/RlreDHsJQYeanvjXFPklGzXlwz45 rrvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=AThSIIFr1MNxei6GzfPPmaTqIlS3Gkxg7bofXJUPBLQ=; b=bs7TeR7XWtPQwLpyIu8NRmfDjG/rgTElp/SNRFLXOFEMTLIJi+LRwSi06z4TpfeEKM eah3oy9lTJFTD9iG7xCB5Q23mELybDrCHZ3uz/fqUtGrxyhBJLSIcZZ3Tm4OHrunyG/f Sb0AA57Ka4UFRovqWrddOiZM6ukGNF+DKMAnmEWwxXxxZWlMs0HkKgq5xfcVGTbRenhi gRlHncjDk0Chsyg6/XwE1NOYnAQOFW+DAHczEc43npsCFeQJdGxTOHUB3J5ifsYn0KPp HyuBX9SLj6M1C1gzxwqb3YxCt2ChzcHSsqvZfKhPN1zkZW7hg63AbXkhALLI/7aQue6P WLwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Xuuc6c3A; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.92.50.105]) by smtp.gmail.com with ESMTPSA id o4sm4153485wrq.66.2018.12.18.13.29.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Dec 2018 13:29:17 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Martin Blumenstingl , Carlo Caione , Kevin Hilman , linux-arm-kernel@lists.infradead.org (moderated list:ARM/Amlogic Meson SoC support), linux-amlogic@lists.infradead.org (open list:ARM/Amlogic Meson SoC support) Subject: [PATCH 06/25] clocksource/drivers/meson6_timer: Use register names from the datasheet Date: Tue, 18 Dec 2018 22:28:24 +0100 Message-Id: <20181218212844.30445-6-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181218212844.30445-1-daniel.lezcano@linaro.org> References: <20181218212844.30445-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Martin Blumenstingl This makes the driver use the names from S805 datasheet for the preprocessor #defines. This makes it easier to spot that the driver currently only supports Timer A (as clockevent with interrupt support) and Timer E (as clocksource without interrupts). Timer B, C and D (which are similar to Timer A) are currently not supported by the driver. While here, this also removes the internal "CED_ID" and "CSD_ID" defines which are used to identify the timer. These IDs are not described in the datasheet and thus make it harder to compare the code to what's written in the datasheet. Signed-off-by: Martin Blumenstingl Signed-off-by: Daniel Lezcano --- drivers/clocksource/meson6_timer.c | 108 +++++++++++++++++------------ 1 file changed, 64 insertions(+), 44 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/meson6_timer.c b/drivers/clocksource/meson6_timer.c index 92f20991a937..23c7638e2bb3 100644 --- a/drivers/clocksource/meson6_timer.c +++ b/drivers/clocksource/meson6_timer.c @@ -10,6 +10,8 @@ * warranty of any kind, whether express or implied. */ +#include +#include #include #include #include @@ -20,80 +22,96 @@ #include #include -#define CED_ID 0 -#define CSD_ID 4 - -#define TIMER_ISA_MUX 0 -#define TIMER_ISA_VAL(t) (((t) + 1) << 2) - -#define TIMER_INPUT_BIT(t) (2 * (t)) -#define TIMER_ENABLE_BIT(t) (16 + (t)) -#define TIMER_PERIODIC_BIT(t) (12 + (t)) - -#define TIMER_CED_INPUT_MASK (3UL << TIMER_INPUT_BIT(CED_ID)) -#define TIMER_CSD_INPUT_MASK (7UL << TIMER_INPUT_BIT(CSD_ID)) - -#define TIMER_CED_UNIT_1US 0 -#define TIMER_CSD_UNIT_1US 1 +#define MESON_ISA_TIMER_MUX 0x00 +#define MESON_ISA_TIMER_MUX_TIMERD_EN BIT(19) +#define MESON_ISA_TIMER_MUX_TIMERC_EN BIT(18) +#define MESON_ISA_TIMER_MUX_TIMERB_EN BIT(17) +#define MESON_ISA_TIMER_MUX_TIMERA_EN BIT(16) +#define MESON_ISA_TIMER_MUX_TIMERD_MODE BIT(15) +#define MESON_ISA_TIMER_MUX_TIMERC_MODE BIT(14) +#define MESON_ISA_TIMER_MUX_TIMERB_MODE BIT(13) +#define MESON_ISA_TIMER_MUX_TIMERA_MODE BIT(12) +#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK GENMASK(10, 8) +#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_SYSTEM_CLOCK 0x0 +#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1US 0x1 +#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_10US 0x2 +#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_100US 0x3 +#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1MS 0x4 +#define MESON_ISA_TIMER_MUX_TIMERD_INPUT_CLOCK_MASK GENMASK(7, 6) +#define MESON_ISA_TIMER_MUX_TIMERC_INPUT_CLOCK_MASK GENMASK(5, 4) +#define MESON_ISA_TIMER_MUX_TIMERB_INPUT_CLOCK_MASK GENMASK(3, 2) +#define MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK GENMASK(1, 0) +#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1US 0x0 +#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_10US 0x1 +#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_100US 0x0 +#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1MS 0x3 + +#define MESON_ISA_TIMERA 0x04 +#define MESON_ISA_TIMERB 0x08 +#define MESON_ISA_TIMERC 0x0c +#define MESON_ISA_TIMERD 0x10 +#define MESON_ISA_TIMERE 0x14 static void __iomem *timer_base; static u64 notrace meson6_timer_sched_read(void) { - return (u64)readl(timer_base + TIMER_ISA_VAL(CSD_ID)); + return (u64)readl(timer_base + MESON_ISA_TIMERE); } -static void meson6_clkevt_time_stop(unsigned char timer) +static void meson6_clkevt_time_stop(void) { - u32 val = readl(timer_base + TIMER_ISA_MUX); + u32 val = readl(timer_base + MESON_ISA_TIMER_MUX); - writel(val & ~TIMER_ENABLE_BIT(timer), timer_base + TIMER_ISA_MUX); + writel(val & ~MESON_ISA_TIMER_MUX_TIMERA_EN, + timer_base + MESON_ISA_TIMER_MUX); } -static void meson6_clkevt_time_setup(unsigned char timer, unsigned long delay) +static void meson6_clkevt_time_setup(unsigned long delay) { - writel(delay, timer_base + TIMER_ISA_VAL(timer)); + writel(delay, timer_base + MESON_ISA_TIMERA); } -static void meson6_clkevt_time_start(unsigned char timer, bool periodic) +static void meson6_clkevt_time_start(bool periodic) { - u32 val = readl(timer_base + TIMER_ISA_MUX); + u32 val = readl(timer_base + MESON_ISA_TIMER_MUX); if (periodic) - val |= TIMER_PERIODIC_BIT(timer); + val |= MESON_ISA_TIMER_MUX_TIMERA_MODE; else - val &= ~TIMER_PERIODIC_BIT(timer); + val &= ~MESON_ISA_TIMER_MUX_TIMERA_MODE; - writel(val | TIMER_ENABLE_BIT(timer), timer_base + TIMER_ISA_MUX); + writel(val | MESON_ISA_TIMER_MUX_TIMERA_EN, + timer_base + MESON_ISA_TIMER_MUX); } static int meson6_shutdown(struct clock_event_device *evt) { - meson6_clkevt_time_stop(CED_ID); + meson6_clkevt_time_stop(); return 0; } static int meson6_set_oneshot(struct clock_event_device *evt) { - meson6_clkevt_time_stop(CED_ID); - meson6_clkevt_time_start(CED_ID, false); + meson6_clkevt_time_stop(); + meson6_clkevt_time_start(false); return 0; } static int meson6_set_periodic(struct clock_event_device *evt) { - meson6_clkevt_time_stop(CED_ID); - meson6_clkevt_time_setup(CED_ID, USEC_PER_SEC / HZ - 1); - meson6_clkevt_time_start(CED_ID, true); + meson6_clkevt_time_stop(); + meson6_clkevt_time_setup(USEC_PER_SEC / HZ - 1); + meson6_clkevt_time_start(true); return 0; } static int meson6_clkevt_next_event(unsigned long evt, struct clock_event_device *unused) { - meson6_clkevt_time_stop(CED_ID); - meson6_clkevt_time_setup(CED_ID, evt); - meson6_clkevt_time_start(CED_ID, false); + meson6_clkevt_time_stop(); + meson6_clkevt_time_setup(evt); + meson6_clkevt_time_start(false); return 0; } @@ -144,22 +162,24 @@ static int __init meson6_timer_init(struct device_node *node) } /* Set 1us for timer E */ - val = readl(timer_base + TIMER_ISA_MUX); - val &= ~TIMER_CSD_INPUT_MASK; - val |= TIMER_CSD_UNIT_1US << TIMER_INPUT_BIT(CSD_ID); - writel(val, timer_base + TIMER_ISA_MUX); + val = readl(timer_base + MESON_ISA_TIMER_MUX); + val &= ~MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK; + val |= FIELD_PREP(MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK, + MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1US); + writel(val, timer_base + MESON_ISA_TIMER_MUX); sched_clock_register(meson6_timer_sched_read, 32, USEC_PER_SEC); - clocksource_mmio_init(timer_base + TIMER_ISA_VAL(CSD_ID), node->name, + clocksource_mmio_init(timer_base + MESON_ISA_TIMERE, node->name, 1000 * 1000, 300, 32, clocksource_mmio_readl_up); /* Timer A base 1us */ - val &= ~TIMER_CED_INPUT_MASK; - val |= TIMER_CED_UNIT_1US << TIMER_INPUT_BIT(CED_ID); - writel(val, timer_base + TIMER_ISA_MUX); + val &= ~MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK; + val |= FIELD_PREP(MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK, + MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1US); + writel(val, timer_base + MESON_ISA_TIMER_MUX); /* Stop the timer A */ - meson6_clkevt_time_stop(CED_ID); + meson6_clkevt_time_stop(); ret = setup_irq(irq, &meson6_timer_irq); if (ret) { From patchwork Tue Dec 18 21:28:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 154200 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4204337ljp; Tue, 18 Dec 2018 13:31:02 -0800 (PST) X-Google-Smtp-Source: AFSGD/Xy25q+2a31dM9jv355pb6BK3zkQwTy3YLw7cgIe1p7CnSB0wV5ghZogU8YMxOxtjSLT+w/ X-Received: by 2002:a17:902:2969:: with SMTP id g96mr17811791plb.295.1545168662667; Tue, 18 Dec 2018 13:31:02 -0800 (PST) ARC-Seal: i=1; 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[92.92.50.105]) by smtp.gmail.com with ESMTPSA id o4sm4153485wrq.66.2018.12.18.13.29.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Dec 2018 13:29:19 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Martin Blumenstingl , Carlo Caione , Kevin Hilman , linux-arm-kernel@lists.infradead.org (moderated list:ARM/Amlogic Meson SoC support), linux-amlogic@lists.infradead.org (open list:ARM/Amlogic Meson SoC support) Subject: [PATCH 07/25] clocksource/drivers/meson6_timer: Implement the ARM delay timer Date: Tue, 18 Dec 2018 22:28:25 +0100 Message-Id: <20181218212844.30445-7-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181218212844.30445-1-daniel.lezcano@linaro.org> References: <20181218212844.30445-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Martin Blumenstingl Implement an ARM delay timer to be used for udelay(). This allows us to skip the delay loop calibration at boot. With this patch udelay() is now independent of CPU frequency changes. This is a good thing on Meson8, Meson8b and Meson8m2 because changing the CPU frequency requires running the CPU clock off the XTAL while changing the PLL or it's dividers. After changing the CPU clocks we need to wait a few usecs for the clock to become stable. So having an udelay() implementation that doesn't depend on the CPU frequency is beneficial. Suggested-by: Jianxin Pan Signed-off-by: Martin Blumenstingl Signed-off-by: Daniel Lezcano --- drivers/clocksource/meson6_timer.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) -- 2.17.1 diff --git a/drivers/clocksource/meson6_timer.c b/drivers/clocksource/meson6_timer.c index 23c7638e2bb3..84bd9479c3f8 100644 --- a/drivers/clocksource/meson6_timer.c +++ b/drivers/clocksource/meson6_timer.c @@ -22,6 +22,10 @@ #include #include +#ifdef CONFIG_ARM +#include +#endif + #define MESON_ISA_TIMER_MUX 0x00 #define MESON_ISA_TIMER_MUX_TIMERD_EN BIT(19) #define MESON_ISA_TIMER_MUX_TIMERC_EN BIT(18) @@ -54,6 +58,18 @@ static void __iomem *timer_base; +#ifdef CONFIG_ARM +static unsigned long meson6_read_current_timer(void) +{ + return readl_relaxed(timer_base + MESON_ISA_TIMERE); +} + +static struct delay_timer meson6_delay_timer = { + .read_current_timer = meson6_read_current_timer, + .freq = 1000 * 1000, +}; +#endif + static u64 notrace meson6_timer_sched_read(void) { return (u64)readl(timer_base + MESON_ISA_TIMERE); @@ -192,6 +208,12 @@ static int __init meson6_timer_init(struct device_node *node) clockevents_config_and_register(&meson6_clockevent, USEC_PER_SEC, 1, 0xfffe); + +#ifdef CONFIG_ARM + /* Also use MESON_ISA_TIMERE for delays */ + register_current_timer_delay(&meson6_delay_timer); +#endif + return 0; } TIMER_OF_DECLARE(meson6, "amlogic,meson6-timer", From patchwork Tue Dec 18 21:28:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 154199 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4204224ljp; Tue, 18 Dec 2018 13:30:54 -0800 (PST) X-Google-Smtp-Source: AFSGD/W0D3efpLVrrOzSwqogAT4TOpMDyYqvkdJGoE256Z6uF2yg5JspgBrVpd+Hofw73+LPVlVq X-Received: by 2002:a63:1b1f:: with SMTP id b31mr17012479pgb.66.1545168653906; Tue, 18 Dec 2018 13:30:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545168653; cv=none; d=google.com; s=arc-20160816; b=ObSPXTSzULmjowCrcpbp1bJreGcbUQNjpbp+eDJTiLYcesumVO2BTGl/J76p9XWADB 3I7Hx1YX9ESCzDmlANKNGd4RBnR0O3ysae3mmUx2F6KwkER3MMJkZctBz2kVGSGrKMUP MHgcySa8LeVMsXY05yiEbVDTm9kMxIqyxl/+IEhapVC8QrOl9CzBkRGhGONK80+GveGr Pd8X3tdWo1KzFB9wfSPYelp7hrwRRDx7zWACyKv1wQYehNAZg2B00hM0Bv+vMm6l7c+p 0jKB92IxjB6pJqAE3wzmg24lUzL9BMl65chK3OpiYdaR6hsf7FPsvQ7L5l1LyVDMhffb iBqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=NRONHF0HHvvIqlLpPf6sMlWUD+SdPWgYu2xk+QwdQD8=; b=nHHg+t7s3RGU5noaupoLgGAHLW4VhVpjN2kljvAWsp3Z/6YIzAxO3b1ZVxFXCIiZO7 vWZOPFrOTHp3/007sHKV+H+QF9AX6y7WpJuGWyUJnZWyAQ0v6vX5oTZHKyuBHtFozvMP AUzi91m171kQBPG232RhOhkKEa6eqx/KFDZ7pYnQLKBtN6tQZ6QIXkyeYNTWvNzu4kTj ebbk9+cYBM6UbFyEyXQ79+EpNhoOmbln8apSj6bBtB/HcC7gJHy1DFy7+9wUw+vdgPMB vXyiRxJ3SCtEljeiNHJtHnOKFwLOFjYhBFNFKQ0frU++JEFFLCTISrjUfY2XtIBcMCtP iRoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Gm3OnN61; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.92.50.105]) by smtp.gmail.com with ESMTPSA id o4sm4153485wrq.66.2018.12.18.13.29.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Dec 2018 13:29:20 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Anson Huang , Anson Huang Subject: [PATCH 08/25] clocksource/drivers/imx-gpt: Add support for ARM64 Date: Tue, 18 Dec 2018 22:28:26 +0100 Message-Id: <20181218212844.30445-8-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181218212844.30445-1-daniel.lezcano@linaro.org> References: <20181218212844.30445-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Anson Huang This patch allows building and compile-testing the i.MX GPT driver also for ARM64. The delay_timer is only supported on ARMv7. Signed-off-by: Anson Huang Signed-off-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 2 +- drivers/clocksource/timer-imx-gpt.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 64d5759ddf0e..8761a1c21b6c 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -567,7 +567,7 @@ config H8300_TPU config CLKSRC_IMX_GPT bool "Clocksource using i.MX GPT" if COMPILE_TEST - depends on ARM && CLKDEV_LOOKUP + depends on (ARM || ARM64) && CLKDEV_LOOKUP select CLKSRC_MMIO config CLKSRC_IMX_TPM diff --git a/drivers/clocksource/timer-imx-gpt.c b/drivers/clocksource/timer-imx-gpt.c index 165fbbb1c9a0..a3d6ccbf4a16 100644 --- a/drivers/clocksource/timer-imx-gpt.c +++ b/drivers/clocksource/timer-imx-gpt.c @@ -141,21 +141,25 @@ static u64 notrace mxc_read_sched_clock(void) return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0; } +#if defined(CONFIG_ARM) static struct delay_timer imx_delay_timer; static unsigned long imx_read_current_timer(void) { return readl_relaxed(sched_clock_reg); } +#endif static int __init mxc_clocksource_init(struct imx_timer *imxtm) { unsigned int c = clk_get_rate(imxtm->clk_per); void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn; +#if defined(CONFIG_ARM) imx_delay_timer.read_current_timer = &imx_read_current_timer; imx_delay_timer.freq = c; register_current_timer_delay(&imx_delay_timer); +#endif sched_clock_reg = reg; From patchwork Tue Dec 18 21:28:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 154182 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4202961ljp; Tue, 18 Dec 2018 13:29:28 -0800 (PST) X-Google-Smtp-Source: AFSGD/WyaCs3c5Zmgsm44W/ZAExB3Y3x8aCjjK8Itn4cTcm0oNMwvjapHbRRZj3BhjIQY1IN+WZA X-Received: by 2002:a17:902:108a:: with SMTP id c10mr9117821pla.131.1545168568472; Tue, 18 Dec 2018 13:29:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545168568; cv=none; d=google.com; s=arc-20160816; b=AP64DtXaTFGxKT/+MGulUzlhZWcxwPGPdVC0C9lJKpZnrnsvI3m2og3MbKbwGRLB+Z MGgxVrg4XNz/X0x6gH89xqYEi4aIxNgL624lTYV/+94pUc05NMWRYbrF1E0wlj/eXzPQ uSsWtDNfqSgu4ltbsEhbduShtPD2pcR9Ye/1xAzP+646uGsSu+aB3AKjvHDwJien86Ux yEHz/p+RAS0F/vijb7PI6MIuxLAkaowhdEbyyusuQvdzPn0TOi2NHETcx9prc3lhowQO wj3soVtctCZqPTuvEUvdmVchqa8thSxW72LbaSjrLwBU4b9CsrAqGxqT4MRJ/GUrr5EZ JVHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=JDGG/ePDW8fZY0txCpV8Qva5v2tCPJZst6J7AJgbbOs=; b=It0zfrnVehYfHOLqo0DMwfx3Dc82RDnv1cjRsZaxCshfIUBtSthkJsE4Xrygv1RFmw 4Yzp4SB0Wt/bhq7uvI6fL3Ozg6a9yNDKkXOroYwJGX8JZy+sIon3fARDaHv4rL4t1Axq zlYC3Fgi5kItdDDFJBQF/IogdJiDU3dg71rFLjzgUp5OkrOUkG3P1Vy0mEb+vpvTfjWk 0JbCuLp5SKdQYfP/sG94mOo8a54AIL2KHVlUuvAIpLrSuOEAioDueeOidsTXXC+lrvO4 TCHSO9OHSCqxX/0qcmA1AqUZhctXBn8XcJjq25cWIq8khOpnhSRUwdX0IjyCb5YWC3Wf vb6A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TM7PWvV5; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.92.50.105]) by smtp.gmail.com with ESMTPSA id o4sm4153485wrq.66.2018.12.18.13.29.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Dec 2018 13:29:22 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH 09/25] clocksource/drivers/imx-gpt: Remove unnecessary irq protection Date: Tue, 18 Dec 2018 22:28:27 +0100 Message-Id: <20181218212844.30445-9-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181218212844.30445-1-daniel.lezcano@linaro.org> References: <20181218212844.30445-1-daniel.lezcano@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Clément Péron shutdown and oneshot are already protected against irq interruptions Signed-off-by: Clément Péron Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-imx-gpt.c | 17 ----------------- 1 file changed, 17 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/timer-imx-gpt.c b/drivers/clocksource/timer-imx-gpt.c index a3d6ccbf4a16..706c0d0ff56c 100644 --- a/drivers/clocksource/timer-imx-gpt.c +++ b/drivers/clocksource/timer-imx-gpt.c @@ -202,15 +202,8 @@ static int v2_set_next_event(unsigned long evt, static int mxc_shutdown(struct clock_event_device *ced) { struct imx_timer *imxtm = to_imx_timer(ced); - unsigned long flags; u32 tcn; - /* - * The timer interrupt generation is disabled at least - * for enough time to call mxc_set_next_event() - */ - local_irq_save(flags); - /* Disable interrupt in GPT module */ imxtm->gpt->gpt_irq_disable(imxtm); @@ -225,21 +218,12 @@ static int mxc_shutdown(struct clock_event_device *ced) printk(KERN_INFO "%s: changing mode\n", __func__); #endif /* DEBUG */ - local_irq_restore(flags); - return 0; } static int mxc_set_oneshot(struct clock_event_device *ced) { struct imx_timer *imxtm = to_imx_timer(ced); - unsigned long flags; - - /* - * The timer interrupt generation is disabled at least - * for enough time to call mxc_set_next_event() - */ - local_irq_save(flags); /* Disable interrupt in GPT module */ imxtm->gpt->gpt_irq_disable(imxtm); @@ -264,7 +248,6 @@ static int mxc_set_oneshot(struct clock_event_device *ced) * mode switching */ imxtm->gpt->gpt_irq_enable(imxtm); - local_irq_restore(flags); return 0; } From patchwork Tue Dec 18 21:28:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 154198 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4204108ljp; Tue, 18 Dec 2018 13:30:47 -0800 (PST) X-Google-Smtp-Source: AFSGD/XBRTKP5B8MCfSLk6i1PbIvkW8KrmFi4FuGa3pK3jmnX12zLYQLJGT6GdUc1VsStIfOemw9 X-Received: by 2002:a62:6143:: with SMTP id v64mr18054838pfb.142.1545168647582; Tue, 18 Dec 2018 13:30:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545168647; cv=none; d=google.com; s=arc-20160816; b=ZAHo6FIXrXtxTLK1zcnxPMNYYXV90ib9JICcxMEJUDXxbmbVBndJpGKMHm4pAgUOhE Qaoiy5HEiZfpKxd+dn22pdsQ2NUaAXAJOMklX+p2EkY91vaxUeLmfkdhBguv/JPc50w8 sQlrSaiLrRPT5O0R3ETSTr1kDF9IchzDPUjQlUFbUFBW0eBXXQC02eA6y9A/JrNa3a58 YMhvgi5EzgTPG4w1MajfR4Tv8NvIQ5nTQJdVYBO490CODDiCNZdsKzuMncsRdiqBYoTH kmSsnRjw0OKmdAU/j0uIQdqncV/IZUB2qx+vCJzX382ox1B/tVg+XodSZlQkkqag07ik t15Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=LlG9LbRT/Q0m531ljY3ISX/R0czf+ZPbNjDuaHFc7o0=; b=uQeyApcXBFuUWe6dj+pnD5iwByQDAJfp8k3uwafepJxoywHwztVW3eO8S/ZisfvW+G Q0bdnEl7JZczBMzFc9Y7PjoK+r3dPsTIBzoTrE24Mhs4up5vaunTyUisMIYcUTEnxL8N Ku/UiSc9uIG9n8D8QQAA6oaVnPxPUyXNOBC7BRodQZRHFwBFGjO9+6002ICRpmtwFuW9 TiLyYPMQg236k8Wrz5zOURPQtbmgn/vqkPwy8Uyt7Gqi7kQEk81GKpl1BhEXn2txd+OQ svU1v34BlyW573crxLs3IKSo5wz7piGzaM4TkeO3Rt9qPnwkQxA26/oT4kuqG03e5Vjk 5XCg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WvAnzJLS; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.92.50.105]) by smtp.gmail.com with ESMTPSA id o4sm4153485wrq.66.2018.12.18.13.29.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Dec 2018 13:29:25 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Biju Das , Rob Herring , Mark Rutland , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH 11/25] dt-bindings: timer: renesas, cmt: Document r8a77470 CMT support Date: Tue, 18 Dec 2018 22:28:29 +0100 Message-Id: <20181218212844.30445-11-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181218212844.30445-1-daniel.lezcano@linaro.org> References: <20181218212844.30445-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Biju Das Document SoC specific compatible strings for r8a77470. No driver change is needed as the fallback strings will activate the right code. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Simon Horman Reviewed-by: Rob Herring Signed-off-by: Daniel Lezcano --- Documentation/devicetree/bindings/timer/renesas,cmt.txt | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt index 6de27b60b51a..eb602c599341 100644 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt @@ -28,6 +28,8 @@ Required Properties: - "renesas,r8a7744-cmt1" for the 48-bit CMT1 device included in r8a7744. - "renesas,r8a7745-cmt0" for the 32-bit CMT0 device included in r8a7745. - "renesas,r8a7745-cmt1" for the 48-bit CMT1 device included in r8a7745. + - "renesas,r8a77470-cmt0" for the 32-bit CMT0 device included in r8a77470. + - "renesas,r8a77470-cmt1" for the 48-bit CMT1 device included in r8a77470. - "renesas,r8a7790-cmt0" for the 32-bit CMT0 device included in r8a7790. - "renesas,r8a7790-cmt1" for the 48-bit CMT1 device included in r8a7790. - "renesas,r8a7791-cmt0" for the 32-bit CMT0 device included in r8a7791. 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[92.92.50.105]) by smtp.gmail.com with ESMTPSA id o4sm4153485wrq.66.2018.12.18.13.29.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Dec 2018 13:29:27 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Alexey Brodkin , Alexey Brodkin , Vineet Gupta , stable@vger.kernel.org, linux-snps-arc@lists.infradead.org (open list:SYNOPSYS ARC ARCHITECTURE) Subject: [PATCH 12/25] clocksource/drivers/arc_timer: Utilize generic sched_clock Date: Tue, 18 Dec 2018 22:28:30 +0100 Message-Id: <20181218212844.30445-12-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181218212844.30445-1-daniel.lezcano@linaro.org> References: <20181218212844.30445-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Alexey Brodkin It turned out we used to use default implementation of sched_clock() from kernel/sched/clock.c which was as precise as 1/HZ, i.e. by default we had 10 msec granularity of time measurement. Now given ARC built-in timers are clocked with the same frequency as CPU cores we may get much higher precision of time tracking. Thus we switch to generic sched_clock which really reads ARC hardware counters. This is especially helpful for measuring short events. That's what we used to have: ------------------------------>8------------------------ $ perf stat /bin/sh -c /root/lmbench-master/bin/arc/hello > /dev/null Performance counter stats for '/bin/sh -c /root/lmbench-master/bin/arc/hello': 10.000000 task-clock (msec) # 2.832 CPUs utilized 1 context-switches # 0.100 K/sec 1 cpu-migrations # 0.100 K/sec 63 page-faults # 0.006 M/sec 3049480 cycles # 0.305 GHz 1091259 instructions # 0.36 insn per cycle 256828 branches # 25.683 M/sec 27026 branch-misses # 10.52% of all branches 0.003530687 seconds time elapsed 0.000000000 seconds user 0.010000000 seconds sys ------------------------------>8------------------------ And now we'll see: ------------------------------>8------------------------ $ perf stat /bin/sh -c /root/lmbench-master/bin/arc/hello > /dev/null Performance counter stats for '/bin/sh -c /root/lmbench-master/bin/arc/hello': 3.004322 task-clock (msec) # 0.865 CPUs utilized 1 context-switches # 0.333 K/sec 1 cpu-migrations # 0.333 K/sec 63 page-faults # 0.021 M/sec 2986734 cycles # 0.994 GHz 1087466 instructions # 0.36 insn per cycle 255209 branches # 84.947 M/sec 26002 branch-misses # 10.19% of all branches 0.003474829 seconds time elapsed 0.003519000 seconds user 0.000000000 seconds sys ------------------------------>8------------------------ Note how much more meaningful is the second output - time spent for execution pretty much matches number of cycles spent (we're runnign @ 1GHz here). Signed-off-by: Alexey Brodkin Cc: Daniel Lezcano Cc: Vineet Gupta Cc: Thomas Gleixner Cc: stable@vger.kernel.org Acked-by: Vineet Gupta Signed-off-by: Daniel Lezcano Signed-off-by: Daniel Lezcano --- arch/arc/Kconfig | 1 + drivers/clocksource/Kconfig | 1 + drivers/clocksource/arc_timer.c | 22 ++++++++++++++++++++++ 3 files changed, 24 insertions(+) -- 2.17.1 diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index c9e2a1323536..74b5a654f664 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -26,6 +26,7 @@ config ARC select GENERIC_IRQ_SHOW select GENERIC_PCI_IOMAP select GENERIC_PENDING_IRQ if SMP + select GENERIC_SCHED_CLOCK select GENERIC_SMP_IDLE_THREAD select HAVE_ARCH_KGDB select HAVE_ARCH_TRACEHOOK diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 8761a1c21b6c..c57b156f49a2 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -277,6 +277,7 @@ config CLKSRC_MPS2 config ARC_TIMERS bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST + depends on GENERIC_SCHED_CLOCK select TIMER_OF help These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores diff --git a/drivers/clocksource/arc_timer.c b/drivers/clocksource/arc_timer.c index 20da9b1d7f7d..b28970ca4a7a 100644 --- a/drivers/clocksource/arc_timer.c +++ b/drivers/clocksource/arc_timer.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include @@ -88,6 +89,11 @@ static u64 arc_read_gfrc(struct clocksource *cs) return (((u64)h) << 32) | l; } +static notrace u64 arc_gfrc_clock_read(void) +{ + return arc_read_gfrc(NULL); +} + static struct clocksource arc_counter_gfrc = { .name = "ARConnect GFRC", .rating = 400, @@ -111,6 +117,8 @@ static int __init arc_cs_setup_gfrc(struct device_node *node) if (ret) return ret; + sched_clock_register(arc_gfrc_clock_read, 64, arc_timer_freq); + return clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq); } TIMER_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc); @@ -139,6 +147,11 @@ static u64 arc_read_rtc(struct clocksource *cs) return (((u64)h) << 32) | l; } +static notrace u64 arc_rtc_clock_read(void) +{ + return arc_read_rtc(NULL); +} + static struct clocksource arc_counter_rtc = { .name = "ARCv2 RTC", .rating = 350, @@ -170,6 +183,8 @@ static int __init arc_cs_setup_rtc(struct device_node *node) write_aux_reg(AUX_RTC_CTRL, 1); + sched_clock_register(arc_rtc_clock_read, 64, arc_timer_freq); + return clocksource_register_hz(&arc_counter_rtc, arc_timer_freq); } TIMER_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc); @@ -185,6 +200,11 @@ static u64 arc_read_timer1(struct clocksource *cs) return (u64) read_aux_reg(ARC_REG_TIMER1_CNT); } +static notrace u64 arc_timer1_clock_read(void) +{ + return arc_read_timer1(NULL); +} + static struct clocksource arc_counter_timer1 = { .name = "ARC Timer1", .rating = 300, @@ -209,6 +229,8 @@ static int __init arc_cs_setup_timer1(struct device_node *node) write_aux_reg(ARC_REG_TIMER1_CNT, 0); write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH); + sched_clock_register(arc_timer1_clock_read, 32, arc_timer_freq); + return clocksource_register_hz(&arc_counter_timer1, arc_timer_freq); } From patchwork Tue Dec 18 21:28:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 154196 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4203898ljp; Tue, 18 Dec 2018 13:30:34 -0800 (PST) X-Google-Smtp-Source: AFSGD/VY797ivbhuU2SrwejjEw5HaNSumhIJhjvl0pHX4JCDpqoYm0EOkFI9KU1ZL7azNjoPf7f2 X-Received: by 2002:a17:902:e08b:: with SMTP id cb11mr18053886plb.263.1545168634809; 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[92.92.50.105]) by smtp.gmail.com with ESMTPSA id o4sm4153485wrq.66.2018.12.18.13.29.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Dec 2018 13:29:28 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Anson Huang , Anson Huang Subject: [PATCH 13/25] clocksource/drivers/timer-imx-tpm: Convert the driver to timer-of Date: Tue, 18 Dec 2018 22:28:31 +0100 Message-Id: <20181218212844.30445-13-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181218212844.30445-1-daniel.lezcano@linaro.org> References: <20181218212844.30445-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Anson Huang Convert the driver to use the timer_of helpers. This allows to handle timer base, clock and irq using common timer_of driver and it simplifies the code. Signed-off-by: Anson Huang Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-imx-tpm.c | 136 +++++++++++----------------- 1 file changed, 55 insertions(+), 81 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/timer-imx-tpm.c b/drivers/clocksource/timer-imx-tpm.c index b7aa2b817078..c3dd4d2f2a6e 100644 --- a/drivers/clocksource/timer-imx-tpm.c +++ b/drivers/clocksource/timer-imx-tpm.c @@ -12,6 +12,8 @@ #include #include +#include "timer-of.h" + #define TPM_PARAM 0x4 #define TPM_PARAM_WIDTH_SHIFT 16 #define TPM_PARAM_WIDTH_MASK (0xff << 16) @@ -33,9 +35,7 @@ #define TPM_C0V 0x24 static int counter_width; -static int rating; static void __iomem *timer_base; -static struct clock_event_device clockevent_tpm; static inline void tpm_timer_disable(void) { @@ -80,19 +80,6 @@ static u64 notrace tpm_read_sched_clock(void) return tpm_read_counter(); } -static int __init tpm_clocksource_init(unsigned long rate) -{ - tpm_delay_timer.read_current_timer = &tpm_read_current_timer; - tpm_delay_timer.freq = rate; - register_current_timer_delay(&tpm_delay_timer); - - sched_clock_register(tpm_read_sched_clock, counter_width, rate); - - return clocksource_mmio_init(timer_base + TPM_CNT, "imx-tpm", - rate, rating, counter_width, - clocksource_mmio_readl_up); -} - static int tpm_set_next_event(unsigned long delta, struct clock_event_device *evt) { @@ -137,74 +124,77 @@ static irqreturn_t tpm_timer_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static struct clock_event_device clockevent_tpm = { - .name = "i.MX7ULP TPM Timer", - .features = CLOCK_EVT_FEAT_ONESHOT, - .set_state_oneshot = tpm_set_state_oneshot, - .set_next_event = tpm_set_next_event, - .set_state_shutdown = tpm_set_state_shutdown, +static struct timer_of to_tpm = { + .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK, + .clkevt = { + .name = "i.MX7ULP TPM Timer", + .rating = 200, + .features = CLOCK_EVT_FEAT_ONESHOT, + .set_state_shutdown = tpm_set_state_shutdown, + .set_state_oneshot = tpm_set_state_oneshot, + .set_next_event = tpm_set_next_event, + .cpumask = cpu_possible_mask, + }, + .of_irq = { + .handler = tpm_timer_interrupt, + .flags = IRQF_TIMER | IRQF_IRQPOLL, + }, }; -static int __init tpm_clockevent_init(unsigned long rate, int irq) +static int __init tpm_clocksource_init(void) { - int ret; + tpm_delay_timer.read_current_timer = &tpm_read_current_timer; + tpm_delay_timer.freq = timer_of_rate(&to_tpm) >> 3; + register_current_timer_delay(&tpm_delay_timer); - ret = request_irq(irq, tpm_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, - "i.MX7ULP TPM Timer", &clockevent_tpm); + sched_clock_register(tpm_read_sched_clock, counter_width, + timer_of_rate(&to_tpm) >> 3); - clockevent_tpm.rating = rating; - clockevent_tpm.cpumask = cpumask_of(0); - clockevent_tpm.irq = irq; - clockevents_config_and_register(&clockevent_tpm, rate, 300, - GENMASK(counter_width - 1, 1)); + return clocksource_mmio_init(timer_base + TPM_CNT, + "imx-tpm", + timer_of_rate(&to_tpm) >> 3, + to_tpm.clkevt.rating, + counter_width, + clocksource_mmio_readl_up); +} - return ret; +static void __init tpm_clockevent_init(void) +{ + clockevents_config_and_register(&to_tpm.clkevt, + timer_of_rate(&to_tpm) >> 3, + 300, + GENMASK(counter_width - 1, + 1)); } static int __init tpm_timer_init(struct device_node *np) { - struct clk *ipg, *per; - int irq, ret; - u32 rate; - - timer_base = of_iomap(np, 0); - if (!timer_base) { - pr_err("tpm: failed to get base address\n"); - return -ENXIO; - } - - irq = irq_of_parse_and_map(np, 0); - if (!irq) { - pr_err("tpm: failed to get irq\n"); - ret = -ENOENT; - goto err_iomap; - } + struct clk *ipg; + int ret; ipg = of_clk_get_by_name(np, "ipg"); - per = of_clk_get_by_name(np, "per"); - if (IS_ERR(ipg) || IS_ERR(per)) { - pr_err("tpm: failed to get ipg or per clk\n"); - ret = -ENODEV; - goto err_clk_get; + if (IS_ERR(ipg)) { + pr_err("tpm: failed to get ipg clk\n"); + return -ENODEV; } - /* enable clk before accessing registers */ ret = clk_prepare_enable(ipg); if (ret) { pr_err("tpm: ipg clock enable failed (%d)\n", ret); - goto err_clk_get; + clk_put(ipg); + return ret; } - ret = clk_prepare_enable(per); - if (ret) { - pr_err("tpm: per clock enable failed (%d)\n", ret); - goto err_per_clk_enable; - } + ret = timer_of_init(np, &to_tpm); + if (ret) + return ret; + + timer_base = timer_of_base(&to_tpm); - counter_width = (readl(timer_base + TPM_PARAM) & TPM_PARAM_WIDTH_MASK) - >> TPM_PARAM_WIDTH_SHIFT; + counter_width = (readl(timer_base + TPM_PARAM) + & TPM_PARAM_WIDTH_MASK) >> TPM_PARAM_WIDTH_SHIFT; /* use rating 200 for 32-bit counter and 150 for 16-bit counter */ - rating = counter_width == 0x20 ? 200 : 150; + to_tpm.clkevt.rating = counter_width == 0x20 ? 200 : 150; /* * Initialize tpm module to a known state @@ -229,29 +219,13 @@ static int __init tpm_timer_init(struct device_node *np) writel(TPM_SC_CMOD_INC_PER_CNT | (counter_width == 0x20 ? TPM_SC_CMOD_DIV_DEFAULT : TPM_SC_CMOD_DIV_MAX), - timer_base + TPM_SC); + timer_base + TPM_SC); /* set MOD register to maximum for free running mode */ writel(GENMASK(counter_width - 1, 0), timer_base + TPM_MOD); - rate = clk_get_rate(per) >> 3; - ret = tpm_clocksource_init(rate); - if (ret) - goto err_per_clk_enable; - - ret = tpm_clockevent_init(rate, irq); - if (ret) - goto err_per_clk_enable; - - return 0; + tpm_clockevent_init(); -err_per_clk_enable: - clk_disable_unprepare(ipg); -err_clk_get: - clk_put(per); - clk_put(ipg); -err_iomap: - iounmap(timer_base); - return ret; + return tpm_clocksource_init(); } TIMER_OF_DECLARE(imx7ulp, "fsl,imx7ulp-tpm", tpm_timer_init); From patchwork Tue Dec 18 21:28:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 154185 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4203090ljp; Tue, 18 Dec 2018 13:29:37 -0800 (PST) X-Google-Smtp-Source: AFSGD/VuuGSzuOXFCBB4EU0ovk6MApLfSaLmcUzWISYGjveLdkn5nV7bEJOSPdhlEE/ZhIbmDy0l X-Received: by 2002:a17:902:a411:: with SMTP id p17mr17649975plq.292.1545168577508; Tue, 18 Dec 2018 13:29:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545168577; cv=none; d=google.com; s=arc-20160816; b=Gb3NrO1lFDsTABhyzxVEov7aIWc4oVCq647zRRctUaLj2P5zu4OBJJuRjD8Wy3rWW1 ghgYvmfxT/A7Y9oNnO0JPV94OquzLmr452R2BY1obeHERin0gb6iPLSDBmCItXs0L5eH aJxZuvcQ76EAnsnEGugpZLBMgucEp4EzDBCOog3KbCEMz7xEF3o4uaouwf0zOft3IpUb 8dbtG0jTJAWFfW5OrV60H/W47VQ3HsIZsWocpAwAej/qjQFN9v8qvbFYWhiCQdipaH6O EOjJIAeQiTamXgV2KUV3SSEFdQ47RqL8gSFgy3MJdo2MzP1CyXJ3JnJ0C5eZ7TWECRxD Y7kg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=QNYOuzWiRe8n31bZiL2aJF+DJft2DVSSW8AmaS53Sng=; b=LUn6vHKuYSMDORR9hVKguCo2/LyQoiJt9PwJtqWYjjSHBspx6t7fwsHt6XVqGm6wuB y7xeauUXIYPAd5bAEQ3iWXdHAl5nM+NZLiWjjxvxN9exiwaOjLE4MKwJZR9I+VTMZ52s JBEDgIZgHaFncQOtBTe9vDHwfrDc6UiAGMT2mM8QkA2DmhQiJDcF9Eb6V7Q1Fm5H8Ryj t1UM1gnwclwc1t/fKTz9s/btCeu2QpXqEKyJJ9JmJIosuucut0FycUSvs0uWcLLTPz95 HCwO56es6/dXMEHpDkagg8hnofrcaAfUFp7NIgnPDMPqmwpBMG7OQqWn/lEgSVsXbsTr o66w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cdf4UhSu; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.92.50.105]) by smtp.gmail.com with ESMTPSA id o4sm4153485wrq.66.2018.12.18.13.29.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Dec 2018 13:29:30 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Biju Das , Rob Herring , Mark Rutland , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH 14/25] dt-bindings: timer: renesas, cmt: Document r8a774a1 CMT support Date: Tue, 18 Dec 2018 22:28:32 +0100 Message-Id: <20181218212844.30445-14-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181218212844.30445-1-daniel.lezcano@linaro.org> References: <20181218212844.30445-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Biju Das Document SoC specific bindings for RZ/G2M (r8a774a1) SoC. Signed-off-by: Biju Das Reviewed-by: Simon Horman Signed-off-by: Daniel Lezcano --- .../devicetree/bindings/timer/renesas,cmt.txt | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt index eb602c599341..862a80f0380a 100644 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt @@ -30,6 +30,8 @@ Required Properties: - "renesas,r8a7745-cmt1" for the 48-bit CMT1 device included in r8a7745. - "renesas,r8a77470-cmt0" for the 32-bit CMT0 device included in r8a77470. - "renesas,r8a77470-cmt1" for the 48-bit CMT1 device included in r8a77470. + - "renesas,r8a774a1-cmt0" for the 32-bit CMT0 device included in r8a774a1. + - "renesas,r8a774a1-cmt1" for the 48-bit CMT1 device included in r8a774a1. - "renesas,r8a7790-cmt0" for the 32-bit CMT0 device included in r8a7790. - "renesas,r8a7790-cmt1" for the 48-bit CMT1 device included in r8a7790. - "renesas,r8a7791-cmt0" for the 32-bit CMT0 device included in r8a7791. @@ -51,9 +53,12 @@ Required Properties: and RZ/G1. These are fallbacks for r8a73a4, R-Car Gen2 and RZ/G1 entries listed above. - - "renesas,rcar-gen3-cmt0" for 32-bit CMT0 devices included in R-Car Gen3. - - "renesas,rcar-gen3-cmt1" for 48-bit CMT1 devices included in R-Car Gen3. - These are fallbacks for R-Car Gen3 entries listed above. + - "renesas,rcar-gen3-cmt0" for 32-bit CMT0 devices included in R-Car Gen3 + and RZ/G2. + - "renesas,rcar-gen3-cmt1" for 48-bit CMT1 devices included in R-Car Gen3 + and RZ/G2. + These are fallbacks for R-Car Gen3 and RZ/G2 entries listed + above. - reg: base address and length of the registers block for the timer module. - interrupts: interrupt-specifier for the timer, one per channel. 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[92.92.50.105]) by smtp.gmail.com with ESMTPSA id o4sm4153485wrq.66.2018.12.18.13.29.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Dec 2018 13:29:32 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Stefan Wahren , Simon Arlott , Eric Anholt , Florian Fainelli , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITE...), linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2835 ARM ARCHITECTURE) Subject: [PATCH 15/25] clocksource/drivers/bcm2835: Switch to SPDX identifier Date: Tue, 18 Dec 2018 22:28:33 +0100 Message-Id: <20181218212844.30445-15-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181218212844.30445-1-daniel.lezcano@linaro.org> References: <20181218212844.30445-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Stefan Wahren Adopt the SPDX license identifier headers to ease license compliance management. Also drop the FSF address. Cc: Simon Arlott Signed-off-by: Stefan Wahren Reviewed-by: Eric Anholt Acked-by: Daniel Lezcano Signed-off-by: Daniel Lezcano --- drivers/clocksource/bcm2835_timer.c | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/bcm2835_timer.c b/drivers/clocksource/bcm2835_timer.c index 60da2537bef9..2b196cbfadb6 100644 --- a/drivers/clocksource/bcm2835_timer.c +++ b/drivers/clocksource/bcm2835_timer.c @@ -1,19 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2012 Simon Arlott - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include From patchwork Tue Dec 18 21:28:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 154195 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4203795ljp; Tue, 18 Dec 2018 13:30:29 -0800 (PST) X-Google-Smtp-Source: AFSGD/VP3aZRcsC2FgT1zXIffHnNu042IV/h++4uHyG4m4sTaQAAi7waIg66JHG3vEjkUJ4CWiG7 X-Received: by 2002:a63:f74f:: with SMTP id f15mr17329261pgk.190.1545168629243; Tue, 18 Dec 2018 13:30:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545168629; cv=none; d=google.com; s=arc-20160816; b=w/j0+hgoG/PKkiowzm9l6dhJ1cmLLxLQ9+U+FAvcB5Rch/wpZ2edm+pAxgcfkzQfWS 1/9v6jc4gG5WVYaHiMQqsWd/WW8o7m6MxqUPtrlxIRnLo1hyVKTXDzsoz6glCTXVMLkd UtcKjJF1DPmSnip3AA+Bhcxu3jKFs9bk8kc6M8oITX6qXe//j3TzXIouB7i5XKvNhqr6 dzL/9rW8ogNuAAKbA97+/KdR8XjQkvMBT2FSd1OL1QsZQRXfCKpY/3t4BX+n7UrOjEfv tQK08SmEtNhJLIx0B758Qpcb0Dt6ou7VoYsjwzyiePdU8UnnJ0+nd8FfAjimASqLi6X9 Sr0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=8yYswTIddbl98Ij+qY0GbRy4Tl1Yh+JSAqMNtmY8jFQ=; b=s3mulznRCfs6hLGBEDLW2nor9WaWeLwkaOiwzoIx6edFUFpWRolpLe7SZ4SL+y07jh ONLUEJlfs5113D/CYAqnlmdmYHmOLEB1ZmwXN+x4S11HSMoBG1ksu4su3n9NlLcNbhpQ DEy3l/qS733NHzQz/orPxfam/p8b4PpV9MZ469ry2qkgz/Lrj8RNgJv8Bk7hvSlC5eZl fWD7xj9CReVFZ1cQMjARF/nuUR3/6kYbE96pq+2Ry7mZVcFX52jTo+gFM1tDQfowcDia s9NaYKVsDRXoZxArxZgTQQE1loAvzG42AembT3hKQlOe0ZyQ7iTmD0XXI9s6gK2fGf/e 6xdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=g401sXmL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.92.50.105]) by smtp.gmail.com with ESMTPSA id o4sm4153485wrq.66.2018.12.18.13.29.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Dec 2018 13:29:33 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Yangtao Li Subject: [PATCH 16/25] clocksource/drivers/integrator-ap: Add missing of_node_put() Date: Tue, 18 Dec 2018 22:28:34 +0100 Message-Id: <20181218212844.30445-16-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181218212844.30445-1-daniel.lezcano@linaro.org> References: <20181218212844.30445-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Yangtao Li The function of_find_node_by_path() acquires a reference to the node returned by it and that reference needs to be dropped by its caller. integrator_ap_timer_init_of() doesn't do that. The pri_node and the sec_node are used as an identifier to compare against the current node, so we can directly drop the refcount after getting the node from the path as it is not used as pointer. By dropping the refcount right after getting it, a single variable is needed instead of two. Fix this by use a single variable and drop the refcount right after of_find_node_by_path(). Signed-off-by: Yangtao Li Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-integrator-ap.c | 25 +++++++++++++++-------- 1 file changed, 16 insertions(+), 9 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/timer-integrator-ap.c b/drivers/clocksource/timer-integrator-ap.c index 76e526f58620..19fb7de4b928 100644 --- a/drivers/clocksource/timer-integrator-ap.c +++ b/drivers/clocksource/timer-integrator-ap.c @@ -181,8 +181,7 @@ static int __init integrator_ap_timer_init_of(struct device_node *node) int irq; struct clk *clk; unsigned long rate; - struct device_node *pri_node; - struct device_node *sec_node; + struct device_node *alias_node; base = of_io_request_and_map(node, 0, "integrator-timer"); if (IS_ERR(base)) @@ -204,7 +203,18 @@ static int __init integrator_ap_timer_init_of(struct device_node *node) return err; } - pri_node = of_find_node_by_path(path); + alias_node = of_find_node_by_path(path); + + /* + * The pointer is used as an identifier not as a pointer, we + * can drop the refcount on the of__node immediately after + * getting it. + */ + of_node_put(alias_node); + + if (node == alias_node) + /* The primary timer lacks IRQ, use as clocksource */ + return integrator_clocksource_init(rate, base); err = of_property_read_string(of_aliases, "arm,timer-secondary", &path); @@ -213,14 +223,11 @@ static int __init integrator_ap_timer_init_of(struct device_node *node) return err; } + alias_node = of_find_node_by_path(path); - sec_node = of_find_node_by_path(path); - - if (node == pri_node) - /* The primary timer lacks IRQ, use as clocksource */ - return integrator_clocksource_init(rate, base); + of_node_put(alias_node); - if (node == sec_node) { + if (node == alias_node) { /* The secondary timer will drive the clock event */ irq = irq_of_parse_and_map(node, 0); return integrator_clockevent_init(rate, base, irq); From patchwork Tue Dec 18 21:28:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 154187 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4203153ljp; Tue, 18 Dec 2018 13:29:42 -0800 (PST) X-Google-Smtp-Source: AFSGD/W385wpeoJpfsSZmYWM73YlaexI5otyRZKscY2hII993OVmmUuPHYtbJSDpSVESL8vsIx45 X-Received: by 2002:a63:ea4f:: with SMTP id l15mr16844728pgk.102.1545168582558; Tue, 18 Dec 2018 13:29:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545168582; cv=none; d=google.com; s=arc-20160816; b=yEdN5KpzfE8d59neN1TKBJJZtI9+ZpWvmgV4UQOB3wvC8NN4N5mScwGKeIt62E7zQ1 u1mPSoDb30+RiN4VIDJfQdy7GPIso98d1U+YaeKp5JnqCqPIPz6qzlP3Sv8aMmA71Mnd GprY3SP4Cvpmvr4ZtgpQSnDFp+5vDuAXFLMcIB3eYY7fanFJ8CmKdvtp7NvnC12nUPra suBOZ/pgAFJMcjCCoFeq4gUhVqKVeOibhEbeRToY5t3WbYmwte1K94vYi9LS0izwUZ2S LuDFH59qzEogQcFEfqUiv+aguADPZPaM5EVC/gHHi+P9CjlUHCpFCaiNXjDxbgf8U+Pf 1taQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=k16PQBXt9q9uOtxHm8JlnMyaHL4qmIeiuhgTg+Wmsps=; b=fEST3C9EAqkwGBF37V/+UwJ7Z9kL3gLPRG9mkcmEiagFkliK2Vw3k0xaDVzH69pXq5 DqGpxfpGUJ+EBuTJAtUhosFVdMeSpDsYMGMylFWdSGurxwgwMziNXwH3jTtPHF1HKhb3 Vr5I4ZBI188+O1m0Myrm/vBosS/ZxlkfxWTiTBBf/7l2rbP/GHPP8YRuffv77vG2kzqQ +n+k0mBvpCzONhmhCagYaLD0AdSaS/3P9TVDhPmn3SQSyFArEf/umdX8khWNIyvAQA4R yH+k/vkWroFJiMlydBIQSc3iwAb/wV2cJLmilSyDlL5F9+HXdosEIAQDNO/cxZmeiUix QUXw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bFN0pwhg; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.92.50.105]) by smtp.gmail.com with ESMTPSA id o4sm4153485wrq.66.2018.12.18.13.29.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Dec 2018 13:29:34 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Tao Ren Subject: [PATCH 17/25] clocksource/drivers/fttmr010: Fix invalid interrupt register access Date: Tue, 18 Dec 2018 22:28:35 +0100 Message-Id: <20181218212844.30445-17-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181218212844.30445-1-daniel.lezcano@linaro.org> References: <20181218212844.30445-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tao Ren TIMER_INTR_MASK register (Base Address of Timer + 0x38) is not designed for masking interrupts on ast2500 chips, and it's not even listed in ast2400 datasheet, so it's not safe to access TIMER_INTR_MASK on aspeed chips. Similarly, TIMER_INTR_STATE register (Base Address of Timer + 0x34) is not interrupt status register on ast2400 and ast2500 chips. Although there is no side effect to reset the register in fttmr010_common_init(), it's just misleading to do so. Besides, "count_down" is renamed to "is_aspeed" in "fttmr010" structure, and more comments are added so the code is more readble. Signed-off-by: Tao Ren Reviewed-by: Linus Walleij Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-fttmr010.c | 73 ++++++++++++++++------------ 1 file changed, 42 insertions(+), 31 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/timer-fttmr010.c b/drivers/clocksource/timer-fttmr010.c index cf93f6419b51..fadff7915dd9 100644 --- a/drivers/clocksource/timer-fttmr010.c +++ b/drivers/clocksource/timer-fttmr010.c @@ -21,7 +21,7 @@ #include /* - * Register definitions for the timers + * Register definitions common for all the timer variants. */ #define TIMER1_COUNT (0x00) #define TIMER1_LOAD (0x04) @@ -36,9 +36,10 @@ #define TIMER3_MATCH1 (0x28) #define TIMER3_MATCH2 (0x2c) #define TIMER_CR (0x30) -#define TIMER_INTR_STATE (0x34) -#define TIMER_INTR_MASK (0x38) +/* + * Control register (TMC30) bit fields for fttmr010/gemini/moxart timers. + */ #define TIMER_1_CR_ENABLE BIT(0) #define TIMER_1_CR_CLOCK BIT(1) #define TIMER_1_CR_INT BIT(2) @@ -53,8 +54,9 @@ #define TIMER_3_CR_UPDOWN BIT(11) /* - * The Aspeed AST2400 moves bits around in the control register - * and lacks bits for setting the timer to count upwards. + * Control register (TMC30) bit fields for aspeed ast2400/ast2500 timers. + * The aspeed timers move bits around in the control register and lacks + * bits for setting the timer to count upwards. */ #define TIMER_1_CR_ASPEED_ENABLE BIT(0) #define TIMER_1_CR_ASPEED_CLOCK BIT(1) @@ -66,6 +68,18 @@ #define TIMER_3_CR_ASPEED_CLOCK BIT(9) #define TIMER_3_CR_ASPEED_INT BIT(10) +/* + * Interrupt status/mask register definitions for fttmr010/gemini/moxart + * timers. + * The registers don't exist and they are not needed on aspeed timers + * because: + * - aspeed timer overflow interrupt is controlled by bits in Control + * Register (TMC30). + * - aspeed timers always generate interrupt when either one of the + * Match registers equals to Status register. + */ +#define TIMER_INTR_STATE (0x34) +#define TIMER_INTR_MASK (0x38) #define TIMER_1_INT_MATCH1 BIT(0) #define TIMER_1_INT_MATCH2 BIT(1) #define TIMER_1_INT_OVERFLOW BIT(2) @@ -80,7 +94,7 @@ struct fttmr010 { void __iomem *base; unsigned int tick_rate; - bool count_down; + bool is_aspeed; u32 t1_enable_val; struct clock_event_device clkevt; #ifdef CONFIG_ARM @@ -130,7 +144,7 @@ static int fttmr010_timer_set_next_event(unsigned long cycles, cr &= ~fttmr010->t1_enable_val; writel(cr, fttmr010->base + TIMER_CR); - if (fttmr010->count_down) { + if (fttmr010->is_aspeed) { /* * ASPEED Timer Controller will load TIMER1_LOAD register * into TIMER1_COUNT register when the timer is re-enabled. @@ -175,16 +189,17 @@ static int fttmr010_timer_set_oneshot(struct clock_event_device *evt) /* Setup counter start from 0 or ~0 */ writel(0, fttmr010->base + TIMER1_COUNT); - if (fttmr010->count_down) + if (fttmr010->is_aspeed) { writel(~0, fttmr010->base + TIMER1_LOAD); - else + } else { writel(0, fttmr010->base + TIMER1_LOAD); - /* Enable interrupt */ - cr = readl(fttmr010->base + TIMER_INTR_MASK); - cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2); - cr |= TIMER_1_INT_MATCH1; - writel(cr, fttmr010->base + TIMER_INTR_MASK); + /* Enable interrupt */ + cr = readl(fttmr010->base + TIMER_INTR_MASK); + cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2); + cr |= TIMER_1_INT_MATCH1; + writel(cr, fttmr010->base + TIMER_INTR_MASK); + } return 0; } @@ -201,9 +216,8 @@ static int fttmr010_timer_set_periodic(struct clock_event_device *evt) writel(cr, fttmr010->base + TIMER_CR); /* Setup timer to fire at 1/HZ intervals. */ - if (fttmr010->count_down) { + if (fttmr010->is_aspeed) { writel(period, fttmr010->base + TIMER1_LOAD); - writel(0, fttmr010->base + TIMER1_MATCH1); } else { cr = 0xffffffff - (period - 1); writel(cr, fttmr010->base + TIMER1_COUNT); @@ -281,23 +295,21 @@ static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed) } /* - * The Aspeed AST2400 moves bits around in the control register, - * otherwise it works the same. + * The Aspeed timers move bits around in the control register. */ if (is_aspeed) { fttmr010->t1_enable_val = TIMER_1_CR_ASPEED_ENABLE | TIMER_1_CR_ASPEED_INT; - /* Downward not available */ - fttmr010->count_down = true; + fttmr010->is_aspeed = true; } else { fttmr010->t1_enable_val = TIMER_1_CR_ENABLE | TIMER_1_CR_INT; - } - /* - * Reset the interrupt mask and status - */ - writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK); - writel(0, fttmr010->base + TIMER_INTR_STATE); + /* + * Reset the interrupt mask and status + */ + writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK); + writel(0, fttmr010->base + TIMER_INTR_STATE); + } /* * Enable timer 1 count up, timer 2 count up, except on Aspeed, @@ -306,9 +318,8 @@ static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed) if (is_aspeed) val = TIMER_2_CR_ASPEED_ENABLE; else { - val = TIMER_2_CR_ENABLE; - if (!fttmr010->count_down) - val |= TIMER_1_CR_UPDOWN | TIMER_2_CR_UPDOWN; + val = TIMER_2_CR_ENABLE | TIMER_1_CR_UPDOWN | + TIMER_2_CR_UPDOWN; } writel(val, fttmr010->base + TIMER_CR); @@ -321,7 +332,7 @@ static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed) writel(0, fttmr010->base + TIMER2_MATCH1); writel(0, fttmr010->base + TIMER2_MATCH2); - if (fttmr010->count_down) { + if (fttmr010->is_aspeed) { writel(~0, fttmr010->base + TIMER2_LOAD); clocksource_mmio_init(fttmr010->base + TIMER2_COUNT, "FTTMR010-TIMER2", @@ -371,7 +382,7 @@ static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed) #ifdef CONFIG_ARM /* Also use this timer for delays */ - if (fttmr010->count_down) + if (fttmr010->is_aspeed) fttmr010->delay_timer.read_current_timer = fttmr010_read_current_timer_down; else From patchwork Tue Dec 18 21:28:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 154186 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4203147ljp; Tue, 18 Dec 2018 13:29:42 -0800 (PST) X-Google-Smtp-Source: AFSGD/WIZhYV2h1iOG7DgrtgQbjg+9x8SVVxNKOpgw4rBhAwEEux54BAmvkSg5oOQlY6S5Bq9glK X-Received: by 2002:a62:55c4:: with SMTP id j187mr13907027pfb.129.1545168582181; Tue, 18 Dec 2018 13:29:42 -0800 (PST) ARC-Seal: i=1; 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[92.92.50.105]) by smtp.gmail.com with ESMTPSA id o4sm4153485wrq.66.2018.12.18.13.29.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Dec 2018 13:29:36 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Anson Huang , Anson Huang Subject: [PATCH 18/25] clocksource/drivers/timer-imx-tpm: Specify clock name for timer-of Date: Tue, 18 Dec 2018 22:28:36 +0100 Message-Id: <20181218212844.30445-18-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181218212844.30445-1-daniel.lezcano@linaro.org> References: <20181218212844.30445-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Anson Huang i.MX TPM needs "ipg" clock for register access and "per" clock for timer function, the driver gets "ipg" clock by searching the clock name, but timer-of initialization will get first clock in device tree TPM node since no clock name specified in of_clk, that means the "per" clock MUST be the first clock entry in device tree TPM node, this patch specifies clock name for of_clk to avoid this restriction, it makes TPM driver work properly with different sequence of clock entries in device tree TPM node. Signed-off-by: Anson Huang Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-imx-tpm.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.17.1 diff --git a/drivers/clocksource/timer-imx-tpm.c b/drivers/clocksource/timer-imx-tpm.c index c3dd4d2f2a6e..c1d52d5264c2 100644 --- a/drivers/clocksource/timer-imx-tpm.c +++ b/drivers/clocksource/timer-imx-tpm.c @@ -139,6 +139,9 @@ static struct timer_of to_tpm = { .handler = tpm_timer_interrupt, .flags = IRQF_TIMER | IRQF_IRQPOLL, }, + .of_clk = { + .name = "per", + }, }; static int __init tpm_clocksource_init(void) From patchwork Tue Dec 18 21:28:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 154194 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4203722ljp; Tue, 18 Dec 2018 13:30:23 -0800 (PST) X-Google-Smtp-Source: AFSGD/X07N6vqyuArE259SxqKuX8zVh68dqpzYhMpvlKFGBaGziKT4H9dX3Vg8Yuh3qvbruu8M/X X-Received: by 2002:a62:cec6:: with SMTP id y189mr4516506pfg.100.1545168623565; Tue, 18 Dec 2018 13:30:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545168623; cv=none; d=google.com; s=arc-20160816; b=wtwLEbL5LrTUjA6YCYPG+1A1BYWudgfd/NFnOCAxu+lxCcD1JmhSDo1dWd++fveJn3 I1AdfRr6XN/HAX64IanEXJBEiK0PuwNnKb68nlIABVtClZdiz+0up1IOwV0aJwH1QXTk VyyCo7OVQdcl8eOVRQ9AFsljmxVr0rYA/DQuR2DgGNHBE617cHaZZgs4IXUlD6r6WI4T xCz+zUE/Djonc+FxKMCna961s92E0+Hj4C05rBeDILEUIJzAAy4OjTMQE8PFEZ4SkfGE 3GbqqcFbhim7Ng3UQIE+SGWkKeRgUqRLtiJ30Hk+SMFVWGlghMaVjpLjrH663epS4m5F aIVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=HuxNRSLo1Y/SD7lAUX6QeRhvOXk945RDrLuI7e8huwc=; b=X34jpLhA/qj/rtDqnBmXz8ACBbaT0RdXD1RIXCtoLm5EHSWUkJDoFfZEO/jqFbYfgN ARq/5Zo+qLXDFmi13N5SjCeoD1ocg3hh/TsL5dO01wZV2RVG0SgVtPMq32pr+0ISA8y+ Y9G9f3hnCJOja0AGlvKE9mH1bFnvVh5Itz1Mm2QwgaRxxZ6bZd/SGZbmey1zOJBLtR4C 9eVmknR3N79SUQh5zm9olC9Xcna7LejRvQFKV/NyAXNCWqJgy680QSq2k5w8gu/PxqQR eitCIC1bc99+9wYuM790+kJvICwG500NionYYWkAhrJnShsbov9lf05nBZRITmItdsvE 3QAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=atusBLcC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.92.50.105]) by smtp.gmail.com with ESMTPSA id o4sm4153485wrq.66.2018.12.18.13.29.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Dec 2018 13:29:38 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Anup Patel , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org (open list:RISC-V ARCHITECTURE) Subject: [PATCH 19/25] clocksource/drivers/riscv_timer: Provide the sched_clock Date: Tue, 18 Dec 2018 22:28:37 +0100 Message-Id: <20181218212844.30445-19-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181218212844.30445-1-daniel.lezcano@linaro.org> References: <20181218212844.30445-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Anup Patel Currently, we don't have a sched_clock registered for RISC-V systems. This means Linux time keeping will use jiffies (running at HZ) as the default sched_clock. To avoid this, we explicity provide sched_clock using RISC-V rdtime instruction (similar to riscv_timer clocksource). Signed-off-by: Anup Patel Reviewed-by: Palmer Dabbelt Signed-off-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 2 +- drivers/clocksource/riscv_timer.c | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index c57b156f49a2..a4ae339e0101 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -599,7 +599,7 @@ config ATCPIT100_TIMER config RISCV_TIMER bool "Timer for the RISC-V platform" - depends on RISCV + depends on GENERIC_SCHED_CLOCK && RISCV default y select TIMER_PROBE select TIMER_OF diff --git a/drivers/clocksource/riscv_timer.c b/drivers/clocksource/riscv_timer.c index 084e97dc10ed..431892200a08 100644 --- a/drivers/clocksource/riscv_timer.c +++ b/drivers/clocksource/riscv_timer.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -49,6 +50,11 @@ static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs) return get_cycles64(); } +static u64 riscv_sched_clock(void) +{ + return get_cycles64(); +} + static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = { .name = "riscv_clocksource", .rating = 300, @@ -97,6 +103,9 @@ static int __init riscv_timer_init_dt(struct device_node *n) cs = per_cpu_ptr(&riscv_clocksource, cpuid); clocksource_register_hz(cs, riscv_timebase); + sched_clock_register(riscv_sched_clock, + BITS_PER_LONG, riscv_timebase); + error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING, "clockevents/riscv/timer:starting", riscv_timer_starting_cpu, riscv_timer_dying_cpu); From patchwork Tue Dec 18 21:28:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 154188 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4203218ljp; Tue, 18 Dec 2018 13:29:46 -0800 (PST) X-Google-Smtp-Source: AFSGD/XL0XpLq+NLVkvCCbL11v7kQjkd8gx1LyiMcs+f+0yycTk7vj1Yd0sGidXyTwEK8DOI/dCy X-Received: by 2002:a63:fd53:: with SMTP id m19mr711441pgj.340.1545168586596; Tue, 18 Dec 2018 13:29:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545168586; cv=none; d=google.com; s=arc-20160816; b=MJeS0D9tLK60xXuhDggFuPj5qcrAuwC3OjtnuSfWwLs3tRwUB0GHznRiRYza0A3xwk yQ4gB9qYVN2IHB6f4hFkMzdBjFva7CEE9xDsKaVm26METxGbJZnArc0/peeLyNnJIi27 o69n2NkQThcLCV4LmvjglEeoj2zx0X5k7oh84kGAiMtThN+3RTk9qnrDX/QIWGLJ/PJm pLVVbuq+EitU8sCqOo8C+RiGKOtWTRDH/0EXu2v3oSJMVWLEOTUCe/yEUqjMSDXIY5Yg sEmTo0Jwjm1WUcUY+y2nM9Tn8sMSpxs/wSvVa5U4jjIYJ7VO8GqYn6Nd4DCDAFodPyiP iwNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=EQh4Wy4xg4tu3G5mjMUe7R/MpSc7Nf6V6BJXMW/ceAY=; b=O3O5SOs6HYyhz2saLOldfwojQBWPJkmxwOk3BlGtqmm7V7QEsv8m0A7xGyQjunYhW9 VNNmRvyvJsU8LI8ckA28GRU0sk0Fv5Azm36ZjdHcBfyVlYTt9gTh8XiLsR9iavexHZF9 b1XC1cC7pOM8OzrgIrvUny4phEhFgzA2hpXYTDJC1Q+R2rL5CnH85yUUCOI3SPiJ1x9O T4FZ9kvr9LWRVJCkiRFeOTO+I1q42zF7HZove12f9u9ZAhzy54BWJuedC5QjFAwR7UgF CsPv3BOWVMiI3ECWMiFySdE4Buz+KuRH+AfEScuMSRc2yxKMHyJy/MgJ+fz1/+EQawKE HrPA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ajm80HsT; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.92.50.105]) by smtp.gmail.com with ESMTPSA id o4sm4153485wrq.66.2018.12.18.13.29.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Dec 2018 13:29:39 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org (open list:RISC-V ARCHITECTURE) Subject: [PATCH 20/25] clocksource/drivers/riscv: Change name riscv_timer to timer-riscv Date: Tue, 18 Dec 2018 22:28:38 +0100 Message-Id: <20181218212844.30445-20-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181218212844.30445-1-daniel.lezcano@linaro.org> References: <20181218212844.30445-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In order to unify the names in this directory, let's rename the driver to be prefixed with timer-* Reviewed-by: Palmer Dabbelt Signed-off-by: Daniel Lezcano --- drivers/clocksource/Makefile | 2 +- drivers/clocksource/{riscv_timer.c => timer-riscv.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename drivers/clocksource/{riscv_timer.c => timer-riscv.c} (100%) -- 2.17.1 diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index dd9138104568..ddf697b29df9 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -78,6 +78,6 @@ obj-$(CONFIG_H8300_TPU) += h8300_tpu.o obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o obj-$(CONFIG_X86_NUMACHIP) += numachip.o obj-$(CONFIG_ATCPIT100_TIMER) += timer-atcpit100.o -obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o +obj-$(CONFIG_RISCV_TIMER) += timer-riscv.o obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o diff --git a/drivers/clocksource/riscv_timer.c b/drivers/clocksource/timer-riscv.c similarity index 100% rename from drivers/clocksource/riscv_timer.c rename to drivers/clocksource/timer-riscv.c From patchwork Tue Dec 18 21:28:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 154193 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4203565ljp; Tue, 18 Dec 2018 13:30:12 -0800 (PST) X-Google-Smtp-Source: AFSGD/V+cKKzfNjhMEd9t/4wPYGcqZMXMGcZHJdYmPJjKBnPNslQ4NrS+LoXPojI9eNeJLrw9Hk2 X-Received: by 2002:a63:2109:: with SMTP id h9mr17096432pgh.277.1545168612321; Tue, 18 Dec 2018 13:30:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545168612; cv=none; d=google.com; s=arc-20160816; b=adLgzrDvruxEmVFlSt0c8+akBMxKibAvh1Xi5UZyJDpGC9g4eOd/weJpILamPQkCaz qnoO2vYvm149nlYq2M9iIRH5oyFOTNruQ5BR3iYSwrPhx/wWiJXLOPLQtzMjugPfYFUy nEDQ32etQCefpWLNBYfpNqHkhlfJAuijikjJgqTEFEaMU/lx+fSvgkeNJCu0SVbn6pSm LoUCUp7lx7rA7facbPFwRUvfORdU58WKaFsuGdgrWuMwPtQwSC7RIfXgpEvNPfu6+vkj 1JnClhrcxd1ooKoU7gKwXKS59uxorOzLwGTGNzlvJJcNnNTr6RYhdNgsDuSlxzE68RX5 egzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=Ortts1jeLglmGDZSNPMXJ+Gydp1wITIqzfWnCQEmT+Q=; b=0gtXiEFjiAT7u20gKE209ax2Y2S5X4cThb+3KuIOhcmdMITonaoz2yc/7PB7jBkvY2 EgZJtcER2IfgfNzuWWkVpj91oe0/bJaXfdy+f3dss7iy5LrnTbb0xMFn0ploPVb9Y8Se tjR3zdokk8WcINPGn2woeWcyrsTbIrTIbvQJHkGb1HltcykBBrqbIztLfqvaW2ZSol/F Eb7TfSsF+GNldLgW6ab07Q8zBNsHNtP41DVm5XVOuNkdF1upeoSX2t3pTxthfDhyi8jq i3qw1/bJ7VxbzCOmgX58bXYgp0DuqriQgeaEBOGXs+eQXtMhEz1YclylhD8HPw4e+jGW FGAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JV1PTNuh; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.92.50.105]) by smtp.gmail.com with ESMTPSA id o4sm4153485wrq.66.2018.12.18.13.29.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Dec 2018 13:29:41 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org Subject: [PATCH 21/25] clocksource/drivers/rockchip: Change name rockchip_timer to timer-rockchip Date: Tue, 18 Dec 2018 22:28:39 +0100 Message-Id: <20181218212844.30445-21-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181218212844.30445-1-daniel.lezcano@linaro.org> References: <20181218212844.30445-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In order to unify the names in this directory, let's rename the driver to be prefixed with timer-* Signed-off-by: Daniel Lezcano --- drivers/clocksource/Makefile | 2 +- drivers/clocksource/{rockchip_timer.c => timer-rockchip.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename drivers/clocksource/{rockchip_timer.c => timer-rockchip.c} (100%) -- 2.17.1 diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index ddf697b29df9..9d0c0fa0d69b 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -20,7 +20,7 @@ obj-$(CONFIG_OMAP_DM_TIMER) += timer-ti-dm.o obj-$(CONFIG_DW_APB_TIMER) += dw_apb_timer.o obj-$(CONFIG_DW_APB_TIMER_OF) += dw_apb_timer_of.o obj-$(CONFIG_FTTMR010_TIMER) += timer-fttmr010.o -obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o +obj-$(CONFIG_ROCKCHIP_TIMER) += timer-rockchip.o obj-$(CONFIG_CLKSRC_NOMADIK_MTU) += nomadik-mtu.o obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o obj-$(CONFIG_ARMADA_370_XP_TIMER) += timer-armada-370-xp.o diff --git a/drivers/clocksource/rockchip_timer.c b/drivers/clocksource/timer-rockchip.c similarity index 100% rename from drivers/clocksource/rockchip_timer.c rename to drivers/clocksource/timer-rockchip.c From patchwork Tue Dec 18 21:28:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 154191 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4203399ljp; Tue, 18 Dec 2018 13:30:01 -0800 (PST) X-Google-Smtp-Source: AFSGD/VNrfznf81FpVbmZ/8k6Z0LzePggLNVma9Au5sYIQ1WYZxpCJJmR1Zlhqx9QESaI5IMU4yS X-Received: by 2002:a17:902:b406:: with SMTP id x6mr17060865plr.329.1545168600989; Tue, 18 Dec 2018 13:30:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545168600; cv=none; d=google.com; s=arc-20160816; b=Xxag0xlQm1iO+k1+JTG5SAIcTXU4SA60i5Zlo6zSLTI8U9vDAn08M2faaKnNjZN+5V fj/DOFHKEujuBjRU3nGWosVYJJYh56jkS/3gAp5ovfYJRg1B3zDCYtLMEWhJJwfs81GO eq3JY7ZCUnIxrAk6ylEkYudteA/HScQw7O9r+dmATtKWEdEuRJtBy81D0WbmZMWUgtFZ T11+uvaipy0i0sDa/AmnXw1fv8azgyUQLKxUze8HhQv7dlq9PlArdVN961WyKLmouYuZ N7vgF/zUPA3l6zKxqjbNNewGHSt4+OuIll0HXyfdlo2G/U4g0ruVDAd5Xti2YgrzBcNl FlkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=Lh3sCoQnHdMfpD8fOEoK0bAy5YMLicHLNk46Xrw66/8=; b=S1C6QJrSAFuHHi2DQRrEXvEKDssnOHH1RpenPoD262V/mFJxe03phW9Ix63TSuZ10c pkR9vaRq0uGwFhkkNfSHa8rGdeQoFQmRPgnObPkBIh1wURw/wwlSt73NJBGmlbrHDotS 2zPMqL3DGvz9yimkhcXvWuXkVM1GSZ5QAqvIWYvN20COtZTIAAQq7fk6Lo6G9BWMsXCV 6ScXIG5MXXoJNfa54N9iMf3uKEdtLaNKRddDbakf13WtaXra18Ol3G8KBr9/YaHNgwGL Py1E9043s8tMiG9dSkiDv10WIP8LCRGUeMMfXVdS4uVA3t5JGwbLMykUPZGFJ/dgR7xu +OKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fyl+vxoT; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.92.50.105]) by smtp.gmail.com with ESMTPSA id o4sm4153485wrq.66.2018.12.18.13.29.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Dec 2018 13:29:42 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org Subject: [PATCH 22/25] clocksource/drivers/tegra20: Change name tegra20_timer to timer-tegra20 Date: Tue, 18 Dec 2018 22:28:40 +0100 Message-Id: <20181218212844.30445-22-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181218212844.30445-1-daniel.lezcano@linaro.org> References: <20181218212844.30445-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In order to unify the names in this directory, let's rename the driver to be prefixed with timer-* Signed-off-by: Daniel Lezcano --- drivers/clocksource/Makefile | 2 +- drivers/clocksource/{tegra20_timer.c => timer-tegra20.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename drivers/clocksource/{tegra20_timer.c => timer-tegra20.c} (100%) -- 2.17.1 diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 9d0c0fa0d69b..e02c1af0c716 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -35,7 +35,7 @@ obj-$(CONFIG_U300_TIMER) += timer-u300.o obj-$(CONFIG_SUN4I_TIMER) += sun4i_timer.o obj-$(CONFIG_SUN5I_HSTIMER) += timer-sun5i.o obj-$(CONFIG_MESON6_TIMER) += meson6_timer.o -obj-$(CONFIG_TEGRA_TIMER) += tegra20_timer.o +obj-$(CONFIG_TEGRA_TIMER) += timer-tegra20.o obj-$(CONFIG_VT8500_TIMER) += timer-vt8500.o obj-$(CONFIG_NSPIRE_TIMER) += timer-zevio.o obj-$(CONFIG_BCM_KONA_TIMER) += bcm_kona_timer.o diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/timer-tegra20.c similarity index 100% rename from drivers/clocksource/tegra20_timer.c rename to drivers/clocksource/timer-tegra20.c From patchwork Tue Dec 18 21:28:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 154189 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4203294ljp; Tue, 18 Dec 2018 13:29:52 -0800 (PST) X-Google-Smtp-Source: AFSGD/XG4ruWuRLWlAtJSf8gANpYrsmhKgbtAEI0z/KUYwoYToh3iPfJNEhPji1UkHup1BttzYOs X-Received: by 2002:a62:1c0a:: with SMTP id c10mr2871053pfc.213.1545168592382; Tue, 18 Dec 2018 13:29:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545168592; cv=none; d=google.com; s=arc-20160816; b=fTTJK5Y3r3lT+JiBrFpd5T0ra8O/4jGTFNj1tmrjUvUzoTHDlRKJik0M7vr+ErEA5L xK/uR/lV6Ir4UjHtLeW94eRDBQVjNKMExGbuS0wElPJ9XoH/CJTqPoVSYMTHQyBH27Te P2M4qL5uZCFl1zwEIUFyURm2His87kt5Tk90/wn/sAbO3+63DKmDQpFlz3I32pA5S9/U AChowJ1+OE0sX8lJP2isfPga+Bl5rubBnSJ//gVw0f7H3OOzyCh0P6+5AxSJz8rL8d5P q+BZTIM7Q8kGPDJOzsc/+4Tf4PDTnW+smle1kasETeEVoVjlv3xVJDuSi2KZ3VzgQCeO 9Puw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=Gb4QAzm/KkE/XU1ketpNUvqBhzZcGDx6YZBMsdzWQdg=; b=Ere8IWQTzAolL2V2kF1hud+nsHx4/wVrdr2hCpKB0hWc4JpBRlfdqZnNogUquf4CBD LNWz4hn1D9YHZhTuldpsM9X7UtKQgCnrRqbpBdh3MEaQNq06IiE8ZH3VHldL5ubSJNNu qApU2yeHVy+Ooa7Y22rSt1jooyhhwmiF/d9LzT4yqOy4YAQOHtENnqn4U2w8dia6WUJJ 7HcXBe5q2QJtFLEYC46nEwPZvdxaAPlwpavbz3tvpzz5/os4rurv7ZhAuWsxfQYOPZO5 1dkoOJrQMtUhtE/Pt5y9bRigmxdS+XY4XKOs17Fk52O+AxVP1MS94jZsJzfEaLGN1Ld2 1eTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NveSwk6Q; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.92.50.105]) by smtp.gmail.com with ESMTPSA id o4sm4153485wrq.66.2018.12.18.13.29.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Dec 2018 13:29:43 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org Subject: [PATCH 23/25] clocksource/drivers/sun4i: Change name sun4i_timer to timer-sun4i Date: Tue, 18 Dec 2018 22:28:41 +0100 Message-Id: <20181218212844.30445-23-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181218212844.30445-1-daniel.lezcano@linaro.org> References: <20181218212844.30445-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In order to unify the names in this directory, let's rename the driver to be prefixed with timer-* Signed-off-by: Daniel Lezcano --- drivers/clocksource/Makefile | 2 +- drivers/clocksource/{sun4i_timer.c => timer-sun4i.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename drivers/clocksource/{sun4i_timer.c => timer-sun4i.c} (100%) -- 2.17.1 diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index e02c1af0c716..37732cb5710c 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -32,7 +32,7 @@ obj-$(CONFIG_MXS_TIMER) += mxs_timer.o obj-$(CONFIG_CLKSRC_PXA) += pxa_timer.o obj-$(CONFIG_PRIMA2_TIMER) += timer-prima2.o obj-$(CONFIG_U300_TIMER) += timer-u300.o -obj-$(CONFIG_SUN4I_TIMER) += sun4i_timer.o +obj-$(CONFIG_SUN4I_TIMER) += timer-sun4i.o obj-$(CONFIG_SUN5I_HSTIMER) += timer-sun5i.o obj-$(CONFIG_MESON6_TIMER) += meson6_timer.o obj-$(CONFIG_TEGRA_TIMER) += timer-tegra20.o diff --git a/drivers/clocksource/sun4i_timer.c b/drivers/clocksource/timer-sun4i.c similarity index 100% rename from drivers/clocksource/sun4i_timer.c rename to drivers/clocksource/timer-sun4i.c From patchwork Tue Dec 18 21:28:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 154192 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4203434ljp; Tue, 18 Dec 2018 13:30:03 -0800 (PST) X-Google-Smtp-Source: AFSGD/WaIMFdbggHmyjrltjFCOwflDwvtdkaZ4DYUXWOf4srlWYgnntD0iAGoeMhQ2EFli8h7dgT X-Received: by 2002:a17:902:3124:: with SMTP id w33mr18091532plb.241.1545168603723; Tue, 18 Dec 2018 13:30:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545168603; cv=none; d=google.com; s=arc-20160816; b=vkHAO+s1fIXpDqDkSHb5RuOtteCjmVGmUKnV534aU14KiGJaa5Qcq6Ki7eN4y0LUfD 8ELKAXF8dWZdll+XKdl9lI7drxvzEifzBuJAKshcj2tPzYpcwkKILwlqDF4hCkjrPceg qHpqRczB65Uub1rlUogMoSppJNU+0bH5nFBKbYyvUPXp/ZGD/xJHTmEkgngnBNSRRoF9 7QWZsKNCJAVQQz+8X4/o1PkhBpXPVCrJ4ZTXVp69jOoTUgOhq6t5E9y+is2DORJDM9LA fqEwGFqfplslOJDTUBBl/S+Ll4RMUZlVXA9RUpz3fjixSvfuVpBaxbFTha+CqwvSxdfd qaSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=qjdnO2DNnqjz1/W8KEFUahSKSMHQuREy7uvLbg+oEK0=; b=H2x93Oew3rTqz3dMiafzDoIgSBVlhoj1Vcgp1uU8ro94tYaKxKpO0qZeyjK+8AeMiz zG6TxWd54o3f85w12jrjYNzolLjLIPocSJrsLAu2TioAHTTo9k5gDh0om6TZDNNVw6pf Ao9gOokBAnGO8tXIoI54j5k4k9kChOzUfgIr1BmjNmsWORDzNLIcJCh4QWFxHQ8a7iko iZDnYCRR/VbANDk+BacZcLdUAvAqa961u2yW77fg6twS8IQABeNZcTWhCYd5mr/uCF+2 EAnd2zUscoSQtz5zYpDvHhRLE7q2gWQ+yBoJEcB2KAUUyFvrW2pYDkIzCpEqahEzyvpi BE5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NhWBv41U; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.92.50.105]) by smtp.gmail.com with ESMTPSA id o4sm4153485wrq.66.2018.12.18.13.29.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Dec 2018 13:29:45 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org Subject: [PATCH 24/25] clocksource/drivers/meson6: Change name meson6_timer timer-meson6 Date: Tue, 18 Dec 2018 22:28:42 +0100 Message-Id: <20181218212844.30445-24-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181218212844.30445-1-daniel.lezcano@linaro.org> References: <20181218212844.30445-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In order to unify the names in this directory, let's rename the driver to be prefixed with timer-* Signed-off-by: Daniel Lezcano --- drivers/clocksource/Makefile | 2 +- drivers/clocksource/{meson6_timer.c => timer-meson6.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename drivers/clocksource/{meson6_timer.c => timer-meson6.c} (100%) -- 2.17.1 diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 37732cb5710c..f475927d5140 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -34,7 +34,7 @@ obj-$(CONFIG_PRIMA2_TIMER) += timer-prima2.o obj-$(CONFIG_U300_TIMER) += timer-u300.o obj-$(CONFIG_SUN4I_TIMER) += timer-sun4i.o obj-$(CONFIG_SUN5I_HSTIMER) += timer-sun5i.o -obj-$(CONFIG_MESON6_TIMER) += meson6_timer.o +obj-$(CONFIG_MESON6_TIMER) += timer-meson6.o obj-$(CONFIG_TEGRA_TIMER) += timer-tegra20.o obj-$(CONFIG_VT8500_TIMER) += timer-vt8500.o obj-$(CONFIG_NSPIRE_TIMER) += timer-zevio.o diff --git a/drivers/clocksource/meson6_timer.c b/drivers/clocksource/timer-meson6.c similarity index 100% rename from drivers/clocksource/meson6_timer.c rename to drivers/clocksource/timer-meson6.c From patchwork Tue Dec 18 21:28:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 154190 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4203336ljp; Tue, 18 Dec 2018 13:29:56 -0800 (PST) X-Google-Smtp-Source: AFSGD/UBUUDSL3sj4xU89Ak4L7h9d/1xoFDjWA/269UBIalHclX6Zs6ZXMG0cTxfokbv4zkonpv0 X-Received: by 2002:a62:220d:: with SMTP id i13mr17985628pfi.162.1545168596449; Tue, 18 Dec 2018 13:29:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545168596; cv=none; d=google.com; s=arc-20160816; b=Pa1ZY8CRwLdAr4GiPeAcKwEyoBlDZMvcpZblnYNKxZk0Hw8ipDG5/zLcHa6P5n7iGP hmG/bW+aE2agHUn11cZODAHQIBDL7Bb4r/Iin/BfPd1cF9MgcK8zya9uEmORpXVscGii JrAtWsXTwGcH8qP6i/NRo5djj5fVDpCDUOnT5ty1J8GrXkP3OPfUnT1fbp1nBFa2PDCa PMbTZbzCZACuXZYWyy4AeOVV0HtRAqLWiysbRioRj4KKen0QdgEqiK4SB5XhqUd0DUyb gjnwKGi3hkT9X8aCOH6+mlDP+7nS8DK99QukupQFW3XzV+4W3F2eYVqdnWlsI17H8V2G 8TMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9na8wrimAOJy2qcVvWt2fiFxxnkVPKFvxqnrSeY6pZQ=; b=RilV/zQ04ruZ07Ez92e6mVWNHQoPIzf/E9oR7AdKVZNDMa0lHDT6XyJ5Oiiswt7xLH LhvBwbeP5LHewELNEWRHsOrFg+EoVe04tuZbEyYnnmOiaqretMCDn3UZrJv+w0w7JYno 0T8VBdjN/jW4g+p1Oj5tt/oY1zy6odHbzzJvL6CvB7r0Qxk5/+JOf9ZmbNGpiYhfiICe BJ3Ga3AcnTJTxkPXzGHN0tNa1RAWciqblxN8PGqIL1o8qnJsZjaMpJ5mBmdiSjSR74wb YPR0Nh78J9yUkL/wFMh7h/wddttXQ2KWip2IcsNYPkwuxEogjxjd96a6ZXu/L+t189YQ aa3g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="i/DFQRJY"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.92.50.105]) by smtp.gmail.com with ESMTPSA id o4sm4153485wrq.66.2018.12.18.13.29.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Dec 2018 13:29:50 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Manivannan Sadhasivam , =?utf-8?q?Andreas_F=C3=A4rber?= Subject: [PATCH 25/25] clocksource/drivers/rda: Add clock driver for RDA8810PL SoC Date: Tue, 18 Dec 2018 22:28:43 +0100 Message-Id: <20181218212844.30445-25-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181218212844.30445-1-daniel.lezcano@linaro.org> References: <20181218212844.30445-1-daniel.lezcano@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Manivannan Sadhasivam Add clock driver for RDA Micro RDA8810PL SoC supporting OSTIMER and HWTIMER. RDA8810PL has two independent timers: OSTIMER (56 bit) and HWTIMER (64 bit). Each timer provides optional interrupt support. In this driver, OSTIMER is used for clockevents and HWTIMER is used for clocksource. Signed-off-by: Andreas Färber Signed-off-by: Manivannan Sadhasivam Signed-off-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 8 ++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-rda.c | 195 ++++++++++++++++++++++++++++++++ 3 files changed, 204 insertions(+) create mode 100644 drivers/clocksource/timer-rda.c -- 2.17.1 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index a4ae339e0101..a9e26f6a81a1 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -105,6 +105,14 @@ config OWL_TIMER help Enables the support for the Actions Semi Owl timer driver. +config RDA_TIMER + bool "RDA timer driver" if COMPILE_TEST + depends on GENERIC_CLOCKEVENTS + select CLKSRC_MMIO + select TIMER_OF + help + Enables the support for the RDA Micro timer driver. + config SUN4I_TIMER bool "Sun4i timer driver" if COMPILE_TEST depends on HAS_IOMEM diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index f475927d5140..cdd210ff89ea 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -57,6 +57,7 @@ obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o obj-$(CONFIG_OWL_TIMER) += timer-owl.o obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o obj-$(CONFIG_NPCM7XX_TIMER) += timer-npcm7xx.o +obj-$(CONFIG_RDA_TIMER) += timer-rda.o obj-$(CONFIG_ARC_TIMERS) += arc_timer.o obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o diff --git a/drivers/clocksource/timer-rda.c b/drivers/clocksource/timer-rda.c new file mode 100644 index 000000000000..fd1199c189bf --- /dev/null +++ b/drivers/clocksource/timer-rda.c @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * RDA8810PL SoC timer driver + * + * Copyright RDA Microelectronics Company Limited + * Copyright (c) 2017 Andreas Färber + * Copyright (c) 2018 Manivannan Sadhasivam + * + * RDA8810PL has two independent timers: OSTIMER (56 bit) and HWTIMER (64 bit). + * Each timer provides optional interrupt support. In this driver, OSTIMER is + * used for clockevents and HWTIMER is used for clocksource. + */ + +#include +#include + +#include "timer-of.h" + +#define RDA_OSTIMER_LOADVAL_L 0x000 +#define RDA_OSTIMER_CTRL 0x004 +#define RDA_HWTIMER_LOCKVAL_L 0x024 +#define RDA_HWTIMER_LOCKVAL_H 0x028 +#define RDA_TIMER_IRQ_MASK_SET 0x02c +#define RDA_TIMER_IRQ_MASK_CLR 0x030 +#define RDA_TIMER_IRQ_CLR 0x034 + +#define RDA_OSTIMER_CTRL_ENABLE BIT(24) +#define RDA_OSTIMER_CTRL_REPEAT BIT(28) +#define RDA_OSTIMER_CTRL_LOAD BIT(30) + +#define RDA_TIMER_IRQ_MASK_OSTIMER BIT(0) + +#define RDA_TIMER_IRQ_CLR_OSTIMER BIT(0) + +static int rda_ostimer_start(void __iomem *base, bool periodic, u64 cycles) +{ + u32 ctrl, load_l; + + load_l = (u32)cycles; + ctrl = ((cycles >> 32) & 0xffffff); + ctrl |= RDA_OSTIMER_CTRL_LOAD | RDA_OSTIMER_CTRL_ENABLE; + if (periodic) + ctrl |= RDA_OSTIMER_CTRL_REPEAT; + + /* Enable ostimer interrupt first */ + writel_relaxed(RDA_TIMER_IRQ_MASK_OSTIMER, + base + RDA_TIMER_IRQ_MASK_SET); + + /* Write low 32 bits first, high 24 bits are with ctrl */ + writel_relaxed(load_l, base + RDA_OSTIMER_LOADVAL_L); + writel_relaxed(ctrl, base + RDA_OSTIMER_CTRL); + + return 0; +} + +static int rda_ostimer_stop(void __iomem *base) +{ + /* Disable ostimer interrupt first */ + writel_relaxed(RDA_TIMER_IRQ_MASK_OSTIMER, + base + RDA_TIMER_IRQ_MASK_CLR); + + writel_relaxed(0, base + RDA_OSTIMER_CTRL); + + return 0; +} + +static int rda_ostimer_set_state_shutdown(struct clock_event_device *evt) +{ + struct timer_of *to = to_timer_of(evt); + + rda_ostimer_stop(timer_of_base(to)); + + return 0; +} + +static int rda_ostimer_set_state_oneshot(struct clock_event_device *evt) +{ + struct timer_of *to = to_timer_of(evt); + + rda_ostimer_stop(timer_of_base(to)); + + return 0; +} + +static int rda_ostimer_set_state_periodic(struct clock_event_device *evt) +{ + struct timer_of *to = to_timer_of(evt); + unsigned long cycles_per_jiffy; + + rda_ostimer_stop(timer_of_base(to)); + + cycles_per_jiffy = ((unsigned long long)NSEC_PER_SEC / HZ * + evt->mult) >> evt->shift; + rda_ostimer_start(timer_of_base(to), true, cycles_per_jiffy); + + return 0; +} + +static int rda_ostimer_tick_resume(struct clock_event_device *evt) +{ + return 0; +} + +static int rda_ostimer_set_next_event(unsigned long evt, + struct clock_event_device *ev) +{ + struct timer_of *to = to_timer_of(ev); + + rda_ostimer_start(timer_of_base(to), false, evt); + + return 0; +} + +static irqreturn_t rda_ostimer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = dev_id; + struct timer_of *to = to_timer_of(evt); + + /* clear timer int */ + writel_relaxed(RDA_TIMER_IRQ_CLR_OSTIMER, + timer_of_base(to) + RDA_TIMER_IRQ_CLR); + + if (evt->event_handler) + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct timer_of rda_ostimer_of = { + .flags = TIMER_OF_IRQ | TIMER_OF_BASE, + + .clkevt = { + .name = "rda-ostimer", + .rating = 250, + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | + CLOCK_EVT_FEAT_DYNIRQ, + .set_state_shutdown = rda_ostimer_set_state_shutdown, + .set_state_oneshot = rda_ostimer_set_state_oneshot, + .set_state_periodic = rda_ostimer_set_state_periodic, + .tick_resume = rda_ostimer_tick_resume, + .set_next_event = rda_ostimer_set_next_event, + }, + + .of_base = { + .name = "rda-timer", + .index = 0, + }, + + .of_irq = { + .name = "ostimer", + .handler = rda_ostimer_interrupt, + .flags = IRQF_TIMER, + }, +}; + +static u64 rda_hwtimer_read(struct clocksource *cs) +{ + void __iomem *base = timer_of_base(&rda_ostimer_of); + u32 lo, hi; + + /* Always read low 32 bits first */ + do { + lo = readl_relaxed(base + RDA_HWTIMER_LOCKVAL_L); + hi = readl_relaxed(base + RDA_HWTIMER_LOCKVAL_H); + } while (hi != readl_relaxed(base + RDA_HWTIMER_LOCKVAL_H)); + + return ((u64)hi << 32) | lo; +} + +static struct clocksource rda_hwtimer_clocksource = { + .name = "rda-timer", + .rating = 400, + .read = rda_hwtimer_read, + .mask = CLOCKSOURCE_MASK(64), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static int __init rda_timer_init(struct device_node *np) +{ + unsigned long rate = 2000000; + int ret; + + ret = timer_of_init(np, &rda_ostimer_of); + if (ret) + return ret; + + clocksource_register_hz(&rda_hwtimer_clocksource, rate); + + clockevents_config_and_register(&rda_ostimer_of.clkevt, rate, + 0x2, UINT_MAX); + + return 0; +} + +TIMER_OF_DECLARE(rda8810pl, "rda,8810pl-timer", rda_timer_init);