From patchwork Tue Dec 18 21:59:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 154204 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4226261ljp; Tue, 18 Dec 2018 14:00:19 -0800 (PST) X-Google-Smtp-Source: AFSGD/XHWF6BDvN56DvstsmFvTwcOWTty11TqN5qj4SNhsqbwu57Z5cHzDi3b6yNrXiyp/nOHmWY X-Received: by 2002:a17:902:bd4a:: with SMTP id b10mr18052543plx.232.1545170419269; Tue, 18 Dec 2018 14:00:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545170419; cv=none; d=google.com; s=arc-20160816; b=A8RCyfmpWzOxCCBguoG1wvu5QOIT8Q6XffEiQbkWRb/Vxz8Gm2bktXzuVP5QUksZLN bEXNi408exlKn33wudWcZYNJ5ZK398eNZWOorCdki9r8sT3enKVX6OdSDZjKbYuFFP6p DYbtX3xaN0SpxRN8qzPAWfwKFH9cLo2wyfYTo6zXwdFLXWcQAv3wzs4PPxzyPXw6QNvn 4BIav3neP8kaDMe28HDm+qtcie3uohuDdPWNiVrVaShpAP6nkFCjKa4XRfHbWimM8lsd iE2aCJhqs7wxcOLwqno5wMkEpDNof1hb6Xcadh9m2RV5NVs6EEscvEqPzWKDyeH6fVQo D2ng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tpqz4ACGIOtLM4HqS4NAXeXkX30klbBq1A6Ib2bKOio=; b=bOIcvGPxTslkXQi+idqSKi2ZckMAYR0lAkfJwnY0cwhK3d4ftDeCsnCuafjy6xHjQU RXweSkCo0Arq0KOz2pjqN1zxUKBLyJUs1wLeCfGrDCRFaMpFfQQi7gb+cVeugyyZfm9R sQB77ZlPSVo1nIPt/4QRYDsAlNdxCRI+uh8WUIiW/EQJ/tUNk/LwHCpDITC5o4qzp5bK xg8eEF1GLPR5bOKZzS1jfoBus2/fwpq9qYx0XoZX8vns5Lq4t3Hj5C0dtNR/HFC32Gp7 mIHBxjDtXLFGzI6d8LtbWlUGd0AEHAmzst3HJ09VhaJpvlcAUw6aRUhDK1dbVbJquU7U gjyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="i/fRFzCT"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n125si15383919pga.179.2018.12.18.14.00.18; Tue, 18 Dec 2018 14:00:19 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="i/fRFzCT"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727477AbeLRWAS (ORCPT + 31 others); Tue, 18 Dec 2018 17:00:18 -0500 Received: from mail-wm1-f65.google.com ([209.85.128.65]:52904 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727140AbeLRWAO (ORCPT ); Tue, 18 Dec 2018 17:00:14 -0500 Received: by mail-wm1-f65.google.com with SMTP id m1so4160992wml.2 for ; Tue, 18 Dec 2018 14:00:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tpqz4ACGIOtLM4HqS4NAXeXkX30klbBq1A6Ib2bKOio=; b=i/fRFzCTgNABf8zdGWGdJ9qTQ/YRneT6VnI104ffcCY6zdAhclR4fP95jE555PBLps pRay398khSraRt1yZZ8zJ6habJBovOhERqypu2StNAVRl74nbo8PlIqYoNRzTCtohesr 7ICA16Yva22BBhf51cb4PWBT/c3oexETyhDFA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tpqz4ACGIOtLM4HqS4NAXeXkX30klbBq1A6Ib2bKOio=; b=uYRSD+T03JDZ8RCQi3/jTm3SidZMuLVr9iRAvi0+DpjDV8sjjFLAmoN9Wbp+9eyafS p9CxHKRW6Q27J4O7i5+eCD7kuMnWRYl03maU3sT/nN/78KIo0E72buprfS+972fgStoZ eXpRjlrlPkgg1sbHTmF7y/g816myQKEIACxy4WC2gMbNXm6ZR8pKeXblB00b2xZOX1Ma cMRGsNSJFI474gyFJbD9w2wXlIWVET5i01GjqN1BXCpEpzpJpRaw0uwO+S/icqUwRTnD avZgVGV+aqM2D4xgLkvYW4KLxFkGeeFXmQjKXbwKnk9105Me0LeULPLdIiSfGEXzzcJS IfSA== X-Gm-Message-State: AA+aEWak3+vw85NLgTdoCopVa/RPPlN1/ytGVFB8j6vvfVWwTFBeTFOO W0VgmIVzlgcSxiCLoOksNly3/hT74K4= X-Received: by 2002:a1c:7fca:: with SMTP id a193mr4805082wmd.36.1545170413140; Tue, 18 Dec 2018 14:00:13 -0800 (PST) Received: from linaro.org ([2a00:23c5:6815:3901:cf0e:17bd:f425:fac3]) by smtp.gmail.com with ESMTPSA id x76sm7449158wmd.27.2018.12.18.14.00.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Dec 2018 14:00:12 -0800 (PST) From: Mike Leach To: mike.leach@linaro.org, linux@armlinux.org.uk Cc: mathieu.poirier@linaro.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [RESEND PATCH v3 1/2] drivers: amba: Updates to component identification for driver matching. Date: Tue, 18 Dec 2018 21:59:43 +0000 Message-Id: <20181218215944.2444-2-mike.leach@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181218215944.2444-1-mike.leach@linaro.org> References: <20181218215944.2444-1-mike.leach@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The CoreSight specification (ARM IHI 0029E), updates the ID register requirements for components on an AMBA bus, to cover both traditional ARM Primecell type devices, and newer CoreSight and other components. The Peripheral ID (PID) / Component ID (CID) pair is extended in certain cases to uniquely identify components. CoreSight components related to a single function can share Peripheral ID values, and must be further identified using a Unique Component Identifier (UCI). e.g. the ETM, CTI, PMU and Debug hardware of the A35 all share the same PID. Bits 15:12 of the CID are defined to be the device class. Class 0xF remains for PrimeCell and legacy components. Class 0x9 defines the component as CoreSight (CORESIGHT_CID above) Class 0x0, 0x1, 0xB, 0xE define components that do not have driver support at present. Class 0x2-0x8,0xA and 0xD-0xD are presently reserved. The specification futher defines which classes of device use the standard CID/PID pair, and when additional ID registers are required. The patches provide an update of amba_device and matching code to handle the additional registers required for the Class 0x9 (CoreSight) UCI. The *data pointer in the amba_id is used by the driver to provide extended ID register values for matching. CoreSight components where PID/CID pair is currently sufficient for unique identification need not provide this additional information. Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier --- drivers/amba/bus.c | 45 +++++++++++++++++++++++++++++++++------- include/linux/amba/bus.h | 32 ++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+), 8 deletions(-) -- 2.19.1 Reviewed-by: Suzuki K Poulose Tested-by: Sai Prakash Ranjan diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c index 41b706403ef7..524296a0eba0 100644 --- a/drivers/amba/bus.c +++ b/drivers/amba/bus.c @@ -26,19 +26,36 @@ #define to_amba_driver(d) container_of(d, struct amba_driver, drv) -static const struct amba_id * -amba_lookup(const struct amba_id *table, struct amba_device *dev) +/* called on periphid match and class 0x9 coresight device. */ +static int +amba_cs_uci_id_match(const struct amba_id *table, struct amba_device *dev) { int ret = 0; + struct amba_cs_uci_id *uci; + + uci = table->data; + /* no table data - return match on periphid */ + if (!uci) + return 1; + + /* test against read devtype and masked devarch value */ + ret = (dev->uci.devtype == uci->devtype) && + ((dev->uci.devarch & uci->devarch_mask) == uci->devarch); + return ret; +} + +static const struct amba_id * +amba_lookup(const struct amba_id *table, struct amba_device *dev) +{ while (table->mask) { - ret = (dev->periphid & table->mask) == table->id; - if (ret) - break; + if (((dev->periphid & table->mask) == table->id) && + ((dev->cid != CORESIGHT_CID) || + (amba_cs_uci_id_match(table, dev)))) + return table; table++; } - - return ret ? table : NULL; + return NULL; } static int amba_match(struct device *dev, struct device_driver *drv) @@ -399,10 +416,22 @@ static int amba_device_try_add(struct amba_device *dev, struct resource *parent) cid |= (readl(tmp + size - 0x10 + 4 * i) & 255) << (i * 8); + if (cid == CORESIGHT_CID) { + /* set the base to the start of the last 4k block */ + void __iomem *csbase = tmp + size - 4096; + + dev->uci.devarch = + readl(csbase + UCI_REG_DEVARCH_OFFSET); + dev->uci.devtype = + readl(csbase + UCI_REG_DEVTYPE_OFFSET) & 0xff; + } + amba_put_disable_pclk(dev); - if (cid == AMBA_CID || cid == CORESIGHT_CID) + if (cid == AMBA_CID || cid == CORESIGHT_CID) { dev->periphid = pid; + dev->cid = cid; + } if (!dev->periphid) ret = -ENODEV; diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h index d143c13bed26..8c0f392e4da2 100644 --- a/include/linux/amba/bus.h +++ b/include/linux/amba/bus.h @@ -25,6 +25,36 @@ #define AMBA_CID 0xb105f00d #define CORESIGHT_CID 0xb105900d +/* + * CoreSight Architecture specification updates the ID specification + * for components on the AMBA bus. (ARM IHI 0029E) + * + * Bits 15:12 of the CID are the device class. + * + * Class 0xF remains for PrimeCell and legacy components. (AMBA_CID above) + * Class 0x9 defines the component as CoreSight (CORESIGHT_CID above) + * Class 0x0, 0x1, 0xB, 0xE define components that do not have driver support + * at present. + * Class 0x2-0x8,0xA and 0xD-0xD are presently reserved. + * + * Remaining CID bits stay as 0xb105-00d + */ + +/* + * Class 0x9 components use additional values to form a Unique Component + * Identifier (UCI), where peripheral ID values are identical for different + * components. Passed to the amba bus code from the component driver via + * the amba_id->data pointer. + */ +struct amba_cs_uci_id { + unsigned int devarch; + unsigned int devarch_mask; + unsigned int devtype; +}; + +#define UCI_REG_DEVTYPE_OFFSET 0xFCC +#define UCI_REG_DEVARCH_OFFSET 0xFBC + struct clk; struct amba_device { @@ -32,6 +62,8 @@ struct amba_device { struct resource res; struct clk *pclk; unsigned int periphid; + unsigned int cid; + struct amba_cs_uci_id uci; unsigned int irq[AMBA_NR_IRQS]; char *driver_override; }; From patchwork Tue Dec 18 21:59:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 154205 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4226277ljp; Tue, 18 Dec 2018 14:00:20 -0800 (PST) X-Google-Smtp-Source: AFSGD/UvPTaFGDz4LCQ2RXovHrF8mMrq1kRASXnzWY3m8AcpgLUY7NXE1bLACU+jMlVrYTVQwoNu X-Received: by 2002:a63:2d82:: with SMTP id t124mr17135498pgt.260.1545170420105; Tue, 18 Dec 2018 14:00:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545170420; cv=none; d=google.com; s=arc-20160816; b=B5vDLBpX6aCffdAcRmlc2AOvupmDxld9r74kr65HNGyWF2rF+0wRCI0fJgC6Jiuvof qRZlU/2bwpPDZSYT45q11d997ab/FCA8XvQUe9UcrcY5CprHirJvvD1p9YhduGX9cr/V 7LmrQI3nfZoIUgyka0l7y0jqG8D5p9T99epds4w13o2HYUysFNEf0NDiFxhgrzOe56rf +nMm6NsEc6u7zO8rfYMGmIyfeHixAuDKpMUObK7FySiqg9bJyyA918Y0B7kd3tn7bnnb MyD6Cl6Ishopu6a9HdRuYsadUfhTzHAD4NPH3FOhEPldRV+EQTFQx2TM41OAggCZbEer X0Gw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ydSAlnd72VkQ6lGpPSCbYq4vE2P1PydjacJOrhz/zN0=; b=P6IOs4sO0uPIVIXo1jx7rv3Ga3v9kLPpfJHAlqgzeHqUiuG7FhejP8ETaAXNhzojN/ b2k0k4CuHRsmcWFsqWNR8bfsT9RbUavUGtPf+Z1qYU8jjLk7Wuwi4XxPLnKBDIcSXVYW bNkwH5exSyaLBpV64hsvSHhFNVSx64MQR+K4iH9EMnlAkgjM/eCKll+SFvmZue5qtZ7X yTkvT8CgocZfvIV+RNm7FtWtwKn76O2TbVpU6XIcFl2lo6wXybRFtDbegd82eV5HfOEN JZtb1pShl+PveHFRom7cneXNkwLufC0aEysWA29DPXsbxLQAYWkGyOYTfEIwl2CMnEsd G9pw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="jRIUyLp/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 4si14230911pla.299.2018.12.18.14.00.19; Tue, 18 Dec 2018 14:00:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="jRIUyLp/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727498AbeLRWAS (ORCPT + 31 others); Tue, 18 Dec 2018 17:00:18 -0500 Received: from mail-wr1-f66.google.com ([209.85.221.66]:43806 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726559AbeLRWAQ (ORCPT ); Tue, 18 Dec 2018 17:00:16 -0500 Received: by mail-wr1-f66.google.com with SMTP id r10so17461360wrs.10 for ; Tue, 18 Dec 2018 14:00:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ydSAlnd72VkQ6lGpPSCbYq4vE2P1PydjacJOrhz/zN0=; b=jRIUyLp/4QHRrny9LWddhWAJID7GF7mlDFGuK2DnWoswCv7oSP10H/WQBrHtf9JYve dakU/umJ5DqsjpHY0X7DjOIWA3ATFeMt4kItii6TFazvHROYMg1NAZNsdjtxu8ja8eH/ ukVCXTHZYrYzF5ISBZ6jUyVKuTLvWgbUhMtsc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ydSAlnd72VkQ6lGpPSCbYq4vE2P1PydjacJOrhz/zN0=; b=WVtbtK0CBkGcZmNMlIO1ci4D20K6vCVum7HTduaTwoCoNECUslb8QK+xP9pY4sagTK 31KQ7/duofkV2ozrGNO+82SHuoqk1ZISEOxJp/8e7F4aMHMVHs+36ZIkDuu1ZDYfX5vE UU87vOVcd7JKeZx084jjAB3PY0I5UOgziogiKZ6iUaZGzt1M6/AF9ZWaVwhg3Cjx71BQ kyK9WF+kktwDIHej+4y4mZX23E1UeF/ybO/ngCNaddxYGGu4eSUUD6+DkcbVAzVUvMID sUC8CZrRm8hzN3NrIijVH+4fCPRIfs1cxC/86T2jFVujO35tarH6iF5iyubNAC+Ot90t GbHw== X-Gm-Message-State: AA+aEWaRtxL288UQX7N4RAf/wF8iaIQwunqK4fzGoQSjdb4Ti4Dy6kSr Wc3PpHs9RApjw8/TYmEzzmR42Q== X-Received: by 2002:a5d:68c3:: with SMTP id p3mr16815373wrw.34.1545170414485; Tue, 18 Dec 2018 14:00:14 -0800 (PST) Received: from linaro.org ([2a00:23c5:6815:3901:cf0e:17bd:f425:fac3]) by smtp.gmail.com with ESMTPSA id x76sm7449158wmd.27.2018.12.18.14.00.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Dec 2018 14:00:13 -0800 (PST) From: Mike Leach To: mike.leach@linaro.org, linux@armlinux.org.uk Cc: mathieu.poirier@linaro.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [RESEND PATCH v3 2/2] coresight: etmv4: Update ID register table to add UCI support Date: Tue, 18 Dec 2018 21:59:44 +0000 Message-Id: <20181218215944.2444-3-mike.leach@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181218215944.2444-1-mike.leach@linaro.org> References: <20181218215944.2444-1-mike.leach@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Updates the ID register tables to contain a UCI entry for the A35 ETM device to allow correct matching of driver in the amba bus code. Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm4x.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) -- 2.19.1 Reviewed-by: Suzuki K Poulose diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 53e2fb6e86f6..2fb8054e43ab 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1073,12 +1073,28 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) .mask = 0x000fffff, \ } +static struct amba_cs_uci_id uci_id_etm4[] = { + { + /* ETMv4 UCI data */ + .devarch = 0x47704a13, + .devarch_mask = 0xfff0ffff, + .devtype = 0x00000013, + } +}; + +#define ETM4x_AMBA_UCI_ID(pid) \ + { \ + .id = pid, \ + .mask = 0x000fffff, \ + .data = uci_id_etm4, \ + } + static const struct amba_id etm4_ids[] = { ETM4x_AMBA_ID(0x000bb95d), /* Cortex-A53 */ ETM4x_AMBA_ID(0x000bb95e), /* Cortex-A57 */ ETM4x_AMBA_ID(0x000bb95a), /* Cortex-A72 */ ETM4x_AMBA_ID(0x000bb959), /* Cortex-A73 */ - ETM4x_AMBA_ID(0x000bb9da), /* Cortex-A35 */ + ETM4x_AMBA_UCI_ID(0x000bb9da), /* Cortex-A35 */ {}, };