From patchwork Wed Dec 19 11:03:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 154251 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4800574ljp; Wed, 19 Dec 2018 03:07:13 -0800 (PST) X-Google-Smtp-Source: AFSGD/XVOOLEpsT2lTXbFgQoJ5KfD2uwSamJy57UlQKq7PIWa8INSp0OPN9lbqjARGgXkam0rDWw X-Received: by 2002:a50:b0e5:: with SMTP id j92mr18378862edd.188.1545217633752; Wed, 19 Dec 2018 03:07:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545217633; cv=none; d=google.com; s=arc-20160816; b=kjfN7lQp/diECOSYXp0foSOcDl1M4nbn/FDkSXIl3771eatEjHrY61WtHPVNYReVae nnX9cGXwpzouK2wOwpoV1zsj9qRDFBG579bcbK66faPF+IxM/o5R6f7AQXN/ccnI68/n ndyJTNPQd+zCiIypa97Llh6t9BVE5TEPxUqDY0lmFa80Kct9FPDYyMTKiuvAQFXD6hd0 KHqtA8tppSD3sMUm+88cqYB9uIhrIOi8u40Oco/V01kpqW7FS17uqkt2GEDYdqumBkAL RymC7Lhy1nbpyIpoC/Y4OkYUqDLsi4RmR6gpnpy7HftfeXQutEahNpBh1FA+rRyOC304 AtHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:dkim-filter; bh=sYeiX0g8Bf/cmMz1DQZmx82mDmrBnC2FwU/vNXjriRU=; b=bs/PEu8lCb9R/KWx9lQXG84JGbGX9oBHdB5t2v8FM9ag4RKdm1WVqDPWIIp7sqEOQ4 7bO24yUevgJ5mPVTy9ci5pUG3at4l+0nNeqFK77i9BZovYYCnyf1EEDKhSqWGVGHy4ce +pP8mz+UPS2loJjFRN5eQNYS71/zxDTiIunoo4Izwt3bftA0gA0eaNyEgEY67y/gSojj BQFPdZI9ou/o+toMgFZWPNdOQWsB3nTnC3+f2FmI+B0+J/KwpfVroFMqcUehIm45rL2F MMU20OIGhWGIt+geue/4Cgj7rwN+sPGP4ALkSMGeV2/BzBScjwXmpguvSbzGgVoFvV40 4Ajw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b="JI/Oid02"; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id k11-v6si2602200ejb.269.2018.12.19.03.07.13; Wed, 19 Dec 2018 03:07:13 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b="JI/Oid02"; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 60F3CC220AF; Wed, 19 Dec 2018 11:05:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 67F5CC220BA; Wed, 19 Dec 2018 11:04:11 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 76C88C21F49; Wed, 19 Dec 2018 11:04:01 +0000 (UTC) Received: from conuserg-09.nifty.com (conuserg-09.nifty.com [210.131.2.76]) by lists.denx.de (Postfix) with ESMTPS id A0923C22086 for ; Wed, 19 Dec 2018 11:03:57 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id wBJB3SMK001192; Wed, 19 Dec 2018 20:03:29 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com wBJB3SMK001192 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1545217409; bh=z6cP0LHcC788toJ9DNSTXjYYFqdBCWNtOOnbXufiDrE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JI/Oid024XH4yAjuMUxLegHj+sM2bSAONWxveniKZ1r9Yw1qvpZ1gCSi/nAEPCVNO X5auRt7p5WvOtOUagKOUa20JlsOPAWcSKaMk7UmRhv/SxwjgGfYmGRUV6QTrzB+d4L xW8wX/pf0J3st08pS5xhm/88XHpDVWWwJBQ0cvP7ugwxpR5Sk4LAdYJDZyzZ+qMU99 SSI4yz5UpWAFd+oiBeCRoNsU1SYzzINDTbBkyYoan8lJWMAVhNVrtKElTuAgJW5vDz PNY9mzgcDmgQiOhKOPIo7tK3vKzfifoNv3+EGmyGVmQAEhqqgjXJnZ6jgs7LRDM2S9 Hyql24MwfOMnw== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Wed, 19 Dec 2018 20:03:13 +0900 Message-Id: <1545217401-27018-2-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1545217401-27018-1-git-send-email-yamada.masahiro@socionext.com> References: <1545217401-27018-1-git-send-email-yamada.masahiro@socionext.com> Cc: Tom Rini Subject: [U-Boot] [PATCH 1/9] ARM: uniphier: do not modify bootcmd environment variable at run-time X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Some users might want to modify 'bootcmd' at compile-time by editing include/configs/uniphier.h, but overwriting it at run-time makes it impossible. Instead, set 'bootdev' at run-time, which contains the boot device the system is booting from, then indirectly reference it from 'bootcmd'. It is up to users whether to override 'bootcmd'. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/board_late_init.c | 8 ++++---- configs/uniphier_ld4_sld8_defconfig | 1 + configs/uniphier_v7_defconfig | 1 + configs/uniphier_v8_defconfig | 1 + include/configs/uniphier.h | 4 ++++ 5 files changed, 11 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c index 1b871c6..972dbe8 100644 --- a/arch/arm/mach-uniphier/board_late_init.c +++ b/arch/arm/mach-uniphier/board_late_init.c @@ -66,20 +66,20 @@ int board_late_init(void) switch (uniphier_boot_device_raw()) { case BOOT_DEVICE_MMC1: printf("eMMC Boot"); - env_set("bootcmd", "run bootcmd_mmc0; run distro_bootcmd"); + env_set("bootdev", "emmc"); break; case BOOT_DEVICE_NAND: printf("NAND Boot"); - env_set("bootcmd", "run bootcmd_ubifs0; run distro_bootcmd"); + env_set("bootdev", "nand"); nand_denali_wp_disable(); break; case BOOT_DEVICE_NOR: printf("NOR Boot"); - env_set("bootcmd", "run tftpboot; run distro_bootcmd"); + env_set("bootdev", "nor"); break; case BOOT_DEVICE_USB: printf("USB Boot"); - env_set("bootcmd", "run bootcmd_usb0; run distro_bootcmd"); + env_set("bootdev", "usb"); break; default: printf("Unknown"); diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig index 6b9e22a..bede166 100644 --- a/configs/uniphier_ld4_sld8_defconfig +++ b/configs/uniphier_ld4_sld8_defconfig @@ -9,6 +9,7 @@ CONFIG_ARCH_UNIPHIER_LD4_SLD8=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_NR_DRAM_BANKS=3 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_BOOTCOMMAND="run ${bootdev}boot" CONFIG_LOGLEVEL=6 CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig index 4c06f27..be4ab7c 100644 --- a/configs/uniphier_v7_defconfig +++ b/configs/uniphier_v7_defconfig @@ -8,6 +8,7 @@ CONFIG_SPL=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_NR_DRAM_BANKS=3 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_BOOTCOMMAND="run ${bootdev}boot" CONFIG_LOGLEVEL=6 CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig index f8f9bdf..6f7c269 100644 --- a/configs/uniphier_v8_defconfig +++ b/configs/uniphier_v8_defconfig @@ -7,6 +7,7 @@ CONFIG_ARCH_UNIPHIER_V8_MULTI=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_NR_DRAM_BANKS=3 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_BOOTCOMMAND="run ${bootdev}boot" CONFIG_LOGLEVEL=6 CONFIG_CMD_CONFIG=y CONFIG_CMD_IMLS=y diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 70f8712..7d14c31 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -171,6 +171,10 @@ "initrd_high=0xffffffffffffffff\0" \ "scriptaddr=0x85000000\0" \ "nor_base=0x42000000\0" \ + "emmcboot=mmcsetn && run bootcmd_mmc${mmc_first_dev}\0" \ + "nandboot=run bootcmd_ubifs0\0" \ + "norboot=run tftpboot\0" \ + "usbboot=run bootcmd_usb0\0" \ "sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \ "tftpboot $tmp_addr $second_image && " \ "setexpr tmp_addr $nor_base + 0x70000 && " \ From patchwork Wed Dec 19 11:03:14 2018 Content-Type: text/plain; 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If there is found a file 'boot.scr', run it before invoking the distro boot command. Signed-off-by: Masahiro Yamada --- configs/uniphier_ld4_sld8_defconfig | 2 +- configs/uniphier_v7_defconfig | 2 +- configs/uniphier_v8_defconfig | 2 +- include/configs/uniphier.h | 20 ++++++++++++++++++++ 4 files changed, 23 insertions(+), 3 deletions(-) diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig index bede166..98a0017 100644 --- a/configs/uniphier_ld4_sld8_defconfig +++ b/configs/uniphier_ld4_sld8_defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH_UNIPHIER_LD4_SLD8=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_NR_DRAM_BANKS=3 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set -CONFIG_BOOTCOMMAND="run ${bootdev}boot" +CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot" CONFIG_LOGLEVEL=6 CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig index be4ab7c..bba8e18 100644 --- a/configs/uniphier_v7_defconfig +++ b/configs/uniphier_v7_defconfig @@ -8,7 +8,7 @@ CONFIG_SPL=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_NR_DRAM_BANKS=3 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set -CONFIG_BOOTCOMMAND="run ${bootdev}boot" +CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot" CONFIG_LOGLEVEL=6 CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig index 6f7c269..df6c511 100644 --- a/configs/uniphier_v8_defconfig +++ b/configs/uniphier_v8_defconfig @@ -7,7 +7,7 @@ CONFIG_ARCH_UNIPHIER_V8_MULTI=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_NR_DRAM_BANKS=3 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set -CONFIG_BOOTCOMMAND="run ${bootdev}boot" +CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot" CONFIG_LOGLEVEL=6 CONFIG_CMD_CONFIG=y CONFIG_CMD_IMLS=y diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 7d14c31..1e509ce 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -169,12 +169,32 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "initrd_high=0xffffffffffffffff\0" \ + "script=boot.scr\0" \ "scriptaddr=0x85000000\0" \ "nor_base=0x42000000\0" \ "emmcboot=mmcsetn && run bootcmd_mmc${mmc_first_dev}\0" \ "nandboot=run bootcmd_ubifs0\0" \ "norboot=run tftpboot\0" \ "usbboot=run bootcmd_usb0\0" \ + "emmcscript=setenv devtype mmc && " \ + "mmcsetn && " \ + "setenv devnum ${mmc_first_dev} && " \ + "run loadscript_fat\0" \ + "nandscript=echo Running ${script} from ubi ... && " \ + "ubi part UBI && " \ + "ubifsmount ubi0:boot && " \ + "ubifsload ${loadaddr} ${script} && " \ + "source\0" \ + "norscript=echo Running ${script} from tftp ... && " \ + "tftpboot ${script} &&" \ + "source\0" \ + "usbscript=usb start && " \ + "setenv devtype usb && " \ + "setenv devnum 0 && " \ + "run loadscript_fat\0" \ + "loadscript_fat=echo Running ${script} from ${devtype}${devnum} ... && " \ + "load ${devtype} ${devnum}:1 ${loadaddr} ${script} && " \ + "source\0" \ "sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \ "tftpboot $tmp_addr $second_image && " \ "setexpr tmp_addr $nor_base + 0x70000 && " \ From patchwork Wed Dec 19 11:03:15 2018 Content-Type: text/plain; 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Wed, 19 Dec 2018 11:04:20 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E7F37C21FA0; Wed, 19 Dec 2018 11:04:01 +0000 (UTC) Received: from conuserg-09.nifty.com (conuserg-09.nifty.com [210.131.2.76]) by lists.denx.de (Postfix) with ESMTPS id A2628C220D5 for ; Wed, 19 Dec 2018 11:03:57 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id wBJB3SMM001192; Wed, 19 Dec 2018 20:03:30 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com wBJB3SMM001192 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1545217410; bh=Fp7n7xkEf04Ny72CUfq5N4cmQoRgxes2HZ2rlLQWoyU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=0pwXwRCaoIBPteUo+z918Ol7i8YBy0GrWaEvGNplUhZ4oI1NsmW0lVYI0HsxUTEiR lTI7jrN0tbt5wgW4a9+kQ8vAU3lEpShVMSzJgc86XQElXXkmqEHK1r+0tVbEAE9n/w P4f3xNaxzCruFJMURzrVK85VNtF4QTuc/b8EHAYfKXQ1nmi3tM+wH4orRykRSg4KVy H/EPAaYy6fT9/Ks+FIV2R2yymeAcsEyTYHYu2A1lhWfpGNQZ4UqPFFa2Ef3KzwpLbr 5S09aQy0ejNdFdxevqElfCutUBDbv61F3zjS9qxqg/z48gKskSurGakClFIdPKkuli rswap5xcTqjhQ== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Wed, 19 Dec 2018 20:03:15 +0900 Message-Id: <1545217401-27018-4-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1545217401-27018-1-git-send-email-yamada.masahiro@socionext.com> References: <1545217401-27018-1-git-send-email-yamada.masahiro@socionext.com> Cc: Tom Rini Subject: [U-Boot] [PATCH 3/9] ARM: uniphier: add CONFIG_PREBOOT X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" For more boot-flow flexibility, Signed-off-by: Masahiro Yamada --- include/configs/uniphier.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 1e509ce..95d6452 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -124,6 +124,8 @@ "third_image=u-boot.bin\0" #endif +#define CONFIG_PREBOOT "env exist ${bootdev}preboot && run ${bootdev}preboot" + #define CONFIG_ROOTPATH "/nfs/root/path" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs $bootargs root=/dev/nfs rw " \ From patchwork Wed Dec 19 11:03:16 2018 Content-Type: text/plain; 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[81.169.180.215]) by mx.google.com with ESMTP id r6-v6si2068437eji.124.2018.12.19.03.06.54; Wed, 19 Dec 2018 03:06:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=PJC1g7Cq; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 154D2C2205E; Wed, 19 Dec 2018 11:04:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 25639C22063; Wed, 19 Dec 2018 11:03:50 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D6399C21F49; Wed, 19 Dec 2018 11:03:47 +0000 (UTC) Received: from conuserg-09.nifty.com (conuserg-09.nifty.com [210.131.2.76]) by lists.denx.de (Postfix) with ESMTPS id B1449C21F85 for ; Wed, 19 Dec 2018 11:03:46 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id wBJB3SMN001192; Wed, 19 Dec 2018 20:03:30 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com wBJB3SMN001192 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1545217411; bh=F429/uICNPUGjmLCpjKHMxON9r2P5LD14Kpt7fv0AUc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PJC1g7CqOo+SxwpHo+3WbVPY0orHpMqi1Xc14x9S7XbSUVmv/u/rsyQdTgHNqHvlN AgpjGC4Ld7zld3lgKkjj9gCQWPMLDyYDIcMU1wr6a54xfXBLxrmNQixpK+tLHiQr2I Q34zz32ko1ditXEhpaoCTRK/jhWAb6bc+QyFUZ7hpfR9G4zW6aEK4EA2ZDxPcye6kz +rDvWJkU73aqwLfhWDbaRBKmxE35yRlO0xw8LhEE7WKjPhXQsYLtkcZ5lcc0HlgGC7 81Hm8WY5YB2WerBmXF7+BthFtFy9pazdDwh5qnLS4u/5xKL0amiSHLvN+CW/TU0sIn Vk93HFKEdJ2xg== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Wed, 19 Dec 2018 20:03:16 +0900 Message-Id: <1545217401-27018-5-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1545217401-27018-1-git-send-email-yamada.masahiro@socionext.com> References: <1545217401-27018-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 4/9] linux/kernel.h: import DIV_ROUND_CLOSEST_ULL from Linux X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Copied from Linux v4.20-rc7. Signed-off-by: Masahiro Yamada --- include/linux/kernel.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/linux/kernel.h b/include/linux/kernel.h index bd88483..a85c15d 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h @@ -102,6 +102,18 @@ (((__x) - ((__d) / 2)) / (__d)); \ } \ ) +/* + * Same as above but for u64 dividends. divisor must be a 32-bit + * number. + */ +#define DIV_ROUND_CLOSEST_ULL(x, divisor)( \ +{ \ + typeof(divisor) __d = divisor; \ + unsigned long long _tmp = (x) + (__d) / 2; \ + do_div(_tmp, __d); \ + _tmp; \ +} \ +) /* * Multiplies an integer by a fraction, while avoiding unnecessary From patchwork Wed Dec 19 11:03:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 154253 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4801609ljp; Wed, 19 Dec 2018 03:08:09 -0800 (PST) X-Google-Smtp-Source: AFSGD/U5NWiymRjncNFPYzjdK8IUZ4Iy3uZYBIkZoNxKzIazaYV7DOHgDET/xlIF4BtDDrCt6IKl X-Received: by 2002:aa7:df07:: with SMTP id c7mr19561915edy.85.1545217689419; Wed, 19 Dec 2018 03:08:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545217689; cv=none; d=google.com; s=arc-20160816; b=Ej+XRW4gooENZz3ozrxgDnnQy2Nq74ypbulQaWD3R7mHMK179k7yP3vVEl70ixzEEV Of00EN4paxPQjD9g12dI/K8/fGXGkn9DjEjxMx9fbAbZXPd/TUhZ4yDB0U5xFuRsg50+ S76K2GqjTbNl1PajMiSxJzaUfmOvgHliSPTgT4oJeWguNQWlx8kwlF/dXhVY7kF0EYBK cOJSYiMFI/e3XLMiecnk6vWS+zD7AFYnZzMU8tMbJ7bh+kzl5MnmNDD2W6kjn5xuouys 8edzqGwCeobxKrHqRLByqKzHD6C8d8/zn+fpez6X4vyWP8WQq9qpvUrdrQbSghmimN1d f23A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:dkim-filter; bh=f9gjF6pneqctTeYX+t8D76E/CHa0Pkd+/bagTXjTA6w=; b=csWAKEzgCdWmK3zk52U0gNjFC85hW9XBkopCmSVc6gYn4UoZ1TBYSTpam/07bNT/fP 4bIKbg3/iUVAg42zAdlrJnnnTUIjEYI1Q6ExTNJDHGKtUEIGw63Ew+Ii5TO+Ry2WxYmB vbHC2xCj96nnSm/0d0/hluIJt3M+aOCxHiBg2jLRRJcy/qP386IIx/8HsY03uzd+74eX yTt9oWXt77CWzMQeF35Z5plLkDmFIVVcHe1TBplvdI5U7gQrJ4vDGGDJYPjLhhji0IUk lIPj6W/Q1Dl6AkReVDMyQJBaIdQPHirETYCyITK+xGqAz7ZlvPo6rJNLOfF3nruylwwJ Jm3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=q8nXZE37; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id z13-v6si2322955ejw.113.2018.12.19.03.08.09; Wed, 19 Dec 2018 03:08:09 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=q8nXZE37; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 0EAA6C21F85; Wed, 19 Dec 2018 11:05:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 9C960C22075; Wed, 19 Dec 2018 11:03:50 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E7E31C21EB4; Wed, 19 Dec 2018 11:03:47 +0000 (UTC) Received: from conuserg-09.nifty.com (conuserg-09.nifty.com [210.131.2.76]) by lists.denx.de (Postfix) with ESMTPS id A495DC21F49 for ; Wed, 19 Dec 2018 11:03:46 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id wBJB3SMO001192; Wed, 19 Dec 2018 20:03:31 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com wBJB3SMO001192 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1545217411; bh=wZfAZHAzS2eUfIfn3ZsjWgEB8Hk8ivMnltTOXclEsAk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=q8nXZE37wv3ALiy4kVin11Ji/v08bou/wlIQEmQ38JGtlql0dAbw7+i9B1fdnL3a4 C2TCd533yvu7YFAzCC5W1847jjawmwGjp2478VHTicuQ2m/XuIZr91HJC7kvqRVjFC Bnbtg/FAI8bSSUxuBW64I0oA21VhQr+mOseXtzz/6pXvGXX9pbPkHFRs3PPDvRkZ5x 19uHWxvqwyOcYzfCCTQm52oSfVA/krk8kv2gO/87VFOk+4tVwDwr2+57e0Pk/cL5Sl hAd8st2FFxliPx8pSIfbx2bO+eXRGzgotnCBzoOU4PXzdjK1S9chx0lWFU7Vmf62w2 +EdARAGIBv4Tg== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Wed, 19 Dec 2018 20:03:17 +0900 Message-Id: <1545217401-27018-6-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1545217401-27018-1-git-send-email-yamada.masahiro@socionext.com> References: <1545217401-27018-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 5/9] mtd: rawnand: denali_dt: add more clocks based on IP datasheet X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Based on Linux commit 6f1fe97bec349a1fd6c5a8c7c5998d759fe721d5 Currently, denali_dt.c requires a single anonymous clock, but the Denali User's Guide requires three clocks for this IP: - clk: controller core clock - clk_x: bus interface clock - ecc_clk: clock at which ECC circuitry is run This commit supports these named clocks to represent the real hardware. For the backward compatibility, the driver still accepts a single clock just as before. The clk_x_rate is taken from the clock driver again if the named clock "clk_x" is available. This will happen only for future DT, hence the existing DT files are not affected. Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/raw/denali_dt.c | 38 +++++++++++++++++++++++++++++++++++--- 1 file changed, 35 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index 65a7797..f9eadb4 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -62,7 +62,7 @@ static int denali_dt_probe(struct udevice *dev) { struct denali_nand_info *denali = dev_get_priv(dev); const struct denali_dt_data *data; - struct clk clk; + struct clk clk, clk_x, clk_ecc; struct resource res; int ret; @@ -87,15 +87,47 @@ static int denali_dt_probe(struct udevice *dev) denali->host = devm_ioremap(dev, res.start, resource_size(&res)); - ret = clk_get_by_index(dev, 0, &clk); + ret = clk_get_by_name(dev, "nand", &clk); + if (ret) + ret = clk_get_by_index(dev, 0, &clk); if (ret) return ret; + ret = clk_get_by_name(dev, "nand_x", &clk_x); + if (ret) + clk_x.dev = NULL; + + ret = clk_get_by_name(dev, "ecc", &clk_ecc); + if (ret) + clk_ecc.dev = NULL; + ret = clk_enable(&clk); if (ret) return ret; - denali->clk_x_rate = clk_get_rate(&clk); + if (clk_x.dev) { + ret = clk_enable(&clk_x); + if (ret) + return ret; + } + + if (clk_ecc.dev) { + ret = clk_enable(&clk_ecc); + if (ret) + return ret; + } + + if (clk_x.dev) { + denali->clk_x_rate = clk_get_rate(&clk_x); + } else { + /* + * Hardcode the clock rates for the backward compatibility. + * This works for both SOCFPGA and UniPhier. + */ + dev_notice(dev, + "necessary clock is missing. default clock rates are used.\n"); + denali->clk_x_rate = 200000000; + } return denali_init(denali); } From patchwork Wed Dec 19 11:03:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 154249 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4800136ljp; Wed, 19 Dec 2018 03:06:50 -0800 (PST) X-Google-Smtp-Source: AFSGD/XDJKc+7fGNJC2bMD/BqpdG/kCeE75o9Pj8Rj8WkzOwu7avD/xs9RyaSftt8Hfx4rTH4HdJ X-Received: by 2002:a17:906:2da2:: with SMTP id g2-v6mr12668157eji.189.1545217610173; Wed, 19 Dec 2018 03:06:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545217610; cv=none; d=google.com; s=arc-20160816; b=IEgbDIz4Osef5W2cC8+2nU34wn2KR9ckBEYqj4sNTXJUep9YT8n413vQhEmcOGcE1c 8MQr+a/meM3m+C43IGHIFTyEXPKz5hv2J7j5Q9Q1BAJ7HO+X7jt/PMcw4banw1pdBGHy 9tnNnSFx8l54pXpGht5CM7T0xD3OPe57Gwamg0ugrGIq9gsFJYGxy+sa1ElVTSj/1BGY rCd8WGINF9eQ+4Dvd3ITTYDzChfYY4EcdXVrRQi2ShUxAO2se2IUKErX93IVBznKDDm9 Cj+fwcgTMGvuiBGP33VfSExRlk3cmZIBif4R2CeJcjzoz2WdujsVWYjXjb4OuBLAuM0w 9X+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:dkim-filter; bh=SyHgNhQn+iErSuv3YmmVa4uqdC5KYjqDhPB/2vIHeMA=; b=PZWZLVcaXqKCWJ8ERgye+D2MpGGqtultuIKizBBtCKja5Zorb3AxPFUQyCR1G0+sbE /jizXQvwiCShVhZ/ZJkPE8nmGW9ccvroOCqP1UNvJKXRHReIeSHSgUdaHPku8pI8PoU0 +XKQmrA/yK6AmEFctnP8fQblAOId3drW5J/RrIz7bhzYuQLN3LM9JCUFHbc2wX/pTF0Z Yw8tnV17qRnvd6dOZ0F3woK9run1vi7BB8KKRcvGYLrf/0hpiavrESIi4whkujqio24z yMkTrWwGIFj7tGbqk6a+dIzy1CdE3kG/z74eyh6RVk3OGt9STO+TWrLQAUIQnjnQEoDd eVFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=YlrpL4Oq; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id p37si4444134edc.272.2018.12.19.03.06.49; Wed, 19 Dec 2018 03:06:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=YlrpL4Oq; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id C1CDBC22026; Wed, 19 Dec 2018 11:04:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 86405C2201F; Wed, 19 Dec 2018 11:03:49 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id BCFBCC21EF2; Wed, 19 Dec 2018 11:03:47 +0000 (UTC) Received: from conuserg-09.nifty.com (conuserg-09.nifty.com [210.131.2.76]) by lists.denx.de (Postfix) with ESMTPS id C7213C21F8A for ; Wed, 19 Dec 2018 11:03:46 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id wBJB3SMP001192; Wed, 19 Dec 2018 20:03:31 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com wBJB3SMP001192 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1545217411; bh=hPo1VGk6rZSiFCXotbocQpvd6SsnuR9Vv3TDe1LKcEA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YlrpL4OqZsGstUAHgyVb89p6eTNNjfU97IWxCN7qWuzwfRClM70zdHwIy0RbppdV+ 21NqEAe/6nLodx4tGXpGvzP3Q5PuNPjeGKDnzhOTIHhZtLh7bn0CyD3surqSiLXylX X3RQK8oZ5YSZi1suhMUQ7WhLnfR+bf8KWJS/3cURap0mWG9Z9e/QndoJMRjtpUMDk9 QmC9DcDKHBBXTAAQB+Ikftz5Il1UK+rnKuK0KaLmEwJNGa7NebG/MPbW1hE7Fk6a3F 6GQcX2uGS6fpcNfLcAvprJrP7XrIVBHEmQ5K1PWAi8ddUZdHunCWgEQGZGoKAwdZqT tm7S3VPRQrU3A== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Wed, 19 Dec 2018 20:03:18 +0900 Message-Id: <1545217401-27018-7-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1545217401-27018-1-git-send-email-yamada.masahiro@socionext.com> References: <1545217401-27018-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 6/9] mtd: rawnand: denali: optimize timing parameters for data interface X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Based on Linux commit 1dfac31a5a63ac04a9b5fbc3f5105a586560f191 This commit improves the ->setup_data_interface() hook. The denali_setup_data_interface() needs the frequency of clk_x and the ratio of clk_x / clk. The latter is currently hardcoded in the driver, like this: #define DENALI_CLK_X_MULT 6 The IP datasheet requires that clk_x / clk be 4, 5, or 6. I just chose 6 because it is the most defensive value, but it is not optimal. By getting the clock rate of both "clk" and "clk_x", the driver can compute the timing values more precisely. To not break the existing platforms, the fallback value, 50 MHz is provided. It is true for all upstreamed platforms. Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/raw/denali.c | 47 ++++++++++++++++++++-------------------- drivers/mtd/nand/raw/denali.h | 1 + drivers/mtd/nand/raw/denali_dt.c | 2 ++ 3 files changed, 26 insertions(+), 24 deletions(-) diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c index d1cac06..bbfa3b6 100644 --- a/drivers/mtd/nand/raw/denali.c +++ b/drivers/mtd/nand/raw/denali.c @@ -69,14 +69,6 @@ static int dma_mapping_error(void *dev, dma_addr_t addr) #define DENALI_INVALID_BANK -1 #define DENALI_NR_BANKS 4 -/* - * The bus interface clock, clk_x, is phase aligned with the core clock. The - * clk_x is an integral multiple N of the core clk. The value N is configured - * at IP delivery time, and its available value is 4, 5, or 6. We need to align - * to the largest value to make it work with any possible configuration. - */ -#define DENALI_CLK_X_MULT 6 - static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd) { return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand); @@ -946,7 +938,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, { struct denali_nand_info *denali = mtd_to_denali(mtd); const struct nand_sdr_timings *timings; - unsigned long t_clk; + unsigned long t_x, mult_x; int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data; int rdwr_en_lo, rdwr_en_hi, rdwr_en_lo_hi, cs_setup; int addr_2_data_mask; @@ -957,15 +949,24 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, return PTR_ERR(timings); /* clk_x period in picoseconds */ - t_clk = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate); - if (!t_clk) + t_x = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate); + if (!t_x) + return -EINVAL; + + /* + * The bus interface clock, clk_x, is phase aligned with the core clock. + * The clk_x is an integral multiple N of the core clk. The value N is + * configured at IP delivery time, and its available value is 4, 5, 6. + */ + mult_x = DIV_ROUND_CLOSEST_ULL(denali->clk_x_rate, denali->clk_rate); + if (mult_x < 4 || mult_x > 6) return -EINVAL; if (chipnr == NAND_DATA_IFACE_CHECK_ONLY) return 0; /* tREA -> ACC_CLKS */ - acc_clks = DIV_ROUND_UP(timings->tREA_max, t_clk); + acc_clks = DIV_ROUND_UP(timings->tREA_max, t_x); acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE); tmp = ioread32(denali->reg + ACC_CLKS); @@ -974,7 +975,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, iowrite32(tmp, denali->reg + ACC_CLKS); /* tRWH -> RE_2_WE */ - re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_clk); + re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_x); re_2_we = min_t(int, re_2_we, RE_2_WE__VALUE); tmp = ioread32(denali->reg + RE_2_WE); @@ -983,7 +984,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, iowrite32(tmp, denali->reg + RE_2_WE); /* tRHZ -> RE_2_RE */ - re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_clk); + re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_x); re_2_re = min_t(int, re_2_re, RE_2_RE__VALUE); tmp = ioread32(denali->reg + RE_2_RE); @@ -997,8 +998,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, * With WE_2_RE properly set, the Denali controller automatically takes * care of the delay; the driver need not set NAND_WAIT_TCCS. */ - we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), - t_clk); + we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), t_x); we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE); tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE); @@ -1013,7 +1013,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, if (denali->revision < 0x0501) addr_2_data_mask >>= 1; - addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_clk); + addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_x); addr_2_data = min_t(int, addr_2_data, addr_2_data_mask); tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA); @@ -1023,7 +1023,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, /* tREH, tWH -> RDWR_EN_HI_CNT */ rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min), - t_clk); + t_x); rdwr_en_hi = min_t(int, rdwr_en_hi, RDWR_EN_HI_CNT__VALUE); tmp = ioread32(denali->reg + RDWR_EN_HI_CNT); @@ -1032,11 +1032,10 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, iowrite32(tmp, denali->reg + RDWR_EN_HI_CNT); /* tRP, tWP -> RDWR_EN_LO_CNT */ - rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), - t_clk); + rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), t_x); rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min), - t_clk); - rdwr_en_lo_hi = max(rdwr_en_lo_hi, DENALI_CLK_X_MULT); + t_x); + rdwr_en_lo_hi = max_t(int, rdwr_en_lo_hi, mult_x); rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi); rdwr_en_lo = min_t(int, rdwr_en_lo, RDWR_EN_LO_CNT__VALUE); @@ -1046,8 +1045,8 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, iowrite32(tmp, denali->reg + RDWR_EN_LO_CNT); /* tCS, tCEA -> CS_SETUP_CNT */ - cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_clk) - rdwr_en_lo, - (int)DIV_ROUND_UP(timings->tCEA_max, t_clk) - acc_clks, + cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_x) - rdwr_en_lo, + (int)DIV_ROUND_UP(timings->tCEA_max, t_x) - acc_clks, 0); cs_setup = min_t(int, cs_setup, CS_SETUP_CNT__VALUE); diff --git a/drivers/mtd/nand/raw/denali.h b/drivers/mtd/nand/raw/denali.h index 9b797be..019deda 100644 --- a/drivers/mtd/nand/raw/denali.h +++ b/drivers/mtd/nand/raw/denali.h @@ -292,6 +292,7 @@ struct udevice; struct denali_nand_info { struct nand_chip nand; + unsigned long clk_rate; /* core clock rate */ unsigned long clk_x_rate; /* bus interface clock rate */ int active_bank; /* currently selected bank */ struct udevice *dev; diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index f9eadb4..d384b97 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -118,6 +118,7 @@ static int denali_dt_probe(struct udevice *dev) } if (clk_x.dev) { + denali->clk_rate = clk_get_rate(&clk); denali->clk_x_rate = clk_get_rate(&clk_x); } else { /* @@ -126,6 +127,7 @@ static int denali_dt_probe(struct udevice *dev) */ dev_notice(dev, "necessary clock is missing. default clock rates are used.\n"); + denali->clk_rate = 50000000; denali->clk_x_rate = 200000000; } From patchwork Wed Dec 19 11:03:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 154247 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4796901ljp; Wed, 19 Dec 2018 03:03:55 -0800 (PST) X-Google-Smtp-Source: AFSGD/Wzj9Vv/yTqhxe8voP6zFqEYsKlHRj32cREq55/XrjLIMhbeaYG7upgiRLfmrHlNnUNGhnw X-Received: by 2002:a50:94f4:: with SMTP id t49mr19907756eda.24.1545217434904; Wed, 19 Dec 2018 03:03:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545217434; cv=none; d=google.com; s=arc-20160816; b=QqtO88YJnsG4cMTKFt82z/vaPzQw4uwr77Lk3bKNCkX1nSmpCS0+ycsvkczvLSz8/v KyZSEm7cKVHhdStiQxJBBYlLy47r6ldk4AAYk3lOr1O622Uq/yIfNxQzZpPqJSSmPcK4 G4UVaE+eKPZyHSF2hIrl/BPJYY6EtKOzJwrKVe61+voEZPg4p7FOqfI5dP1Tt0b0d3KL m2SSNddf8wdIzrEIL1Qga6b/huSKzwoU/BR7vl18COdVLbmGI4O0olkr0nOIbxFgkA3j gSgYB+PPU3l00UQpuMYNakBxvnIXsgk3vgTpVYvfkzjfpwlUeRN14sTZWyIGaqeqWe8o AtKg== ARC-Message-Signature: i=1; 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[81.169.180.215]) by mx.google.com with ESMTP id u28si4195688edi.62.2018.12.19.03.03.54; Wed, 19 Dec 2018 03:03:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=Eq+5iwel; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 083DAC22076; Wed, 19 Dec 2018 11:03:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 7BD2BC21EF2; Wed, 19 Dec 2018 11:03:48 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 964ADC21F98; Wed, 19 Dec 2018 11:03:47 +0000 (UTC) Received: from conuserg-09.nifty.com (conuserg-09.nifty.com [210.131.2.76]) by lists.denx.de (Postfix) with ESMTPS id A14F1C21EF2 for ; Wed, 19 Dec 2018 11:03:46 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id wBJB3SMQ001192; Wed, 19 Dec 2018 20:03:32 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com wBJB3SMQ001192 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1545217412; bh=WGRl6r1m0R2t/3xEAjlOKP8P9bQAZMbu/0pdWlomXek=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Eq+5iwelcFOgbt5fL6ica82gxB/nphab4LICNYxr9AkXOuXjN4KuhiRPQkOJUuqGC wQsIY0BfbuRxk06vDV5voKxjhzq1sr97yu0dR+YqW6p7QmuO8eB0a4gOrlaVHSeDr/ XtUjFxltlSaimVS5CjuTatRn2pQJbxg0dbUCgdMsUHOUU3N3bqbX/CzM60RCJWg7vx up7p6OzutakxaxmnvA7MbY76uLmN2uTewYmENYtCAGzjMB2HrQ9EGq3k9r5lajA5xA 5gna1xS8fV2u2u1U4Bxx6J/h1/k1vfS4b56a3k/VCJ5BnJukLFcjuMtrqx9IyohqK3 fjtOE9DvX3KUQ== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Wed, 19 Dec 2018 20:03:19 +0900 Message-Id: <1545217401-27018-8-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1545217401-27018-1-git-send-email-yamada.masahiro@socionext.com> References: <1545217401-27018-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 7/9] mtd: rawnand: denali: fix a race condition when DMA is kicked X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Based on Linux commit cf51e4b9c34407bf0c3d9b582b7837e047e1df47 Add the register read-back, commenting why this is necessary. Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/raw/denali.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c index bbfa3b6..e0eb133 100644 --- a/drivers/mtd/nand/raw/denali.c +++ b/drivers/mtd/nand/raw/denali.c @@ -587,6 +587,12 @@ static int denali_dma_xfer(struct denali_nand_info *denali, void *buf, } iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE); + /* + * The ->setup_dma() hook kicks DMA by using the data/command + * interface, which belongs to a different AXI port from the + * register interface. Read back the register to avoid a race. + */ + ioread32(denali->reg + DMA_ENABLE); denali_reset_irq(denali); denali->setup_dma(denali, dma_addr, page, write); From patchwork Wed Dec 19 11:03:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 154248 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4798353ljp; Wed, 19 Dec 2018 03:05:13 -0800 (PST) X-Google-Smtp-Source: AFSGD/UyoMGRdnGMbuoxglZrSMdwUnKL+sRXLzqvoN0nz0WsJEcox0rf6lhPhTsmWCqCoEZsTc+V X-Received: by 2002:a17:906:7751:: with SMTP id o17-v6mr15938255ejn.15.1545217513467; Wed, 19 Dec 2018 03:05:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545217513; cv=none; d=google.com; s=arc-20160816; b=NhTzX/QbnUrLUmg4Xm2bDYgqEcmNQNYbDxwlYLH02MP72Okm1Ej9uSoVwJcpdkhyuS Q5hZMR/sPvgzjAIZxN/1uBlBdGk5Tf4Q9oiBwqpotoHXNdP9VpiZlkAdwZUIAOwEtOXw CJOEH8A37e2Z9H5JYm2DFrA4lN1Sl1XYdXCDns94YsnFY2Jq3+Ohv7RDYOZrY4rrEzgQ XZS7f/WjvwvMENNd9TdGhKdWvF2+YBuPPLfByCVRHLbIR5g94M9G3s1AR56ghuEyEyC9 9EBCKO/8XGR9ZwxrFzRp2pvMHCciExePEFjdYJle4TZT47s7T6dpa6s3MpXCmHF/rUOK LSwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:dkim-filter; bh=C1OcI6wvQ/22w1Xo8N9kRnTEvHngM2rsvdRXo+zkKFI=; b=gHioSlO6dNUKqX+XvCUjjjV0olT5UVY7ALUhRfP5w7nORmdPK89D7rDpyIyEHl9I5H gb53/xFSq2H74Uu367AW87/RYuemtII4vW6bxu2wsa1Y7vQfSmDN4ymrOaO6qQzaCiAU w2rzVJv0f7ttkgXg1FEmomVyDtOk8Mkqg1ad32NBOlBpZ7UO9gQmdoahP62CWYaTm3rw fa1/wJ4Z4WioIM+UAMNrdbdL0EmIhSwMXSJNBbzj30nIW72OT2d1f0/bW0K08bbS34jE w6xl15j7mNk/THS4i5knq7XEoGLLdCKait9K7SbuxsHmyN8vUFb5pQveElIEy+2dJwlq xJbA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=ewg2z+ca; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id 2-v6si682126eju.12.2018.12.19.03.05.13; Wed, 19 Dec 2018 03:05:13 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=ewg2z+ca; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 13069C2206E; Wed, 19 Dec 2018 11:04:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 11364C21FAC; Wed, 19 Dec 2018 11:03:49 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id AAD96C21EB4; Wed, 19 Dec 2018 11:03:47 +0000 (UTC) Received: from conuserg-09.nifty.com (conuserg-09.nifty.com [210.131.2.76]) by lists.denx.de (Postfix) with ESMTPS id 9C70FC21EB4 for ; Wed, 19 Dec 2018 11:03:46 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id wBJB3SMR001192; Wed, 19 Dec 2018 20:03:32 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com wBJB3SMR001192 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1545217412; bh=kI8BrC+eRpj5euVzqD134Vlct7zMawBiVlttfrkFOFs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ewg2z+camoEbXDooly5BDZAyLKHbD1r+7mSrdTNVKcsdt5HvxVEUaOuWdh+kjf6CC NJ8gHsDtPJdhXLdg63cQ6NZqkAWC/VlW+JwqjC9TS0bOkhmRddSo/RtXkl9oD7FXz5 jabMhpR1znJUEGEiRFRvUwg794m3ZORsGMVWdcXhw6l47xMhhXQsm+uztEeLTnqgQb 4HmMnS12jWM2r9dbNuBN3t4BmsX8w4hXia8XeABQ0NPB+yzMQHhr5Gq3CF0AKIyOKM lMdTKJfIdxDTdYNVR+NqEl3SKkz47hUMxR2P1Cj+36HKvQcL57EfQG3AFndXctiXis OeE5+nGVTscHw== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Wed, 19 Dec 2018 20:03:20 +0900 Message-Id: <1545217401-27018-9-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1545217401-27018-1-git-send-email-yamada.masahiro@socionext.com> References: <1545217401-27018-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 8/9] clk: uniphier: add NAND 200MHz clock X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The Denali NAND controller IP needs three clocks: - clk: controller core clock - clk_x: bus interface clock - ecc_clk: clock at which ECC circuitry is run Currently, only the first one (50MHz) is provided. The rest of the two clock ports must be connected to the 200MHz clock line. Add this. Signed-off-by: Masahiro Yamada --- drivers/clk/uniphier/clk-uniphier-sys.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c index 9e087b6..487b43e 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -6,13 +6,12 @@ #include "clk-uniphier.h" -/* Denali driver requires clk_x rate (clk: 50MHz, clk_x & ecc_clk: 200MHz) */ #define UNIPHIER_LD4_SYS_CLK_NAND(_id) \ - UNIPHIER_CLK_RATE(128, 200000000), \ + UNIPHIER_CLK_RATE(128, 50000000), \ UNIPHIER_CLK_GATE((_id), 128, 0x2104, 2) #define UNIPHIER_LD11_SYS_CLK_NAND(_id) \ - UNIPHIER_CLK_RATE(128, 200000000), \ + UNIPHIER_CLK_RATE(128, 50000000), \ UNIPHIER_CLK_GATE((_id), 128, 0x210c, 0) const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { @@ -20,6 +19,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) ||\ defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B) UNIPHIER_LD4_SYS_CLK_NAND(2), + UNIPHIER_CLK_RATE(3, 200000000), UNIPHIER_CLK_GATE_SIMPLE(6, 0x2104, 12), /* ether (Pro4, PXs2) */ UNIPHIER_CLK_GATE_SIMPLE(7, 0x2104, 5), /* ether-gb (Pro4) */ UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10), /* stdmac */ @@ -36,6 +36,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20) UNIPHIER_LD11_SYS_CLK_NAND(2), + UNIPHIER_CLK_RATE(3, 200000000), UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 6), /* ether */ UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8), /* stdmac */ UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */ @@ -48,6 +49,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = { #if defined(CONFIG_ARCH_UNIPHIER_PXS3) UNIPHIER_LD11_SYS_CLK_NAND(2), + UNIPHIER_CLK_RATE(3, 200000000), UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 9), /* ether0 */ UNIPHIER_CLK_GATE_SIMPLE(7, 0x210c, 10), /* ether1 */ UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4), /* usb30 (gio0) */ From patchwork Wed Dec 19 11:03:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 154255 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4803373ljp; Wed, 19 Dec 2018 03:09:46 -0800 (PST) X-Google-Smtp-Source: AFSGD/X79pe/Qs0qacIDPRoP/sRC22ceuHqaYw1vtaPxsdyjyesESLKuOiM1K+7dxwklJ025bG4Y X-Received: by 2002:a17:906:30d5:: with SMTP id b21-v6mr16399633ejb.42.1545217786414; Wed, 19 Dec 2018 03:09:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545217786; cv=none; d=google.com; s=arc-20160816; b=nIQe79JSrKBtXfx3pFfPjPqnv9K46QFvSVw14X7FoIuAd8dcA0065bM5WMt1Yu9Lrb 8d8eYx3qAp9OQVVz5vNpAsCqR50lV3BBGnIVSobgj3LNvjLIHe8aeENRelCAJ5Qanaxi 70CpK4g8BOl1IxjUKi2EIdstII40vLx2hLpxcRPcMRgA+agD5wqooRx3MxmEEWxg1ZWi BAKDHbXEo9VNiVhaHiAIXU3WBrRHaJd1IRK1kISzrPPl350j8PMg46a+oS1Pros2zQxO nAZqVkgUq4PlxPhs3jdcGBxVi4bWXAh6H9EPBm6+1vJdirhQBrN2LaS2ywpucpyFMyRB SAxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:dkim-filter; bh=I5GPTwL6Flg8uJ0bFmrLpIsGrlrTBjFssI5l2SmEC0Q=; b=zYp+906WPems05EtZ4CgE9BX9+IP747xOLWgjmsOngk0MnYeHOEfB2RPDgl9ONUWi4 NBiNOjC33k6cN+XOALokKyEsSCRPmhnwAf6FVLLDdaS1GSLYQpPQST4nPTXmXVgOVUf/ FRHvES1kJeI/Sq0OCmqSOBA/FZwM9OmdgpmwwT9QEdC6f2QIfTVoquDNgRw4qCB9czsx IQUw4cVDwJnQwIdjUabhT7/gej7CEVq0N7FJvatB5LWMXFMIWQDaLFbYQuwu9Bdqrpoi 68eF1Z4Q6JWoVlBia7U70jcDr7PbI7SIURADUkGomV52O2E5w2KNY6ONLKTxGhSV4aFe TsZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=lROdm1u7; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id cg5-v6si1981676ejb.288.2018.12.19.03.09.46; Wed, 19 Dec 2018 03:09:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=lROdm1u7; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id F34BCC220AF; Wed, 19 Dec 2018 11:06:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6AED6C220B7; Wed, 19 Dec 2018 11:04:28 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 80668C220B7; Wed, 19 Dec 2018 11:04:02 +0000 (UTC) Received: from conuserg-09.nifty.com (conuserg-09.nifty.com [210.131.2.76]) by lists.denx.de (Postfix) with ESMTPS id B3B87C21FFA for ; Wed, 19 Dec 2018 11:03:57 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id wBJB3SMS001192; Wed, 19 Dec 2018 20:03:33 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com wBJB3SMS001192 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1545217413; bh=X4YJ+f4VRT8LnfOGUH4WUjngDkfyMo1yO3jXkTAiiHM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lROdm1u7rG3HtakARqY84unbLiC4TRy3AYRM2o4lA2zlVB5Hbrh9K+p9fUSERMJt8 YsogjrkE9PSQs0vlA6XkQRCSLk/SpneLuX29uiT61oMzsNHoFRTEGTpP+sT/qWHoLz z7mn2IrLOLBloV3cZDTVMrjDPeo0HcPBbXOtG7a3fURG4EL5jRN7dzFMlRzSBo9d4v 3I/6hVec2ZfCI2AlEudJLdIWrBjyRZh9jP9B/y9g7Q8rzv9in7iBjQjSNNLFr1ImBw r1pmJlD9ppcCbjqQJkOu4WUPVLjC28Xm0rM/2P0t4gcNYFbyfqsRBvqCU80x0AfxKn 0RMFPpKG4IajA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Wed, 19 Dec 2018 20:03:21 +0900 Message-Id: <1545217401-27018-10-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1545217401-27018-1-git-send-email-yamada.masahiro@socionext.com> References: <1545217401-27018-1-git-send-email-yamada.masahiro@socionext.com> Cc: Tom Rini Subject: [U-Boot] [PATCH 9/9] ARM: uniphier: dts: sync with Linux 4.20-rc7 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Currently, the DWC3 USB node is out of sync because the bindings for the UniPhier DWC3 PHY diverged between Linux and U-Boot. Signed-off-by: Masahiro Yamada --- arch/arm/dts/uniphier-ld11.dtsi | 52 ++++++- arch/arm/dts/uniphier-ld20-global.dts | 4 + arch/arm/dts/uniphier-ld20-ref.dts | 4 + arch/arm/dts/uniphier-ld20.dtsi | 242 +++++++++++++++++++++++++++++- arch/arm/dts/uniphier-ld4.dtsi | 14 +- arch/arm/dts/uniphier-pinctrl.dtsi | 20 +++ arch/arm/dts/uniphier-pro4-ace.dts | 8 +- arch/arm/dts/uniphier-pro4-sanji.dts | 8 +- arch/arm/dts/uniphier-pro4.dtsi | 143 +++++++++++++++++- arch/arm/dts/uniphier-pro5.dtsi | 25 +++- arch/arm/dts/uniphier-pxs2.dtsi | 207 +++++++++++++++++++++++++- arch/arm/dts/uniphier-pxs3.dtsi | 267 +++++++++++++++++++++++++++++++++- arch/arm/dts/uniphier-sld8.dtsi | 14 +- 13 files changed, 992 insertions(+), 16 deletions(-) diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi index d63b56e..31ba52b 100644 --- a/arch/arm/dts/uniphier-ld11.dtsi +++ b/arch/arm/dts/uniphier-ld11.dtsi @@ -116,6 +116,28 @@ #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi1: spi@54006100 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006100 0x100>; + interrupts = <0 216 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; @@ -432,6 +454,8 @@ <&mio_clk 12>; resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>; + phy-names = "usb"; + phys = <&usb_phy0>; has-transaction-translator; }; @@ -446,6 +470,8 @@ <&mio_clk 13>; resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>; + phy-names = "usb"; + phys = <&usb_phy1>; has-transaction-translator; }; @@ -460,6 +486,8 @@ <&mio_clk 14>; resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>; + phy-names = "usb"; + phys = <&usb_phy2>; has-transaction-translator; }; @@ -488,6 +516,27 @@ pinctrl: pinctrl { compatible = "socionext,uniphier-ld11-pinctrl"; }; + + usb-phy { + compatible = "socionext,uniphier-ld11-usb2-phy"; + #address-cells = <1>; + #size-cells = <0>; + + usb_phy0: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + usb_phy1: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + usb_phy2: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + }; }; soc-glue@5f900000 { @@ -571,7 +620,8 @@ interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; - clocks = <&sys_clk 2>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; }; }; diff --git a/arch/arm/dts/uniphier-ld20-global.dts b/arch/arm/dts/uniphier-ld20-global.dts index 1a5e7c2..9ca692e 100644 --- a/arch/arm/dts/uniphier-ld20-global.dts +++ b/arch/arm/dts/uniphier-ld20-global.dts @@ -145,6 +145,10 @@ }; }; +&usb { + status = "okay"; +}; + &nand { status = "okay"; }; diff --git a/arch/arm/dts/uniphier-ld20-ref.dts b/arch/arm/dts/uniphier-ld20-ref.dts index 440c2e6..406244a 100644 --- a/arch/arm/dts/uniphier-ld20-ref.dts +++ b/arch/arm/dts/uniphier-ld20-ref.dts @@ -75,3 +75,7 @@ drive-strength = <9>; }; }; + +&usb { + status = "okay"; +}; diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi index 9970497..b9ed613 100644 --- a/arch/arm/dts/uniphier-ld20.dtsi +++ b/arch/arm/dts/uniphier-ld20.dtsi @@ -224,6 +224,50 @@ #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi1: spi@54006100 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006100 0x100>; + interrupts = <0 216 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi2: spi@54006200 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006200 0x100>; + interrupts = <0 229 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi3: spi@54006300 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006300 0x100>; + interrupts = <0 230 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi3>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; @@ -567,6 +611,50 @@ efuse@200 { compatible = "socionext,uniphier-efuse"; reg = <0x200 0x68>; + #address-cells = <1>; + #size-cells = <1>; + + /* USB cells */ + usb_rterm0: trim@54,4 { + reg = <0x54 1>; + bits = <4 2>; + }; + usb_rterm1: trim@55,4 { + reg = <0x55 1>; + bits = <4 2>; + }; + usb_rterm2: trim@58,4 { + reg = <0x58 1>; + bits = <4 2>; + }; + usb_rterm3: trim@59,4 { + reg = <0x59 1>; + bits = <4 2>; + }; + usb_sel_t0: trim@54,0 { + reg = <0x54 1>; + bits = <0 4>; + }; + usb_sel_t1: trim@55,0 { + reg = <0x55 1>; + bits = <0 4>; + }; + usb_sel_t2: trim@58,0 { + reg = <0x58 1>; + bits = <0 4>; + }; + usb_sel_t3: trim@59,0 { + reg = <0x59 1>; + bits = <0 4>; + }; + usb_hs_i0: trim@56,0 { + reg = <0x56 1>; + bits = <0 4>; + }; + usb_hs_i2: trim@5a,0 { + reg = <0x5a 1>; + bits = <0 4>; + }; }; }; @@ -634,6 +722,157 @@ }; }; + _usb: usb@65a00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65a00000 0xcd00>; + interrupt-names = "host"; + interrupts = <0 134 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>, + <&pinctrl_usb2>, <&pinctrl_usb3>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>; + resets = <&usb_rst 15>; + phys = <&usb_hsphy0>, <&usb_hsphy1>, + <&usb_hsphy2>, <&usb_hsphy3>, + <&usb_ssphy0>, <&usb_ssphy1>; + dr_mode = "host"; + }; + + usb-glue@65b00000 { + compatible = "socionext,uniphier-ld20-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65b00000 0x400>; + + usb_rst: reset@0 { + compatible = "socionext,uniphier-ld20-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb_vbus0: regulator@100 { + compatible = "socionext,uniphier-ld20-usb3-regulator"; + reg = <0x100 0x10>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb_vbus1: regulator@110 { + compatible = "socionext,uniphier-ld20-usb3-regulator"; + reg = <0x110 0x10>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb_vbus2: regulator@120 { + compatible = "socionext,uniphier-ld20-usb3-regulator"; + reg = <0x120 0x10>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb_vbus3: regulator@130 { + compatible = "socionext,uniphier-ld20-usb3-regulator"; + reg = <0x130 0x10>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb_hsphy0: hs-phy@200 { + compatible = "socionext,uniphier-ld20-usb3-hsphy"; + reg = <0x200 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 16>; + vbus-supply = <&usb_vbus0>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, + <&usb_hs_i0>; + }; + + usb_hsphy1: hs-phy@210 { + compatible = "socionext,uniphier-ld20-usb3-hsphy"; + reg = <0x210 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 16>; + vbus-supply = <&usb_vbus1>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>, + <&usb_hs_i0>; + }; + + usb_hsphy2: hs-phy@220 { + compatible = "socionext,uniphier-ld20-usb3-hsphy"; + reg = <0x220 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 17>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 17>; + vbus-supply = <&usb_vbus2>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>, + <&usb_hs_i2>; + }; + + usb_hsphy3: hs-phy@230 { + compatible = "socionext,uniphier-ld20-usb3-hsphy"; + reg = <0x230 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 17>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 17>; + vbus-supply = <&usb_vbus3>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>, + <&usb_hs_i2>; + }; + + usb_ssphy0: ss-phy@300 { + compatible = "socionext,uniphier-ld20-usb3-ssphy"; + reg = <0x300 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 18>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 18>; + vbus-supply = <&usb_vbus0>; + }; + + usb_ssphy1: ss-phy@310 { + compatible = "socionext,uniphier-ld20-usb3-ssphy"; + reg = <0x310 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 19>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 19>; + vbus-supply = <&usb_vbus1>; + }; + }; + + /* FIXME: U-Boot own node */ usb: usb@65b00000 { compatible = "socionext,uniphier-ld20-dwc3"; reg = <0x65b00000 0x1000>; @@ -660,7 +899,8 @@ interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; - clocks = <&sys_clk 2>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; }; }; diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi index f505f64..b73d594 100644 --- a/arch/arm/dts/uniphier-ld4.dtsi +++ b/arch/arm/dts/uniphier-ld4.dtsi @@ -63,6 +63,17 @@ cache-level = <2>; }; + spi: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; @@ -381,7 +392,8 @@ interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand2cs>; - clocks = <&sys_clk 2>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; }; }; diff --git a/arch/arm/dts/uniphier-pinctrl.dtsi b/arch/arm/dts/uniphier-pinctrl.dtsi index aeb47b0..1fee5ff 100644 --- a/arch/arm/dts/uniphier-pinctrl.dtsi +++ b/arch/arm/dts/uniphier-pinctrl.dtsi @@ -131,6 +131,26 @@ function = "sd1"; }; + pinctrl_spi0: spi0 { + groups = "spi0"; + function = "spi0"; + }; + + pinctrl_spi1: spi1 { + groups = "spi1"; + function = "spi1"; + }; + + pinctrl_spi2: spi2 { + groups = "spi2"; + function = "spi2"; + }; + + pinctrl_spi3: spi3 { + groups = "spi3"; + function = "spi3"; + }; + pinctrl_system_bus: system-bus { groups = "system_bus", "system_bus_cs1"; function = "system_bus"; diff --git a/arch/arm/dts/uniphier-pro4-ace.dts b/arch/arm/dts/uniphier-pro4-ace.dts index bff90c2..ce8ea7b 100644 --- a/arch/arm/dts/uniphier-pro4-ace.dts +++ b/arch/arm/dts/uniphier-pro4-ace.dts @@ -73,11 +73,11 @@ status = "okay"; }; -&usb0 { +&usb2 { status = "okay"; }; -&usb1 { +&usb3 { status = "okay"; }; @@ -92,10 +92,10 @@ }; }; -&usb2 { +&usb0 { status = "okay"; }; -&usb3 { +&usb1 { status = "okay"; }; diff --git a/arch/arm/dts/uniphier-pro4-sanji.dts b/arch/arm/dts/uniphier-pro4-sanji.dts index 7f5b957..686dd3a 100644 --- a/arch/arm/dts/uniphier-pro4-sanji.dts +++ b/arch/arm/dts/uniphier-pro4-sanji.dts @@ -68,11 +68,11 @@ status = "okay"; }; -&usb0 { +&usb2 { status = "okay"; }; -&usb1 { +&usb3 { status = "okay"; }; @@ -87,10 +87,10 @@ }; }; -&usb2 { +&usb0 { status = "okay"; }; -&usb3 { +&usb1 { status = "okay"; }; diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi index 8974844..ef34208 100644 --- a/arch/arm/dts/uniphier-pro4.dtsi +++ b/arch/arm/dts/uniphier-pro4.dtsi @@ -71,6 +71,17 @@ cache-level = <2>; }; + spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; @@ -317,6 +328,8 @@ <&mio_clk 12>; resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>; + phy-names = "usb"; + phys = <&usb_phy0>; has-transaction-translator; }; @@ -331,6 +344,8 @@ <&mio_clk 13>; resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>; + phy-names = "usb"; + phys = <&usb_phy1>; has-transaction-translator; }; @@ -342,6 +357,34 @@ pinctrl: pinctrl { compatible = "socionext,uniphier-pro4-pinctrl"; }; + + usb-phy { + compatible = "socionext,uniphier-pro4-usb2-phy"; + #address-cells = <1>; + #size-cells = <0>; + + usb_phy0: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + usb_phy1: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + usb_phy2: phy@2 { + reg = <2>; + #phy-cells = <0>; + vbus-supply = <&usb0_vbus>; + }; + + usb_phy3: phy@3 { + reg = <3>; + #phy-cells = <0>; + vbus-supply = <&usb1_vbus>; + }; + }; }; soc-glue@5f900000 { @@ -434,6 +477,60 @@ }; }; + _usb0: usb@65a00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65a00000 0xcd00>; + interrupt-names = "host", "peripheral"; + interrupts = <0 134 4>, <0 135 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; + resets = <&usb0_rst 4>; + phys = <&usb_phy2>, <&usb0_ssphy>; + dr_mode = "host"; + }; + + usb-glue@65b00000 { + compatible = "socionext,uniphier-pro4-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65b00000 0x100>; + + usb0_vbus: regulator@0 { + compatible = "socionext,uniphier-pro4-usb3-regulator"; + reg = <0 0x10>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 14>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 14>; + }; + + usb0_ssphy: ss-phy@10 { + compatible = "socionext,uniphier-pro4-usb3-ssphy"; + reg = <0x10 0x10>; + #phy-cells = <0>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 14>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 14>; + vbus-supply = <&usb0_vbus>; + }; + + usb0_rst: reset@40 { + compatible = "socionext,uniphier-pro4-usb3-reset"; + reg = <0x40 0x4>; + #reset-cells = <1>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 14>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 14>; + }; + }; + + /* FIXME: U-Boot own node */ usb0: usb@65b00000 { compatible = "socionext,uniphier-pro4-dwc3"; status = "disabled"; @@ -452,6 +549,49 @@ }; }; + _usb1: usb@65c00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65c00000 0xcd00>; + interrupt-names = "host", "peripheral"; + interrupts = <0 137 4>, <0 138 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; + resets = <&usb1_rst 4>; + phys = <&usb_phy3>; + dr_mode = "host"; + }; + + usb-glue@65d00000 { + compatible = "socionext,uniphier-pro4-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65d00000 0x100>; + + usb1_vbus: regulator@0 { + compatible = "socionext,uniphier-pro4-usb3-regulator"; + reg = <0 0x10>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 15>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 15>; + }; + + usb1_rst: reset@40 { + compatible = "socionext,uniphier-pro4-usb3-reset"; + reg = <0x40 0x4>; + #reset-cells = <1>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 15>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 15>; + }; + }; + + /* FIXME: U-Boot own node */ usb1: usb@65d00000 { compatible = "socionext,uniphier-pro4-dwc3"; status = "disabled"; @@ -478,7 +618,8 @@ interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; - clocks = <&sys_clk 2>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; }; }; diff --git a/arch/arm/dts/uniphier-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi index 6e0ea79..9cad79d 100644 --- a/arch/arm/dts/uniphier-pro5.dtsi +++ b/arch/arm/dts/uniphier-pro5.dtsi @@ -156,6 +156,28 @@ cache-level = <3>; }; + spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi1: spi@54006100 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006100 0x100>; + interrupts = <0 216 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; @@ -475,7 +497,8 @@ interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand2cs>; - clocks = <&sys_clk 2>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; }; diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi index 63c1c2c..fa25ffd 100644 --- a/arch/arm/dts/uniphier-pxs2.dtsi +++ b/arch/arm/dts/uniphier-pxs2.dtsi @@ -167,6 +167,28 @@ cache-level = <2>; }; + spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi1: spi@54006100 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006100 0x100>; + interrupts = <0 216 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; @@ -557,6 +579,103 @@ }; }; + _usb0: usb@65a00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65a00000 0xcd00>; + interrupt-names = "host", "peripheral"; + interrupts = <0 134 4>, <0 135 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>; + resets = <&usb0_rst 15>; + phys = <&usb0_hsphy0>, <&usb0_hsphy1>, + <&usb0_ssphy0>, <&usb0_ssphy1>; + dr_mode = "host"; + }; + + usb-glue@65b00000 { + compatible = "socionext,uniphier-pxs2-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65b00000 0x400>; + + usb0_rst: reset@0 { + compatible = "socionext,uniphier-pxs2-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb0_vbus0: regulator@100 { + compatible = "socionext,uniphier-pxs2-usb3-regulator"; + reg = <0x100 0x10>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb0_vbus1: regulator@110 { + compatible = "socionext,uniphier-pxs2-usb3-regulator"; + reg = <0x110 0x10>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb0_hsphy0: hs-phy@200 { + compatible = "socionext,uniphier-pxs2-usb3-hsphy"; + reg = <0x200 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 16>; + vbus-supply = <&usb0_vbus0>; + }; + + usb0_hsphy1: hs-phy@210 { + compatible = "socionext,uniphier-pxs2-usb3-hsphy"; + reg = <0x210 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 16>; + vbus-supply = <&usb0_vbus1>; + }; + + usb0_ssphy0: ss-phy@300 { + compatible = "socionext,uniphier-pxs2-usb3-ssphy"; + reg = <0x300 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 17>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 17>; + vbus-supply = <&usb0_vbus0>; + }; + + usb0_ssphy1: ss-phy@310 { + compatible = "socionext,uniphier-pxs2-usb3-ssphy"; + reg = <0x310 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 18>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 18>; + vbus-supply = <&usb0_vbus1>; + }; + }; + + /* FIXME: U-Boot own node */ usb0: usb@65b00000 { compatible = "socionext,uniphier-pxs2-dwc3"; status = "disabled"; @@ -575,6 +694,91 @@ }; }; + _usb1: usb@65c00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65c00000 0xcd00>; + interrupt-names = "host", "peripheral"; + interrupts = <0 137 4>, <0 138 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 15>, <&sys_clk 15>, <&sys_clk 15>; + resets = <&usb1_rst 15>; + phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>; + dr_mode = "host"; + }; + + usb-glue@65d00000 { + compatible = "socionext,uniphier-pxs2-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65d00000 0x400>; + + usb1_rst: reset@0 { + compatible = "socionext,uniphier-pxs2-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "link"; + clocks = <&sys_clk 15>; + reset-names = "link"; + resets = <&sys_rst 15>; + }; + + usb1_vbus0: regulator@100 { + compatible = "socionext,uniphier-pxs2-usb3-regulator"; + reg = <0x100 0x10>; + clock-names = "link"; + clocks = <&sys_clk 15>; + reset-names = "link"; + resets = <&sys_rst 15>; + }; + + usb1_vbus1: regulator@110 { + compatible = "socionext,uniphier-pxs2-usb3-regulator"; + reg = <0x110 0x10>; + clock-names = "link"; + clocks = <&sys_clk 15>; + reset-names = "link"; + resets = <&sys_rst 15>; + }; + + usb1_hsphy0: hs-phy@200 { + compatible = "socionext,uniphier-pxs2-usb3-hsphy"; + reg = <0x200 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 15>, <&sys_clk 20>; + reset-names = "link", "phy"; + resets = <&sys_rst 15>, <&sys_rst 20>; + vbus-supply = <&usb1_vbus0>; + }; + + usb1_hsphy1: hs-phy@210 { + compatible = "socionext,uniphier-pxs2-usb3-hsphy"; + reg = <0x210 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 15>, <&sys_clk 20>; + reset-names = "link", "phy"; + resets = <&sys_rst 15>, <&sys_rst 20>; + vbus-supply = <&usb1_vbus1>; + }; + + usb1_ssphy0: ss-phy@300 { + compatible = "socionext,uniphier-pxs2-usb3-ssphy"; + reg = <0x300 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 15>, <&sys_clk 21>; + reset-names = "link", "phy"; + resets = <&sys_rst 15>, <&sys_rst 21>; + vbus-supply = <&usb1_vbus0>; + }; + }; + + /* FIXME: U-Boot own node */ usb1: usb@65d00000 { compatible = "socionext,uniphier-pxs2-dwc3"; status = "disabled"; @@ -601,7 +805,8 @@ interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand2cs>; - clocks = <&sys_clk 2>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; }; }; diff --git a/arch/arm/dts/uniphier-pxs3.dtsi b/arch/arm/dts/uniphier-pxs3.dtsi index daf7453..f629c6a 100644 --- a/arch/arm/dts/uniphier-pxs3.dtsi +++ b/arch/arm/dts/uniphier-pxs3.dtsi @@ -144,6 +144,28 @@ #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi1: spi@54006100 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006100 0x100>; + interrupts = <0 216 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; @@ -384,6 +406,50 @@ efuse@200 { compatible = "socionext,uniphier-efuse"; reg = <0x200 0x68>; + #address-cells = <1>; + #size-cells = <1>; + + /* USB cells */ + usb_rterm0: trim@54,4 { + reg = <0x54 1>; + bits = <4 2>; + }; + usb_rterm1: trim@55,4 { + reg = <0x55 1>; + bits = <4 2>; + }; + usb_rterm2: trim@58,4 { + reg = <0x58 1>; + bits = <4 2>; + }; + usb_rterm3: trim@59,4 { + reg = <0x59 1>; + bits = <4 2>; + }; + usb_sel_t0: trim@54,0 { + reg = <0x54 1>; + bits = <0 4>; + }; + usb_sel_t1: trim@55,0 { + reg = <0x55 1>; + bits = <0 4>; + }; + usb_sel_t2: trim@58,0 { + reg = <0x58 1>; + bits = <0 4>; + }; + usb_sel_t3: trim@59,0 { + reg = <0x59 1>; + bits = <0 4>; + }; + usb_hs_i0: trim@56,0 { + reg = <0x56 1>; + bits = <0 4>; + }; + usb_hs_i2: trim@5a,0 { + reg = <0x5a 1>; + bits = <0 4>; + }; }; }; @@ -465,6 +531,109 @@ }; }; + _usb0: usb@65a00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65a00000 0xcd00>; + interrupt-names = "host", "peripheral"; + interrupts = <0 134 4>, <0 135 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; + resets = <&usb0_rst 15>; + phys = <&usb0_hsphy0>, <&usb0_hsphy1>, + <&usb0_ssphy0>, <&usb0_ssphy1>; + dr_mode = "host"; + }; + + usb-glue@65b00000 { + compatible = "socionext,uniphier-pxs3-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65b00000 0x400>; + + usb0_rst: reset@0 { + compatible = "socionext,uniphier-pxs3-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "link"; + clocks = <&sys_clk 12>; + reset-names = "link"; + resets = <&sys_rst 12>; + }; + + usb0_vbus0: regulator@100 { + compatible = "socionext,uniphier-pxs3-usb3-regulator"; + reg = <0x100 0x10>; + clock-names = "link"; + clocks = <&sys_clk 12>; + reset-names = "link"; + resets = <&sys_rst 12>; + }; + + usb0_vbus1: regulator@110 { + compatible = "socionext,uniphier-pxs3-usb3-regulator"; + reg = <0x110 0x10>; + clock-names = "link"; + clocks = <&sys_clk 12>; + reset-names = "link"; + resets = <&sys_rst 12>; + }; + + usb0_hsphy0: hs-phy@200 { + compatible = "socionext,uniphier-pxs3-usb3-hsphy"; + reg = <0x200 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 12>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 12>, <&sys_rst 16>; + vbus-supply = <&usb0_vbus0>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, + <&usb_hs_i0>; + }; + + usb0_hsphy1: hs-phy@210 { + compatible = "socionext,uniphier-pxs3-usb3-hsphy"; + reg = <0x210 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 12>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 12>, <&sys_rst 16>; + vbus-supply = <&usb0_vbus1>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>, + <&usb_hs_i0>; + }; + + usb0_ssphy0: ss-phy@300 { + compatible = "socionext,uniphier-pxs3-usb3-ssphy"; + reg = <0x300 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 12>, <&sys_clk 17>; + reset-names = "link", "phy"; + resets = <&sys_rst 12>, <&sys_rst 17>; + vbus-supply = <&usb0_vbus0>; + }; + + usb0_ssphy1: ss-phy@310 { + compatible = "socionext,uniphier-pxs3-usb3-ssphy"; + reg = <0x310 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 12>, <&sys_clk 18>; + reset-names = "link", "phy"; + resets = <&sys_rst 12>, <&sys_rst 18>; + vbus-supply = <&usb0_vbus1>; + }; + }; + + /* FIXME: U-Boot own node */ usb0: usb@65b00000 { compatible = "socionext,uniphier-pxs3-dwc3"; status = "disabled"; @@ -483,6 +652,101 @@ }; }; + _usb1: usb@65c00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65c00000 0xcd00>; + interrupt-names = "host", "peripheral"; + interrupts = <0 137 4>, <0 138 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>; + resets = <&usb1_rst 15>; + phys = <&usb1_hsphy0>, <&usb1_hsphy1>, + <&usb1_ssphy0>; + dr_mode = "host"; + }; + + usb-glue@65d00000 { + compatible = "socionext,uniphier-pxs3-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65d00000 0x400>; + + usb1_rst: reset@0 { + compatible = "socionext,uniphier-pxs3-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "link"; + clocks = <&sys_clk 13>; + reset-names = "link"; + resets = <&sys_rst 13>; + }; + + usb1_vbus0: regulator@100 { + compatible = "socionext,uniphier-pxs3-usb3-regulator"; + reg = <0x100 0x10>; + clock-names = "link"; + clocks = <&sys_clk 13>; + reset-names = "link"; + resets = <&sys_rst 13>; + }; + + usb1_vbus1: regulator@110 { + compatible = "socionext,uniphier-pxs3-usb3-regulator"; + reg = <0x110 0x10>; + clock-names = "link"; + clocks = <&sys_clk 13>; + reset-names = "link"; + resets = <&sys_rst 13>; + }; + + usb1_hsphy0: hs-phy@200 { + compatible = "socionext,uniphier-pxs3-usb3-hsphy"; + reg = <0x200 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy", "phy-ext"; + clocks = <&sys_clk 13>, <&sys_clk 20>, + <&sys_clk 14>; + reset-names = "link", "phy"; + resets = <&sys_rst 13>, <&sys_rst 20>; + vbus-supply = <&usb1_vbus0>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>, + <&usb_hs_i2>; + }; + + usb1_hsphy1: hs-phy@210 { + compatible = "socionext,uniphier-pxs3-usb3-hsphy"; + reg = <0x210 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy", "phy-ext"; + clocks = <&sys_clk 13>, <&sys_clk 20>, + <&sys_clk 14>; + reset-names = "link", "phy"; + resets = <&sys_rst 13>, <&sys_rst 20>; + vbus-supply = <&usb1_vbus1>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>, + <&usb_hs_i2>; + }; + + usb1_ssphy0: ss-phy@300 { + compatible = "socionext,uniphier-pxs3-usb3-ssphy"; + reg = <0x300 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy", "phy-ext"; + clocks = <&sys_clk 13>, <&sys_clk 21>, + <&sys_clk 14>; + reset-names = "link", "phy"; + resets = <&sys_rst 13>, <&sys_rst 21>; + vbus-supply = <&usb1_vbus0>; + }; + }; + + /* FIXME: U-Boot own node */ usb1: usb@65d00000 { compatible = "socionext,uniphier-pxs3-dwc3"; status = "disabled"; @@ -509,7 +773,8 @@ interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; - clocks = <&sys_clk 2>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; }; }; diff --git a/arch/arm/dts/uniphier-sld8.dtsi b/arch/arm/dts/uniphier-sld8.dtsi index 437265b..f7fcf6b 100644 --- a/arch/arm/dts/uniphier-sld8.dtsi +++ b/arch/arm/dts/uniphier-sld8.dtsi @@ -63,6 +63,17 @@ cache-level = <2>; }; + spi: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; @@ -385,7 +396,8 @@ interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand2cs>; - clocks = <&sys_clk 2>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; }; };