From patchwork Wed Apr 27 14:46:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Piyush Malgujar X-Patchwork-Id: 566886 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20E9CC433EF for ; Wed, 27 Apr 2022 14:47:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238553AbiD0OuO (ORCPT ); Wed, 27 Apr 2022 10:50:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238594AbiD0OuN (ORCPT ); Wed, 27 Apr 2022 10:50:13 -0400 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C50F23A71F; Wed, 27 Apr 2022 07:47:01 -0700 (PDT) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 23R8PvKm029548; Wed, 27 Apr 2022 07:46:58 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=kUzkGHosfalGaRapK8AEVNc6FRaQFJYIbMbE7o+fLSQ=; b=JOqTrqelIkscEbNsw12aw/yQYr6a/OeWKgXSoUY2p11o/JF2Ra92BdWzMpxDZSYs1tDz 0QBMcrH0qANhmGii5E2qUSCL77961h03t6dmwT1P3XXb6dXR0UmuFq/bqHF+ncLtPM6D YtjRLvqCCImbt1ChanogYBjZRxqmJ12on06Bcr2dK4vyRi7ydRsazcYuMVxu7NWhaqsy hxieoNmPpJxFUlt5A5N+FXeZ3DtRZmonC0YxWhQ86HZLA3ZXX3yhFt6Kspvb4SXMQpTN p0wunk95E6OWG19n02lfhCt90KEfS6WJ+WRKs38XvEfnL14PvyiFRGotNoU86D2Hgi0c rg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3fprsqu79w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 27 Apr 2022 07:46:58 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 27 Apr 2022 07:46:57 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 27 Apr 2022 07:46:57 -0700 Received: from localhost.localdomain (unknown [10.110.150.250]) by maili.marvell.com (Postfix) with ESMTP id C113E3F7063; Wed, 27 Apr 2022 07:46:56 -0700 (PDT) From: Piyush Malgujar To: , , CC: , , , , , , , Piyush Malgujar Subject: [PATCH 1/5] gpio: thunderx: avoid potential deadlock Date: Wed, 27 Apr 2022 07:46:16 -0700 Message-ID: <20220427144620.9105-2-pmalgujar@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220427144620.9105-1-pmalgujar@marvell.com> References: <20220427144620.9105-1-pmalgujar@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: LAvtWri8CC1NfFI3tKWyRRAYN6aS-AzR X-Proofpoint-GUID: LAvtWri8CC1NfFI3tKWyRRAYN6aS-AzR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-04-27_04,2022-04-27_01,2022-02-23_01 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Using irqsave/irqrestore locking variants to avoid any deadlock. Signed-off-by: Piyush Malgujar --- drivers/gpio/gpio-thunderx.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/gpio/gpio-thunderx.c b/drivers/gpio/gpio-thunderx.c index 9f66deab46eaa99d05413a996b585284c433574d..bb2b40e4033b00134af35592b6b7c7f83cf6c737 100644 --- a/drivers/gpio/gpio-thunderx.c +++ b/drivers/gpio/gpio-thunderx.c @@ -104,16 +104,17 @@ static int thunderx_gpio_request(struct gpio_chip *chip, unsigned int line) static int thunderx_gpio_dir_in(struct gpio_chip *chip, unsigned int line) { struct thunderx_gpio *txgpio = gpiochip_get_data(chip); + unsigned long flags; if (!thunderx_gpio_is_gpio(txgpio, line)) return -EIO; - raw_spin_lock(&txgpio->lock); + raw_spin_lock_irqsave(&txgpio->lock, flags); clear_bit(line, txgpio->invert_mask); clear_bit(line, txgpio->od_mask); writeq(txgpio->line_entries[line].fil_bits, txgpio->register_base + bit_cfg_reg(line)); - raw_spin_unlock(&txgpio->lock); + raw_spin_unlock_irqrestore(&txgpio->lock, flags); return 0; } @@ -135,11 +136,12 @@ static int thunderx_gpio_dir_out(struct gpio_chip *chip, unsigned int line, { struct thunderx_gpio *txgpio = gpiochip_get_data(chip); u64 bit_cfg = txgpio->line_entries[line].fil_bits | GPIO_BIT_CFG_TX_OE; + unsigned long flags; if (!thunderx_gpio_is_gpio(txgpio, line)) return -EIO; - raw_spin_lock(&txgpio->lock); + raw_spin_lock_irqsave(&txgpio->lock, flags); thunderx_gpio_set(chip, line, value); @@ -151,7 +153,7 @@ static int thunderx_gpio_dir_out(struct gpio_chip *chip, unsigned int line, writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line)); - raw_spin_unlock(&txgpio->lock); + raw_spin_unlock_irqrestore(&txgpio->lock, flags); return 0; } @@ -188,11 +190,12 @@ static int thunderx_gpio_set_config(struct gpio_chip *chip, int ret = -ENOTSUPP; struct thunderx_gpio *txgpio = gpiochip_get_data(chip); void __iomem *reg = txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET; + unsigned long flags; if (!thunderx_gpio_is_gpio(txgpio, line)) return -EIO; - raw_spin_lock(&txgpio->lock); + raw_spin_lock_irqsave(&txgpio->lock, flags); orig_invert = test_bit(line, txgpio->invert_mask); new_invert = orig_invert; orig_od = test_bit(line, txgpio->od_mask); @@ -243,7 +246,7 @@ static int thunderx_gpio_set_config(struct gpio_chip *chip, default: break; } - raw_spin_unlock(&txgpio->lock); + raw_spin_unlock_irqrestore(&txgpio->lock, flags); /* * If currently output and OPEN_DRAIN changed, install the new @@ -329,6 +332,7 @@ static int thunderx_gpio_irq_set_type(struct irq_data *d, struct thunderx_gpio *txgpio = gpiochip_get_data(gc); struct thunderx_line *txline = &txgpio->line_entries[irqd_to_hwirq(d)]; + unsigned long flags; u64 bit_cfg; irqd_set_trigger_type(d, flow_type); @@ -342,7 +346,7 @@ static int thunderx_gpio_irq_set_type(struct irq_data *d, irq_set_handler_locked(d, handle_fasteoi_mask_irq); } - raw_spin_lock(&txgpio->lock); + raw_spin_lock_irqsave(&txgpio->lock, flags); if (flow_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)) { bit_cfg |= GPIO_BIT_CFG_PIN_XOR; set_bit(txline->line, txgpio->invert_mask); @@ -351,7 +355,7 @@ static int thunderx_gpio_irq_set_type(struct irq_data *d, } clear_bit(txline->line, txgpio->od_mask); writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(txline->line)); - raw_spin_unlock(&txgpio->lock); + raw_spin_unlock_irqrestore(&txgpio->lock, flags); return IRQ_SET_MASK_OK; } From patchwork Wed Apr 27 14:46:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Piyush Malgujar X-Patchwork-Id: 567362 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DD52C433FE for ; Wed, 27 Apr 2022 14:47:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238598AbiD0Ou0 (ORCPT ); Wed, 27 Apr 2022 10:50:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238657AbiD0OuZ (ORCPT ); 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Wed, 27 Apr 2022 07:47:08 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 27 Apr 2022 07:47:06 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 27 Apr 2022 07:47:06 -0700 Received: from localhost.localdomain (unknown [10.110.150.250]) by maili.marvell.com (Postfix) with ESMTP id D08FA3F7063; Wed, 27 Apr 2022 07:47:05 -0700 (PDT) From: Piyush Malgujar To: , , CC: , , , , , , , Piyush Malgujar Subject: [PATCH 2/5] dt-bindings: gpio: gpio-thunderx: Describe pin-cfg option Date: Wed, 27 Apr 2022 07:46:17 -0700 Message-ID: <20220427144620.9105-3-pmalgujar@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220427144620.9105-1-pmalgujar@marvell.com> References: <20220427144620.9105-1-pmalgujar@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 1rhJ-vk_rVehFRlKEshunqQkzaFeuKHx X-Proofpoint-GUID: 1rhJ-vk_rVehFRlKEshunqQkzaFeuKHx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-04-27_04,2022-04-27_01,2022-02-23_01 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add support for pin-cfg to configure GPIO Pins Signed-off-by: Piyush Malgujar --- Documentation/devicetree/bindings/gpio/gpio-thunderx.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt b/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt index 3f883ae29d116887e702ead20b26a25f9d2349d5..05f0be98afdcae941ff8a24c3fdabd8af83ccb87 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt @@ -14,6 +14,9 @@ Optional Properties: "interrupt-controller" is present. - First cell is the GPIO pin number relative to the controller. - Second cell is triggering flags as defined in interrupts.txt. +- pin-cfg: Configuration of pin's function, filters, XOR and output mode. + - First cell is the GPIO pin number + - Second cell is a value written to GPIO_BIT_CFG register at driver probe. Example: @@ -24,4 +27,5 @@ gpio_6_0: gpio@6,0 { #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + pin-cfg = <57 0x2300000>, <58 0x2500000>; }; From patchwork Wed Apr 27 14:46:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Piyush Malgujar X-Patchwork-Id: 567361 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 585CFC433FE for ; Wed, 27 Apr 2022 14:48:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238659AbiD0Ovl (ORCPT ); Wed, 27 Apr 2022 10:51:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238666AbiD0Ouc (ORCPT ); Wed, 27 Apr 2022 10:50:32 -0400 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F1D443BA7D; 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Wed, 27 Apr 2022 07:47:16 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 27 Apr 2022 07:47:14 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 27 Apr 2022 07:47:14 -0700 Received: from localhost.localdomain (unknown [10.110.150.250]) by maili.marvell.com (Postfix) with ESMTP id 6CFFA5B6948; Wed, 27 Apr 2022 07:47:14 -0700 (PDT) From: Piyush Malgujar To: , , CC: , , , , , , , Piyush Malgujar Subject: [PATCH 3/5] gpio: thunderx: Configure GPIO pins at probe Date: Wed, 27 Apr 2022 07:46:18 -0700 Message-ID: <20220427144620.9105-4-pmalgujar@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220427144620.9105-1-pmalgujar@marvell.com> References: <20220427144620.9105-1-pmalgujar@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 14M_RTwEzwoHuUHAtoOCpcRGZbihR07T X-Proofpoint-GUID: 14M_RTwEzwoHuUHAtoOCpcRGZbihR07T X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-04-27_04,2022-04-27_01,2022-02-23_01 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add support to configure GPIO pins using DTS 'pin-cfg' Signed-off-by: Piyush Malgujar --- drivers/gpio/gpio-thunderx.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/gpio/gpio-thunderx.c b/drivers/gpio/gpio-thunderx.c index bb2b40e4033b00134af35592b6b7c7f83cf6c737..451c412512450fea717937376002d2ba35d1c508 100644 --- a/drivers/gpio/gpio-thunderx.c +++ b/drivers/gpio/gpio-thunderx.c @@ -426,6 +426,32 @@ static void *thunderx_gpio_populate_parent_alloc_info(struct gpio_chip *chip, return info; } +static void thunderx_gpio_pinsel(struct device *dev, + struct thunderx_gpio *txgpio) +{ + struct device_node *node; + const __be32 *pinsel; + int npins, rlen, i; + u32 pin, sel; + + node = dev_of_node(dev); + if (!node) + return; + + pinsel = of_get_property(node, "pin-cfg", &rlen); + if (!pinsel || rlen % 2) + return; + + npins = rlen / sizeof(__be32) / 2; + + for (i = 0; i < npins; i++) { + pin = of_read_number(pinsel++, 1); + sel = of_read_number(pinsel++, 1); + dev_dbg(dev, "Set GPIO pin %d CFG register to %x\n", pin, sel); + writeq(sel, txgpio->register_base + bit_cfg_reg(pin)); + } +} + static int thunderx_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id) { @@ -548,6 +574,9 @@ static int thunderx_gpio_probe(struct pci_dev *pdev, if (err) goto out; + /* Configure default functions of GPIO pins */ + thunderx_gpio_pinsel(dev, txgpio); + /* Push on irq_data and the domain for each line. */ for (i = 0; i < ngpio; i++) { struct irq_fwspec fwspec; From patchwork Wed Apr 27 14:46:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Piyush Malgujar X-Patchwork-Id: 566884 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A66CC43217 for ; Wed, 27 Apr 2022 14:48:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238697AbiD0Ovl (ORCPT ); Wed, 27 Apr 2022 10:51:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238750AbiD0Ouj (ORCPT ); Wed, 27 Apr 2022 10:50:39 -0400 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 357A03BA4B; Wed, 27 Apr 2022 07:47:27 -0700 (PDT) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 23R8jpdZ029645; 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Wed, 27 Apr 2022 07:47:23 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 27 Apr 2022 07:47:23 -0700 Received: from localhost.localdomain (unknown [10.110.150.250]) by maili.marvell.com (Postfix) with ESMTP id 2EB883F7063; Wed, 27 Apr 2022 07:47:23 -0700 (PDT) From: Piyush Malgujar To: , , CC: , , , , , , , Piyush Malgujar Subject: [PATCH 4/5] gpio: thunderx: extend PIN_SEL_MASK to cover otx2 platform Date: Wed, 27 Apr 2022 07:46:19 -0700 Message-ID: <20220427144620.9105-5-pmalgujar@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220427144620.9105-1-pmalgujar@marvell.com> References: <20220427144620.9105-1-pmalgujar@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: wZSqUzC7mEqMcS_b2O2sMGq8zt872j0H X-Proofpoint-GUID: wZSqUzC7mEqMcS_b2O2sMGq8zt872j0H X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-04-27_04,2022-04-27_01,2022-02-23_01 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Extending the PIN_SEL_MASK to support otx2 platform which was earlier RAZ. Signed-off-by: Piyush Malgujar --- drivers/gpio/gpio-thunderx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-thunderx.c b/drivers/gpio/gpio-thunderx.c index 451c412512450fea717937376002d2ba35d1c508..87ab1ad7e652347a67b7747ea497b944498a8b41 100644 --- a/drivers/gpio/gpio-thunderx.c +++ b/drivers/gpio/gpio-thunderx.c @@ -32,7 +32,7 @@ #define GPIO_BIT_CFG_FIL_CNT_SHIFT 4 #define GPIO_BIT_CFG_FIL_SEL_SHIFT 8 #define GPIO_BIT_CFG_TX_OD BIT(12) -#define GPIO_BIT_CFG_PIN_SEL_MASK GENMASK(25, 16) +#define GPIO_BIT_CFG_PIN_SEL_MASK GENMASK(26, 16) #define GPIO_INTR 0x800 #define GPIO_INTR_INTR BIT(0) #define GPIO_INTR_INTR_W1S BIT(1) From patchwork Wed Apr 27 14:46:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Piyush Malgujar X-Patchwork-Id: 566885 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D160DC433EF for ; Wed, 27 Apr 2022 14:47:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238616AbiD0Our (ORCPT ); Wed, 27 Apr 2022 10:50:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238536AbiD0Oup (ORCPT ); Wed, 27 Apr 2022 10:50:45 -0400 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A8C63BA59; Wed, 27 Apr 2022 07:47:34 -0700 (PDT) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 23R8jpda029645; Wed, 27 Apr 2022 07:47:31 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=gsxpG4RiXnCTCF6V9lo/7D//jaoYpWLGlyTjAD+8/qk=; b=koGcsTh8SpOBk2r6NfOSKOAo4RsmzmAnH5jn03a2QcYMlA9fxXDUpspTfDNk8qjBIS1T MnUSAw/JBmQWKSt9j/0gBs09AIQxjWb96zVW+YqZczWukuwwLY7EmJA8J4uvHBrlbKU1 yiYozr/5xmBdZP2JIrSTF1oxhDNcv3omS+fTrBctxjZpn0GoaH0Bt8gS5ECuBxeIalwm UUkvtKWoBi3gpI0AZYaYTJTvodESnxQcwDJ+sselMYF24CPxQALfX+96SSGP2MNikLJj yuxML5Wep0pyJ5Ls4TpBxbUBWJbJBteqUYorrdM8rmKFx3yCg3cqCS3WNL2Ny4fqSZG2 XQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3fprsqu7ca-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 27 Apr 2022 07:47:31 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 27 Apr 2022 07:47:30 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 27 Apr 2022 07:47:30 -0700 Received: from localhost.localdomain (unknown [10.110.150.250]) by maili.marvell.com (Postfix) with ESMTP id ADFAF3F7063; Wed, 27 Apr 2022 07:47:29 -0700 (PDT) From: Piyush Malgujar To: , , CC: , , , , , , , Piyush Malgujar Subject: [PATCH 5/5] gpio: thunderx: change handler for level interrupt Date: Wed, 27 Apr 2022 07:46:20 -0700 Message-ID: <20220427144620.9105-6-pmalgujar@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220427144620.9105-1-pmalgujar@marvell.com> References: <20220427144620.9105-1-pmalgujar@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 0uaggkiGNeQvQqwE58ua4JEIRGRBqzNm X-Proofpoint-GUID: 0uaggkiGNeQvQqwE58ua4JEIRGRBqzNm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-04-27_04,2022-04-27_01,2022-02-23_01 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The current level interrupt handler is masking the GPIO interrupt and not unmasking it, to resolve that, handle_level_irq is used. Signed-off-by: Witold Sadowski Signed-off-by: Piyush Malgujar Reviewed-by: Linus Walleij --- drivers/gpio/gpio-thunderx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-thunderx.c b/drivers/gpio/gpio-thunderx.c index 87ab1ad7e652347a67b7747ea497b944498a8b41..b1063e53ceb8edf26ca1a6ecab8035aad62128a1 100644 --- a/drivers/gpio/gpio-thunderx.c +++ b/drivers/gpio/gpio-thunderx.c @@ -343,7 +343,7 @@ static int thunderx_gpio_irq_set_type(struct irq_data *d, irq_set_handler_locked(d, handle_fasteoi_ack_irq); bit_cfg |= GPIO_BIT_CFG_INT_TYPE; } else { - irq_set_handler_locked(d, handle_fasteoi_mask_irq); + irq_set_handler_locked(d, handle_level_irq); } raw_spin_lock_irqsave(&txgpio->lock, flags);