From patchwork Tue May 3 20:09:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 569121 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B427C433FE for ; Tue, 3 May 2022 20:10:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240665AbiECUNo (ORCPT ); Tue, 3 May 2022 16:13:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234092AbiECUNm (ORCPT ); Tue, 3 May 2022 16:13:42 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 3DB14403F4; Tue, 3 May 2022 13:10:01 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 5DCE816D1; Tue, 3 May 2022 23:10:33 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 5DCE816D1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1651608633; bh=4LJQQ+flJun0UygUXRUKxHXx7rdadvvKQYRSaah2pvM=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=pwPVwEjAoL4fUnf46GzG8WEgfF9JpBHkITFbRMqJdrIPjWAQROCZb0zAHmyOpRz2W dAlQcD8p+SSTJg01AR0QnUdW9stfJ/Yei7ewk9lExh05nC0csiwI24kAjLzPMIbUu8 o02qv4H8NhRjJX6CNdji7t4NpIAnZZhDnlCeSbKg= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 3 May 2022 23:09:59 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Rob Herring , Krzysztof Kozlowski CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , , , Subject: [PATCH v2 01/23] dt-bindings: ata: ahci-platform: Drop dma-coherent property declaration Date: Tue, 3 May 2022 23:09:16 +0300 Message-ID: <20220503200938.18027-2-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220503200938.18027-1-Sergey.Semin@baikalelectronics.ru> References: <20220503200938.18027-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org It's redundant to have the 'dma-coherent' property explicitly specified in the DT schema because it's a generic property described in the core DT-schema by which the property is always evaluated. Signed-off-by: Serge Semin --- Changelog v2: - This is a new patch created after rebasing v1 onto the 5.18-rc3 kernel. --- Documentation/devicetree/bindings/ata/ahci-platform.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.yaml b/Documentation/devicetree/bindings/ata/ahci-platform.yaml index c146ab8e14e5..9304e4731965 100644 --- a/Documentation/devicetree/bindings/ata/ahci-platform.yaml +++ b/Documentation/devicetree/bindings/ata/ahci-platform.yaml @@ -87,8 +87,6 @@ properties: description: regulator for AHCI controller - dma-coherent: true - phy-supply: description: regulator for PHY power From patchwork Tue May 3 20:09:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 569120 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 070F6C433F5 for ; Tue, 3 May 2022 20:10:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242175AbiECUNp (ORCPT ); Tue, 3 May 2022 16:13:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48654 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236380AbiECUNm (ORCPT ); Tue, 3 May 2022 16:13:42 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 6EE5D27143; Tue, 3 May 2022 13:10:07 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 9A53B16DA; Tue, 3 May 2022 23:10:37 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 9A53B16DA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1651608637; bh=zHaHwKz/yCVMvZJtPXeZzX7KArDCiwAc5Mq+USo7pmc=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=e4NJ0gWE0usDCwyFRiDo57cUnOpQT5zW9B6KhDrD/VXkUAJyCV9vKUs+qnMqq2Qch 5Nnj4LSt9kJMFc/ZBv7fOniNyWfK9Tu20JL9YGcMhU+FbGf7BU05OgnGn7ZaAVc0j0 nCxeypGD+OBUzHZcS7NWM/Ke7cASfaykBx3zud60= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 3 May 2022 23:10:03 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Rob Herring , , , Subject: [PATCH v2 05/23] ata: libahci_platform: Explicitly set rc on devres_alloc failure Date: Tue, 3 May 2022 23:09:20 +0300 Message-ID: <20220503200938.18027-6-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220503200938.18027-1-Sergey.Semin@baikalelectronics.ru> References: <20220503200938.18027-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org It's better for readability and maintainability to explicitly assign an error number to the variable used then as a return value from the method on the cleanup-on-error path. So adding new code in the method we won't have to think whether the overridden rc-variable is set afterward in case of an error. Saving one line of code doesn't worth it especially seeing the rest of the ahci_platform_get_resources() function errors handling blocks do explicitly write errno to rc. Signed-off-by: Serge Semin --- Changelog v2: - Drop rc variable initialization (@Damien) --- drivers/ata/libahci_platform.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c index 32495ae96567..f7f9bfcfc164 100644 --- a/drivers/ata/libahci_platform.c +++ b/drivers/ata/libahci_platform.c @@ -389,7 +389,7 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev, struct ahci_host_priv *hpriv; struct clk *clk; struct device_node *child; - int i, enabled_ports = 0, rc = -ENOMEM, child_nodes; + int i, enabled_ports = 0, rc, child_nodes; u32 mask_port_map = 0; if (!devres_open_group(dev, NULL, GFP_KERNEL)) @@ -397,8 +397,10 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev, hpriv = devres_alloc(ahci_platform_put_resources, sizeof(*hpriv), GFP_KERNEL); - if (!hpriv) + if (!hpriv) { + rc = -ENOMEM; goto err_out; + } devres_add(dev, hpriv); From patchwork Tue May 3 20:09:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 569119 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4949C433F5 for ; Tue, 3 May 2022 20:10:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242265AbiECUNs (ORCPT ); Tue, 3 May 2022 16:13:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48654 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237775AbiECUNn (ORCPT ); Tue, 3 May 2022 16:13:43 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 7585E3FBE9; Tue, 3 May 2022 13:10:08 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id D759E16DE; Tue, 3 May 2022 23:10:40 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru D759E16DE DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1651608640; bh=6HMO+sQEG0eDggOCw6HtXOnAgHhA4OiT4KgL3s0gPcs=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=kQYuIWdEZhdQzY0Q7MIEq0udyTHAxSDmDL5hKSD55Zbst4pfmdEt1NVgoSodBDCIh rcjVd3V0RmC6RjgIP4M2RQBWXe5zLORMxpL8e0N5MNaEZb43e0VeD5cKIKQfw2xNC6 E68zGMYsRKqkn0LXeWt1SlLMzgVJcwY+sJuDPprM= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 3 May 2022 23:10:06 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Rob Herring , , , Subject: [PATCH v2 08/23] ata: libahci_platform: Add function returning a clock-handle by id Date: Tue, 3 May 2022 23:09:23 +0300 Message-ID: <20220503200938.18027-9-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220503200938.18027-1-Sergey.Semin@baikalelectronics.ru> References: <20220503200938.18027-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Since all the clocks are retrieved by the method ahci_platform_get_resources() there is no need for the LLD (glue) drivers to be looking for some particular of them in the kernel clocks table again. Instead we suggest to add a simple method returning a device-specific clock with passed connection ID if it is managed to be found. Otherwise the function will return NULL. Thus the glue-drivers won't need to either manually touching the hpriv->clks array or calling clk_get()-friends. The AHCI platform drivers will be able to use the new function right after the ahci_platform_get_resources() method invocation and up to the device removal. Signed-off-by: Serge Semin --- Changelog v2: - Fix some grammar mistakes in the method description. --- drivers/ata/libahci_platform.c | 27 +++++++++++++++++++++++++++ include/linux/ahci_platform.h | 3 +++ 2 files changed, 30 insertions(+) diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c index 3cff86c225fd..7ff6626fd569 100644 --- a/drivers/ata/libahci_platform.c +++ b/drivers/ata/libahci_platform.c @@ -94,6 +94,33 @@ void ahci_platform_disable_phys(struct ahci_host_priv *hpriv) } EXPORT_SYMBOL_GPL(ahci_platform_disable_phys); +/** + * ahci_platform_find_clk - Find platform clock + * @hpriv: host private area to store config values + * @con_id: clock connection ID + * + * This function returns a pointer to the clock descriptor of the clock with + * the passed ID. + * + * RETURNS: + * Pointer to the clock descriptor on success otherwise NULL + */ +struct clk *ahci_platform_find_clk(struct ahci_host_priv *hpriv, const char *con_id) +{ + struct clk *clk = NULL; + int i; + + for (i = 0; i < hpriv->n_clks; i++) { + if (!strcmp(hpriv->clks[i].id, con_id)) { + clk = hpriv->clks[i].clk; + break; + } + } + + return clk; +} +EXPORT_SYMBOL_GPL(ahci_platform_find_clk); + /** * ahci_platform_enable_clks - Enable platform clocks * @hpriv: host private area to store config values diff --git a/include/linux/ahci_platform.h b/include/linux/ahci_platform.h index 49e5383d4222..fd964e6a68d6 100644 --- a/include/linux/ahci_platform.h +++ b/include/linux/ahci_platform.h @@ -13,6 +13,7 @@ #include +struct clk; struct device; struct ata_port_info; struct ahci_host_priv; @@ -21,6 +22,8 @@ struct scsi_host_template; int ahci_platform_enable_phys(struct ahci_host_priv *hpriv); void ahci_platform_disable_phys(struct ahci_host_priv *hpriv); +struct clk * +ahci_platform_find_clk(struct ahci_host_priv *hpriv, const char *con_id); int ahci_platform_enable_clks(struct ahci_host_priv *hpriv); void ahci_platform_disable_clks(struct ahci_host_priv *hpriv); int ahci_platform_enable_regulators(struct ahci_host_priv *hpriv); From patchwork Tue May 3 20:09:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 569118 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D44EBC4332F for ; Tue, 3 May 2022 20:10:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242282AbiECUNu (ORCPT ); Tue, 3 May 2022 16:13:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48692 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242179AbiECUNo (ORCPT ); Tue, 3 May 2022 16:13:44 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 5951826AE3; Tue, 3 May 2022 13:10:10 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 30DDA1DFF8; Tue, 3 May 2022 23:10:43 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 30DDA1DFF8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1651608643; bh=kAvAo0Xyh3tr65Bbm2f0YNCTB8PUXE60W2QC7FBw7fk=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=BXNqjfrowSppsCXS/eEP5oiCtRHrkp7J5zx8sF1YZJW5+CrDLPITMNPUP/7FO4VEo 7zPkkNjM0fLqUbG5puihgYgAl7YGF5iCyRNSvmuUpDcIsSqSK2+5mM4dpwnCLn0coP 387ayr7TmHmrUsQHgzMnNQVyNBeJ6Q6PNMEd0kac= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 3 May 2022 23:10:09 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Matthias Brugger , Patrice Chotard CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Rob Herring , , , , , Subject: [PATCH v2 10/23] ata: libahci_platform: Parse ports-implemented property in resources getter Date: Tue, 3 May 2022 23:09:25 +0300 Message-ID: <20220503200938.18027-11-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220503200938.18027-1-Sergey.Semin@baikalelectronics.ru> References: <20220503200938.18027-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The ports-implemented property is mainly used on the OF-based platforms with no ports mapping initialized by a bootloader/BIOS firmware. Seeing the same of_property_read_u32()-based pattern has already been implemented in the generic AHCI LLDD (glue) driver and in the Mediatek, St AHCI drivers let's move the property read procedure to the generic ahci_platform_get_resources() method. Thus we'll have the forced ports mapping feature supported for each OF-based platform which requires that, and stop re-implementing the same pattern in there a bit simplifying the code. Signed-off-by: Serge Semin --- drivers/ata/ahci_mtk.c | 2 -- drivers/ata/ahci_platform.c | 3 --- drivers/ata/ahci_st.c | 3 --- drivers/ata/libahci_platform.c | 3 +++ 4 files changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/ata/ahci_mtk.c b/drivers/ata/ahci_mtk.c index 1f6c85fde983..c056378e3e72 100644 --- a/drivers/ata/ahci_mtk.c +++ b/drivers/ata/ahci_mtk.c @@ -118,8 +118,6 @@ static int mtk_ahci_parse_property(struct ahci_host_priv *hpriv, SYS_CFG_SATA_EN); } - of_property_read_u32(np, "ports-implemented", &hpriv->force_port_map); - return 0; } diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c index 28a8de5b48b9..9b56490ecbc3 100644 --- a/drivers/ata/ahci_platform.c +++ b/drivers/ata/ahci_platform.c @@ -56,9 +56,6 @@ static int ahci_probe(struct platform_device *pdev) if (rc) return rc; - of_property_read_u32(dev->of_node, - "ports-implemented", &hpriv->force_port_map); - if (of_device_is_compatible(dev->of_node, "hisilicon,hisi-ahci")) hpriv->flags |= AHCI_HFLAG_NO_FBS | AHCI_HFLAG_NO_NCQ; diff --git a/drivers/ata/ahci_st.c b/drivers/ata/ahci_st.c index 7526653c843b..068621099c00 100644 --- a/drivers/ata/ahci_st.c +++ b/drivers/ata/ahci_st.c @@ -168,9 +168,6 @@ static int st_ahci_probe(struct platform_device *pdev) st_ahci_configure_oob(hpriv->mmio); - of_property_read_u32(dev->of_node, - "ports-implemented", &hpriv->force_port_map); - err = ahci_platform_init_host(pdev, hpriv, &st_ahci_port_info, &ahci_platform_sht); if (err) { diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c index 4e54e19f07b2..f7f9cac10cb1 100644 --- a/drivers/ata/libahci_platform.c +++ b/drivers/ata/libahci_platform.c @@ -512,6 +512,9 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev, goto err_out; } + of_property_read_u32(dev->of_node, + "ports-implemented", &hpriv->force_port_map); + if (child_nodes) { for_each_child_of_node(dev->of_node, child) { u32 port; From patchwork Tue May 3 20:09:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 569117 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 069D0C43219 for ; Tue, 3 May 2022 20:10:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242289AbiECUNv (ORCPT ); Tue, 3 May 2022 16:13:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242213AbiECUNp (ORCPT ); Tue, 3 May 2022 16:13:45 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 1E18D2C112; Tue, 3 May 2022 13:10:11 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 6DECD1E019; Tue, 3 May 2022 23:10:44 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 6DECD1E019 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1651608644; bh=oH7lfkiEYXF2C7OEv0pADf3awSH8hsOXvowsTPSKNLA=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=IOXlkGPi1WfxdIOz/nJyq1abhez5oz2c4BTAhgu87BfLW8em6pcTjbAd6M7vfvk76 INGFzl0K2eruwt0JftSgcWhafYmbhqpJRwbWhp5G/VmyujXk1ZCawuzILPR/80sxmb MetUNG0Zx293IaiRHYJzbiDJqX4AY8gQTcfdFUQ0= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 3 May 2022 23:10:10 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Rob Herring , , , Subject: [PATCH v2 11/23] ata: libahci_platform: Introduce reset assertion/deassertion methods Date: Tue, 3 May 2022 23:09:26 +0300 Message-ID: <20220503200938.18027-12-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220503200938.18027-1-Sergey.Semin@baikalelectronics.ru> References: <20220503200938.18027-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Currently the ACHI-platform library supports only the assert and deassert reset signals and ignores the platforms with self-deasserting reset lines. That prone to having the platforms with self-deasserting reset method misbehaviour when it comes to resuming from sleep state after the clocks have been fully disabled. For such cases the controller needs to be fully reset all over after the reference clocks are enabled and stable, otherwise the controller state machine might be in an undetermined state. The best solution would be to auto-detect which reset method is supported by the particular platform and use it implicitly in the framework of the ahci_platform_enable_resources()/ahci_platform_disable_resources() methods. Alas it can't be implemented due to the AHCI-platform library already supporting the shared reset control lines. As [1] says in such case we have to use only one of the next methods: + reset_control_assert()/reset_control_deassert(); + reset_control_reset()/reset_control_rearm(). If the driver had an exclusive control over the reset lines we could have been able to manipulate the lines with no much limitation and just used the combination of the methods above to cover all the possible reset-control cases. Since the shared reset control has already been advertised and couldn't be changed with no risk to breaking the platforms relying on it, we have no choice but to make the platform drivers to determine which reset methods the platform reset system supports. In order to implement both types of reset control support we suggest to introduce the new AHCI-platform flag: AHCI_PLATFORM_RST_TRIGGER, which when passed to the ahci_platform_get_resources() method together with the AHCI_PLATFORM_GET_RESETS flag will indicate that the reset lines are self-deasserting thus the reset_control_reset()/reset_control_rearm() will be used to control the reset state. Otherwise the reset_control_deassert()/reset_control_assert() methods will be utilized. [1] Documentation/driver-api/reset.rst Signed-off-by: Serge Semin --- Changelog v2: - Convert the ahci_platform_assert_rsts() method to returning int status (@Damien). - Fix some grammar mistakes in the ahci_platform_deassert_rsts() doc (@Damien). --- drivers/ata/ahci.h | 1 + drivers/ata/libahci_platform.c | 50 ++++++++++++++++++++++++++++++---- include/linux/ahci_platform.h | 5 +++- 3 files changed, 50 insertions(+), 6 deletions(-) diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h index c3770a19781b..7d834deefeb9 100644 --- a/drivers/ata/ahci.h +++ b/drivers/ata/ahci.h @@ -340,6 +340,7 @@ struct ahci_host_priv { bool got_runtime_pm; /* Did we do pm_runtime_get? */ unsigned int n_clks; struct clk_bulk_data *clks; /* Optional */ + unsigned int f_rsts; struct reset_control *rsts; /* Optional */ struct regulator **target_pwrs; /* Optional */ struct regulator *ahci_regulator;/* Optional */ diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c index f7f9cac10cb1..f5ee2f9d014b 100644 --- a/drivers/ata/libahci_platform.c +++ b/drivers/ata/libahci_platform.c @@ -150,6 +150,44 @@ void ahci_platform_disable_clks(struct ahci_host_priv *hpriv) } EXPORT_SYMBOL_GPL(ahci_platform_disable_clks); +/** + * ahci_platform_deassert_rsts - Deassert/trigger platform resets + * @hpriv: host private area to store config values + * + * This function deasserts or triggers all the reset lines found for + * the AHCI device. + * + * RETURNS: + * 0 on success otherwise a negative error code + */ +int ahci_platform_deassert_rsts(struct ahci_host_priv *hpriv) +{ + if (hpriv->f_rsts & AHCI_PLATFORM_RST_TRIGGER) + return reset_control_reset(hpriv->rsts); + + return reset_control_deassert(hpriv->rsts); +} +EXPORT_SYMBOL_GPL(ahci_platform_deassert_rsts); + +/** + * ahci_platform_assert_rsts - Assert/rearm platform resets + * @hpriv: host private area to store config values + * + * This function asserts or rearms (for self-deasserting resets) all + * the reset controls found for the AHCI device. + * + * RETURNS: + * 0 on success otherwise a negative error code + */ +int ahci_platform_assert_rsts(struct ahci_host_priv *hpriv) +{ + if (hpriv->f_rsts & AHCI_PLATFORM_RST_TRIGGER) + return reset_control_rearm(hpriv->rsts); + + return reset_control_assert(hpriv->rsts); +} +EXPORT_SYMBOL_GPL(ahci_platform_assert_rsts); + /** * ahci_platform_enable_regulators - Enable regulators * @hpriv: host private area to store config values @@ -247,18 +285,18 @@ int ahci_platform_enable_resources(struct ahci_host_priv *hpriv) if (rc) goto disable_regulator; - rc = reset_control_deassert(hpriv->rsts); + rc = ahci_platform_deassert_rsts(hpriv); if (rc) goto disable_clks; rc = ahci_platform_enable_phys(hpriv); if (rc) - goto disable_resets; + goto disable_rsts; return 0; -disable_resets: - reset_control_assert(hpriv->rsts); +disable_rsts: + ahci_platform_assert_rsts(hpriv); disable_clks: ahci_platform_disable_clks(hpriv); @@ -285,7 +323,7 @@ void ahci_platform_disable_resources(struct ahci_host_priv *hpriv) { ahci_platform_disable_phys(hpriv); - reset_control_assert(hpriv->rsts); + ahci_platform_assert_rsts(hpriv); ahci_platform_disable_clks(hpriv); @@ -478,6 +516,8 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev, rc = PTR_ERR(hpriv->rsts); goto err_out; } + + hpriv->f_rsts = flags & AHCI_PLATFORM_RST_TRIGGER; } /* diff --git a/include/linux/ahci_platform.h b/include/linux/ahci_platform.h index fd964e6a68d6..3418980b0341 100644 --- a/include/linux/ahci_platform.h +++ b/include/linux/ahci_platform.h @@ -26,6 +26,8 @@ struct clk * ahci_platform_find_clk(struct ahci_host_priv *hpriv, const char *con_id); int ahci_platform_enable_clks(struct ahci_host_priv *hpriv); void ahci_platform_disable_clks(struct ahci_host_priv *hpriv); +int ahci_platform_deassert_rsts(struct ahci_host_priv *hpriv); +int ahci_platform_assert_rsts(struct ahci_host_priv *hpriv); int ahci_platform_enable_regulators(struct ahci_host_priv *hpriv); void ahci_platform_disable_regulators(struct ahci_host_priv *hpriv); int ahci_platform_enable_resources(struct ahci_host_priv *hpriv); @@ -44,6 +46,7 @@ int ahci_platform_resume_host(struct device *dev); int ahci_platform_suspend(struct device *dev); int ahci_platform_resume(struct device *dev); -#define AHCI_PLATFORM_GET_RESETS 0x01 +#define AHCI_PLATFORM_GET_RESETS BIT(0) +#define AHCI_PLATFORM_RST_TRIGGER BIT(1) #endif /* _AHCI_PLATFORM_H */ From patchwork Tue May 3 20:09:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 569116 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47B62C4167D for ; Tue, 3 May 2022 20:10:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234092AbiECUOF (ORCPT ); Tue, 3 May 2022 16:14:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48788 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242219AbiECUNq (ORCPT ); Tue, 3 May 2022 16:13:46 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 6A508403C9; Tue, 3 May 2022 13:10:12 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 90D5EBC0; Tue, 3 May 2022 23:10:45 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 90D5EBC0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1651608645; bh=zyEGv+36zyeeJ4S0Wls9R252Y4Cs1w7GDhpbUZted1Q=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=g6jrVKhZ7nju7RpINdXasQHUXXpaDxZ3bhf4C1Uq9WLVQn+xFQF2sIELjGYsi1aGB GG3O2BU5JrLX7YnVn+G26nL+f68CijLeAb9heTE5aA3/dhhdD2Hi21ixj8t6ZBT8Ua /PRCzyrgsdaxTxTub2OyUy5dIrpFGC+fRyhg3+Jg= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 3 May 2022 23:10:11 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Rob Herring , Krzysztof Kozlowski CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , , , Subject: [PATCH v2 12/23] dt-bindings: ata: ahci: Add platform capability properties Date: Tue, 3 May 2022 23:09:27 +0300 Message-ID: <20220503200938.18027-13-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220503200938.18027-1-Sergey.Semin@baikalelectronics.ru> References: <20220503200938.18027-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In case if the platform doesn't have BIOS or a comprehensive firmware installed then the HBA capability flags will be left uninitialized. As a good alternative we can define a set AHCI DT-node properties to describe all of HW-init capabilities flags. Luckily there aren't too many of them. SSS - Staggered Spin-up support and MPS - Mechanical Presence Switch support determine the corresponding feature availability for whole HBA by means of the "hba-sss" and "hba-smps" properties. Each port can have the "hba-{hpcp,mpsp,cpd,esp,fbscp}" defined indicatating that the port supports the next functionality: HPCP - HotPlug capable port, MPSP - Mechanical Presence Switch attached to a port, CPD - Cold Plug detection, ESP - External SATA Port (eSATA), FBSCP - FIS-based switching capable port. Signed-off-by: Serge Semin --- Alternatively we could define them as a bitfield, but having a set of boolean properties seemed a better idea since in that case we can implement a simple inter-dependency rules for them, which can't be done should we take the bitfields path. --- .../devicetree/bindings/ata/ahci-common.yaml | 66 +++++++++++++++++++ .../bindings/ata/ahci-platform.yaml | 11 ++++ 2 files changed, 77 insertions(+) diff --git a/Documentation/devicetree/bindings/ata/ahci-common.yaml b/Documentation/devicetree/bindings/ata/ahci-common.yaml index 70f915748270..371f5bd90639 100644 --- a/Documentation/devicetree/bindings/ata/ahci-common.yaml +++ b/Documentation/devicetree/bindings/ata/ahci-common.yaml @@ -75,6 +75,19 @@ properties: phy-names: const: sata-phy + hba-sss: + type: boolean + description: + Staggered Spin-up Support. Indicates whether the HBA supports the + staggered spin-up on its ports, for use in balancing power spikes. + + hba-smps: + type: boolean + description: + Mechanical Presence Switch Support. Indicates whether the HBA supports + mechanical presence switches on its ports for use in hot plug + operations. + ports-implemented: $ref: '/schemas/types.yaml#/definitions/uint32' description: @@ -97,6 +110,40 @@ patternProperties: minimum: 0 maximum: 31 + hba-hpcp: + type: boolean + description: + Hot Plug Capable Port. Indicates that this port’s signal and power + connectors are externally accessible via a joint signal and power + connector for blindmate device hot plug. It is mutually exclusive + with the ESP feature. + + hba-mpsp: + type: boolean + description: + Mechanical Presence Switch Attached to Port. Indicates whether + the platform an mechanical presence switch attached to this + port. + + hba-cpd: + type: boolean + description: + Cold Presence Detection. Indicates whether the platform supports + cold presence detection on this port. + + hba-esp: + type: boolean + description: + External SATA Port. Indicates that this port’s signal connector + is externally accessible on a signal only connector (e.g. eSATA + connector). + + hba-fbscp: + type: boolean + description: + FIS-based Switching Capable Port. Indicates whether this port + supports Port Multiplier FIS-based switching. + phys: description: Individual AHCI SATA port PHY maxItems: 1 @@ -111,6 +158,25 @@ patternProperties: required: - reg + # eSATA can't be enabled together with the HotPlug capability + oneOf: + - required: + - hba-hpcp + - required: + - hba-esp + - not: + anyOf: + - required: + - hba-hpcp + - required: + - hba-esp + + # HotPlug capability must be enabled together with Cold Plug + # Detection and Mechanical Presence Switching. + dependencies: + hba-cpd: ["hba-hpcp"] + hba-mpsp: ["hba-hpcp"] + additionalProperties: true required: diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.yaml b/Documentation/devicetree/bindings/ata/ahci-platform.yaml index 76075d3c8987..6cad7e86f3bb 100644 --- a/Documentation/devicetree/bindings/ata/ahci-platform.yaml +++ b/Documentation/devicetree/bindings/ata/ahci-platform.yaml @@ -117,14 +117,25 @@ examples: #address-cells = <1>; #size-cells = <0>; + hba-smps; + sata0: sata-port@0 { reg = <0>; + + hba-fbscp; + hba-esp; + phys = <&sata_phy 0>; target-supply = <®_sata0>; }; sata1: sata-port@1 { reg = <1>; + + hba-fbscp; + hba-hpcp; + hba-mpsp; + phys = <&sata_phy 1>; target-supply = <®_sata1>; }; From patchwork Tue May 3 20:09:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 569115 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C41E4C433EF for ; Tue, 3 May 2022 20:10:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231851AbiECUOJ (ORCPT ); Tue, 3 May 2022 16:14:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242262AbiECUNs (ORCPT ); Tue, 3 May 2022 16:13:48 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 8C21D38D; Tue, 3 May 2022 13:10:14 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id CB411BC2; Tue, 3 May 2022 23:10:47 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru CB411BC2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1651608647; bh=jCdYikKW5d7lD5eqc9AjF8QycAGAXvdMRkyDuad2vIQ=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=KeyjznIt6Wfs29n8CGlxuCGXESIgXDahjFeEo3sFQ98FCfmVMewxRD+37Qji3aqhR qOdDtZpDVRsKP+e0PSkGQQtFw+2TyhL+ZFBveRZlkJwshfWzqbqGQjPE5LFM/jYoKQ R8Y0SchDZKIHIKwsYOfS8UCBLqWXpdW5WA3240gc= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 3 May 2022 23:10:13 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Rob Herring , , , Subject: [PATCH v2 14/23] ata: libahci: Discard redundant force_port_map parameter Date: Tue, 3 May 2022 23:09:29 +0300 Message-ID: <20220503200938.18027-15-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220503200938.18027-1-Sergey.Semin@baikalelectronics.ru> References: <20220503200938.18027-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Currently there are four port-map-related fields declared in the ahci_host_priv structure and used to setup the HBA ports mapping. First the ports-mapping is read from the PI register and immediately stored in the saved_port_map field. If forced_port_map is initialized with non-zero value then its value will have greater priority over the value read from PI, thus it will override the saved_port_map field. That value will be then masked by a non-zero mask_port_map field and after some sanity checks it will be stored in the ahci_host_priv.port_map field as a final port mapping. As you can see the logic is a bit too complicated for such a simple task. We can freely get rid from at least one of the fields with no change to the implemented semantic. The force_port_map field can be replaced with taking non-zero saved_port_map value into account. So if saved_port_map is pre-initialized by the low level drivers (platform drivers) then it will have greater priority over the value read from PI register and will be used as actual HBA ports mapping later on. Thus the ports map forcing task will be just transferred from the force_port_map to saved_port_map field. This modification will perfectly fit into the feature of having OF-based initialization of the HW-init HBA CSR fields we are about to introduce in the next commit. Signed-off-by: Serge Semin --- drivers/ata/ahci.c | 2 +- drivers/ata/ahci.h | 1 - drivers/ata/libahci.c | 10 ++++++---- drivers/ata/libahci_platform.c | 2 +- 4 files changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index 397dfd27c90d..9bc8fa77e92f 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -656,7 +656,7 @@ static void ahci_pci_save_initial_config(struct pci_dev *pdev, { if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) { dev_info(&pdev->dev, "JMB361 has only one port\n"); - hpriv->force_port_map = 1; + hpriv->saved_port_map = 1; } /* diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h index f501531bd1b3..0e66446a5883 100644 --- a/drivers/ata/ahci.h +++ b/drivers/ata/ahci.h @@ -327,7 +327,6 @@ struct ahci_port_priv { struct ahci_host_priv { /* Input fields */ unsigned int flags; /* AHCI_HFLAG_* */ - u32 force_port_map; /* force port map */ u32 mask_port_map; /* mask out particular bits */ void __iomem * mmio; /* bus-independent mem map */ diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c index cf8c7fd59ada..000a7072614f 100644 --- a/drivers/ata/libahci.c +++ b/drivers/ata/libahci.c @@ -453,7 +453,6 @@ void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv) * reset. Values without are used for driver operation. */ hpriv->saved_cap = cap = readl(mmio + HOST_CAP); - hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); /* CAP2 register is only defined for AHCI 1.2 and later */ vers = readl(mmio + HOST_VERSION); @@ -517,10 +516,13 @@ void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv) cap &= ~HOST_CAP_SXS; } - if (hpriv->force_port_map && port_map != hpriv->force_port_map) { + /* Override the HBA ports mapping if the platform needs it */ + port_map = readl(mmio + HOST_PORTS_IMPL); + if (hpriv->saved_port_map && port_map != hpriv->saved_port_map) { dev_info(dev, "forcing port_map 0x%x -> 0x%x\n", - port_map, hpriv->force_port_map); - port_map = hpriv->force_port_map; + port_map, hpriv->saved_port_map); + port_map = hpriv->saved_port_map; + } else { hpriv->saved_port_map = port_map; } diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c index f5ee2f9d014b..56aced7a76cd 100644 --- a/drivers/ata/libahci_platform.c +++ b/drivers/ata/libahci_platform.c @@ -553,7 +553,7 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev, } of_property_read_u32(dev->of_node, - "ports-implemented", &hpriv->force_port_map); + "ports-implemented", &hpriv->saved_port_map); if (child_nodes) { for_each_child_of_node(dev->of_node, child) { From patchwork Tue May 3 20:09:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 569113 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0335BC433F5 for ; Tue, 3 May 2022 20:10:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242280AbiECUOO (ORCPT ); Tue, 3 May 2022 16:14:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49984 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242398AbiECUOE (ORCPT ); Tue, 3 May 2022 16:14:04 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id F2C29268; Tue, 3 May 2022 13:10:17 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 1A4E2BC5; Tue, 3 May 2022 23:10:51 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 1A4E2BC5 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1651608651; bh=0tT5W6mH0DshKtIGdNRZiGpshDPCxzFMGC1c/gF5izc=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=lV1bY1EIAzHsrnVnT+6kVHGNr+pJhX/H2Zlahk7GmA8giDbxA2EHxyHUVBUKFew7Z 5b7GxF1joAFIhf2JLPe17IOk4pHnNb2mtf2R+d5C9qc3IvKDtluXIf48qKN59obADn a/J8HQPi5fWjM0xObezowBxexmaowaBUbS31xV2A= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 3 May 2022 23:10:17 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Rob Herring , , , Subject: [PATCH v2 17/23] ata: ahci: Introduce firmware-specific caps initialization Date: Tue, 3 May 2022 23:09:32 +0300 Message-ID: <20220503200938.18027-18-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220503200938.18027-1-Sergey.Semin@baikalelectronics.ru> References: <20220503200938.18027-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org There are systems with no BIOS or comprehensive embedded firmware which could be able to properly initialize the SATA AHCI controller platform-specific capabilities. In that case a good alternative to having a clever bootloader is to create a device tree node with the properties well describing all the AHCI-related platform specifics. All the settings which are normally detected and marked as available in the HBA and its ports capabilities fields [1] could be defined in the platform DTB by means of a set of the dedicated properties. Such approach perfectly fits to the DTB-philosophy - to provide hardware/platform description. So here we suggest to extend the SATA AHCI device tree bindings with the next set of additional DT boolean properties: 1) hba-sss - Controller supports Staggered Spin-up. 2) hba-smps - Mechanical Presence Switch is support by controller. 3) hba-hpcp - Hot Plug Capable Port. 4) hba-mpsp - Mechanical Presence Switch Attached to Port. 5) hba-cpd - Cold Presence Detection. 6) hba-esp - External SATA Port. 7) hba-fbscp - FIS-based Switching Capable Port. All of these capabilities require to have a corresponding hardware configuration. Thus it's ok to have them defined in DTB. Even though the driver currently takes into account the state of the ESP and FBSCP flags state only, there is nothing wrong with having all them supported by the generic AHCI library in order to have a complete OF-based platform-capabilities initialization procedure. These properties will be parsed in the ahci_platform_get_resources() method and their values will be stored in the saved_* fields of the ahci_host_priv structure, which in its turn then will be used to restore the H.CAP, H.PI and P#.CMD capability fields on device init and after HBA reset. Please note this modification concerns the HW-init HBA and its ports flags only, which are by specification [1] are supposed to be initialized by the BIOS/platform firmware/expansion ROM and which are normally declared in the one-time-writable-after-reset register fields. Even though these flags aren't supposed to be cleared after HBA reset some AHCI instances may violate that rule so we still need to perform the fields resetting after each reset. Luckily the corresponding functionality has already been partly implemented in the framework of the ahci_save_initial_config() and ahci_restore_initial_config() methods. [1] Serial ATA AHCI 1.3.1 Specification, p. 103 Signed-off-by: Serge Semin --- drivers/ata/ahci.h | 1 + drivers/ata/libahci.c | 51 ++++++++++++++++++++++++++++------ drivers/ata/libahci_platform.c | 51 ++++++++++++++++++++++++++++++++-- 3 files changed, 92 insertions(+), 11 deletions(-) diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h index 8b9826533ae5..0de221055961 100644 --- a/drivers/ata/ahci.h +++ b/drivers/ata/ahci.h @@ -337,6 +337,7 @@ struct ahci_host_priv { u32 saved_cap; /* saved initial cap */ u32 saved_cap2; /* saved initial cap2 */ u32 saved_port_map; /* saved initial port_map */ + u32 saved_port_cap[AHCI_MAX_PORTS]; /* saved port_cap */ u32 em_loc; /* enclosure management location */ u32 em_buf_sz; /* EM buffer size in byte */ u32 em_msg_type; /* EM message type */ diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c index 1ffaa5f5f21a..763ff1058da6 100644 --- a/drivers/ata/libahci.c +++ b/drivers/ata/libahci.c @@ -16,6 +16,7 @@ * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf */ +#include #include #include #include @@ -443,16 +444,28 @@ static ssize_t ahci_show_em_supported(struct device *dev, void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv) { void __iomem *mmio = hpriv->mmio; - u32 cap, cap2, vers, port_map; + void __iomem *port_mmio; + unsigned long port_map; + u32 cap, cap2, vers; int i; /* make sure AHCI mode is enabled before accessing CAP */ ahci_enable_ahci(mmio); - /* Values prefixed with saved_ are written back to host after - * reset. Values without are used for driver operation. + /* + * Values prefixed with saved_ are written back to the HBA and ports + * registers after reset. Values without are used for driver operation. + */ + + /* + * Override HW-init HBA capability fields with platform-specific values. + * The rest of the HBA capabilities are defined with strictly RO flags + * and can't be modified in CSR anyway. */ - hpriv->saved_cap = cap = readl(mmio + HOST_CAP); + cap = readl(mmio + HOST_CAP); + if (hpriv->saved_cap) + cap = (cap & ~(HOST_CAP_SSS | HOST_CAP_MPS)) | hpriv->saved_cap; + hpriv->saved_cap = cap; /* CAP2 register is only defined for AHCI 1.2 and later */ vers = readl(mmio + HOST_VERSION); @@ -519,7 +532,7 @@ void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv) /* Override the HBA ports mapping if the platform needs it */ port_map = readl(mmio + HOST_PORTS_IMPL); if (hpriv->saved_port_map && port_map != hpriv->saved_port_map) { - dev_info(dev, "forcing port_map 0x%x -> 0x%x\n", + dev_info(dev, "forcing port_map 0x%lx -> 0x%x\n", port_map, hpriv->saved_port_map); port_map = hpriv->saved_port_map; } else { @@ -527,7 +540,7 @@ void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv) } if (hpriv->mask_port_map) { - dev_warn(dev, "masking port_map 0x%x -> 0x%x\n", + dev_warn(dev, "masking port_map 0x%lx -> 0x%lx\n", port_map, port_map & hpriv->mask_port_map); port_map &= hpriv->mask_port_map; @@ -546,7 +559,7 @@ void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv) */ if (map_ports > ahci_nr_ports(cap)) { dev_warn(dev, - "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n", + "implemented port map (0x%lx) contains more ports than nr_ports (%u), using nr_ports\n", port_map, ahci_nr_ports(cap)); port_map = 0; } @@ -555,12 +568,26 @@ void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv) /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */ if (!port_map && vers < 0x10300) { port_map = (1 << ahci_nr_ports(cap)) - 1; - dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map); + dev_warn(dev, "forcing PORTS_IMPL to 0x%lx\n", port_map); /* write the fixed up value to the PI register */ hpriv->saved_port_map = port_map; } + /* + * Preserve the ports capabilities defined by the platform. Note there + * is no need in storing the rest of the P#.CMD fields since they are + * volatile. + */ + for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) { + if (hpriv->saved_port_cap[i]) + continue; + + port_mmio = __ahci_port_base(hpriv, i); + hpriv->saved_port_cap[i] = + readl(port_mmio + PORT_CMD) & PORT_CMD_CAP; + } + /* record values to use during operation */ hpriv->cap = cap; hpriv->cap2 = cap2; @@ -590,13 +617,21 @@ EXPORT_SYMBOL_GPL(ahci_save_initial_config); static void ahci_restore_initial_config(struct ata_host *host) { struct ahci_host_priv *hpriv = host->private_data; + unsigned long port_map = hpriv->port_map; void __iomem *mmio = hpriv->mmio; + void __iomem *port_mmio; + int i; writel(hpriv->saved_cap, mmio + HOST_CAP); if (hpriv->saved_cap2) writel(hpriv->saved_cap2, mmio + HOST_CAP2); writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ + + for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) { + port_mmio = __ahci_port_base(hpriv, i); + writel(hpriv->saved_port_cap[i], port_mmio + PORT_CMD); + } } static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c index 56aced7a76cd..dece57364a3d 100644 --- a/drivers/ata/libahci_platform.c +++ b/drivers/ata/libahci_platform.c @@ -23,6 +23,7 @@ #include #include #include + #include "ahci.h" static void ahci_host_stop(struct ata_host *host); @@ -410,6 +411,44 @@ static int ahci_platform_get_regulator(struct ahci_host_priv *hpriv, u32 port, return rc; } +static int ahci_platform_get_firmware(struct ahci_host_priv *hpriv, + struct device *dev) +{ + struct device_node *child; + u32 port; + + of_property_read_u32(dev->of_node, + "ports-implemented", &hpriv->saved_port_map); + + if (of_property_read_bool(dev->of_node, "hba-sss")) + hpriv->saved_cap |= HOST_CAP_SSS; + if (of_property_read_bool(dev->of_node, "hba-smps")) + hpriv->saved_cap |= HOST_CAP_MPS; + + for_each_child_of_node(dev->of_node, child) { + if (!of_device_is_available(child)) + continue; + + if (of_property_read_u32(child, "reg", &port)) { + of_node_put(child); + return -EINVAL; + } + + if (of_property_read_bool(child, "hba-hpcp")) + hpriv->saved_port_cap[port] |= PORT_CMD_HPCP; + if (of_property_read_bool(child, "hba-mpsp")) + hpriv->saved_port_cap[port] |= PORT_CMD_MPSP; + if (of_property_read_bool(child, "hba-cpd")) + hpriv->saved_port_cap[port] |= PORT_CMD_CPD; + if (of_property_read_bool(child, "hba-esp")) + hpriv->saved_port_cap[port] |= PORT_CMD_ESP; + if (of_property_read_bool(child, "hba-fbscp")) + hpriv->saved_port_cap[port] |= PORT_CMD_FBSCP; + } + + return 0; +} + /** * ahci_platform_get_resources - Get platform resources * @pdev: platform device to get resources for @@ -552,9 +591,6 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev, goto err_out; } - of_property_read_u32(dev->of_node, - "ports-implemented", &hpriv->saved_port_map); - if (child_nodes) { for_each_child_of_node(dev->of_node, child) { u32 port; @@ -619,6 +655,15 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev, if (rc == -EPROBE_DEFER) goto err_out; } + + /* + * Retrieve firmware-specific flags which then will be used to set + * the HW-init fields of HBA and its ports + */ + rc = ahci_platform_get_firmware(hpriv, dev); + if (rc) + goto err_out; + pm_runtime_enable(dev); pm_runtime_get_sync(dev); hpriv->got_runtime_pm = true; From patchwork Tue May 3 20:09:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 569112 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 110B3C433EF for ; Tue, 3 May 2022 20:10:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240553AbiECUOQ (ORCPT ); Tue, 3 May 2022 16:14:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50356 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234537AbiECUOF (ORCPT ); Tue, 3 May 2022 16:14:05 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 21CEF314; Tue, 3 May 2022 13:10:20 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id F177ABC7; Tue, 3 May 2022 23:10:53 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru F177ABC7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1651608653; bh=JOMEm6g6eWeozoVB76D9aA5f5pDIgnUYwyU5xZ4hAu8=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=nO88eZLg66iirViRiPnPWO6n+mVPW57lx/sF59hJricXArXbr3SAoheopgVf0txqT hu8ICt+Xuw2WveWuNYsdyvzwb4qODPMjbtrl8MMb44CNSY3+rxmFYXWGjZpgzzA2gU IFbQu/rVlDKp7KCwzji/ETFmUw+h8kWacS5oK3KM= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 3 May 2022 23:10:19 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Serge Semin CC: Serge Semin , Alexey Malahov , Pavel Parkhomenko , Rob Herring , , , Subject: [PATCH v2 19/23] ata: ahci: Add DWC AHCI SATA controller support Date: Tue, 3 May 2022 23:09:34 +0300 Message-ID: <20220503200938.18027-20-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220503200938.18027-1-Sergey.Semin@baikalelectronics.ru> References: <20220503200938.18027-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Synopsys AHCI SATA controller can work pretty under with the generic AHCI-platform driver control. But there are vendor-specific peculiarities which can tune the device performance up and which may need to be fixed up for proper device functioning. In addition some DWC AHCI-based controllers may require small platform-specific fixups, so adding them in the generic AHCI driver would have ruined the code simplicity. Shortly speaking in order to keep the generic AHCI-platform code clean and have DWC AHCI SATA-specific features supported we suggest to add a dedicated DWC AHCI SATA device driver. Aside with the standard AHCI-platform resources getting, enabling/disabling and the controller registration the new driver performs the next actions. First of all there is a way to verify whether the HBA/ports capabilities activated in OF are correct. Almost all features availability is reflected in the vendor-specific parameters registers. So the DWC AHCI driver does the capabilities sanity check based on the corresponding fields state. Secondly if either the Command Completion Coalescing or the Device Sleep feature is enabled the DWC AHCI-specific internal 1ms timer must be fixed in accordance with the application clock signal frequency. In particular the timer value must be set to be Fapp * 1000. Normally the SoC designers pre-configure the TIMER1MS register to contain a correct value by default. But the platforms can support the application clock rate change. If that happens the 1ms timer value must be accordingly updated otherwise the dependent features won't work as expected. In the DWC AHCI driver we suggest to rely on the "aclk" reference clock rate to set the timer interval up. That clock source is supposed to be the AHCI SATA application clock in accordance with the DT bindings. Finally DWC AHCI SATA controller AXI/AHB bus DMA-engine can be tuned up to transfer up to 1024 * FIFO words at a time by setting the Tx/Rx transaction size in the DMA control register. The maximum value depends on the DMA data bus and AXI/AHB bus maximum burst length. In most of the cases it's better to set the maximum possible value to reach the best AHCI SATA controller performance. But sometimes in order to improve the system interconnect responsiveness, transferring in smaller data chunks may be more preferable. For such cases and for the case when the default value doesn't provide the best DMA bus performance we suggest to use the new HBA-port specific DT-properties "snps,{tx,rx}-ts-max" to tune the DMA transactions size up. After all the settings denoted above are handled the DWC AHCI SATA driver proceeds further with the standard AHCI-platform host initializations. Note since DWC AHCI controller is now have a dedicated driver we can discard the corresponding compatible string from the ahci-platform.c module. The same concerns "snps,spear-ahci" compatible string, which is also based on the DWC AHCI IP-core. Signed-off-by: Serge Semin --- Note there are three more AHCI SATA drivers which have been created for the devices based on the DWC AHCI SATA IP-core. It's AHCI SunXi, St and iMX drivers. Mostly they don't support the features implemented in this driver. So hopefully sometime in future they can be converted to be based on the generic DWC AHCI SATA driver and just perform some subvendor-specific setups in their own LLDD (glue) driver code. But for now let's leave the generic DWC AHCI SATA code as is. Hopefully the new DWC AHCI-based device drivers will try at least to re-use a part of the DWC AHCI driver methods if not being able to be integrated in the generic DWC driver code. Changelog v2: - Change the local objects prefix from 'dwc_ahci_' to 'ahci_dwc_'. (@Damien) --- drivers/ata/Kconfig | 10 + drivers/ata/Makefile | 1 + drivers/ata/ahci_dwc.c | 395 ++++++++++++++++++++++++++++++++++++ drivers/ata/ahci_platform.c | 2 - 4 files changed, 406 insertions(+), 2 deletions(-) create mode 100644 drivers/ata/ahci_dwc.c diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index bb45a9c00514..95e0e022b5bb 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -176,6 +176,16 @@ config AHCI_DM816 If unsure, say N. +config AHCI_DWC + tristate "Synopsys DWC AHCI SATA support" + select SATA_HOST + default SATA_AHCI_PLATFORM + help + This option enables support for the Synopsys DWC AHCI SATA + controller implementation. + + If unsure, say N. + config AHCI_ST tristate "ST AHCI SATA support" depends on ARCH_STI diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index b8aebfb14e82..34623365d9a6 100644 --- a/drivers/ata/Makefile +++ b/drivers/ata/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_AHCI_BRCM) += ahci_brcm.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_CEVA) += ahci_ceva.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_DA850) += ahci_da850.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_DM816) += ahci_dm816.o libahci.o libahci_platform.o +obj-$(CONFIG_AHCI_DWC) += ahci_dwc.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_IMX) += ahci_imx.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_MTK) += ahci_mtk.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o libahci.o libahci_platform.o diff --git a/drivers/ata/ahci_dwc.c b/drivers/ata/ahci_dwc.c new file mode 100644 index 000000000000..73380aaaebab --- /dev/null +++ b/drivers/ata/ahci_dwc.c @@ -0,0 +1,395 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DWC AHCI SATA Platform driver + * + * Copyright (C) 2021 BAIKAL ELECTRONICS, JSC + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ahci.h" + +#define DRV_NAME "ahci-dwc" + +#define AHCI_DWC_FBS_PMPN_MAX 15 + +/* DWC AHCI SATA controller specific registers */ +#define AHCI_DWC_HOST_OOBR 0xbc +#define AHCI_DWC_HOST_OOB_WE BIT(31) +#define AHCI_DWC_HOST_CWMIN_MASK GENMASK(30, 24) +#define AHCI_DWC_HOST_CWMAX_MASK GENMASK(23, 16) +#define AHCI_DWC_HOST_CIMIN_MASK GENMASK(15, 8) +#define AHCI_DWC_HOST_CIMAX_MASK GENMASK(7, 0) + +#define AHCI_DWC_HOST_GPCR 0xd0 +#define AHCI_DWC_HOST_GPSR 0xd4 + +#define AHCI_DWC_HOST_TIMER1MS 0xe0 +#define AHCI_DWC_HOST_TIMV_MASK GENMASK(19, 0) + +#define AHCI_DWC_HOST_GPARAM1R 0xe8 +#define AHCI_DWC_HOST_ALIGN_M BIT(31) +#define AHCI_DWC_HOST_RX_BUFFER BIT(30) +#define AHCI_DWC_HOST_PHY_DATA_MASK GENMASK(29, 28) +#define AHCI_DWC_HOST_PHY_RST BIT(27) +#define AHCI_DWC_HOST_PHY_CTRL_MASK GENMASK(26, 21) +#define AHCI_DWC_HOST_PHY_STAT_MASK GENMASK(20, 15) +#define AHCI_DWC_HOST_LATCH_M BIT(14) +#define AHCI_DWC_HOST_PHY_TYPE_MASK GENMASK(13, 11) +#define AHCI_DWC_HOST_RET_ERR BIT(10) +#define AHCI_DWC_HOST_AHB_ENDIAN_MASK GENMASK(9, 8) +#define AHCI_DWC_HOST_S_HADDR BIT(7) +#define AHCI_DWC_HOST_M_HADDR BIT(6) +#define AHCI_DWC_HOST_S_HDATA_MASK GENMASK(5, 3) +#define AHCI_DWC_HOST_M_HDATA_MASK GENMASK(2, 0) + +#define AHCI_DWC_HOST_GPARAM2R 0xec +#define AHCI_DWC_HOST_FBS_MEM_S BIT(19) +#define AHCI_DWC_HOST_FBS_PMPN_MASK GENMASK(17, 16) +#define AHCI_DWC_HOST_FBS_SUP BIT(15) +#define AHCI_DWC_HOST_DEV_CP BIT(14) +#define AHCI_DWC_HOST_DEV_MP BIT(13) +#define AHCI_DWC_HOST_ENCODE_M BIT(12) +#define AHCI_DWC_HOST_RXOOB_CLK_M BIT(11) +#define AHCI_DWC_HOST_RXOOB_M BIT(10) +#define AHCI_DWC_HOST_TXOOB_M BIT(9) +#define AHCI_DWC_HOST_RXOOB_M BIT(10) +#define AHCI_DWC_HOST_RXOOB_CLK_MASK GENMASK(8, 0) + +#define AHCI_DWC_HOST_PPARAMR 0xf0 +#define AHCI_DWC_HOST_TX_MEM_M BIT(11) +#define AHCI_DWC_HOST_TX_MEM_S BIT(10) +#define AHCI_DWC_HOST_RX_MEM_M BIT(9) +#define AHCI_DWC_HOST_RX_MEM_S BIT(8) +#define AHCI_DWC_HOST_TXFIFO_DEPTH GENMASK(7, 4) +#define AHCI_DWC_HOST_RXFIFO_DEPTH GENMASK(3, 0) + +#define AHCI_DWC_HOST_TESTR 0xf4 +#define AHCI_DWC_HOST_PSEL_MASK GENMASK(18, 16) +#define AHCI_DWC_HOST_TEST_IF BIT(0) + +#define AHCI_DWC_HOST_VERSIONR 0xf8 +#define AHCI_DWC_HOST_IDR 0xfc + +#define AHCI_DWC_PORT_DMACR 0x70 +#define AHCI_DWC_PORT_RXABL_MASK GENMASK(15, 12) +#define AHCI_DWC_PORT_TXABL_MASK GENMASK(11, 8) +#define AHCI_DWC_PORT_RXTS_MASK GENMASK(7, 4) +#define AHCI_DWC_PORT_TXTS_MASK GENMASK(3, 0) +#define AHCI_DWC_PORT_PHYCR 0x74 +#define AHCI_DWC_PORT_PHYSR 0x78 + +struct ahci_dwc_host_priv { + struct platform_device *pdev; + + u32 timv; + u32 dmacr[AHCI_MAX_PORTS]; +}; + +static struct ahci_host_priv *ahci_dwc_get_resources(struct platform_device *pdev) +{ + struct ahci_dwc_host_priv *dpriv; + struct ahci_host_priv *hpriv; + + dpriv = devm_kzalloc(&pdev->dev, sizeof(*dpriv), GFP_KERNEL); + if (!dpriv) + return ERR_PTR(-ENOMEM); + + dpriv->pdev = pdev; + + hpriv = ahci_platform_get_resources(pdev, AHCI_PLATFORM_GET_RESETS); + if (IS_ERR(hpriv)) + return hpriv; + + hpriv->plat_data = (void *)dpriv; + + return hpriv; +} + +static void ahci_dwc_check_cap(struct ahci_host_priv *hpriv) +{ + unsigned long port_map = hpriv->saved_port_map | hpriv->mask_port_map; + struct ahci_dwc_host_priv *dpriv = hpriv->plat_data; + bool dev_mp, dev_cp, fbs_sup; + unsigned int fbs_pmp; + u32 param; + int i; + + param = readl(hpriv->mmio + AHCI_DWC_HOST_GPARAM2R); + dev_mp = !!(param & AHCI_DWC_HOST_DEV_MP); + dev_cp = !!(param & AHCI_DWC_HOST_DEV_CP); + fbs_sup = !!(param & AHCI_DWC_HOST_FBS_SUP); + fbs_pmp = 5 * FIELD_GET(AHCI_DWC_HOST_FBS_PMPN_MASK, param); + + if (!dev_mp && hpriv->saved_cap & HOST_CAP_MPS) { + dev_warn(&dpriv->pdev->dev, "MPS is unsupported\n"); + hpriv->saved_cap &= ~HOST_CAP_MPS; + } + + + if (fbs_sup && fbs_pmp < AHCI_DWC_FBS_PMPN_MAX) { + dev_warn(&dpriv->pdev->dev, "PMPn is limited up to %u ports\n", + fbs_pmp); + } + + for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) { + if (!dev_mp && hpriv->saved_port_cap[i] & PORT_CMD_MPSP) { + dev_warn(&dpriv->pdev->dev, "MPS incapable port %d\n", i); + hpriv->saved_port_cap[i] &= ~PORT_CMD_MPSP; + } + + if (!dev_cp && hpriv->saved_port_cap[i] & PORT_CMD_CPD) { + dev_warn(&dpriv->pdev->dev, "CPD incapable port %d\n", i); + hpriv->saved_port_cap[i] &= ~PORT_CMD_CPD; + } + + if (!fbs_sup && hpriv->saved_port_cap[i] & PORT_CMD_FBSCP) { + dev_warn(&dpriv->pdev->dev, "FBS incapable port %d\n", i); + hpriv->saved_port_cap[i] &= ~PORT_CMD_FBSCP; + } + } +} + +static void ahci_dwc_init_timer(struct ahci_host_priv *hpriv) +{ + struct ahci_dwc_host_priv *dpriv = hpriv->plat_data; + unsigned long rate; + struct clk *aclk; + u32 cap, cap2; + + /* 1ms tick is generated only for the CCC or DevSleep features */ + cap = readl(hpriv->mmio + HOST_CAP); + cap2 = readl(hpriv->mmio + HOST_CAP2); + if (!(cap & HOST_CAP_CCC) && !(cap2 & HOST_CAP2_SDS)) + return; + + /* + * Tick is generated based on the AXI/AHB application clocks signal + * so we need to be sure in the clock we are going to use. + */ + aclk = ahci_platform_find_clk(hpriv, "aclk"); + if (!aclk) + return; + + /* 1ms timer interval is set as TIMV = AMBA_FREQ[MHZ] * 1000 */ + dpriv->timv = readl(hpriv->mmio + AHCI_DWC_HOST_TIMER1MS); + dpriv->timv = FIELD_GET(AHCI_DWC_HOST_TIMV_MASK, dpriv->timv); + rate = clk_get_rate(aclk) / 1000UL; + if (rate == dpriv->timv) + return; + + dev_info(&dpriv->pdev->dev, "Update CCC/DevSlp timer for Fapp %lu MHz\n", + rate / 1000UL); + dpriv->timv = FIELD_PREP(AHCI_DWC_HOST_TIMV_MASK, rate); + writel(dpriv->timv, hpriv->mmio + AHCI_DWC_HOST_TIMER1MS); +} + +static int ahci_dwc_init_dmacr(struct ahci_host_priv *hpriv) +{ + struct ahci_dwc_host_priv *dpriv = hpriv->plat_data; + struct device_node *child; + void __iomem *port_mmio; + u32 port, dmacr, ts; + + /* + * Update the DMA Tx/Rx transaction sizes in accordance with the + * platform setup. Note values exceeding maximal or minimal limits will + * be automatically clamped. Also note the register isn't affected by + * the HBA global reset so we can freely initialize it once until the + * next system reset. + */ + for_each_child_of_node(dpriv->pdev->dev.of_node, child) { + if (!of_device_is_available(child)) + continue; + + if (of_property_read_u32(child, "reg", &port)) { + of_node_put(child); + return -EINVAL; + } + + port_mmio = __ahci_port_base(hpriv, port); + dmacr = readl(port_mmio + AHCI_DWC_PORT_DMACR); + + if (!of_property_read_u32(child, "snps,tx-ts-max", &ts)) { + ts = ilog2(ts); + dmacr &= ~AHCI_DWC_PORT_TXTS_MASK; + dmacr |= FIELD_PREP(AHCI_DWC_PORT_TXTS_MASK, ts); + } + + if (!of_property_read_u32(child, "snps,rx-ts-max", &ts)) { + ts = ilog2(ts); + dmacr &= ~AHCI_DWC_PORT_RXTS_MASK; + dmacr |= FIELD_PREP(AHCI_DWC_PORT_RXTS_MASK, ts); + } + + writel(dmacr, port_mmio + AHCI_DWC_PORT_DMACR); + dpriv->dmacr[port] = dmacr; + } + + return 0; +} + +static int ahci_dwc_init_host(struct ahci_host_priv *hpriv) +{ + int rc; + + rc = ahci_platform_enable_resources(hpriv); + if (rc) + return rc; + + ahci_dwc_check_cap(hpriv); + + ahci_dwc_init_timer(hpriv); + + rc = ahci_dwc_init_dmacr(hpriv); + if (rc) + goto err_disable_resources; + + return 0; + +err_disable_resources: + ahci_platform_disable_resources(hpriv); + + return rc; +} + +static int ahci_dwc_reinit_host(struct ahci_host_priv *hpriv) +{ + struct ahci_dwc_host_priv *dpriv = hpriv->plat_data; + unsigned long port_map = hpriv->port_map; + void __iomem *port_mmio; + int i, rc; + + rc = ahci_platform_enable_resources(hpriv); + if (rc) + return rc; + + writel(dpriv->timv, hpriv->mmio + AHCI_DWC_HOST_TIMER1MS); + + for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) { + port_mmio = __ahci_port_base(hpriv, i); + writel(dpriv->dmacr[i], port_mmio + AHCI_DWC_PORT_DMACR); + } + + return 0; +} + +static void ahci_dwc_clear_host(struct ahci_host_priv *hpriv) +{ + ahci_platform_disable_resources(hpriv); +} + +static void ahci_dwc_stop_host(struct ata_host *host) +{ + struct ahci_host_priv *hpriv = host->private_data; + + ahci_dwc_clear_host(hpriv); +} + +static struct ata_port_operations ahci_dwc_port_ops = { + .inherits = &ahci_platform_ops, + .host_stop = ahci_dwc_stop_host, +}; + +static const struct ata_port_info ahci_dwc_port_info = { + .flags = AHCI_FLAG_COMMON, + .pio_mask = ATA_PIO4, + .udma_mask = ATA_UDMA6, + .port_ops = &ahci_dwc_port_ops, +}; + +static struct scsi_host_template ahci_dwc_scsi_info = { + AHCI_SHT(DRV_NAME), +}; + +static int ahci_dwc_probe(struct platform_device *pdev) +{ + struct ahci_host_priv *hpriv; + int rc; + + hpriv = ahci_dwc_get_resources(pdev); + if (IS_ERR(hpriv)) + return PTR_ERR(hpriv); + + rc = ahci_dwc_init_host(hpriv); + if (rc) + return rc; + + rc = ahci_platform_init_host(pdev, hpriv, &ahci_dwc_port_info, + &ahci_dwc_scsi_info); + if (rc) + goto err_clear_host; + + return 0; + +err_clear_host: + ahci_dwc_clear_host(hpriv); + + return rc; +} + +#ifdef CONFIG_PM_SLEEP +static int ahci_dwc_suspend(struct device *dev) +{ + struct ata_host *host = dev_get_drvdata(dev); + struct ahci_host_priv *hpriv = host->private_data; + int rc; + + rc = ahci_platform_suspend_host(dev); + if (rc) + return rc; + + ahci_dwc_clear_host(hpriv); + + return 0; +} + +static int ahci_dwc_resume(struct device *dev) +{ + struct ata_host *host = dev_get_drvdata(dev); + struct ahci_host_priv *hpriv = host->private_data; + int rc; + + rc = ahci_dwc_reinit_host(hpriv); + if (rc) + return rc; + + return ahci_platform_resume_host(dev); +} +#endif + +static SIMPLE_DEV_PM_OPS(ahci_dwc_pm_ops, ahci_dwc_suspend, ahci_dwc_resume); + +static const struct of_device_id ahci_dwc_of_match[] = { + { .compatible = "snps,dwc-ahci", }, + { .compatible = "snps,spear-ahci", }, + {}, +}; +MODULE_DEVICE_TABLE(of, ahci_dwc_of_match); + +static struct platform_driver ahci_dwc_driver = { + .probe = ahci_dwc_probe, + .remove = ata_platform_remove_one, + .shutdown = ahci_platform_shutdown, + .driver = { + .name = DRV_NAME, + .of_match_table = ahci_dwc_of_match, + .pm = &ahci_dwc_pm_ops, + }, +}; +module_platform_driver(ahci_dwc_driver); + +MODULE_DESCRIPTION("DWC AHCI SATA platform driver"); +MODULE_AUTHOR("Serge Semin "); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c index 9b56490ecbc3..8f5572a9f8f1 100644 --- a/drivers/ata/ahci_platform.c +++ b/drivers/ata/ahci_platform.c @@ -80,9 +80,7 @@ static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend, static const struct of_device_id ahci_of_match[] = { { .compatible = "generic-ahci", }, /* Keep the following compatibles for device tree compatibility */ - { .compatible = "snps,spear-ahci", }, { .compatible = "ibm,476gtr-ahci", }, - { .compatible = "snps,dwc-ahci", }, { .compatible = "hisilicon,hisi-ahci", }, { .compatible = "cavium,octeon-7130-ahci", }, { /* sentinel */ } From patchwork Tue May 3 20:09:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 569111 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DF24C433F5 for ; Tue, 3 May 2022 20:12:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236285AbiECUPi (ORCPT ); Tue, 3 May 2022 16:15:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50284 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242414AbiECUOF (ORCPT ); Tue, 3 May 2022 16:14:05 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 9D7EFFD2C; Tue, 3 May 2022 13:10:22 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 0FFD2BC8; Tue, 3 May 2022 23:10:55 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 0FFD2BC8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1651608655; bh=0MZ3pFwaoAf1KuXrTCdk8j1jnXWBxdE74VDIFr7flf0=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=muVqa5LOcnJYIQdX+RQvvnpV1L5o/X7RFI/pRWD3EfdhMFWfXKMjjQ8m2l7yx7YGc omUkwu7Nr+rysYY2zs2MHvzZ4AhjCPkuQxcQaryzhmYYA3QV90Xn6CsGPi1r8kKWXG 8kfUUlW0Z1txPpe63sPLVVpO/62VC/f8mJEdHAZM= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 3 May 2022 23:10:21 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Serge Semin , Rob Herring , Krzysztof Kozlowski CC: Serge Semin , Alexey Malahov , Pavel Parkhomenko , , , Subject: [PATCH v2 20/23] dt-bindings: ata: ahci: Add Baikal-T1 AHCI SATA controller DT schema Date: Tue, 3 May 2022 23:09:35 +0300 Message-ID: <20220503200938.18027-21-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220503200938.18027-1-Sergey.Semin@baikalelectronics.ru> References: <20220503200938.18027-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Baikal-T1 AHCI controller is based on the DWC AHCI SATA IP-core v4.10a with the next specific settings: two SATA ports, cascaded CSR access based on two clock domains (APB and AXI), selectable source of the reference clock (though stable work is currently available from the external source only), two reset lanes for the application and SATA ports domains. Other than that the device is fully compatible with the generic DWC AHCI SATA bindings. Signed-off-by: Serge Semin --- Changelog v2: - Rename 'syscon' property to 'baikal,bt1-syscon'. - Drop macro usage from the example node. --- .../bindings/ata/baikal,bt1-ahci.yaml | 127 ++++++++++++++++++ 1 file changed, 127 insertions(+) create mode 100644 Documentation/devicetree/bindings/ata/baikal,bt1-ahci.yaml diff --git a/Documentation/devicetree/bindings/ata/baikal,bt1-ahci.yaml b/Documentation/devicetree/bindings/ata/baikal,bt1-ahci.yaml new file mode 100644 index 000000000000..7c2eae75434f --- /dev/null +++ b/Documentation/devicetree/bindings/ata/baikal,bt1-ahci.yaml @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/baikal,bt1-ahci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Baikal-T1 SoC AHCI SATA controller + +maintainers: + - Serge Semin + +description: | + AHCI SATA controller embedded into the Baikal-T1 SoC is based on the + DWC AHCI SATA v4.10a IP-core. + +allOf: + - $ref: snps,dwc-ahci.yaml# + +properties: + compatible: + contains: + const: baikal,bt1-ahci + + clocks: + items: + - description: Peripheral APB bus clock source + - description: Application AXI BIU clock + - description: Internal SATA Ports reference clock + - description: External SATA Ports reference clock + + clock-names: + items: + - const: pclk + - const: aclk + - const: ref_int + - const: ref_ext + + resets: + items: + - description: Application AXI BIU domain reset + - description: SATA Ports clock domain reset + + reset-names: + items: + - const: arst + - const: ref + + baikal,bt1-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle reference to the CCU system controller. It is required to + switch between internal and external SATA reference clock sources. + + ports-implemented: + maximum: 0x3 + +patternProperties: + "^sata-port@[0-9a-e]$": + type: object + + properties: + reg: + minimum: 0 + maximum: 1 + + snps,tx-ts-max: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Due to having AXI3 bus interface utilized the maximum Tx DMA + transaction size can't exceed 16 beats (AxLEN[3:0]). + minimum: 1 + maximum: 16 + + snps,rx-ts-max: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Due to having AXI3 bus interface utilized the maximum Rx DMA + transaction size can't exceed 16 beats (AxLEN[3:0]). + minimum: 1 + maximum: 16 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - baikal,bt1-syscon + +unevaluatedProperties: false + +examples: + - | + sata@1f050000 { + compatible = "baikal,bt1-ahci", "snps,dwc-ahci"; + reg = <0x1f050000 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + + interrupts = <0 64 4>; + + clocks = <&ccu_sys 1>, <&ccu_axi 2>, <&ccu_sys 0>, <&clk_sata>; + clock-names = "pclk", "aclk", "ref_int", "ref_ext"; + + resets = <&ccu_axi 2>, <&ccu_sys 0>; + reset-names = "arst", "ref"; + + baikal,bt1-syscon = <&syscon>; + + ports-implemented = <0x3>; + + sata-port@0 { + reg = <0>; + + snps,tx-ts-max = <4>; + snps,rx-ts-max = <4>; + }; + + sata-port@1 { + reg = <1>; + + snps,tx-ts-max = <4>; + snps,rx-ts-max = <4>; + }; + }; +... From patchwork Tue May 3 20:09:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 569114 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9CBFC433FE for ; Tue, 3 May 2022 20:10:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242251AbiECUOM (ORCPT ); Tue, 3 May 2022 16:14:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50092 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242407AbiECUOE (ORCPT ); Tue, 3 May 2022 16:14:04 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id B05B710FC5; Tue, 3 May 2022 13:10:24 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 10159BCA; Tue, 3 May 2022 23:10:57 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 10159BCA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1651608657; bh=W0zpVpyp21FcmZKKvGW6SPQXo73H6PMb/goz++F2IU4=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=MjTejYhr15EERK9tdO2fZAuNOrK5W0o3yj/CYvRsrxO5OsbUreTyIqUQdUJHUvuLV oQNsMIjddihdpGn3avu1VLHiGLWRKdJmsrBGwK0m34LCGOn5P3kgdYdPruGkrO/aFo szr5xAomabj24jgNVmmLKzQ/pRRM3yEt/lZ3JZuQ= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 3 May 2022 23:10:23 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Serge Semin CC: Serge Semin , Alexey Malahov , Pavel Parkhomenko , Rob Herring , , , Subject: [PATCH v2 22/23] ata: ahci-dwc: Add Baikal-T1 AHCI SATA interface support Date: Tue, 3 May 2022 23:09:37 +0300 Message-ID: <20220503200938.18027-23-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220503200938.18027-1-Sergey.Semin@baikalelectronics.ru> References: <20220503200938.18027-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org It's almost fully compatible DWC AHCI SATA IP-core derivative except the reference clocks source, which need to be very carefully selected. In particular the DWC AHCI SATA PHY can be clocked either from the pads ref_pad_clk_{m,p} or from the internal wires ref_alt_clk_{m,n}. In the later case the clock signal is generated from the Baikal-T1 CCU SATA PLL. The clocks source is selected by means of the ref_use_pad wire connected to the CCU SATA reference clock CSR. In normal situation it would be much more handy to use the internal reference clock source, but alas we haven't managed to make the AHCI controller working well with it so far. So it's preferable to have the controller clocked from the external clock generator and fallback to the internal clock source only as a last resort. Other than that the controller is full compatible with the DWC AHCI SATA IP-core. Signed-off-by: Serge Semin --- Changelog v2: - Rename 'syscon' property to 'baikal,bt1-syscon'. - Change the local objects prefix from 'dwc_ahci_' to 'ahci_dwc_', from 'bt1_ahci_' to 'ahci_bt1_'. (@Damien) --- drivers/ata/Kconfig | 1 + drivers/ata/ahci_dwc.c | 87 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 88 insertions(+) diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 95e0e022b5bb..249717cdc74f 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -180,6 +180,7 @@ config AHCI_DWC tristate "Synopsys DWC AHCI SATA support" select SATA_HOST default SATA_AHCI_PLATFORM + select MFD_SYSCON if (MIPS_BAIKAL_T1 || COMPILE_TEST) help This option enables support for the Synopsys DWC AHCI SATA controller implementation. diff --git a/drivers/ata/ahci_dwc.c b/drivers/ata/ahci_dwc.c index f987efa1ad59..d464db20f869 100644 --- a/drivers/ata/ahci_dwc.c +++ b/drivers/ata/ahci_dwc.c @@ -13,10 +13,12 @@ #include #include #include +#include #include #include #include #include +#include #include "ahci.h" @@ -90,6 +92,26 @@ #define AHCI_DWC_PORT_PHYCR 0x74 #define AHCI_DWC_PORT_PHYSR 0x78 +/* Baikal-T1 AHCI SATA specific registers */ +#define AHCI_BT1_HOST_PHYCR AHCI_DWC_HOST_GPCR +#define AHCI_BT1_HOST_MPLM_MASK GENMASK(29, 23) +#define AHCI_BT1_HOST_LOSDT_MASK GENMASK(22, 20) +#define AHCI_BT1_HOST_CRR BIT(19) +#define AHCI_BT1_HOST_CRW BIT(18) +#define AHCI_BT1_HOST_CRCD BIT(17) +#define AHCI_BT1_HOST_CRCA BIT(16) +#define AHCI_BT1_HOST_CRDI_MASK GENMASK(15, 0) + +#define AHCI_BT1_HOST_PHYSR AHCI_DWC_HOST_GPSR +#define AHCI_BT1_HOST_CRA BIT(16) +#define AHCI_BT1_HOST_CRDO_MASK GENMASK(15, 0) + +/* Baikal-T1 CCU registers concerning the AHCI SATA module */ +#define BT1_CCU_SYS_SATA_REF 0x60 +#define BT1_CCU_SYS_SATA_REF_EXT BIT(28) +#define BT1_CCU_SYS_SATA_REF_INV BIT(29) +#define BT1_CCU_SYS_SATA_REF_BUF BIT(30) + struct ahci_dwc_plat_data { unsigned int pflags; unsigned int hflags; @@ -106,6 +128,65 @@ struct ahci_dwc_host_priv { u32 dmacr[AHCI_MAX_PORTS]; }; +static int ahci_bt1_init(struct ahci_host_priv *hpriv) +{ + struct ahci_dwc_host_priv *dpriv = hpriv->plat_data; + struct regmap *sys_regs; + u32 ref_ctl, mask; + + /* APB and application clocks are required */ + if (!ahci_platform_find_clk(hpriv, "pclk") || + !ahci_platform_find_clk(hpriv, "aclk")) { + dev_err(&dpriv->pdev->dev, "No system clocks specified\n"); + return -EINVAL; + } + + /* + * We need to select the PHY reference clock source. The signal + * can be delivered either from the chip pads or from the internal + * PLL. The source is selected by the PHY's ref_use_pad signal + * tied up into one of the CCU SATA ref-ctl register field. + */ + sys_regs = syscon_regmap_lookup_by_phandle(dpriv->pdev->dev.of_node, + "baikal,bt1-syscon"); + if (IS_ERR(sys_regs)) { + dev_err(&dpriv->pdev->dev, "CCU syscon couldn't be found\n"); + return PTR_ERR(sys_regs); + } + + (void)regmap_read(sys_regs, BT1_CCU_SYS_SATA_REF, &ref_ctl); + + /* + * Prefer activating external reference clock if one is supplied. + * If there is no external ref clock, then we have no choice but + * to fall back to the internal signal coming from PLL. Alas + * we haven't managed to make the interface working well when it's + * used so far, but in no alternative let's at least try... + */ + if (ahci_platform_find_clk(hpriv, "ref_ext")) { + ref_ctl |= BT1_CCU_SYS_SATA_REF_EXT; + mask = BT1_CCU_SYS_SATA_REF_EXT; + } else if (ahci_platform_find_clk(hpriv, "ref_int")) { + ref_ctl &= ~BT1_CCU_SYS_SATA_REF_EXT; + ref_ctl |= BT1_CCU_SYS_SATA_REF_INV | BT1_CCU_SYS_SATA_REF_BUF; + mask = BT1_CCU_SYS_SATA_REF_EXT | + BT1_CCU_SYS_SATA_REF_INV | BT1_CCU_SYS_SATA_REF_BUF; + dev_warn(&dpriv->pdev->dev, "Fallback to PLL-based ref clock!\n"); + } else { + dev_err(&dpriv->pdev->dev, "No ref clock specified\n"); + return -EINVAL; + } + + regmap_update_bits(sys_regs, BT1_CCU_SYS_SATA_REF, mask, ref_ctl); + + /* + * Fully reset the SATA AXI and ref clocks domain so to ensure the + * state machine is working from scratch. + */ + ahci_platform_assert_rsts(hpriv); + return ahci_platform_deassert_rsts(hpriv); +} + static struct ahci_host_priv *ahci_dwc_get_resources(struct platform_device *pdev) { struct ahci_dwc_host_priv *dpriv; @@ -415,9 +496,15 @@ struct ahci_dwc_plat_data ahci_dwc_plat = { .pflags = AHCI_PLATFORM_GET_RESETS, }; +struct ahci_dwc_plat_data ahci_bt1_plat = { + .pflags = AHCI_PLATFORM_GET_RESETS | AHCI_PLATFORM_RST_TRIGGER, + .init = ahci_bt1_init, +}; + static const struct of_device_id ahci_dwc_of_match[] = { { .compatible = "snps,dwc-ahci", &ahci_dwc_plat }, { .compatible = "snps,spear-ahci", &ahci_dwc_plat }, + { .compatible = "baikal,bt1-ahci", &ahci_bt1_plat }, {}, }; MODULE_DEVICE_TABLE(of, ahci_dwc_of_match);