From patchwork Mon Dec 31 18:55:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 154630 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp11197372ljp; Mon, 31 Dec 2018 10:55:48 -0800 (PST) X-Google-Smtp-Source: ALg8bN4Opp4BUPCeczm0iwe20mYnnfD99EURDpS33u2bLIp5dItcImzlrfTOJNekAk0CQdrC8Mn1 X-Received: by 2002:a17:902:4124:: with SMTP id e33mr37847139pld.236.1546282548180; Mon, 31 Dec 2018 10:55:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546282548; cv=none; d=google.com; s=arc-20160816; b=NNqKQM5KVdHEs09hiZDd4b8bO9UaFYb0i6Qh23B4ksb1VhV2BtH9fcrpcNHWZNhVRR V1gmcL+IyQjJ/NJIDp5eQj4CGp+Olan9ijmQnA3vtmkGI4QlytizllKrhnGjjhfCmwrt Ue5l41HQ3XGXO5LsjLhB7y2eQLVen1FqWajRB/+7tI4pHdcHc6iT0wbDKMrjB84HXcQa uVI4Bz4vKuXbN3KeMQAFXeE/s87npav1vpP8hryAY9p5uTYcbbMXY/M4HgHOpV6xsGIZ jUA5kUeQ9IujHe6s/7NgdluqBhHKlay5KlNSzhnWdzriDMSpr1EnENBAhsoJYyuB52i0 Q19Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=wGON2lybsGy7FC0OgCUYudVtpokObJD+vq+U001MecQ=; b=H64jNWKYki2XIZcMnP0PoJrb80dbRQHGUDbGDGTXqMTVGpftegF8Gb9FvIjWIY+bCx ESC+Viq+HFSERDb91w+Mh+KkkNgNq/sZ3fkFCf69Du9RO1saUd+sBonDSjteiR1qdNkH Ub6AK8aahSB5GeGCqk8p+B5QM4/+N3fOL/L7YlA3d25/uVOHmPp+ZvgRj5S17KDlZlsP PNODQXUWDAjn1sIbU6kwXWNHo+qO+RUpJFhfS2Cs6Jeu8OLKjDLVTNI/9Tr9v439OGrx ZXnY/c2lGPooWC7IVKsKlcbWE/psMd1rz4GcbH5EG3TClfBuYIEPlI68AFRRf/nvaTP9 apxw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=X8Tt52Jc; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o195si8652274pfg.106.2018.12.31.10.55.47; Mon, 31 Dec 2018 10:55:48 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=X8Tt52Jc; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727777AbeLaSzp (ORCPT + 7 others); Mon, 31 Dec 2018 13:55:45 -0500 Received: from mail-pl1-f195.google.com ([209.85.214.195]:36212 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727772AbeLaSzp (ORCPT ); Mon, 31 Dec 2018 13:55:45 -0500 Received: by mail-pl1-f195.google.com with SMTP id g9so12896349plo.3 for ; Mon, 31 Dec 2018 10:55:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wGON2lybsGy7FC0OgCUYudVtpokObJD+vq+U001MecQ=; b=X8Tt52JcCR8ZkeN2DDakfZzHCPRVV4UzdKgl85bFhx1Btuy/aWNp56Wa1wbQuEAxvX /6FPeBENCGfp9th/naRoCzH1Em3pitOhqvpb8ASdME5jGaStYrLVfWR45Km9V/MoK3RH 9hQfv8eqdpXnFgZsEYmGWIB+ds0g8icOp38qw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wGON2lybsGy7FC0OgCUYudVtpokObJD+vq+U001MecQ=; b=pK3pHhPrjSCtBQGgRVknB3/s6H/tX7EcD5ekgnyZ2j2FsZy/VVG16C8ZIUSpHl7WvS 5glQQy9jiaLYH1I4+N2GZmutLr6TYtU3pK+mrfE9Ks0ClMR4TJ+dhTRfk4La9snjzzu4 /icWhO/rrUzsOQQ1g75j0GJBA0Z2r4b1WzfaiLj8AGS7mIWO1EHdEDD8DhB0hPKICrFw srZ0eboxFIwgvSX5WWS9H0Xlvmw1/fhRPKjaVpi7F930AcnW6wAbB+H0XWAsDbSSn+J+ 00XS+rK2FlmDCLiQcys3uLsXiVLDOtKbHlTwCgJW5oaL28DNpNWzZa5IfIp3aGiO4+z3 W3ow== X-Gm-Message-State: AJcUukfQ6Wz8t4413iTxakB+1A6IlLi+lpiGBWKNApvLnLpRIPlHhXQT 9eH6lUca380q+4HBXs4X0o32 X-Received: by 2002:a17:902:c05:: with SMTP id 5mr38534757pls.155.1546282544662; Mon, 31 Dec 2018 10:55:44 -0800 (PST) Received: from localhost.localdomain ([2405:204:7440:b882:8d58:e15f:9ff4:efc2]) by smtp.gmail.com with ESMTPSA id s9sm66146224pgl.88.2018.12.31.10.55.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 31 Dec 2018 10:55:44 -0800 (PST) From: Manivannan Sadhasivam To: sboyd@kernel.org, mturquette@baylibre.com, afaerber@suse.de, robh+dt@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 1/6] clk: actions: Add configurable PLL delay Date: Tue, 1 Jan 2019 00:25:12 +0530 Message-Id: <20181231185517.18517-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181231185517.18517-1-manivannan.sadhasivam@linaro.org> References: <20181231185517.18517-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org S500 SoC requires configurable delay for different PLLs. Hence, add a separate macro for declaring a PLL with configurable delay and also modify the existing OWL_PLL_NO_PARENT macro to use default delay so that no need to modify the existing S700/S900 drivers. Signed-off-by: Manivannan Sadhasivam --- drivers/clk/actions/owl-pll.c | 2 +- drivers/clk/actions/owl-pll.h | 30 ++++++++++++++++++++++++------ 2 files changed, 25 insertions(+), 7 deletions(-) -- 2.17.1 diff --git a/drivers/clk/actions/owl-pll.c b/drivers/clk/actions/owl-pll.c index 058e06d7099f..02437bdedf4d 100644 --- a/drivers/clk/actions/owl-pll.c +++ b/drivers/clk/actions/owl-pll.c @@ -179,7 +179,7 @@ static int owl_pll_set_rate(struct clk_hw *hw, unsigned long rate, regmap_write(common->regmap, pll_hw->reg, reg); - udelay(PLL_STABILITY_WAIT_US); + udelay(pll_hw->delay); return 0; } diff --git a/drivers/clk/actions/owl-pll.h b/drivers/clk/actions/owl-pll.h index 0aae30abd5dc..6fb0d45bb088 100644 --- a/drivers/clk/actions/owl-pll.h +++ b/drivers/clk/actions/owl-pll.h @@ -13,6 +13,8 @@ #include "owl-common.h" +#define OWL_PLL_DEF_DELAY 50 + /* last entry should have rate = 0 */ struct clk_pll_table { unsigned int val; @@ -27,6 +29,7 @@ struct owl_pll_hw { u8 width; u8 min_mul; u8 max_mul; + u8 delay; const struct clk_pll_table *table; }; @@ -36,7 +39,7 @@ struct owl_pll { }; #define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ - _width, _min_mul, _max_mul, _table) \ + _width, _min_mul, _max_mul, _delay, _table) \ { \ .reg = _reg, \ .bfreq = _bfreq, \ @@ -45,6 +48,7 @@ struct owl_pll { .width = _width, \ .min_mul = _min_mul, \ .max_mul = _max_mul, \ + .delay = _delay, \ .table = _table, \ } @@ -52,8 +56,8 @@ struct owl_pll { _shift, _width, _min_mul, _max_mul, _table, _flags) \ struct owl_pll _struct = { \ .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ - _width, _min_mul, \ - _max_mul, _table), \ + _width, _min_mul, _max_mul, \ + OWL_PLL_DEF_DELAY, _table), \ .common = { \ .regmap = NULL, \ .hw.init = CLK_HW_INIT(_name, \ @@ -67,8 +71,23 @@ struct owl_pll { _shift, _width, _min_mul, _max_mul, _table, _flags) \ struct owl_pll _struct = { \ .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ - _width, _min_mul, \ - _max_mul, _table), \ + _width, _min_mul, _max_mul, \ + OWL_PLL_DEF_DELAY, _table), \ + .common = { \ + .regmap = NULL, \ + .hw.init = CLK_HW_INIT_NO_PARENT(_name, \ + &owl_pll_ops, \ + _flags), \ + }, \ + } + +#define OWL_PLL_NO_PARENT_DELAY(_struct, _name, _reg, _bfreq, _bit_idx, \ + _shift, _width, _min_mul, _max_mul, _delay, _table, \ + _flags) \ + struct owl_pll _struct = { \ + .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ + _width, _min_mul, _max_mul, \ + _delay, _table), \ .common = { \ .regmap = NULL, \ .hw.init = CLK_HW_INIT_NO_PARENT(_name, \ @@ -78,7 +97,6 @@ struct owl_pll { } #define mul_mask(m) ((1 << ((m)->width)) - 1) -#define PLL_STABILITY_WAIT_US (50) static inline struct owl_pll *hw_to_owl_pll(const struct clk_hw *hw) { From patchwork Mon Dec 31 18:55:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 154631 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp11197470ljp; Mon, 31 Dec 2018 10:55:55 -0800 (PST) X-Google-Smtp-Source: ALg8bN4duZEvC8yPlZy9jBMxNn0Toe0OZY5B0d2yPeLmxb3wX/O/dEnql6XDyIiIqvNndzew+hll X-Received: by 2002:a63:6f0d:: with SMTP id k13mr8296615pgc.42.1546282555134; Mon, 31 Dec 2018 10:55:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546282555; cv=none; d=google.com; s=arc-20160816; b=e7wfQSyhEFpch5PEVP1kzUuflWALggwZZRER6lh5v/q3gyZ9YMCYd9w/t4TcRiw+3j ppEc4/uL0IcCyOKsloWcUinkUsEE1EIyNPX+uLmTqcAN9LLcpCFBKZojn+Z+QxtNeSrl RqkjEa5y+aHrpt1VSIhgjeYLjar/hWB/TMQ722z5tKgwT4N2O4no4kybQOmKP2rxdPIE onOPGlikV7b1TbVp8c9RAPgD328NqpqpUXJOpr2M4Xi89D37+Pf4ZeOFcO+eUPV2rlsO ZJyw1bB0jXcBAtP5D7PoNT1R52Rqyt4tNH8hHO3pWF1hz5Y9k/hp1wYTFt4hIoNfg2DY x5jQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=9D7Rmsu05/Pbcqbi1xBn66qiVOUkQv4REhih46r6FtQ=; b=kRbUTyOL+5EWpH7tTrznFgjuLM9ViLg0LD0+wvoBaMOacE2BHPDPsDPAwEU0PDgwUw +eByiyPqwFsSh8otITqAeMc352L30lRay3Zfrn5Z4wpJbNFCWm5ebBDfyGNL6nK6R7Bm ds0RBA86NVsY+k+Dgntwlir04WBExcW9qUOLVRB6gk7yxXtBtgeeI7nlxf+fQ7ws7yOx OBy/7nQgtFmx7+GpD2LdCNbDCnWbpU3pazQ9YlfXx9v+Yjboexd3YmnoQjO6RVUhrSXI FnYH/yV3B28GgnMCtDHLR7nTTQucboh1fr8bS3nhHxd0Q9bsFNS/DWWnJOoQZwmcyKZn H11A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Uhjesctv; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n24si1085562pgv.119.2018.12.31.10.55.54; Mon, 31 Dec 2018 10:55:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Uhjesctv; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727791AbeLaSzw (ORCPT + 7 others); Mon, 31 Dec 2018 13:55:52 -0500 Received: from mail-pf1-f193.google.com ([209.85.210.193]:39327 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727788AbeLaSzw (ORCPT ); Mon, 31 Dec 2018 13:55:52 -0500 Received: by mail-pf1-f193.google.com with SMTP id r136so13461848pfc.6 for ; Mon, 31 Dec 2018 10:55:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9D7Rmsu05/Pbcqbi1xBn66qiVOUkQv4REhih46r6FtQ=; b=Uhjesctv2Sn27JZlyXrOgt4VnPsGLpQiRpLu0pyiNYRmKSYhCoDrGpQeWpf1rMU+7+ nrH4mLw6X3N2HaUnYTAv/DB3s+CsG13BXY9/bbkpMMcZm74+reGhIiw1/us7rjTqbz0Q 4lLNMtsU4F6M7rZz4mujTd8dqQLbpPdWXDHxs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9D7Rmsu05/Pbcqbi1xBn66qiVOUkQv4REhih46r6FtQ=; b=ncen7JsTD+IuKmLLF0tyo5xqknlz4gHbQod2J3uu8r/WlF8XGqfI48PGrLINVjl4wY pvDmpwv45juZd4QTH74wCAkae02pTO2sLZypTEKUwDU2Q+Nmj3CAHWylhvJD+d0MxuII /zYy0x6H+sFruijI2Ug1Re2Kfb8qCPrku/q50QNdTDELKAOuBPPzMQNFCGVd7gV/F2O9 TsVajwjrGslpynmxdEgtJ+2v5UlppBxihwYFKJuDubgBv0P8mNFMk5gE16LmEX7lkoss JI4PZy15wEe4kd+21PY+6swVbYmunVGYXUgJlzkQCJX4q218A99RGzr4QSeTKfNB5wJl zRzg== X-Gm-Message-State: AJcUukcFOt3AY+zMwwO+WvAfYLJIgIfl0XDnWXUQCpfujppysi7MKYU2 QKGqpRMSZe//P4rvKQSV3Res X-Received: by 2002:a63:4b60:: with SMTP id k32mr8334133pgl.186.1546282551092; Mon, 31 Dec 2018 10:55:51 -0800 (PST) Received: from localhost.localdomain ([2405:204:7440:b882:8d58:e15f:9ff4:efc2]) by smtp.gmail.com with ESMTPSA id s9sm66146224pgl.88.2018.12.31.10.55.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 31 Dec 2018 10:55:50 -0800 (PST) From: Manivannan Sadhasivam To: sboyd@kernel.org, mturquette@baylibre.com, afaerber@suse.de, robh+dt@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Edgar Bernardi Righi , Manivannan Sadhasivam Subject: [PATCH 2/6] dt-bindings: clock: Add DT bindings for Actions Semi S500 CMU Date: Tue, 1 Jan 2019 00:25:13 +0530 Message-Id: <20181231185517.18517-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181231185517.18517-1-manivannan.sadhasivam@linaro.org> References: <20181231185517.18517-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Edgar Bernardi Righi Add devicetree bindings for Actions Semi S500 Clock Management Unit. Signed-off-by: Edgar Bernardi Righi [Mani: Documented S500 CMU compatible] Signed-off-by: Manivannan Sadhasivam --- Rob, I have removed your Reviewed-by tag for this patch since the earlier revision contained only bindings constants and lacked the compatible documentation, which is added now. .../bindings/clock/actions,owl-cmu.txt | 7 +- include/dt-bindings/clock/actions,s500-cmu.h | 78 +++++++++++++++++++ 2 files changed, 82 insertions(+), 3 deletions(-) create mode 100644 include/dt-bindings/clock/actions,s500-cmu.h -- 2.17.1 diff --git a/Documentation/devicetree/bindings/clock/actions,owl-cmu.txt b/Documentation/devicetree/bindings/clock/actions,owl-cmu.txt index 2ef86ae96df8..86183f559022 100644 --- a/Documentation/devicetree/bindings/clock/actions,owl-cmu.txt +++ b/Documentation/devicetree/bindings/clock/actions,owl-cmu.txt @@ -2,13 +2,14 @@ The Actions Semi Owl Clock Management Unit generates and supplies clock to various controllers within the SoC. The clock binding described here is -applicable to S900 and S700 SoC's. +applicable to S900,S700 and S500 SoC's. Required Properties: - compatible: should be one of the following, "actions,s900-cmu" "actions,s700-cmu" + "actions,s500-cmu" - reg: physical base address of the controller and length of memory mapped region. - clocks: Reference to the parent clocks ("hosc", "losc") @@ -19,8 +20,8 @@ Each clock is assigned an identifier, and client nodes can use this identifier to specify the clock which they consume. All available clocks are defined as preprocessor macros in corresponding -dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h header and can be -used in device tree sources. +dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h or +actions,s500-cmu.h header and can be used in device tree sources. External clocks: diff --git a/include/dt-bindings/clock/actions,s500-cmu.h b/include/dt-bindings/clock/actions,s500-cmu.h new file mode 100644 index 000000000000..dc3fd2b0299d --- /dev/null +++ b/include/dt-bindings/clock/actions,s500-cmu.h @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree binding constants for Actions Semi S500 Clock Management Unit + * + * Copyright (c) 2014 Actions Semi Inc. + * Copyright (c) 2018 LSI-TEC - Caninos Loucos + */ + +#ifndef __DT_BINDINGS_CLOCK_S500_CMU_H +#define __DT_BINDINGS_CLOCK_S500_CMU_H + +#define CLK_NONE 0 + +/* fixed rate clocks */ +#define CLK_LOSC 1 +#define CLK_HOSC 2 + +/* pll clocks */ +#define CLK_CORE_PLL 3 +#define CLK_DEV_PLL 4 +#define CLK_DDR_PLL 5 +#define CLK_NAND_PLL 6 +#define CLK_DISPLAY_PLL 7 +#define CLK_ETHERNET_PLL 8 +#define CLK_AUDIO_PLL 9 + +/* system clock */ +#define CLK_DEV 10 +#define CLK_H 11 +#define CLK_AHBPREDIV 12 +#define CLK_AHB 13 +#define CLK_DE 14 +#define CLK_BISP 15 +#define CLK_VCE 16 +#define CLK_VDE 17 + +/* peripheral device clock */ +#define CLK_TIMER 18 +#define CLK_I2C0 19 +#define CLK_I2C1 20 +#define CLK_I2C2 21 +#define CLK_I2C3 22 +#define CLK_PWM0 23 +#define CLK_PWM1 24 +#define CLK_PWM2 25 +#define CLK_PWM3 26 +#define CLK_PWM4 27 +#define CLK_PWM5 28 +#define CLK_SD0 29 +#define CLK_SD1 30 +#define CLK_SD2 31 +#define CLK_SENSOR0 32 +#define CLK_SENSOR1 33 +#define CLK_SPI0 34 +#define CLK_SPI1 35 +#define CLK_SPI2 36 +#define CLK_SPI3 37 +#define CLK_UART0 38 +#define CLK_UART1 39 +#define CLK_UART2 40 +#define CLK_UART3 41 +#define CLK_UART4 42 +#define CLK_UART5 43 +#define CLK_UART6 44 +#define CLK_DE1 45 +#define CLK_DE2 46 +#define CLK_I2SRX 47 +#define CLK_I2STX 48 +#define CLK_HDMI_AUDIO 49 +#define CLK_HDMI 50 +#define CLK_SPDIF 51 +#define CLK_NAND 52 +#define CLK_ECC 53 +#define CLK_RMII_REF 54 + +#define CLK_NR_CLKS (CLK_RMII_REF + 1) + +#endif /* __DT_BINDINGS_CLOCK_S500_CMU_H */ From patchwork Mon Dec 31 18:55:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 154632 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp11197542ljp; Mon, 31 Dec 2018 10:56:00 -0800 (PST) X-Google-Smtp-Source: ALg8bN6lB37SMd4wua5p2sGO/WxDungk4LVQ0BgYl0VjUwqb2giRVSGtNQ6bstHs9zPVExFXf3fY X-Received: by 2002:a17:902:76cb:: with SMTP id j11mr39029563plt.179.1546282560589; Mon, 31 Dec 2018 10:56:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546282560; cv=none; d=google.com; s=arc-20160816; b=dNR52fBZ2Sn3mpkk+wppkFwEQi+6YZA9rwpAXQpyRGM2LKqNyFt3PrRJ/xacaIoRMd NhCpJ29rwh7ZNsiaSBxkxfkKJwWRWqu1LjOyl9g9XbROxvWUC68ADh9wGtbqjyZE9gt2 SKncFGKdce0rlZ2xkG4beQ+paV+IXNn59mGcl5rnf1isXcJwdJin7nK9R1MqeWRAMZ3o flrYx6wjUuS0r4YVXNc5mtk6cqvXzUvUeBIYI2IpEd0NXfVPmK/TyCn9tc3gX9UWutCi x5IPCUs1y0aTC2dcDc70T/hzQbynIEKfdAjt4YWtBpV64dXqkaaS8KHazrjChyqdJlAz aBPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=QzEw+0c7YCMrIJx0PSwB5TjdR5ksSYaunb0Z3JfV66A=; b=FMW1W3LAUIbSb7YGGO1RaARwa9BtwTOqbifToCuoukul31/4z46vJA/c5fCoCLlE+m BgXZ3t7oKfXf5psekQPzphTzSxgpwkGkehrCZFx6fJbHPi+Kt1iLx8tH8xavsjDYCNVl IZmJkzSzT+mtWaWZmkIPNxfQOtmTxJI4H5GTWTh43w7Q55wUuACKC3c9IYcqjLjKtYax gLT5USzT92nQXlRQfsh8taOJpla1/NM6dDFX9rjqHCNQxEST2Yk8YY81m1u64+VnhDCb 31XHjFOQifEB3krustllTM9QBquyjdK9Tao1P77hiyOg2/AGA01yAtJNAWcvejBsy0nO sRmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="drYNuZs/"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Edgar Bernardi Righi [Mani: Fixed commit message and DTS] Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/owl-s500.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) -- 2.17.1 diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 5ceb6cc4451d..aa758538de8c 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -3,8 +3,10 @@ * Actions Semi S500 SoC * * Copyright (c) 2016-2017 Andreas Färber + * Copyright (c) 2018 Edgar Bernardi Righi */ +#include #include #include @@ -70,6 +72,12 @@ #clock-cells = <0>; }; + losc: losc { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -124,6 +132,7 @@ compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0120000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART0>; status = "disabled"; }; @@ -131,6 +140,7 @@ compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0122000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART1>; status = "disabled"; }; @@ -138,6 +148,7 @@ compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0124000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART2>; status = "disabled"; }; @@ -145,6 +156,7 @@ compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0126000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART3>; status = "disabled"; }; @@ -152,6 +164,7 @@ compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0128000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART4>; status = "disabled"; }; @@ -159,6 +172,7 @@ compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb012a000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART5>; status = "disabled"; }; @@ -166,9 +180,17 @@ compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb012c000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART6>; status = "disabled"; }; + cmu: clock-controller@b0160000 { + compatible = "actions,s500-cmu"; + reg = <0xb0160000 0x8000>; + clocks = <&hosc>, <&losc>; + #clock-cells = <1>; + }; + timer: timer@b0168000 { compatible = "actions,s500-timer"; reg = <0xb0168000 0x8000>; From patchwork Mon Dec 31 18:55:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 154633 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp11197614ljp; Mon, 31 Dec 2018 10:56:07 -0800 (PST) X-Google-Smtp-Source: ALg8bN5G/AnLoGHp9Zxj4fcG+YUXxYzz1nQDY3u7lV80L//cCOyegB46uiQ3O4o3iZZ2ZejoqFvw X-Received: by 2002:a17:902:aa4c:: with SMTP id c12mr38045109plr.48.1546282567533; Mon, 31 Dec 2018 10:56:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546282567; cv=none; d=google.com; s=arc-20160816; b=vSPdvvLNpNFk7UDkDq8Wg+k5DxNfXwimuVbM4g9nJsBoA2F3+sz4OJxrmNbiwTvFzd 4xR5UPNMWkp03PDkVgnqJgk/kgiUNY8XJEm6moABUjMqIo+X7JXD/iR8+/vS8mxxrTO2 a0NTtcYvaNxB5ZmYwirRXBRzBXxeEwFLQhR5vxnYxUEXuqscQgVMyuxtua2B2ChOZ5SN 4YTHTWuOk3gSke376PtTpsRROncqKZEG/qDi3EP5xEpyggetp76WjN5cifAYU7FnE1hE 77PkKoOGZk8g7YnqMbkgADHQmjOpKoR3fDcuIj0GU5hn8DYskhfXKJvl3O8E84sQMhst hqoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=xnTFjl+GiCKiqWScUNzvjAlPROFJTsMxFZH/vteR13U=; b=ZAdgrKsxq2jheoe+VNSxnqQdGZsiEICNQzDedg65/ozbxBh18wiaDPgTuH/4pY5pHi 7NJfdWiagIktWbQpkhO69dF5duf96X8M8x6vkFBmap7gnrb6yLAz8FrrmPvSiNPcanX6 CD8rCUadrNYuskfTYrKpMqotouP/l64GOGyzwtSA+74N3XzD20F7WUEIl+A5c3OLIb5S pZDacOElN0/qjn9nNE8k36woyBXFARvbli4qxIhFbOtcDZiP+114N3kPug+ee1PP8WMC lEGY0ddchagbNJZvmDrP9iGehcHzDWj/Wie5sHpb4mOz3Y6txxcO5R/CzylUbkSoSNG1 vsQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DAfoUXX2; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 72si44638366plb.224.2018.12.31.10.56.07; Mon, 31 Dec 2018 10:56:07 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DAfoUXX2; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727825AbeLaS4G (ORCPT + 7 others); Mon, 31 Dec 2018 13:56:06 -0500 Received: from mail-pl1-f194.google.com ([209.85.214.194]:44797 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727822AbeLaS4F (ORCPT ); Mon, 31 Dec 2018 13:56:05 -0500 Received: by mail-pl1-f194.google.com with SMTP id e11so12884079plt.11 for ; Mon, 31 Dec 2018 10:56:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xnTFjl+GiCKiqWScUNzvjAlPROFJTsMxFZH/vteR13U=; b=DAfoUXX2Mm4QCjZqfBd/jHNgGDXixo8Idl2Ej2QqqP8eRoI+RjdqXc//NL6yfnGUki x96pi+g9+u6YtEP3M6799NXkX8CxIyuptrQkPatVQ/7t4Wpa9OBmKzf2ffLtp1crXjcD 0onod/iPgWI3xVsGvCupVe1PmvzcKQWx74o8g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xnTFjl+GiCKiqWScUNzvjAlPROFJTsMxFZH/vteR13U=; b=NUEVxmGuT5xQqeayVkouFoU4etHvMx/uwo/yv8jWGDNpua3QTSUx+VhcHz+23i2L1d QnOoNgLTtngkchWWHL3zr5p9wjmJNPjMEzvAHiOSEPQYzUwdL8jD3at5MnbpP4pVZ9wo c3Wzbb1v972YzN91ojMxY7eTK+lincQUF7IvRJ8h+Rs5WIIXwIRVwX8RMoW2ATLIOZMu zFa965q6TtE9AR0ki7v8Y0QrJ0+WUM/BDVVDyGlc+ZxWVX3xnRQrPWGOkCjVEmRxLr/C R0RZAwMBtVDLRcNbZ6onjp85xsdRNHuQsvkb+g1NliszOwi4IDdyzs3RGWpM/PglWq4G 0fLw== X-Gm-Message-State: AJcUukdCnMOIT7V5QUPsv3Y6Q28Kcz19+jj28C8ah6VNwQZ8gQtnbgqR HP7R9hzuNUrYpdx5Ma+pWspI X-Received: by 2002:a17:902:3064:: with SMTP id u91mr37492748plb.325.1546282563704; Mon, 31 Dec 2018 10:56:03 -0800 (PST) Received: from localhost.localdomain ([2405:204:7440:b882:8d58:e15f:9ff4:efc2]) by smtp.gmail.com with ESMTPSA id s9sm66146224pgl.88.2018.12.31.10.55.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 31 Dec 2018 10:56:03 -0800 (PST) From: Manivannan Sadhasivam To: sboyd@kernel.org, mturquette@baylibre.com, afaerber@suse.de, robh+dt@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam , Edgar Bernardi Righi Subject: [PATCH 4/6] ARM: dts: Remove fake UART clock for S500 based SBCs Date: Tue, 1 Jan 2019 00:25:15 +0530 Message-Id: <20181231185517.18517-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181231185517.18517-1-manivannan.sadhasivam@linaro.org> References: <20181231185517.18517-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Since Actions Semi S500 SoC has gained support for Clock Management Unit in kernel, let's remove the fake UART clocks from Cubieboard6, Guitar and Sparky SBCs. Signed-off-by: Edgar Bernardi Righi Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/owl-s500-cubieboard6.dts | 7 ------- arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts | 7 ------- arch/arm/boot/dts/owl-s500-sparky.dts | 7 ------- 3 files changed, 21 deletions(-) -- 2.17.1 diff --git a/arch/arm/boot/dts/owl-s500-cubieboard6.dts b/arch/arm/boot/dts/owl-s500-cubieboard6.dts index 7c96c59b610d..c2b02895910c 100644 --- a/arch/arm/boot/dts/owl-s500-cubieboard6.dts +++ b/arch/arm/boot/dts/owl-s500-cubieboard6.dts @@ -25,12 +25,6 @@ device_type = "memory"; reg = <0x0 0x80000000>; }; - - uart3_clk: uart3-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; }; &timer { @@ -39,5 +33,4 @@ &uart3 { status = "okay"; - clocks = <&uart3_clk>; }; diff --git a/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts b/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts index e610d49395d2..7ae34a23e320 100644 --- a/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts +++ b/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts @@ -18,15 +18,8 @@ chosen { stdout-path = "serial3:115200n8"; }; - - uart3_clk: uart3-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; }; &uart3 { status = "okay"; - clocks = <&uart3_clk>; }; diff --git a/arch/arm/boot/dts/owl-s500-sparky.dts b/arch/arm/boot/dts/owl-s500-sparky.dts index c665ce8b88b4..9d8f7336bec0 100644 --- a/arch/arm/boot/dts/owl-s500-sparky.dts +++ b/arch/arm/boot/dts/owl-s500-sparky.dts @@ -25,12 +25,6 @@ device_type = "memory"; reg = <0x0 0x40000000>; /* 1 or 2 GiB */ }; - - uart3_clk: uart3-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; }; &timer { @@ -39,5 +33,4 @@ &uart3 { status = "okay"; - clocks = <&uart3_clk>; }; From patchwork Mon Dec 31 18:55:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 154634 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp11197725ljp; Mon, 31 Dec 2018 10:56:15 -0800 (PST) X-Google-Smtp-Source: ALg8bN6BmmiwNHANiaPaY5Izmk2Jo1VYMJqAdx6IoL2IgSI/yHhujoSq4oz/N6TD5EprRA9fj+I0 X-Received: by 2002:a17:902:8d8e:: with SMTP id v14mr37947372plo.133.1546282575303; Mon, 31 Dec 2018 10:56:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546282575; cv=none; d=google.com; s=arc-20160816; b=aCWEmXjehwt0hWsyAFbaWNKVIVXoX6bnjkfo6IGLS0Ufm+X/V+76PMcvC/FEk8l7pW 7d/R2KL2hmZKpw0YytfCaK0h+NqQCqCWHl81cnvH5sIK7IFIGCRA6ApRozbbOs/UmW7e WAWHQ5YhbIN83LFmovlPYQV1GMnCIpQNb7n8c25BM6W/3UydAt/IzdOxMPfzaoeonLFM lBVGtYLZwDIx9fL3QegXq+YLJ3k1Tmmds0LkiUqkYXnIh66rOYTBc8Meu4keqX1uKhV5 OH5vO4ryjQIHX2sfed+tavolLAzSKSGI5imiLfNu4w5rbI8zBOOgi1S11iy5UDnS9lkW o1Gw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=UwW0EYSDEEweABTfqJHVBQZKjbgkRBM0Ptj+o96JZ5g=; b=NgTABvbduA1/IogR5P39/Kg5db95bBJozj3rvoDjEtN2yVAf48x5yQfA0umAWmLP2Y N/b0RLxUFOhHneNxy7ZSs0SFxmFz+cP+GVYvzRMz3ZGqLDEMOMYNQAzJ2ctWX2mBmdjL ohn1kyTJLgotJqGVpyKPdXD5EBynYIVah13Oo23yAje35V4CZW3wvDhKDYwybO0aSqLk fQ9OnRxXMHKtaP9tVauj/wNXRAmFQKzX13g0yHNCWn9ys3MSh81j4LPNcWs9FTSa2ufC K9m53s7h2MZgRayDMN3vojIWpCAS6dTtUYHxI/YOrhM6alcIbGy/n89LXa8jcRogRDML JW9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=G3Rh21ts; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 191si44938475pgf.41.2018.12.31.10.56.15; Mon, 31 Dec 2018 10:56:15 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=G3Rh21ts; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727843AbeLaS4N (ORCPT + 7 others); Mon, 31 Dec 2018 13:56:13 -0500 Received: from mail-pg1-f196.google.com ([209.85.215.196]:38928 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727841AbeLaS4M (ORCPT ); Mon, 31 Dec 2018 13:56:12 -0500 Received: by mail-pg1-f196.google.com with SMTP id w6so12947096pgl.6 for ; Mon, 31 Dec 2018 10:56:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UwW0EYSDEEweABTfqJHVBQZKjbgkRBM0Ptj+o96JZ5g=; b=G3Rh21ts1PuS/b2BnKkkiRGJYC76O8Fkl6j0wvYKPCKw+R662nTXYCpw+tPKEr2JEc 239+4tx7TRmsXnIEk/67z6x6rDLCU8v4V/QGIoccGIv/eP5Cm1HeR3xRtPzydBfmP+J9 Ncc/Tr75girZ4w9Fy9t+Jyvj1nEvoAgfRLG9s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UwW0EYSDEEweABTfqJHVBQZKjbgkRBM0Ptj+o96JZ5g=; b=PkpK7feBb3kmIFpCbgQkAujL7qiSY+rJiovuB3KO1gtrh89l+PcUZ6+4I+y+v/97HH IKVFg5p4MJu+80syHzkPYnNHgHELtdd4SMOV89uHYanr8J3lVHprJ0NT2cEsyOHzupAw e4Q+y9EoGhYlUQ7Ui/DYQKNfCInYIrvEjVigakWzjQ9HYznuOljVa1M79zDht5HhQ+QG 8Y/zHlnF/JhHY/nn0g7oTEfIm4MxvhuR63eqeYHXrKjFrC7sUFAu9khhR7oVTMDUf2Ho hD2VBvN+/Rn1gmNkjxL7L7algX4aKRVdYnIQ8KKPmdhte1EXXlKpfLNpa8DQEkjfqexz MOpg== X-Gm-Message-State: AA+aEWY5imRrtfi+OnkvLLwAwWrfTtmBwFZFjpNANaEztAM0+/6W+X+W +UFuQLijtYtuZiuT6PSR3IHA X-Received: by 2002:a62:b24a:: with SMTP id x71mr39774647pfe.148.1546282571328; Mon, 31 Dec 2018 10:56:11 -0800 (PST) Received: from localhost.localdomain ([2405:204:7440:b882:8d58:e15f:9ff4:efc2]) by smtp.gmail.com with ESMTPSA id s9sm66146224pgl.88.2018.12.31.10.56.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 31 Dec 2018 10:56:10 -0800 (PST) From: Manivannan Sadhasivam To: sboyd@kernel.org, mturquette@baylibre.com, afaerber@suse.de, robh+dt@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam , Edgar Bernardi Righi Subject: [PATCH 5/6] clk: actions: Add clock driver for S500 SoC Date: Tue, 1 Jan 2019 00:25:16 +0530 Message-Id: <20181231185517.18517-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181231185517.18517-1-manivannan.sadhasivam@linaro.org> References: <20181231185517.18517-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add common clock driver for Actions Semi S500 SoC. Signed-off-by: Edgar Bernardi Righi [Mani: cleaned up the driver] Signed-off-by: Manivannan Sadhasivam --- drivers/clk/actions/Kconfig | 5 + drivers/clk/actions/Makefile | 1 + drivers/clk/actions/owl-s500.c | 524 +++++++++++++++++++++++++++++++++ 3 files changed, 530 insertions(+) create mode 100644 drivers/clk/actions/owl-s500.c -- 2.17.1 diff --git a/drivers/clk/actions/Kconfig b/drivers/clk/actions/Kconfig index 04f0a6355726..5b45ca35757e 100644 --- a/drivers/clk/actions/Kconfig +++ b/drivers/clk/actions/Kconfig @@ -9,6 +9,11 @@ if CLK_ACTIONS # SoC Drivers +config CLK_OWL_S500 + bool "Support for the Actions Semi OWL S500 clocks" + depends on ARCH_ACTIONS || COMPILE_TEST + default ARCH_ACTIONS + config CLK_OWL_S700 bool "Support for the Actions Semi OWL S700 clocks" depends on (ARM64 && ARCH_ACTIONS) || COMPILE_TEST diff --git a/drivers/clk/actions/Makefile b/drivers/clk/actions/Makefile index ccfdf9781cef..a2588e55c790 100644 --- a/drivers/clk/actions/Makefile +++ b/drivers/clk/actions/Makefile @@ -10,5 +10,6 @@ clk-owl-y += owl-pll.o clk-owl-y += owl-reset.o # SoC support +obj-$(CONFIG_CLK_OWL_S500) += owl-s500.o obj-$(CONFIG_CLK_OWL_S700) += owl-s700.o obj-$(CONFIG_CLK_OWL_S900) += owl-s900.o diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c new file mode 100644 index 000000000000..93feea8d71e2 --- /dev/null +++ b/drivers/clk/actions/owl-s500.c @@ -0,0 +1,524 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Actions Semi Owl S500 SoC clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam +// +// Copyright (c) 2018 LSI-TEC - Caninos Loucos +// Author: Edgar Bernardi Righi + +#include +#include + +#include "owl-common.h" +#include "owl-composite.h" +#include "owl-divider.h" +#include "owl-factor.h" +#include "owl-fixed-factor.h" +#include "owl-gate.h" +#include "owl-mux.h" +#include "owl-pll.h" + +#include + +#define CMU_COREPLL (0x0000) +#define CMU_DEVPLL (0x0004) +#define CMU_DDRPLL (0x0008) +#define CMU_NANDPLL (0x000C) +#define CMU_DISPLAYPLL (0x0010) +#define CMU_AUDIOPLL (0x0014) +#define CMU_TVOUTPLL (0x0018) +#define CMU_BUSCLK (0x001C) +#define CMU_SENSORCLK (0x0020) +#define CMU_LCDCLK (0x0024) +#define CMU_DSICLK (0x0028) +#define CMU_CSICLK (0x002C) +#define CMU_DECLK (0x0030) +#define CMU_BISPCLK (0x0034) +#define CMU_BUSCLK1 (0x0038) +#define CMU_VDECLK (0x0040) +#define CMU_VCECLK (0x0044) +#define CMU_NANDCCLK (0x004C) +#define CMU_SD0CLK (0x0050) +#define CMU_SD1CLK (0x0054) +#define CMU_SD2CLK (0x0058) +#define CMU_UART0CLK (0x005C) +#define CMU_UART1CLK (0x0060) +#define CMU_UART2CLK (0x0064) +#define CMU_PWM4CLK (0x0068) +#define CMU_PWM5CLK (0x006C) +#define CMU_PWM0CLK (0x0070) +#define CMU_PWM1CLK (0x0074) +#define CMU_PWM2CLK (0x0078) +#define CMU_PWM3CLK (0x007C) +#define CMU_USBPLL (0x0080) +#define CMU_ETHERNETPLL (0x0084) +#define CMU_CVBSPLL (0x0088) +#define CMU_LENSCLK (0x008C) +#define CMU_GPU3DCLK (0x0090) +#define CMU_CORECTL (0x009C) +#define CMU_DEVCLKEN0 (0x00A0) +#define CMU_DEVCLKEN1 (0x00A4) +#define CMU_DEVRST0 (0x00A8) +#define CMU_DEVRST1 (0x00AC) +#define CMU_UART3CLK (0x00B0) +#define CMU_UART4CLK (0x00B4) +#define CMU_UART5CLK (0x00B8) +#define CMU_UART6CLK (0x00BC) +#define CMU_SSCLK (0x00C0) +#define CMU_DIGITALDEBUG (0x00D0) +#define CMU_ANALOGDEBUG (0x00D4) +#define CMU_COREPLLDEBUG (0x00D8) +#define CMU_DEVPLLDEBUG (0x00DC) +#define CMU_DDRPLLDEBUG (0x00E0) +#define CMU_NANDPLLDEBUG (0x00E4) +#define CMU_DISPLAYPLLDEBUG (0x00E8) +#define CMU_TVOUTPLLDEBUG (0x00EC) +#define CMU_DEEPCOLORPLLDEBUG (0x00F4) +#define CMU_AUDIOPLL_ETHPLLDEBUG (0x00F8) +#define CMU_CVBSPLLDEBUG (0x00FC) + +#define OWL_S500_COREPLL_DELAY (150) +#define OWL_S500_DDRPLL_DELAY (63) +#define OWL_S500_DEVPLL_DELAY (28) +#define OWL_S500_NANDPLL_DELAY (44) +#define OWL_S500_DISPLAYPLL_DELAY (57) +#define OWL_S500_ETHERNETPLL_DELAY (25) +#define OWL_S500_AUDIOPLL_DELAY (100) + +static const struct clk_pll_table clk_audio_pll_table[] = { + { 0, 45158400 }, { 1, 49152000 }, + { 0, 0 }, +}; + +/* pll clocks */ +static OWL_PLL_NO_PARENT_DELAY(ethernet_pll_clk, "ethernet_pll_clk", CMU_ETHERNETPLL, 500000000, 0, 0, 0, 0, 0, OWL_S500_ETHERNETPLL_DELAY, NULL, CLK_IGNORE_UNUSED); +static OWL_PLL_NO_PARENT_DELAY(core_pll_clk, "core_pll_clk", CMU_COREPLL, 12000000, 9, 0, 8, 4, 134, OWL_S500_COREPLL_DELAY, NULL, CLK_IGNORE_UNUSED); +static OWL_PLL_NO_PARENT_DELAY(ddr_pll_clk, "ddr_pll_clk", CMU_DDRPLL, 12000000, 8, 0, 8, 1, 67, OWL_S500_DDRPLL_DELAY, NULL, CLK_IGNORE_UNUSED); +static OWL_PLL_NO_PARENT_DELAY(nand_pll_clk, "nand_pll_clk", CMU_NANDPLL, 6000000, 8, 0, 7, 2, 86, OWL_S500_NANDPLL_DELAY, NULL, CLK_IGNORE_UNUSED); +static OWL_PLL_NO_PARENT_DELAY(display_pll_clk, "display_pll_clk", CMU_DISPLAYPLL, 6000000, 8, 0, 8, 2, 126, OWL_S500_DISPLAYPLL_DELAY, NULL, CLK_IGNORE_UNUSED); +static OWL_PLL_NO_PARENT_DELAY(dev_pll_clk, "dev_pll_clk", CMU_DEVPLL, 6000000, 8, 0, 7, 8, 126, OWL_S500_DEVPLL_DELAY, NULL, CLK_IGNORE_UNUSED); +static OWL_PLL_NO_PARENT_DELAY(audio_pll_clk, "audio_pll_clk", CMU_AUDIOPLL, 0, 4, 0, 1, 0, 0, OWL_S500_AUDIOPLL_DELAY, clk_audio_pll_table, CLK_IGNORE_UNUSED); + +static const char *dev_clk_mux_p[] = { "hosc", "dev_pll_clk" }; +static const char *bisp_clk_mux_p[] = { "display_pll_clk", "dev_clk" }; +static const char *sensor_clk_mux_p[] = { "hosc", "bisp_clk" }; +static const char *sd_clk_mux_p[] = { "dev_clk", "nand_pll_clk" }; +static const char *pwm_clk_mux_p[] = { "losc", "hosc" }; +static const char *ahbprediv_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" }; +static const char *uart_clk_mux_p[] = { "hosc", "dev_pll_clk" }; +static const char *de_clk_mux_p[] = { "display_pll_clk", "dev_clk" }; +static const char *i2s_clk_mux_p[] = { "audio_pll_clk" }; +static const char *hde_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" }; +static const char *nand_clk_mux_p[] = { "nand_pll_clk", "display_pll_clk", "dev_clk", "ddr_pll_clk" }; + +static struct clk_factor_table sd_factor_table[] = { + /* bit0 ~ 4 */ + { 0, 1, 1 }, { 1, 1, 2 }, { 2, 1, 3 }, { 3, 1, 4 }, + { 4, 1, 5 }, { 5, 1, 6 }, { 6, 1, 7 }, { 7, 1, 8 }, + { 8, 1, 9 }, { 9, 1, 10 }, { 10, 1, 11 }, { 11, 1, 12 }, + { 12, 1, 13 }, { 13, 1, 14 }, { 14, 1, 15 }, { 15, 1, 16 }, + { 16, 1, 17 }, { 17, 1, 18 }, { 18, 1, 19 }, { 19, 1, 20 }, + { 20, 1, 21 }, { 21, 1, 22 }, { 22, 1, 23 }, { 23, 1, 24 }, + { 24, 1, 25 }, { 25, 1, 26 }, { 26, 1, 27 }, { 27, 1, 28 }, + { 28, 1, 29 }, { 29, 1, 30 }, { 30, 1, 31 }, { 31, 1, 32 }, + + /* bit8: /128 */ + { 256, 1, 1 * 128 }, { 257, 1, 2 * 128 }, { 258, 1, 3 * 128 }, { 259, 1, 4 * 128 }, + { 260, 1, 5 * 128 }, { 261, 1, 6 * 128 }, { 262, 1, 7 * 128 }, { 263, 1, 8 * 128 }, + { 264, 1, 9 * 128 }, { 265, 1, 10 * 128 }, { 266, 1, 11 * 128 }, { 267, 1, 12 * 128 }, + { 268, 1, 13 * 128 }, { 269, 1, 14 * 128 }, { 270, 1, 15 * 128 }, { 271, 1, 16 * 128 }, + { 272, 1, 17 * 128 }, { 273, 1, 18 * 128 }, { 274, 1, 19 * 128 }, { 275, 1, 20 * 128 }, + { 276, 1, 21 * 128 }, { 277, 1, 22 * 128 }, { 278, 1, 23 * 128 }, { 279, 1, 24 * 128 }, + { 280, 1, 25 * 128 }, { 281, 1, 26 * 128 }, { 282, 1, 27 * 128 }, { 283, 1, 28 * 128 }, + { 284, 1, 29 * 128 }, { 285, 1, 30 * 128 }, { 286, 1, 31 * 128 }, { 287, 1, 32 * 128 }, + { 0, 0, 0 }, +}; + +static struct clk_factor_table bisp_factor_table[] = { + { 0, 1, 1 }, { 1, 1, 2 }, { 2, 1, 3 }, { 3, 1, 4 }, + { 4, 1, 5 }, { 5, 1, 6 }, { 6, 1, 7 }, { 7, 1, 8 }, + { 0, 0, 0 }, +}; + +static struct clk_factor_table ahb_factor_table[] = { + { 1, 1, 2 }, { 2, 1, 3 }, + { 0, 0, 0 }, +}; + +static struct clk_div_table rmii_ref_div_table[] = { + { 0, 4 }, { 1, 10 }, + { 0, 0 }, +}; + +static struct clk_div_table i2s_div_table[] = { + { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, + { 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 }, + { 8, 24 }, + { 0, 0 }, +}; + +static struct clk_div_table nand_div_table[] = { + { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 6 }, + { 4, 8 }, { 5, 10 }, { 6, 12 }, { 7, 14 }, + { 8, 16 }, { 9, 18 }, { 10, 20 }, { 11, 22 }, + { 0, 0 }, +}; + +/* mux clock */ +static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT); +static OWL_MUX(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT); + +/* gate clocks */ +static OWL_GATE(spi0_clk, "spi0_clk", "ahb_clk", CMU_DEVCLKEN1, 10, 0, CLK_IGNORE_UNUSED); +static OWL_GATE(spi1_clk, "spi1_clk", "ahb_clk", CMU_DEVCLKEN1, 11, 0, CLK_IGNORE_UNUSED); +static OWL_GATE(spi2_clk, "spi2_clk", "ahb_clk", CMU_DEVCLKEN1, 12, 0, CLK_IGNORE_UNUSED); +static OWL_GATE(spi3_clk, "spi3_clk", "ahb_clk", CMU_DEVCLKEN1, 13, 0, CLK_IGNORE_UNUSED); +static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0); +static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0); + +/* divider clocks */ +static OWL_DIVIDER(h_clk, "h_clk", "ahbprevdiv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0); +static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0); + +/* factor clocks */ +static OWL_FACTOR(ahb_clk, "ahb_clk", "h_clk", CMU_BUSCLK1, 2, 2, ahb_factor_table, 0, 0); +static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 3, bisp_factor_table, 0, 0); +static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 3, bisp_factor_table, 0, 0); + +/* composite clocks */ +static OWL_COMP_FACTOR(vce_clk, "vce_clk", hde_clk_mux_p, + OWL_MUX_HW(CMU_VCECLK, 4, 2), + OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0), + OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, bisp_factor_table), + 0); + +static OWL_COMP_FACTOR(vde_clk, "vde_clk", hde_clk_mux_p, + OWL_MUX_HW(CMU_VDECLK, 4, 2), + OWL_GATE_HW(CMU_DEVCLKEN0, 25, 0), + OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, bisp_factor_table), + 0); + +static OWL_COMP_FACTOR(bisp_clk, "bisp_clk", bisp_clk_mux_p, + OWL_MUX_HW(CMU_BISPCLK, 4, 1), + OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0), + OWL_FACTOR_HW(CMU_BISPCLK, 0, 3, 0, bisp_factor_table), + 0); + +static OWL_COMP_FACTOR(sensor0_clk, "sensor0_clk", sensor_clk_mux_p, + OWL_MUX_HW(CMU_SENSORCLK, 4, 1), + OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0), + OWL_FACTOR_HW(CMU_SENSORCLK, 0, 3, 0, bisp_factor_table), + CLK_IGNORE_UNUSED); + +static OWL_COMP_FACTOR(sensor1_clk, "sensor1_clk", sensor_clk_mux_p, + OWL_MUX_HW(CMU_SENSORCLK, 4, 1), + OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0), + OWL_FACTOR_HW(CMU_SENSORCLK, 8, 3, 0, bisp_factor_table), + CLK_IGNORE_UNUSED); + +static OWL_COMP_FACTOR(sd0_clk, "sd0_clk", sd_clk_mux_p, + OWL_MUX_HW(CMU_SD0CLK, 9, 1), + OWL_GATE_HW(CMU_DEVCLKEN0, 5, 0), + OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table), + 0); + +static OWL_COMP_FACTOR(sd1_clk, "sd1_clk", sd_clk_mux_p, + OWL_MUX_HW(CMU_SD1CLK, 9, 1), + OWL_GATE_HW(CMU_DEVCLKEN0, 6, 0), + OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table), + 0); + +static OWL_COMP_FACTOR(sd2_clk, "sd2_clk", sd_clk_mux_p, + OWL_MUX_HW(CMU_SD2CLK, 9, 1), + OWL_GATE_HW(CMU_DEVCLKEN0, 7, 0), + OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table), + 0); + +static OWL_COMP_DIV(pwm0_clk, "pwm0_clk", pwm_clk_mux_p, + OWL_MUX_HW(CMU_PWM0CLK, 12, 1), + OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0), + OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL), + 0); + +static OWL_COMP_DIV(pwm1_clk, "pwm1_clk", pwm_clk_mux_p, + OWL_MUX_HW(CMU_PWM1CLK, 12, 1), + OWL_GATE_HW(CMU_DEVCLKEN1, 24, 0), + OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL), + 0); + +static OWL_COMP_DIV(pwm2_clk, "pwm2_clk", pwm_clk_mux_p, + OWL_MUX_HW(CMU_PWM2CLK, 12, 1), + OWL_GATE_HW(CMU_DEVCLKEN1, 25, 0), + OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL), + 0); + +static OWL_COMP_DIV(pwm3_clk, "pwm3_clk", pwm_clk_mux_p, + OWL_MUX_HW(CMU_PWM3CLK, 12, 1), + OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0), + OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL), + 0); + +static OWL_COMP_DIV(pwm4_clk, "pwm4_clk", pwm_clk_mux_p, + OWL_MUX_HW(CMU_PWM4CLK, 12, 1), + OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0), + OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL), + 0); + +static OWL_COMP_DIV(pwm5_clk, "pwm5_clk", pwm_clk_mux_p, + OWL_MUX_HW(CMU_PWM5CLK, 12, 1), + OWL_GATE_HW(CMU_DEVCLKEN0, 0, 0), + OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL), + 0); + +static OWL_COMP_PASS(de_clk, "de_clk", de_clk_mux_p, + OWL_MUX_HW(CMU_DECLK, 12, 1), + OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0), + 0); + +static OWL_COMP_FIXED_FACTOR(i2c0_clk, "i2c0_clk", "ethernet_pll_clk", + OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0), + 1, 5, 0); + +static OWL_COMP_FIXED_FACTOR(i2c1_clk, "i2c1_clk", "ethernet_pll_clk", + OWL_GATE_HW(CMU_DEVCLKEN1, 15, 0), + 1, 5, 0); + +static OWL_COMP_FIXED_FACTOR(i2c2_clk, "i2c2_clk", "ethernet_pll_clk", + OWL_GATE_HW(CMU_DEVCLKEN1, 30, 0), + 1, 5, 0); + +static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "ethernet_pll_clk", + OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0), + 1, 5, 0); + +static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p, + OWL_MUX_HW(CMU_UART0CLK, 16, 1), + OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0), + OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + CLK_IGNORE_UNUSED); + +static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p, + OWL_MUX_HW(CMU_UART1CLK, 16, 1), + OWL_GATE_HW(CMU_DEVCLKEN1, 7, 0), + OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + CLK_IGNORE_UNUSED); + +static OWL_COMP_DIV(uart2_clk, "uart2_clk", uart_clk_mux_p, + OWL_MUX_HW(CMU_UART2CLK, 16, 1), + OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0), + OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + CLK_IGNORE_UNUSED); + +static OWL_COMP_DIV(uart3_clk, "uart3_clk", uart_clk_mux_p, + OWL_MUX_HW(CMU_UART3CLK, 16, 1), + OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0), + OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + CLK_IGNORE_UNUSED); + +static OWL_COMP_DIV(uart4_clk, "uart4_clk", uart_clk_mux_p, + OWL_MUX_HW(CMU_UART4CLK, 16, 1), + OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0), + OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + CLK_IGNORE_UNUSED); + +static OWL_COMP_DIV(uart5_clk, "uart5_clk", uart_clk_mux_p, + OWL_MUX_HW(CMU_UART5CLK, 16, 1), + OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0), + OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + CLK_IGNORE_UNUSED); + +static OWL_COMP_DIV(uart6_clk, "uart6_clk", uart_clk_mux_p, + OWL_MUX_HW(CMU_UART6CLK, 16, 1), + OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0), + OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + CLK_IGNORE_UNUSED); + +static OWL_COMP_DIV(i2srx_clk, "i2srx_clk", i2s_clk_mux_p, + OWL_MUX_HW(CMU_AUDIOPLL, 24, 1), + OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0), + OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, i2s_div_table), + 0); + +static OWL_COMP_DIV(i2stx_clk, "i2stx_clk", i2s_clk_mux_p, + OWL_MUX_HW(CMU_AUDIOPLL, 24, 1), + OWL_GATE_HW(CMU_DEVCLKEN0, 20, 0), + OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, i2s_div_table), + 0); + +static OWL_COMP_DIV(hdmia_clk, "hdmia_clk", i2s_clk_mux_p, + OWL_MUX_HW(CMU_AUDIOPLL, 24, 1), + OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0), + OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, i2s_div_table), + 0); + +static OWL_COMP_DIV(spdif_clk, "spdif_clk", i2s_clk_mux_p, + OWL_MUX_HW(CMU_AUDIOPLL, 24, 1), + OWL_GATE_HW(CMU_DEVCLKEN0, 23, 0), + OWL_DIVIDER_HW(CMU_AUDIOPLL, 28, 4, 0, i2s_div_table), + 0); + +static OWL_COMP_DIV(nand_clk, "nand_clk", nand_clk_mux_p, + OWL_MUX_HW(CMU_NANDCCLK, 8, 2), + OWL_GATE_HW(CMU_DEVCLKEN0, 4, 0), + OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, nand_div_table), + CLK_SET_RATE_PARENT); + +static OWL_COMP_DIV(ecc_clk, "ecc_clk", nand_clk_mux_p, + OWL_MUX_HW(CMU_NANDCCLK, 8, 2), + OWL_GATE_HW(CMU_DEVCLKEN0, 4, 0), + OWL_DIVIDER_HW(CMU_NANDCCLK, 4, 3, 0, nand_div_table), + CLK_SET_RATE_PARENT); + +static struct owl_clk_common *s500_clks[] = { + ðernet_pll_clk.common, + &core_pll_clk.common, + &ddr_pll_clk.common, + &dev_pll_clk.common, + &nand_pll_clk.common, + &audio_pll_clk.common, + &display_pll_clk.common, + &dev_clk.common, + &timer_clk.common, + &i2c0_clk.common, + &i2c1_clk.common, + &i2c2_clk.common, + &i2c3_clk.common, + &uart0_clk.common, + &uart1_clk.common, + &uart2_clk.common, + &uart3_clk.common, + &uart4_clk.common, + &uart5_clk.common, + &uart6_clk.common, + &pwm0_clk.common, + &pwm1_clk.common, + &pwm2_clk.common, + &pwm3_clk.common, + &pwm4_clk.common, + &pwm5_clk.common, + &sensor0_clk.common, + &sensor1_clk.common, + &sd0_clk.common, + &sd1_clk.common, + &sd2_clk.common, + &bisp_clk.common, + &ahb_clk.common, + &ahbprediv_clk.common, + &h_clk.common, + &spi0_clk.common, + &spi1_clk.common, + &spi2_clk.common, + &spi3_clk.common, + &rmii_ref_clk.common, + &de_clk.common, + &de1_clk.common, + &de2_clk.common, + &i2srx_clk.common, + &i2stx_clk.common, + &hdmia_clk.common, + &hdmi_clk.common, + &vce_clk.common, + &vde_clk.common, + &spdif_clk.common, + &nand_clk.common, + &ecc_clk.common, +}; + +static struct clk_hw_onecell_data s500_hw_clks = { + .hws = { + [CLK_ETHERNET_PLL] = ðernet_pll_clk.common.hw, + [CLK_CORE_PLL] = &core_pll_clk.common.hw, + [CLK_DDR_PLL] = &ddr_pll_clk.common.hw, + [CLK_NAND_PLL] = &nand_pll_clk.common.hw, + [CLK_DISPLAY_PLL] = &display_pll_clk.common.hw, + [CLK_DEV_PLL] = &dev_pll_clk.common.hw, + [CLK_AUDIO_PLL] = &audio_pll_clk.common.hw, + [CLK_TIMER] = &timer_clk.common.hw, + [CLK_DEV] = &dev_clk.common.hw, + [CLK_DE] = &de_clk.common.hw, + [CLK_DE1] = &de1_clk.common.hw, + [CLK_DE2] = &de2_clk.common.hw, + [CLK_I2C0] = &i2c0_clk.common.hw, + [CLK_I2C1] = &i2c1_clk.common.hw, + [CLK_I2C2] = &i2c2_clk.common.hw, + [CLK_I2C3] = &i2c3_clk.common.hw, + [CLK_I2SRX] = &i2srx_clk.common.hw, + [CLK_I2STX] = &i2stx_clk.common.hw, + [CLK_UART0] = &uart0_clk.common.hw, + [CLK_UART1] = &uart1_clk.common.hw, + [CLK_UART2] = &uart2_clk.common.hw, + [CLK_UART3] = &uart3_clk.common.hw, + [CLK_UART4] = &uart4_clk.common.hw, + [CLK_UART5] = &uart5_clk.common.hw, + [CLK_UART6] = &uart6_clk.common.hw, + [CLK_PWM0] = &pwm0_clk.common.hw, + [CLK_PWM1] = &pwm1_clk.common.hw, + [CLK_PWM2] = &pwm2_clk.common.hw, + [CLK_PWM3] = &pwm3_clk.common.hw, + [CLK_PWM4] = &pwm4_clk.common.hw, + [CLK_PWM5] = &pwm5_clk.common.hw, + [CLK_SENSOR0] = &sensor0_clk.common.hw, + [CLK_SENSOR1] = &sensor1_clk.common.hw, + [CLK_SD0] = &sd0_clk.common.hw, + [CLK_SD1] = &sd1_clk.common.hw, + [CLK_SD2] = &sd2_clk.common.hw, + [CLK_BISP] = &bisp_clk.common.hw, + [CLK_SPI0] = &spi0_clk.common.hw, + [CLK_SPI1] = &spi1_clk.common.hw, + [CLK_SPI2] = &spi2_clk.common.hw, + [CLK_SPI3] = &spi3_clk.common.hw, + [CLK_AHB] = &ahb_clk.common.hw, + [CLK_H] = &h_clk.common.hw, + [CLK_AHBPREDIV] = &ahbprediv_clk.common.hw, + [CLK_RMII_REF] = &rmii_ref_clk.common.hw, + [CLK_HDMI_AUDIO] = &hdmia_clk.common.hw, + [CLK_HDMI] = &hdmi_clk.common.hw, + [CLK_VDE] = &vde_clk.common.hw, + [CLK_VCE] = &vce_clk.common.hw, + [CLK_SPDIF] = &spdif_clk.common.hw, + [CLK_NAND] = &nand_clk.common.hw, + [CLK_ECC] = &ecc_clk.common.hw, + }, + .num = CLK_NR_CLKS, +}; + +static struct owl_clk_desc s500_clk_desc = { + .clks = s500_clks, + .num_clks = ARRAY_SIZE(s500_clks), + + .hw_clks = &s500_hw_clks, +}; + +static int s500_clk_probe(struct platform_device *pdev) +{ + struct owl_clk_desc *desc; + + desc = &s500_clk_desc; + owl_clk_regmap_init(pdev, desc); + + return owl_clk_probe(&pdev->dev, desc->hw_clks); +} + +static const struct of_device_id s500_clk_of_match[] = { + { .compatible = "actions,s500-cmu", }, + { /* sentinel */ } +}; + +static struct platform_driver s500_clk_driver = { + .probe = s500_clk_probe, + .driver = { + .name = "s500-cmu", + .of_match_table = s500_clk_of_match, + }, +}; + +static int __init s500_clk_init(void) +{ + return platform_driver_register(&s500_clk_driver); +} +core_initcall(s500_clk_init);