From patchwork Tue May 10 22:44:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Joseph S. Barrera III" X-Patchwork-Id: 571346 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5076CC4332F for ; Tue, 10 May 2022 22:46:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237296AbiEJWqg (ORCPT ); Tue, 10 May 2022 18:46:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51650 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237299AbiEJWqe (ORCPT ); Tue, 10 May 2022 18:46:34 -0400 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D80DF219F7D for ; Tue, 10 May 2022 15:46:32 -0700 (PDT) Received: by mail-pj1-x1030.google.com with SMTP id l7-20020a17090aaa8700b001dd1a5b9965so409784pjq.2 for ; Tue, 10 May 2022 15:46:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=cas3WrPYcOTITvsK8sqkdFJ7F5GSqZjy/I9tu4uL6bQ=; b=IfbnihDT4arwhhqau4ENKL0JOOsckZtTk9DCSl9mqxpej2mm+j3lIx02dFWMPs+zPB Ii/ymqTTRPQjK1Z7ZI/7fRpVzRG8/J54RD/5dAz5fFYFEWbzXbkIdsFzfdGzuoHo2HFj 4rN1kLB23a2vx/TRjmxmpYCc+BLH+lR0VDbhY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=cas3WrPYcOTITvsK8sqkdFJ7F5GSqZjy/I9tu4uL6bQ=; b=rRw2ix5gfQm1mXr0nOGqQWUKQecnZb7TYHH+kpL2TwNgWPGZvHYuY2Th1myjEm/hNv m+hrT7jVHEAVcyNweaK5m3/cgOO+VaTyVwbwJM7IDIaTRck/aHrl911jyUV8smwYzGEz AUzzG1VANQFwWLD2d61/bAxY4Dy+Hv+5KYJ5p0WJ4Bdl3YlGf0P9TQjor4+bTzZLQpel liC/D2Xss7GSzhbazVTJ9EZoJj3ALC0pCiTc/ZMOULUPt5Q8oUxQnmBfdWHmRx77irNL ERyktMao+yr4SyBo7Xge2os1FCSLxjiqgeyqUfdVW9ki6bonpAROf7CuT2S0VjNG/g1m A5dA== X-Gm-Message-State: AOAM5314arkQOCt+zlh9GeKQkWgun0WNfjhUBcJp8YWsLD6jZbEXZAeA ceY3TOVIIwqf9lQKbTLwuYGfKA== X-Google-Smtp-Source: ABdhPJzTzY+IJla5OGe4dLEoZ6S9pdx8wcO3mdLxuMYXpM1mNT2V6xsAlNMvuohTnXIS1Y3qor2xng== X-Received: by 2002:a17:902:7d93:b0:14d:d401:f59b with SMTP id a19-20020a1709027d9300b0014dd401f59bmr22825012plm.14.1652222792216; Tue, 10 May 2022 15:46:32 -0700 (PDT) Received: from joebar-glaptop.lan (c-71-202-34-56.hsd1.ca.comcast.net. [71.202.34.56]) by smtp.gmail.com with ESMTPSA id p14-20020a170902b08e00b0015e8da1fb07sm144256plr.127.2022.05.10.15.46.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 May 2022 15:46:31 -0700 (PDT) From: "Joseph S. Barrera III" To: LKML Cc: Douglas Anderson , Alexandru M Stan , "Joseph S. Barrera III" , Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v5 1/5] arm64: dts: qcom: sc7180: Add wormdingler dts files Date: Tue, 10 May 2022 15:44:23 -0700 Message-Id: <20220510154406.v5.1.Id769ddc5dbf570ccb511db96da59f97d08f75a9c@changeid> X-Mailer: git-send-email 2.31.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Wormdingler is a trogdor-based board, shipping to customers as the Lenovo IdeaPad Chromebook Duet 3. These dts files are copies from the downstream Chrome OS 5.4 kernel, but with the camera (sc7180-trogdor-mipi-camera.dtsi) #include removed. Signed-off-by: Joseph S. Barrera III --- Changes in v5: - Replaced _ in node name with - - Ordered nodes by name Changes in v4: - Cleaned up rt5682s files - Restored camcc definition - Added missing version history Changes in v3: - Removed camcc definition Changes in v2: - Word wrapped patch description. - Removed "Author" from patch description. - Fixed whitespace around "en_pp3300_dx_edp" arch/arm64/boot/dts/qcom/Makefile | 6 + .../sc7180-trogdor-wormdingler-rev0-boe.dts | 22 + .../sc7180-trogdor-wormdingler-rev0-inx.dts | 22 + .../qcom/sc7180-trogdor-wormdingler-rev0.dtsi | 53 +++ ...0-trogdor-wormdingler-rev1-boe-rt5682s.dts | 29 ++ .../sc7180-trogdor-wormdingler-rev1-boe.dts | 28 ++ ...0-trogdor-wormdingler-rev1-inx-rt5682s.dts | 29 ++ .../sc7180-trogdor-wormdingler-rev1-inx.dts | 22 + .../dts/qcom/sc7180-trogdor-wormdingler.dtsi | 417 ++++++++++++++++++ 9 files changed, 628 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-boe.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-inx.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 2f8aec2cc6db..e4114e22548a 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -81,6 +81,12 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3-lte.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev0-boe.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev0-inx.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-boe.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-inx.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-crd.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-boe.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-boe.dts new file mode 100644 index 000000000000..d6ed7d0afe4a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-boe.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x10 => 16 + * - bits 7..4: Panel ID: 0x1 (BOE) + */ + +/dts-v1/; + +#include "sc7180-trogdor-wormdingler-rev0.dtsi" + +/ { + model = "Google Wormdingler rev0 BOE panel board"; + compatible = "google,wormdingler-rev0-sku16", "qcom,sc7180"; +}; + +&panel { + compatible = "boe,tv110c9m-ll3"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-inx.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-inx.dts new file mode 100644 index 000000000000..c03525ea64ca --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-inx.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x0 => 0 + * - bits 7..4: Panel ID: 0x0 (INX) + */ + +/dts-v1/; + +#include "sc7180-trogdor-wormdingler-rev0.dtsi" + +/ { + model = "Google Wormdingler rev0 INX panel board"; + compatible = "google,wormdingler-rev0-sku0", "qcom,sc7180"; +}; + +&panel { + compatible = "innolux,hj110iz-01a"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi new file mode 100644 index 000000000000..db29e0cba29d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + * + */ + +/dts-v1/; + +#include "sc7180-trogdor-wormdingler.dtsi" + +&avdd_lcd { + gpio = <&tlmm 80 GPIO_ACTIVE_HIGH>; +}; + +&panel { + enable-gpios = <&tlmm 76 GPIO_ACTIVE_HIGH>; +}; + +&v1p8_mipi { + gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; +}; + +/* PINCTRL - modifications to sc7180-trogdor-wormdingler.dtsi */ +&avdd_lcd_en { + pinmux { + pins = "gpio80"; + }; + + pinconf { + pins = "gpio80"; + }; +}; + +&mipi_1800_en { + pinmux { + pins = "gpio81"; + }; + + pinconf { + pins = "gpio81"; + }; +}; +&vdd_reset_1800 { + pinmux { + pins = "gpio76"; + }; + + pinconf { + pins = "gpio76"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dts new file mode 100644 index 000000000000..aa605885c371 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x401 => 1025 + * - bits 11..8: Panel ID: 0x4 (BOE) + */ + +/dts-v1/; + +#include "sc7180-trogdor-wormdingler-rev1-boe.dts" + +/ { + model = "Google Wormdingler rev1+ (BOE, rt5682s)"; + compatible = "google,wormdingler-sku1025", "qcom,sc7180"; +}; + +&alc5682 { + compatible = "realtek,rt5682s"; + realtek,dmic1-clk-pin = <2>; + realtek,dmic-clk-rate-hz = <2048000>; +}; + +&sound { + compatible = "google,sc7180-trogdor"; + model = "sc7180-rt5682s-max98357a-1mic"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe.dts new file mode 100644 index 000000000000..c5b0658bd632 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x400 => 1024 + * - bits 11..8: Panel ID: 0x4 (BOE) + */ + +/dts-v1/; + +#include "sc7180-trogdor-wormdingler.dtsi" + +/ { + model = "Google Wormdingler rev1+ BOE panel board"; + compatible = "google,wormdingler-sku1024", "qcom,sc7180"; +}; + +&dsi_phy { + qcom,phy-rescode-offset-top = /bits/ 8 <31 31 31 31 (-32)>; + qcom,phy-rescode-offset-bot = /bits/ 8 <31 31 31 31 (-32)>; + qcom,phy-drive-ldo-level = <450>; +}; + +&panel { + compatible = "boe,tv110c9m-ll3"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dts new file mode 100644 index 000000000000..7116c44c8d85 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x0001 => 1 + * - bits 11..8: Panel ID: 0x0 (INX) + */ + +/dts-v1/; + +#include "sc7180-trogdor-wormdingler-rev1-inx.dts" + +/ { + model = "Google Wormdingler rev1+ (INX, rt5682s)"; + compatible = "google,wormdingler-sku1", "qcom,sc7180"; +}; + +&alc5682 { + compatible = "realtek,rt5682s"; + realtek,dmic1-clk-pin = <2>; + realtek,dmic-clk-rate-hz = <2048000>; +}; + +&sound { + compatible = "google,sc7180-trogdor"; + model = "sc7180-rt5682s-max98357a-1mic"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx.dts new file mode 100644 index 000000000000..dd34a2297ea0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x0000 => 0 + * - bits 11..8: Panel ID: 0x0 (INX) + */ + +/dts-v1/; + +#include "sc7180-trogdor-wormdingler.dtsi" + +/ { + model = "Google Wormdingler rev1+ INX panel board"; + compatible = "google,wormdingler-sku0", "qcom,sc7180"; +}; + +&panel { + compatible = "innolux,hj110iz-01a"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi new file mode 100644 index 000000000000..cced926364e5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi @@ -0,0 +1,417 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180.dtsi" + +ap_ec_spi: &spi6 {}; +ap_h1_spi: &spi0 {}; + +#include "sc7180-trogdor.dtsi" + +/ { + avdd_lcd: avdd-lcd { + compatible = "regulator-fixed"; + regulator-name = "avdd_lcd"; + + gpio = <&tlmm 88 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&avdd_lcd_en>; + + vin-supply = <&pp5000_a>; + }; + + avee_lcd: avee-lcd { + compatible = "regulator-fixed"; + regulator-name = "avee_lcd"; + + gpio = <&tlmm 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&avee_lcd_en>; + + vin-supply = <&pp5000_a>; + }; + + pp1800_ts: + v1p8_mipi: v1p8-mipi { + compatible = "regulator-fixed"; + regulator-name = "v1p8_mipi"; + + gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&mipi_1800_en>; + + vin-supply = <&pp3300_a>; + }; + + thermal-zones { + skin_temp_thermal: skin-temp-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&pm6150_adc_tm 1>; + sustainable-power = <574>; + + trips { + skin_temp_alert0: trip-point0 { + temperature = <58000>; + hysteresis = <1000>; + type = "passive"; + }; + + skin_temp_alert1: trip-point1 { + temperature = <62500>; + hysteresis = <1000>; + type = "passive"; + }; + + skin-temp-crit { + temperature = <68000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&skin_temp_alert0>; + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&skin_temp_alert1>; + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; + +&ap_tp_i2c { + status = "disabled"; +}; + +&backlight { + pwms = <&cros_ec_pwm 0>; +}; + +&camcc { + status = "okay"; +}; + +&cros_ec { + base_detection: cbas { + compatible = "google,cros-cbas"; + }; +}; + +&dsi0 { + + panel: panel@0 { + reg = <0>; + enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_reset_1800>; + avdd-supply = <&avdd_lcd>; + avee-supply = <&avee_lcd>; + pp1800-supply = <&v1p8_mipi>; + pp3300-supply = <&pp3300_dx_edp>; + backlight = <&backlight>; + rotation = <270>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; + + ports { + port@1 { + endpoint { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@1 { + compatible = "hid-over-i2c"; + reg = <0x01>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_l>; + + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + + post-power-on-delay-ms = <70>; + hid-descr-addr = <0x0001>; + + vdd-supply = <&pp3300_ts>; + vddl-supply = <&pp1800_ts>; + }; +}; + +&pm6150_adc { + skin-temp-thermistor@4d { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm6150_adc_tm { + status = "okay"; + + skin-temp-thermistor@1 { + reg = <1>; + io-channels = <&pm6150_adc ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pp1800_uf_cam { + status = "okay"; +}; + +&pp1800_wf_cam { + status = "okay"; +}; + +&pp2800_uf_cam { + status = "okay"; +}; + +&pp2800_wf_cam { + status = "okay"; +}; + +&wifi { + qcom,ath10k-calibration-variant = "GO_WORMDINGLER"; +}; + +/* + * No eDP on this board but it's logically the same signal so just give it + * a new name and assign the proper GPIO. + */ +pp3300_disp_on: &pp3300_dx_edp { + gpio = <&tlmm 85 GPIO_ACTIVE_HIGH>; +}; + +/* PINCTRL - modifications to sc7180-trogdor.dtsi */ + +/* + * No eDP on this board but it's logically the same signal so just give it + * a new name and assign the proper GPIO. + */ + +tp_en: &en_pp3300_dx_edp { + pinmux { + pins = "gpio85"; + }; + + pinconf { + pins = "gpio85"; + }; +}; + +/* PINCTRL - board-specific pinctrl */ + +&tlmm { + gpio-line-names = "HUB_RST_L", + "AP_RAM_ID0", + "AP_SKU_ID2", + "AP_RAM_ID1", + "", + "AP_RAM_ID2", + "UF_CAM_EN", + "WF_CAM_EN", + "TS_RESET_L", + "TS_INT_L", + "", + "", + "AP_EDP_BKLTEN", + "UF_CAM_MCLK", + "WF_CAM_CLK", + "", + "", + "UF_CAM_SDA", + "UF_CAM_SCL", + "WF_CAM_SDA", + "WF_CAM_SCL", + "AVEE_LCD_EN", + "", + "AMP_EN", + "", + "", + "", + "", + "HP_IRQ", + "WF_CAM_RST_L", + "UF_CAM_RST_L", + "AP_BRD_ID2", + "", + "AP_BRD_ID0", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "BT_UART_CTS", + "BT_UART_RTS", + "BT_UART_TXD", + "BT_UART_RXD", + "H1_AP_INT_ODL", + "", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "HP_I2C_SDA", + "HP_I2C_SCL", + "FORCED_USB_BOOT", + "AMP_BCLK", + "AMP_LRCLK", + "AMP_DIN", + "", + "HP_BCLK", + "HP_LRCLK", + "HP_DOUT", + "HP_DIN", + "HP_MCLK", + "AP_SKU_ID0", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "AP_SPI_CLK", + "AP_SPI_MOSI", + "AP_SPI_MISO", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_L. + */ + "AP_FLASH_WP_L", + "", + "AP_SPI_CS0_L", + "", + "", + "", + "", + "WLAN_SW_CTRL", + "", + "REPORT_E", + "", + "ID0", + "", + "ID1", + "", + "", + "", + "CODEC_PWR_EN", + "HUB_EN", + "TP_EN", + "MIPI_1.8V_EN", + "VDD_RESET_1.8V", + "AVDD_LCD_EN", + "", + "AP_SKU_ID1", + "AP_RST_REQ", + "", + "AP_BRD_ID1", + "AP_EC_INT_L", + "SDM_GRFC_3", + "", + "", + "BOOT_CONFIG_4", + "BOOT_CONFIG_2", + "", + "", + "", + "", + "", + "", + "", + "BOOT_CONFIG_3", + "WCI2_LTE_COEX_TXD", + "WCI2_LTE_COEX_RXD", + "", + "", + "", + "", + "FORCED_USB_BOOT_POL", + "AP_TS_PEN_I2C_SDA", + "AP_TS_PEN_I2C_SCL", + "DP_HOT_PLUG_DET", + "EC_IN_RW_ODL"; + + avdd_lcd_en: avdd-lcd-en { + pinmux { + pins = "gpio88"; + function = "gpio"; + }; + + pinconf { + pins = "gpio88"; + drive-strength = <2>; + bias-disable; + }; + }; + + avee_lcd_en: avee-lcd-en { + pinmux { + pins = "gpio21"; + function = "gpio"; + }; + + pinconf { + pins = "gpio21"; + drive-strength = <2>; + bias-disable; + }; + }; + + mipi_1800_en: mipi-1800-en { + pinmux { + pins = "gpio86"; + function = "gpio"; + }; + + pinconf { + pins = "gpio86"; + drive-strength = <2>; + bias-disable; + }; + }; + + vdd_reset_1800: vdd-reset-1800 { + pinmux { + pins = "gpio87"; + function = "gpio"; + }; + + pinconf { + pins = "gpio87"; + drive-strength = <2>; + bias-disable; + }; + }; +}; From patchwork Tue May 10 22:44:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Joseph S. Barrera III" X-Patchwork-Id: 571345 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BD0FC4332F for ; Tue, 10 May 2022 22:46:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237365AbiEJWqi (ORCPT ); Tue, 10 May 2022 18:46:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51650 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237323AbiEJWqg (ORCPT ); Tue, 10 May 2022 18:46:36 -0400 Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C80D221B164 for ; Tue, 10 May 2022 15:46:34 -0700 (PDT) Received: by mail-pj1-x1031.google.com with SMTP id cx11-20020a17090afd8b00b001d9fe5965b3so3194619pjb.3 for ; Tue, 10 May 2022 15:46:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5PuRerUjTeI8coAv5h8g14C2LQ6w5cW6RGkKNsh9rtI=; b=Q0gt5hOwl6c6dNRljdd7nHNBvGEwOUXTNLcJ6v3aeoSrJDbdzVT+n5Pjb7UbJU5lza nJHvLV6wX+ttBq5T5cFKodW34iYwIlutvKbT5kMNMfARyz+0NiS9eUw/SKX01V5oz1Vr ZpHK4P2WfNMpATEU8fy9xGR4yp61EYDygdb58= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5PuRerUjTeI8coAv5h8g14C2LQ6w5cW6RGkKNsh9rtI=; b=6tHEVwuYbLuCSqJiEXrNrDQ+H5oluaeHAIi9YoXzFMNB4Q8MY0tPNxPwokBlss6tqZ G89+Tb5jMMsCBBYPsBa1yx9Gp2jxKBlTVNbcFITpxUI8xyhTi+McjQUXJX3VnXXsL/vK xsH2oRy+DiPYECLoNKjcn0eW53Vbcles7XcfbpYi4R72NIwdDA9tNVWyLAyc6Im1ohXG CB73Na7SpH8e8MJP0fcWfm8TMegvB/aReevZx9HeoYtnMXt/57fCjVwupUyA5ZLSGczG kcvnVswLeXhvFPY9jm35VXpGYNnbJrzRaOGCuL1fdGQd7C68C4YWoLlSgEV7OmfYnP1m eAbQ== X-Gm-Message-State: AOAM5322TZfK8f4aUEkmKV9ckp7ahQMfgxjdlf2qt+A2di39PP130IUz tCf2BK8qbzlhW448zYm+zKxWiw== X-Google-Smtp-Source: ABdhPJwvZUNeRl7GhIRo7W0wbv/1wR8QXsT2iphKWnil1D1maujTwt2qPRxCbgUbW/JlY6/BBiI8UA== X-Received: by 2002:a17:903:1108:b0:15f:bce:19f8 with SMTP id n8-20020a170903110800b0015f0bce19f8mr12826511plh.7.1652222794324; Tue, 10 May 2022 15:46:34 -0700 (PDT) Received: from joebar-glaptop.lan (c-71-202-34-56.hsd1.ca.comcast.net. [71.202.34.56]) by smtp.gmail.com with ESMTPSA id p14-20020a170902b08e00b0015e8da1fb07sm144256plr.127.2022.05.10.15.46.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 May 2022 15:46:34 -0700 (PDT) From: "Joseph S. Barrera III" To: LKML Cc: Douglas Anderson , Alexandru M Stan , "Joseph S. Barrera III" , Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v5 3/5] arm64: dts: qcom: sc7180: Add quackingstick dts files Date: Tue, 10 May 2022 15:44:25 -0700 Message-Id: <20220510154406.v5.3.I0977b1a08830d0caa8bfb1bdedb4ecceac709a7f@changeid> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20220510154406.v5.1.Id769ddc5dbf570ccb511db96da59f97d08f75a9c@changeid> References: <20220510154406.v5.1.Id769ddc5dbf570ccb511db96da59f97d08f75a9c@changeid> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Quackingstick is a trogdor-based board. These dts files are copies from the downstream Chrome OS 5.4 kernel, but with downstream bits removed. Signed-off-by: Joseph S. Barrera III Reviewed-by: Douglas Anderson --- Changes in v5: - Removed extra newline - Added comment that compatible will be filled in per-board Changes in v4: - Added missing version history Changes in v3: - First inclusion in this series arch/arm64/boot/dts/qcom/Makefile | 2 + .../sc7180-trogdor-quackingstick-r0-lte.dts | 38 ++ .../qcom/sc7180-trogdor-quackingstick-r0.dts | 26 ++ .../qcom/sc7180-trogdor-quackingstick.dtsi | 324 ++++++++++++++++++ 4 files changed, 390 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0-lte.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 2330b5ea13bf..5cfd6316768c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -85,6 +85,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3-lte.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-quackingstick-r0.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-quackingstick-r0-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev0-boe.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev0-inx.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-boe.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0-lte.dts new file mode 100644 index 000000000000..35e8945fc56d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0-lte.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Quackingstick board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x600 => 1536 + * - bits 11..8: Panel ID: 0x6 (AUO) + */ + +#include "sc7180-trogdor-quackingstick-r0.dts" +#include "sc7180-trogdor-lte-sku.dtsi" + +/ { + model = "Google Quackingstick (rev0+) with LTE"; + compatible = "google,quackingstick-sku1536", "qcom,sc7180"; +}; + +&ap_sar_sensor { + compatible = "semtech,sx9324"; + semtech,ph0-pin = <3 1 3>; + semtech,ph1-pin = <2 1 2>; + semtech,ph2-pin = <3 3 1>; + semtech,ph3-pin = <1 3 3>; + semtech,ph01-resolution = <1024>; + semtech,ph23-resolution = <1024>; + semtech,startup-sensor = <1>; + semtech,ph01-proxraw-strength = <3>; + semtech,ph23-proxraw-strength = <3>; + semtech,avg-pos-strength = <256>; + + /delete-property/ svdd-supply; + vdd-supply = <&pp1800_prox>; +}; + +&ap_sar_sensor_i2c { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0.dts new file mode 100644 index 000000000000..5c81e44ed4a5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Quackingstick board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x601 => 1537 + * - bits 11..8: Panel ID: 0x6 (AUO) + */ + +#include "sc7180-trogdor-quackingstick.dtsi" + +/ { + model = "Google Quackingstick (rev0+)"; + compatible = "google,quackingstick-sku1537", "qcom,sc7180"; +}; + +&dsi_phy { + qcom,phy-rescode-offset-top = /bits/ 8 <(-13) (-13) (-13) (-13) (-13)>; + qcom,phy-rescode-offset-bot = /bits/ 8 <(-13) (-13) (-13) (-13) (-13)>; + qcom,phy-drive-ldo-level = <375>; +}; + +&panel { + compatible = "auo,b101uan08.3"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi new file mode 100644 index 000000000000..d39f43757932 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi @@ -0,0 +1,324 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Quackingstick board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180.dtsi" + +ap_ec_spi: &spi6 {}; +ap_h1_spi: &spi0 {}; + +#include "sc7180-trogdor.dtsi" + +/ { + ppvar_lcd: ppvar-lcd { + compatible = "regulator-fixed"; + regulator-name = "ppvar_lcd"; + + gpio = <&tlmm 88 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&ppvar_lcd_en>; + + vin-supply = <&pp5000_a>; + }; + + v1p8_disp: v1p8-disp { + compatible = "regulator-fixed"; + regulator-name = "v1p8_disp"; + + gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&pp1800_disp_on>; + + vin-supply = <&pp3300_a>; + }; +}; + +&ap_tp_i2c { + status = "disabled"; +}; + +&backlight { + pwms = <&cros_ec_pwm 0>; +}; + +&camcc { + status = "okay"; +}; + +&dsi0 { + panel: panel@0 { + /* Compatible will be filled in per-board */ + reg = <0>; + enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst>; + avdd-supply = <&ppvar_lcd>; + pp1800-supply = <&v1p8_disp>; + pp3300-supply = <&pp3300_dx_edp>; + backlight = <&backlight>; + rotation = <270>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; + + ports { + port@1 { + endpoint { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&gpio_keys { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; + + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + + post-power-on-delay-ms = <20>; + hid-descr-addr = <0x0001>; + + vdd-supply = <&pp3300_ts>; + }; +}; + +&sdhc_2 { + status = "okay"; +}; + +&pp1800_uf_cam { + status = "okay"; +}; + +&pp1800_wf_cam { + status = "okay"; +}; + +&pp2800_uf_cam { + status = "okay"; +}; + +&pp2800_wf_cam { + status = "okay"; +}; + +/* + * No eDP on this board but it's logically the same signal so just give it + * a new name and assign the proper GPIO. + */ +pp3300_disp_on: &pp3300_dx_edp { + gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; +}; + +/* PINCTRL - modifications to sc7180-trogdor.dtsi */ + +/* + * No eDP on this board but it's logically the same signal so just give it + * a new name and assign the proper GPIO. + */ + +tp_en: &en_pp3300_dx_edp { + pinmux { + pins = "gpio67"; + }; + + pinconf { + pins = "gpio67"; + }; +}; + +/* PINCTRL - board-specific pinctrl */ + +&tlmm { + gpio-line-names = "HUB_RST_L", + "AP_RAM_ID0", + "AP_SKU_ID2", + "AP_RAM_ID1", + "", + "AP_RAM_ID2", + "UF_CAM_EN", + "WF_CAM_EN", + "TS_RESET_L", + "TS_INT_L", + "", + "", + "AP_EDP_BKLTEN", + "UF_CAM_MCLK", + "WF_CAM_CLK", + "EDP_BRIJ_I2C_SDA", + "EDP_BRIJ_I2C_SCL", + "UF_CAM_SDA", + "UF_CAM_SCL", + "WF_CAM_SDA", + "WF_CAM_SCL", + "", + "", + "AMP_EN", + "P_SENSOR_INT_L", + "AP_SAR_SENSOR_SDA", + "AP_SAR_SENSOR_SCL", + "", + "HP_IRQ", + "WF_CAM_RST_L", + "UF_CAM_RST_L", + "AP_BRD_ID2", + "", + "AP_BRD_ID0", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "", + "", + "", + "", + "H1_AP_INT_ODL", + "", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "HP_I2C_SDA", + "HP_I2C_SCL", + "FORCED_USB_BOOT", + "", + "", + "AMP_DIN", + "PEN_DET_ODL", + "HP_BCLK", + "HP_LRCLK", + "HP_DOUT", + "HP_DIN", + "HP_MCLK", + "AP_SKU_ID0", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "AP_SPI_CLK", + "AP_SPI_MOSI", + "AP_SPI_MISO", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_L. + */ + "AP_FLASH_WP_L", + "EN_PP3300_DX_EDP", + "AP_SPI_CS0_L", + "SD_CD_ODL", + "", + "", + "", + "", + "", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RST", + "UIM2_PRESENT_L", + "UIM1_DATA", + "UIM1_CLK", + "UIM1_RST", + "", + "CODEC_PWR_EN", + "HUB_EN", + "", + "PP1800_DISP_ON", + "LCD_RST", + "PPVAR_LCD_EN", + "", + "AP_SKU_ID1", + "AP_RST_REQ", + "", + "AP_BRD_ID1", + "AP_EC_INT_L", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "AP_TS_I2C_SDA", + "AP_TS_I2C_SCL", + "DP_HOT_PLUG_DET", + "EC_IN_RW_ODL"; + + lcd_rst: lcd-rst { + pinmux { + pins = "gpio87"; + function = "gpio"; + }; + + pinconf { + pins = "gpio87"; + drive-strength = <2>; + bias-disable; + }; + }; + + ppvar_lcd_en: ppvar-lcd-en { + pinmux { + pins = "gpio88"; + function = "gpio"; + }; + + pinconf { + pins = "gpio88"; + drive-strength = <2>; + bias-disable; + }; + }; + + pp1800_disp_on: pp1800-disp-on { + pinmux { + pins = "gpio86"; + function = "gpio"; + }; + + pinconf { + pins = "gpio86"; + drive-strength = <2>; + bias-disable; + }; + }; +}; From patchwork Tue May 10 22:44:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Joseph S. Barrera III" X-Patchwork-Id: 571344 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E98CAC43219 for ; Tue, 10 May 2022 22:46:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237363AbiEJWqr (ORCPT ); Tue, 10 May 2022 18:46:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52054 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237359AbiEJWqi (ORCPT ); Tue, 10 May 2022 18:46:38 -0400 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EC83021E310 for ; Tue, 10 May 2022 15:46:36 -0700 (PDT) Received: by mail-pj1-x102d.google.com with SMTP id fv2so505702pjb.4 for ; Tue, 10 May 2022 15:46:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hjptzdLf1gCERRe02HGCOwCzQVmJOB0+x939FyCO2xQ=; b=UTR1LJELBHWGz2oZWIf4FZ9wkS4cdIU5/OPogOMwxbxYC0JxuWTU2Flp7c6ZniAlFu 0WIKbumbh5coQaRfZ2SDSdJ1m8UKnNE6K8uv1In//N9qCOZzgG9GsCw+prJ/uOcbvo47 e1uXpUN2TH/ZYdB/b7bEjB7Q4B2KS3XC+LjM4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hjptzdLf1gCERRe02HGCOwCzQVmJOB0+x939FyCO2xQ=; b=nkqw/xGocIYbZFa3vH572XxXybJVmzJqrel6Va5yWap+F1LQ455V2FB2NSEaikWG9l XKgJGhiZXJkLSQA/hLFDviGkhrbegC1T+j3AP6z2C5fnIThzOyXEoK+fgNuR3dxSypQY xgA8h3+I5+BQIA2vUcDxoZ54UuIQ036dWQTWdthHtD7stdUkY06b5WC9jlrhA/IrKH8h hxec8WkTcBgj5syGqM/ffqpO9P2eiGE4pLrWPs+/JQYNd1mCJGo993/f2nsoMiVaR3yq OgUN6YtWXIJglhrEP1Hc5V3LiB5yvIexcXbjlmOuvv8HJqxDTqYC0CjS2Wq353paUq6d eL2w== X-Gm-Message-State: AOAM531aXu9dJs8RE3ocW15QthJkoi/NoFc/qdlJgnq6/gMaidM+V6Hx U4gRFbcNjyM9CvvwMqO2FfQP3g== X-Google-Smtp-Source: ABdhPJzW1E1iZrRpdEmwEsNqWUXZIKICMDN0NFlHOEp7blO5hf+MCQQ/MCKASTYQI79yvuEuTfx02Q== X-Received: by 2002:a17:902:e882:b0:15e:b9e8:ba1b with SMTP id w2-20020a170902e88200b0015eb9e8ba1bmr22783526plg.71.1652222796619; Tue, 10 May 2022 15:46:36 -0700 (PDT) Received: from joebar-glaptop.lan (c-71-202-34-56.hsd1.ca.comcast.net. [71.202.34.56]) by smtp.gmail.com with ESMTPSA id p14-20020a170902b08e00b0015e8da1fb07sm144256plr.127.2022.05.10.15.46.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 May 2022 15:46:36 -0700 (PDT) From: "Joseph S. Barrera III" To: LKML Cc: Douglas Anderson , Alexandru M Stan , "Joseph S. Barrera III" , Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v5 5/5] arm64: dts: qcom: sc7180: Add kingoftown dts files Date: Tue, 10 May 2022 15:44:27 -0700 Message-Id: <20220510154406.v5.5.Ib62291487a664a65066d18a3e83c5428a6d2cc6c@changeid> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20220510154406.v5.1.Id769ddc5dbf570ccb511db96da59f97d08f75a9c@changeid> References: <20220510154406.v5.1.Id769ddc5dbf570ccb511db96da59f97d08f75a9c@changeid> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Kingoftown is a trogdor-based board. These dts files are unchanged copies from the downstream Chrome OS 5.4 kernel. Signed-off-by: Joseph S. Barrera III Reviewed-by: Douglas Anderson --- (no changes since v4) Changes in v4: - Fixed description (no downstream bits removed). - Added missing version history. Changes in v3: - None Changes in v2: - First inclusion in series. arch/arm64/boot/dts/qcom/Makefile | 2 + .../dts/qcom/sc7180-trogdor-kingoftown-r0.dts | 44 ++++ .../dts/qcom/sc7180-trogdor-kingoftown-r1.dts | 17 ++ .../dts/qcom/sc7180-trogdor-kingoftown.dtsi | 223 ++++++++++++++++++ 4 files changed, 286 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r1.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index dc26704dfe34..a9f2ad013179 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -60,6 +60,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r4.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-kingoftown-r0.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-kingoftown-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts new file mode 100644 index 000000000000..85aec1be98fc --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Kingoftown board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" +#include "sc7180-trogdor-kingoftown.dtsi" + +/ { + model = "Google Kingoftown (rev0)"; + compatible = "google,kingoftown-rev0", "qcom,sc7180"; +}; + +/* + * In rev1+, the enable pin of pp3300_fp_tp will be tied to pp1800_l10a + * power rail instead, since kingoftown does not have FP. + */ +&pp3300_fp_tp { + gpio = <&tlmm 74 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&en_fp_rails>; +}; + +&tlmm { + en_fp_rails: en-fp-rails { + pinmux { + pins = "gpio74"; + function = "gpio"; + }; + + pinconf { + pins = "gpio74"; + drive-strength = <2>; + bias-disable; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r1.dts new file mode 100644 index 000000000000..2be9138ba89f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r1.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Kingoftown board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180.dtsi" +#include "sc7180-trogdor-parade-ps8640.dtsi" +#include "sc7180-trogdor-kingoftown.dtsi" + +/ { + model = "Google Kingoftown (rev1+)"; + compatible = "google,kingoftown", "qcom,sc7180"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi new file mode 100644 index 000000000000..e7503a5b0403 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Kingoftown board device tree source + * + * Copyright 2021 Google LLC. + */ + +ap_ec_spi: &spi6 {}; +ap_h1_spi: &spi0 {}; + +#include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-lte-sku.dtsi" + +&alc5682 { + compatible = "realtek,rt5682s"; + realtek,dmic1-clk-pin = <2>; + realtek,dmic-clk-rate-hz = <2048000>; +}; + +ap_ts_pen_1v8: &i2c4 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@10 { + compatible = "elan,ekth3500"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; + + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + + vcc33-supply = <&pp3300_ts>; + + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; + }; +}; + +&keyboard_controller { + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + + CROS_STD_MAIN_KEYMAP + >; +}; + +&panel { + compatible = "edp-panel"; +}; + +&pp3300_dx_edp { + gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; +}; + +&sound { + compatible = "google,sc7180-trogdor"; + model = "sc7180-rt5682s-max98357a-1mic"; +}; + +&wifi { + qcom,ath10k-calibration-variant = "GO_KINGOFTOWN"; +}; + +/* PINCTRL - modifications to sc7180-trogdor.dtsi */ + +&en_pp3300_dx_edp { + pinmux { + pins = "gpio67"; + }; + + pinconf { + pins = "gpio67"; + }; +}; + +/* PINCTRL - board-specific pinctrl */ + +&tlmm { + gpio-line-names = "TP_INT_L", /* 0 */ + "AP_RAM_ID0", + "AP_SKU_ID2", + "AP_RAM_ID1", + "", + "AP_RAM_ID2", + "AP_TP_I2C_SDA", + "AP_TP_I2C_SCL", + "TS_RESET_L", + "TS_INT_L", + "", /* 10 */ + "EDP_BRIJ_IRQ", + "AP_EDP_BKLTEN", + "", + "", + "EDP_BRIJ_I2C_SDA", + "EDP_BRIJ_I2C_SCL", + "HUB_RST_L", + "", + "", + "", /* 20 */ + "", + "", + "AMP_EN", + "", + "", + "", + "", + "HP_IRQ", + "", + "", /* 30 */ + "AP_BRD_ID2", + "BRIJ_SUSPEND", + "AP_BRD_ID0", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "BT_UART_CTS", + "BT_UART_RTS", + "BT_UART_TXD", /* 40 */ + "BT_UART_RXD", + "H1_AP_INT_ODL", + "", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "HP_I2C_SDA", + "HP_I2C_SCL", + "FORCED_USB_BOOT", + "AMP_BCLK", + "AMP_LRCLK", /* 50 */ + "AMP_DIN", + "", + "HP_BCLK", + "HP_LRCLK", + "HP_DOUT", + "HP_DIN", + "HP_MCLK", + "AP_SKU_ID0", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", /* 60 */ + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "AP_SPI_CLK", + "AP_SPI_MOSI", + "AP_SPI_MISO", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_L. + */ + "AP_FLASH_WP_L", + "EN_PP3300_DX_EDP", + "AP_SPI_CS0_L", + "", + "", /* 70 */ + "", + "", + "", + "EN_FP_RAILS", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RST", + "UIM2_PRESENT_L", + "UIM1_DATA", + "UIM1_CLK", /* 80 */ + "UIM1_RST", + "", + "CODEC_PWR_EN", + "HUB_EN", + "", + "", + "", + "", + "", + "AP_SKU_ID1", /* 90 */ + "AP_RST_REQ", + "", + "AP_BRD_ID1", + "AP_EC_INT_L", + "", + "", + "", + "", + "", + "", /* 100 */ + "", + "", + "", + "EDP_BRIJ_EN", + "", + "", + "", + "", + "", + "", /* 110 */ + "", + "", + "", + "", + "AP_TS_PEN_I2C_SDA", + "AP_TS_PEN_I2C_SCL", + "DP_HOT_PLUG_DET", + "EC_IN_RW_ODL"; +};