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[209.132.180.67]) by mx.google.com with ESMTP id t136si14911005pfc.262.2019.01.04.23.29.34; Fri, 04 Jan 2019 23:29:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EJZ0d7pU; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726257AbfAEH3b (ORCPT + 7 others); Sat, 5 Jan 2019 02:29:31 -0500 Received: from mail-pf1-f196.google.com ([209.85.210.196]:34086 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726234AbfAEH3b (ORCPT ); Sat, 5 Jan 2019 02:29:31 -0500 Received: by mail-pf1-f196.google.com with SMTP id h3so19353609pfg.1 for ; Fri, 04 Jan 2019 23:29:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZLG0p6pOlEKJqG/ydnT1Alp81sx/m3rHMuhpQtuwbbQ=; b=EJZ0d7pU3z4gJ3luqtxOqm0cnFR6Y/svP6seHeGrN6D5WenFUCJxOKk0VJGRiqC0bB p7pssvPaglrTPqs6h3o7FM6BRLrQL5yM5PbDTgzI7TjyZIi+DUdkIhUxxvHiXXiWOez0 tmtExd9B9GDOVDttEHfFoS2oGg2IIVmEIGfFw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZLG0p6pOlEKJqG/ydnT1Alp81sx/m3rHMuhpQtuwbbQ=; b=ZNQsIB5rBC8qrdc09qsUnekS0SO/N+b7EvM1NDIbHCMhRYzeFLXahpBClPuvnul9Gt el/sBf7ZsQc4Vg4/jbwUB68aARQQ1fp46XKENAVIbtTSi3b3OkZ23Nf7m1tpJiWeSILX eqxp1aqybNBmT4HrjLdbuoFMLRRHFLrELr0eaeDhhHPckHmQba2IR4vPMx5VIGXu+Xqq j3TAkSheaSi9QlzyS0COfWmWxe86Q4e7s0uL8wLCovxk3YO/tZ9GS6FgbjXJ5ug8ti+r Tmx3wVG3Uil8m125e9hfaQoeL5ERE54vKOlZ7ZzyHoQjVMhoTQdoeJ+6V5G51oqE5A48 0MhQ== X-Gm-Message-State: AJcUukfwmwRtdcR3e+NcJv7KvzXLuSj6DPWOTlLAmRcnoSd4JEc9r1Zb IUH3UCdb2WOgot7jtXdogvDq X-Received: by 2002:a63:5723:: with SMTP id l35mr22381883pgb.228.1546673370470; Fri, 04 Jan 2019 23:29:30 -0800 (PST) Received: from localhost.localdomain ([2405:204:72cb:a88d:406c:3ac8:e78f:4779]) by smtp.gmail.com with ESMTPSA id k24sm90677367pfj.13.2019.01.04.23.29.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Jan 2019 23:29:29 -0800 (PST) From: Manivannan Sadhasivam To: vinholikatti@gmail.com, jejb@linux.vnet.ibm.com, martin.petersen@oracle.com, liwei213@huawei.com, robh+dt@kernel.org Cc: linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, john.stultz@linaro.org, amit.kucheria@linaro.org, guodong.xu@linaro.org, Manivannan Sadhasivam Subject: [PATCH v2 2/3] arm64: dts: hisilicon: hi3670: Add UFS controller support Date: Sat, 5 Jan 2019 12:58:58 +0530 Message-Id: <20190105072859.9134-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190105072859.9134-1-manivannan.sadhasivam@linaro.org> References: <20190105072859.9134-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add UFS controller support for HiSilicon HI3670 SoC. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 6ccdf5040ffd..285219dd657f 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -654,6 +654,24 @@ clock-names = "apb_pclk"; }; + /* UFS */ + ufs: ufs@ff3c0000 { + compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1"; + /* 0: HCI standard */ + /* 1: UFS SYS CTRL */ + reg = <0x0 0xff3c0000 0x0 0x1000>, + <0x0 0xff3e0000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>, + <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>; + clock-names = "ref_clk", "phy_clk"; + freq-table-hz = <0 0>, <0 0>; + /* offset: 0x84; bit: 12 */ + resets = <&crg_rst 0x84 12>; + reset-names = "rst"; + }; + /* SD */ dwmmc1: dwmmc1@ff37f000 { compatible = "hisilicon,hi3670-dw-mshc";