From patchwork Tue Jan 8 16:30:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154989 Delivered-To: patches@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp5070097jaa; Tue, 8 Jan 2019 08:30:12 -0800 (PST) X-Received: by 2002:adf:eec9:: with SMTP id a9mr1920663wrp.242.1546965012729; Tue, 08 Jan 2019 08:30:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546965012; cv=none; d=google.com; s=arc-20160816; b=06CvNRNTHRlAvnq3VWwjhFCucAJjUS+ZesL3z59CrdJh9utaKYR/27FYWJqMpXLE7f 4vQl+XwTT8mJsPhqr1DPh/36HYlv74ojLlMpYrOy5AtaCH/fOvPDRfL1QSrdrVIkjeuX ZAbWq6ySEiQa3Fc0LVByaM0gOVXhzCGMh8hdU1UTdqJ2t8sun2qCMHrNgNOwTRaIO0ey 41u82eIroBatTP351FXfR/gmmwDMGy/RGLCCmZvYhFwRsZ4QJIqX1Hz9izGn28p6ftVU Nk05OX2Uu4YVUqZrEVJgV7gRTSBCIQscbE6jcNCr5q/xlhDqarwZnyq2C6C2BI8COSuy xfyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=8TvLhHeHZ8C43Ib56UzJG7XSdaUbxT7qr+rCEbqz1Ng=; b=k/8eOUHmZ8yUvauYdm6oEHZ11KrdaAcxarlWMGtPc4Ndm9vy486gH70hIP7l3Hjm2b 0q6MvOcgJZ6QsfPVhoOoWdLO/wOtPV1YuR5xrV1qs/4SONnpNZ+vksF/ZDLybHYR4P5i DNzVrM0SCrc4xVnMAf9lzq29U/K7bmPsQLX5mEAhrpclSKFeiKe6+nCWEPLCgAyaXPca 8Brtlou7hYOL+TCREny8Miw/KxPphSaA1bZp4f88bs+1jSeHFAvriqObKYlVFXCdZDzF hybtoRwgfzkxJbZJZVlZUwKYTQ4gG/rpvB2+qzh3Yj2TGlF5G6iEIA2n+dyl/IvK0i/X dz0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OD1j2net; spf=pass (google.com: domain of peter.maydell@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=peter.maydell@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id b17sor37876082wrt.48.2019.01.08.08.30.12 for (Google Transport Security); Tue, 08 Jan 2019 08:30:12 -0800 (PST) Received-SPF: pass (google.com: domain of peter.maydell@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OD1j2net; spf=pass (google.com: domain of peter.maydell@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=peter.maydell@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8TvLhHeHZ8C43Ib56UzJG7XSdaUbxT7qr+rCEbqz1Ng=; b=OD1j2netgEyGE6MXVCLp5wTzMppg3ETryCQe6xQ8ubpj8ybsL8WJMjh9ABEEzUeW60 F3DWwWLRHzcwrR9YDAYk9RFlqocA+R/js2DZ4pVue5Yzm53WPHsL+2EkYEGZy0podt1o aga6nAqdRm8AgcPLXAEbpwGoxCSKvm/DcoiMU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8TvLhHeHZ8C43Ib56UzJG7XSdaUbxT7qr+rCEbqz1Ng=; b=C905I9FHN2Ui1WRdw7iSS+7uT27PxNICS94pGVmxP5UiLcuuJ37tHKgTo8IPdlND8N Qi70edHKvt0pY7UtqJgkEbJ0XeFfnp+z3AV7i39HyHBaw/iod2W2FQVAZoB9RyzpOa7U u+FXSymt0FgJZh50fqymDgESQ9tVmornHMoKU5oqgvrMI7Bs7TLsRsNQuDs+BzpO8CdJ xKdHS+C6kyI5+GPon9OTfWx31peNQgb6iPL1yR42/U1L5xfcFsksbzAmyhs9/lCM2uIA Ut/2ptpiSGsockfjSy6/0ZTarKw93cC6x6q3R7W0vkIY8lMLLKMy3zgBn00eN13hoOtW arPQ== X-Gm-Message-State: AJcUukfYK5wec7srqlol2Uyka5wtI4P58hh/neexYCwKKgtN3egOzW3q beszqvQyMlvx/vxQBZAvrfiLcuDO X-Google-Smtp-Source: ALg8bN5xoqxOYLsxVi9NPFmNiYUfuRBU4ebmZEZNPZlY4OvPOMCVOr9r9FW8Pk5wOvduZ0DOuY6I6A== X-Received: by 2002:a05:6000:100f:: with SMTP id a15mr2074153wrx.298.1546965012378; Tue, 08 Jan 2019 08:30:12 -0800 (PST) Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id x81sm11278839wmg.17.2019.01.08.08.30.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 08 Jan 2019 08:30:11 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Richard Henderson , Peter Crosthwaite , Paolo Bonzini , Alistair Francis , "Edgar E. Iglesias" , Eduardo Habkost , Marcel Apfelbaum , "Emilio G . Cota" Subject: [PATCH 1/4] hw/arm/xlx-zynqmp: Realize cluster after putting RPUs in it Date: Tue, 8 Jan 2019 16:30:05 +0000 Message-Id: <20190108163008.7006-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190108163008.7006-1-peter.maydell@linaro.org> References: <20190108163008.7006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Currently the cluster implementation doesn't have any constraints on the ordering of realizing the TYPE_CPU_CLUSTER and populating it with child objects. We want to impose a constraint that realize must happen only after all the child objects are added, so move the realize of rpu_cluster. (The apu_cluster is already realized after child population.) Signed-off-by: Peter Maydell --- hw/arm/xlnx-zynqmp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.19.2 Reviewed-by: Luc Michel Reviewed-by: Alistair Francis diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index c67ac2e64ac..370b0e44a38 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -183,8 +183,6 @@ static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu, &error_abort, NULL); qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); - qdev_init_nofail(DEVICE(&s->rpu_cluster)); - for (i = 0; i < num_rpus; i++) { char *name; @@ -212,6 +210,8 @@ static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu, return; } } + + qdev_init_nofail(DEVICE(&s->rpu_cluster)); } static void xlnx_zynqmp_init(Object *obj) From patchwork Tue Jan 8 16:30:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154990 Delivered-To: patches@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp5070129jaa; Tue, 8 Jan 2019 08:30:14 -0800 (PST) X-Received: by 2002:a5d:628a:: with SMTP id k10mr1896295wru.254.1546965014680; Tue, 08 Jan 2019 08:30:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546965014; cv=none; d=google.com; s=arc-20160816; b=0hxHHlcmOJgADLbyj+uCPz197v76Evx1Gw8MEKzQGLGWkzflKHvzngzBHXu5XBkxlQ nQ2pDVBEcRx1LebQ9sMOZXfTG5cilecCzkCwBW5YqPWIgPpfVXGyVp26JNR8gSikz+eP Rfa45ZeNxz3xQewIslTmG/ptJ3DBkXU0y7ztM71Ew90ZUeOKSJp/4HnFZ8+6TTxr4gq7 X8uurVrz9qOv1CgUuHUYv1gPbhvt2bIqDpO8gVSms9z3fJq5dcnLLxbneSegxqLiUHzV T6dO/1P6XvSnm27qwtMp6KLHPhga4XPDOhXRi7exxa39Y2LUJDeMfdkAXvZQaPnjfugi PqhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=YbQA+DVaTaDYVaQxTwMAtKAWfFrdJhgpXzSxOuBbRnM=; b=w/S/E8xHt1N3sM7g4xBJgFIWIk8D0v0NZwlUXQo6fE43pV7/YDXIBORmTN5a0ZT9W+ RSO9Zfs8WLSqnna24n1AOA7uWI+y/ZgLe/WvvpJrV2VnLI1qYs23vPYQ6/0aCqb+87yV 6AVzDkGM8zubEEtdpv5S88l0H4x42TmzlFLfPUBSy401y22OH4hZpk0HJku7SuHnqegj kQ3ckEcGBUb1xGT97Q2COnLbe/dOb44xverSsNh/HfAI4bE5iq2931lu2KrP+5lSqPT/ 8OXA/4lZuvSMpQ2088aCRBEABA6ePY43ZJlqJLFq+EL9U4SKtBuE8s+IS4QF67v6z94z RX0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GC4QfhBe; spf=pass (google.com: domain of peter.maydell@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=peter.maydell@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id f193sor7486561wme.9.2019.01.08.08.30.14 for (Google Transport Security); Tue, 08 Jan 2019 08:30:14 -0800 (PST) Received-SPF: pass (google.com: domain of peter.maydell@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GC4QfhBe; spf=pass (google.com: domain of peter.maydell@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=peter.maydell@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YbQA+DVaTaDYVaQxTwMAtKAWfFrdJhgpXzSxOuBbRnM=; b=GC4QfhBeddbU6aUBlbRYZ6v4jU+85Qu2Z5QAfue52hBcgixrikT7jYJEkJ5+VZZQvW QvvA/jW7wOjhKOfoGFVWD766/SlAYy0SsplNHAvRp5nfv2SBQ78DQrfGyjiaQzgPnV/j MwwW0MfxWHQqlqqCUIpcNgxUquHfZt4HUD4Tg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YbQA+DVaTaDYVaQxTwMAtKAWfFrdJhgpXzSxOuBbRnM=; b=qu9rHCmvEW+780qTpkAwXG6So6nQm6Lj+mS69AijGfCX0NBlu0CbKYV6F/yfKctAcQ rBwiq3TXnHe7fKcH42rRmZElUikNamQHh2wvsfykqpmiCbaU4slNCAev4mMiZiT8IrHU mF0tZ6+We+Fvto+x8Vk9sgMIAvz3jvPr22C7pwE69LJGt6GkYvK0wEYYg9J8V9bkJL8t 0FHe/XzJwao5hhMVsF47p7yiQe/8AKjPE7LupgQedqOYozDfPpChYmd066kAUcnTupOh xqOOQlJRDUz4s4zQAEQoAZUjSnqNZ/EBhAhEmgDxs6WAGIv0SwSljmcF0KHHaQyNexHu RVsQ== X-Gm-Message-State: AJcUukcYyf8SrxgnggVSNWNe4rvcQYY3JUp6X27dEdPMgJs8u9g7ATeb c0Hvg51oHUsh0ATcbH5hCsnzIB4d X-Google-Smtp-Source: ALg8bN5XZ3IBaDzH8QJBkh7u+q3aP3ppBSeTZjilUQdKIjPfLHOfQEul1oKCbO2O4wm/JkLogFQJFA== X-Received: by 2002:a1c:9e4a:: with SMTP id h71mr2405012wme.82.1546965013904; Tue, 08 Jan 2019 08:30:13 -0800 (PST) Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id x81sm11278839wmg.17.2019.01.08.08.30.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 08 Jan 2019 08:30:13 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Richard Henderson , Peter Crosthwaite , Paolo Bonzini , Alistair Francis , "Edgar E. Iglesias" , Eduardo Habkost , Marcel Apfelbaum , "Emilio G . Cota" Subject: [PATCH 2/4] qom/cpu: Add cluster_index to CPUState Date: Tue, 8 Jan 2019 16:30:06 +0000 Message-Id: <20190108163008.7006-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190108163008.7006-1-peter.maydell@linaro.org> References: <20190108163008.7006-1-peter.maydell@linaro.org> MIME-Version: 1.0 For TCG we want to distinguish which cluster a CPU is in, and we need to do it quickly. Cache the cluster index in the CPUState struct, by having the cluster object set cpu->cluster_index for each CPU child when it is realized. This means that board/SoC code must add all CPUs to the cluster before realizing the cluster object. Regrettably QOM provides no way to prevent adding children to a realized object and no way for the parent to be notified when a new child is added to it, so we don't have any way to enforce/assert this constraint; all we can do is document it in a comment. The restriction on how many clusters can exist in the system is imposed by TCG code which will be added in a subsequent commit, but the check to enforce it in cluster.c fits better in this one. Signed-off-by: Peter Maydell --- include/hw/cpu/cluster.h | 19 +++++++++++++++++++ include/qom/cpu.h | 7 +++++++ hw/cpu/cluster.c | 33 +++++++++++++++++++++++++++++++++ qom/cpu.c | 1 + 4 files changed, 60 insertions(+) -- 2.19.2 Reviewed-by: Luc Michel diff --git a/include/hw/cpu/cluster.h b/include/hw/cpu/cluster.h index 73818232437..d1bef315d10 100644 --- a/include/hw/cpu/cluster.h +++ b/include/hw/cpu/cluster.h @@ -34,12 +34,31 @@ * Arm big.LITTLE system) they should be in different clusters. If the CPUs do * not have the same view of memory (for example the main CPU and a management * controller processor) they should be in different clusters. + * + * A cluster is created by creating an object of TYPE_CPU_CLUSTER, and then + * adding the CPUs to it as QOM child objects (e.g. using the + * object_initialize_child() or object_property_add_child() functions). + * All CPUs must be added as children before the cluster is realized. + * (Regrettably QOM provides no way to prevent adding children to a realized + * object and no way for the parent to be notified when a new child is added + * to it, so this restriction is not checked for, but the system will not + * behave correctly if it is not adhered to.) + * + * A CPU which is not put into any cluster will be considered implicitly + * to be in a cluster with all the other "loose" CPUs, so all CPUs that are + * not assigned to clusters must be identical. */ #define TYPE_CPU_CLUSTER "cpu-cluster" #define CPU_CLUSTER(obj) \ OBJECT_CHECK(CPUClusterState, (obj), TYPE_CPU_CLUSTER) +/* + * This limit is imposed by TCG, which puts the cluster ID into an + * 8 bit field (and uses all-1s for the default "not in any cluster"). + */ +#define MAX_CLUSTERS 255 + /** * CPUClusterState: * @cluster_id: The cluster ID. This value is for internal use only and should diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 1396f53e5b5..844becbcedc 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -279,6 +279,11 @@ struct qemu_work_item; /** * CPUState: * @cpu_index: CPU index (informative). + * @cluster_index: Identifies which cluster this CPU is in. + * For boards which don't define clusters or for "loose" CPUs not assigned + * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will + * be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER + * QOM parent. * @nr_cores: Number of cores within this CPU package. * @nr_threads: Number of threads within this CPU. * @running: #true if CPU is currently running (lockless). @@ -404,6 +409,7 @@ struct CPUState { /* TODO Move common fields from CPUArchState here. */ int cpu_index; + int cluster_index; uint32_t halted; uint32_t can_do_io; int32_t exception_index; @@ -1109,5 +1115,6 @@ extern const struct VMStateDescription vmstate_cpu_common; #endif /* NEED_CPU_H */ #define UNASSIGNED_CPU_INDEX -1 +#define UNASSIGNED_CLUSTER_INDEX -1 #endif diff --git a/hw/cpu/cluster.c b/hw/cpu/cluster.c index 9d50a235d5c..d672f54a620 100644 --- a/hw/cpu/cluster.c +++ b/hw/cpu/cluster.c @@ -20,19 +20,52 @@ #include "qemu/osdep.h" #include "hw/cpu/cluster.h" +#include "qom/cpu.h" #include "qapi/error.h" #include "qemu/module.h" +#include "qemu/cutils.h" static Property cpu_cluster_properties[] = { DEFINE_PROP_UINT32("cluster-id", CPUClusterState, cluster_id, 0), DEFINE_PROP_END_OF_LIST() }; +static void cpu_cluster_realize(DeviceState *dev, Error **errp) +{ + /* Iterate through all our CPU children and set their cluster_index */ + CPUClusterState *cluster = CPU_CLUSTER(dev); + ObjectPropertyIterator iter; + ObjectProperty *prop; + Object *cluster_obj = OBJECT(dev); + + if (cluster->cluster_id >= MAX_CLUSTERS) { + error_setg(errp, "cluster-id must be less than %d", MAX_CLUSTERS); + return; + } + + object_property_iter_init(&iter, cluster_obj); + while ((prop = object_property_iter_next(&iter))) { + Object *cpu_obj; + CPUState *cpu; + + if (!strstart(prop->type, "child<", NULL)) { + continue; + } + cpu_obj = object_property_get_link(cluster_obj, prop->name, NULL); + cpu = (CPUState *)object_dynamic_cast(cpu_obj, TYPE_CPU); + if (!cpu) { + continue; + } + cpu->cluster_index = cluster->cluster_id; + } +} + static void cpu_cluster_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->props = cpu_cluster_properties; + dc->realize = cpu_cluster_realize; } static const TypeInfo cpu_cluster_type_info = { diff --git a/qom/cpu.c b/qom/cpu.c index 5442a7323be..f5579b1cd50 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -364,6 +364,7 @@ static void cpu_common_initfn(Object *obj) CPUClass *cc = CPU_GET_CLASS(obj); cpu->cpu_index = UNASSIGNED_CPU_INDEX; + cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX; cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs; /* *-user doesn't have configurable SMP topology */ /* the default value is changed by qemu_init_vcpu() for softmmu */ From patchwork Tue Jan 8 16:30:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154991 Delivered-To: patches@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp5070152jaa; Tue, 8 Jan 2019 08:30:16 -0800 (PST) X-Received: by 2002:a1c:ac42:: with SMTP id v63mr2201333wme.119.1546965015857; Tue, 08 Jan 2019 08:30:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546965015; cv=none; d=google.com; s=arc-20160816; b=TAhcp3NyoowhP3LcFj6tmkJVSRrrGuZpP1zqzZvsfbPD+/gWg74wlfTgXvElriq0YL LTKn1Z7RFLjSEm2EusTTUy5Oi4YggiA2KpjkbALvd07t4vyjbjmD0h5Yz1mYAFxivWLg MN1/LRKCEl0+eGnG6TD3gb3kDo6FYaQn7ikFwYeothpipn1MWKlMWc9u3n2VT2+kOJBb zdwmvrDMttv1xHe+QtxAJZWAqBUPMavkTUwOMF3I/URE4z4PtKiQgQELZDS6bzU2THOC Voo67NIxX0UUR/wUapCwkMEoKSDpENRD3UrD9+LQU3ujdkCkEWc7pGeTx0h9jOJPjbFt /BXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=46ldnkoBNzwTQapSHqF1F5MiDCIH8/mF+o2srm542zA=; b=T+hoSlcqCrsYCvjkuXlvy5NZw4HJDb11ygQzaBoi1mrwvZfHbSs9td4xAPHIi45HAh KJqD93vfkv71sIi/NxTQqQuIk7ZSylef/n8TmAxlFailk631pfCw42ylWYmXkOtZBEGQ Ly9/sRMFHhSTjVR+VH9S4p0yue4zyH3EngM171Cp1ii8B+zRQL9NR2Kt//qQ8qOsyVMm dE4dSXIl03jGo49YvXtqMO5S1WyIvLViLrzJSylXVFp3OJ771tKPxVxerERkK3V/ME5D ssMqG1v5nwXH/PEltkuV3U/ZbLBrOQ05HO1GmY8OClNkO0/Ee1j5G4S4uI9QC7t42CSC o4vw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WaPUYokY; spf=pass (google.com: domain of peter.maydell@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=peter.maydell@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id 140sor7444674wme.14.2019.01.08.08.30.15 for (Google Transport Security); Tue, 08 Jan 2019 08:30:15 -0800 (PST) Received-SPF: pass (google.com: domain of peter.maydell@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WaPUYokY; spf=pass (google.com: domain of peter.maydell@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=peter.maydell@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=46ldnkoBNzwTQapSHqF1F5MiDCIH8/mF+o2srm542zA=; b=WaPUYokY5ErXyR7LdmjSESE3txFpKVAfb+jQ2XV7N7W9M0t5rQM1VHbbGd/DxJFHvy c2KlgQw3cYVn9DyvHT7AywpuGKLR5PYDtJM94fqzpk0NjQkrjJJpr5qmU2htXgy+QrRF bkSrPYTJhcV5FTnceKH76MBklxcmTejTqEW/w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=46ldnkoBNzwTQapSHqF1F5MiDCIH8/mF+o2srm542zA=; b=lgJLVVPOxklSHovhaAKY4K1IxzvDR4OURIS4KJOuqovgDDm4DxGm63y3vueWiI9nOa Gj1iEm8S+x6PCRGfssZxZ5fJOnlieGM3jn0lkGDl8OfQGMmGxSW//FPpZX4oekOt8E7h 2G40iCfL6avKmXppnb9lzFKWE6sL4qKSunLtJXo600wM1ZKHdWItaCN7P+/APcfOmiBi lIWtl9iNXISIJXkNJC7M8cRio7tzM2b+nUFebro9xHS5QQ5KGFw3y0QVSb63f+Ki8Sgh cPT7mHaBLixCgLf+3hK6IhdCFhVdJGnY44TTSyiCnh98gDtqSoQHf68dMYopjJwczeQu Ag6A== X-Gm-Message-State: AJcUukdalmw9IDUiffDWCmU2yeCF1nLJQSSS9blY43SgKiItm/PEjhNp qNUrVnZbKr/XOsfhpVgFkJ8SoGZm X-Google-Smtp-Source: ALg8bN74tF166Sq83/2IFptmgmnhGHhKb5TkeuvcFr88Irmh4Gm1DF4/Z21hHUYjWUDU4S1tNkBB9A== X-Received: by 2002:a1c:1b8d:: with SMTP id b135mr2312163wmb.115.1546965015380; Tue, 08 Jan 2019 08:30:15 -0800 (PST) Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id x81sm11278839wmg.17.2019.01.08.08.30.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 08 Jan 2019 08:30:14 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Richard Henderson , Peter Crosthwaite , Paolo Bonzini , Alistair Francis , "Edgar E. Iglesias" , Eduardo Habkost , Marcel Apfelbaum , "Emilio G . Cota" Subject: [PATCH 3/4] accel/tcg: Add cluster number to TCG TB hash Date: Tue, 8 Jan 2019 16:30:07 +0000 Message-Id: <20190108163008.7006-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190108163008.7006-1-peter.maydell@linaro.org> References: <20190108163008.7006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Include the cluster number in the hash we use to look up TBs. This is important because a TB that is valid for one cluster at a given physical address and set of CPU flags is not necessarily valid for another: the two clusters may have different views of physical memory, or may have different CPU features (eg FPU present or absent). We put the cluster number in the high 8 bits of the TB cflags. This gives us up to 256 clusters, which should be enough for anybody. If we ever need more, or need more bits in cflags for other purposes, we could make tb_hash_func() take more data (and expand qemu_xxhash7() to qemu_xxhash8()). Signed-off-by: Peter Maydell --- include/exec/exec-all.h | 4 +++- accel/tcg/cpu-exec.c | 4 ++++ accel/tcg/translate-all.c | 3 +++ 3 files changed, 10 insertions(+), 1 deletion(-) -- 2.19.2 Reviewed-by: Luc Michel Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 815e5b1e838..aa7b81aaf01 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -351,9 +351,11 @@ struct TranslationBlock { #define CF_USE_ICOUNT 0x00020000 #define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock held */ #define CF_PARALLEL 0x00080000 /* Generate code for a parallel context */ +#define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */ +#define CF_CLUSTER_SHIFT 24 /* cflags' mask for hashing/comparison */ #define CF_HASH_MASK \ - (CF_COUNT_MASK | CF_LAST_IO | CF_USE_ICOUNT | CF_PARALLEL) + (CF_COUNT_MASK | CF_LAST_IO | CF_USE_ICOUNT | CF_PARALLEL | CF_CLUSTER_MASK) /* Per-vCPU dynamic tracing state used to generate this TB */ uint32_t trace_vcpu_dstate; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 870027d4359..e578a1a3aee 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -336,6 +336,10 @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, return NULL; } desc.phys_page1 = phys_pc & TARGET_PAGE_MASK; + + cf_mask &= ~CF_CLUSTER_MASK; + cf_mask |= cpu->cluster_index << CF_CLUSTER_SHIFT; + h = tb_hash_func(phys_pc, pc, flags, cf_mask, *cpu->trace_dstate); return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp); } diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 639f0b27287..ba27f5acc8c 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1692,6 +1692,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu, cflags |= CF_NOCACHE | 1; } + cflags &= ~CF_CLUSTER_MASK; + cflags |= cpu->cluster_index << CF_CLUSTER_SHIFT; + buffer_overflow: tb = tb_alloc(pc); if (unlikely(!tb)) { From patchwork Tue Jan 8 16:30:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 154992 Delivered-To: patches@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp5070170jaa; Tue, 8 Jan 2019 08:30:17 -0800 (PST) X-Received: by 2002:a5d:50c5:: with SMTP id f5mr1884385wrt.37.1546965017287; Tue, 08 Jan 2019 08:30:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546965017; cv=none; d=google.com; s=arc-20160816; b=By6FlmUct2Id41xqUY1PswEhBw//oEMmEsMfis7VZ2Fa11h/UhD0gXSUiwN7qhsJt+ 2IsphyjpSfeZC1a837pZLJ0R5SO4hv/M6Fca7lww07E9SvN5vtRfTE5kshJfzWLp71Pl UeSSTBFJEdirnKVO5BppQ0SPWmXkfQEGQPpi7wmLwIQtiP1ObCf7NVnoaihqEjh/Eh6j 0wRxPm1tzRDP2Q/UQSNRC2wlnbRJbz//OkJlOz1zEVo7tjTAH3TvuqHHi8+pMBDj0ioF 0zHSkzGXzMGjq2iWwa4d2WpKrdYXkemKYCgJSyLmwEh5SBuXy4TYKO8bFTNhtYieBwed ElBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=lHw25Aq6KmkJUqEwitBkXgdSRY6pkgGYnAbHYsqk6tg=; b=OIYuRPN1x8TzebK985TgdeRTma83xUvOH3Qgld5wuJSf825hX7EDgzUSRjY3YVhTAj gIEtyu39Fyqq30I74TuR/VPHqgKHIsWDTctghWqjdvda0NkltqiH9E1N1I4EeeFyAjGm VIDPaaSxq/CjkfAF7Wpjv0HZusi4uvRxOE652YMDE2CkiLTwKlB9sSMvRlPRtXDm5ISN 2NqC/mN0/D+FiSaLaVO7EjJ92u0XIc+r6FcYSXZGhPAy6V75ZoaDm3Z5STo+E06LW4um ktRBGHHz/6T6ZerdaaVCssNLn9JO28YCaX9pmMLrW4WU/zBl7eAFw0+jROMXBI81mXcR w2mw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PFC02pyT; spf=pass (google.com: domain of peter.maydell@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=peter.maydell@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id j10sor36799249wrx.15.2019.01.08.08.30.17 for (Google Transport Security); Tue, 08 Jan 2019 08:30:17 -0800 (PST) Received-SPF: pass (google.com: domain of peter.maydell@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PFC02pyT; spf=pass (google.com: domain of peter.maydell@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=peter.maydell@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lHw25Aq6KmkJUqEwitBkXgdSRY6pkgGYnAbHYsqk6tg=; b=PFC02pyTYUTf7RVgboMHb9D890vfTPFjCqcMDUTi7873obKgsYCxfGUgXSthXTt196 OtFBZ19j3LcARz0wiN6DK23UhPjZLNU60Zc3hpmlGejtigi1pm9xKQDQdHq+qovfwPgw b6kuvmHx39Agf/S49EDAMJ+gIXoTe7kAN/0TY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lHw25Aq6KmkJUqEwitBkXgdSRY6pkgGYnAbHYsqk6tg=; b=r+tPIGpRIiasSHS23j8cE0CHMYXyldhAm5nE9tJQGNWeJazgfL6teqAb2duiSOly2G bjVYSlnUQ/OeZ4Pd7JNtNgyqhgdvenLEYhEySCiZXAHqd+bdXR3NgM4iK422JtceAovK 812lTWqgMGe2/XA7qs3x9D5FvQ1G6VgvKJVL9y12AqPuAeGee/lenOBB/q+GLSXtwtKU Y27bS9BpJUOKGKJOXcbxjmbRU1UfaipGGpi8dU7UX6M5kc2yDeDtMwAcgbUwOzyalsSu YNlYjMDGUkj7qyeGFMd2u9v4v7CVe9ur/qHEPBbMEaUJaelSeoHipowIn7WFAn/7dCcE kRaQ== X-Gm-Message-State: AJcUukfSspBdp4iKeGod23ENFRTd/8qJfhMdiexVyUxuUfmWQ0DD7cpJ nOFef/g0iWvr+/Z7jvoViV3dx0ak X-Google-Smtp-Source: ALg8bN5ZIj1zsnqZt+8hHJKF99Se4N2TvoP0ilqbwTvpKPL6Anjr+Ck6457bk6lJLwIJhm0Q6aotSA== X-Received: by 2002:a5d:47d1:: with SMTP id l17mr1925630wrs.319.1546965016893; Tue, 08 Jan 2019 08:30:16 -0800 (PST) Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id x81sm11278839wmg.17.2019.01.08.08.30.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 08 Jan 2019 08:30:16 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Richard Henderson , Peter Crosthwaite , Paolo Bonzini , Alistair Francis , "Edgar E. Iglesias" , Eduardo Habkost , Marcel Apfelbaum , "Emilio G . Cota" Subject: [PATCH 4/4] gdbstub: Simplify gdb_get_cpu_pid() to use cpu->cluster_index Date: Tue, 8 Jan 2019 16:30:08 +0000 Message-Id: <20190108163008.7006-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190108163008.7006-1-peter.maydell@linaro.org> References: <20190108163008.7006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Now we're keeping the cluster index in the CPUState, we don't need to jump through hoops in gdb_get_cpu_pid() to find the associated cluster object. Signed-off-by: Peter Maydell --- gdbstub.c | 48 +++++------------------------------------------- 1 file changed, 5 insertions(+), 43 deletions(-) -- 2.19.2 Reviewed-by: Luc Michel diff --git a/gdbstub.c b/gdbstub.c index bfc7afb5096..5d6cbea9d35 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -644,50 +644,12 @@ static int memtox(char *buf, const char *mem, int len) static uint32_t gdb_get_cpu_pid(const GDBState *s, CPUState *cpu) { -#ifndef CONFIG_USER_ONLY - gchar *path, *name = NULL; - Object *obj; - CPUClusterState *cluster; - uint32_t ret; - - path = object_get_canonical_path(OBJECT(cpu)); - - if (path == NULL) { - /* Return the default process' PID */ - ret = s->processes[s->process_num - 1].pid; - goto out; - } - - name = object_get_canonical_path_component(OBJECT(cpu)); - assert(name != NULL); - - /* - * Retrieve the CPU parent path by removing the last '/' and the CPU name - * from the CPU canonical path. - */ - path[strlen(path) - strlen(name) - 1] = '\0'; - - obj = object_resolve_path_type(path, TYPE_CPU_CLUSTER, NULL); - - if (obj == NULL) { - /* Return the default process' PID */ - ret = s->processes[s->process_num - 1].pid; - goto out; - } - - cluster = CPU_CLUSTER(obj); - ret = cluster->cluster_id + 1; - -out: - g_free(name); - g_free(path); - - return ret; - -#else /* TODO: In user mode, we should use the task state PID */ - return s->processes[s->process_num - 1].pid; -#endif + if (cpu->cluster_index == UNASSIGNED_CLUSTER_INDEX) { + /* Return the default process' PID */ + return s->processes[s->process_num - 1].pid; + } + return cpu->cluster_index + 1; } static GDBProcess *gdb_get_process(const GDBState *s, uint32_t pid)