From patchwork Sat May 21 20:35:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 575251 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55F00C43217 for ; Sat, 21 May 2022 20:35:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345780AbiEUUfa (ORCPT ); Sat, 21 May 2022 16:35:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345748AbiEUUf1 (ORCPT ); Sat, 21 May 2022 16:35:27 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 45229393C9 for ; Sat, 21 May 2022 13:35:25 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id br17so7257462lfb.2 for ; Sat, 21 May 2022 13:35:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Yz1Yzt/Sg0lXAFTAnGbUnGwgR0Ly0/Jt+YYR3V8OSOE=; b=dlEZSv5s71VcVS2besnHXfHlsOo0tHOofPv+jkwhIH9OeB7dS4JSrUGMLi15UrdcUK sqvOfJVboVKjL549dgv7WuIwTpIGUA/zFA90+cZaZf5T8ID27jLZXCMwKy8vgB4FXZ0u 0MfdhHf/FV2l+9uNU6zweiFh/+VWPV/B7xPRQCdsJYwB1dYmdMzda6p0OC6qd9WjjTkP T15clFsohZ8yg/tBxpoQBfrcH+lWm/CVPe3PSa8Gcwg6ccUVdC0YPuDGkRWRQ+S4EbNJ T3htm6RI4Gmihp5iX/naGOzyYWnBMJzpwR/fQ8u2hUnn4VPUKPHtOCeHxCaXBqMlEWpK yinw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Yz1Yzt/Sg0lXAFTAnGbUnGwgR0Ly0/Jt+YYR3V8OSOE=; b=NfyPaPNBaEXL3KhR1Oj0pkgIAazzEzJZfl1Z5XNlY/wN2l1dLgYKKSCfleHzBq2T/v f8edU8LxVYr5dz7pDnJtkO2q8o2t1n629OyOh2NfHynI+EDlA0dUb06texrseUQGOGzz Yut5l9kFCWWE4A36ZM2TG2FvmSI7WTSuFW2vSxBaTs9EEq6jSfyDpnke18QD/KmXWHFG JC/nVmw25sjfHa2HJn6awFxcJxJPLhjnGJWlPS5MpOWC51mvx3zvzBfXNaQVK4Y3EKvb Bv1RbfQtlwd0UtM87Iko7k3FcYhOGdB5T6ghIwFu3EcqJjUsRcClXLFPzk3G04CF/zdA V9BQ== X-Gm-Message-State: AOAM531u9YzMNH5G70mXPL2BPs00VRegH3SdD11os3nmqxISXqqVhrxJ CNOg8ihr1yHUc/nNQd52gRlP5CRRhuKRxQ== X-Google-Smtp-Source: ABdhPJxjgkTeh0iVJd87GEvUXsIksDMH+1Y+WY+35yeeSQf4hV7oWvbSUoexUjdrir2ho9FPOdeuGQ== X-Received: by 2002:a05:6512:b8d:b0:477:96e9:b959 with SMTP id b13-20020a0565120b8d00b0047796e9b959mr11739228lfv.563.1653165323405; Sat, 21 May 2022 13:35:23 -0700 (PDT) Received: from eriador.lan ([2001:470:dd84:abc0::8a5]) by smtp.gmail.com with ESMTPSA id q18-20020a056512211200b00477930c48dasm1179729lfr.184.2022.05.21.13.35.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 May 2022 13:35:22 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Marijn Suijten Subject: [PATCH v2 1/4] arm64: dts: qcom: sdm660: move device nodes to sdm636 Date: Sat, 21 May 2022 23:35:17 +0300 Message-Id: <20220521203520.1513565-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220521203520.1513565-1-dmitry.baryshkov@linaro.org> References: <20220521203520.1513565-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The sdm636 is a lighter version of sdm660. It lacks Turing DSP (cdsp) and has slightly different CPU speed and Adreno version. Reflect this by moving all common device nodes from sdm660.dtsi to sdm636.dtsi and including the later file from the former one. Currently this is implemented in the opposite direction, sdm636 includes sdm660, thus adding cdsp support would require adding delete-node statements to sdm636.dtsi. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sdm636.dtsi | 253 +++++++++++++++++++++++++-- arch/arm64/boot/dts/qcom/sdm660.dtsi | 250 +------------------------- 2 files changed, 250 insertions(+), 253 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm636.dtsi b/arch/arm64/boot/dts/qcom/sdm636.dtsi index ae15d81fa3f9..0cf72f0def38 100644 --- a/arch/arm64/boot/dts/qcom/sdm636.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm636.dtsi @@ -5,19 +5,248 @@ * Copyright (c) 2020, Martin Botka */ -#include "sdm660.dtsi" - -/* - * According to the downstream DTS, - * 636 is basically a 660 except for - * different CPU frequencies, Adreno - * 509 instead of 512 and lack of - * turing IP. These differences will - * be addressed when the aforementioned - * peripherals will be enabled upstream. - */ +#include "sdm630.dtsi" &adreno_gpu { compatible = "qcom,adreno-509.0", "qcom,adreno"; - /* Adreno 509 shares the frequency table with 512 */ + operating-points-v2 = <&gpu_sdm660_opp_table>; + + gpu_sdm660_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* + * 775MHz is only available on the highest speed bin + * Though it cannot be used for now due to interconnect + * framework not supporting multiple frequencies + * at the same opp-level + + opp-750000000 { + opp-hz = /bits/ 64 <750000000>; + opp-level = ; + opp-peak-kBps = <5412000>; + opp-supported-hw = <0xCHECKME>; + }; + + * These OPPs are correct, but we are lacking support for the + * GPU regulator. Hence, disable them for now to prevent the + * platform from hanging on high graphics loads. + + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-level = ; + opp-peak-kBps = <5184000>; + opp-supported-hw = <0xFF>; + }; + + opp-647000000 { + opp-hz = /bits/ 64 <647000000>; + opp-level = ; + opp-peak-kBps = <4068000>; + opp-supported-hw = <0xFF>; + }; + + opp-588000000 { + opp-hz = /bits/ 64 <588000000>; + opp-level = ; + opp-peak-kBps = <3072000>; + opp-supported-hw = <0xFF>; + }; + + opp-465000000 { + opp-hz = /bits/ 64 <465000000>; + opp-level = ; + opp-peak-kBps = <2724000>; + opp-supported-hw = <0xFF>; + }; + + opp-370000000 { + opp-hz = /bits/ 64 <370000000>; + opp-level = ; + opp-peak-kBps = <2188000>; + opp-supported-hw = <0xFF>; + }; + */ + + opp-266000000 { + opp-hz = /bits/ 64 <266000000>; + opp-level = ; + opp-peak-kBps = <1648000>; + opp-supported-hw = <0xFF>; + }; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-level = ; + opp-peak-kBps = <1200000>; + opp-supported-hw = <0xFF>; + }; + }; +}; + +&CPU0 { + compatible = "qcom,kryo260"; + capacity-dmips-mhz = <1024>; + /delete-property/ operating-points-v2; +}; + +&CPU1 { + compatible = "qcom,kryo260"; + capacity-dmips-mhz = <1024>; + /delete-property/ operating-points-v2; +}; + +&CPU2 { + compatible = "qcom,kryo260"; + capacity-dmips-mhz = <1024>; + /delete-property/ operating-points-v2; +}; + +&CPU3 { + compatible = "qcom,kryo260"; + capacity-dmips-mhz = <1024>; + /delete-property/ operating-points-v2; +}; + +&CPU4 { + compatible = "qcom,kryo260"; + capacity-dmips-mhz = <640>; + /delete-property/ operating-points-v2; +}; + +&CPU5 { + compatible = "qcom,kryo260"; + capacity-dmips-mhz = <640>; + /delete-property/ operating-points-v2; +}; + +&CPU6 { + compatible = "qcom,kryo260"; + capacity-dmips-mhz = <640>; + /delete-property/ operating-points-v2; +}; + +&CPU7 { + compatible = "qcom,kryo260"; + capacity-dmips-mhz = <640>; + /delete-property/ operating-points-v2; +}; + +&gcc { + compatible = "qcom,gcc-sdm660"; +}; + +&gpucc { + compatible = "qcom,gpucc-sdm660"; +}; + +&mdp { + ports { + port@1 { + reg = <1>; + mdp5_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; +}; + +&mdss { + dsi1: dsi@c996000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0x0c996000 0x400>; + reg-names = "dsi_ctrl"; + + /* DSI1 shares the OPP table with DSI0 */ + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmpd SDM660_VDDCX>; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + assigned-clocks = <&mmcc BYTE1_CLK_SRC>, + <&mmcc PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, + <&dsi1_phy 1>; + + clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_BYTE1_CLK>, + <&mmcc MDSS_BYTE1_INTF_CLK>, + <&mmcc MNOC_AHB_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MISC_AHB_CLK>, + <&mmcc MDSS_PCLK1_CLK>, + <&mmcc MDSS_ESC1_CLK>; + clock-names = "mdp_core", + "byte", + "byte_intf", + "mnoc", + "iface", + "bus", + "core_mmss", + "pixel", + "core"; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&mdp5_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: dsi-phy@c996400 { + compatible = "qcom,dsi-phy-14nm-660"; + reg = <0x0c996400 0x100>, + <0x0c996500 0x300>, + <0x0c996800 0x188>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + status = "disabled"; + }; +}; + +&mmcc { + compatible = "qcom,mmcc-sdm660"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <&gcc GCC_MMSS_GPLL0_CLK>, + <&gcc GCC_MMSS_GPLL0_DIV_CLK>, + <&dsi0_phy 1>, + <&dsi0_phy 0>, + <&dsi1_phy 1>, + <&dsi1_phy 0>, + <0>, + <0>; +}; + +&tlmm { + compatible = "qcom,sdm660-pinctrl"; +}; + +&tsens { + #qcom,sensors = <14>; }; diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi index c92f1cef3d3c..f51f5b27819f 100644 --- a/arch/arm64/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi @@ -7,248 +7,16 @@ * Copyright (c) 2020, Martin Botka */ -#include "sdm630.dtsi" +#include "sdm636.dtsi" + +/* + * According to the downstream DTS, 660 is basically a 660 except for different + * CPU frequencies, Adreno 512 instead of 509 and presens of turing IP. These + * differences will be addressed when the aforementioned peripherals will be + * enabled upstream. + */ &adreno_gpu { compatible = "qcom,adreno-512.0", "qcom,adreno"; - operating-points-v2 = <&gpu_sdm660_opp_table>; - - gpu_sdm660_opp_table: opp-table { - compatible = "operating-points-v2"; - - /* - * 775MHz is only available on the highest speed bin - * Though it cannot be used for now due to interconnect - * framework not supporting multiple frequencies - * at the same opp-level - - opp-750000000 { - opp-hz = /bits/ 64 <750000000>; - opp-level = ; - opp-peak-kBps = <5412000>; - opp-supported-hw = <0xCHECKME>; - }; - - * These OPPs are correct, but we are lacking support for the - * GPU regulator. Hence, disable them for now to prevent the - * platform from hanging on high graphics loads. - - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-level = ; - opp-peak-kBps = <5184000>; - opp-supported-hw = <0xFF>; - }; - - opp-647000000 { - opp-hz = /bits/ 64 <647000000>; - opp-level = ; - opp-peak-kBps = <4068000>; - opp-supported-hw = <0xFF>; - }; - - opp-588000000 { - opp-hz = /bits/ 64 <588000000>; - opp-level = ; - opp-peak-kBps = <3072000>; - opp-supported-hw = <0xFF>; - }; - - opp-465000000 { - opp-hz = /bits/ 64 <465000000>; - opp-level = ; - opp-peak-kBps = <2724000>; - opp-supported-hw = <0xFF>; - }; - - opp-370000000 { - opp-hz = /bits/ 64 <370000000>; - opp-level = ; - opp-peak-kBps = <2188000>; - opp-supported-hw = <0xFF>; - }; - */ - - opp-266000000 { - opp-hz = /bits/ 64 <266000000>; - opp-level = ; - opp-peak-kBps = <1648000>; - opp-supported-hw = <0xFF>; - }; - - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-level = ; - opp-peak-kBps = <1200000>; - opp-supported-hw = <0xFF>; - }; - }; -}; - -&CPU0 { - compatible = "qcom,kryo260"; - capacity-dmips-mhz = <1024>; - /delete-property/ operating-points-v2; -}; - -&CPU1 { - compatible = "qcom,kryo260"; - capacity-dmips-mhz = <1024>; - /delete-property/ operating-points-v2; -}; - -&CPU2 { - compatible = "qcom,kryo260"; - capacity-dmips-mhz = <1024>; - /delete-property/ operating-points-v2; -}; - -&CPU3 { - compatible = "qcom,kryo260"; - capacity-dmips-mhz = <1024>; - /delete-property/ operating-points-v2; -}; - -&CPU4 { - compatible = "qcom,kryo260"; - capacity-dmips-mhz = <640>; - /delete-property/ operating-points-v2; -}; - -&CPU5 { - compatible = "qcom,kryo260"; - capacity-dmips-mhz = <640>; - /delete-property/ operating-points-v2; -}; - -&CPU6 { - compatible = "qcom,kryo260"; - capacity-dmips-mhz = <640>; - /delete-property/ operating-points-v2; -}; - -&CPU7 { - compatible = "qcom,kryo260"; - capacity-dmips-mhz = <640>; - /delete-property/ operating-points-v2; -}; - -&gcc { - compatible = "qcom,gcc-sdm660"; -}; - -&gpucc { - compatible = "qcom,gpucc-sdm660"; -}; - -&mdp { - ports { - port@1 { - reg = <1>; - mdp5_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; - }; - }; - }; -}; - -&mdss { - dsi1: dsi@c996000 { - compatible = "qcom,mdss-dsi-ctrl"; - reg = <0x0c996000 0x400>; - reg-names = "dsi_ctrl"; - - /* DSI1 shares the OPP table with DSI0 */ - operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmpd SDM660_VDDCX>; - - interrupt-parent = <&mdss>; - interrupts = <5>; - - assigned-clocks = <&mmcc BYTE1_CLK_SRC>, - <&mmcc PCLK1_CLK_SRC>; - assigned-clock-parents = <&dsi1_phy 0>, - <&dsi1_phy 1>; - - clocks = <&mmcc MDSS_MDP_CLK>, - <&mmcc MDSS_BYTE1_CLK>, - <&mmcc MDSS_BYTE1_INTF_CLK>, - <&mmcc MNOC_AHB_CLK>, - <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_AXI_CLK>, - <&mmcc MISC_AHB_CLK>, - <&mmcc MDSS_PCLK1_CLK>, - <&mmcc MDSS_ESC1_CLK>; - clock-names = "mdp_core", - "byte", - "byte_intf", - "mnoc", - "iface", - "bus", - "core_mmss", - "pixel", - "core"; - - phys = <&dsi1_phy>; - phy-names = "dsi"; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi1_in: endpoint { - remote-endpoint = <&mdp5_intf2_out>; - }; - }; - - port@1 { - reg = <1>; - dsi1_out: endpoint { - }; - }; - }; - }; - - dsi1_phy: dsi-phy@c996400 { - compatible = "qcom,dsi-phy-14nm-660"; - reg = <0x0c996400 0x100>, - <0x0c996500 0x300>, - <0x0c996800 0x188>; - reg-names = "dsi_phy", - "dsi_phy_lane", - "dsi_pll"; - - #clock-cells = <1>; - #phy-cells = <0>; - - clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; - clock-names = "iface", "ref"; - status = "disabled"; - }; -}; - -&mmcc { - compatible = "qcom,mmcc-sdm660"; - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, - <&sleep_clk>, - <&gcc GCC_MMSS_GPLL0_CLK>, - <&gcc GCC_MMSS_GPLL0_DIV_CLK>, - <&dsi0_phy 1>, - <&dsi0_phy 0>, - <&dsi1_phy 1>, - <&dsi1_phy 0>, - <0>, - <0>; -}; - -&tlmm { - compatible = "qcom,sdm660-pinctrl"; -}; - -&tsens { - #qcom,sensors = <14>; + /* Adreno 512 shares the frequency table with 509 */ }; From patchwork Sat May 21 20:35:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 574970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2FC4C433EF for ; Sat, 21 May 2022 20:35:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345810AbiEUUf3 (ORCPT ); Sat, 21 May 2022 16:35:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345750AbiEUUf1 (ORCPT ); Sat, 21 May 2022 16:35:27 -0400 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ABB30393CE for ; Sat, 21 May 2022 13:35:26 -0700 (PDT) Received: by mail-lf1-x12b.google.com with SMTP id l13so12893338lfp.11 for ; Sat, 21 May 2022 13:35:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xU1pY7ZmHzq1qWB+fNbq08vc5F06jzd4+OCKJVFnSMg=; b=PUqGn2M/XUSc8dj832XHXodX2asafqhCmEPRhoaWB/Mtl0lP722i12dydMjkSblNsJ WeoO2rpnfk959g0/uDsbO7VEeb1fRZ4g7lj3UT8vIj80rSGE3sRkP5SIzg1TwdRA4bQP 4lk6vD65t4Myg/xfyz2zRZe4Q8MW+XV8FpUf8KuKueecxH+VUl+fZILZh+tJmKaMbh2g lMtFHPW+YDty+2UN7IpmOtrbSUmhsovOVwhRvqHy4HqkhBolG9g7J5V0HNOWiUoxJqg4 zeJjVjOGvSXfGyrxA3V68Sya//d9PlL4f8bDNUmRRVLa12Vcqh8QwIA1zazoD7sRqkQs 5nXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xU1pY7ZmHzq1qWB+fNbq08vc5F06jzd4+OCKJVFnSMg=; b=AbwgQ3zHKZSvCK9bMEU1coArXDrZTihKXw2VcUsUzFbKALXF4eK80pt1RdjvpqCclo PAsu0TkidhzZbqNm70z5CO9/8G8zruRvM2rWj+XCXA7pDKLpYrDCNbdddnhQzRsCadPD DysjM0hf33cJmUip4iZ2mo9yyHzWzoZGyP0PSfMA+10ZzTYmjkgzVrxGZTOT5VMNAWuP pUTsng1HrTE5uAWBhIjO8t1wIOzl9LGWUTOgP97e7vnZsnKJ3SshrQNs2wbPX+DQzkXm RGzgnuA+ZOrPs6x9XcrI6V5T7UhhhOgJ/D+FODRibWL4WV83uvSs8jbGqdk3g1jqSkil othA== X-Gm-Message-State: AOAM531TGhqPWblzWhcMp5oISF2BDn/oD6ei00NkFLmxS02ZEd63PBCU S+aWrw0vzuo9H6KNbFPoEYELTQ== X-Google-Smtp-Source: ABdhPJwB0tI2NwiWmPCLCvUQQhXiaVp8RrpMpOO9wEKt0phUVGGKZhUdWjibOURZpk5njS72Gy59mw== X-Received: by 2002:a05:6512:752:b0:474:40ca:b0b with SMTP id c18-20020a056512075200b0047440ca0b0bmr11462140lfs.633.1653165324927; Sat, 21 May 2022 13:35:24 -0700 (PDT) Received: from eriador.lan ([2001:470:dd84:abc0::8a5]) by smtp.gmail.com with ESMTPSA id q18-20020a056512211200b00477930c48dasm1179729lfr.184.2022.05.21.13.35.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 May 2022 13:35:24 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Marijn Suijten Subject: [PATCH v2 2/4] arm64: dts: qcom: sdm660: add device node for the compute PAS Date: Sat, 21 May 2022 23:35:18 +0300 Message-Id: <20220521203520.1513565-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220521203520.1513565-1-dmitry.baryshkov@linaro.org> References: <20220521203520.1513565-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add device tree node describing CDSP device found on the SDM660 (but not on SDM630) platform. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sdm660.dtsi | 68 ++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi index f51f5b27819f..1869eeaff066 100644 --- a/arch/arm64/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi @@ -16,6 +16,74 @@ * enabled upstream. */ +/ { + reserved-memory { + /delete-node/ tzbuffer@94a00000; + + cdsp_region: cdsp@94a00000 { + reg = <0x0 0x94a00000 0x0 0x600000>; + no-map; + }; + + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts = ; + mboxes = <&apcs_glb 30>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc { + cdsp_pil: remoteproc@1a300000 { + compatible = "qcom,sdm660-cdsp-pas"; + reg = <0x1a300000 0x4040>; + + interrupts-extended = + <&intc GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + memory-region = <&cdsp_region>; + power-domains = <&rpmpd SDM660_VDDCX>; + power-domain-names = "cx"; + + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts = ; + + label = "turing"; + mboxes = <&apcs_glb 29>; + qcom,remote-pid = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + &adreno_gpu { compatible = "qcom,adreno-512.0", "qcom,adreno"; /* Adreno 512 shares the frequency table with 509 */ From patchwork Sat May 21 20:35:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 574969 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B7A4C433FE for ; Sat, 21 May 2022 20:35:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345748AbiEUUfb (ORCPT ); Sat, 21 May 2022 16:35:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345557AbiEUUf3 (ORCPT ); Sat, 21 May 2022 16:35:29 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2278A393C4 for ; Sat, 21 May 2022 13:35:28 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id t25so19564753lfg.7 for ; Sat, 21 May 2022 13:35:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=C9xhV4604cnunsv0ioP47Wr0e6BQa6QarxevuPKw7QI=; b=bh/RvFpmIjS7eRGUbitInRvzx5AOWhesctSMK/+KlRq5EtZL9kx3+w+7lrNTOHevll LXqeqyRi24q5RXXkY/oRM9XuKw/vepvdAZ4zPCQv/N3aF1Mmp0vDNQt2qULfEZsxqbQ5 Yf+S1XHY03sBtdzpZ/4Y+w3yd6WD1r7UPdl3SNZuA4L9ICmdsPF+j+LClcQmNJNrWeYZ 6ECBoEFla8kmkBfrZgKMIo0rqV5uKyyA6dngWhqXPgf9H4YaMC84tsNrG+9m9BqWnFKW Bbxr/8I6A4PiyxmMhgXlu95brdmLuFTIxBONWB9Vz5vbA2ZGI9MZUvhpI2Iw0OQp1Luj ya6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=C9xhV4604cnunsv0ioP47Wr0e6BQa6QarxevuPKw7QI=; b=kZj+CiJXVBZhrrtzQnhk14VlDdgeEhgIESf6P7RVcn0m7YqwNN1drh8p5Rhb4yJh0k 0GU8A0/e4xZESFRQI69baqSXqGPurUKxW9YR732+ngrn7nwLSl7sAX0osF89mGEkfVPv AH+iQN8BTJBF/iNZPIwdlYTZewlPCxewpDC67j/dx2YHpnQpAONZXv8UoRRrsaed0Rfo oSLprPzHEwsfJVxREUMeIGydlptGQXENOB7ZLyVRgvLZZCsLPVYmfU8obP/7EaOgS8Rk JeqUH7n6D5n76TsyyI0Ffk5fpFIznxBP0VRqKrKBtBdBOVFeRju0KkHxs73QYdMJEZE6 iJ8Q== X-Gm-Message-State: AOAM530Jo7JnDdY3TwJajj3XlZm/5Mqr6PwZHk6UMn7tBVM3CPeakR0j EPYPgT2WWaKHx6XvubHdd4YfYA== X-Google-Smtp-Source: ABdhPJzT3hNdKmvoNExx+ACfLlWREVnaAuCmUg2q2LiymcqEmrodQ+ehiRP73kKY8Gf9bsR8R/+U8g== X-Received: by 2002:a05:6512:c1a:b0:478:595c:e2fe with SMTP id z26-20020a0565120c1a00b00478595ce2femr5120276lfu.45.1653165326467; Sat, 21 May 2022 13:35:26 -0700 (PDT) Received: from eriador.lan ([2001:470:dd84:abc0::8a5]) by smtp.gmail.com with ESMTPSA id q18-20020a056512211200b00477930c48dasm1179729lfr.184.2022.05.21.13.35.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 May 2022 13:35:25 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Marijn Suijten Subject: [PATCH v2 3/4] arm64: dts: qcom: sdm630: add device node for the modem PAS Date: Sat, 21 May 2022 23:35:19 +0300 Message-Id: <20220521203520.1513565-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220521203520.1513565-1-dmitry.baryshkov@linaro.org> References: <20220521203520.1513565-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add device tree node describing modem device found on the SDM630/SDM660 devices. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 59 ++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 55de345895e6..25b0067a93af 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1006,6 +1006,65 @@ data { }; }; + mss_pil: remoteproc@4080000 { + compatible = "qcom,sdm660-mss-pil"; + reg = <0x04080000 0x408>, <0x04180000 0x48>; + reg-names = "qdsp6", "rmb"; + + interrupts-extended = + <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack", + "shutdown-ack"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&gcc GCC_MSS_GPLL0_DIV_CLK>, + <&gcc GCC_MSS_SNOC_AXI_CLK>, + <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "iface", "bus", "mem", "gpll0_mss", + "snoc_axi", "mnoc_axi", "xo", "qdss"; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + resets = <&gcc GCC_MSS_RESTART>; + reset-names = "mss_restart"; + + qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; + + power-domains = <&rpmpd SDM660_VDDCX>, + <&rpmpd SDM660_VDDMX>; + power-domain-names = "cx", "mx"; + + status = "disabled"; + + mba { + memory-region = <&mba_region>; + }; + + mpss { + memory-region = <&mpss_region>; + }; + + glink-edge { + interrupts = ; + label = "modem"; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 15>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + adreno_gpu: gpu@5000000 { compatible = "qcom,adreno-508.0", "qcom,adreno"; From patchwork Sat May 21 20:35:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 575250 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F72BC433EF for ; Sat, 21 May 2022 20:35:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345894AbiEUUfb (ORCPT ); Sat, 21 May 2022 16:35:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345750AbiEUUf3 (ORCPT ); Sat, 21 May 2022 16:35:29 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2EFE239687 for ; Sat, 21 May 2022 13:35:28 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id c19so6471674lfv.5 for ; Sat, 21 May 2022 13:35:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NikKax1TY449HcRi8lZ9MlsO8yEVEfcjkxzb8ZcULgo=; b=O/RRBcYY/bPHmEN+np/9vlrRuefSdq2JQqhkUk04++cqHAuzxWyCU5iY4DbkckED6G XkVjqvtw/1QPNLnxZl+YcHPqTFhRsod5zRq1uUcxXE8OZJ9KaSycnJf/6Dn6IZ8wK//I 3b/WmoOhZjxrotRwcSXUdnV6uBeEQSK+EVDjNeB7K1cJPWCudK7Izd3k/f+SMVmHbE14 E5sQLsE7esQG5exxY0iiXHayIRl/oM358apHBraf5ZxUgsdWAyCH90mLfJbUJ8A6LHPY vi6wIpcCiz+wsEWmxnWRRp/AdODvHjZ94RhOc0r42GsUXbFzMDtJlGYeq8n9aXJu+9sm dXYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NikKax1TY449HcRi8lZ9MlsO8yEVEfcjkxzb8ZcULgo=; b=wLED3WzYEbFGCzg9xJfDvvEvBFz3Muk7w4peQMiY5qcGsIOMn1ASisZziypYhfxr/Z c2+3EeIhsUqkT4WywNcdrQMnzV3W0PYC2REC3B62sdL5dQmKvGJJRtJVlgYxvEGzhfJs 1uwbSGACOD4mYTKagSbDoDV398qKDNxTI39NSKSaFnFD3YPffeiZNFNGTBGV2dVmDtXI V3G40TziTmKxDXRUT7A0T3bPY2hR2au9QF5lu8/Sj15XM6BpFnWi9cp/pwehusJq/EA4 OShFtysHxBAVcYoaEeILeRrWMdnyWImfI8uosh3Ahmm9Sxxlo+0DWGZhJoBQg64VgaGJ iTrw== X-Gm-Message-State: AOAM530+ZEe8JvnOjFU8bdTKk68v9lYF5Us9XFm2CvbzcAWmVhsIquDH 0Tak36SDxxUBwDYhrU+E3vrWBbJolsyLkg== X-Google-Smtp-Source: ABdhPJxD+UZZs7+foO+tu1pmUUY7hWuW8wVO+fP8W9lEEH1F6hxpje5cJ3XzOe822Y3X0W528xowOg== X-Received: by 2002:a05:6512:1311:b0:474:315e:8aaf with SMTP id x17-20020a056512131100b00474315e8aafmr11350115lfu.421.1653165327776; Sat, 21 May 2022 13:35:27 -0700 (PDT) Received: from eriador.lan ([2001:470:dd84:abc0::8a5]) by smtp.gmail.com with ESMTPSA id q18-20020a056512211200b00477930c48dasm1179729lfr.184.2022.05.21.13.35.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 May 2022 13:35:27 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Marijn Suijten Subject: [PATCH v2 4/4] arm64: dts: qcom: sda660-inforce-ifc6560: enable cdsp and modem Date: Sat, 21 May 2022 23:35:20 +0300 Message-Id: <20220521203520.1513565-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220521203520.1513565-1-dmitry.baryshkov@linaro.org> References: <20220521203520.1513565-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable CDSP and modem devices on the Inforce IFC6560 board. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts index 28050bc5f081..0bf9c86aaefe 100644 --- a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts +++ b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts @@ -183,6 +183,11 @@ bluetooth { }; }; +&cdsp_pil { + status = "okay"; + firmware-name = "qcom/ifc6560/cdsp.mbn"; +}; + &dsi0 { status = "okay"; vdda-supply = <&vreg_l1a_1p225>; @@ -206,6 +211,11 @@ &mmss_smmu { status = "okay"; }; +&mss_pil { + status = "okay"; + firmware-name = "qcom/ifc6560/mba.mbn", "qcom/ifc6560/modem.mbn"; +}; + &pon_pwrkey { status = "okay"; };