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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.31.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:31:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:30:59 +1000 Message-Id: <20190108223129.5570-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v3 01/31] target/arm: Add state for the ARMv8.3-PAuth extension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add storage space for the 5 encryption keys. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson ---- v2: Remove pointless double migration. Use a struct to make it clear which half is which. --- target/arm/cpu.h | 30 +++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6f606eb97b..8b891bbc30 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -201,11 +201,16 @@ typedef struct ARMVectorReg { uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); } ARMVectorReg; -/* In AArch32 mode, predicate registers do not exist at all. */ #ifdef TARGET_AARCH64 +/* In AArch32 mode, predicate registers do not exist at all. */ typedef struct ARMPredicateReg { uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16); } ARMPredicateReg; + +/* In AArch32 mode, PAC keys do not exist at all. */ +typedef struct ARMPACKey { + uint64_t lo, hi; +} ARMPACKey; #endif @@ -605,6 +610,14 @@ typedef struct CPUARMState { uint32_t cregs[16]; } iwmmxt; +#ifdef TARGET_AARCH64 + ARMPACKey apia_key; + ARMPACKey apib_key; + ARMPACKey apda_key; + ARMPACKey apdb_key; + ARMPACKey apga_key; +#endif + #if defined(CONFIG_USER_ONLY) /* For usermode syscall translation. */ int eabi; @@ -3264,6 +3277,21 @@ static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; } +static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) +{ + /* + * Note that while QEMU will only implement the architected algorithm + * QARMA, and thus APA+GPA, the host cpu for kvm may use implementation + * defined algorithms, and thus API+GPI, and this predicate controls + * migration of the 128-bit keys. + */ + return (id->id_aa64isar1 & + (FIELD_DP64(0, ID_AA64ISAR1, APA, -1) | + FIELD_DP64(0, ID_AA64ISAR1, API, -1) | + FIELD_DP64(0, ID_AA64ISAR1, GPA, -1) | + FIELD_DP64(0, ID_AA64ISAR1, GPI, -1))) != 0; +} + static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically wrt FP16. */ From patchwork Tue Jan 8 22:31:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155013 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp35270jaa; Tue, 8 Jan 2019 14:37:45 -0800 (PST) X-Google-Smtp-Source: ALg8bN7RkOuhckKh1ofeym1MnxRRzsSMhHwYHyRQKSV4rdKyg4lnnLMV/0/07+QvlZDLjojXWInQ X-Received: by 2002:a5d:6b81:: with SMTP id n1mr3056881wrx.149.1546987065667; Tue, 08 Jan 2019 14:37:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546987065; cv=none; d=google.com; s=arc-20160816; b=k8YoVjZ2qgxRHQIAPwbRDqe+5QriQH4QUK/eYOO6+qpf97g/5u41h5/WEysOVVbE+g LyngOChigsy1fUVSsh9ZwmRc0Aa+2HJkuSvmjhidaKtdP6VJX2xDeGC0JWM3NTbkxEOu kh2wncoclhd6baWaR4RBBV8YXPaXoxHMkeMSbBGhq1NTQ8vqoyVUZAkCuzMPuSnkEIKn DN2j55cMCelz8Riyw2rVU7YsQOVNAE8116FRtao2WfHX57E/DhQ1AmGPeqQ9HOdEG/+G r0JqenprPa4ErgCXPHPGS9qje1vob3uRPkW7OcLxf5dp8SPwi2u7YRWeTUTLyF2d927k bQag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=hH55bLkql39OTMji4tcf4IYVIJI0UJzo6VknZottr4Q=; b=u8tfGF3TMVKEo/XuEUYtjUQexAvJew96/S9jUAkw6nI8n7HyBweiONfSl7hTg3J0vs gi4JCa19Ifyaa172Efpl9yG7U98DN565Hdn5pxMqD0GjYAzwjOVGLfUac77S5Cde9kVo BZqrMpCOsArY5xp61zWl/l11Go8Z6X9emtMGYUMoKtq2oHwWRCJa/r5dnZ2Xp1BeiA9E HKRtBH4JToF0yQEb2LdVzINXFwPfP2hq8DviiA6esAou/0qRf9tmVt6sbZpkL/+wkRom 5sF+RMi6BvzE3TV8LQroclP013ThU4q+ryUpWs1xy/2R0ZLvsXAdpsgKoUXN8MTzAjLZ fn2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NdVSPtsf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.31.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:31:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:00 +1000 Message-Id: <20190108223129.5570-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3 02/31] target/arm: Add SCTLR bits through ARMv8.5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Post v8.4 bits taken from SysReg_v85_xml-00bet8. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson ---- v2: Review fixups from Peter. --- target/arm/cpu.h | 45 +++++++++++++++++++++++++++++++++------------ 1 file changed, 33 insertions(+), 12 deletions(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8b891bbc30..843d5936ea 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -991,12 +991,15 @@ void pmccntr_sync(CPUARMState *env); #define SCTLR_A (1U << 1) #define SCTLR_C (1U << 2) #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ -#define SCTLR_SA (1U << 3) +#define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ +#define SCTLR_SA (1U << 3) /* AArch64 only */ #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ +#define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ +#define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ #define SCTLR_ITD (1U << 7) /* v8 onward */ #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ @@ -1004,35 +1007,53 @@ void pmccntr_sync(CPUARMState *env); #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ #define SCTLR_F (1U << 10) /* up to v6 */ -#define SCTLR_SW (1U << 10) /* v7 onward */ -#define SCTLR_Z (1U << 11) +#define SCTLR_SW (1U << 10) /* v7, RES0 in v8 */ +#define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ +#define SCTLR_EOS (1U << 11) /* v8.5-ExS */ #define SCTLR_I (1U << 12) -#define SCTLR_V (1U << 13) +#define SCTLR_V (1U << 13) /* AArch32 only */ +#define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ #define SCTLR_RR (1U << 14) /* up to v7 */ #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ #define SCTLR_nTWI (1U << 16) /* v8 onward */ -#define SCTLR_HA (1U << 17) +#define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ #define SCTLR_BR (1U << 17) /* PMSA only */ #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ #define SCTLR_nTWE (1U << 18) /* v8 onward */ #define SCTLR_WXN (1U << 19) #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ -#define SCTLR_UWXN (1U << 20) /* v7 onward */ -#define SCTLR_FI (1U << 21) -#define SCTLR_U (1U << 22) +#define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ +#define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ +#define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ +#define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ +#define SCTLR_EIS (1U << 22) /* v8.5-ExS */ #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ +#define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ #define SCTLR_VE (1U << 24) /* up to v7 */ #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ #define SCTLR_EE (1U << 25) #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ -#define SCTLR_NMFI (1U << 27) -#define SCTLR_TRE (1U << 28) -#define SCTLR_AFE (1U << 29) -#define SCTLR_TE (1U << 30) +#define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ +#define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ +#define SCTLR_TRE (1U << 28) /* AArch32 only */ +#define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ +#define SCTLR_AFE (1U << 29) /* AArch32 only */ +#define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ +#define SCTLR_TE (1U << 30) /* AArch32 only */ +#define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ +#define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ +#define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ +#define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ +#define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ +#define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ +#define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ +#define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ +#define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ +#define SCTLR_DSSBS (1ULL << 44) /* v8.5 */ #define CPTR_TCPAC (1U << 31) #define CPTR_TTA (1U << 20) From patchwork Tue Jan 8 22:31:01 2019 Content-Type: text/plain; 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.31.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:31:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:01 +1000 Message-Id: <20190108223129.5570-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v3 03/31] target/arm: Add PAuth active bit to tbflags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There are 5 bits of state that could be added, but to save space within tbflags, add only a single enable bit. Helpers will determine the rest of the state at runtime. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson ---- v2: Fix whitespace, comment grammar. v3: Rebase on FIELD definition. --- target/arm/cpu.h | 1 + target/arm/translate.h | 2 ++ target/arm/helper.c | 19 +++++++++++++++++++ target/arm/translate-a64.c | 1 + 4 files changed, 23 insertions(+) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 843d5936ea..9ad7b2d11e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3014,6 +3014,7 @@ FIELD(TBFLAG_A64, TBI0, 0, 1) FIELD(TBFLAG_A64, TBI1, 1, 1) FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) +FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) static inline bool bswap_code(bool sctlr_b) { diff --git a/target/arm/translate.h b/target/arm/translate.h index 1550aa8bc7..d8a8bb4e9c 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -68,6 +68,8 @@ typedef struct DisasContext { bool is_ldex; /* True if a single-step exception will be taken to the current EL */ bool ss_same_el; + /* True if v8.3-PAuth is active. */ + bool pauth_active; /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ int c15_cpar; /* TCG op of the current insn_start. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index f00c141ef9..f23555b1dc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12983,6 +12983,25 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); } + + if (cpu_isar_feature(aa64_pauth, cpu)) { + /* + * In order to save space in flags, we record only whether + * pauth is "inactive", meaning all insns are implemented as + * a nop, or "active" when some action must be performed. + * The decision of which action to take is left to a helper. + */ + uint64_t sctlr; + if (current_el == 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + sctlr = env->cp15.sctlr_el[1]; + } else { + sctlr = env->cp15.sctlr_el[current_el]; + } + if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { + flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); + } + } } else { *pc = env->regs[15]; flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b7b6ab6371..37a57af715 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13409,6 +13409,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->fp_excp_el = FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL); dc->sve_excp_el = FIELD_EX32(tb_flags, TBFLAG_A64, SVEEXC_EL); dc->sve_len = (FIELD_EX32(tb_flags, TBFLAG_A64, ZCR_LEN) + 1) * 16; + dc->pauth_active = FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE); dc->vec_len = 0; dc->vec_stride = 0; dc->cp_regs = arm_cpu->cp_regs; From patchwork Tue Jan 8 22:31:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155010 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp33058jaa; Tue, 8 Jan 2019 14:34:57 -0800 (PST) X-Google-Smtp-Source: ALg8bN5MoP4xvdPalux/4b0pmLqxh8AxTwOR6Aym+Z+Ffq9YM4DAtCOwBSsj9Zb5xXTiFAzwB5XQ X-Received: by 2002:a5d:4202:: with SMTP id n2mr2789479wrq.260.1546986897499; Tue, 08 Jan 2019 14:34:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546986897; cv=none; d=google.com; s=arc-20160816; b=kq6u78S6qhrqbGwHkleWKT2UwnpQ4+CzZ+kXs9uUM3Sq4x9cNS+QM5c7j8heW+axuq BEvwMmpbVq8DVO9FAcH9TJGxWBv3iShFA5uhVHqhYti8IKLk2oHRZH4CyNSwfdmWTUN1 IqJPylVwpUkOqgrQ1dRN+Gk+s59FdXg6/AYTTy38r1uso8di+prX+n1Cur677XJegEkv SMfWKb6bQQqF5Oq/7DpUzZK5XRI1weCCBOjLD2GK+d3jq/8g1mExo2VdVcgD3Xw4vJyj BvtOnqHAlYN8IGyoQCmUbM6zjZKTsdq96vPqYF10mewS6HHz7LKB8CbNYslbOGWHHRJz 7mCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=DwJeWp+Qr2T2kEfXaMPGSK0wBAkLZExGSauaPxWOW3g=; b=jvg2EBvI/h/xHQ8h89tZyiMrqJWkeNbzohZi+t7xkCAw0V8lWuanllFVHB7mdoKbgY zVSxNro9PScGp93xKmDo52eLfQD7fwMHdJ/m+KrreFY8PRzqiSCqwU4xZ555BERk1aFp aFcggIP08TzI2p0qh5oWNHgcQHA1ef4F4JHvvNteYIKNJg6ZC4v5OZbhn8HZ/vxNv7Iq hTuiX3brcHDQ5Yr6WTidXrgcAWgFCFu3oUHNy4S8AP8YT1GHEgXSmVwRAZMRqfAsdxvA IbMmmBciSawmuGMjAieqR8kS7cDBzj8YM6BU3AGC4Pg6RJPvAE9Skp49ig1v7SMG75lz QP1g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GOZXTnC4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.31.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:31:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:02 +1000 Message-Id: <20190108223129.5570-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v3 04/31] target/arm: Introduce raise_exception_ra X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This path uses cpu_loop_exit_restore to unwind current processor state. Suggested-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 7 +++++++ target/arm/op_helper.c | 19 +++++++++++++++++-- 2 files changed, 24 insertions(+), 2 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/internals.h b/target/arm/internals.h index 78e026d6e9..c01a3f8c96 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -103,6 +103,13 @@ FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */ void QEMU_NORETURN raise_exception(CPUARMState *env, uint32_t excp, uint32_t syndrome, uint32_t target_el); +/* + * Similarly, but also use unwinding to restore cpu state. + */ +void QEMU_NORETURN raise_exception_ra(CPUARMState *env, uint32_t excp, + uint32_t syndrome, uint32_t target_el, + uintptr_t ra); + /* * For AArch64, map a given EL to an index in the banked_spsr array. * Note that this mapping and the AArch32 mapping defined in bank_number() diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index ef72361a36..8b31c6a13b 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -28,8 +28,8 @@ #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) -void raise_exception(CPUARMState *env, uint32_t excp, - uint32_t syndrome, uint32_t target_el) +static CPUState *do_raise_exception(CPUARMState *env, uint32_t excp, + uint32_t syndrome, uint32_t target_el) { CPUState *cs = CPU(arm_env_get_cpu(env)); @@ -50,9 +50,24 @@ void raise_exception(CPUARMState *env, uint32_t excp, cs->exception_index = excp; env->exception.syndrome = syndrome; env->exception.target_el = target_el; + + return cs; +} + +void raise_exception(CPUARMState *env, uint32_t excp, + uint32_t syndrome, uint32_t target_el) +{ + CPUState *cs = do_raise_exception(env, excp, syndrome, target_el); cpu_loop_exit(cs); } +void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, + uint32_t target_el, uintptr_t ra) +{ + CPUState *cs = do_raise_exception(env, excp, syndrome, target_el); + cpu_loop_exit_restore(cs, ra); +} + static int exception_target_el(CPUARMState *env) { int target_el = MAX(1, arm_current_el(env)); From patchwork Tue Jan 8 22:31:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155017 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp37446jaa; Tue, 8 Jan 2019 14:40:47 -0800 (PST) X-Google-Smtp-Source: ALg8bN5+8SEZR/QivhheQnD+AD0LFMPGVtLmE80P35wiI9FNSRXjNAnZ39JCIKBv2nJ1rXePor4k X-Received: by 2002:a1c:2856:: with SMTP id o83mr3417344wmo.45.1546987246926; Tue, 08 Jan 2019 14:40:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546987246; cv=none; d=google.com; s=arc-20160816; b=hFPaBUpNOWcBUsmnVBJhH/mKos/C6OwqiabrbM02VeBoo/XAveUHc2aT31Ri6odpJe Eo1twdO6p9A8+qd9VNOUyqaQOyYG8gi5hef0wkWK0HMChobEc+l2rNiwzeBX1OUl9rXB SNGG/wfmx4nFfkNH0Bwm2TAjWNFnz7jAuL3XymDZcdpF/6VUapUcRQQsdZrlxbrER509 TDdxNAp2VANGKW/icg0yDakRmAk28B1/pB+1UdAWyywbTsr+rPreMT1ymCWN2B3k8/Wp ji3ohPDgbOdwKoaZqMUUJXQkEN2WU+Xm6eHv35T8Q/gohPxo9SLcAWzpGvN7H8welV12 dNEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=h+04INpMZROzc9/azuKb56sot5Z3Kx02xVkcUaXDkl4=; b=kPXZnCyJSuVdjZRJ2lEfNypbbtj0Uk+T9hHNQQW2pTS/xmGlz1x+uwmFzjhMEgFemz 74zXAZyQc5fgiLIW/9ormQtpX4D9pYiT9PP4/WO87nfpwqxlbIVEwlL/swl6+I0jfi6O dUGCJLAqPorI83nPmSj7i1FDghZIYIXoXkaYttBWpFSD8JL6ZpJrrnwnGTKvKHLf49hf aLywJejXgE6QHnmbdg8O8jLSAsWS/td5n+iEKsixjLj5fRtsNBEGfs+U0hkUxQNUdOQl 9boi04wxh8rvkpDZWzEcp8fiY2ewGJQImBo/iBophZ1n3eU7pM3UVtPOMZXfZ8q4YQ77 Cpgg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=TgFB3Vm5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.31.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:31:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:03 +1000 Message-Id: <20190108223129.5570-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v3 05/31] target/arm: Add PAuth helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The cryptographic internals are stubbed out for now, but the enable and trap bits are checked. Signed-off-by: Richard Henderson ---- v2: Remove trap from xpac* helpers; these are now side-effect free. Use struct ARMPACKey. v3: Move code to pauth_helper.c; use raise_exception_ra. --- target/arm/helper-a64.h | 12 +++ target/arm/internals.h | 6 ++ target/arm/pauth_helper.c | 186 ++++++++++++++++++++++++++++++++++++++ target/arm/Makefile.objs | 1 + 4 files changed, 205 insertions(+) create mode 100644 target/arm/pauth_helper.c -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 9d3a907049..28aa0af69d 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -85,3 +85,15 @@ DEF_HELPER_2(advsimd_rinth, f16, f16, ptr) DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr) DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr) DEF_HELPER_2(sqrt_f16, f16, f16, ptr) + +DEF_HELPER_FLAGS_3(pacia, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(pacib, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(pacda, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(pacdb, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(pacga, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(autia, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(autib, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(autda, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(autdb, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64) +DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) diff --git a/target/arm/internals.h b/target/arm/internals.h index c01a3f8c96..0ed20c03cc 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -266,6 +266,7 @@ enum arm_exception_class { EC_CP14DTTRAP = 0x06, EC_ADVSIMDFPACCESSTRAP = 0x07, EC_FPIDTRAP = 0x08, + EC_PACTRAP = 0x09, EC_CP14RRTTRAP = 0x0c, EC_ILLEGALSTATE = 0x0e, EC_AA32_SVC = 0x11, @@ -433,6 +434,11 @@ static inline uint32_t syn_sve_access_trap(void) return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; } +static inline uint32_t syn_pactrap(void) +{ + return EC_PACTRAP << ARM_EL_EC_SHIFT; +} + static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) { return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c new file mode 100644 index 0000000000..902f68a24c --- /dev/null +++ b/target/arm/pauth_helper.c @@ -0,0 +1,186 @@ +/* + * ARM v8.3-PAuth Operations + * + * Copyright (c) 2019 Linaro, Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "exec/exec-all.h" +#include "exec/cpu_ldst.h" +#include "exec/helper-proto.h" +#include "tcg/tcg-gvec-desc.h" + + +static uint64_t pauth_computepac(uint64_t data, uint64_t modifier, + ARMPACKey key) +{ + g_assert_not_reached(); /* FIXME */ +} + +static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, + ARMPACKey *key, bool data) +{ + g_assert_not_reached(); /* FIXME */ +} + +static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, + ARMPACKey *key, bool data, int keynumber) +{ + g_assert_not_reached(); /* FIXME */ +} + +static uint64_t pauth_strip(CPUARMState *env, uint64_t ptr, bool data) +{ + g_assert_not_reached(); /* FIXME */ +} + +static void QEMU_NORETURN pauth_trap(CPUARMState *env, int target_el, + uintptr_t ra) +{ + raise_exception_ra(env, EXCP_UDEF, syn_pactrap(), target_el, ra); +} + +static void pauth_check_trap(CPUARMState *env, int el, uintptr_t ra) +{ + if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) { + uint64_t hcr = arm_hcr_el2_eff(env); + bool trap = !(hcr & HCR_API); + /* FIXME: ARMv8.1-VHE: trap only applies to EL1&0 regime. */ + /* FIXME: ARMv8.3-NV: HCR_NV trap takes precedence for ERETA[AB]. */ + if (trap) { + pauth_trap(env, 2, ra); + } + } + if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) { + if (!(env->cp15.scr_el3 & SCR_API)) { + pauth_trap(env, 3, ra); + } + } +} + +static bool pauth_key_enabled(CPUARMState *env, int el, uint32_t bit) +{ + uint32_t sctlr; + if (el == 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + sctlr = env->cp15.sctlr_el[1]; + } else { + sctlr = env->cp15.sctlr_el[el]; + } + return (sctlr & bit) != 0; +} + +uint64_t HELPER(pacia)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el = arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnIA)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_addpac(env, x, y, &env->apia_key, false); +} + +uint64_t HELPER(pacib)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el = arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnIB)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_addpac(env, x, y, &env->apib_key, false); +} + +uint64_t HELPER(pacda)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el = arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnDA)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_addpac(env, x, y, &env->apda_key, true); +} + +uint64_t HELPER(pacdb)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el = arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnDB)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_addpac(env, x, y, &env->apdb_key, true); +} + +uint64_t HELPER(pacga)(CPUARMState *env, uint64_t x, uint64_t y) +{ + uint64_t pac; + + pauth_check_trap(env, arm_current_el(env), GETPC()); + pac = pauth_computepac(x, y, env->apga_key); + + return pac & 0xffffffff00000000ull; +} + +uint64_t HELPER(autia)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el = arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnIA)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_auth(env, x, y, &env->apia_key, false, 0); +} + +uint64_t HELPER(autib)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el = arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnIB)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_auth(env, x, y, &env->apib_key, false, 1); +} + +uint64_t HELPER(autda)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el = arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnDA)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_auth(env, x, y, &env->apda_key, true, 0); +} + +uint64_t HELPER(autdb)(CPUARMState *env, uint64_t x, uint64_t y) +{ + int el = arm_current_el(env); + if (!pauth_key_enabled(env, el, SCTLR_EnDB)) { + return x; + } + pauth_check_trap(env, el, GETPC()); + return pauth_auth(env, x, y, &env->apdb_key, true, 1); +} + +uint64_t HELPER(xpaci)(CPUARMState *env, uint64_t a) +{ + return pauth_strip(env, a, false); +} + +uint64_t HELPER(xpacd)(CPUARMState *env, uint64_t a) +{ + return pauth_strip(env, a, true); +} diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 11c7baf8a3..1a4fc06448 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -8,6 +8,7 @@ obj-y += translate.o op_helper.o helper.o cpu.o obj-y += neon_helper.o iwmmxt_helper.o vec_helper.o obj-y += gdbstub.o obj-$(TARGET_AARCH64) += cpu64.o translate-a64.o helper-a64.o gdbstub64.o +obj-$(TARGET_AARCH64) += pauth_helper.o obj-y += crypto_helper.o obj-$(CONFIG_SOFTMMU) += arm-powerctl.o From patchwork Tue Jan 8 22:31:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155011 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp33131jaa; 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.31.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:31:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:04 +1000 Message-Id: <20190108223129.5570-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v3 06/31] target/arm: Decode PAuth within system hint space X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Use binary literals. --- target/arm/translate-a64.c | 93 +++++++++++++++++++++++++++++++++----- 1 file changed, 81 insertions(+), 12 deletions(-) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 37a57af715..b72aea3e97 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1471,33 +1471,102 @@ static void handle_hint(DisasContext *s, uint32_t insn, } switch (selector) { - case 0: /* NOP */ - return; - case 3: /* WFI */ + case 0b00000: /* NOP */ + break; + case 0b00011: /* WFI */ s->base.is_jmp = DISAS_WFI; - return; + break; + case 0b00001: /* YIELD */ /* When running in MTTCG we don't generate jumps to the yield and * WFE helpers as it won't affect the scheduling of other vCPUs. * If we wanted to more completely model WFE/SEV so we don't busy * spin unnecessarily we would need to do something more involved. */ - case 1: /* YIELD */ if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { s->base.is_jmp = DISAS_YIELD; } - return; - case 2: /* WFE */ + break; + case 0b00010: /* WFE */ if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { s->base.is_jmp = DISAS_WFE; } - return; - case 4: /* SEV */ - case 5: /* SEVL */ + break; + case 0b00100: /* SEV */ + case 0b00101: /* SEVL */ /* we treat all as NOP at least for now */ - return; + break; + case 0b00111: /* XPACLRI */ + if (s->pauth_active) { + gen_helper_xpaci(cpu_X[30], cpu_env, cpu_X[30]); + } + break; + case 0b01000: /* PACIA1716 */ + if (s->pauth_active) { + gen_helper_pacia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + } + break; + case 0b01010: /* PACIB1716 */ + if (s->pauth_active) { + gen_helper_pacib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + } + break; + case 0b01100: /* AUTIA1716 */ + if (s->pauth_active) { + gen_helper_autia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + } + break; + case 0b01110: /* AUTIB1716 */ + if (s->pauth_active) { + gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + } + break; + case 0b11000: /* PACIAZ */ + if (s->pauth_active) { + gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], + new_tmp_a64_zero(s)); + } + break; + case 0b11001: /* PACIASP */ + if (s->pauth_active) { + gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + } + break; + case 0b11010: /* PACIBZ */ + if (s->pauth_active) { + gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], + new_tmp_a64_zero(s)); + } + break; + case 0b11011: /* PACIBSP */ + if (s->pauth_active) { + gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + } + break; + case 0b11100: /* AUTIAZ */ + if (s->pauth_active) { + gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], + new_tmp_a64_zero(s)); + } + break; + case 0b11101: /* AUTIASP */ + if (s->pauth_active) { + gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + } + break; + case 0b11110: /* AUTIBZ */ + if (s->pauth_active) { + gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], + new_tmp_a64_zero(s)); + } + break; + case 0b11111: /* AUTIBSP */ + if (s->pauth_active) { + gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + } + break; default: /* default specified as NOP equivalent */ - return; + break; } } From patchwork Tue Jan 8 22:31:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155016 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp37416jaa; Tue, 8 Jan 2019 14:40:44 -0800 (PST) X-Google-Smtp-Source: ALg8bN5V1o50QANr/ChAejWTxpI6jh0pk4gdma2B9T+FvUNuh5X2xoeTZbbxMs+xRyHtXSFUAvI7 X-Received: by 2002:a1c:87cc:: with SMTP id j195mr3090793wmd.2.1546987244819; Tue, 08 Jan 2019 14:40:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546987244; cv=none; d=google.com; s=arc-20160816; b=Rwzrhrd+ad6AvLPC5M1Rb8SrvaEf4tpbDQVK/cN6nLlCXQKmKVQYhTXfBQR/NUbtPp 1W8k8+Wsq0ex10xcmdYxnW50qdwiajpO68DqrkpfaE5qoj2bY1oVWKj9oK2emdO48Hk6 WqRYSbF93Gg9eVZ6NB0UfKidAypWvGFvvNPA9fO/lK3F2kzfjDVR1r/46SwR1a90gu0y 6tTQYfBHaZRW+9XDy5saeDaLruWxxGhnExsxX7Wm4TQnlUH7w1CX9yM1w1hYR9vump7T QDthCd196kUr7Ls216XB78MeLAGGthsnoXjsyAc6DMASsS8kG0S9CCkPoP4DR+DvZyIF vv5A== ARC-Message-Signature: i=1; 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.31.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:31:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:05 +1000 Message-Id: <20190108223129.5570-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v3 07/31] target/arm: Rearrange decode in disas_data_proc_1src X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now properly signals unallocated for REV64 with SF=0. Allows for the opcode2 field to be decoded shortly. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 31 ++++++++++++++++++++++--------- 1 file changed, 22 insertions(+), 9 deletions(-) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b72aea3e97..dac61a3c3a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4563,38 +4563,51 @@ static void handle_rev16(DisasContext *s, unsigned int sf, */ static void disas_data_proc_1src(DisasContext *s, uint32_t insn) { - unsigned int sf, opcode, rn, rd; + unsigned int sf, opcode, opcode2, rn, rd; - if (extract32(insn, 29, 1) || extract32(insn, 16, 5)) { + if (extract32(insn, 29, 1)) { unallocated_encoding(s); return; } sf = extract32(insn, 31, 1); opcode = extract32(insn, 10, 6); + opcode2 = extract32(insn, 16, 5); rn = extract32(insn, 5, 5); rd = extract32(insn, 0, 5); - switch (opcode) { - case 0: /* RBIT */ +#define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7)) + + switch (MAP(sf, opcode2, opcode)) { + case MAP(0, 0x00, 0x00): /* RBIT */ + case MAP(1, 0x00, 0x00): handle_rbit(s, sf, rn, rd); break; - case 1: /* REV16 */ + case MAP(0, 0x00, 0x01): /* REV16 */ + case MAP(1, 0x00, 0x01): handle_rev16(s, sf, rn, rd); break; - case 2: /* REV32 */ + case MAP(0, 0x00, 0x02): /* REV/REV32 */ + case MAP(1, 0x00, 0x02): handle_rev32(s, sf, rn, rd); break; - case 3: /* REV64 */ + case MAP(1, 0x00, 0x03): /* REV64 */ handle_rev64(s, sf, rn, rd); break; - case 4: /* CLZ */ + case MAP(0, 0x00, 0x04): /* CLZ */ + case MAP(1, 0x00, 0x04): handle_clz(s, sf, rn, rd); break; - case 5: /* CLS */ + case MAP(0, 0x00, 0x05): /* CLS */ + case MAP(1, 0x00, 0x05): handle_cls(s, sf, rn, rd); break; + default: + unallocated_encoding(s); + break; } + +#undef MAP } static void handle_div(DisasContext *s, bool is_signed, unsigned int sf, From patchwork Tue Jan 8 22:31:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155015 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp35627jaa; Tue, 8 Jan 2019 14:38:12 -0800 (PST) X-Google-Smtp-Source: ALg8bN5vM1uzSyGqxpNDLCMxONhAJPfPLb1EjPnkwyvYL8tYzfSwa+ZBPXHgFdchy8eo5a8fg+Iz X-Received: by 2002:adf:fbc8:: with SMTP id d8mr2763642wrs.318.1546987092753; Tue, 08 Jan 2019 14:38:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546987092; cv=none; d=google.com; s=arc-20160816; b=bm1JoDo4cCnhytbNaG2+UM7x2PBEfCyN/fDTtJas2//F4vtiuXpMAZM2Na+56ycl+s nR9EwNeu2EKk4WmsScOvp+7jKs/ZaeKPYh5oxO9I0Amxxh5IKpzOUEFRKjhP1l24qXuZ 3JbhRsVIspXI8rLPcPPgd53pZVfoLtKubof326R0pyVW6WXTnLj84Vjp5ANOZOxydXJ9 dQQWir1JqH+avFKPbG07ysxrvYMUa75yMNuiQkDnlzd5xIPEV8iR8Xduywje5yed8gSc 2DPB+VAJPRzNZmMmt6LaosctEPPXglSy1QIS5zmKlq93BYtqqGLDrJTV64bZ4ypXCkLL vuAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=RPDBYEPnq8VUHD21sOkgc4lwKfdr/8rUEWyrTjwmWuI=; b=obbTFi2d/14dqVDBfhfJBApiQ9uda6BHpriSmNXj5R0iCQKbAi9kpTxfY8mLmiqyvP Sb8F24wlzIDGQFM7u1IEnXXMvGoW7dZVlFPEOMj0fGWZvlTJ7lE5Wbd11Er0T7kNHhih WbR0/F5jNot/EpJrOT3A5WGMlq3zz6Mi1LIEOIuBub6DORgtlOR2RE9TxFixkwVpulUr fNKUYuVYl9x0PU+m5A4C4Ej6V/KKehexpRtBSr5Sg74kprrkK5Swbk0BcChrA5FJ1lTT OIidHo/NW+KMJ21TIB7nNhQiGjE5KFGpIs2uCcXO1xbd28Wjq4EtHAxwo5++Q8/Sj3sX oCGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gRNKnM+y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.31.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:31:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:06 +1000 Message-Id: <20190108223129.5570-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 08/31] target/arm: Decode PAuth within disas_data_proc_1src X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 146 +++++++++++++++++++++++++++++++++++++ 1 file changed, 146 insertions(+) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index dac61a3c3a..8a8408c1b7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4564,6 +4564,7 @@ static void handle_rev16(DisasContext *s, unsigned int sf, static void disas_data_proc_1src(DisasContext *s, uint32_t insn) { unsigned int sf, opcode, opcode2, rn, rd; + TCGv_i64 tcg_rd; if (extract32(insn, 29, 1)) { unallocated_encoding(s); @@ -4602,7 +4603,152 @@ static void disas_data_proc_1src(DisasContext *s, uint32_t insn) case MAP(1, 0x00, 0x05): handle_cls(s, sf, rn, rd); break; + case MAP(1, 0x01, 0x00): /* PACIA */ + if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_pacia(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x01): /* PACIB */ + if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_pacib(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x02): /* PACDA */ + if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_pacda(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x03): /* PACDB */ + if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_pacdb(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x04): /* AUTIA */ + if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_autia(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x05): /* AUTIB */ + if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_autib(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x06): /* AUTDA */ + if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_autda(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x07): /* AUTDB */ + if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_autdb(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + } else if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + break; + case MAP(1, 0x01, 0x08): /* PACIZA */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_pacia(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x09): /* PACIZB */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_pacib(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x0a): /* PACDZA */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_pacda(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x0b): /* PACDZB */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_pacdb(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x0c): /* AUTIZA */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_autia(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x0d): /* AUTIZB */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_autib(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x0e): /* AUTDZA */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_autda(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x0f): /* AUTDZB */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_autdb(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + } + break; + case MAP(1, 0x01, 0x10): /* XPACI */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_xpaci(tcg_rd, cpu_env, tcg_rd); + } + break; + case MAP(1, 0x01, 0x11): /* XPACD */ + if (!dc_isar_feature(aa64_pauth, s) || rn != 31) { + goto do_unallocated; + } else if (s->pauth_active) { + tcg_rd = cpu_reg(s, rd); + gen_helper_xpacd(tcg_rd, cpu_env, tcg_rd); + } + break; default: + do_unallocated: unallocated_encoding(s); break; } From patchwork Tue Jan 8 22:31:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155018 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp37702jaa; Tue, 8 Jan 2019 14:41:10 -0800 (PST) X-Google-Smtp-Source: ALg8bN6NWPbIFrEPkAMDtBuGiNfmULf47Mrz/fekaqe1K+hbmaySjTC9H0jDXmx7ngA/TbtAxmu8 X-Received: by 2002:a1c:e1d5:: with SMTP id y204mr3082400wmg.65.1546987270409; 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.31.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:31:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:07 +1000 Message-Id: <20190108223129.5570-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v3 09/31] target/arm: Decode PAuth within disas_data_proc_2src X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8a8408c1b7..3f08db580b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4884,6 +4884,13 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) case 11: /* RORV */ handle_shift_reg(s, A64_SHIFT_TYPE_ROR, sf, rm, rn, rd); break; + case 12: /* PACGA */ + if (sf == 0 || !dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + gen_helper_pacga(cpu_reg(s, rd), cpu_env, + cpu_reg(s, rn), cpu_reg_sp(s, rm)); + break; case 16: case 17: case 18: @@ -4899,6 +4906,7 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) break; } default: + do_unallocated: unallocated_encoding(s); break; } From patchwork Tue Jan 8 22:31:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155021 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp39387jaa; Tue, 8 Jan 2019 14:43:41 -0800 (PST) X-Google-Smtp-Source: ALg8bN6yGNu4ffNUYy65OlQg36kB2++iQa+gQk+hI7YtvY1qqJd+Z5TR0HASn3IdO/OUQVayL2Rb X-Received: by 2002:a5d:65ce:: with SMTP id e14mr2741989wrw.150.1546987421860; Tue, 08 Jan 2019 14:43:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546987421; cv=none; d=google.com; s=arc-20160816; b=qx2TNQhpz1bi0fD/Zr3tIk2UR+C583eSCG2f58LluEsbHK8t1HKVGHUgdfnyiVs/73 0eqfRNgKMuP9Vja7gD0BqJqs0YDIkxZNj2ScCOYq/V7eikPtf2w6z3OgHHhbLsECAf5e S/JDR5nSe5ifoe3gLmXGk8xQJzVm99868LudjfISi5VHstueEMes+5bGCG1wvsRKdb4q po3cPOH4Vesv4VTgWS9qTqlklEUWkI7V0C78dDsYTxazHrOLy00kVl/RNP27Lwisrhio pQ1kkjuOzsq03RXayt9teoj4U8/1OoWXBx6q2YvbN9kCHyezLqRx1sDe2Ps3tKONP/Me PP6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=Lt41ush15v+T/TJPDHCvxVydKk9mEhGCuLjZ+pQgQ+U=; b=dXX8ekPEK0Ae1e2nDTY+D44mqp/qLEn50MDemmnzaMwqawkpgGSiZ9mC0UOjDDlNmZ Tv7ok2Q3m5/iKQZ+BHlws/L8fQt6cxizEDBBtLIMPAZL49e3CK7Q7wgQXsgIf7msA7Rv l2eBobFJh172xFBVkXEfXyC1Yxro0NLsQp5h/Q+RHkGAt0oRIoRx6EjO3CHBB2S0RtXM GpG9Akh1O/ZEPRemC3GOmBnxkSgXHgpmtHgaVumMM4YQOR5zYFmR4V3PiMOkO8db2XGF C/42MpBOAdLerjVcmLfwtqtOmrbSvXE2VfoSeBkJgeb/LZ8cwT0AcDtoFRMaGsSCxdnk WUWw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="I/Eb/Qmc"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:08 +1000 Message-Id: <20190108223129.5570-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v3 10/31] target/arm: Move helper_exception_return to helper-a64.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This function is only used by AArch64. Code movement only. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 2 + target/arm/helper.h | 1 - target/arm/helper-a64.c | 155 ++++++++++++++++++++++++++++++++++++++++ target/arm/op_helper.c | 155 ---------------------------------------- 4 files changed, 157 insertions(+), 156 deletions(-) -- 2.17.2 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 28aa0af69d..55299896c4 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -86,6 +86,8 @@ DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr) DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr) DEF_HELPER_2(sqrt_f16, f16, f16, ptr) +DEF_HELPER_1(exception_return, void, env) + DEF_HELPER_FLAGS_3(pacia, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(pacib, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(pacda, TCG_CALL_NO_WG, i64, env, i64, i64) diff --git a/target/arm/helper.h b/target/arm/helper.h index 8c9590091b..53a38188c6 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -79,7 +79,6 @@ DEF_HELPER_2(get_cp_reg64, i64, env, ptr) DEF_HELPER_3(msr_i_pstate, void, env, i32, i32) DEF_HELPER_1(clear_pstate_ss, void, env) -DEF_HELPER_1(exception_return, void, env) DEF_HELPER_2(get_r13_banked, i32, env, i32) DEF_HELPER_3(set_r13_banked, void, env, i32, i32) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 61799d20e1..66ff70dcdb 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -887,6 +887,161 @@ uint32_t HELPER(advsimd_f16touinth)(uint32_t a, void *fpstp) return float16_to_uint16(a, fpst); } +static int el_from_spsr(uint32_t spsr) +{ + /* Return the exception level that this SPSR is requesting a return to, + * or -1 if it is invalid (an illegal return) + */ + if (spsr & PSTATE_nRW) { + switch (spsr & CPSR_M) { + case ARM_CPU_MODE_USR: + return 0; + case ARM_CPU_MODE_HYP: + return 2; + case ARM_CPU_MODE_FIQ: + case ARM_CPU_MODE_IRQ: + case ARM_CPU_MODE_SVC: + case ARM_CPU_MODE_ABT: + case ARM_CPU_MODE_UND: + case ARM_CPU_MODE_SYS: + return 1; + case ARM_CPU_MODE_MON: + /* Returning to Mon from AArch64 is never possible, + * so this is an illegal return. + */ + default: + return -1; + } + } else { + if (extract32(spsr, 1, 1)) { + /* Return with reserved M[1] bit set */ + return -1; + } + if (extract32(spsr, 0, 4) == 1) { + /* return to EL0 with M[0] bit set */ + return -1; + } + return extract32(spsr, 2, 2); + } +} + +void HELPER(exception_return)(CPUARMState *env) +{ + int cur_el = arm_current_el(env); + unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el); + uint32_t spsr = env->banked_spsr[spsr_idx]; + int new_el; + bool return_to_aa64 = (spsr & PSTATE_nRW) == 0; + + aarch64_save_sp(env, cur_el); + + arm_clear_exclusive(env); + + /* We must squash the PSTATE.SS bit to zero unless both of the + * following hold: + * 1. debug exceptions are currently disabled + * 2. singlestep will be active in the EL we return to + * We check 1 here and 2 after we've done the pstate/cpsr write() to + * transition to the EL we're going to. + */ + if (arm_generate_debug_exceptions(env)) { + spsr &= ~PSTATE_SS; + } + + new_el = el_from_spsr(spsr); + if (new_el == -1) { + goto illegal_return; + } + if (new_el > cur_el + || (new_el == 2 && !arm_feature(env, ARM_FEATURE_EL2))) { + /* Disallow return to an EL which is unimplemented or higher + * than the current one. + */ + goto illegal_return; + } + + if (new_el != 0 && arm_el_is_aa64(env, new_el) != return_to_aa64) { + /* Return to an EL which is configured for a different register width */ + goto illegal_return; + } + + if (new_el == 2 && arm_is_secure_below_el3(env)) { + /* Return to the non-existent secure-EL2 */ + goto illegal_return; + } + + if (new_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { + goto illegal_return; + } + + qemu_mutex_lock_iothread(); + arm_call_pre_el_change_hook(arm_env_get_cpu(env)); + qemu_mutex_unlock_iothread(); + + if (!return_to_aa64) { + env->aarch64 = 0; + /* We do a raw CPSR write because aarch64_sync_64_to_32() + * will sort the register banks out for us, and we've already + * caught all the bad-mode cases in el_from_spsr(). + */ + cpsr_write(env, spsr, ~0, CPSRWriteRaw); + if (!arm_singlestep_active(env)) { + env->uncached_cpsr &= ~PSTATE_SS; + } + aarch64_sync_64_to_32(env); + + if (spsr & CPSR_T) { + env->regs[15] = env->elr_el[cur_el] & ~0x1; + } else { + env->regs[15] = env->elr_el[cur_el] & ~0x3; + } + qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " + "AArch32 EL%d PC 0x%" PRIx32 "\n", + cur_el, new_el, env->regs[15]); + } else { + env->aarch64 = 1; + pstate_write(env, spsr); + if (!arm_singlestep_active(env)) { + env->pstate &= ~PSTATE_SS; + } + aarch64_restore_sp(env, new_el); + env->pc = env->elr_el[cur_el]; + qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " + "AArch64 EL%d PC 0x%" PRIx64 "\n", + cur_el, new_el, env->pc); + } + /* + * Note that cur_el can never be 0. If new_el is 0, then + * el0_a64 is return_to_aa64, else el0_a64 is ignored. + */ + aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64); + + qemu_mutex_lock_iothread(); + arm_call_el_change_hook(arm_env_get_cpu(env)); + qemu_mutex_unlock_iothread(); + + return; + +illegal_return: + /* Illegal return events of various kinds have architecturally + * mandated behaviour: + * restore NZCV and DAIF from SPSR_ELx + * set PSTATE.IL + * restore PC from ELR_ELx + * no change to exception level, execution state or stack pointer + */ + env->pstate |= PSTATE_IL; + env->pc = env->elr_el[cur_el]; + spsr &= PSTATE_NZCV | PSTATE_DAIF; + spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF); + pstate_write(env, spsr); + if (!arm_singlestep_active(env)) { + env->pstate &= ~PSTATE_SS; + } + qemu_log_mask(LOG_GUEST_ERROR, "Illegal exception return at EL%d: " + "resuming execution at 0x%" PRIx64 "\n", cur_el, env->pc); +} + /* * Square Root and Reciprocal square root */ diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 8b31c6a13b..c998eadfaa 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -1029,161 +1029,6 @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome) } } -static int el_from_spsr(uint32_t spsr) -{ - /* Return the exception level that this SPSR is requesting a return to, - * or -1 if it is invalid (an illegal return) - */ - if (spsr & PSTATE_nRW) { - switch (spsr & CPSR_M) { - case ARM_CPU_MODE_USR: - return 0; - case ARM_CPU_MODE_HYP: - return 2; - case ARM_CPU_MODE_FIQ: - case ARM_CPU_MODE_IRQ: - case ARM_CPU_MODE_SVC: - case ARM_CPU_MODE_ABT: - case ARM_CPU_MODE_UND: - case ARM_CPU_MODE_SYS: - return 1; - case ARM_CPU_MODE_MON: - /* Returning to Mon from AArch64 is never possible, - * so this is an illegal return. - */ - default: - return -1; - } - } else { - if (extract32(spsr, 1, 1)) { - /* Return with reserved M[1] bit set */ - return -1; - } - if (extract32(spsr, 0, 4) == 1) { - /* return to EL0 with M[0] bit set */ - return -1; - } - return extract32(spsr, 2, 2); - } -} - -void HELPER(exception_return)(CPUARMState *env) -{ - int cur_el = arm_current_el(env); - unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el); - uint32_t spsr = env->banked_spsr[spsr_idx]; - int new_el; - bool return_to_aa64 = (spsr & PSTATE_nRW) == 0; - - aarch64_save_sp(env, cur_el); - - arm_clear_exclusive(env); - - /* We must squash the PSTATE.SS bit to zero unless both of the - * following hold: - * 1. debug exceptions are currently disabled - * 2. singlestep will be active in the EL we return to - * We check 1 here and 2 after we've done the pstate/cpsr write() to - * transition to the EL we're going to. - */ - if (arm_generate_debug_exceptions(env)) { - spsr &= ~PSTATE_SS; - } - - new_el = el_from_spsr(spsr); - if (new_el == -1) { - goto illegal_return; - } - if (new_el > cur_el - || (new_el == 2 && !arm_feature(env, ARM_FEATURE_EL2))) { - /* Disallow return to an EL which is unimplemented or higher - * than the current one. - */ - goto illegal_return; - } - - if (new_el != 0 && arm_el_is_aa64(env, new_el) != return_to_aa64) { - /* Return to an EL which is configured for a different register width */ - goto illegal_return; - } - - if (new_el == 2 && arm_is_secure_below_el3(env)) { - /* Return to the non-existent secure-EL2 */ - goto illegal_return; - } - - if (new_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { - goto illegal_return; - } - - qemu_mutex_lock_iothread(); - arm_call_pre_el_change_hook(arm_env_get_cpu(env)); - qemu_mutex_unlock_iothread(); - - if (!return_to_aa64) { - env->aarch64 = 0; - /* We do a raw CPSR write because aarch64_sync_64_to_32() - * will sort the register banks out for us, and we've already - * caught all the bad-mode cases in el_from_spsr(). - */ - cpsr_write(env, spsr, ~0, CPSRWriteRaw); - if (!arm_singlestep_active(env)) { - env->uncached_cpsr &= ~PSTATE_SS; - } - aarch64_sync_64_to_32(env); - - if (spsr & CPSR_T) { - env->regs[15] = env->elr_el[cur_el] & ~0x1; - } else { - env->regs[15] = env->elr_el[cur_el] & ~0x3; - } - qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " - "AArch32 EL%d PC 0x%" PRIx32 "\n", - cur_el, new_el, env->regs[15]); - } else { - env->aarch64 = 1; - pstate_write(env, spsr); - if (!arm_singlestep_active(env)) { - env->pstate &= ~PSTATE_SS; - } - aarch64_restore_sp(env, new_el); - env->pc = env->elr_el[cur_el]; - qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " - "AArch64 EL%d PC 0x%" PRIx64 "\n", - cur_el, new_el, env->pc); - } - /* - * Note that cur_el can never be 0. If new_el is 0, then - * el0_a64 is return_to_aa64, else el0_a64 is ignored. - */ - aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64); - - qemu_mutex_lock_iothread(); - arm_call_el_change_hook(arm_env_get_cpu(env)); - qemu_mutex_unlock_iothread(); - - return; - -illegal_return: - /* Illegal return events of various kinds have architecturally - * mandated behaviour: - * restore NZCV and DAIF from SPSR_ELx - * set PSTATE.IL - * restore PC from ELR_ELx - * no change to exception level, execution state or stack pointer - */ - env->pstate |= PSTATE_IL; - env->pc = env->elr_el[cur_el]; - spsr &= PSTATE_NZCV | PSTATE_DAIF; - spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF); - pstate_write(env, spsr); - if (!arm_singlestep_active(env)) { - env->pstate &= ~PSTATE_SS; - } - qemu_log_mask(LOG_GUEST_ERROR, "Illegal exception return at EL%d: " - "resuming execution at 0x%" PRIx64 "\n", cur_el, env->pc); -} - /* Return true if the linked breakpoint entry lbn passes its checks */ static bool linked_bp_matches(ARMCPU *cpu, int lbn) { From patchwork Tue Jan 8 22:31:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155020 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp39347jaa; Tue, 8 Jan 2019 14:43:37 -0800 (PST) X-Google-Smtp-Source: ALg8bN7+RpLIPsWqjS7Axb0qt1djmEBoe+05OSfsS6h2hl8fdCAILdOy2niG5vk1aL+RXvyH7ZAW X-Received: by 2002:adf:b243:: with SMTP id y3mr2929018wra.184.1546987417288; Tue, 08 Jan 2019 14:43:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546987417; cv=none; d=google.com; s=arc-20160816; b=OQXwDlvX05M/UOX/ndy9YkispsSpDi3zhKsem/UXV7VnYItNR6jQcTWBCkTUO48KRo zqU/TG1opf+mc6y91U2Cdd8m2xVg2ZXKkHZOLlb4V8jiiSuZCsSHFYeiPgTL8hrD+smc onuOu639FYg96PGbNFEJBRoOzZMeEC7Tm5SFGMuiSknPEHykn0HmPPUbdhiPo46ipGpz AKkodqDOqqbc5elb709uXKMWjR+jyGWyNFX8Yy27ly1cMVh/ncpJ1fCz/tEErGAzHZd5 q1Z9ZZXiEdgpM6IxlYuMY1VHJ4+kexHLFc9MYnGWavXghTDeA2g8F3aJqaQZpcIJRWYM 64GQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=jUqKqF6uZxUk1yU/tgbIwMa93VE1Y7GaEYbnjg1Eu+A=; b=wnbWKLc05cfo8M+metlw4i8KOk5lWLh5g+KPIaXJzvBSYCfedsjOwD+hseg+WC2+jV /rG9O6Fp0Hdc5f4IfLmYIW4YIDfOHhNGZUIWmZoLQzbaVzZJPDSHe6VwpExpP3cIZIm4 /bgfPdCavryp2lLBfNsynir3j2b7wpkZlM8IOCuUWkPx5C612OXXGfIlx/l9sLKt4VAl jQ49WNykWkbSo8YahpmfuU7xyTtNpmWJ25ODbovoTx69yOf7Jvf2qLxqE98esydVoJUC DSYPGGzGE7aeRwkCL0NGz+HQUkLpBUMcRJWRd0xWgqfh0kimeMLAfxb5wO46LKuCyhZG FHIg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=foHoYkCE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:09 +1000 Message-Id: <20190108223129.5570-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::430 Subject: [Qemu-devel] [PATCH v3 11/31] target/arm: Add new_pc argument to helper_exception_return X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 2 +- target/arm/helper-a64.c | 10 +++++----- target/arm/translate-a64.c | 7 ++++++- 3 files changed, 12 insertions(+), 7 deletions(-) -- 2.17.2 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 55299896c4..aff8d6c9f3 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -86,7 +86,7 @@ DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr) DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr) DEF_HELPER_2(sqrt_f16, f16, f16, ptr) -DEF_HELPER_1(exception_return, void, env) +DEF_HELPER_2(exception_return, void, env, i64) DEF_HELPER_FLAGS_3(pacia, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(pacib, TCG_CALL_NO_WG, i64, env, i64, i64) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 66ff70dcdb..101fa6d3ea 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -925,7 +925,7 @@ static int el_from_spsr(uint32_t spsr) } } -void HELPER(exception_return)(CPUARMState *env) +void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) { int cur_el = arm_current_el(env); unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el); @@ -991,9 +991,9 @@ void HELPER(exception_return)(CPUARMState *env) aarch64_sync_64_to_32(env); if (spsr & CPSR_T) { - env->regs[15] = env->elr_el[cur_el] & ~0x1; + env->regs[15] = new_pc & ~0x1; } else { - env->regs[15] = env->elr_el[cur_el] & ~0x3; + env->regs[15] = new_pc & ~0x3; } qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " "AArch32 EL%d PC 0x%" PRIx32 "\n", @@ -1005,7 +1005,7 @@ void HELPER(exception_return)(CPUARMState *env) env->pstate &= ~PSTATE_SS; } aarch64_restore_sp(env, new_el); - env->pc = env->elr_el[cur_el]; + env->pc = new_pc; qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " "AArch64 EL%d PC 0x%" PRIx64 "\n", cur_el, new_el, env->pc); @@ -1031,7 +1031,7 @@ illegal_return: * no change to exception level, execution state or stack pointer */ env->pstate |= PSTATE_IL; - env->pc = env->elr_el[cur_el]; + env->pc = new_pc; spsr &= PSTATE_NZCV | PSTATE_DAIF; spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF); pstate_write(env, spsr); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 3f08db580b..2df2323646 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1981,6 +1981,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) { unsigned int opc, op2, op3, rn, op4; + TCGv_i64 dst; opc = extract32(insn, 21, 4); op2 = extract32(insn, 16, 5); @@ -2011,7 +2012,11 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } - gen_helper_exception_return(cpu_env); + dst = tcg_temp_new_i64(); + tcg_gen_ld_i64(dst, cpu_env, + offsetof(CPUARMState, elr_el[s->current_el])); + gen_helper_exception_return(cpu_env, dst); + tcg_temp_free_i64(dst); if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_end(); } From patchwork Tue Jan 8 22:31:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155014 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp35506jaa; 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:10 +1000 Message-Id: <20190108223129.5570-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::632 Subject: [Qemu-devel] [PATCH v3 12/31] target/arm: Rearrange decode in disas_uncond_b_reg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This will enable PAuth decode in a subsequent patch. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 47 +++++++++++++++++++++++++++++--------- 1 file changed, 36 insertions(+), 11 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2df2323646..e601753032 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1989,32 +1989,54 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) rn = extract32(insn, 5, 5); op4 = extract32(insn, 0, 5); - if (op4 != 0x0 || op3 != 0x0 || op2 != 0x1f) { - unallocated_encoding(s); - return; + if (op2 != 0x1f) { + goto do_unallocated; } switch (opc) { case 0: /* BR */ case 1: /* BLR */ case 2: /* RET */ - gen_a64_set_pc(s, cpu_reg(s, rn)); + switch (op3) { + case 0: + if (op4 != 0) { + goto do_unallocated; + } + dst = cpu_reg(s, rn); + break; + + default: + goto do_unallocated; + } + + gen_a64_set_pc(s, dst); /* BLR also needs to load return address */ if (opc == 1) { tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); } break; + case 4: /* ERET */ if (s->current_el == 0) { - unallocated_encoding(s); - return; + goto do_unallocated; + } + switch (op3) { + case 0: + if (op4 != 0) { + goto do_unallocated; + } + dst = tcg_temp_new_i64(); + tcg_gen_ld_i64(dst, cpu_env, + offsetof(CPUARMState, elr_el[s->current_el])); + break; + + default: + goto do_unallocated; } if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } - dst = tcg_temp_new_i64(); - tcg_gen_ld_i64(dst, cpu_env, - offsetof(CPUARMState, elr_el[s->current_el])); + gen_helper_exception_return(cpu_env, dst); tcg_temp_free_i64(dst); if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { @@ -2023,14 +2045,17 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) /* Must exit loop to check un-masked IRQs */ s->base.is_jmp = DISAS_EXIT; return; + case 5: /* DRPS */ - if (rn != 0x1f) { - unallocated_encoding(s); + if (op3 != 0 || op4 != 0 || rn != 0x1f) { + goto do_unallocated; } else { unsupported_encoding(s, insn); } return; + default: + do_unallocated: unallocated_encoding(s); return; } From patchwork Tue Jan 8 22:31:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155026 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp41796jaa; Tue, 8 Jan 2019 14:47:02 -0800 (PST) X-Google-Smtp-Source: ALg8bN7f0dj4d5NQ2nr6RAry95TgMLKUrVTvE76+wVA+WnYtbpLmHIOdhCNTj0i2d+XBVadBrz7T X-Received: by 2002:a1c:2457:: with SMTP id k84mr3124605wmk.139.1546987621927; Tue, 08 Jan 2019 14:47:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546987621; cv=none; d=google.com; s=arc-20160816; b=fxajgR5XIQllyI1W98J0BkvRpl4+xXQHUJgGjeCGnHB5gtnF93h1aoDU5c91BIvhsJ TfGGip6hVj6mr1vO4cKtfaPhgVUv9kPo0ql9UIdGP9X3vrdZkH3bTeTPa6GQ6W9KASOn 9c3ksMCk526RPgLwRi4DyXQsgBZ5hvk5aUmQtns+8uPBk68L/efnG+LsOZENZEc4nCFP PJWIkZHYEYFFePtnCqBwj3YjpwFWxvkOXg4LwpNTs7M8x3OgvrL0IIoG2jfP9bDynS6/ 4R8k+ossqiHhOOn4vkbGzbWDdoQqeVDjRVja/1blddF5ilofO7B99IGsNgbXSAIfKLoq lC6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=WDCmraVytCVp2uFN73TTP/9xo07ZZ0ObLi7t4pJW3JA=; b=wLdEuBvbDqBvfh5X2Kdc3Zc7sjOVybwNo4YonSJ3ZeFHvl7tS62Y/bv7AmMYV+lOGY BOIByVBxHOQXbxQLG43uSSV9feZ5J/f8KskpqmmW6IxIROE55C2UNswpg14Xbszaw/1k X9V5qi4gsa3i1lfImCxp7S+pZrtOs2iFDI5FD2iSVzbGT3tI7au80QIfajRUNBN7IcRE TdTpN/fUUzUPDyXQIMHHJCOE6S3LsuiMxWxiMLmX6ykudtUarXUBAb4fbU/Ru6WMS2KH ful5Ni0fpHpxNNvm73wnG2Xb7ALB6+ZNc2xARLXUl8bNvGCBEiPp0LfHIR23e+XuezwL 3S2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jXBE5C17; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:11 +1000 Message-Id: <20190108223129.5570-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v3 13/31] target/arm: Decode PAuth within disas_uncond_b_reg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 82 +++++++++++++++++++++++++++++++++++++- 1 file changed, 81 insertions(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e601753032..fa50003f0b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1982,6 +1982,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) { unsigned int opc, op2, op3, rn, op4; TCGv_i64 dst; + TCGv_i64 modifier; opc = extract32(insn, 21, 4); op2 = extract32(insn, 16, 5); @@ -1999,12 +2000,44 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) case 2: /* RET */ switch (op3) { case 0: + /* BR, BLR, RET */ if (op4 != 0) { goto do_unallocated; } dst = cpu_reg(s, rn); break; + case 2: + case 3: + if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + if (opc == 2) { + /* RETAA, RETAB */ + if (rn != 0x1f || op4 != 0x1f) { + goto do_unallocated; + } + rn = 30; + modifier = cpu_X[31]; + } else { + /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */ + if (op4 != 0x1f) { + goto do_unallocated; + } + modifier = new_tmp_a64_zero(s); + } + if (s->pauth_active) { + dst = new_tmp_a64(s); + if (op3 == 2) { + gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier); + } else { + gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier); + } + } else { + dst = cpu_reg(s, rn); + } + break; + default: goto do_unallocated; } @@ -2016,12 +2049,38 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) } break; + case 8: /* BRAA */ + case 9: /* BLRAA */ + if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + if (op3 != 2 || op3 != 3) { + goto do_unallocated; + } + if (s->pauth_active) { + dst = new_tmp_a64(s); + modifier = cpu_reg_sp(s, op4); + if (op3 == 2) { + gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier); + } else { + gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier); + } + } else { + dst = cpu_reg(s, rn); + } + gen_a64_set_pc(s, dst); + /* BLRAA also needs to load return address */ + if (opc == 9) { + tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); + } + break; + case 4: /* ERET */ if (s->current_el == 0) { goto do_unallocated; } switch (op3) { - case 0: + case 0: /* ERET */ if (op4 != 0) { goto do_unallocated; } @@ -2030,6 +2089,27 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) offsetof(CPUARMState, elr_el[s->current_el])); break; + case 2: /* ERETAA */ + case 3: /* ERETAB */ + if (!dc_isar_feature(aa64_pauth, s)) { + goto do_unallocated; + } + if (rn != 0x1f || op4 != 0x1f) { + goto do_unallocated; + } + dst = tcg_temp_new_i64(); + tcg_gen_ld_i64(dst, cpu_env, + offsetof(CPUARMState, elr_el[s->current_el])); + if (s->pauth_active) { + modifier = cpu_X[31]; + if (op3 == 2) { + gen_helper_autia(dst, cpu_env, dst, modifier); + } else { + gen_helper_autib(dst, cpu_env, dst, modifier); + } + } + break; + default: goto do_unallocated; } From patchwork Tue Jan 8 22:31:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155023 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp39683jaa; Tue, 8 Jan 2019 14:44:07 -0800 (PST) X-Google-Smtp-Source: ALg8bN4foqcvFVqaZySWq8yrhsOZM6DKMqA/hdOu6stuEXwUvcLT8X8Q0C+dOSQwwlXiPHBeabAZ X-Received: by 2002:a5d:6988:: with SMTP id g8mr2703778wru.33.1546987446913; Tue, 08 Jan 2019 14:44:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546987446; cv=none; d=google.com; s=arc-20160816; b=lRQQakYoz7l4GISuAG8a9XVJm6hMTH7ymzCtsjuKDzeu43KdKwWiQjgu7cKL84gBO4 hrvebbAmrH34Pw8nF6YTFPcb6F0t8kKSNxPT0g3hG7IBbnB6HFA6W9LxK55NNfrvTIeS KazAz3Ul54Uo3yq6GEWVqXeS2CZv/CPzA8Evet4j0LlroBQIJjrtKSU8SgfVabP/GfcW g1uu7NT24OYUoq901IBMAxu9iS1jgofhIR3xF41YGRVqgVBmBylS5TJ79RhsubJ8I8ZZ 4JMj+0w7699GCnQ6gk8F7QD1NqJpB1CREIoBhMsfltHOzBtJR7DvNX/s/b4GiyQ5lOEi aHGQ== ARC-Message-Signature: i=1; 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:12 +1000 Message-Id: <20190108223129.5570-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v3 14/31] target/arm: Decode Load/store register (pac) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Not that there are any stores involved, but why argue with ARM's naming convention. Signed-off-by: Richard Henderson --- v3: Use do_gpr_ld; fix sextend typo; iss_valid only for !wback. --- target/arm/translate-a64.c | 60 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index fa50003f0b..a4dfdf5836 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3146,6 +3146,63 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, s->be_data | size | MO_ALIGN); } +/* PAC memory operations + * + * 31 30 27 26 24 22 21 12 11 10 5 0 + * +------+-------+---+-----+-----+---+--------+---+---+----+-----+ + * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt | + * +------+-------+---+-----+-----+------------+---+---+----+-----+ + * + * Rt: the result register + * Rn: base address or SP + * V: vector flag (always 0 as of v8.3) + * M: clear for key DA, set for key DB + * W: pre-indexing flag + * S: sign for imm9. + */ +static void disas_ldst_pac(DisasContext *s, uint32_t insn, + int size, int rt, bool is_vector) +{ + int rn = extract32(insn, 5, 5); + bool is_wback = extract32(insn, 11, 1); + bool use_key_a = !extract32(insn, 23, 1); + int offset; + TCGv_i64 tcg_addr, tcg_rt; + + if (size != 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) { + unallocated_encoding(s); + return; + } + + if (rn == 31) { + gen_check_sp_alignment(s); + } + tcg_addr = read_cpu_reg_sp(s, rn, 1); + + if (s->pauth_active) { + if (use_key_a) { + gen_helper_autda(tcg_addr, cpu_env, tcg_addr, cpu_X[31]); + } else { + gen_helper_autdb(tcg_addr, cpu_env, tcg_addr, cpu_X[31]); + } + } + + /* Form the 10-bit signed, scaled offset. */ + offset = (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9); + offset = sextract32(offset << size, 0, 10 + size); + tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); + + tcg_rt = cpu_reg(s, rt); + + do_gpr_ld(s, tcg_rt, tcg_addr, size, /* is_signed */ false, + /* extend */ false, /* iss_valid */ !is_wback, + /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false); + + if (is_wback) { + tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr); + } +} + /* Load/store register (all forms) */ static void disas_ldst_reg(DisasContext *s, uint32_t insn) { @@ -3171,6 +3228,9 @@ static void disas_ldst_reg(DisasContext *s, uint32_t insn) case 2: disas_ldst_reg_roffset(s, insn, opc, size, rt, is_vector); return; + default: + disas_ldst_pac(s, insn, size, rt, is_vector); + return; } break; case 1: From patchwork Tue Jan 8 22:31:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155029 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp44180jaa; Tue, 8 Jan 2019 14:50:17 -0800 (PST) X-Google-Smtp-Source: ALg8bN4isjb4C+eKysqSzcscn68UD6hX/yDiKQVhplomdwtGzI38FD+DumNdCxXp6lCXMHFwwGm/ X-Received: by 2002:adf:90e5:: with SMTP id i92mr2676785wri.210.1546987817451; Tue, 08 Jan 2019 14:50:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546987817; cv=none; d=google.com; s=arc-20160816; b=EFWCNVafjY0oFSjvY3f0f0zxO5KQH+DOLsHhdPf0I8pnHEu67Up0sIJ2kOMxPDh38R 3QmW8YchONEgg4OYvrBglBKQ/NhNtNsBa1xMYC/l4O0UmB0ROe1gkRsYQ1ERFNWOw1vR tV+0VuIDYizIm+zcW8zt1/zRtboMxmozo89TtMs7gxRqH3BvNCo+wOG9SoBgC+qFWcM5 8PZSlGF6UQnBhexK6/f2492aw+4+06eq5Gesr5oy6TQxrHrXKcSgTP7qTIzwzG6Ffz8P qu6Y4iw9FH1GBowtCGJ8gdQIC9leaHmXo6A3ZZ+D5Y7OZvJoFy3bIwOe/YGZcKGCdXoA yrwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=NXvQI4SDFPXeWp0pGzcoDK8YDYSgU/rnRAlnBVBgc8Q=; b=ne47LC9AhPmiqI+z3lrTCwM294EK56CIBwKFbQCjistmO3/b2fL11WX1P48mv3lQ0Q i7l3xwmGZBSmkYTcew7h77V6B4xFwvrPFoNErYrHfoP6yaiYzegO7w7zKzv/n6V48tm4 W9fpV1pdLollodYJEgZhIHnQ4Mds8D9nnDWZ/TZW72S0EfLdkepzlpzbAmyvpkkGiF0Q JRHzH9ejgJurX416+HF8ObU5HFPnqYEaGdb0LxXjaZK79tBktC9rWtzIKnlji6EFL7iE JY0Nu5u1MCG8cPXgnptQrlktseg4QNetT70TAq1LXM/NDZTYrPCyxli9gUErreCu4Qkk YTwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kV6+cR9q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:13 +1000 Message-Id: <20190108223129.5570-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v3 15/31] target/arm: Move cpu_mmu_index out of line X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This function is, or will shortly become, too big to inline. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 48 +++++---------------------------------------- target/arm/helper.c | 44 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+), 43 deletions(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9ad7b2d11e..eb83a71b67 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2741,54 +2741,16 @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) } /* Return the MMU index for a v7M CPU in the specified security and - * privilege state + * privilege state. */ -static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, - bool secstate, - bool priv) -{ - ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; - - if (priv) { - mmu_idx |= ARM_MMU_IDX_M_PRIV; - } - - if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) { - mmu_idx |= ARM_MMU_IDX_M_NEGPRI; - } - - if (secstate) { - mmu_idx |= ARM_MMU_IDX_M_S; - } - - return mmu_idx; -} +ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, + bool secstate, bool priv); /* Return the MMU index for a v7M CPU in the specified security state */ -static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, - bool secstate) -{ - bool priv = arm_current_el(env) != 0; - - return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); -} +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); /* Determine the current mmu_idx to use for normal loads/stores */ -static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) -{ - int el = arm_current_el(env); - - if (arm_feature(env, ARM_FEATURE_M)) { - ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); - - return arm_to_core_mmu_idx(mmu_idx); - } - - if (el < 2 && arm_is_secure_below_el3(env)) { - return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); - } - return el; -} +int cpu_mmu_index(CPUARMState *env, bool ifetch); /* Indexes used when registering address spaces with cpu_address_space_init */ typedef enum ARMASIdx { diff --git a/target/arm/helper.c b/target/arm/helper.c index f23555b1dc..56d0b60b74 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12949,6 +12949,50 @@ int fp_exception_el(CPUARMState *env, int cur_el) return 0; } +ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, + bool secstate, bool priv) +{ + ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; + + if (priv) { + mmu_idx |= ARM_MMU_IDX_M_PRIV; + } + + if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) { + mmu_idx |= ARM_MMU_IDX_M_NEGPRI; + } + + if (secstate) { + mmu_idx |= ARM_MMU_IDX_M_S; + } + + return mmu_idx; +} + +/* Return the MMU index for a v7M CPU in the specified security state */ +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) +{ + bool priv = arm_current_el(env) != 0; + + return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); +} + +int cpu_mmu_index(CPUARMState *env, bool ifetch) +{ + int el = arm_current_el(env); + + if (arm_feature(env, ARM_FEATURE_M)) { + ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); + + return arm_to_core_mmu_idx(mmu_idx); + } + + if (el < 2 && arm_is_secure_below_el3(env)) { + return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); + } + return el; +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { From patchwork Tue Jan 8 22:31:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155022 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp39617jaa; Tue, 8 Jan 2019 14:44:03 -0800 (PST) X-Google-Smtp-Source: ALg8bN5xzjacVhVMNbWgJSmV77QUIKFmr+sJuUcPrGnnE+4WRzy56io7JChiQqve3rx1BqVuCXjq X-Received: by 2002:a1c:5f8a:: with SMTP id t132mr3316308wmb.40.1546987443145; Tue, 08 Jan 2019 14:44:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546987443; cv=none; d=google.com; s=arc-20160816; b=NKheYnMS9rmso7mIwyXxr0AQFgWS65CB9N7dSvbLk3pSkS/fnqdmn/7W/zsDdOEEkd t1xHR0qZdc08F6m8z6SMDXgrmclC4AK+UiOntfbgBxDLAfiSqsi30gAlpckLHW5rarPl jn/vAsYKvUMHYN6ARJY427rAifum04V39q2j5VlyNSpX72rmaqLluGXQh7jXAYXS3sKk w5D5I9iwkhP63crbufSPbo7Xj24aXbenW/LBycTbUYZzz6bLdP4n2Y7aqlB0BDRDeHU9 rITTvhtueOnMY4AIuJEVuO7Vd0NOuriU2l9MCxTzkVK3JbvJElKk+PcTBRIUuSWY0Cwg w8Aw== ARC-Message-Signature: i=1; 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:14 +1000 Message-Id: <20190108223129.5570-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 16/31] target/arm: Introduce arm_mmu_idx X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The pattern ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); is computing the full ARMMMUIdx, stripping off the ARM bits, and then putting them back. Avoid the extra two steps with the appropriate helper function. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson ---- v2: Move arm_mmu_idx declaration to internals.h. --- target/arm/cpu.h | 9 ++++++++- target/arm/internals.h | 8 ++++++++ target/arm/helper.c | 27 ++++++++++++++++----------- 3 files changed, 32 insertions(+), 12 deletions(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index eb83a71b67..c1d511f274 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2749,7 +2749,14 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, /* Return the MMU index for a v7M CPU in the specified security state */ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); -/* Determine the current mmu_idx to use for normal loads/stores */ +/** + * cpu_mmu_index: + * @env: The cpu environment + * @ifetch: True for code access, false for data access. + * + * Return the core mmu index for the current translation regime. + * This function is used by generic TCG code paths. + */ int cpu_mmu_index(CPUARMState *env, bool ifetch); /* Indexes used when registering address spaces with cpu_address_space_init */ diff --git a/target/arm/internals.h b/target/arm/internals.h index 0ed20c03cc..89f3b122a4 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -919,4 +919,12 @@ void arm_cpu_update_virq(ARMCPU *cpu); */ void arm_cpu_update_vfiq(ARMCPU *cpu); +/** + * arm_mmu_idx: + * @env: The cpu environment + * + * Return the full ARMMMUIdx for the current translation regime. + */ +ARMMMUIdx arm_mmu_idx(CPUARMState *env); + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index 56d0b60b74..ba6733c4f1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7117,7 +7117,7 @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain, limit = env->v7m.msplim[M_REG_S]; } } else { - mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); + mmu_idx = arm_mmu_idx(env); frame_sp_p = &env->regs[13]; limit = v7m_sp_limit(env); } @@ -7298,7 +7298,7 @@ static bool v7m_push_stack(ARMCPU *cpu) CPUARMState *env = &cpu->env; uint32_t xpsr = xpsr_read(env); uint32_t frameptr = env->regs[13]; - ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); + ARMMMUIdx mmu_idx = arm_mmu_idx(env); /* Align stack pointer if the guest wants that */ if ((frameptr & 4) && @@ -11073,7 +11073,7 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, int prot; bool ret; ARMMMUFaultInfo fi = {}; - ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); + ARMMMUIdx mmu_idx = arm_mmu_idx(env); *attrs = (MemTxAttrs) {}; @@ -12977,26 +12977,31 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); } -int cpu_mmu_index(CPUARMState *env, bool ifetch) +ARMMMUIdx arm_mmu_idx(CPUARMState *env) { - int el = arm_current_el(env); + int el; if (arm_feature(env, ARM_FEATURE_M)) { - ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); - - return arm_to_core_mmu_idx(mmu_idx); + return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); } + el = arm_current_el(env); if (el < 2 && arm_is_secure_below_el3(env)) { - return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); + return ARMMMUIdx_S1SE0 + el; + } else { + return ARMMMUIdx_S12NSE0 + el; } - return el; +} + +int cpu_mmu_index(CPUARMState *env, bool ifetch) +{ + return arm_to_core_mmu_idx(arm_mmu_idx(env)); } void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { - ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); + ARMMMUIdx mmu_idx = arm_mmu_idx(env); int current_el = arm_current_el(env); int fp_el = fp_exception_el(env, current_el); uint32_t flags = 0; From patchwork Tue Jan 8 22:31:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155030 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp44268jaa; Tue, 8 Jan 2019 14:50:23 -0800 (PST) X-Google-Smtp-Source: ALg8bN6c+oH95YujtP6wiGtLsmX5yTPUROJDtCH7PS34WVOqsVYIqB3uFUnybFHdVJAzLjIXE65T X-Received: by 2002:a1c:cc2:: with SMTP id 185mr3309625wmm.1.1546987823808; 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:15 +1000 Message-Id: <20190108223129.5570-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v3 17/31] target/arm: Introduce arm_stage1_mmu_idx X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" While we could expose stage_1_mmu_idx, the combination is probably going to be more useful. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 15 +++++++++++++++ target/arm/helper.c | 7 +++++++ 2 files changed, 22 insertions(+) -- 2.17.2 diff --git a/target/arm/internals.h b/target/arm/internals.h index 89f3b122a4..248fdf7a3c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -927,4 +927,19 @@ void arm_cpu_update_vfiq(ARMCPU *cpu); */ ARMMMUIdx arm_mmu_idx(CPUARMState *env); +/** + * arm_stage1_mmu_idx: + * @env: The cpu environment + * + * Return the ARMMMUIdx for the stage1 traversal for the current regime. + */ +#ifdef CONFIG_USER_ONLY +static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) +{ + return ARMMMUIdx_S1NSE0; +} +#else +ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); +#endif + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index ba6733c4f1..4af8abd18f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12998,6 +12998,13 @@ int cpu_mmu_index(CPUARMState *env, bool ifetch) return arm_to_core_mmu_idx(arm_mmu_idx(env)); } +#ifndef CONFIG_USER_ONLY +ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) +{ + return stage_1_mmu_idx(arm_mmu_idx(env)); +} +#endif + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { From patchwork Tue Jan 8 22:31:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155024 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp39955jaa; Tue, 8 Jan 2019 14:44:31 -0800 (PST) X-Google-Smtp-Source: ALg8bN61VAXc7tJRgDa/7rj1KL9bG8DC/09WuayvG0BBt96VODEU+KgVsEtlVrFASFJvpW13jCHD X-Received: by 2002:a5d:444a:: with SMTP id x10mr1164241wrr.162.1546987471791; Tue, 08 Jan 2019 14:44:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546987471; cv=none; d=google.com; s=arc-20160816; b=RGC9+xCKmR6P1dU4YAKKBlXP3ANOp54Ho0nyix4aReBXzuZZInt39A1cqGlDqmgmmp 1+PEV7+lMxbrtWIuOyZ4wWGLgVHLI+O0BOSF8NVsba9ulQCOAxZhRPlN0ZAb38DpQh15 waOG+SIj5ovTVT0Ug874VrcaUxunZqEVtjCqnHPeKmcHBEXTTZMF6IbzLvilRYsfwe9Y /ydkbYMKiX/01soy6677WXoOwa6lF3Pe0FeAfBSybMrf+AH69oEl2laAsBXMQohVt/yT gCFvoVkb5lI1WdxsM1aTnQB3LMs3WyHRlHBaT6b32KA987Ah5Xj76/aDQ/29aJ+qX/8G 7YSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=5Y1f2Ah2ro2iLFV8pn6+8bjx8cENN0ztZ1gZEE2M3yw=; b=rpB7JJ/VCeJgd4dqguURbzXeT8iYRA9m2OLYXEwoq6gmEYAXxNDtIc/6Sm6R6tZ+Ky rUETKsHuAZO2TSWrrRTZEGjkMjYiMLqhtqoBJo06ZTx+1E1rx9PdB2t6KrCiFXfiJaM2 iqQAb0Md3fzoC8Yde+2OfhjmRQnOmJqsFimhWYDU2GsOFqJY40BjLFJ+C3iMvHWmrXZq T+6qAMIS0KUYHNbT1eOdjH+NV/A4UIjxtLxFaQdoAWRJ9RnfgJ7hAgVnAsKTETpk1ZEF pi31MI1ng8EY226NJPgl9sPyqQzTQqbB2HmNU+E0qMmqmb12oNnr8Vysh17iMVhwPo9L nJ5A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=E4zDDBox; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:16 +1000 Message-Id: <20190108223129.5570-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v3 18/31] target/arm: Create ARMVAParameters and helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split out functions to extract the virtual address parameters. Let the functions choose T0 or T1 address space half, if present. Extract (most of) the control bits that vary between EL or Tx. Signed-off-by: Richard Henderson ---- v2: Incorporate feedback wrt VTCR, HTCR, and more. v3: Remove TBID, HA, HD from this patch. --- target/arm/internals.h | 14 +++ target/arm/helper.c | 275 ++++++++++++++++++++++------------------- 2 files changed, 161 insertions(+), 128 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/internals.h b/target/arm/internals.h index 248fdf7a3c..fdda2c866a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -942,4 +942,18 @@ static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); #endif +/* + * Parameters of a given virtual address, as extracted from the + * translation control register (TCR) for a given regime. + */ +typedef struct ARMVAParameters { + unsigned tsz : 8; + unsigned select : 1; + bool tbi : 1; + bool epd : 1; + bool hpd : 1; + bool using16k : 1; + bool using64k : 1; +} ARMVAParameters; + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index 4af8abd18f..5ee8761111 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9744,6 +9744,122 @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; } +static ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, + ARMMMUIdx mmu_idx, bool data) +{ + uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; + uint32_t el = regime_el(env, mmu_idx); + bool tbi, epd, hpd, using16k, using64k; + int select, tsz; + + /* Bit 55 is always between the two regions, and is canonical for + * determining if address tagging is enabled. + */ + select = extract64(va, 55, 1); + + if (el > 1) { + tsz = extract32(tcr, 0, 6); + using64k = extract32(tcr, 14, 1); + using16k = extract32(tcr, 15, 1); + if (mmu_idx == ARMMMUIdx_S2NS) { + /* VTCR_EL2 */ + tbi = hpd = false; + } else { + tbi = extract32(tcr, 20, 1); + hpd = extract32(tcr, 24, 1); + } + epd = false; + } else if (!select) { + tsz = extract32(tcr, 0, 6); + epd = extract32(tcr, 7, 1); + using64k = extract32(tcr, 14, 1); + using16k = extract32(tcr, 15, 1); + tbi = extract64(tcr, 37, 1); + hpd = extract64(tcr, 41, 1); + } else { + int tg = extract32(tcr, 30, 2); + using16k = tg == 1; + using64k = tg == 3; + tsz = extract32(tcr, 16, 6); + epd = extract32(tcr, 23, 1); + tbi = extract64(tcr, 38, 1); + hpd = extract64(tcr, 42, 1); + } + tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ + tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ + + return (ARMVAParameters) { + .tsz = tsz, + .select = select, + .tbi = tbi, + .epd = epd, + .hpd = hpd, + .using16k = using16k, + .using64k = using64k, + }; +} + +static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, + ARMMMUIdx mmu_idx) +{ + uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; + uint32_t el = regime_el(env, mmu_idx); + int select, tsz; + bool epd, hpd; + + if (mmu_idx == ARMMMUIdx_S2NS) { + /* VTCR */ + bool sext = extract32(tcr, 4, 1); + bool sign = extract32(tcr, 3, 1); + + /* If the sign-extend bit is not the same as t0sz[3], the result + * is unpredictable. Flag this as a guest error. + */ + if (sign != sext) { + qemu_log_mask(LOG_GUEST_ERROR, + "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n"); + } + tsz = sextract32(tcr, 0, 4) + 8; + select = 0; + hpd = false; + epd = false; + } else if (el == 2) { + /* HTCR */ + tsz = extract32(tcr, 0, 3); + select = 0; + hpd = extract64(tcr, 24, 1); + epd = false; + } else { + int t0sz = extract32(tcr, 0, 3); + int t1sz = extract32(tcr, 16, 3); + + if (t1sz == 0) { + select = va > (0xffffffffu >> t0sz); + } else { + /* Note that we will detect errors later. */ + select = va >= ~(0xffffffffu >> t1sz); + } + if (!select) { + tsz = t0sz; + epd = extract32(tcr, 7, 1); + hpd = extract64(tcr, 41, 1); + } else { + tsz = t1sz; + epd = extract32(tcr, 23, 1); + hpd = extract64(tcr, 42, 1); + } + /* For aarch32, hpd0 is not enabled without t2e as well. */ + hpd &= extract32(tcr, 6, 1); + } + + return (ARMVAParameters) { + .tsz = tsz, + .select = select, + .epd = epd, + .hpd = hpd, + }; +} + static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, @@ -9755,26 +9871,20 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, /* Read an LPAE long-descriptor translation table. */ ARMFaultType fault_type = ARMFault_Translation; uint32_t level; - uint32_t epd = 0; - int32_t t0sz, t1sz; - uint32_t tg; + ARMVAParameters param; uint64_t ttbr; - int ttbr_select; hwaddr descaddr, indexmask, indexmask_grainsize; uint32_t tableattrs; - target_ulong page_size; + target_ulong page_size, top_bits; uint32_t attrs; - int32_t stride = 9; - int32_t addrsize; - int inputsize; - int32_t tbi = 0; + int32_t stride; + int addrsize, inputsize; TCR *tcr = regime_tcr(env, mmu_idx); int ap, ns, xn, pxn; uint32_t el = regime_el(env, mmu_idx); - bool ttbr1_valid = true; + bool ttbr1_valid; uint64_t descaddrmask; bool aarch64 = arm_el_is_aa64(env, el); - bool hpd = false; /* TODO: * This code does not handle the different format TCR for VTCR_EL2. @@ -9783,91 +9893,43 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, * support for those page table walks. */ if (aarch64) { + param = aa64_va_parameters(env, address, mmu_idx, + access_type != MMU_INST_FETCH); level = 0; - addrsize = 64; - if (el > 1) { - if (mmu_idx != ARMMMUIdx_S2NS) { - tbi = extract64(tcr->raw_tcr, 20, 1); - } - } else { - if (extract64(address, 55, 1)) { - tbi = extract64(tcr->raw_tcr, 38, 1); - } else { - tbi = extract64(tcr->raw_tcr, 37, 1); - } - } - tbi *= 8; - /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it * invalid. */ - if (el > 1) { - ttbr1_valid = false; - } + ttbr1_valid = (el < 2); + addrsize = 64 - 8 * param.tbi; + inputsize = 64 - param.tsz; } else { + param = aa32_va_parameters(env, address, mmu_idx); level = 1; - addrsize = 32; /* There is no TTBR1 for EL2 */ - if (el == 2) { - ttbr1_valid = false; - } + ttbr1_valid = (el != 2); + addrsize = (mmu_idx == ARMMMUIdx_S2NS ? 40 : 32); + inputsize = addrsize - param.tsz; } - /* Determine whether this address is in the region controlled by - * TTBR0 or TTBR1 (or if it is in neither region and should fault). - * This is a Non-secure PL0/1 stage 1 translation, so controlled by - * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32: + /* We determined the region when collecting the parameters, but we + * have not yet validated that the address is valid for the region. + * Extract the top bits and verify that they all match select. */ - if (aarch64) { - /* AArch64 translation. */ - t0sz = extract32(tcr->raw_tcr, 0, 6); - t0sz = MIN(t0sz, 39); - t0sz = MAX(t0sz, 16); - } else if (mmu_idx != ARMMMUIdx_S2NS) { - /* AArch32 stage 1 translation. */ - t0sz = extract32(tcr->raw_tcr, 0, 3); - } else { - /* AArch32 stage 2 translation. */ - bool sext = extract32(tcr->raw_tcr, 4, 1); - bool sign = extract32(tcr->raw_tcr, 3, 1); - /* Address size is 40-bit for a stage 2 translation, - * and t0sz can be negative (from -8 to 7), - * so we need to adjust it to use the TTBR selecting logic below. - */ - addrsize = 40; - t0sz = sextract32(tcr->raw_tcr, 0, 4) + 8; - - /* If the sign-extend bit is not the same as t0sz[3], the result - * is unpredictable. Flag this as a guest error. */ - if (sign != sext) { - qemu_log_mask(LOG_GUEST_ERROR, - "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n"); - } - } - t1sz = extract32(tcr->raw_tcr, 16, 6); - if (aarch64) { - t1sz = MIN(t1sz, 39); - t1sz = MAX(t1sz, 16); - } - if (t0sz && !extract64(address, addrsize - t0sz, t0sz - tbi)) { - /* there is a ttbr0 region and we are in it (high bits all zero) */ - ttbr_select = 0; - } else if (ttbr1_valid && t1sz && - !extract64(~address, addrsize - t1sz, t1sz - tbi)) { - /* there is a ttbr1 region and we are in it (high bits all one) */ - ttbr_select = 1; - } else if (!t0sz) { - /* ttbr0 region is "everything not in the ttbr1 region" */ - ttbr_select = 0; - } else if (!t1sz && ttbr1_valid) { - /* ttbr1 region is "everything not in the ttbr0 region" */ - ttbr_select = 1; - } else { - /* in the gap between the two regions, this is a Translation fault */ + top_bits = sextract64(address, inputsize, addrsize - inputsize); + if (-top_bits != param.select || (param.select && !ttbr1_valid)) { + /* In the gap between the two regions, this is a Translation fault */ fault_type = ARMFault_Translation; goto do_fault; } + if (param.using64k) { + stride = 13; + } else if (param.using16k) { + stride = 11; + } else { + stride = 9; + } + /* Note that QEMU ignores shareability and cacheability attributes, * so we don't need to do anything with the SH, ORGN, IRGN fields * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the @@ -9875,56 +9937,13 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, * implement any ASID-like capability so we can ignore it (instead * we will always flush the TLB any time the ASID is changed). */ - if (ttbr_select == 0) { - ttbr = regime_ttbr(env, mmu_idx, 0); - if (el < 2) { - epd = extract32(tcr->raw_tcr, 7, 1); - } - inputsize = addrsize - t0sz; - - tg = extract32(tcr->raw_tcr, 14, 2); - if (tg == 1) { /* 64KB pages */ - stride = 13; - } - if (tg == 2) { /* 16KB pages */ - stride = 11; - } - if (aarch64 && el > 1) { - hpd = extract64(tcr->raw_tcr, 24, 1); - } else { - hpd = extract64(tcr->raw_tcr, 41, 1); - } - if (!aarch64) { - /* For aarch32, hpd0 is not enabled without t2e as well. */ - hpd &= extract64(tcr->raw_tcr, 6, 1); - } - } else { - /* We should only be here if TTBR1 is valid */ - assert(ttbr1_valid); - - ttbr = regime_ttbr(env, mmu_idx, 1); - epd = extract32(tcr->raw_tcr, 23, 1); - inputsize = addrsize - t1sz; - - tg = extract32(tcr->raw_tcr, 30, 2); - if (tg == 3) { /* 64KB pages */ - stride = 13; - } - if (tg == 1) { /* 16KB pages */ - stride = 11; - } - hpd = extract64(tcr->raw_tcr, 42, 1); - if (!aarch64) { - /* For aarch32, hpd1 is not enabled without t2e as well. */ - hpd &= extract64(tcr->raw_tcr, 6, 1); - } - } + ttbr = regime_ttbr(env, mmu_idx, param.select); /* Here we should have set up all the parameters for the translation: * inputsize, ttbr, epd, stride, tbi */ - if (epd) { + if (param.epd) { /* Translation table walk disabled => Translation fault on TLB miss * Note: This is always 0 on 64-bit EL2 and EL3. */ @@ -10037,7 +10056,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, } /* Merge in attributes from table descriptors */ attrs |= nstable << 3; /* NS */ - if (hpd) { + if (param.hpd) { /* HPD disables all the table attributes except NSTable. */ break; } From patchwork Tue Jan 8 22:31:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155032 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp46507jaa; Tue, 8 Jan 2019 14:53:29 -0800 (PST) X-Google-Smtp-Source: ALg8bN5dfL/Kn9N1Z/Oe7BLAqr2/WxPwwVDSxH3xs2gCFtppvY71iXURGV8jaZN6SlJrOyVdz5dv X-Received: by 2002:a1c:570d:: with SMTP id l13mr3306979wmb.139.1546988008985; Tue, 08 Jan 2019 14:53:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546988008; cv=none; d=google.com; s=arc-20160816; b=xoWCzgW9L6FQyFOTMRxjzKxn+wRvzoJLuBX0g1Ln9oBnaEab1bq2/RaUmvAdaE49OG 8tHD9xsNnhMQGFZPXWe8j/gY2FMOJSy6VTzmb+ozMdMeTXrGhXOEWcpcI2cRsjDxmh1w 4En3CHgDvstWjKmBLDvCvMJ4I3rFOIeXCA8I4EBNnjOBOKSpMcVp8Kv5j6ojjQDYW0Jo F8g1bvsE71hX6Xsy2oegGGZ5Ei02bCjAmzzt2q2REmBqJ5emRjfKU2wTlsXF1faLwiR/ 6zS/k4CJpXbCMpg6pBJv+jp4BUnX2NniDqFHViih7z3jEhZrV5U7dSX5UCSyCW7ZK25T lRbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=wmwmyBe+39serfWjlr1w69S1eK6hJM8LpCs3XyG58Yg=; b=PZ/0WqweMkCppG0RCRq23+tn7ZQ7doiNHpN9eJKVPveyPO5bPm0z5UYqbgzfPHKvJc itpvCFM8Ii3DvpvDsSArg6qEob8zMsIJMkXZcx1zdQRftvvFboqODU2jF2b/wrFEsrLU 75yu1di5qzWORN2sdOVIaGmE8mWcCVKMXxwgsAm5mv0xuuT5Uf3H89oHN5p0r+tJAgzk tDKvE6eOSB3mkeSRocukb9FNhBO+G+yJNMIk3k6Jum0OBTN8CHBaPEXH2N8zU8z72AP2 ZWx2czcyVnC5DJ3odYZ5YHbJsNSLGZBVaWaIflCXqs9ckU+58zPayoAviZkqueE47gFq nKBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HEM+oTc4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:17 +1000 Message-Id: <20190108223129.5570-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 19/31] target/arm: Merge TBFLAG_AA_TB{0, 1} to TBII X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will shortly want to talk about TBI as it relates to data. Passing around a pair of variables is less convenient than a single variable. Signed-off-by: Richard Henderson ---- v3: New, split out of a later patch set. --- target/arm/cpu.h | 3 +-- target/arm/translate.h | 3 +-- target/arm/helper.c | 5 ++--- target/arm/translate-a64.c | 13 +++++++------ 4 files changed, 11 insertions(+), 13 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c1d511f274..ea9b8ec4a1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2979,8 +2979,7 @@ FIELD(TBFLAG_A32, HANDLER, 21, 1) FIELD(TBFLAG_A32, STACKCHECK, 22, 1) /* Bit usage when in AArch64 state */ -FIELD(TBFLAG_A64, TBI0, 0, 1) -FIELD(TBFLAG_A64, TBI1, 1, 1) +FIELD(TBFLAG_A64, TBII, 0, 2) FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) diff --git a/target/arm/translate.h b/target/arm/translate.h index d8a8bb4e9c..bb37d35741 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -26,8 +26,7 @@ typedef struct DisasContext { int user; #endif ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */ - bool tbi0; /* TBI0 for EL0/1 or TBI for EL2/3 */ - bool tbi1; /* TBI1 for EL0/1, not used for EL2/3 */ + uint8_t tbii; /* TBI1|TBI0 for EL0/1 or TBI for EL2/3 */ bool ns; /* Use non-secure CPREG bank on access */ int fp_excp_el; /* FP exception EL or 0 if enabled */ int sve_excp_el; /* SVE exception EL or 0 if enabled */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 5ee8761111..f934c80c28 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13038,10 +13038,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, *pc = env->pc; flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); /* Get control bits for tagged addresses */ - flags = FIELD_DP32(flags, TBFLAG_A64, TBI0, + flags = FIELD_DP32(flags, TBFLAG_A64, TBII, + (arm_regime_tbi1(env, mmu_idx) << 1) | arm_regime_tbi0(env, mmu_idx)); - flags = FIELD_DP32(flags, TBFLAG_A64, TBI1, - arm_regime_tbi1(env, mmu_idx)); if (cpu_isar_feature(aa64_sve, cpu)) { int sve_el = sve_exception_el(env, current_el); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a4dfdf5836..ee92533469 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -276,13 +276,15 @@ void gen_a64_set_pc_im(uint64_t val) */ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) { + /* Note that TBII is TBI1:TBI0. */ + int tbi = s->tbii; if (s->current_el <= 1) { /* Test if NEITHER or BOTH TBI values are set. If so, no need to * examine bit 55 of address, can just generate code. * If mixed, then test via generated code */ - if (s->tbi0 && s->tbi1) { + if (tbi == 3) { TCGv_i64 tmp_reg = tcg_temp_new_i64(); /* Both bits set, sign extension from bit 55 into [63:56] will * cover both cases @@ -290,7 +292,7 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) tcg_gen_shli_i64(tmp_reg, src, 8); tcg_gen_sari_i64(cpu_pc, tmp_reg, 8); tcg_temp_free_i64(tmp_reg); - } else if (!s->tbi0 && !s->tbi1) { + } else if (tbi == 0) { /* Neither bit set, just load it as-is */ tcg_gen_mov_i64(cpu_pc, src); } else { @@ -300,7 +302,7 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) tcg_gen_andi_i64(tcg_bit55, src, (1ull << 55)); - if (s->tbi0) { + if (tbi == 1) { /* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */ tcg_gen_andi_i64(tcg_tmpval, src, 0x00FFFFFFFFFFFFFFull); @@ -318,7 +320,7 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) tcg_temp_free_i64(tcg_tmpval); } } else { /* EL > 1 */ - if (s->tbi0) { + if (tbi != 0) { /* Force tag byte to all zero */ tcg_gen_andi_i64(cpu_pc, src, 0x00FFFFFFFFFFFFFFull); } else { @@ -13806,8 +13808,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->condexec_cond = 0; core_mmu_idx = FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); dc->mmu_idx = core_to_arm_mmu_idx(env, core_mmu_idx); - dc->tbi0 = FIELD_EX32(tb_flags, TBFLAG_A64, TBI0); - dc->tbi1 = FIELD_EX32(tb_flags, TBFLAG_A64, TBI1); + dc->tbii = FIELD_EX32(tb_flags, TBFLAG_A64, TBII); dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user = (dc->current_el == 0); From patchwork Tue Jan 8 22:31:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155027 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp42568jaa; Tue, 8 Jan 2019 14:48:07 -0800 (PST) X-Google-Smtp-Source: ALg8bN7NH2Yf1xrYj1Cj2i+mRzmN5f2pUXU0cPIVpiDCOR0AvhL9Mi2ODCBFIe2biUo5QwM7lMuS X-Received: by 2002:a1c:f613:: with SMTP id w19mr3193839wmc.0.1546987687744; Tue, 08 Jan 2019 14:48:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546987687; cv=none; d=google.com; s=arc-20160816; b=UklG4d/W1BUgzTR82PUG73eTROZHpVJczq3FK2dk4vLy0oQ66H5Nvebu5FyIoLFrqg CDunFyOK9FFN24rpgD9RIjkjnIA1Y0D9V2BUbvOurQayC3dU3LSPnIHFUAq7a3zzJuaA XuruJnj1mcBVRcRLW7nd6xCY73EcPtNfyojJKMcJbdOaWSsUnSphjtwMpnxC5qp31qLo fgKMfHG9nZv15QE1c0oEpMpKVK27yivQHpMTUn4Nksk2aWYI01EB7NElfBdRujVyX7rv UD/4o+SGeg6MpAZKNBwXgimYkEfpuUDUqCTV1TwctB9XtEan9AhNpEAjP07DuqgWSxbz XALg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=HtgD2kb0Tk4a5mvvgc/yTa4iLNXqbugMtAKVtQjNC/Y=; b=nuWxSYtgbqySOYkIM8gfk1B58a5cxkT7MEx8fV/f/5rgBQAiEgbc4OK4ckmi0rntzq lN3YhD0Bg5dWvSXgxyOqPGKt4bHTpqKYodjvtQKpWA39KyZzm2QwOxUAugqtbvAMOm7I bMEN5QsIE8jmw4KOfGBehLdmGItkcBrUrNdL7sSENRb1QiiEUHSnOFRYFOn8K8QUgjXS 4KbCES9s1GwHVHe5Ojmy5j1S1PouT0ekBw4nkLOnNmzuhxGTb+sVP+jZhyINj3mpQm4a +7faHAexS4vyVZdC7JxHNjlyhA5YPTr31viEy9o+5W7nPnmsTK23blB4LXhQsornZVkM +2sA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="W/gcyjNT"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:18 +1000 Message-Id: <20190108223129.5570-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v3 20/31] target/arm: Export aa64_va_parameters to internals.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We need to reuse this from helper-a64.c. Provide a stub definition for CONFIG_USER_ONLY. This matches the stub definitions that we removed for arm_regime_tbi{0,1} before. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 17 +++++++++++++++++ target/arm/helper.c | 4 ++-- 2 files changed, 19 insertions(+), 2 deletions(-) -- 2.17.2 diff --git a/target/arm/internals.h b/target/arm/internals.h index fdda2c866a..82cf685695 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -956,4 +956,21 @@ typedef struct ARMVAParameters { bool using64k : 1; } ARMVAParameters; +#ifdef CONFIG_USER_ONLY +static inline ARMVAParameters aa64_va_parameters(CPUARMState *env, + uint64_t va, + ARMMMUIdx mmu_idx, bool data) +{ + return (ARMVAParameters) { + /* 48-bit address space */ + .tsz = 16, + /* We can't handle tagged addresses properly in user-only mode */ + .tbi = false, + }; +} +#else +ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, + ARMMMUIdx mmu_idx, bool data); +#endif + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index f934c80c28..f4538c9f82 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9744,8 +9744,8 @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; } -static ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, - ARMMMUIdx mmu_idx, bool data) +ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, + ARMMMUIdx mmu_idx, bool data) { uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; uint32_t el = regime_el(env, mmu_idx); From patchwork Tue Jan 8 22:31:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155035 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp48550jaa; Tue, 8 Jan 2019 14:56:28 -0800 (PST) X-Google-Smtp-Source: ALg8bN5/evzdb7/sLGRPxlc+i/Lx8KsR+Y0mLIYKJm3Z2+CnxhCDvBSXPMRQpFLe+7wuh/teLE15 X-Received: by 2002:a5d:4652:: with SMTP id j18mr2921611wrs.279.1546988188578; Tue, 08 Jan 2019 14:56:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546988188; cv=none; d=google.com; s=arc-20160816; b=XoAxdlX5ojVPfsaQ10nBUXkSAmBpCuSk4nLuOwFHh2nBujgTY/0m2u+U/gNW3whSE1 X4kOWLuqvpWCFGo5jGVZvAIEiiAAXylkTkB4WDu1Gauc/+xN92uyv1g11PjyFEF6dU1M N6kS76TXoMjnlOPrpqWUL2QCV0mhl0J7bZ7wrUBrGBBUHzaFi/FAR/SYNq3w6yl5AnLH p+OMFWzSIzrJWTtMAsbBWZr1mvm4Df2A+FRfV06iZW4gUPJ5x1aVXMKkM8aq0jQGAsMq w6VSfwhOjwGqKvuaIVGO5K0/D6RBGtP4d9+cn0IIM8M/vSUzRJ+KYbS6qhQdxkhh9+k/ K+TQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=Jm0q4VrYesXT+1aKV7gHpLk65YgMU1hEIfu+1DhEv/c=; b=XnEYAYSzjgnJV8fcobvUbT4qs+3MpjrrkshNMSXqp/eIQSDf90KTtEW77RzDjSdpJR pGKT8pHBKDts7140mjfdRVoaeIFv5Ivu9SKJNBi1smOuVwGc8l6ujzrLI48zsslsEKIw WjbAdh2rXjB+xzTOhMMnPAnBKzhtuirRvcN99GZ0l6Wh2QuBnq3XYBl9pC1kAurbneZ2 f/ypvjToBEPvHOk9K2XyOs9i+vo3XAk/kEU3vbg3K7e9KOotbd2JxptDvgxMpx/o/pUs D0rDNuvta1Q/KKwkWosD3TAmmxc7EpLxmZ7WEOHfBDq/bvtBpM1VFq9g7hoajmvG0bTO mhiw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WMtx8eMW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:19 +1000 Message-Id: <20190108223129.5570-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 21/31] target/arm: Add aa64_va_parameters_both X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will want to check TBI for I and D simultaneously. Signed-off-by: Richard Henderson --- target/arm/internals.h | 15 ++++++++++++--- target/arm/helper.c | 10 ++++++++-- 2 files changed, 20 insertions(+), 5 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/internals.h b/target/arm/internals.h index 82cf685695..acd99b579c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -957,9 +957,9 @@ typedef struct ARMVAParameters { } ARMVAParameters; #ifdef CONFIG_USER_ONLY -static inline ARMVAParameters aa64_va_parameters(CPUARMState *env, - uint64_t va, - ARMMMUIdx mmu_idx, bool data) +static inline ARMVAParameters aa64_va_parameters_both(CPUARMState *env, + uint64_t va, + ARMMMUIdx mmu_idx) { return (ARMVAParameters) { /* 48-bit address space */ @@ -968,7 +968,16 @@ static inline ARMVAParameters aa64_va_parameters(CPUARMState *env, .tbi = false, }; } + +static inline ARMVAParameters aa64_va_parameters(CPUARMState *env, + uint64_t va, + ARMMMUIdx mmu_idx, bool data) +{ + return aa64_va_parameters_both(env, va, mmu_idx); +} #else +ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, + ARMMMUIdx mmu_idx); ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data); #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index f4538c9f82..28322ae109 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9744,8 +9744,8 @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; } -ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, - ARMMMUIdx mmu_idx, bool data) +ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, + ARMMMUIdx mmu_idx) { uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; uint32_t el = regime_el(env, mmu_idx); @@ -9799,6 +9799,12 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, }; } +ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, + ARMMMUIdx mmu_idx, bool data) +{ + return aa64_va_parameters_both(env, va, mmu_idx); +} + static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, ARMMMUIdx mmu_idx) { From patchwork Tue Jan 8 22:31:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155039 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp50455jaa; Tue, 8 Jan 2019 14:59:18 -0800 (PST) X-Google-Smtp-Source: ALg8bN7VYMaZsyEeIQFB4pZ4QZUCvWyER83w1DRJSV0BpCd8SpEtalWq4iT78J5G3z3xxRuMDMB3 X-Received: by 2002:a1c:9dc4:: with SMTP id g187mr3319999wme.152.1546988358091; Tue, 08 Jan 2019 14:59:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546988358; cv=none; d=google.com; s=arc-20160816; b=INjFm++Fq3ZO7H0nD2aKjHusFg6JIVCc5NxkKofHrsEpI8nQh092IfpBNUt04NvyB7 zjo0nIZiFTvLH3ldALvb79NSseh9J6JjGmigv16eWnlinDVItDSV6H7SyDHjzuNPnJrI b6/qdSSYaemhAFN/7vFVp/YuwwhNojVut1AHtqePGqHNW8FkUpRoguj3GjAoQ+y0ZUg8 1s/v2Qzb2VgJt0HshXBqXl484APfblTEpZuvT8h41iytf1IwRq4ihC1iB0ujbDaUKr/S FXoy+bi3MDWYWAkTJSIGKkz9Sd7UAjeJJ0a96hHofMs9dIfSC6LAYBrukBIcsysatItQ U+DA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=Y+pdCEdbsU3nNMbRtt2E6v/yS6MnA/Ob8unhe6A5OEI=; b=FVgKxlZKfyk93bGgFwsV9KLaxKqRloUbwyfx5mXLTAr1OtLBl4PQtBvw6nrKpAYbyr +sphNAHT4/pCARfXbkIF6Vw8xhRe3gLN4wqKRV64j9LKKSZrK555bJD0oo5M7eHNoCSF ziiKoDJvE3JEO1HE6wT0joRzYRebG4mvOU3IeI8jPiaF/iZWW3WruafUdMXyctMXg3WF 9GBl43+uJJakJg5fd6c2p9WBSiou5Xhj9QIUYwzXM/Yar+rVFOqDsGi8OUfi56p1aV0o S6IdtXM3ynN1bImjSSj7rrFZG/FfKXMCg6sUfjv8gvansiJgU26a9t7GN19FwmlOhnou c+hQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="D/9zyi+k"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:20 +1000 Message-Id: <20190108223129.5570-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3 22/31] target/arm: Decode TBID from TCR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use TBID in aa64_va_parameters depending on the data parameter. This automatically updates all existing users of the function. Signed-off-by: Richard Henderson --- target/arm/internals.h | 1 + target/arm/helper.c | 14 +++++++++++--- 2 files changed, 12 insertions(+), 3 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/internals.h b/target/arm/internals.h index acd99b579c..a6fd4582b2 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -950,6 +950,7 @@ typedef struct ARMVAParameters { unsigned tsz : 8; unsigned select : 1; bool tbi : 1; + bool tbid : 1; bool epd : 1; bool hpd : 1; bool using16k : 1; diff --git a/target/arm/helper.c b/target/arm/helper.c index 28322ae109..cc3c0d47c8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9749,7 +9749,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, { uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; uint32_t el = regime_el(env, mmu_idx); - bool tbi, epd, hpd, using16k, using64k; + bool tbi, tbid, epd, hpd, using16k, using64k; int select, tsz; /* Bit 55 is always between the two regions, and is canonical for @@ -9763,10 +9763,11 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, using16k = extract32(tcr, 15, 1); if (mmu_idx == ARMMMUIdx_S2NS) { /* VTCR_EL2 */ - tbi = hpd = false; + tbi = tbid = hpd = false; } else { tbi = extract32(tcr, 20, 1); hpd = extract32(tcr, 24, 1); + tbid = extract32(tcr, 29, 1); } epd = false; } else if (!select) { @@ -9776,6 +9777,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, using16k = extract32(tcr, 15, 1); tbi = extract64(tcr, 37, 1); hpd = extract64(tcr, 41, 1); + tbid = extract64(tcr, 51, 1); } else { int tg = extract32(tcr, 30, 2); using16k = tg == 1; @@ -9784,6 +9786,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, epd = extract32(tcr, 23, 1); tbi = extract64(tcr, 38, 1); hpd = extract64(tcr, 42, 1); + tbid = extract64(tcr, 52, 1); } tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ @@ -9792,6 +9795,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, .tsz = tsz, .select = select, .tbi = tbi, + .tbid = tbid, .epd = epd, .hpd = hpd, .using16k = using16k, @@ -9802,7 +9806,11 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data) { - return aa64_va_parameters_both(env, va, mmu_idx); + ARMVAParameters ret = aa64_va_parameters_both(env, va, mmu_idx); + + /* Present TBI as a composite with TBID. */ + ret.tbi &= (data || !ret.tbid); + return ret; } static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, From patchwork Tue Jan 8 22:31:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155019 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp38345jaa; Tue, 8 Jan 2019 14:42:06 -0800 (PST) X-Google-Smtp-Source: ALg8bN67OvkVld0d/Peg3fLoF/qkReO5wTkIA86usgXiE7b2wxYXJfS6oeUc8dZWeI/gQl7yzcnl X-Received: by 2002:adf:aa9c:: with SMTP id h28mr2810827wrc.216.1546987326758; Tue, 08 Jan 2019 14:42:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546987326; cv=none; d=google.com; s=arc-20160816; b=VscQW2V/Yr9bLciKAaiCHFd6IzgWWr3vnaKoSfyXxp8Cb3Itr5vXW/2pTkd/HFymit ArYSb+d/mMGtU0kUcLotxYr2m6rKLv9nkOsi4sfkmCRLhHaS1c1ASeNbdXueFuxYMK1n H0Lg/Pk9bumvAPj7pBw0mJeugBEGNdDXwlJXUEOaXdLO6RqOaOxEzc8c68s1RTl5fIxM 8Bj4Wi8GIJXOw/maNPBveFC8LCnfZZfmTFepBfbYq0qdaaa//rLTL1dVYoba5+nF/59L Ogg9Q2SapUlv7XX57a1PQTs7u3d+VhJan3w/+1e2L7VDIJ4yOZwjk0WpBSeOJT9acIwQ xPaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=x4CNbPTPbLbD5OUpnvxNmBSc1i8+hDI/XOOOW1xKo9M=; b=kxoLgWq6liC2JrLdB+4rHJmyQJhET7tqXfC+CsOJmwFrQ2cQ0AAUqlCG2zPfxiBGmc L37VusLvlpFJe0qzoy16iLl+kwGDf7ZTH2UhExqiU10OKg3RCxJ+83DyBmqwAhcsUkEs BopJu4pWKqyDVyFe4WuKog/JrtlFyKHddHkj5sq89P0B2QBXVG6oEZZ1AonQTvjt4TU2 rGGl53cLoBA3Y8EhDrknqw89BijMN7I9wE85rFBR6O2XAEV7eoJoxnyQ8gaVQbvSS4Xt DNmnIdNY5ZESDjnU65XdQvK5WuAygzx7E+BUs9N+Zz+s5CjoFcIvRvYAjaOx0CJu7ujm apsA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bh2NdUAu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:21 +1000 Message-Id: <20190108223129.5570-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v3 23/31] target/arm: Reuse aa64_va_parameters for setting tbflags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The arm_regime_tbi{0,1} functions are replacable with the new function by giving the lowest and highest address. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Use aa64_va_parameters_both and compute both tbii and tbid. Merged back from a later patch set. --- target/arm/cpu.h | 35 ----------------------- target/arm/helper.c | 70 ++++++++++++++++----------------------------- 2 files changed, 24 insertions(+), 81 deletions(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ea9b8ec4a1..8512ca3552 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3015,41 +3015,6 @@ static inline bool arm_cpu_bswap_data(CPUARMState *env) } #endif -#ifndef CONFIG_USER_ONLY -/** - * arm_regime_tbi0: - * @env: CPUARMState - * @mmu_idx: MMU index indicating required translation regime - * - * Extracts the TBI0 value from the appropriate TCR for the current EL - * - * Returns: the TBI0 value. - */ -uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx); - -/** - * arm_regime_tbi1: - * @env: CPUARMState - * @mmu_idx: MMU index indicating required translation regime - * - * Extracts the TBI1 value from the appropriate TCR for the current EL - * - * Returns: the TBI1 value. - */ -uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx); -#else -/* We can't handle tagged addresses properly in user-only mode */ -static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - return 0; -} - -static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - return 0; -} -#endif - void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags); diff --git a/target/arm/helper.c b/target/arm/helper.c index cc3c0d47c8..e610155166 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8957,48 +8957,6 @@ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) return mmu_idx; } -/* Returns TBI0 value for current regime el */ -uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - TCR *tcr; - uint32_t el; - - /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert - * a stage 1+2 mmu index into the appropriate stage 1 mmu index. - */ - mmu_idx = stage_1_mmu_idx(mmu_idx); - - tcr = regime_tcr(env, mmu_idx); - el = regime_el(env, mmu_idx); - - if (el > 1) { - return extract64(tcr->raw_tcr, 20, 1); - } else { - return extract64(tcr->raw_tcr, 37, 1); - } -} - -/* Returns TBI1 value for current regime el */ -uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - TCR *tcr; - uint32_t el; - - /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert - * a stage 1+2 mmu index into the appropriate stage 1 mmu index. - */ - mmu_idx = stage_1_mmu_idx(mmu_idx); - - tcr = regime_tcr(env, mmu_idx); - el = regime_el(env, mmu_idx); - - if (el > 1) { - return 0; - } else { - return extract64(tcr->raw_tcr, 38, 1); - } -} - /* Return the TTBR associated with this translation regime */ static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn) @@ -13051,10 +13009,30 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, *pc = env->pc; flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); - /* Get control bits for tagged addresses */ - flags = FIELD_DP32(flags, TBFLAG_A64, TBII, - (arm_regime_tbi1(env, mmu_idx) << 1) | - arm_regime_tbi0(env, mmu_idx)); + +#ifndef CONFIG_USER_ONLY + /* + * Get control bits for tagged addresses. Note that the + * translator only uses this for instruction addresses. + */ + { + ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); + ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); + int tbii, tbid; + + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + if (regime_el(env, stage1) < 2) { + ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1); + tbid = (p1.tbi << 1) | p0.tbi; + tbii = tbid & ~((p1.tbid << 1) | p0.tbid); + } else { + tbid = p0.tbi; + tbii = tbid & !p0.tbid; + } + + flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); + } +#endif if (cpu_isar_feature(aa64_sve, cpu)) { int sve_el = sve_exception_el(env, current_el); From patchwork Tue Jan 8 22:31:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155033 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp46553jaa; Tue, 8 Jan 2019 14:53:32 -0800 (PST) X-Google-Smtp-Source: ALg8bN6Z+qUDSrdyR/z1U2ireXG37aPGTQrb8vkdIVw2Wn2i9xpU3w6K/5kIkTxPBIVhDoz46er4 X-Received: by 2002:adf:e78f:: with SMTP id n15mr2901346wrm.115.1546988012841; Tue, 08 Jan 2019 14:53:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546988012; cv=none; d=google.com; s=arc-20160816; b=QeQTpfHax+Ni38M3Dy4tuPhtYCaLiBeSTftKG9u4SLN5sAS1BMyvZH1ugyfiMO+m1j YbtA1r4MW85LETJ9Jq33mIdHgvwQ7gdBuBNLfgm7771cShKk/axTTj1k3yGucUEK7HKl J+WZBkptfEidrQm61dcnZlmHVYwoLHe74v456/fY+vtr0tGtpnqmiT7iV8kQS0QLdvJ6 WHiYH87He2CeTNJK80d/mhwOrSSc4PsuWQ5Ww2Os5IAnyGq+ECxc5u/iIJ+G9AKOymEc hvFkh0fQWClj7Dcitf0CcjsHwfhlK+uFYfIZP1cf1gTmWcsNMfnl5GkHz1h4ZLMIh89l avpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=Mg19AKP3OnF6DGhhumbtnC9AwmLPjVNrmPOLEIDNGYE=; b=j97XTjCFLbXxu/M2vSn4R8KL1sNXrzsWQnyejrxt8uOZXhzlvYS4dPK4nKTDBXhLk9 HRO1KdpViPL7REm91X426TSSFbicWxBJtYoe4QujI+sWmAoBFJohAZJqoRcokQSJ5yvP qdSsOAWuf3mYV4zf9RxZ3GS6DvHVRVcQP4KyXp5ETnj0qJm8KODaJEcLflWasLD/P4e/ g8quNcIMoO49BJMcYESIra7gF0F+ix/r154o1TNRM6q69LiInqgnihbtu1hxacybLzEP U2LXU2Biv9Jt0QDIUozHCAAVjEGjMwB3SbLUt3cmpeMb2kNofO7Kg7q/x56MErpCUV9S 4HLA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="HjSM/PXy"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:22 +1000 Message-Id: <20190108223129.5570-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3 24/31] target/arm: Implement pauth_strip X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Stripping out the authentication data does not require any crypto, it merely requires the virtual address parameters. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/pauth_helper.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index 902f68a24c..e02376a2d0 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c @@ -38,6 +38,15 @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, g_assert_not_reached(); /* FIXME */ } +static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) +{ + uint64_t extfield = -param.select; + int bot_pac_bit = 64 - param.tsz; + int top_pac_bit = 64 - 8 * param.tbi; + + return deposit64(ptr, bot_pac_bit, top_pac_bit - bot_pac_bit, extfield); +} + static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, ARMPACKey *key, bool data, int keynumber) { @@ -46,7 +55,10 @@ static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, static uint64_t pauth_strip(CPUARMState *env, uint64_t ptr, bool data) { - g_assert_not_reached(); /* FIXME */ + ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); + + return pauth_original_ptr(ptr, param); } static void QEMU_NORETURN pauth_trap(CPUARMState *env, int target_el, From patchwork Tue Jan 8 22:31:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155025 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp40265jaa; Tue, 8 Jan 2019 14:44:58 -0800 (PST) X-Google-Smtp-Source: ALg8bN5Fdo2C2zOcvZFNhQbVf/4S87CXNQRgaa0Ukp0qOrc2fMXXBdJA77PSbHzo1XFf0CLBsxU6 X-Received: by 2002:a5d:4e82:: with SMTP id e2mr2743275wru.291.1546987498796; Tue, 08 Jan 2019 14:44:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546987498; cv=none; d=google.com; s=arc-20160816; b=Kf2jnwZIKFwfG97CjIQUuoKkV9FRrukUrip2wPHWxDm9dcls7EQpU5CUV/i8d8aVRQ KYJJLfdz4o9EXolIy+DJKzztxB0BmaFBIyhC+8PxDw6P/TeJfCCU5jps5f1GN7S5w4f6 VtuK45pmxZLvZhFcGHZWEYvFKZTu/85l8wJgrKkOsr8nNH2zXjxj+RlnXdv9h0rTsKLG Z9rPGSDLu5I5V3ofuaghgkvBu2LVtugIy+ErCrzrYzvpJBims6v+yMr8jMIyAW4yXiJo RxRa+ZPhif70EaFAbTkTPS1klWY7RWMfXw7oWiNhrcmq4AhozOuNJKQWgZvytZ0Abr1h KVuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=01IO6/Fjvs90ItdmEEqL8n0fmAXQds5N0LRFVoEcyAc=; b=mGdFIW5P2bb7oeYQ/zaHn6Hvn0lLL9sOQyXspdOwg+GpSVAqoa2UlGJ9l+OTWesLXZ sFexssiJkB1w/qmdgGtjvp6oiW8UscHV5YI8gIV+8OKM0sOn9dTP0AVdtMOlxavcjqh0 IhKc2oYrN5IYTQhWomzxTxHKMkKwe5UOKCMFl13kHtlQbBMHipqbEl9O6ZVfeJ1X502c 4QNhZi6maHsgBB4Sh1PPOtkBNH6DpH7QoS2uocg5oS6pBq53rBU9+7OWMGUI6LTA6emF O8UycVshko7wVTBZkYwxqv77vXi3xh748RlhoDJrFzot5rG30SJ2mTzHZV319Srd1F/h cQUw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=H2LfJane; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:23 +1000 Message-Id: <20190108223129.5570-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v3 25/31] target/arm: Implement pauth_auth X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is not really functional yet, because the crypto is not yet implemented. This, however follows the Auth pseudo function. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/pauth_helper.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index e02376a2d0..fa7707e0bf 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c @@ -50,7 +50,26 @@ static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, ARMPACKey *key, bool data, int keynumber) { - g_assert_not_reached(); /* FIXME */ + ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); + int bot_bit, top_bit; + uint64_t pac, orig_ptr, test; + + orig_ptr = pauth_original_ptr(ptr, param); + pac = pauth_computepac(orig_ptr, modifier, *key); + bot_bit = 64 - param.tsz; + top_bit = 64 - 8 * param.tbi; + + test = (pac ^ ptr) & ~MAKE_64BIT_MASK(55, 1); + if (unlikely(extract64(test, bot_bit, top_bit - bot_bit))) { + int error_code = (keynumber << 1) | (keynumber ^ 1); + if (param.tbi) { + return deposit64(ptr, 53, 2, error_code); + } else { + return deposit64(ptr, 61, 2, error_code); + } + } + return orig_ptr; } static uint64_t pauth_strip(CPUARMState *env, uint64_t ptr, bool data) From patchwork Tue Jan 8 22:31:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155028 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp42902jaa; Tue, 8 Jan 2019 14:48:34 -0800 (PST) X-Google-Smtp-Source: ALg8bN5j4xOoQQqEaoUzE9GfoQ02pXIkLP40MN1h50Aya7vpHgtqQ3D82pWxAV2yCmJoHXOU44HS X-Received: by 2002:a1c:c87:: with SMTP id 129mr3008479wmm.116.1546987713946; Tue, 08 Jan 2019 14:48:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546987713; cv=none; d=google.com; s=arc-20160816; b=MTDd5l0JXSY5WmRUBBmk/DkzsWBJkuKitsSzAdb8trnFdTdyc1BFWjQRLDZbSS0o/V ZQbY7mlD04ihkw05EFKzCjxaXbovM420+BJ2Yqw/GhL5339PiYsxt92Pi9LMLdz9q7m+ sqbSfwz9/9Ri/tNf8wLVnPooKeJxdS/qdpx0OtPJaASeS8XYgTNPmGKCC3Fo1YqqVxS3 Toeg/xoo5tM4HssGio3jbzzSKijgUJQ2ty+LX6wbYEOdzu5GLqFKByTAeaWJLlgu2nKj Rd72dY7yVsh42vUZTwDrloEhJ0EWuQkkH5LqykHWrjnQTSaxeRSntBbnU34HmThW8lV8 4AYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=m+Zcu5dZ/zmIPm21/MzZiFGJp7J+d+OfEJPTnePaGgs=; b=Bfbm1DP97akZvTyIcZw2ARrLvIv2W5PYm6ZX9VsNqb/fkPfFWCKWj7q+u3FptkdaBK 0M3CH3a74+gW52s4UAS3amo+sZzSse55ddCWJJnjdubp+N6mKXMtE0NVeXAo0AkJg8VJ kjeIsbLrHGGsB5dNtryC7lIAlsA9Rg+Rwt2cLR9MDKvHaY7iW4O5hxI4O+hYJhz8EIsB cvIHTnwhxFOL4r+BtT+k8eOWCygk7T74V9mz4pQtZTgEiqUCd4KvSbFOUCswrmFxlM2I A2XhBFN1sI8/kUJtdZRIsjMfez4qURn18zPPFczQefresl3qf+ma91MnXWIBAiyXpAIp U6DA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="F+F+/Iry"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:24 +1000 Message-Id: <20190108223129.5570-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62b Subject: [Qemu-devel] [PATCH v3 26/31] target/arm: Implement pauth_addpac X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is not really functional yet, because the crypto is not yet implemented. This, however follows the AddPAC pseudo function. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson ---- v3: Use MAKE_64BIT_MASK one more place. --- target/arm/pauth_helper.c | 42 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index fa7707e0bf..bc89dd8c11 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c @@ -35,7 +35,47 @@ static uint64_t pauth_computepac(uint64_t data, uint64_t modifier, static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, ARMPACKey *key, bool data) { - g_assert_not_reached(); /* FIXME */ + ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); + uint64_t pac, ext_ptr, ext, test; + int bot_bit, top_bit; + + /* If tagged pointers are in use, use ptr<55>, otherwise ptr<63>. */ + if (param.tbi) { + ext = sextract64(ptr, 55, 1); + } else { + ext = sextract64(ptr, 63, 1); + } + + /* Build a pointer with known good extension bits. */ + top_bit = 64 - 8 * param.tbi; + bot_bit = 64 - param.tsz; + ext_ptr = deposit64(ptr, bot_bit, top_bit - bot_bit, ext); + + pac = pauth_computepac(ext_ptr, modifier, *key); + + /* + * Check if the ptr has good extension bits and corrupt the + * pointer authentication code if not. + */ + test = sextract64(ptr, bot_bit, top_bit - bot_bit); + if (test != 0 && test != -1) { + pac ^= MAKE_64BIT_MASK(top_bit - 1, 1); + } + + /* + * Preserve the determination between upper and lower at bit 55, + * and insert pointer authentication code. + */ + if (param.tbi) { + ptr &= ~MAKE_64BIT_MASK(bot_bit, 55 - bot_bit + 1); + pac &= MAKE_64BIT_MASK(bot_bit, 54 - bot_bit + 1); + } else { + ptr &= MAKE_64BIT_MASK(0, bot_bit); + pac &= ~(MAKE_64BIT_MASK(55, 1) | MAKE_64BIT_MASK(0, bot_bit)); + } + ext &= MAKE_64BIT_MASK(55, 1); + return pac | ext | ptr; } static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) From patchwork Tue Jan 8 22:31:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155036 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp48618jaa; Tue, 8 Jan 2019 14:56:34 -0800 (PST) X-Google-Smtp-Source: ALg8bN6IZf3ney2u2bxgO//eYoxcbTKnQB6BnuG8SbL9x4qabztE7SZxteVyl48TST7Ri+i7qGfZ X-Received: by 2002:a1c:9a0d:: with SMTP id c13mr3335708wme.41.1546988194241; Tue, 08 Jan 2019 14:56:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546988194; cv=none; d=google.com; s=arc-20160816; b=YdKY2p0fwpEefhajcnqUEJik4UnBiL7hSHJ+n4fWZPXl8W7lOK3YeP7PguGeU7KYE1 BTV0yzhrBL7XCzoRp9ls0DLmyB7oL9rs3f1TUn2kkGVI0AOKUXr5ZtPs2HhwJZyDXZY0 zlLIfybpyxrPAzzfitDVfX2ay+OSVOmmngbuYIqkqyyo+1NlijlXXF7qK7eoTGMLEi51 7u/dKpN0HbRhZ/GXVLk78Pm3CMDPfF+EK4EuwaDwwGBXzCUxyOvIEAiU8qAmuJY962U1 Nv8FpMmmg81JbriZ3rbGGeaqaGN7ix+rk0luCzexAEF8yigrQKlhiRuUFdR+UyGazVL7 kyRA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=TVFC2GnajrDi6vJcNao7tzlaxbm1uciSrDAJDzmWUhc=; b=qbqn/NM2af2Tdc0whOXil2T6qTC0/HVPq6AbrQrpGVwHOsoRSceT22CMHLUA5sft7b UZRurHf9rc7KiMCF1q5edcQAyO+0B3GNBHW5SNbfeBSF9qcTzjTfr5j6FfcRnR/r159o 2Edbzk64y/QsBX5b1G6LHAb0BtHu5mJ4t+DqRuXh2yli7T0A8n8fQdh71wNW92V3avlS lwTeNfAjCbi5vuVp1HB6IZRpCF3muLsBHyVLCZIq5J0rVtEg272t2XX2GPm/xw6+q7Lw iOw1HtxO5G+I8DsTGlyI2N8xTn0A/7jALwJOeVLbv8D8YJ+MRd4LCNit7GGFojuAzvjI peTQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=A5JIwu+p; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:25 +1000 Message-Id: <20190108223129.5570-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v3 27/31] target/arm: Implement pauth_computepac X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is the main crypto routine, an implementation of QARMA. This matches, as much as possible, ARM pseudocode. Signed-off-by: Richard Henderson --- target/arm/pauth_helper.c | 241 +++++++++++++++++++++++++++++++++++++- 1 file changed, 240 insertions(+), 1 deletion(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index bc89dd8c11..bc0c9b84e7 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c @@ -26,10 +26,249 @@ #include "tcg/tcg-gvec-desc.h" +static uint64_t pac_cell_shuffle(uint64_t i) +{ + uint64_t o = 0; + + o |= extract64(i, 52, 4); + o |= extract64(i, 24, 4) << 4; + o |= extract64(i, 44, 4) << 8; + o |= extract64(i, 0, 4) << 12; + + o |= extract64(i, 28, 4) << 16; + o |= extract64(i, 48, 4) << 20; + o |= extract64(i, 4, 4) << 24; + o |= extract64(i, 40, 4) << 28; + + o |= extract64(i, 32, 4) << 32; + o |= extract64(i, 12, 4) << 36; + o |= extract64(i, 56, 4) << 40; + o |= extract64(i, 20, 4) << 44; + + o |= extract64(i, 8, 4) << 48; + o |= extract64(i, 36, 4) << 52; + o |= extract64(i, 16, 4) << 56; + o |= extract64(i, 60, 4) << 60; + + return o; +} + +static uint64_t pac_cell_inv_shuffle(uint64_t i) +{ + uint64_t o = 0; + + o |= extract64(i, 12, 4); + o |= extract64(i, 24, 4) << 4; + o |= extract64(i, 48, 4) << 8; + o |= extract64(i, 36, 4) << 12; + + o |= extract64(i, 56, 4) << 16; + o |= extract64(i, 44, 4) << 20; + o |= extract64(i, 4, 4) << 24; + o |= extract64(i, 16, 4) << 28; + + o |= i & MAKE_64BIT_MASK(32, 4); + o |= extract64(i, 52, 4) << 36; + o |= extract64(i, 28, 4) << 40; + o |= extract64(i, 8, 4) << 44; + + o |= extract64(i, 20, 4) << 48; + o |= extract64(i, 0, 4) << 52; + o |= extract64(i, 40, 4) << 56; + o |= i & MAKE_64BIT_MASK(60, 4); + + return o; +} + +static uint64_t pac_sub(uint64_t i) +{ + static const uint8_t sub[16] = { + 0xb, 0x6, 0x8, 0xf, 0xc, 0x0, 0x9, 0xe, + 0x3, 0x7, 0x4, 0x5, 0xd, 0x2, 0x1, 0xa, + }; + uint64_t o = 0; + int b; + + for (b = 0; b < 64; b += 16) { + o |= (uint64_t)sub[(i >> b) & 0xf] << b; + } + return o; +} + +static uint64_t pac_inv_sub(uint64_t i) +{ + static const uint8_t inv_sub[16] = { + 0x5, 0xe, 0xd, 0x8, 0xa, 0xb, 0x1, 0x9, + 0x2, 0x6, 0xf, 0x0, 0x4, 0xc, 0x7, 0x3, + }; + uint64_t o = 0; + int b; + + for (b = 0; b < 64; b += 16) { + o |= (uint64_t)inv_sub[(i >> b) & 0xf] << b; + } + return o; +} + +static int rot_cell(int cell, int n) +{ + /* 4-bit rotate left by n. */ + cell |= cell << 4; + return extract32(cell, 4 - n, 4); +} + +static uint64_t pac_mult(uint64_t i) +{ + uint64_t o = 0; + int b; + + for (b = 0; b < 4 * 4; b += 4) { + int i0, i4, i8, ic, t0, t1, t2, t3; + + i0 = extract64(i, b, 4); + i4 = extract64(i, b + 4 * 4, 4); + i8 = extract64(i, b + 8 * 4, 4); + ic = extract64(i, b + 12 * 4, 4); + + t0 = rot_cell(i8, 1) ^ rot_cell(i4, 2) ^ rot_cell(i0, 1); + t1 = rot_cell(ic, 1) ^ rot_cell(i4, 1) ^ rot_cell(i0, 2); + t2 = rot_cell(ic, 2) ^ rot_cell(i8, 1) ^ rot_cell(i0, 1); + t3 = rot_cell(ic, 1) ^ rot_cell(i8, 2) ^ rot_cell(i4, 1); + + o |= (uint64_t)t3 << b; + o |= (uint64_t)t2 << (b + 4 * 4); + o |= (uint64_t)t1 << (b + 8 * 4); + o |= (uint64_t)t0 << (b + 12 * 4); + } + return o; +} + +static uint64_t tweak_cell_rot(uint64_t cell) +{ + return (cell >> 1) | (((cell ^ (cell >> 1)) & 1) << 3); +} + +static uint64_t tweak_shuffle(uint64_t i) +{ + uint64_t o = 0; + + o |= extract64(i, 16, 4) << 0; + o |= extract64(i, 20, 4) << 4; + o |= tweak_cell_rot(extract64(i, 24, 4)) << 8; + o |= extract64(i, 28, 4) << 12; + + o |= tweak_cell_rot(extract64(i, 44, 4)) << 16; + o |= extract64(i, 8, 4) << 20; + o |= extract64(i, 12, 4) << 24; + o |= tweak_cell_rot(extract64(i, 32, 4)) << 28; + + o |= extract64(i, 48, 4) << 32; + o |= extract64(i, 52, 4) << 36; + o |= extract64(i, 56, 4) << 40; + o |= tweak_cell_rot(extract64(i, 60, 4)) << 44; + + o |= tweak_cell_rot(extract64(i, 0, 4)) << 48; + o |= extract64(i, 4, 4) << 52; + o |= tweak_cell_rot(extract64(i, 40, 4)) << 56; + o |= tweak_cell_rot(extract64(i, 36, 4)) << 60; + + return o; +} + +static uint64_t tweak_cell_inv_rot(uint64_t cell) +{ + return ((cell << 1) & 0xf) | ((cell & 1) ^ (cell >> 3)); +} + +static uint64_t tweak_inv_shuffle(uint64_t i) +{ + uint64_t o = 0; + + o |= tweak_cell_inv_rot(extract64(i, 48, 4)); + o |= extract64(i, 52, 4) << 4; + o |= extract64(i, 20, 4) << 8; + o |= extract64(i, 24, 4) << 12; + + o |= extract64(i, 0, 4) << 16; + o |= extract64(i, 4, 4) << 20; + o |= tweak_cell_inv_rot(extract64(i, 8, 4)) << 24; + o |= extract64(i, 12, 4) << 28; + + o |= tweak_cell_inv_rot(extract64(i, 28, 4)) << 32; + o |= tweak_cell_inv_rot(extract64(i, 60, 4)) << 36; + o |= tweak_cell_inv_rot(extract64(i, 56, 4)) << 40; + o |= tweak_cell_inv_rot(extract64(i, 16, 4)) << 44; + + o |= extract64(i, 32, 4) << 48; + o |= extract64(i, 36, 4) << 52; + o |= extract64(i, 40, 4) << 56; + o |= tweak_cell_inv_rot(extract64(i, 44, 4)) << 60; + + return o; +} + static uint64_t pauth_computepac(uint64_t data, uint64_t modifier, ARMPACKey key) { - g_assert_not_reached(); /* FIXME */ + static const uint64_t RC[5] = { + 0x0000000000000000ull, + 0x13198A2E03707344ull, + 0xA4093822299F31D0ull, + 0x082EFA98EC4E6C89ull, + 0x452821E638D01377ull, + }; + const uint64_t alpha = 0xC0AC29B7C97C50DDull; + /* Note that in the ARM pseudocode, key0 contains bits <127:64> + * and key1 contains bits <63:0> of the 128-bit key. + */ + uint64_t key0 = key.hi, key1 = key.lo; + uint64_t workingval, runningmod, roundkey, modk0; + int i; + + modk0 = (key0 << 63) | ((key0 >> 1) ^ (key0 >> 63)); + runningmod = modifier; + workingval = data ^ key0; + + for (i = 0; i <= 4; ++i) { + roundkey = key1 ^ runningmod; + workingval ^= roundkey; + workingval ^= RC[i]; + if (i > 0) { + workingval = pac_cell_shuffle(workingval); + workingval = pac_mult(workingval); + } + workingval = pac_sub(workingval); + runningmod = tweak_shuffle(runningmod); + } + roundkey = modk0 ^ runningmod; + workingval ^= roundkey; + workingval = pac_cell_shuffle(workingval); + workingval = pac_mult(workingval); + workingval = pac_sub(workingval); + workingval = pac_cell_shuffle(workingval); + workingval = pac_mult(workingval); + workingval ^= key1; + workingval = pac_cell_inv_shuffle(workingval); + workingval = pac_inv_sub(workingval); + workingval = pac_mult(workingval); + workingval = pac_cell_inv_shuffle(workingval); + workingval ^= key0; + workingval ^= runningmod; + for (i = 0; i <= 4; ++i) { + workingval = pac_inv_sub(workingval); + if (i < 4) { + workingval = pac_mult(workingval); + workingval = pac_cell_inv_shuffle(workingval); + } + runningmod = tweak_inv_shuffle(runningmod); + roundkey = key1 ^ runningmod; + workingval ^= RC[4-i]; + workingval ^= roundkey; + workingval ^= alpha; + } + workingval ^= modk0; + + return workingval; } static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, From patchwork Tue Jan 8 22:31:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155031 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp45274jaa; Tue, 8 Jan 2019 14:51:50 -0800 (PST) X-Google-Smtp-Source: ALg8bN6UYfRZ2EQH2Yhth6Tt3ujyobU9KfzZ+3vwhU1xrzV8q7XPSZqp0HXj/E2TKAo0yS1anCez X-Received: by 2002:adf:c108:: with SMTP id r8mr2956105wre.233.1546987910186; Tue, 08 Jan 2019 14:51:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546987910; cv=none; d=google.com; s=arc-20160816; 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X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v3 28/31] target/arm: Add PAuth system registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson ---- v3: Fix typos. --- target/arm/helper.c | 70 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) -- 2.17.2 diff --git a/target/arm/helper.c b/target/arm/helper.c index e610155166..0e1bf521ab 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5061,6 +5061,70 @@ static CPAccessResult access_lor_other(CPUARMState *env, return access_lor_ns(env); } +#ifdef TARGET_AARCH64 +static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el = arm_current_el(env); + + if (el < 2 && + arm_feature(env, ARM_FEATURE_EL2) && + !(arm_hcr_el2_eff(env) & HCR_APK)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && + arm_feature(env, ARM_FEATURE_EL3) && + !(env->cp15.scr_el3 & SCR_APK)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo pauth_reginfo[] = { + { .name = "APDAKEYLO_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 0, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apda_key.lo) }, + { .name = "APDAKEYHI_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 1, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apda_key.hi) }, + { .name = "APDBKEYLO_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 2, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apdb_key.lo) }, + { .name = "APDBKEYHI_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 3, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apdb_key.hi) }, + { .name = "APGAKEYLO_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 0, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apga_key.lo) }, + { .name = "APGAKEYHI_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 1, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apga_key.hi) }, + { .name = "APIAKEYLO_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 0, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apia_key.lo) }, + { .name = "APIAKEYHI_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 1, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apia_key.hi) }, + { .name = "APIBKEYLO_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 2, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apib_key.lo) }, + { .name = "APIBKEYHI_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3, + .access = PL1_RW, .accessfn = access_pauth, + .fieldoffset = offsetof(CPUARMState, apib_key.hi) }, + REGINFO_SENTINEL +}; +#endif + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -5845,6 +5909,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &zcr_el3_reginfo); } } + +#ifdef TARGET_AARCH64 + if (cpu_isar_feature(aa64_pauth, cpu)) { + define_arm_cp_regs(cpu, pauth_reginfo); + } +#endif } void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) From patchwork Tue Jan 8 22:31:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155034 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp46766jaa; Tue, 8 Jan 2019 14:53:55 -0800 (PST) X-Google-Smtp-Source: ALg8bN42NwtmFxTqj2zsYe8gOXAZ069vK37wPDZDPA03tQy3Nmgcn9ZqU4L5uAz4yT94JRmEFZyv X-Received: by 2002:a1c:7c07:: with SMTP id x7mr3248632wmc.82.1546988035484; Tue, 08 Jan 2019 14:53:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546988035; 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X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3 29/31] target/arm: Enable PAuth for -cpu max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.2 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 4b544a1c58..1974f1aeb7 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -316,6 +316,10 @@ static void aarch64_max_initfn(Object *obj) t = cpu->isar.id_aa64isar1; t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); + t = FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected only */ + t = FIELD_DP64(t, ID_AA64ISAR1, API, 0); + t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1); + t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0); cpu->isar.id_aa64isar1 = t; t = cpu->isar.id_aa64pfr0; From patchwork Tue Jan 8 22:31:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155038 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp49200jaa; Tue, 8 Jan 2019 14:57:21 -0800 (PST) X-Google-Smtp-Source: ALg8bN5nzuGLjaYayayWlbug3twOEFrDfL7sFFaWXReNk7iCroJiJB1nGNfkOEbkOZusSucEL9i/ X-Received: by 2002:adf:eb45:: with SMTP id u5mr2705998wrn.102.1546988241779; Tue, 08 Jan 2019 14:57:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546988241; cv=none; d=google.com; s=arc-20160816; b=jDNe7z0649Tg6MYiFmmmCW1Ls3UjpQoNHz9iqcjZVYYor1hli4okc0Up4SJHe5SWIi Sv+XNH1VMK52z7MEOchpMTERda3bytglP/hFA3JhDLjatv1fbM3JROnQtn1Hr0uy0VoF rter8ScR8nhqDQiMb4YbQL1q3F5RJvFF5JHQnL/0pQmrh9tfBV68GM/DTN7tOXSHH+Sj VPBFkLypWYNj4G9XqSDD58dc23bpGYgkmn+I3gtav23rTfa/GzFIWzVvI7bvOdz/HtI+ zsvi1HqWcl/UPiXD29fk/aTL3SLUcWu2C4wqCmWPFBFYd0j5NUr1u6t+yN8QATWdLCDx fd2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=SsMK15voUNz/4OMQjnv/6CxVykvnZyFEz9xWDCHBxbE=; b=VaAOhtoOGZwsAG5SEsCFToyyKNhKEXcuernYA29KJ47S0B3MinFrsvuMPHY6lJ7GaS 0v17CY/f8voQ+lth3MMPI8XC6DV4wvSIMCXgV9pRODSDQDJk/o3jjWZ2qT1rngyg/Yo9 Bxh9JYAbQRsiybro8RfU0wbvkEOob4mLK3s0mRLmGuKK39wZw2o5iGknMExZGqYjHznX ywpMwe+XHAt4W7xF/ZNWAPEuBqUtP5f3a5avvgJTEaOgVjx7M65LRZ1b6CVlMI2gaqQ5 1HHcuX4H6LbJ/f2J5BS/aw4ZIEUVJRvGbIzAFi3ItFQ/Ebv1kCNe8GLH6it4NbtgvEWw BnXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RFtKkgTF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:28 +1000 Message-Id: <20190108223129.5570-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v3 30/31] target/arm: Enable PAuth for user-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add 4 attributes that controls the EL1 enable bits, as we may not always want to turn on pointer authentication with -cpu max. However, by default they are enabled. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 3 +++ target/arm/cpu64.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4c4e9e169e..14bc24a35a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -162,6 +162,9 @@ static void arm_cpu_reset(CPUState *s) env->pstate = PSTATE_MODE_EL0t; /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; + /* Enable all PAC instructions */ + env->cp15.hcr_el2 |= HCR_API; + env->cp15.scr_el3 |= SCR_API; /* and to the FP/Neon instructions */ env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); /* and to the SVE instructions */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1974f1aeb7..d0de0d5dcf 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -285,6 +285,38 @@ static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name, error_propagate(errp, err); } +#ifdef CONFIG_USER_ONLY +static void cpu_max_get_packey(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + const uint64_t *bit = opaque; + bool enabled = (cpu->env.cp15.sctlr_el[1] & *bit) != 0; + + visit_type_bool(v, name, &enabled, errp); +} + +static void cpu_max_set_packey(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + Error *err = NULL; + const uint64_t *bit = opaque; + bool enabled; + + visit_type_bool(v, name, &enabled, errp); + + if (!err) { + if (enabled) { + cpu->env.cp15.sctlr_el[1] |= *bit; + } else { + cpu->env.cp15.sctlr_el[1] &= ~*bit; + } + } + error_propagate(errp, err); +} +#endif + /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); * otherwise, a CPU with as many features enabled as our emulation supports. * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; @@ -360,6 +392,34 @@ static void aarch64_max_initfn(Object *obj) */ cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ + + /* + * Note that Linux will enable enable all of the keys at once. + * But doing it this way will allow experimentation beyond that. + */ + { + static const uint64_t apia_bit = SCTLR_EnIA; + static const uint64_t apib_bit = SCTLR_EnIB; + static const uint64_t apda_bit = SCTLR_EnDA; + static const uint64_t apdb_bit = SCTLR_EnDB; + + object_property_add(obj, "apia", "bool", cpu_max_get_packey, + cpu_max_set_packey, NULL, + (void *)&apia_bit, &error_fatal); + object_property_add(obj, "apib", "bool", cpu_max_get_packey, + cpu_max_set_packey, NULL, + (void *)&apib_bit, &error_fatal); + object_property_add(obj, "apda", "bool", cpu_max_get_packey, + cpu_max_set_packey, NULL, + (void *)&apda_bit, &error_fatal); + object_property_add(obj, "apdb", "bool", cpu_max_get_packey, + cpu_max_set_packey, NULL, + (void *)&apdb_bit, &error_fatal); + + /* Enable all PAC keys by default. */ + cpu->env.cp15.sctlr_el[1] |= SCTLR_EnIA | SCTLR_EnIB; + cpu->env.cp15.sctlr_el[1] |= SCTLR_EnDA | SCTLR_EnDB; + } #endif cpu->sve_max_vq = ARM_MAX_VQ; From patchwork Tue Jan 8 22:31:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155037 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp48857jaa; Tue, 8 Jan 2019 14:56:52 -0800 (PST) X-Google-Smtp-Source: ALg8bN4GtRoHFSWW5GxaKz7u77AEYkU+So6nlEvrlBVL96AVG5mSO0m6tGDlet377Q3ZT36T6g+7 X-Received: by 2002:a7b:c1d7:: with SMTP id a23mr3025867wmj.48.1546988212896; Tue, 08 Jan 2019 14:56:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546988212; cv=none; d=google.com; s=arc-20160816; b=b0L9dDO2+XI7cLQfbRvDMzaAagcWKqGY5daw/RW4EN7FpRqfUksqrzZ1uQbiH7fTzc G8UfNCEskWgsi4LZGfv2Yu4E643VPo79WfpfcyxNLlS30ovK+FzPoDNaCOhveDkkDhgn JNlvEpiDGzomWhHhkYk1P9mviCGCGF3h/ARvA15Y0daIrFJscEgUHWuRS06gyCoM5f/E qsE3sROLEu4uRfww8xaUnmP0LCw9Pq3FMlrn6KutuTqjuwaNK8kvb+YKtx1invRPmNVs wUSQktjsU472HznDJuvjNzytuphzVXE/+6+NADETZWEXVubLrkvNgv+v7tgAjjzDPvNj fCRQ== ARC-Message-Signature: i=1; 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[2001:44b8:2176:c800:8cc6:2630:7d99:5ef1]) by smtp.gmail.com with ESMTPSA id w128sm100686177pfw.79.2019.01.08.14.32.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Jan 2019 14:32:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 9 Jan 2019 08:31:29 +1000 Message-Id: <20190108223129.5570-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190108223129.5570-1-richard.henderson@linaro.org> References: <20190108223129.5570-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3 31/31] target/arm: Tidy TBI handling in gen_a64_set_pc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We can perform this with fewer operations. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson ---- v3: Update for tbii = tbi1:tbi0. --- target/arm/translate-a64.c | 62 +++++++++++++------------------------- 1 file changed, 21 insertions(+), 41 deletions(-) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ee92533469..c398da9214 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -261,7 +261,7 @@ void gen_a64_set_pc_im(uint64_t val) /* Load the PC from a generic TCG variable. * * If address tagging is enabled via the TCR TBI bits, then loading - * an address into the PC will clear out any tag in the it: + * an address into the PC will clear out any tag in it: * + for EL2 and EL3 there is only one TBI bit, and if it is set * then the address is zero-extended, clearing bits [63:56] * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0 @@ -280,54 +280,34 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) int tbi = s->tbii; if (s->current_el <= 1) { - /* Test if NEITHER or BOTH TBI values are set. If so, no need to - * examine bit 55 of address, can just generate code. - * If mixed, then test via generated code - */ - if (tbi == 3) { - TCGv_i64 tmp_reg = tcg_temp_new_i64(); - /* Both bits set, sign extension from bit 55 into [63:56] will - * cover both cases - */ - tcg_gen_shli_i64(tmp_reg, src, 8); - tcg_gen_sari_i64(cpu_pc, tmp_reg, 8); - tcg_temp_free_i64(tmp_reg); - } else if (tbi == 0) { - /* Neither bit set, just load it as-is */ - tcg_gen_mov_i64(cpu_pc, src); - } else { - TCGv_i64 tcg_tmpval = tcg_temp_new_i64(); - TCGv_i64 tcg_bit55 = tcg_temp_new_i64(); - TCGv_i64 tcg_zero = tcg_const_i64(0); + if (tbi != 0) { + /* Sign-extend from bit 55. */ + tcg_gen_sextract_i64(cpu_pc, src, 0, 56); - tcg_gen_andi_i64(tcg_bit55, src, (1ull << 55)); + if (tbi != 3) { + TCGv_i64 tcg_zero = tcg_const_i64(0); - if (tbi == 1) { - /* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */ - tcg_gen_andi_i64(tcg_tmpval, src, - 0x00FFFFFFFFFFFFFFull); - tcg_gen_movcond_i64(TCG_COND_EQ, cpu_pc, tcg_bit55, tcg_zero, - tcg_tmpval, src); - } else { - /* tbi0==0, tbi1==1, so 1-fill upper byte if bit 55 = 1 */ - tcg_gen_ori_i64(tcg_tmpval, src, - 0xFF00000000000000ull); - tcg_gen_movcond_i64(TCG_COND_NE, cpu_pc, tcg_bit55, tcg_zero, - tcg_tmpval, src); + /* + * The two TBI bits differ. + * If tbi0, then !tbi1: only use the extension if positive. + * if !tbi0, then tbi1: only use the extension if negative. + */ + tcg_gen_movcond_i64(tbi == 1 ? TCG_COND_GE : TCG_COND_LT, + cpu_pc, cpu_pc, tcg_zero, cpu_pc, src); + tcg_temp_free_i64(tcg_zero); } - tcg_temp_free_i64(tcg_zero); - tcg_temp_free_i64(tcg_bit55); - tcg_temp_free_i64(tcg_tmpval); + return; } - } else { /* EL > 1 */ + } else { if (tbi != 0) { /* Force tag byte to all zero */ - tcg_gen_andi_i64(cpu_pc, src, 0x00FFFFFFFFFFFFFFull); - } else { - /* Load unmodified address */ - tcg_gen_mov_i64(cpu_pc, src); + tcg_gen_extract_i64(cpu_pc, src, 0, 56); + return; } } + + /* Load unmodified address */ + tcg_gen_mov_i64(cpu_pc, src); } typedef struct DisasCompare64 {