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[220.239.117.135]) by smtp.gmail.com with ESMTPSA id h74sm140934699pfd.35.2019.01.10.04.17.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 Jan 2019 04:17:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 Jan 2019 23:17:26 +1100 Message-Id: <20190110121736.23448-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190110121736.23448-1-richard.henderson@linaro.org> References: <20190110121736.23448-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH 01/11] target/arm: Introduce isar_feature_aa64_bti X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Also create field definitions for id_aa64pfr1 from ARMv8.5. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8512ca3552..fadb74d9a6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1630,6 +1630,9 @@ FIELD(ID_AA64PFR0, GIC, 24, 4) FIELD(ID_AA64PFR0, RAS, 28, 4) FIELD(ID_AA64PFR0, SVE, 32, 4) +FIELD(ID_AA64PFR1, BT, 0, 4) +FIELD(ID_AA64PFR1, SBSS, 4, 4) + FIELD(ID_AA64MMFR0, PARANGE, 0, 4) FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) FIELD(ID_AA64MMFR0, BIGEND, 8, 4) @@ -3268,6 +3271,11 @@ static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; } +static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ From patchwork Thu Jan 10 12:17:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155137 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1832032jaa; Thu, 10 Jan 2019 04:21:24 -0800 (PST) X-Google-Smtp-Source: ALg8bN4XceQ9KXWT57/fwyaLp9z5al2LZIKB3ExFtL3vJJfyqy7jBmdkPxdGsFjuoCpFfBuh2U5a X-Received: by 2002:a1c:2c44:: with SMTP id s65mr10306035wms.80.1547122884439; Thu, 10 Jan 2019 04:21:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547122884; cv=none; d=google.com; s=arc-20160816; b=ImnePc/BTwoOv95CD6ibbA1AlWDIZTRLyi/bjcFPFFyce+tDFAU3JnW1G3STcJGvVb 8We6VU2D3pZZrSTTQnXdzuXfcbELFWDrTOXbLAk3uh3FGy/vo8C07w7qcMhvT87a9zks YBZHnJfR2jC8bf35YhXLvtwjRc3fhObVW4N9kuupx5Tgtzs60EPec7kSAG/XIaXf18mb 5iinSdcS5wjszlKIPBbGPNngvfEglnBeooLY/7nxy6yETWKXRa/88MGVO4tW6depZwwo jGWdDgBTB8J1fNo7VmHJko2jAG0wJWAewRMYFX/mtQBUtsh2YnSJr7DOCIwiZWMKijN/ mEUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=oasvDAmRt5epJt1fiYz/E8kNR8BOc+EcbCwre/X4ac8=; b=fUWYwOX9koKfP4LeMJnTHI3BNqrVYFVP9g7LVcyz2bCk9gkvAM4Jih75m583fEoesm m4yg81cOaWH10k/HRL8tCbMNKD8hF4JtivpJGks9HZCGjd38d75Y7ibBVeGHuOpxIOhX xMY3E74Bef5llfdQd6bNwg3DcWvtXlhsSUOAuzig+L08TLAOPiR/UZi53KIJpeRpAEoR QpQTch50v3Ll5gomC6o6eizVQD2RBLNGavRSjAu3CMivTeWmSOXMNasWeAs2128KiJhS ZvFbzlS0czGuG8T+Fp2urWnAo1EG5/6NrQ0s/0WO/AbUUvn2Pr9ojfh+AOG4BVMDoJiH moGg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dI88+ojo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[220.239.117.135]) by smtp.gmail.com with ESMTPSA id h74sm140934699pfd.35.2019.01.10.04.17.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 Jan 2019 04:17:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 Jan 2019 23:17:27 +1100 Message-Id: <20190110121736.23448-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190110121736.23448-1-richard.henderson@linaro.org> References: <20190110121736.23448-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH 02/11] target/arm: Add PSTATE.BTYPE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Place this in its own field within ENV, as that will make it easier to reset from within TCG generated code. With the change to pstate_read/write, exception entry and return are automatically handled. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 8 ++++++-- target/arm/translate-a64.c | 3 +++ 2 files changed, 9 insertions(+), 2 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fadb74d9a6..8179c07250 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -234,6 +234,7 @@ typedef struct CPUARMState { * semantics as for AArch32, as described in the comments on each field) * nRW (also known as M[4]) is kept, inverted, in env->aarch64 * DAIF (exception masks) are kept in env->daif + * BTYPE is kept in env->btype * all other bits are stored in their correct places in env->pstate */ uint32_t pstate; @@ -263,6 +264,7 @@ typedef struct CPUARMState { uint32_t GE; /* cpsr[19:16] */ uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ + uint32_t btype; /* BTI branch type. spsr[11:10]. */ uint64_t daif; /* exception masks, in the bits they are in PSTATE */ uint64_t elr_el[4]; /* AArch64 exception link regs */ @@ -1155,6 +1157,7 @@ void pmccntr_sync(CPUARMState *env); #define PSTATE_I (1U << 7) #define PSTATE_A (1U << 8) #define PSTATE_D (1U << 9) +#define PSTATE_BTYPE (3U << 10) #define PSTATE_IL (1U << 20) #define PSTATE_SS (1U << 21) #define PSTATE_V (1U << 28) @@ -1163,7 +1166,7 @@ void pmccntr_sync(CPUARMState *env); #define PSTATE_N (1U << 31) #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) -#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF) +#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) /* Mode values for AArch64 */ #define PSTATE_MODE_EL3h 13 #define PSTATE_MODE_EL3t 12 @@ -1195,7 +1198,7 @@ static inline uint32_t pstate_read(CPUARMState *env) ZF = (env->ZF == 0); return (env->NF & 0x80000000) | (ZF << 30) | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) - | env->pstate | env->daif; + | env->pstate | env->daif | (env->btype << 10); } static inline void pstate_write(CPUARMState *env, uint32_t val) @@ -1205,6 +1208,7 @@ static inline void pstate_write(CPUARMState *env, uint32_t val) env->CF = (val >> 29) & 1; env->VF = (val << 3) & 0x80000000; env->daif = val & PSTATE_DAIF; + env->btype = (val >> 10) & 3; env->pstate = val & ~CACHED_PSTATE_BITS; } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2c5ad1774a..e43f0982f9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -163,6 +163,9 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, el, psr & PSTATE_SP ? 'h' : 't'); + if (cpu_isar_feature(aa64_bti, cpu)) { + cpu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); + } if (!(flags & CPU_DUMP_FPU)) { cpu_fprintf(f, "\n"); return; From patchwork Thu Jan 10 12:17:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155140 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1834925jaa; Thu, 10 Jan 2019 04:24:39 -0800 (PST) X-Google-Smtp-Source: ALg8bN7c1d9c6uqZCDPpWDd0gVr1Sjfdo57ii3aI/ICPfirSY5FkJb0vi53rhJoKRpdK3r8cZStt X-Received: by 2002:a1c:c2d4:: with SMTP id s203mr9625526wmf.3.1547123079846; Thu, 10 Jan 2019 04:24:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547123079; cv=none; d=google.com; s=arc-20160816; b=q5B3541bu+mSgpTfrESgG1e78o9YR4HbxlWkKz0/9tyPxkY+6A18aKtRuQUtFzQeze cuLqP7vaKNJoBMADQV7aNu1ZqFW5cUj03UHTod50EZ3Iay1Q2/H5IExBj1BfF+r1y+eZ 24tehqFoEWCqSUHEIFSrtJiPGX94D6IQipAw8l+uewhTcrOqiwHbuCu4DIHxJgdL7Lsm jllXnxFed7F2IktZjkXUat8KXVNW9eli8zdAxooeDHyRIgnj+rmMjmU3xH2N2X0HZBWK 0TV6pSM2Nol2RZC1KtHTcje27sm3v0n9YkvUXh51EUAm+ccEVMVMD1LD31EbJCHJ86Rn jnag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=fkaNmZExNvexpax6vpTVFC0ERbhvs5NzXZdOCGU7hoY=; b=kP5OYpw3xdBPLhAjAWQu9eD6ooe1DvBdpIboXoFcFaFxeJ6v95oV/wWZpVACjrePn1 QDzkAtr5j6iA3zKsB6CNXo8LYwmYu/LaJKfj7DK6EG8ohjSmvCiC4viSoswEEwTWz5L7 NtkQmfojEwCU4Zjy2p77LK66zNWxR5s8ptvMYs2csPsBtZ7FDX0/7dQF7HTaHbFcRf8C vK+vcH2GyiYPcdt8jR10PoqThSwL1TMMxsBZ9I3b1rz55cCCKZ3QsV1XIo5PI113SCLY AHSJ6DRYYk7Q2H7HWxvxOSVwsBdQILSph4ziO1Kv2ELx9wKpmqXqTvffp1mHE48jgf09 IMZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PZHnUCJ0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[220.239.117.135]) by smtp.gmail.com with ESMTPSA id h74sm140934699pfd.35.2019.01.10.04.17.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 Jan 2019 04:17:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 Jan 2019 23:17:28 +1100 Message-Id: <20190110121736.23448-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190110121736.23448-1-richard.henderson@linaro.org> References: <20190110121736.23448-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH 03/11] target/arm: Add BT and BTYPE to tb->flags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 ++ target/arm/translate.h | 4 ++++ target/arm/helper.c | 22 +++++++++++++++------- target/arm/translate-a64.c | 2 ++ 4 files changed, 23 insertions(+), 7 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8179c07250..506c490a16 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2990,6 +2990,8 @@ FIELD(TBFLAG_A64, TBII, 0, 2) FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) +FIELD(TBFLAG_A64, BT, 9, 1) +FIELD(TBFLAG_A64, BTYPE, 10, 2) static inline bool bswap_code(bool sctlr_b) { diff --git a/target/arm/translate.h b/target/arm/translate.h index bb37d35741..3d5e8bacac 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -69,6 +69,10 @@ typedef struct DisasContext { bool ss_same_el; /* True if v8.3-PAuth is active. */ bool pauth_active; + /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ + bool bt; + /* A copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. */ + uint8_t btype; /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ int c15_cpar; /* TCG op of the current insn_start. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 0e1bf521ab..138d9d5565 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13076,6 +13076,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, if (is_a64(env)) { ARMCPU *cpu = arm_env_get_cpu(env); + uint64_t sctlr; *pc = env->pc; flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); @@ -13120,6 +13121,12 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); } + if (current_el == 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + sctlr = env->cp15.sctlr_el[1]; + } else { + sctlr = env->cp15.sctlr_el[current_el]; + } if (cpu_isar_feature(aa64_pauth, cpu)) { /* * In order to save space in flags, we record only whether @@ -13127,17 +13134,18 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, * a nop, or "active" when some action must be performed. * The decision of which action to take is left to a helper. */ - uint64_t sctlr; - if (current_el == 0) { - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - sctlr = env->cp15.sctlr_el[1]; - } else { - sctlr = env->cp15.sctlr_el[current_el]; - } if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); } } + + if (cpu_isar_feature(aa64_bti, cpu)) { + /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ + if (sctlr & (current_el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { + flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1); + } + flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); + } } else { *pc = env->regs[15]; flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e43f0982f9..ca2ae40701 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13800,6 +13800,8 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->sve_excp_el = FIELD_EX32(tb_flags, TBFLAG_A64, SVEEXC_EL); dc->sve_len = (FIELD_EX32(tb_flags, TBFLAG_A64, ZCR_LEN) + 1) * 16; dc->pauth_active = FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE); + dc->bt = FIELD_EX32(tb_flags, TBFLAG_A64, BT); + dc->btype = FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE); dc->vec_len = 0; dc->vec_stride = 0; dc->cp_regs = arm_cpu->cp_regs; From patchwork Thu Jan 10 12:17:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155138 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1832113jaa; Thu, 10 Jan 2019 04:21:31 -0800 (PST) X-Google-Smtp-Source: ALg8bN5kQ02zKoVn+qFN6HL2MA69UAEh/PVpbgL/WF9OpyxOmd4jQjFAsSr9qvZigtL/qp5rYgrz X-Received: by 2002:adf:8228:: with SMTP id 37mr8748952wrb.160.1547122890992; Thu, 10 Jan 2019 04:21:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547122890; cv=none; d=google.com; s=arc-20160816; b=KbFzvnQqw1j3T/WNkV8LODpnug/RW4pf1sJEIC+o3mABaXq1zZOoQieaFOzDMx0Uay aOih/6pWMuSZe3InxyBrbD6rZffw7mXiu6AWDmSvWUOH69nRCGpqLZk4KWTHFMP+tFi8 hr//gHE3Di+yfhMZeivIdQ0Hs+BjTHGf14j1e5yHtDwvhzHih8+fasePvO5MdwR/VhmC D0wcCWXa3CzJz3u16bW8oJ2YZ58UOPplIVD35mj/amlXAgo78qxN3/2JxpSlp3oJUrYv FHO6CQWpyZeM2BE0py2bqCgDuW8t+tBgUaqncON6Y/g55vemThqJoNjYJowyIVAQ1IBG 2uBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=6iqUO+dfMicx3Wse2EXLLlldaaZeN5/b/MYFSpmB9uM=; b=cJ75S0QkblkZpxq5uJ9FHLtKpPmHm3d/7FMAN0qX5qb+rGWVLZi9RLal9biVfPzTJ9 flKNJFu9PE1jJB8qgLed1OSBQCt9d363JgjrKcD9GCgnBcDgipYZPQKJ03aRozwdEvDF A14bI7ZCTAkUesoU8uW2qi5GKS/a9ok2EupKRxSpCVHKCaKgmcviaphdpYTOQ6EKr1wY LVtrjosaO79/Kz4bzC67cVp1tUjEH+lem/KJCdbisOZDk3uMJIvgmNm7ksymhyEgysIX ctFDPLeYOZZVX7/iLlNTTeq+gWMyBAzFAAI/LRGXpHnt9TPGa8MUa2y7eW/+kjaGIs2G h0Ug== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=L6geguyR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[220.239.117.135]) by smtp.gmail.com with ESMTPSA id h74sm140934699pfd.35.2019.01.10.04.17.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 Jan 2019 04:17:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 Jan 2019 23:17:29 +1100 Message-Id: <20190110121736.23448-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190110121736.23448-1-richard.henderson@linaro.org> References: <20190110121736.23448-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH 04/11] target/arm: Record the GP bit for a page in MemTxAttrs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This isn't really a transaction attribute, but that's the most convenient place to hold a random bit of information within the softmmu tlb. Signed-off-by: Richard Henderson --- include/exec/memattrs.h | 2 ++ target/arm/helper.c | 6 ++++++ 2 files changed, 8 insertions(+) -- 2.17.2 diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index d4a1642098..39d61188e1 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -35,6 +35,8 @@ typedef struct MemTxAttrs { unsigned int secure:1; /* Memory access is usermode (unprivileged) */ unsigned int user:1; + /* Page is marked as "guarded" */ + unsigned int guarded:1; /* Requester ID (for MSI for example) */ unsigned int requester_id:16; } MemTxAttrs; diff --git a/target/arm/helper.c b/target/arm/helper.c index 138d9d5565..4e9ea2ed39 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9927,6 +9927,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, bool ttbr1_valid; uint64_t descaddrmask; bool aarch64 = arm_el_is_aa64(env, el); + bool guarded = false; /* TODO: * This code does not handle the different format TCR for VTCR_EL2. @@ -10098,6 +10099,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, } /* Merge in attributes from table descriptors */ attrs |= nstable << 3; /* NS */ + guarded |= extract64(descriptor, 50, 1); /* GP */ if (param.hpd) { /* HPD disables all the table attributes except NSTable. */ break; @@ -10143,6 +10145,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, */ txattrs->secure = false; } + /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */ + if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) { + txattrs->guarded = true; + } if (cacheattrs != NULL) { if (mmu_idx == ARMMMUIdx_S2NS) { From patchwork Thu Jan 10 12:17:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155148 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1837297jaa; Thu, 10 Jan 2019 04:27:21 -0800 (PST) X-Google-Smtp-Source: ALg8bN6BaGPJfpTivImjp6lXdtqKK+6ZTBinJJghunGw/BP+ewf244N7UlRnmegkY3aCJyd4KAd3 X-Received: by 2002:a1c:c70f:: with SMTP id x15mr9674055wmf.130.1547123241177; Thu, 10 Jan 2019 04:27:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547123241; cv=none; d=google.com; s=arc-20160816; b=FyeruogivoIl2ggb2hEWPkcu7GHTxzbr1ODUBK8n5wgNkHLWGx+dTwBmqP9uRz1vwI 4vVbEiJn3EQlej4Ml0LOD2+unfNpHbFRmNoJ/QlorlC+5sKICNLsSrHGnGfXEPEAJPeA 5P3aSG4MQ1PC1r8QG2xYj2rLULkVfmDwXzz4HjA10MpaXFYDPzdD0ENGxF/xFDfFJRdj +aN/UcnVT9F04ZSuQPewBEcNdRXKSVRONDG3+aXSxb56sMag8IgQusfYqgys802BUOZX 6pRFIGT+161DK8F/BebjvOMQRdTM2hhE4/cGZIFk4IotfPLtjtzue9Sw2YU2JRNRVF1L ka6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=/YB2L3OtfumYbatzc4HBobxII2tPYayqfJux+fHDtIY=; b=pCyci/nQFwrLV1FyqyJJbF3qVKSY4u4dytoFV7O2/Gr/ZQQTV1l94/zEwDIbS1CdXp oNzBRDbgmQP2MJSOpG1wUDKnjagWQNnbwn0zI4cm3LoYokUF87F/jC9EhF28oHoWIL0S J2+/K4KOP35atbnf3gbrTm/POGsbR//GjPFZc7y2A7CI8Jwduifcx/zzQk29+TBls19y iCeulDwI89pLzTqiXNvkZveALtkvfyGc78+3GXftdtxHvgQiNt6NxiBancqXAAooEvhH ljrgk4IRQdko78zfhC/kIgPXlpO5PRcJxwibFJ6j0DXWJfq2rjEvV3dzVuimtma6XoSb IEag== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HWYtGytL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[220.239.117.135]) by smtp.gmail.com with ESMTPSA id h74sm140934699pfd.35.2019.01.10.04.17.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 Jan 2019 04:17:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 Jan 2019 23:17:30 +1100 Message-Id: <20190110121736.23448-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190110121736.23448-1-richard.henderson@linaro.org> References: <20190110121736.23448-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH 05/11] target/arm: Default handling of BTYPE during translation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The branch target exception for guarded pages has high priority, and only 8 instructions are valid for that case. Perform this check before doing any other decode. Clear BTYPE after all insns that neither set BTYPE nor exit via exception (DISAS_NORETURN). Not yet handled are insns that exit via DISAS_NORETURN for some other reason, like direct branches. Signed-off-by: Richard Henderson --- target/arm/internals.h | 6 ++ target/arm/translate.h | 9 ++- target/arm/translate-a64.c | 139 +++++++++++++++++++++++++++++++++++++ 3 files changed, 152 insertions(+), 2 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/internals.h b/target/arm/internals.h index a6fd4582b2..d01a3f9f44 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -268,6 +268,7 @@ enum arm_exception_class { EC_FPIDTRAP = 0x08, EC_PACTRAP = 0x09, EC_CP14RRTTRAP = 0x0c, + EC_BTITRAP = 0x0d, EC_ILLEGALSTATE = 0x0e, EC_AA32_SVC = 0x11, EC_AA32_HVC = 0x12, @@ -439,6 +440,11 @@ static inline uint32_t syn_pactrap(void) return EC_PACTRAP << ARM_EL_EC_SHIFT; } +static inline uint32_t syn_btitrap(int btype) +{ + return (EC_BTITRAP << ARM_EL_EC_SHIFT) | btype; +} + static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) { return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) diff --git a/target/arm/translate.h b/target/arm/translate.h index 3d5e8bacac..f73939d7b4 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -71,8 +71,13 @@ typedef struct DisasContext { bool pauth_active; /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ bool bt; - /* A copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. */ - uint8_t btype; + /* + * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. + * < 0, set by the current instruction. + */ + int8_t btype; + /* True if this page is guarded. */ + bool guarded_page; /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ int c15_cpar; /* TCG op of the current insn_start. */ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ca2ae40701..68eb27089a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -128,6 +128,16 @@ static inline int get_a64_user_mem_index(DisasContext *s) return arm_to_core_mmu_idx(useridx); } +static void reset_btype(DisasContext *s) +{ + if (s->btype != 0) { + TCGv_i32 zero = tcg_const_i32(0); + tcg_gen_st_i32(zero, cpu_env, offsetof(CPUARMState, btype)); + tcg_temp_free_i32(zero); + s->btype = 0; + } +} + void aarch64_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags) { @@ -13716,6 +13726,90 @@ static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn) } } +/** + * is_guarded_page: + * @env: The cpu environment + * @s: The DisasContext + * + * Return true if the page is guarded. + */ +static bool is_guarded_page(CPUARMState *env, DisasContext *s) +{ +#ifdef CONFIG_USER_ONLY + return false; /* FIXME */ +#else + uint64_t addr = s->base.pc_first; + int mmu_idx = arm_to_core_mmu_idx(s->mmu_idx); + unsigned int index = tlb_index(env, mmu_idx, addr); + CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); + + /* + * We test this immediately after reading an insn, which means + * that any normal page must be in the TLB. The only exception + * would be for executing from flash or device memory, which + * does not retain the TLB entry. + * + * FIXME: Assume false for those, for now. We could use + * arm_cpu_get_phys_page_attrs_debug to re-read the page + * table entry even for that case. + */ + return (tlb_hit(entry->addr_code, addr) && + env->iotlb[mmu_idx][index].attrs.guarded); +#endif +} + +/** + * btype_destination_ok: + * @insn: The instruction at the branch destination + * @bt: SCTLR_ELx.BT + * @btype: PSTATE.BTYPE, and is non-zero + * + * On a guarded page, there are a limited number of insns + * that may be present at the branch target: + * - branch target identifiers, + * - paciasp, pacibsp, + * - BRK insn + * - HLT insn + * Anything else causes a Branch Target Exception. + * + * Return true if the branch is compatible, false to raise BTITRAP. + */ +static bool btype_destination_ok(uint32_t insn, bool bt, int btype) +{ + if ((insn & 0xfffff01fu) == 0xd503201fu) { + /* HINT space */ + switch (extract32(insn, 5, 7)) { + case 031: /* PACIASP */ + case 033: /* PACIBSP */ + /* + * If SCTLR_ELx.BT, then PACI*SP are not compatible + * with btype == 3. Otherwise all btype are ok. + */ + return !bt || btype != 3; + case 040: /* BTI */ + /* Not compatible with any btype. */ + return false; + case 042: /* BTI c */ + /* Not compatible with btype == 3 */ + return btype != 3; + case 044: /* BTI j */ + /* Not compatible with btype == 2 */ + return btype != 2; + case 046: /* BTI jc */ + /* Compatible with any btype. */ + return true; + } + } else { + switch (insn & 0xffe0001fu) { + case 0xd4200000u: /* BRK */ + case 0xd4400000u: /* HLT */ + /* Give priority to the breakpoint exception. */ + return true; + } + } + return false; +} + /* C3.1 A64 instruction index by encoding */ static void disas_a64_insn(CPUARMState *env, DisasContext *s) { @@ -13727,6 +13821,43 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s) s->fp_access_checked = false; + if (dc_isar_feature(aa64_bti, s)) { + if (s->base.num_insns == 1) { + /* + * At the first insn of the TB, compute s->guarded_page. + * We delayed computing this until successfully reading + * the first insn of the TB, above. This (mostly) ensures + * that the softmmu tlb entry has been populated, and the + * page table GP bit is available. + * + * Note that we need to compute this even if btype == 0, + * because this value is used for BR instructions later + * where ENV is not available. + */ + s->guarded_page = is_guarded_page(env, s); + + /* First insn can have btype set to non-zero. */ + tcg_debug_assert(s->btype >= 0); + + /* + * Note that the Branch Target Exception has fairly high + * priority -- below debugging exceptions but above most + * everything else. This allows us to handle this now + * instead of waiting until the insn is otherwise decoded. + */ + if (s->btype != 0 + && s->guarded_page + && !btype_destination_ok(insn, s->bt, s->btype)) { + gen_exception_insn(s, 4, EXCP_UDEF, syn_btitrap(s->btype), + default_exception_el(s)); + return; + } + } else { + /* Not the first insn: btype must be 0. */ + tcg_debug_assert(s->btype == 0); + } + } + switch (extract32(insn, 25, 4)) { case 0x0: case 0x1: case 0x3: /* UNALLOCATED */ unallocated_encoding(s); @@ -13763,6 +13894,14 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s) /* if we allocated any temporaries, free them here */ free_tmp_a64(s); + + /* + * After execution of most insns, btype is reset to 0. + * Note that we set btype == -1 when the insn sets btype. + */ + if (s->btype > 0 && s->base.is_jmp != DISAS_NORETURN) { + reset_btype(s); + } } static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, From patchwork Thu Jan 10 12:17:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155151 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1837674jaa; Thu, 10 Jan 2019 04:27:48 -0800 (PST) X-Google-Smtp-Source: ALg8bN5710HvuyBxdTs5O2YPuPSjxEcMEwrgQV+yd54L6EXWH9aUQGRGV4SHdIYIdkiwUgxjH6MN X-Received: by 2002:adf:e34b:: with SMTP id n11mr8552538wrj.91.1547123268095; Thu, 10 Jan 2019 04:27:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547123268; cv=none; d=google.com; s=arc-20160816; b=I3dbKhXVtxw+c5tK+NLDzr7aAiOYpCWSvWQozjRLmfHD2ILOnkUAkG/66b8mBA32Fe 1/B9lAVfEfEFTRiRP65DUSyspJhGXkLrtEhKePQi+YMKBK5Exnh1YlKVj/g/FhY9Fs3Z VmV94FxmIGOcjvrzTkKwhkgFv3HWgRE/WcdbdnJJwNhw1tG2ij9OcF6t+NMa8zrVaPQ6 6f7POc6VSIZgvzbIQgSxXOHDdu+QpFLsASwiRnbahbn/BAlRaLA7SpxxuxEuLMx7BlHg HF3zVfmZWmP3xWhjrHAHSJradR6wRjZ0NdymaUt51PNgICPjVymlRaFL1zDcqe2jQZEb LUgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=XRiJh3WKJG2YABKLlUHfm4ue/ZPukKnI+eeZ63W9pjg=; b=R4Agy0IActqixZ5g/FpECwZZwUmztIhdaYyg5h5jBAJrmXzRvBCB1LGiyGccxfFyeJ DX9PtZUHp1LP9C/udSqDGeuVbJi3WMxuXfyKsd5Hob6Jp7LdWkvtU1RC6tjLIOtRLP7t eoYxeTSqfdOyD2J2fje9ZczzZcp4mYqPmaq301vHNPN0qH7AYQkLbvHOpiU01X9RccmZ 2T+tqV0aHyjQreo99sdODbdwuB6Ee6VJO76/0l2+DmjndTU9M7bTi76L6fpQrYyI0nB1 acLTonKTiwae4tVkzguVl1XvNpLLzIrfGI8nF1XPhadvlK6ZgzsdkCApLO5cGe3Luulq OUUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=V0fTXv6l; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[220.239.117.135]) by smtp.gmail.com with ESMTPSA id h74sm140934699pfd.35.2019.01.10.04.17.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 Jan 2019 04:17:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 Jan 2019 23:17:31 +1100 Message-Id: <20190110121736.23448-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190110121736.23448-1-richard.henderson@linaro.org> References: <20190110121736.23448-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 06/11] target/arm: Reset btype for direct branches and syscalls X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is all of the non-exception cases of DISAS_NORETURN. For the rest of the synchronous exceptions, the state of SPSR_ELx.BTYPE is CONSTRAINED UNPREDICTABLE. However, it makes more sense to me to have syscalls reset BTYPE. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 68eb27089a..f319fa000e 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1362,6 +1362,7 @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) } /* B Branch / BL Branch with link */ + reset_btype(s); gen_goto_tb(s, 0, addr); } @@ -1386,6 +1387,7 @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn) tcg_cmp = read_cpu_reg(s, rt, sf); label_match = gen_new_label(); + reset_btype(s); tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, tcg_cmp, 0, label_match); @@ -1415,6 +1417,8 @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn) tcg_cmp = tcg_temp_new_i64(); tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos)); label_match = gen_new_label(); + + reset_btype(s); tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, tcg_cmp, 0, label_match); tcg_temp_free_i64(tcg_cmp); @@ -1441,6 +1445,7 @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn) addr = s->pc + sextract32(insn, 5, 19) * 4 - 4; cond = extract32(insn, 0, 4); + reset_btype(s); if (cond < 0x0e) { /* genuinely conditional branches */ TCGLabel *label_match = gen_new_label(); @@ -1605,6 +1610,7 @@ static void handle_sync(DisasContext *s, uint32_t insn, * a self-modified code correctly and also to take * any pending interrupts immediately. */ + reset_btype(s); gen_goto_tb(s, 0, s->pc); return; default: @@ -1885,6 +1891,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) switch (op2_ll) { case 1: /* SVC */ gen_ss_advance(s); + reset_btype(s); gen_exception_insn(s, 0, EXCP_SWI, syn_aa64_svc(imm16), default_exception_el(s)); break; @@ -1899,6 +1906,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) gen_a64_set_pc_im(s->pc - 4); gen_helper_pre_hvc(cpu_env); gen_ss_advance(s); + reset_btype(s); gen_exception_insn(s, 0, EXCP_HVC, syn_aa64_hvc(imm16), 2); break; case 3: /* SMC */ @@ -1911,6 +1919,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) gen_helper_pre_smc(cpu_env, tmp); tcg_temp_free_i32(tmp); gen_ss_advance(s); + reset_btype(s); gen_exception_insn(s, 0, EXCP_SMC, syn_aa64_smc(imm16), 3); break; default: From patchwork Thu Jan 10 12:17:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155141 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1835040jaa; Thu, 10 Jan 2019 04:24:47 -0800 (PST) X-Google-Smtp-Source: ALg8bN5ClgoLgkig4zEZkkagTqIyOxRTE6l11DKDBMJwpTArJy/3vhKpgi2j/XrHYLfKe0cFfg7G X-Received: by 2002:a1c:8acf:: with SMTP id m198mr10316470wmd.143.1547123086992; Thu, 10 Jan 2019 04:24:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547123086; cv=none; d=google.com; s=arc-20160816; b=XAEcDAS+JD37yuA/8Ai8UkHnvKtnrqBewlcykrYu9BDezBrx0KW+loyCuOKgUeh0N9 +qzWaBy5eCgiEKYEJUiqWvgUXX/cdPVcC/cSIIOAwYXaT+m5kvt/GVebbQewh94XyPxQ zDY+PBs7xcJ/BN+ESdNWZJlp3Ij0DHzm/oail5tUiOpDmh67ISOM31cnTKhaDhenh0Vp dEXuWOmO6caaz8G+pmmk6Ls5FtN7KuAfpCEEkeRrfNKHQv2XWYFIJWsrzzUYq1cHUhwF rAwtuFD7YIwkhITy+3AKYK5ig6/QGAkMHPZyxEyd1RxtdWg76cA+F5PLd/l0TEp00Nj2 QEeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=PRWaIbFhaCG50KtAhIfgw4/3zpMsZFNNO0ITZ9DcBeA=; b=pZHq52lPvtQDKMhHHakStHq97l7MSm6y8/sn91iJ+C4DuBGzJ2R/gIFjAWCRs9Mcq1 S0G7uSCx0dVOh6xJmvyiKIjOv1J85D7VLkAz3+bTd7tor5wdhEbjyMzaC0AmL8uU8lQ6 bo2k4IF0U37xUkA5W1IO8qP7UrTU9yQZG+OrqY7Rjyw0kG7NuPc74PQZWOor+CuoLFQO Et2JJZUDFl6D9QHLdgpl1ALOkLTuHNgiB9lkzkyzgpvjfq4rMJ5Z/HXvdn5+3qFAsgcM LaxwNnWKtiaCm+6rgq2sRX0dMNrBdoRtarf6ilAlKFzkU2JI3Z1/ADXzbo+uXvxUqDlp dfYA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NzarwsFO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[220.239.117.135]) by smtp.gmail.com with ESMTPSA id h74sm140934699pfd.35.2019.01.10.04.17.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 Jan 2019 04:18:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 Jan 2019 23:17:32 +1100 Message-Id: <20190110121736.23448-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190110121736.23448-1-richard.henderson@linaro.org> References: <20190110121736.23448-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42d Subject: [Qemu-devel] [PATCH 07/11] target/arm: Set btype for indirect branches X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f319fa000e..5f0ecb297f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -138,6 +138,19 @@ static void reset_btype(DisasContext *s) } } +static void set_btype(DisasContext *s, int val) +{ + TCGv_i32 tcg_val; + + /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */ + tcg_debug_assert(val >= 1 && val <= 3); + + tcg_val = tcg_const_i32(val); + tcg_gen_st_i32(tcg_val, cpu_env, offsetof(CPUARMState, btype)); + tcg_temp_free_i32(tcg_val); + s->btype = -1; +} + void aarch64_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags) { @@ -1985,6 +1998,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) { unsigned int opc, op2, op3, rn, op4; + unsigned btype_mod = 2; TCGv_i64 dst; TCGv_i64 modifier; @@ -2002,6 +2016,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) case 0: /* BR */ case 1: /* BLR */ case 2: /* RET */ + btype_mod = opc; switch (op3) { case 0: /* BR, BLR, RET */ @@ -2045,7 +2060,6 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) default: goto do_unallocated; } - gen_a64_set_pc(s, dst); /* BLR also needs to load return address */ if (opc == 1) { @@ -2061,6 +2075,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) if (op3 != 2 || op3 != 3) { goto do_unallocated; } + btype_mod = opc & 1; if (s->pauth_active) { dst = new_tmp_a64(s); modifier = cpu_reg_sp(s, op4); @@ -2144,6 +2159,26 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) return; } + switch (btype_mod) { + case 0: /* BR */ + if (dc_isar_feature(aa64_bti, s)) { + /* BR to {x16,x17} or !guard -> 1, else 3. */ + set_btype(s, rn == 16 || rn == 17 || !s->guarded_page ? 1 : 3); + } + break; + + case 1: /* BLR */ + if (dc_isar_feature(aa64_bti, s)) { + /* BLR sets BTYPE to 2, regardless of source guarded page. */ + set_btype(s, 2); + } + break; + + default: /* RET or none of the above. */ + /* BTYPE will be set to 0 by normal end-of-insn processing. */ + break; + } + s->base.is_jmp = DISAS_JUMP; } From patchwork Thu Jan 10 12:17:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155149 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1837413jaa; Thu, 10 Jan 2019 04:27:29 -0800 (PST) X-Google-Smtp-Source: ALg8bN4rPawE86L2rErMDW8RB1zWrggfy8H7fbaRRtaRq/CLhdPN5/lorlqsGX0AeHC6mwCeQuqy X-Received: by 2002:a05:6000:8a:: with SMTP id m10mr8824787wrx.79.1547123249517; Thu, 10 Jan 2019 04:27:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547123249; cv=none; d=google.com; s=arc-20160816; b=EitKsjZRxmvs1GguXDKhMVuJ+rovnCcbLqEwtLwTQj/Am5au0KrlmPj1Wq4hcI340T jn7mk+9aSv3S47KobRfVrSNfkESnzi+vVwn1Yo7xnA9iUB9rLSxWpXf6TnHj9oQj2kPQ /aIb3+n0CzoeRVrzrttn7LNln7KX7TMem9deI+Ct0q3rO1yh3R4WyKlVMvc1JxNYjcHg 5GAvFY4jC9Ip+NSW9RXQ+c3QNyFzbwlrsz/j4w0fhsRn+Mv0UNPZ+CCGvrWNP+QMue1y EzW97YYtUaQPNzpDRCbWaKL6YXEEQp3/XoMD0x3tr8q/o5nSxOQ8jJh+cI0gsT2/nzuo yjMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=YHh3MpNr2I+etho4t8QqJysbEK1iGomhou5bx9QcAMY=; b=xiiLNtDrd6fpZuGTg0W6izfd0oz7TCIywPw96ZF+xVCxh0mdW4LH8WGS33d19QF4Kg xi6jpXj/M6xPMavprXc+Rzo0UI1z0+auI3u539W+Dk3v69XqxDfkVkqgv+h1ZijxmXZY EFU1ya6zKTKCKJPmGFEas0YL22D8+XHRRzSOBuHmVqoLtf0GrqFzP1gLZ5L/swLstVKH TwmRflMkRHl1OikH3fgBx+T4DYJ2mgXwb1fBo7WBGVQHhZg8ZKFG9g0XvIxMEA/uWWg1 za705vdbuHtULHDY+8Qq+4ZvI0dlV6inycGlUsBvFmjX5q3uRTpFNBIRRgBeP+84vC3P wlAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZSICzhI5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[220.239.117.135]) by smtp.gmail.com with ESMTPSA id h74sm140934699pfd.35.2019.01.10.04.18.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 Jan 2019 04:18:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 Jan 2019 23:17:33 +1100 Message-Id: <20190110121736.23448-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190110121736.23448-1-richard.henderson@linaro.org> References: <20190110121736.23448-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 08/11] target/arm: Add guarded_pages cpu property for user-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" While waiting for a proper userland ABI, allow static test cases to be written assuming that GP is set for all pages. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 4 ++++ target/arm/cpu64.c | 18 ++++++++++++++++++ target/arm/translate-a64.c | 8 +++++++- 3 files changed, 29 insertions(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 506c490a16..929f16dd6b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -882,6 +882,10 @@ struct ARMCPU { */ bool cfgend; +#ifdef CONFIG_USER_ONLY + bool guarded_pages; +#endif + QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; QLIST_HEAD(, ARMELChangeHook) el_change_hooks; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d0de0d5dcf..713d2d5579 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -315,6 +315,18 @@ static void cpu_max_set_packey(Object *obj, Visitor *v, const char *name, } error_propagate(errp, err); } + +static bool aarch64_cpu_get_guarded_pages(Object *obj, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + return cpu->guarded_pages; +} + +static void aarch64_cpu_set_guarded_pages(Object *obj, bool val, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + cpu->guarded_pages = val; +} #endif /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); @@ -420,6 +432,12 @@ static void aarch64_max_initfn(Object *obj) cpu->env.cp15.sctlr_el[1] |= SCTLR_EnIA | SCTLR_EnIB; cpu->env.cp15.sctlr_el[1] |= SCTLR_EnDA | SCTLR_EnDB; } + + object_property_add_bool(obj, "guarded_pages", + aarch64_cpu_get_guarded_pages, + aarch64_cpu_set_guarded_pages, NULL); + object_property_set_description(obj, "guarded_pages", + "Set on/off GuardPage bit for all pages", NULL); #endif cpu->sve_max_vq = ARM_MAX_VQ; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 5f0ecb297f..f225517077 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13780,7 +13780,13 @@ static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn) static bool is_guarded_page(CPUARMState *env, DisasContext *s) { #ifdef CONFIG_USER_ONLY - return false; /* FIXME */ + /* + * FIXME: What is the userland ABI for this? + * For the moment this is controlled by an attribute: + * -cpu max,guarded_pages=on. + */ + ARMCPU *cpu = arm_env_get_cpu(env); + return cpu->guarded_pages; #else uint64_t addr = s->base.pc_first; int mmu_idx = arm_to_core_mmu_idx(s->mmu_idx); From patchwork Thu Jan 10 12:17:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155142 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1835107jaa; Thu, 10 Jan 2019 04:24:51 -0800 (PST) X-Google-Smtp-Source: ALg8bN7ideO1ARaP+yGbsnv5dDkxjXfyk0za78o+HOJvMuDLUWvHVTFhVeQRo9NkppD/sPuHQTwc X-Received: by 2002:a1c:bc82:: with SMTP id m124mr9469009wmf.77.1547123090984; Thu, 10 Jan 2019 04:24:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547123090; cv=none; d=google.com; s=arc-20160816; b=hb5GZ2aHo2VBeRqhxs9l3R70aAE9+Cq1ZiEEXyiYZp0CIBAMREUEChoCGlioK4M4xa LTJk+cZFg15w975yTWEkUcSU2lcQjlNWbODfKgMbGCiePZFXoQ63K4zEZETbI2pmLJsa GmRsX0a01r2rHS+Re4HT8Mm8/P2upiK2pcabv7vKMRyAzJEdX86QUB7Nwrg5Wp/10DP6 yV17n3fU/lsc2aUvkfbuz1CpSU0dNXg4zgg87gfXm4j0CS6xBRi7AGJOCXt407GtLdns QOhbWCwib7umE0YJ6YIF+ZvZcivUV/PCHIzCTKtWTTMNY4ca5ulGXL83m1J6hk0YnvCJ 24uQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=2xcblPi8ob/nT206QUAh9O3OrdajZ4sfTdq1UgATXq4=; b=bGhqO2OZQXIPkUAHGp/cDFmT4ByIjpEKqo71tmfdfUNn0Ul2kxrgXX3T9HbKzUC/WX 2sfwH4xHVK2KNfNZYd8eWJqtfsk0FhDnNT+X0XsfYYd4iqzSELvSW9avpTLwMMTioged oEp8S6nmam3TT8obgqTle2yVaI68zOkMu7quP0lfiC4JJYTEr0/5Y6mR57mw0IJzvpn4 lKpR0hf+NerpdnyKMuabkp7h7O9BZaRGtATPVJ0nCIOyme3hHaPOunBh9O5NdqsVodxp LdK0ecUpoKZwYiBKiyDVVYUdqavNajNBzjEXuEIy27TQ9x8PZDO0pD3asKHyd7S2JuS+ DqYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=FVMyaHBl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[220.239.117.135]) by smtp.gmail.com with ESMTPSA id h74sm140934699pfd.35.2019.01.10.04.18.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 Jan 2019 04:18:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 Jan 2019 23:17:34 +1100 Message-Id: <20190110121736.23448-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190110121736.23448-1-richard.henderson@linaro.org> References: <20190110121736.23448-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH 09/11] target/arm: Enable BTI for -cpu max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 713d2d5579..64fbe75eca 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -372,6 +372,10 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); cpu->isar.id_aa64pfr0 = t; + t = cpu->isar.id_aa64pfr1; + t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); + cpu->isar.id_aa64pfr1 = t; + t = cpu->isar.id_aa64mmfr1; t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); From patchwork Thu Jan 10 12:17:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155150 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1837483jaa; Thu, 10 Jan 2019 04:27:35 -0800 (PST) X-Google-Smtp-Source: ALg8bN7V+QrXd4mCvLfgidGYFNUdfRo0EK32u1SnMFkluN9DId+R9wW7pw43u0KZWfJIQi0KTaIW X-Received: by 2002:adf:fc89:: with SMTP id g9mr6604995wrr.96.1547123255201; Thu, 10 Jan 2019 04:27:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547123255; cv=none; d=google.com; s=arc-20160816; b=q/yWQr58Z+giotX1g7a8V9IOtTfh5mhcbXoadueMpcbsR0yCUH7U47c9JSS+8so9V1 cp5t9yDXF7ifbLfjvoJVw2zFhXGEhr2g0Pq5/3IVA8jPauHGKGDYiQXZHaofYu6A5JO/ H6fsz8ByUgDPpd5+oARJG/whr14LpRmMgRtpJH6wQPOlRGvolTBnO5KS80PdMTQ90UrQ Zz8iAJvsUHtzGic63q7RSc/s2Nc8sBpAGVA9zyIJgJTc5ucD86sXsmX//8bvAhMPzJ7O i/mh8Oj72ROAKcTq6QCFAWb+YF+6rWfx8YdiyFMc2Ey1BTq+2aXf4+1IpU8ot0mUOktx 6kXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=p2TU+6xewpFPfZjXVs3cgyi3ohvpda2DuzV/stCY8oE=; b=0/ij/ds9nNS9IKQmitAHb7P8RYry0FntPHP8ZNHJshskHASf2qqBrO6067FjBmqr9R 3CSEC/CHyUkwhQzCUGB2GLrnqRnkY+wYg/wH+OuQxD2F60NfqluSv8ZusYRHLed2SNr5 nP/LaxxWKwbYoQ2xcToi8OA5ypEgctgIHShzOdv7pzYphoQCAtFoIBY7w5065jRFCAAH 7/349QYebzfpjxa2do1e+unxLgM5N5jGse7t7jiOj/GaFBjLdXdOwoCoJ7mMzToOmx0D ZyQMejTmx8yGDl2QgoFBlbrOg2pUoXUXjrlA3UU6rH7FrpYM80JZL7lhNxiWMVWqEin7 DHCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AJuLh51m; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s7si42293005wru.343.2019.01.10.04.27.34 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 10 Jan 2019 04:27:35 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AJuLh51m; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:58335 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ghZQs-00035E-4v for patch@linaro.org; Thu, 10 Jan 2019 07:27:34 -0500 Received: from eggs.gnu.org ([209.51.188.92]:56172) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ghZI2-0004nh-3S for qemu-devel@nongnu.org; Thu, 10 Jan 2019 07:18:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ghZHu-0007nY-I2 for qemu-devel@nongnu.org; Thu, 10 Jan 2019 07:18:22 -0500 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:38951) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ghZHo-0007kU-6W for qemu-devel@nongnu.org; Thu, 10 Jan 2019 07:18:13 -0500 Received: by mail-pl1-x641.google.com with SMTP id 101so5114634pld.6 for ; Thu, 10 Jan 2019 04:18:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=p2TU+6xewpFPfZjXVs3cgyi3ohvpda2DuzV/stCY8oE=; b=AJuLh51mCjv+PuR7LJlWLy0+bBdGQxM2YHVFZgU8IqRAy9ye5EVa2UVVT7/OQnnMlZ JIajoHJVxnWpRvchgc2UYuoVn4+TQecYAZ7ltNTJogNVDA/rpZTnzm9tt8gAh9Sm3c8l w3pYWSdzUSO25Vr66BKyqwPHBEUA5YJJRW59s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=p2TU+6xewpFPfZjXVs3cgyi3ohvpda2DuzV/stCY8oE=; b=LeFGlfl9i0qjXJ73bVbDP9GSDxmwFE0eK7yhT+he+kG314GNjq7FJw5Yc/IFYXoF0T 89vIGF/yoTgO0C4gv4Dm1KJ8bBLUEiwazqbGY3+pbfxchrfnjaHUNHWwghKFBX4bJLY+ AYUPeoTtxrqa00WkSq0xY/P7cvSHesrcWh4L/2Ml85Rtj5C6B9kyQN/8sQxPjUnkXuZA YamXgchPgN0Ay/mkIcwqMuEDDMCDzXRBHEx0VepAZHxj3D9uckxAa6KmXeWiAb0kjw1V myqPxDuK8F/8kJ4P3QwWzbxWfC7R8D3UCr85EWNzQAAlBTyCrch19n3DCM6T+azlKBgy BCkA== X-Gm-Message-State: AJcUukftJz2TDyrAPDDlRgkKNV99fUAXSWot9zq+aXoHWkcbBj9KFdpy gQmGPCrluHwkxCUYk7VDL0XhKh8axAr3eg== X-Received: by 2002:a17:902:ba89:: with SMTP id k9mr10262428pls.189.1547122688704; Thu, 10 Jan 2019 04:18:08 -0800 (PST) Received: from cloudburst.twiddle.net (c220-239-117-135.belrs4.nsw.optusnet.com.au. [220.239.117.135]) by smtp.gmail.com with ESMTPSA id h74sm140934699pfd.35.2019.01.10.04.18.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 Jan 2019 04:18:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 Jan 2019 23:17:35 +1100 Message-Id: <20190110121736.23448-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190110121736.23448-1-richard.henderson@linaro.org> References: <20190110121736.23448-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH 10/11] linux-user/aarch64: Reset btype for signal handlers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" It does not make sense for a SIGILL handler to enter with the btype set as for the indirect branch that caused the SIGILL. Nor does it make sense to return from a handler with BTYPE set. This could be argued to be the handler's job, setting BTYPE within ucontext->uc_mcontext.pstate, but handling this here while the ABI is undiscussed. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.2 diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index f84a9cf28a..1fb229e696 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -218,6 +218,8 @@ static void target_restore_general_frame(CPUARMState *env, __get_user(env->pc, &sf->uc.tuc_mcontext.pc); __get_user(pstate, &sf->uc.tuc_mcontext.pstate); pstate_write(env, pstate); + /* Reset btype that might have been there going into the frame. */ + env->btype = 0; } static void target_restore_fpsimd_record(CPUARMState *env, @@ -510,6 +512,8 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, env->xregs[29] = frame_addr + fr_ofs; env->pc = ka->_sa_handler; env->xregs[30] = return_addr; + /* Reset btype going into the signal handler. */ + env->btype = 0; if (info) { tswap_siginfo(&frame->info, info); env->xregs[1] = frame_addr + offsetof(struct target_rt_sigframe, info); From patchwork Thu Jan 10 12:17:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155152 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1839238jaa; Thu, 10 Jan 2019 04:29:40 -0800 (PST) X-Google-Smtp-Source: ALg8bN77P69KRFDDwxZMXeelmwhOh869nhgzwSM0OzZoMdxyhjo25gKB3K+C3ojn0HnHtUjgG0z5 X-Received: by 2002:a7b:c08f:: with SMTP id r15mr9946048wmh.118.1547123380428; Thu, 10 Jan 2019 04:29:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547123380; cv=none; d=google.com; s=arc-20160816; b=OrJcp4tZevnAloeh3PNeJhrQBo+zg/967lS9BxqiQ+Wo7NTXpKnM9ySe2Tlj1+GBpt lgNvn056R6PodyhBIIqIMqeodOZ1a7ju34c1OfvwxWaqokF7m98OunG0D8K/AkVTs0f8 MCiC06Jl+tmXvUb8nB6iMXqLYg8gfLaFeQ0IquORviaqwG+ViQOGpNIbNAkLZuaQj3s1 bHtggWW/j8FcClBOv8nWAHTgTEqdXm2f6GorLqqsZ9yyYgFNu3JSx6k5SNuW2Ofth0xj L0QXgs7/JGDMdZOQlmweW2rClUdWUjwC1rd3FnjtSQG+KfX3egJakyQHIiKgzTLgGLEx DCcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=DkHGGDD7DZ0xeYnvEOJO+AcazmZv0MJI3ad+LhKQaBM=; b=HgdtETFUyBMaLatmWNiHrLhu6vrDSAKEhqG1JX8TDRyUCaKk9F6QNw2dTjLpDc0oWx bPqGaEAE+XZRWhJrwTXDlsuFie2mqt72CrMzg5FSezeEvbmM6O66g/TnghduLsPUyKgc oR0+QKI6sxTzZUBOO2qUGKD7b028lEvgHWfNyCO2fEB9FThKlXT6tIZqPMKOsrjMcgzK +vhzQJhDSJG8O68koggkeH8OBemhuui28qPjD74HscDyrEDTksXOdzKK65dM0ynjOw0V 4/zi96qy6n5Et1wGMrt3+cnLVmUE3VS1+R2mrxpVhN12BC14iUVbVNsIVC5cWDfZaX3s H9kQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZWbOKnno; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[220.239.117.135]) by smtp.gmail.com with ESMTPSA id h74sm140934699pfd.35.2019.01.10.04.18.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 Jan 2019 04:18:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 Jan 2019 23:17:36 +1100 Message-Id: <20190110121736.23448-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190110121736.23448-1-richard.henderson@linaro.org> References: <20190110121736.23448-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH 11/11] tests/tcg/aarch64: Add bti smoke test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tests/tcg/aarch64/bti-1.c | 61 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/bti-crt.inc.c | 51 ++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 7 +++- 3 files changed, 118 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/aarch64/bti-1.c create mode 100644 tests/tcg/aarch64/bti-crt.inc.c -- 2.17.2 diff --git a/tests/tcg/aarch64/bti-1.c b/tests/tcg/aarch64/bti-1.c new file mode 100644 index 0000000000..fa8a521a47 --- /dev/null +++ b/tests/tcg/aarch64/bti-1.c @@ -0,0 +1,61 @@ +/* + * Branch target identification, basic notskip cases. + */ + +#include "bti-crt.inc.c" + +static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc) +{ + uc->uc_mcontext.pc += 8; +} + +#define NOP "nop" +#define BTI_N "hint #32" +#define BTI_C "hint #34" +#define BTI_J "hint #36" +#define BTI_JC "hint #38" + +#define BTYPE_1(DEST) \ + asm("mov %0,#1; adr x16, 1f; br x16; 1: " DEST "; mov %0,#0" \ + : "=r"(skipped) : : "x16") + +#define BTYPE_2(DEST) \ + asm("mov %0,#1; adr x16, 1f; blr x16; 1: " DEST "; mov %0,#0" \ + : "=r"(skipped) : : "x16", "x30") + +#define BTYPE_3(DEST) \ + asm("mov %0,#1; adr x15, 1f; br x15; 1: " DEST "; mov %0,#0" \ + : "=r"(skipped) : : "x15") + +#define TEST(WHICH, DEST, EXPECT) \ + do { WHICH(DEST); fail += skipped ^ EXPECT; } while (0) + + +int main() +{ + int fail = 0; + int skipped; + + /* Signal-like with SA_SIGINFO. */ + signal_info(SIGILL, skip2_sigill); + + TEST(BTYPE_1, NOP, 1); + TEST(BTYPE_1, BTI_N, 1); + TEST(BTYPE_1, BTI_C, 0); + TEST(BTYPE_1, BTI_J, 0); + TEST(BTYPE_1, BTI_JC, 0); + + TEST(BTYPE_2, NOP, 1); + TEST(BTYPE_2, BTI_N, 1); + TEST(BTYPE_2, BTI_C, 0); + TEST(BTYPE_2, BTI_J, 1); + TEST(BTYPE_2, BTI_JC, 0); + + TEST(BTYPE_3, NOP, 1); + TEST(BTYPE_3, BTI_N, 1); + TEST(BTYPE_3, BTI_C, 1); + TEST(BTYPE_3, BTI_J, 0); + TEST(BTYPE_3, BTI_JC, 0); + + return fail; +} diff --git a/tests/tcg/aarch64/bti-crt.inc.c b/tests/tcg/aarch64/bti-crt.inc.c new file mode 100644 index 0000000000..ef7831ad76 --- /dev/null +++ b/tests/tcg/aarch64/bti-crt.inc.c @@ -0,0 +1,51 @@ +/* + * Minimal user-environment for testing BTI. + * + * Normal libc is not built with BTI support enabled, and so could + * generate a BTI TRAP before ever reaching main. + */ + +#include +#include +#include +#include + +int main(void); + +void _start(void) +{ + exit(main()); +} + +void exit(int ret) +{ + register int x0 __asm__("x0") = ret; + register int x8 __asm__("x8") = __NR_exit; + + asm volatile("svc #0" : : "r"(x0), "r"(x8)); + __builtin_unreachable(); +} + +/* + * Irritatingly, the user API struct sigaction does not match the + * kernel API struct sigaction. So for simplicity, isolate the + * kernel ABI here, and make this act like signal. + */ +void signal_info(int sig, void (*fn)(int, siginfo_t *, ucontext_t *)) +{ + struct kernel_sigaction { + void (*handler)(int, siginfo_t *, ucontext_t *); + unsigned long flags; + unsigned long restorer; + unsigned long mask; + } sa = { fn, SA_SIGINFO, 0, 0 }; + + register int x0 __asm__("x0") = sig; + register void *x1 __asm__("x1") = &sa; + register void *x2 __asm__("x2") = 0; + register int x3 __asm__("x3") = sizeof(unsigned long); + register int x8 __asm__("x8") = __NR_rt_sigaction; + + asm volatile("svc #0" + : : "r"(x0), "r"(x1), "r"(x2), "r"(x3), "r"(x8) : "memory"); +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 08c45b8470..3d56e7c6ea 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -8,10 +8,15 @@ VPATH += $(AARCH64_SRC) # we don't build any of the ARM tests AARCH64_TESTS=$(filter-out $(ARM_TESTS), $(TESTS)) AARCH64_TESTS+=fcvt -TESTS:=$(AARCH64_TESTS) fcvt: LDFLAGS+=-lm run-fcvt: fcvt $(call run-test,$<,$(QEMU) $<, "$< on $(TARGET_NAME)") $(call diff-out,$<,$(AARCH64_SRC)/fcvt.ref) + +AARCH64_TESTS += bti-1 +bti-1: LDFLAGS += -nostartfiles -nodefaultlibs -nostdlib +run-bti-1: QEMU += -cpu max,guarded_pages=on + +TESTS:=$(AARCH64_TESTS)