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([2602:ae:1547:e101:250:b6ff:fe24:58ae]) by smtp.gmail.com with ESMTPSA id 184-20020a6302c1000000b003fcf1279c84sm5562151pgc.33.2022.06.04.16.10.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jun 2022 16:10:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 1/3] target/riscv: Set env->bins in gen_exception_illegal Date: Sat, 4 Jun 2022 23:10:02 +0000 Message-Id: <20220604231004.49990-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220604231004.49990-1-richard.henderson@linaro.org> References: <20220604231004.49990-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" While we set env->bins when unwinding for ILLEGAL_INST, from e.g. csrrw, we weren't setting it for immediately illegal instructions. Add a testcase for mtval via both exception paths. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1060 Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/translate.c | 2 + tests/tcg/riscv64/Makefile.softmmu-target | 21 +++++++++ tests/tcg/riscv64/issue1060.S | 53 +++++++++++++++++++++++ tests/tcg/riscv64/semihost.ld | 21 +++++++++ 4 files changed, 97 insertions(+) create mode 100644 tests/tcg/riscv64/Makefile.softmmu-target create mode 100644 tests/tcg/riscv64/issue1060.S create mode 100644 tests/tcg/riscv64/semihost.ld diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 55a4713af2..9196aa71db 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -238,6 +238,8 @@ static void generate_exception_mtval(DisasContext *ctx, int excp) static void gen_exception_illegal(DisasContext *ctx) { + tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, + offsetof(CPURISCVState, bins)); generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); } diff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv64/Makefile.softmmu-target new file mode 100644 index 0000000000..d51ece7023 --- /dev/null +++ b/tests/tcg/riscv64/Makefile.softmmu-target @@ -0,0 +1,21 @@ +# +# Aarch64 system tests +# + +TEST_SRC = $(SRC_PATH)/tests/tcg/riscv64 +VPATH += $(TEST_SRC) + +LINK_SCRIPT = $(TEST_SRC)/semihost.ld +LDFLAGS = -T $(LINK_SCRIPT) +CFLAGS += -g -Og + +%.o: %.S + $(CC) $(CFLAGS) $< -c -o $@ +%: %.o $(LINK_SCRIPT) + $(LD) $(LDFLAGS) $< -o $@ + +QEMU_OPTS += -M virt -display none -semihosting -device loader,file= + +EXTRA_RUNS += run-issue1060 +run-issue1060: issue1060 + $(call run-test, $<, $(QEMU) $(QEMU_OPTS)$<) diff --git a/tests/tcg/riscv64/issue1060.S b/tests/tcg/riscv64/issue1060.S new file mode 100644 index 0000000000..17b7fe1be2 --- /dev/null +++ b/tests/tcg/riscv64/issue1060.S @@ -0,0 +1,53 @@ + .option norvc + + .text + .global _start +_start: + lla t0, trap + csrw mtvec, t0 + + # These are all illegal instructions + csrw time, x0 + .insn i CUSTOM_0, 0, x0, x0, 0x321 + csrw time, x0 + .insn i CUSTOM_0, 0, x0, x0, 0x123 + csrw cycle, x0 + + # Success! + li a0, 0 + j _exit + +trap: + # When an instruction traps, compare it to the insn in memory. + csrr t0, mepc + csrr t1, mtval + lwu t2, 0(t0) + bne t1, t2, fail + + # Skip the insn and continue. + addi t0, t0, 4 + csrw mepc, t0 + mret + +fail: + li a0, 1 + +# Exit code in a0 +_exit: + lla a1, semiargs + li t0, 0x20026 # ADP_Stopped_ApplicationExit + sd t0, 0(a1) + sd a0, 8(a1) + li a0, 0x20 # TARGET_SYS_EXIT_EXTENDED + + # Semihosting call sequence + .balign 16 + slli zero, zero, 0x1f + ebreak + srai zero, zero, 0x7 + j . + + .data + .balign 16 +semiargs: + .space 16 diff --git a/tests/tcg/riscv64/semihost.ld b/tests/tcg/riscv64/semihost.ld new file mode 100644 index 0000000000..a59cc56b28 --- /dev/null +++ b/tests/tcg/riscv64/semihost.ld @@ -0,0 +1,21 @@ +ENTRY(_start) + +SECTIONS +{ + /* virt machine, RAM starts at 2gb */ + . = 0x80000000; + .text : { + *(.text) + } + .rodata : { + *(.rodata) + } + /* align r/w section to next 2mb */ + . = ALIGN(1 << 21); + .data : { + *(.data) + } + .bss : { + *(.bss) + } +} From patchwork Sat Jun 4 23:10:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 578756 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp2784478max; Sat, 4 Jun 2022 16:13:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx++cdx9SgA7+P59sb4eMmgAf5LGnwzUAO1PK3LWed7yKJTvm/yexoW/N3gcz19A6pN1XZC X-Received: by 2002:a05:620a:bce:b0:6a6:7055:c99 with SMTP id s14-20020a05620a0bce00b006a670550c99mr11528199qki.378.1654384430051; Sat, 04 Jun 2022 16:13:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654384430; cv=none; d=google.com; s=arc-20160816; b=lIGcGuPpw0hHaLyGarzauP+Jyyg91J1hhxtyP1D0SgLituH0seeDMmMnK4XZCHT+XC h+gdL4YxiFNZGwWL/rB8UbbSgq62tj9wTpI38pv+XFcBPZ3YRrutHytRy4Odtd4zinpj zXv7uvuibzJkfbpgFvhRVNG+ZNUHHm72plyt5PqyAeHRWwRTR5vtllrgoOmTo2pMhmAQ kb/1Iqo7ElhFsoyCCWLN7QbRyXsLhLnI0R/YP4D/5RiWgtEdGhqbD6hi1XpPQrkGPuZt s5jk4nMRrIhrp5AH2iHOIMx5jl/7486S/1ZfmAgZ4a6OvGSZX17D2ExhwkMOdYAw/fZb tvHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=SwpxzSVSdURXSZL6tDOTL8VJqOtYjKYsT4i+YQrSyxQ=; b=iaLnK30omarbBUNri6g5Y4ngrMJNTKqkV3OiJTL19qz41CzU0Mzr5hVbGW4INd9RFm EEMYFKIyZKqBxIS3nG87m6r6TtQarfUE709ofZvs9pPiTz190abgqc7biKx1Mu0iiwha c7ou7A2ojfHoikteVCfxeUn+6Oqiy84EAvCMdnol8FoxJtio1ptigl1MRdmwQcZrN3ga jCuMRfmR7MCP3fqG8S4A7aL/H3GLHuA7VTDdIkR1L6+Z1/2pkvNTtNOiJqLG+N8UrWtZ AMweA2hfBfBwiP/PvWabNn4TfuH9PjCwm3qDW49OjA09SUylbzE1ubbVlE+GAU3eTc3Z xEQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OTVmxmB2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:250:b6ff:fe24:58ae]) by smtp.gmail.com with ESMTPSA id 184-20020a6302c1000000b003fcf1279c84sm5562151pgc.33.2022.06.04.16.10.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jun 2022 16:10:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 2/3] target/riscv: Remove generate_exception_mtval Date: Sat, 4 Jun 2022 23:10:03 +0000 Message-Id: <20220604231004.49990-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220604231004.49990-1-richard.henderson@linaro.org> References: <20220604231004.49990-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The function doesn't set mtval, it sets badaddr. Move the set of badaddr directly into gen_exception_inst_addr_mis and use generate_exception. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/translate.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 9196aa71db..6e4bbea1cd 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -228,14 +228,6 @@ static void generate_exception(DisasContext *ctx, int excp) ctx->base.is_jmp = DISAS_NORETURN; } -static void generate_exception_mtval(DisasContext *ctx, int excp) -{ - gen_set_pc_imm(ctx, ctx->base.pc_next); - tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); - gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); - ctx->base.is_jmp = DISAS_NORETURN; -} - static void gen_exception_illegal(DisasContext *ctx) { tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, @@ -245,7 +237,8 @@ static void gen_exception_illegal(DisasContext *ctx) static void gen_exception_inst_addr_mis(DisasContext *ctx) { - generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); + tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); + generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); } static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) From patchwork Sat Jun 4 23:10:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 578755 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp2783712max; Sat, 4 Jun 2022 16:12:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzqH/41RqM2/smP5VQ2qwMgt+0oYkaOQLxkIABIx8CYyKqXn2jw8Oe2TtFNNjAhOOYmeOBT X-Received: by 2002:a05:622a:610:b0:302:eca8:6376 with SMTP id z16-20020a05622a061000b00302eca86376mr13131403qta.18.1654384336747; Sat, 04 Jun 2022 16:12:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654384336; cv=none; d=google.com; s=arc-20160816; b=x9aAGtSlPUnx2cXJz9pq/A0NpregSCw27GkzFFDcC93eF3U/K+06qZstXdmXkxBD/5 7ab/6rVgZ0LQAnRiLZOJES+iprl+2PKGg8t4vzhZXSiOwyVpCIsWrVQXSDJiNuvenrih dWeDhgzSMp/Awvw+Vo7Q84KHGTn4vlQObioCXflm9P3wFy48If2MzGSoVPuTPlFNwBn7 BDGy3IKkH3lamLWfxtD1ICm1U8VFKrGaYi4phmYRNsTySm9b36PYYkjlEY9oZjU8fZTe gvj39VHfZmST9OzIjpbABQO+xT2anTeUmYUvHHzEYUIANg1zXqan+ZSJhuSYgDNRr/GX p7Kw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=JEMAlLL3NGuLqFLBWL9oqhqscgsFoPyEqTMfa3vc+S8=; b=WdspHh9ifQy94DPn4VTPM5Xdl39OnG1eVUU0nROhVmdM5MkpDILs+DjT9vyFg05Gdv FGKq5yt81s2zHCF9XLo/JIAFpNvKoggpegFd6WLt3DP501l/qf1LHHLSCu0geIbRP6yk L8uSoByJ7bx5V6QY0o3Yi/6hic6xf98Eq7LYbY6icDqCTgYAB0Jmynd+4VWgsegGWekK NVnkCHIdRk5Ub//GyMndstweyaCFOERXTXZfMWpWR1f3xZkGeSHgOsQr2/ncvQOm6VWF J1z+Iz6ETQOUOpqtmgi3OLl4vvQPH0CR9zhfWxMRkFidJt0VHhGIV4jCJQNNSaJ07MB4 6FFg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Frkdx98C; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:250:b6ff:fe24:58ae]) by smtp.gmail.com with ESMTPSA id 184-20020a6302c1000000b003fcf1279c84sm5562151pgc.33.2022.06.04.16.10.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jun 2022 16:10:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 3/3] target/riscv: Minimize the calls to decode_save_opc Date: Sat, 4 Jun 2022 23:10:04 +0000 Message-Id: <20220604231004.49990-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220604231004.49990-1-richard.henderson@linaro.org> References: <20220604231004.49990-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The set of instructions that require decode_save_opc for unwinding is really fairly small -- only insns that can raise ILLEGAL_INSN at runtime. This includes CSR, anything that uses a *new* fp rounding mode, and many privileged insns. Since unwind info is stored as the difference from the previous insn, storing a 0 for most insns minimizes the size of the unwind info. Booting a debian kernel image to the missing rootfs panic yields - gen code size 22226819/1026886656 + gen code size 21601907/1026886656 on 41k TranslationBlocks, a savings of 610kB or a bit less than 3%. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/translate.c | 18 +++++++++--------- target/riscv/insn_trans/trans_privileged.c.inc | 4 ++++ target/riscv/insn_trans/trans_rvh.c.inc | 2 ++ target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ 4 files changed, 17 insertions(+), 9 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6e4bbea1cd..b328a7b2ff 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -204,6 +204,13 @@ static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); } +static void decode_save_opc(DisasContext *ctx) +{ + assert(ctx->insn_start != NULL); + tcg_set_insn_start_param(ctx->insn_start, 1, ctx->opcode); + ctx->insn_start = NULL; +} + static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest) { if (get_xl(ctx) == MXL_RV32) { @@ -633,6 +640,8 @@ static void gen_set_rm(DisasContext *ctx, int rm) return; } + /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ + decode_save_opc(ctx); gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); } @@ -1011,13 +1020,6 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) /* Include decoders for factored-out extensions */ #include "decode-XVentanaCondOps.c.inc" -static inline void decode_save_opc(DisasContext *ctx, target_ulong opc) -{ - assert(ctx->insn_start != NULL); - tcg_set_insn_start_param(ctx->insn_start, 1, opc); - ctx->insn_start = NULL; -} - static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) { /* @@ -1034,7 +1036,6 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) /* Check for compressed insn */ if (extract16(opcode, 0, 2) != 3) { - decode_save_opc(ctx, opcode); if (!has_ext(ctx, RVC)) { gen_exception_illegal(ctx); } else { @@ -1049,7 +1050,6 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) opcode32 = deposit32(opcode32, 16, 16, translator_lduw(env, &ctx->base, ctx->base.pc_next + 2)); - decode_save_opc(ctx, opcode32); ctx->opcode = opcode32; ctx->pc_succ_insn = ctx->base.pc_next + 4; diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc index 53613682e8..46f96ad74d 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -75,6 +75,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) { #ifndef CONFIG_USER_ONLY if (has_ext(ctx, RVS)) { + decode_save_opc(ctx); gen_helper_sret(cpu_pc, cpu_env); tcg_gen_exit_tb(NULL, 0); /* no chaining */ ctx->base.is_jmp = DISAS_NORETURN; @@ -90,6 +91,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) static bool trans_mret(DisasContext *ctx, arg_mret *a) { #ifndef CONFIG_USER_ONLY + decode_save_opc(ctx); gen_helper_mret(cpu_pc, cpu_env); tcg_gen_exit_tb(NULL, 0); /* no chaining */ ctx->base.is_jmp = DISAS_NORETURN; @@ -102,6 +104,7 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a) static bool trans_wfi(DisasContext *ctx, arg_wfi *a) { #ifndef CONFIG_USER_ONLY + decode_save_opc(ctx); gen_set_pc_imm(ctx, ctx->pc_succ_insn); gen_helper_wfi(cpu_env); return true; @@ -113,6 +116,7 @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a) static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a) { #ifndef CONFIG_USER_ONLY + decode_save_opc(ctx); gen_helper_tlb_flush(cpu_env); return true; #endif diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc index cebcb3f8f6..4f8aecddc7 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -169,6 +169,7 @@ static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a) { REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY + decode_save_opc(ctx); gen_helper_hyp_gvma_tlb_flush(cpu_env); return true; #endif @@ -179,6 +180,7 @@ static bool trans_hfence_vvma(DisasContext *ctx, arg_sfence_vma *a) { REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY + decode_save_opc(ctx); gen_helper_hyp_tlb_flush(cpu_env); return true; #endif diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index f1342f30f8..cf17458022 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -822,6 +822,8 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a) static bool do_csr_post(DisasContext *ctx) { + /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ + decode_save_opc(ctx); /* We may have changed important cpu state -- exit to main loop. */ gen_set_pc_imm(ctx, ctx->pc_succ_insn); tcg_gen_exit_tb(NULL, 0);