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[209.51.188.17]) by mx.google.com with ESMTPS id js1-20020a0562142aa100b0046b9acb97easi2494648qvb.136.2022.06.06.19.49.14 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 06 Jun 2022 19:49:14 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="l/7OOMPf"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52466 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyPHN-0007Sr-DW for patch@linaro.org; Mon, 06 Jun 2022 22:49:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60964) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyPFt-0006UU-3d for qemu-devel@nongnu.org; Mon, 06 Jun 2022 22:47:41 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]:41613) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyPFq-0000Gj-3Z for qemu-devel@nongnu.org; Mon, 06 Jun 2022 22:47:40 -0400 Received: by mail-pg1-x52c.google.com with SMTP id e66so14528830pgc.8 for ; Mon, 06 Jun 2022 19:47:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=w/iHX6ANtN/zAKSj1imBD0tjZXjeiBLskpYlkOhgS0I=; b=l/7OOMPftewRQ7d5M9h66/VaR4dPsLiZn0T3Qs6jObKZiZgQzo1vMpuKLQ3YiN6bVB miMOTc7eKix0N4ZYFb7CmR0z2RJ2u2G4m1BzyjDPJ7Em+sOIA28o00VV4yTUvvOsoOQl 52mSktWwu/0VnlUHnRxSemyfRobgjkQCHr8V+BM7mm8I/zA1Kz8NJPfvAsefICOiLMKT 7lndCtyo7ViLUPteE0lHy4NhaMFwlZ8Dchlf8gAfl+mA9N7XsCBETZ4vOGHpPEtOwbhv Xv1ZGQR15UPtdY8BvAjOaXUPRHVvuDMi/vZo/VWgmKG3GpJMFlEaUye+AGc2BIvxL8do 6ryQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=w/iHX6ANtN/zAKSj1imBD0tjZXjeiBLskpYlkOhgS0I=; b=WtMuWCe6r8NaSHVhqhpdPBpZIfScVxNNrT3arYrZ7tZhDuhfc8TjqmmgKNwFN5QDMj 2pzs8JZYALIzH+nwjDqWnTvmh5YjrwEo/O+nBmSs1r1U3tMJsVz2u3k/Svjygao4Lhhf U1TGfv4HQnlsl/HABB+oVhl3YvNla2AvsFKKxNoIlipOOYQ2iE6mV57722GUigvAbTTe lG1bKQKZZAxMUH5JUCj25U9WldaG6M+cAJxFxsgzfVx3Lm1rGg9QLO1pW6yBb+nTZhh+ 0yiFC0sa25yTrKkedNOiRi7+5T3QcjKEP2BuOdC4oX3jF100j7q4HVxGRY4z4f1PiOnl +icw== X-Gm-Message-State: AOAM5313uvBX74D3tdAWS2XhnuGF3oFOXhFKPu+blxPf7Q8iWN4vX6Ka 3gfEPaZovOjMvfTT0ms5QfrABj4YTFCHSQ== X-Received: by 2002:a65:5385:0:b0:3fa:52e3:6468 with SMTP id x5-20020a655385000000b003fa52e36468mr23849622pgq.366.1654570056819; Mon, 06 Jun 2022 19:47:36 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:d3db:cca:e5c9:6531]) by smtp.gmail.com with ESMTPSA id y26-20020aa7805a000000b0051876d83714sm7476904pfm.196.2022.06.06.19.47.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 19:47:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 01/25] target/arm: Mark exception helpers as noreturn Date: Mon, 6 Jun 2022 19:47:10 -0700 Message-Id: <20220607024734.541321-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607024734.541321-1-richard.henderson@linaro.org> References: <20220607024734.541321-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index b1334e0c42..5161cdf73d 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -44,9 +44,9 @@ DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32) DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) -DEF_HELPER_2(exception_internal, void, env, i32) -DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32) -DEF_HELPER_2(exception_bkpt_insn, void, env, i32) +DEF_HELPER_2(exception_internal, noreturn, env, i32) +DEF_HELPER_4(exception_with_syndrome, noreturn, env, i32, i32, i32) +DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) DEF_HELPER_1(setend, void, env) DEF_HELPER_2(wfi, void, env, i32) From patchwork Tue Jun 7 02:47:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 579299 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp4667583max; Mon, 6 Jun 2022 19:56:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw2VGESyn23rcsazyBOchIAaYygDiZ49npKwwzksYZnIJg8YhromK0kOFD5J4pM5CpPUy7N X-Received: by 2002:ac8:5b51:0:b0:304:f6e3:8b36 with SMTP id n17-20020ac85b51000000b00304f6e38b36mr1738268qtw.522.1654570561070; Mon, 06 Jun 2022 19:56:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654570561; cv=none; d=google.com; s=arc-20160816; b=QSlUa6YDG0J2DOLADtMueKq9Mp3pwuY7Ppjw3aLL59hi9EqiIdZtqERT13cM77yeU8 jCRGszYZKA9rtV1efYaAypCTgEPzpEaapCnaULp5AWMc5j0IwxC/LLUZ/pqsafQvLzL0 UHBz5y4OyTWLcVX+8AUfRqTRYmzwuwTphctgqkMPk1hFa5kfySBOR5+t2hnJ1a0aV05x COloIeCvMbB/ixSx+2O72I1NRIww8OdXN/di0ULDJCvpTxWadmzD36ElcEsw1sb/7409 T2U7Uo6J0RkQth4pGw6Hdf9QWrNoj0DGIYz8X6Dn4wK3pW1PxtBhFtmL3JC2prL1N57Q XOxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=T8AfpmQwL0+E6fQxm6ojECpdw/9TThJiZv66f6M94Xg=; b=QYXLy5kfA4IShPK5WwkeaYV+KXnqFR/sd33yKCLyaRRgjXbdw9D6CStGR0zbgoLd8N afUMU1mRl8xK5hiMT0xUwExhXl0YpAycMWL9d/iRaGqwqv5vX023QlqFmkiPjE8j1/Eb Mu/NyE4Ixf7r9QRtGnOLaBMQllP+ipRMgBjnuzO+Yd62AM7wqrx25gWICDGjpJNJfulf 8LmfS4FrV6MaEylWl3hxE5fShketXQXg6hcTUSomn/bfX3FS4G8+SDCNpN0U0oBbCFFB 0BjSHAUl4j2HJIOAIFs3JxLGqD1LJD+UMyavLHvqmSrJOanAQmZ8aSf21NGRw54TTW7Q i30w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YTsaaHAY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:d3db:cca:e5c9:6531]) by smtp.gmail.com with ESMTPSA id y26-20020aa7805a000000b0051876d83714sm7476904pfm.196.2022.06.06.19.47.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 19:47:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 02/25] target/arm: Add coproc parameter to syn_fp_access_trap Date: Mon, 6 Jun 2022 19:47:11 -0700 Message-Id: <20220607024734.541321-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607024734.541321-1-richard.henderson@linaro.org> References: <20220607024734.541321-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" With ARMv8, this field is always RES0. With ARMv7, targeting EL2 and TA=0, it is always 0xA. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/syndrome.h | 7 ++++--- target/arm/translate-a64.c | 3 ++- target/arm/translate-vfp.c | 14 ++++++++++++-- 3 files changed, 18 insertions(+), 6 deletions(-) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 0cb26dde7d..c105f9e6ba 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -185,12 +185,13 @@ static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; } -static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) +static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit, + int coproc) { - /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 coproc == 0xa */ + /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 */ return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | 0xa; + | (cv << 24) | (cond << 20) | coproc; } static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 935e1929bb..14b90a37ea 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1162,7 +1162,8 @@ static bool fp_access_check(DisasContext *s) s->fp_access_checked = true; gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); + syn_fp_access_trap(1, 0xe, false, 0), + s->fp_excp_el); return false; } s->fp_access_checked = true; diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 40a513b822..0f797c56fd 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -219,8 +219,18 @@ static void gen_update_fp_context(DisasContext *s) static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled) { if (s->fp_excp_el) { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); + /* + * The full syndrome is only used for HSR when HCPTR traps: + * For v8, when TA==0, coproc is RES0. + * For v7, any use of a Floating-point instruction or access + * to a Floating-point Extension register that is trapped to + * Hyp mode because of a trap configured in the HCPTR sets + * this field to 0xA. + */ + int coproc = arm_dc_feature(s, ARM_FEATURE_V8) ? 0 : 0xa; + uint32_t syn = syn_fp_access_trap(1, 0xe, false, coproc); + + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn, s->fp_excp_el); return false; } From patchwork Tue Jun 7 02:47:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 579294 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp4665514max; Mon, 6 Jun 2022 19:52:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwOUsgk9VQe/xkPBJurQSAIJslPDRBjQNpCLt/7n33eTBmyosdq6zzmbIJNbsPktI87LYdd X-Received: by 2002:a37:b2c5:0:b0:6a5:d2eb:a132 with SMTP id b188-20020a37b2c5000000b006a5d2eba132mr17893278qkf.106.1654570331283; Mon, 06 Jun 2022 19:52:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654570331; cv=none; d=google.com; s=arc-20160816; b=OVjWKFCrbyrt/JvlX81SJzXU1mk2+sBAJUGpCq++ieVKSJBscWM727M2/cNzbkKjvw seZWqkBh8UDsKolwHUWJrdzgprpy6wYWHQwGrBZDQdaJ50TCqC0+H50v0qR8gPcJzdPz b/sI1Mv738nY/gZjm50A/hAbOtxsn4OIU/mZCD4fTE4gYDd3SWEmLd49nc5N0hMC1t6L BOkvP0K/zhdMoK7gsZZcGvBykhrbTEg8MaRgDz8G9V4EomlqUo3UrF8qaU9DDfMP+1mU q/QAEpADEPYz+94E9DSxIWvQQgRuvzyfJ41uC2DTDOlmLMnjFWjDo7M1F3A83oF4Cs1S hs8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=vyyg44YF2Y/mmVGaXvfp7YJNYhSRY+k5gyUVMMceFu0=; b=zZx6ffARp/pCR6tSM9W6bvBygoYyfOQc9jrUTpELom1oTUK854mhlaQIOLnPUD1snM a3cePrDkTTA5QVxJmaKJrpdr5Com5N3EujkKBP5iMKnZ6bU9pZT4cG0DnFiFDKPkp+6g aD6qbDAUT2EH1Lt089GeCbhXWfjqXEc1xaxqpPWBxx/DV5a5y8GUFSe6vqh+sulfMSiZ Ny5wqGArmU7mL3BcZLq9qwmxggfVBsqVvFPDbOM3HOy6bfVRrPaOAkiqkSLjeqMar7Wl 0GUXs5a3MHwemsXZZWh/nhuZ1IUHIYgNLUYThrRQ955bCNTdKhWmjhkoXvd2mTdtk+pi t8DA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="YtLN5NL/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:d3db:cca:e5c9:6531]) by smtp.gmail.com with ESMTPSA id y26-20020aa7805a000000b0051876d83714sm7476904pfm.196.2022.06.06.19.47.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 19:47:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 03/25] target/arm: Move fp access syndrome adjust out of raise_exception Date: Mon, 6 Jun 2022 19:47:12 -0700 Message-Id: <20220607024734.541321-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607024734.541321-1-richard.henderson@linaro.org> References: <20220607024734.541321-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create helper_exception_advsimdfp_access to handle both the routing and the syndrome contents, depending on the eventual target EL and mode. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.h | 1 + target/arm/translate.h | 9 +++++++++ target/arm/op_helper.c | 32 +++++++++++++++++++++++--------- target/arm/translate-a64.c | 5 ++--- target/arm/translate-vfp.c | 4 +++- 5 files changed, 38 insertions(+), 13 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 5161cdf73d..a13007699d 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -46,6 +46,7 @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(exception_internal, noreturn, env, i32) DEF_HELPER_4(exception_with_syndrome, noreturn, env, i32, i32, i32) +DEF_HELPER_3(exception_advsimdfp_access, noreturn, env, i32, i32) DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) DEF_HELPER_1(setend, void, env) diff --git a/target/arm/translate.h b/target/arm/translate.h index 9f0bb270c5..da5f89d49d 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -337,6 +337,15 @@ static inline void gen_exception(int excp, uint32_t syndrome, tcg_constant_i32(target_el)); } +static inline void gen_exception_advsimdfp_access(DisasContext *s, + uint32_t syndrome) +{ + gen_helper_exception_advsimdfp_access(cpu_env, + tcg_constant_i32(syndrome), + tcg_constant_i32(s->fp_excp_el)); + s->base.is_jmp = DISAS_NORETURN; +} + /* Generate an architectural singlestep exception */ static inline void gen_swstep_exception(DisasContext *s, int isv, int ex) { diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index c4bd668870..67b7dbeaa9 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -34,16 +34,8 @@ void raise_exception(CPUARMState *env, uint32_t excp, CPUState *cs = env_cpu(env); if (target_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { - /* - * Redirect NS EL1 exceptions to NS EL2. These are reported with - * their original syndrome register value, with the exception of - * SIMD/FP access traps, which are reported as uncategorized - * (see DDI0478C.a D1.10.4) - */ + /* Redirect NS EL1 exceptions to NS EL2. */ target_el = 2; - if (syn_get_ec(syndrome) == EC_ADVSIMDFPACCESSTRAP) { - syndrome = syn_uncategorized(); - } } assert(!excp_is_internal(excp)); @@ -384,6 +376,28 @@ void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp, raise_exception(env, excp, syndrome, target_el); } +/* Raise an exception with EC_ADVSIMDFPACCESS. */ +void HELPER(exception_advsimdfp_access)(CPUARMState *env, + uint32_t syndrome, uint32_t target_el) +{ + if (target_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { + /* + * SIMD/FP access traps, when re-routed to EL2, are reported with + * uncategorized syndrome. See DDI0487H.a rule RJNBTN. + */ + target_el = 2; + syndrome = syn_uncategorized(); + } else if (arm_el_is_aa64(env, target_el)) { + /* + * From AArch32, we will have filled in TA and/or COPROC for use + * by aa32 HSR. But in aa64 ESR_ELx, the low 20 bits are RES0. + */ + syndrome &= 0xfff00000; + } + + raise_exception(env, EXCP_UDEF, syndrome, target_el); +} + /* Raise an EXCP_BKPT with the specified syndrome register value, * targeting the correct exception level for debug exceptions. */ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 14b90a37ea..3251c69180 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1161,9 +1161,8 @@ static bool fp_access_check(DisasContext *s) assert(!s->fp_access_checked); s->fp_access_checked = true; - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_fp_access_trap(1, 0xe, false, 0), - s->fp_excp_el); + gen_a64_set_pc_im(s->pc_curr); + gen_exception_advsimdfp_access(s, syn_fp_access_trap(1, 0xe, false, 0)); return false; } s->fp_access_checked = true; diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 0f797c56fd..2a98387411 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -230,7 +230,9 @@ static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled) int coproc = arm_dc_feature(s, ARM_FEATURE_V8) ? 0 : 0xa; uint32_t syn = syn_fp_access_trap(1, 0xe, false, coproc); - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn, s->fp_excp_el); + gen_set_condexec(s); + gen_set_pc_im(s, s->pc_curr); + gen_exception_advsimdfp_access(s, syn); return false; } From patchwork Tue Jun 7 02:47:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 579291 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp4664025max; Mon, 6 Jun 2022 19:49:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy7pQ2kAhyeOyLSz6f7UkAwzpyCymGSB74tXitjZ6HoZqIJ9rrrSHuXwLMep8XFUaEDStH7 X-Received: by 2002:a05:620a:2845:b0:6a3:646f:9ba8 with SMTP id h5-20020a05620a284500b006a3646f9ba8mr18290227qkp.56.1654570141873; Mon, 06 Jun 2022 19:49:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654570141; cv=none; d=google.com; s=arc-20160816; b=gyND+tSQKm1tRRHccJ12a6zrBy1MENBsjmAMh44cAgoh7uSHn89uycWR+CxWaK9CqD aUfH6PLwE7gKLQjT2jqwkPQXua7yGiZXqQTNmRIhEKxfOZxTljWhaQQGDFhIKVlO6yqu eRFDHE7SMtnui8Urh4dqogLF3HOt1UPq9v6Rg5IgI0ea5ZFlYZagN8JX54OFuU5Fy4dX BzrUTWkyT1cQy3oFrNio6BTCcTxqrRcy+JJqwpAI28jLe8BiCgZOg0pKSYzoJSYC2OXB O020PBuVry0bRapbRVKCCRmf/s4P3YVFpwJNi+vIxblDEResWMWAN+Krpo6oV7M//fpU jqWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=6L8pt/IhJxuBRjI6bUDUlD7xMciX/G+qjq8VDpWp4w4=; b=djYVKovEWn2BmcQsLHLnxWYUBBA3wLWy8xx3AOO17P6Q5n1lRO85YJq/tCgqWI68yj x6I9PqynOhP4zj2cbMfoCtUXW5VBTsUI1aa2GnYvd5+Ch7eVQLmz8RGqAeztgQEX5bSN 16hYbTyy9Vr3Q0wafotyqsbhlb19Lsayy79IDhWlTkPMsTVZBe8w6qOvsp6eKag+V76Y JtCLS5/8A5L2d7guTwu4r8UpPEAxM6W8eXP2YhXxmxxLyHAK/NmJAM9yVCkNmTkT163t +F4FOf2dbmaIJ2P3U1/u6WR7botwLHaZKLvq60R9UZg4u4jq7RmKBMtK9YHgNaZkQKG5 hC7Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qRkGDEkN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:d3db:cca:e5c9:6531]) by smtp.gmail.com with ESMTPSA id y26-20020aa7805a000000b0051876d83714sm7476904pfm.196.2022.06.06.19.47.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 19:47:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 04/25] target/arm: Move exception_target_el out of line Date: Mon, 6 Jun 2022 19:47:13 -0700 Message-Id: <20220607024734.541321-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607024734.541321-1-richard.henderson@linaro.org> References: <20220607024734.541321-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the function to op_helper.c, near raise_exception. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 16 +--------------- target/arm/op_helper.c | 15 +++++++++++++++ 2 files changed, 16 insertions(+), 15 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index b654bee468..36c33a6ac5 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1090,21 +1090,6 @@ typedef struct ARMVAParameters { ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data); -static inline int exception_target_el(CPUARMState *env) -{ - int target_el = MAX(1, arm_current_el(env)); - - /* - * No such thing as secure EL1 if EL3 is aarch32, - * so update the target EL to EL3 in this case. - */ - if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) { - target_el = 3; - } - - return target_el; -} - /* Determine if allocation tags are available. */ static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, uint64_t sctlr) @@ -1329,5 +1314,6 @@ void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); #endif void aa32_max_features(ARMCPU *cpu); +int exception_target_el(CPUARMState *env); #endif diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 67b7dbeaa9..00a082d1f7 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -28,6 +28,21 @@ #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) +int exception_target_el(CPUARMState *env) +{ + int target_el = MAX(1, arm_current_el(env)); + + /* + * No such thing as secure EL1 if EL3 is aarch32, + * so update the target EL to EL3 in this case. + */ + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) { + target_el = 3; + } + + return target_el; +} + void raise_exception(CPUARMState *env, uint32_t excp, uint32_t syndrome, uint32_t target_el) { From patchwork Tue Jun 7 02:47:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 579301 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp4667922max; Mon, 6 Jun 2022 19:56:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz+4oVev6jIewbcJ+DJfaG78umRHpBIkq+8GowRtecAt3KA9y/H4y2atafgOakJEbzbt66P X-Received: by 2002:a05:6214:2589:b0:464:69ea:771c with SMTP id fq9-20020a056214258900b0046469ea771cmr24118953qvb.41.1654570601808; Mon, 06 Jun 2022 19:56:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654570601; cv=none; d=google.com; s=arc-20160816; b=f2fmIKxAQSCj4egCGKk64GwcNCBHl+zyab0IUdNHJDYHRLL/BAC00Jw8lQ0aiMxuBi O3YXkPLruMpxS3vwtCZNCFa3dZ51M5hybg3xEIMiEfbJbuvUEf3sGo9UA7KLZ9sUf1zQ Fk1MZ9Vzm06ynyFbkiV4gcGGknZxJRZgQ5kmNrNSgXZ7d1BYKQyF4mUSwf9cX5CyX7ho 5bfEkBVDXGsOOf+/eBCmocYNBdPhLKRyCRt1jSJ7eAdwmBuMHTtjbhBJ/6DV+76veX1g ZrDX/DTobMcdgwFqKcMpaC39VqvX0krudZOo6d5LqTa9s6GEDOtQKOfzzxINoGKtURNS rVhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=SyvEw0v6kbVYTBLHikS3UDLCGmQvw9Yz1NNALVd/Wyo=; b=068MQW8irRMiaRl/3Zp1mtQhnNjylnZUTMvfs1kjEurmivbt1ko46LOUNP/2LGERhw P+y69Rn/t4pO6Rxb8Ix6p4IrGroGAXv+jlLYDL+G5KHGyufnMzSwDNBL52HheDrkiyV9 8Q/pcuQGJJjY0KAeTifzIgQ0w2hdXy+8Ef6734oz7hwacw4v421z4E18DeJNIRnldJk6 MTzdcpRIeMetOvlfg7khRx5YH6gG2ECtrE43PLY1QpnOm+4UPQrRaVid9EzRo8qcJlMw Nemj3fpoJTI3Sdwew4GCj3ZQ8/vyCwpV5jMFKZDLomKGWhwkyXQQZLtWP3TudGitMiUE mhVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MBUKvjyr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:d3db:cca:e5c9:6531]) by smtp.gmail.com with ESMTPSA id y26-20020aa7805a000000b0051876d83714sm7476904pfm.196.2022.06.06.19.47.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 19:47:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 05/25] target/arm: Move arm_singlestep_active out of line Date: Mon, 6 Jun 2022 19:47:14 -0700 Message-Id: <20220607024734.541321-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607024734.541321-1-richard.henderson@linaro.org> References: <20220607024734.541321-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the function to debug_helper.c, and the declaration to internals.h. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 10 ---------- target/arm/internals.h | 1 + target/arm/debug_helper.c | 12 ++++++++++++ 3 files changed, 13 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c1865ad5da..2e115a0281 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3087,16 +3087,6 @@ static inline bool arm_generate_debug_exceptions(CPUARMState *env) } } -/* Is single-stepping active? (Note that the "is EL_D AArch64?" check - * implicitly means this always returns false in pre-v8 CPUs.) - */ -static inline bool arm_singlestep_active(CPUARMState *env) -{ - return extract32(env->cp15.mdscr_el1, 0, 1) - && arm_el_is_aa64(env, arm_debug_target_el(env)) - && arm_generate_debug_exceptions(env); -} - static inline bool arm_sctlr_b(CPUARMState *env) { return diff --git a/target/arm/internals.h b/target/arm/internals.h index 36c33a6ac5..148f2a9252 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1315,5 +1315,6 @@ void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); void aa32_max_features(ARMCPU *cpu); int exception_target_el(CPUARMState *env); +bool arm_singlestep_active(CPUARMState *env); #endif diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 46893697cc..1abf41c5f8 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -11,6 +11,18 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" + +/* + * Is single-stepping active? (Note that the "is EL_D AArch64?" check + * implicitly means this always returns false in pre-v8 CPUs.) + */ +bool arm_singlestep_active(CPUARMState *env) +{ + return extract32(env->cp15.mdscr_el1, 0, 1) + && arm_el_is_aa64(env, arm_debug_target_el(env)) + && arm_generate_debug_exceptions(env); +} + /* Return true if the linked breakpoint entry lbn passes its checks */ static bool linked_bp_matches(ARMCPU *cpu, int lbn) { From patchwork Tue Jun 7 02:47:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 579296 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp4665708max; Mon, 6 Jun 2022 19:52:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxE3tQFYVQmH1fdQsYe8rnpQitNMh1JwHk4QOxuvNdbAWpnkjucjgUb1KBFefYa0uX9Y6lA X-Received: by 2002:a05:6214:202f:b0:432:4810:1b34 with SMTP id 15-20020a056214202f00b0043248101b34mr19529354qvf.35.1654570353757; Mon, 06 Jun 2022 19:52:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654570353; cv=none; d=google.com; s=arc-20160816; b=poxwta2e04Gd95ZC5nI0BuUYETbza7No4VIWOUHBK4jp3Zfg867abWycy2tw0r5v/E 2gFGgEnH0pPxUO2cepHR2jZYL60GnRdnaQWUgng2Owd5pPZEJMyUK46jOx45swEoyOqY oNqb/qVndWlNyEsVzNeAN5SO234FSOvheHqR5a2HwhAIxPNgOuMmZb7KSDgOFdSmiDrj tGRI1hDpi8XDaspfjxn+nvaD0sHKvtvdIfRjd5Zq6ZOz/xUdfNJIcmdKNgJVJZzXkp3Z pF7uRYQ1cOaBSH0+sKf8ed/RJehHytzPScAityIPqHRRRdRYf1OfzSSrpvDrOmx61ssY zetQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=agb1KQVoHZp1Dq8M4FnweXRLwX+H5ZfT4A8G1UBDOMI=; b=g//gIR/7Qqn6BylYU90FkbTIf8UGlPOumpKESxpzehcCwcetmL3a1CFzE9nurOdqtI xuauSb8ZO/K3Go7omFMxFaaWcuOcko6oTZyZxumkmEfXgikPca2zuO3YwuidXC2tZXdy CKXxq4oxz8GfxipTx2PWyaBZ3oJi/7YsJfFC+7IqjKuYVIrx35vdcF/OGHqKKhtDFKUy cJgGIQEQHVM+wZmICEp+kycG+h0i1e90mA+GlIirdJA6CScW7ULw4f2r3SB0MpneQMF5 bzXbiOpuYPLuJBCFUPjgnmRQMz19aQNDrWne1CNusLJKXPbJ3mdOHXO9pX3hDA6aY7x2 x20w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jYeLSqS+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:d3db:cca:e5c9:6531]) by smtp.gmail.com with ESMTPSA id y26-20020aa7805a000000b0051876d83714sm7476904pfm.196.2022.06.06.19.47.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 19:47:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 06/25] target/arm: Move arm_generate_debug_exceptions out of line Date: Mon, 6 Jun 2022 19:47:15 -0700 Message-Id: <20220607024734.541321-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607024734.541321-1-richard.henderson@linaro.org> References: <20220607024734.541321-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move arm_generate_debug_exceptions and its two subroutines, {aa32,aa64}_generate_debug_exceptions into debug_helper.c, and the one interface declaration to internals.h. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 91 ------------------------------------- target/arm/internals.h | 1 + target/arm/debug_helper.c | 94 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 95 insertions(+), 91 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2e115a0281..92c9758e86 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2996,97 +2996,6 @@ static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; } -/* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ -static inline bool aa64_generate_debug_exceptions(CPUARMState *env) -{ - int cur_el = arm_current_el(env); - int debug_el; - - if (cur_el == 3) { - return false; - } - - /* MDCR_EL3.SDD disables debug events from Secure state */ - if (arm_is_secure_below_el3(env) - && extract32(env->cp15.mdcr_el3, 16, 1)) { - return false; - } - - /* - * Same EL to same EL debug exceptions need MDSCR_KDE enabled - * while not masking the (D)ebug bit in DAIF. - */ - debug_el = arm_debug_target_el(env); - - if (cur_el == debug_el) { - return extract32(env->cp15.mdscr_el1, 13, 1) - && !(env->daif & PSTATE_D); - } - - /* Otherwise the debug target needs to be a higher EL */ - return debug_el > cur_el; -} - -static inline bool aa32_generate_debug_exceptions(CPUARMState *env) -{ - int el = arm_current_el(env); - - if (el == 0 && arm_el_is_aa64(env, 1)) { - return aa64_generate_debug_exceptions(env); - } - - if (arm_is_secure(env)) { - int spd; - - if (el == 0 && (env->cp15.sder & 1)) { - /* SDER.SUIDEN means debug exceptions from Secure EL0 - * are always enabled. Otherwise they are controlled by - * SDCR.SPD like those from other Secure ELs. - */ - return true; - } - - spd = extract32(env->cp15.mdcr_el3, 14, 2); - switch (spd) { - case 1: - /* SPD == 0b01 is reserved, but behaves as 0b00. */ - case 0: - /* For 0b00 we return true if external secure invasive debug - * is enabled. On real hardware this is controlled by external - * signals to the core. QEMU always permits debug, and behaves - * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. - */ - return true; - case 2: - return false; - case 3: - return true; - } - } - - return el != 2; -} - -/* Return true if debugging exceptions are currently enabled. - * This corresponds to what in ARM ARM pseudocode would be - * if UsingAArch32() then - * return AArch32.GenerateDebugExceptions() - * else - * return AArch64.GenerateDebugExceptions() - * We choose to push the if() down into this function for clarity, - * since the pseudocode has it at all callsites except for the one in - * CheckSoftwareStep(), where it is elided because both branches would - * always return the same value. - */ -static inline bool arm_generate_debug_exceptions(CPUARMState *env) -{ - if (env->aarch64) { - return aa64_generate_debug_exceptions(env); - } else { - return aa32_generate_debug_exceptions(env); - } -} - static inline bool arm_sctlr_b(CPUARMState *env) { return diff --git a/target/arm/internals.h b/target/arm/internals.h index 148f2a9252..e9ac54f244 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1316,5 +1316,6 @@ void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); void aa32_max_features(ARMCPU *cpu); int exception_target_el(CPUARMState *env); bool arm_singlestep_active(CPUARMState *env); +bool arm_generate_debug_exceptions(CPUARMState *env); #endif diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 1abf41c5f8..20a0e4261a 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -12,6 +12,100 @@ #include "exec/helper-proto.h" +/* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ +static bool aa64_generate_debug_exceptions(CPUARMState *env) +{ + int cur_el = arm_current_el(env); + int debug_el; + + if (cur_el == 3) { + return false; + } + + /* MDCR_EL3.SDD disables debug events from Secure state */ + if (arm_is_secure_below_el3(env) + && extract32(env->cp15.mdcr_el3, 16, 1)) { + return false; + } + + /* + * Same EL to same EL debug exceptions need MDSCR_KDE enabled + * while not masking the (D)ebug bit in DAIF. + */ + debug_el = arm_debug_target_el(env); + + if (cur_el == debug_el) { + return extract32(env->cp15.mdscr_el1, 13, 1) + && !(env->daif & PSTATE_D); + } + + /* Otherwise the debug target needs to be a higher EL */ + return debug_el > cur_el; +} + +static bool aa32_generate_debug_exceptions(CPUARMState *env) +{ + int el = arm_current_el(env); + + if (el == 0 && arm_el_is_aa64(env, 1)) { + return aa64_generate_debug_exceptions(env); + } + + if (arm_is_secure(env)) { + int spd; + + if (el == 0 && (env->cp15.sder & 1)) { + /* + * SDER.SUIDEN means debug exceptions from Secure EL0 + * are always enabled. Otherwise they are controlled by + * SDCR.SPD like those from other Secure ELs. + */ + return true; + } + + spd = extract32(env->cp15.mdcr_el3, 14, 2); + switch (spd) { + case 1: + /* SPD == 0b01 is reserved, but behaves as 0b00. */ + case 0: + /* + * For 0b00 we return true if external secure invasive debug + * is enabled. On real hardware this is controlled by external + * signals to the core. QEMU always permits debug, and behaves + * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. + */ + return true; + case 2: + return false; + case 3: + return true; + } + } + + return el != 2; +} + +/* + * Return true if debugging exceptions are currently enabled. + * This corresponds to what in ARM ARM pseudocode would be + * if UsingAArch32() then + * return AArch32.GenerateDebugExceptions() + * else + * return AArch64.GenerateDebugExceptions() + * We choose to push the if() down into this function for clarity, + * since the pseudocode has it at all callsites except for the one in + * CheckSoftwareStep(), where it is elided because both branches would + * always return the same value. + */ +bool arm_generate_debug_exceptions(CPUARMState *env) +{ + if (env->aarch64) { + return aa64_generate_debug_exceptions(env); + } else { + return aa32_generate_debug_exceptions(env); + } +} + /* * Is single-stepping active? (Note that the "is EL_D AArch64?" check * implicitly means this always returns false in pre-v8 CPUs.) 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([2602:ae:1547:e101:d3db:cca:e5c9:6531]) by smtp.gmail.com with ESMTPSA id y26-20020aa7805a000000b0051876d83714sm7476904pfm.196.2022.06.06.19.47.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 19:47:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 07/25] target/arm: Use is_a64 in arm_generate_debug_exceptions Date: Mon, 6 Jun 2022 19:47:16 -0700 Message-Id: <20220607024734.541321-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607024734.541321-1-richard.henderson@linaro.org> References: <20220607024734.541321-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use the accessor rather than the raw structure member. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/debug_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 20a0e4261a..a18a09a0c3 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -99,7 +99,7 @@ static bool aa32_generate_debug_exceptions(CPUARMState *env) */ bool arm_generate_debug_exceptions(CPUARMState *env) { - if (env->aarch64) { + if (is_a64(env)) { return aa64_generate_debug_exceptions(env); } else { return aa32_generate_debug_exceptions(env); From patchwork Tue Jun 7 02:47:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 579295 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp4665711max; Mon, 6 Jun 2022 19:52:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyObiyO3J9kZ/O2Dd6U4Sjz741rq5+YcOSY0wjv9Yo+FPrUjpBKLflT8wsg2Dyo6NnEmJT7 X-Received: by 2002:a05:620a:895:b0:6a6:a15d:3018 with SMTP id b21-20020a05620a089500b006a6a15d3018mr12854672qka.451.1654570353852; Mon, 06 Jun 2022 19:52:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654570353; cv=none; d=google.com; s=arc-20160816; b=lF1/j6laVdlkSbrOl/Bagyl4WFopHP42R/Ld6Ap+xsFX9WtwDr0jaUFpjZV6QLMhfw YX1K0bdcvEpeS3pSrSj0cZdjrbC6N7hzGAnr3fsOLD+BiyWrj7l3R7i2Xw8eQWbeXeGM dXDuymbIMKE8ZW9IsS/ehflcMNIA6AwLdYLjd1EPp/K8LklDm75k48BJ4/iM4Ou+S1JR G6P+y0Xgtq+in4uY7I4kG+H4rvFPYYCmffhKYotWy0Ak/qKj90eKZrvRzfmP/y7eFOsQ 9Mof9mywxp4RtvDwrpnudrs84WKYoaHHGdwZLMM6VhR2jtx9bWfS7Km1zpmihC+I+mOy ZGeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=t3QqzZZIr7UgbN3ZekMQ8h5fse6DD+fMoam6hjgppWE=; b=WHeMjiVwWqtbSI371y9YM1IkCu63uuO3gqkcSxi4l7ywPi7yDmZOO3SsO3gYmKE5JI NClPQjkkMui6QMlgyu98EgxFIN/wrC7jHDNDPngiBcyC9LnBn5A4nh5BvQir8aZGiUyy 2gTDx06zQUICLouO8rpP5OyBLTQ/LAmDHjG+Bf0Znjm+fteP4o41+gd2UlQ6WSgsFTBg Op41pjxfxvGxvmttz+8qHl4SwNLS16tW/HCHnYQ3VayPZkRxCmA5crTllwOepJoFjT3K tXohpo3e8BRBmHYJW56WXPQQzogamlQU3VzE8pV+zm2EEbMKAclvU1nDJkrYxPaFhlQq VIvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CTmXMfS6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:d3db:cca:e5c9:6531]) by smtp.gmail.com with ESMTPSA id y26-20020aa7805a000000b0051876d83714sm7476904pfm.196.2022.06.06.19.47.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 19:47:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 08/25] target/arm: Move exception_bkpt_insn to debug_helper.c Date: Mon, 6 Jun 2022 19:47:17 -0700 Message-Id: <20220607024734.541321-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607024734.541321-1-richard.henderson@linaro.org> References: <20220607024734.541321-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/debug_helper.c | 31 +++++++++++++++++++++++++++++++ target/arm/op_helper.c | 29 ----------------------------- 2 files changed, 31 insertions(+), 29 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index a18a09a0c3..80dff0788b 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -430,6 +430,37 @@ void arm_debug_excp_handler(CPUState *cs) } } +/* + * Raise an EXCP_BKPT with the specified syndrome register value, + * targeting the correct exception level for debug exceptions. + */ +void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) +{ + int debug_el = arm_debug_target_el(env); + int cur_el = arm_current_el(env); + + /* FSR will only be used if the debug target EL is AArch32. */ + env->exception.fsr = arm_debug_exception_fsr(env); + /* + * FAR is UNKNOWN: clear vaddress to avoid potentially exposing + * values to the guest that it shouldn't be able to see at its + * exception/security level. + */ + env->exception.vaddress = 0; + /* + * Other kinds of architectural debug exception are ignored if + * they target an exception level below the current one (in QEMU + * this is checked by arm_generate_debug_exceptions()). Breakpoint + * instructions are special because they always generate an exception + * to somewhere: if they can't go to the configured debug exception + * level they are taken to the current exception level. + */ + if (debug_el < cur_el) { + debug_el = cur_el; + } + raise_exception(env, EXCP_BKPT, syndrome, debug_el); +} + #if !defined(CONFIG_USER_ONLY) vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 00a082d1f7..ae0009d1a3 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -413,35 +413,6 @@ void HELPER(exception_advsimdfp_access)(CPUARMState *env, raise_exception(env, EXCP_UDEF, syndrome, target_el); } -/* Raise an EXCP_BKPT with the specified syndrome register value, - * targeting the correct exception level for debug exceptions. - */ -void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) -{ - int debug_el = arm_debug_target_el(env); - int cur_el = arm_current_el(env); - - /* FSR will only be used if the debug target EL is AArch32. */ - env->exception.fsr = arm_debug_exception_fsr(env); - /* FAR is UNKNOWN: clear vaddress to avoid potentially exposing - * values to the guest that it shouldn't be able to see at its - * exception/security level. - */ - env->exception.vaddress = 0; - /* - * Other kinds of architectural debug exception are ignored if - * they target an exception level below the current one (in QEMU - * this is checked by arm_generate_debug_exceptions()). Breakpoint - * instructions are special because they always generate an exception - * to somewhere: if they can't go to the configured debug exception - * level they are taken to the current exception level. - */ - if (debug_el < cur_el) { - debug_el = cur_el; - } - raise_exception(env, EXCP_BKPT, syndrome, debug_el); -} - uint32_t HELPER(cpsr_read)(CPUARMState *env) { return cpsr_read(env) & ~CPSR_EXEC; From patchwork Tue Jun 7 02:47:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 579298 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp4667550max; Mon, 6 Jun 2022 19:55:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyUrG1X3tkNyExWKFcPss8Xkxvt0HXpJ7/UC7IslGfGcupVqcE5aY5bAwx6I2c+a9xJ9tTa X-Received: by 2002:a05:620a:2a16:b0:6a5:8dec:580a with SMTP id o22-20020a05620a2a1600b006a58dec580amr16954473qkp.513.1654570556611; Mon, 06 Jun 2022 19:55:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654570556; cv=none; d=google.com; s=arc-20160816; b=dQzOnaQFyGZD/0PYtR7/Vb080PUgsE2UNKZzKq+LXIBtI1ySb9VPlpL/DZd6cPgAgt hiOvNwBu6KwBmOGIRC4iPU1PaEShwloKLjrTucvF6ZbDIXF6UGtxnYs2RsGisYdn4hDw xAX4Xi3I+g2NfxT4pK7IowVlGkZkYMWvvIbgUuXtaGRZLmYv146fKfY4eE4CQf8qOiws ag36pPgHqkZdDxl1WRQ9HQWYsjBufmZOUUkrmXaT5gb+olm8b9E9q/6/mCUcqJLtLUs5 wdtbXa6TGiuNokuMuyyKCrdnDhTPuoLn+MtOCoicCbRYpcbio/UTFOn3gUsZ/jiviCEB 1/9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=bgbyv0kyxTzSSLAbU+4HIoEqn6rfGQtEpi8WGE77FZs=; b=rGgrXONh67k5WvNEMfN3zQqciIxz1uGYCU6898bCndbEFl9p4CLnXTwvpCBRj6OTwH Wxad9JOAjNoY8+iuVpj03jLHAUuuEz0q0ByvxNyCrRJLZLZ6Ra3Z3qacTjOBrUd+KGxG C1CIihvMJJOyBEYfLOn7siNrTAEHeBk9lDefmofxtQJvKF+CqWv1824UGCRit6lbzvyq CgwZTiZs1vqTGzJt2LNvC8d14T5UYeplpFY7YQAVFzGVPIKQYNohosubcBkCQnavNheo OPucKa4mXVRcycWDh2xTryYx71olGOemtZvC5j5W7NhX0BZHVRUEy85ktkb01GpJXczz mLRQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=heDhTZTP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:d3db:cca:e5c9:6531]) by smtp.gmail.com with ESMTPSA id y26-20020aa7805a000000b0051876d83714sm7476904pfm.196.2022.06.06.19.47.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 19:47:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 09/25] target/arm: Move arm_debug_exception_fsr to debug_helper.c Date: Mon, 6 Jun 2022 19:47:18 -0700 Message-Id: <20220607024734.541321-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607024734.541321-1-richard.henderson@linaro.org> References: <20220607024734.541321-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This function now now only used in debug_helper.c, so there is no reason to have a declaration in a header. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 25 ------------------------- target/arm/debug_helper.c | 26 ++++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 25 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index e9ac54f244..c8410ee801 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -793,31 +793,6 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; } -/* Return the FSR value for a debug exception (watchpoint, hardware - * breakpoint or BKPT insn) targeting the specified exception level. - */ -static inline uint32_t arm_debug_exception_fsr(CPUARMState *env) -{ - ARMMMUFaultInfo fi = { .type = ARMFault_Debug }; - int target_el = arm_debug_target_el(env); - bool using_lpae = false; - - if (target_el == 2 || arm_el_is_aa64(env, target_el)) { - using_lpae = true; - } else { - if (arm_feature(env, ARM_FEATURE_LPAE) && - (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { - using_lpae = true; - } - } - - if (using_lpae) { - return arm_fi_to_lfsc(&fi); - } else { - return arm_fi_to_sfsc(&fi); - } -} - /** * arm_num_brps: Return number of implemented breakpoints. * Note that the ID register BRPS field is "number of bps - 1", diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 80dff0788b..a743061e89 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -379,6 +379,32 @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) return check_watchpoints(cpu); } +/* + * Return the FSR value for a debug exception (watchpoint, hardware + * breakpoint or BKPT insn) targeting the specified exception level. + */ +static uint32_t arm_debug_exception_fsr(CPUARMState *env) +{ + ARMMMUFaultInfo fi = { .type = ARMFault_Debug }; + int target_el = arm_debug_target_el(env); + bool using_lpae = false; + + if (target_el == 2 || arm_el_is_aa64(env, target_el)) { + using_lpae = true; + } else { + if (arm_feature(env, ARM_FEATURE_LPAE) && + (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { + using_lpae = true; + } + } + + if (using_lpae) { + return arm_fi_to_lfsc(&fi); + } else { + return arm_fi_to_sfsc(&fi); + } +} + void arm_debug_excp_handler(CPUState *cs) { /* From patchwork Tue Jun 7 02:47:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 579305 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp4669246max; Mon, 6 Jun 2022 19:59:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy33cgwHF4kH/Nz9RCjtA05s06f9dEH5m98RqsZzS7boywEfzabXlyPZG9GldpNrCWzN1hf X-Received: by 2002:a05:6214:20a1:b0:42d:6f51:46e2 with SMTP id 1-20020a05621420a100b0042d6f5146e2mr75266653qvd.67.1654570789462; Mon, 06 Jun 2022 19:59:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654570789; cv=none; d=google.com; s=arc-20160816; b=GmKuau52dG95O4Nt4cgLMGMcQI+8gQ+Ow0CBGyDDquY7PMgAqv+lBhupA9r2MUX9ot XpGAn7+0AeRljBlcUveWJX+VfsCH2z68vjOKep+0/drf2pHSmZoLPSQLLt3rse2ZSTmA lodOR3O21b3u7ezN+Jr8KSu8fuPfCeJeoP3wpElDR4OZAa0QdvuyhhBvBoWX/lY7eK7W qAHHso5VY15/pIyXeXBXzu4PcueYu+i8JL8wfODoxBrRa89CGjPPCWxadOqXWg6PEFL8 99l1anzSdevAZQUHln0uIYlZUVAxET04+noWxyu/wll1pRzTdR+AfXNe+TjTu+OxkYUD vNiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=9S8DgVIYwXT3v7+Mq8zUaV8sSMq5mSYLW1DSinvTJ/c=; b=f8hEPao2FcP247cSLUBbBPWwbLL0dJOfZPP5getVPRtLiEF30Opkd9xunKjAVgD4v9 gxML1sxItzhq5I2cBLj+KQlU3/tQrFouibCbr9ARv9JYlvqDi2lHsj3aI7Un5kQ9HuFr B29AsQ1ZFzI2WQbGHXgF27r42h+iMJzC+hLY1qqVTMKqGsWKvzRCuWfe8+OyBhwJrvbG Sb62O+DpT52Y59dMbcxVqx+XtTeGkDGjIybeZsCNgXYqZG1Sg9pgpiiWoY4WXHqmRKb4 cVR8hBckLhd78xKrHg6nyJ3i05u2gKZsRgV7Jsz7xt9SE5wcSudBKxj5IsrRwpXwYFx+ c/YA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=S91Jd+1o; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:d3db:cca:e5c9:6531]) by smtp.gmail.com with ESMTPSA id y26-20020aa7805a000000b0051876d83714sm7476904pfm.196.2022.06.06.19.47.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 19:47:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 10/25] target/arm: Rename helper_exception_with_syndrome Date: Mon, 6 Jun 2022 19:47:19 -0700 Message-Id: <20220607024734.541321-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607024734.541321-1-richard.henderson@linaro.org> References: <20220607024734.541321-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rename to helper_exception_with_syndrome_el, to emphasize that the target el is a parameter. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.h | 2 +- target/arm/translate.h | 6 +++--- target/arm/op_helper.c | 6 +++--- target/arm/translate.c | 6 +++--- 4 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index a13007699d..aca86612b4 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -45,7 +45,7 @@ DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32) DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(exception_internal, noreturn, env, i32) -DEF_HELPER_4(exception_with_syndrome, noreturn, env, i32, i32, i32) +DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32) DEF_HELPER_3(exception_advsimdfp_access, noreturn, env, i32, i32) DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) diff --git a/target/arm/translate.h b/target/arm/translate.h index da5f89d49d..1d6a8c7dca 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -332,9 +332,9 @@ static inline void gen_ss_advance(DisasContext *s) static inline void gen_exception(int excp, uint32_t syndrome, uint32_t target_el) { - gen_helper_exception_with_syndrome(cpu_env, tcg_constant_i32(excp), - tcg_constant_i32(syndrome), - tcg_constant_i32(target_el)); + gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), + tcg_constant_i32(syndrome), + tcg_constant_i32(target_el)); } static inline void gen_exception_advsimdfp_access(DisasContext *s, diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index ae0009d1a3..1c4e6753f6 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -373,7 +373,7 @@ void HELPER(yield)(CPUARMState *env) * those EXCP values which are special cases for QEMU to interrupt * execution and not to be used for exceptions which are passed to * the guest (those must all have syndrome information and thus should - * use exception_with_syndrome). + * use exception_with_syndrome*). */ void HELPER(exception_internal)(CPUARMState *env, uint32_t excp) { @@ -385,8 +385,8 @@ void HELPER(exception_internal)(CPUARMState *env, uint32_t excp) } /* Raise an exception with the specified syndrome register value */ -void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp, - uint32_t syndrome, uint32_t target_el) +void HELPER(exception_with_syndrome_el)(CPUARMState *env, uint32_t excp, + uint32_t syndrome, uint32_t target_el) { raise_exception(env, excp, syndrome, target_el); } diff --git a/target/arm/translate.c b/target/arm/translate.c index 87a899d638..dc033600c0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1119,9 +1119,9 @@ static void gen_exception_el(DisasContext *s, int excp, uint32_t syn, { gen_set_condexec(s); gen_set_pc_im(s, s->pc_curr); - gen_helper_exception_with_syndrome(cpu_env, - tcg_constant_i32(excp), - tcg_constant_i32(syn), tcg_el); + gen_helper_exception_with_syndrome_el(cpu_env, + tcg_constant_i32(excp), + tcg_constant_i32(syn), tcg_el); s->base.is_jmp = DISAS_NORETURN; } From patchwork Tue Jun 7 02:47:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 579302 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp4668788max; Mon, 6 Jun 2022 19:58:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzNwfI3SxahHhyq69SnKSzQzpts/PJztBIBDVeG6j2T2h7l60d3XdNRxnk430N7iWeBedvV X-Received: by 2002:a37:aac7:0:b0:6a6:a784:7190 with SMTP id t190-20020a37aac7000000b006a6a7847190mr11609989qke.361.1654570723737; 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([2602:ae:1547:e101:d3db:cca:e5c9:6531]) by smtp.gmail.com with ESMTPSA id y26-20020aa7805a000000b0051876d83714sm7476904pfm.196.2022.06.06.19.47.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 19:47:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 11/25] target/arm: Introduce gen_exception_insn_el_v Date: Mon, 6 Jun 2022 19:47:20 -0700 Message-Id: <20220607024734.541321-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607024734.541321-1-richard.henderson@linaro.org> References: <20220607024734.541321-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a function below gen_exception_insn that takes the target_el as a TCGv_i32, replacing gen_exception_el. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index dc033600c0..9cb31663dd 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1086,8 +1086,8 @@ static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp) s->base.is_jmp = DISAS_NORETURN; } -void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, - uint32_t syn, uint32_t target_el) +static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp, + uint32_t syn, TCGv_i32 tcg_el) { if (s->aarch64) { gen_a64_set_pc_im(pc); @@ -1095,10 +1095,17 @@ void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, gen_set_condexec(s); gen_set_pc_im(s, pc); } - gen_exception(excp, syn, target_el); + gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), + tcg_constant_i32(syn), tcg_el); s->base.is_jmp = DISAS_NORETURN; } +void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, + uint32_t syn, uint32_t target_el) +{ + gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el)); +} + static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) { gen_set_condexec(s); @@ -1114,17 +1121,6 @@ void unallocated_encoding(DisasContext *s) default_exception_el(s)); } -static void gen_exception_el(DisasContext *s, int excp, uint32_t syn, - TCGv_i32 tcg_el) -{ - gen_set_condexec(s); - gen_set_pc_im(s, s->pc_curr); - gen_helper_exception_with_syndrome_el(cpu_env, - tcg_constant_i32(excp), - tcg_constant_i32(syn), tcg_el); - s->base.is_jmp = DISAS_NORETURN; -} - /* Force a TB lookup after an instruction that changes the CPU state. */ void gen_lookup_tb(DisasContext *s) { @@ -2847,7 +2843,8 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, tcg_el = tcg_constant_i32(3); } - gen_exception_el(s, EXCP_UDEF, syn_uncategorized(), tcg_el); + gen_exception_insn_el_v(s, s->pc_curr, EXCP_UDEF, + syn_uncategorized(), tcg_el); tcg_temp_free_i32(tcg_el); return false; } From patchwork Tue Jun 7 02:47:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 579306 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp4671034max; Mon, 6 Jun 2022 20:02:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwJytWCfdirfmvzaQ/7QCxiPxr9XGcPj4gj22ad2poGxi+rIT03dkbiZ6eE1UO4+1E22qqf X-Received: by 2002:a05:6214:238b:b0:456:30d0:140e with SMTP id fw11-20020a056214238b00b0045630d0140emr74514433qvb.84.1654570948558; Mon, 06 Jun 2022 20:02:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654570948; cv=none; d=google.com; s=arc-20160816; b=xPCP4b0mxxsDOAk2Jq7B1GzgDWN2GIj24AHOcznsoMwiqCEz6Ig5tX6sLS4KN/rsic PPm3ni4yCWBEpCqEpfK0LkmJITn+msCDMFBa1SvROjAzwoVMaUl6E0TO6ulYuaJ+ShTE NhvqI5QkW8d1qKRmqKem8p+6WZMxefR3R9kpCX6NQ5BZZqindTwInpg2lBeMCHSgssck kWMqK6WJLcu0KOfnoxqxdTowG8Y7uvLZ50Cs87/adJVS9MjrM+DzplD67655QZ5tTP+3 TYKIlFQaNYD1/qdXbwhrTH7nTLoes8iuQamJW7x2TE79nqW62eChaB1zPULLPNDlZCFv +kjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=S+xsC7lZ+/OAT5GsLdjM1Piovvny0mMzGC3UEnlB6jo=; b=dHagvggV8aVgwh9afcGRiZ/TjQbT+zsrEfillUQc4r2YiALyiQ+OEu5T9mA+Y/cEHH oKu6ga32BhaEX7wtysHXKJSfgCtFot44tQdlUgHE9zbTCADJpjpihwU8JckRzN0u1UcX 5llImxtSVa4EKi8y8tlDSYwT7fmkyiu/UlOOqHAJwC8CUIowqu+mx/k/AvviO26fmJLD v7BRIhZ2zQtRlsX2cEm1vrnspXRPo0EV1bRaSRGiKl1C/bLuhs4fTbbZ5RYNC+V6ZqTI QXam063qoeQldGNVryVHfSLliykDoJrBy/7s8UcZfUc0E7z9VUbOd8WcMsQiiSwo3Efb xyiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="r/ftB78b"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:d3db:cca:e5c9:6531]) by smtp.gmail.com with ESMTPSA id y26-20020aa7805a000000b0051876d83714sm7476904pfm.196.2022.06.06.19.47.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 19:47:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 12/25] target/arm: Rename gen_exception_insn to gen_exception_insn_el Date: Mon, 6 Jun 2022 19:47:21 -0700 Message-Id: <20220607024734.541321-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607024734.541321-1-richard.henderson@linaro.org> References: <20220607024734.541321-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.h | 4 ++-- target/arm/translate-a64.c | 30 +++++++++++++-------------- target/arm/translate-m-nocp.c | 16 +++++++------- target/arm/translate-mve.c | 4 ++-- target/arm/translate-vfp.c | 4 ++-- target/arm/translate.c | 39 ++++++++++++++++++----------------- 6 files changed, 49 insertions(+), 48 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 1d6a8c7dca..c54db51d70 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -279,8 +279,8 @@ void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); void arm_gen_test_cc(int cc, TCGLabel *label); MemOp pow2_align(unsigned i); void unallocated_encoding(DisasContext *s); -void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, - uint32_t syn, uint32_t target_el); +void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp, + uint32_t syn, uint32_t target_el); /* Return state of Alternate Half-precision flag, caller frees result */ static inline TCGv_i32 get_ahp_flag(void) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 3251c69180..cc96535fae 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1178,8 +1178,8 @@ bool sve_access_check(DisasContext *s) assert(!s->sve_access_checked); s->sve_access_checked = true; - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_sve_access_trap(), s->sve_excp_el); + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, + syn_sve_access_trap(), s->sve_excp_el); return false; } s->sve_access_checked = true; @@ -1815,8 +1815,8 @@ static void gen_sysreg_undef(DisasContext *s, bool isread, } else { syndrome = syn_uncategorized(); } - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syndrome, - default_exception_el(s)); + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syndrome, + default_exception_el(s)); } /* MRS - move from system register @@ -2068,8 +2068,8 @@ static void disas_exc(DisasContext *s, uint32_t insn) switch (op2_ll) { case 1: /* SVC */ gen_ss_advance(s); - gen_exception_insn(s, s->base.pc_next, EXCP_SWI, - syn_aa64_svc(imm16), default_exception_el(s)); + gen_exception_insn_el(s, s->base.pc_next, EXCP_SWI, + syn_aa64_svc(imm16), default_exception_el(s)); break; case 2: /* HVC */ if (s->current_el == 0) { @@ -2082,8 +2082,8 @@ static void disas_exc(DisasContext *s, uint32_t insn) gen_a64_set_pc_im(s->pc_curr); gen_helper_pre_hvc(cpu_env); gen_ss_advance(s); - gen_exception_insn(s, s->base.pc_next, EXCP_HVC, - syn_aa64_hvc(imm16), 2); + gen_exception_insn_el(s, s->base.pc_next, EXCP_HVC, + syn_aa64_hvc(imm16), 2); break; case 3: /* SMC */ if (s->current_el == 0) { @@ -2093,8 +2093,8 @@ static void disas_exc(DisasContext *s, uint32_t insn) gen_a64_set_pc_im(s->pc_curr); gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm16))); gen_ss_advance(s); - gen_exception_insn(s, s->base.pc_next, EXCP_SMC, - syn_aa64_smc(imm16), 3); + gen_exception_insn_el(s, s->base.pc_next, EXCP_SMC, + syn_aa64_smc(imm16), 3); break; default: unallocated_encoding(s); @@ -14724,8 +14724,8 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) * Illegal execution state. This has priority over BTI * exceptions, but comes after instruction abort exceptions. */ - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_illegalstate(), default_exception_el(s)); + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, + syn_illegalstate(), default_exception_el(s)); return; } @@ -14756,9 +14756,9 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) if (s->btype != 0 && s->guarded_page && !btype_destination_ok(insn, s->bt, s->btype)) { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_btitrap(s->btype), - default_exception_el(s)); + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, + syn_btitrap(s->btype), + default_exception_el(s)); return; } } else { diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c index 27363a7b4e..636bfb1788 100644 --- a/target/arm/translate-m-nocp.c +++ b/target/arm/translate-m-nocp.c @@ -143,8 +143,8 @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a) tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel); if (s->fp_excp_el != 0) { - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, - syn_uncategorized(), s->fp_excp_el); + gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), s->fp_excp_el); return true; } @@ -376,7 +376,7 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, if (!vfp_access_check_m(s, true)) { /* * This was only a conditional exception, so override - * gen_exception_insn()'s default to DISAS_NORETURN + * gen_exception_insn_el()'s default to DISAS_NORETURN */ s->base.is_jmp = DISAS_NEXT; break; @@ -532,7 +532,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, if (!vfp_access_check_m(s, true)) { /* * This was only a conditional exception, so override - * gen_exception_insn()'s default to DISAS_NORETURN + * gen_exception_insn_el()'s default to DISAS_NORETURN */ s->base.is_jmp = DISAS_NEXT; break; @@ -765,14 +765,14 @@ static bool trans_NOCP(DisasContext *s, arg_nocp *a) } if (a->cp != 10) { - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, - syn_uncategorized(), default_exception_el(s)); + gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), default_exception_el(s)); return true; } if (s->fp_excp_el != 0) { - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, - syn_uncategorized(), s->fp_excp_el); + gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), s->fp_excp_el); return true; } diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 4267d43cc7..5aec2a1555 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -100,8 +100,8 @@ bool mve_eci_check(DisasContext *s) return true; default: /* Reserved value: INVSTATE UsageFault */ - gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), - default_exception_el(s)); + gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), + default_exception_el(s)); return false; } } diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 2a98387411..f939d64101 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -262,8 +262,8 @@ bool vfp_access_check_m(DisasContext *s, bool skip_context_update) * the encoding space handled by the patterns in m-nocp.decode, * and for them we may need to raise NOCP here. */ - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, - syn_uncategorized(), s->fp_excp_el); + gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), s->fp_excp_el); return false; } diff --git a/target/arm/translate.c b/target/arm/translate.c index 9cb31663dd..44f462a3a3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1100,8 +1100,8 @@ static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp, s->base.is_jmp = DISAS_NORETURN; } -void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, - uint32_t syn, uint32_t target_el) +void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp, + uint32_t syn, uint32_t target_el) { gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el)); } @@ -1117,8 +1117,8 @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) void unallocated_encoding(DisasContext *s) { /* Unallocated and reserved encodings are uncategorized */ - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), - default_exception_el(s)); + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), + default_exception_el(s)); } /* Force a TB lookup after an instruction that changes the CPU state. */ @@ -2869,8 +2869,8 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, undef: /* If we get here then some access check did not pass */ - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_uncategorized(), exc_target); + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, + syn_uncategorized(), exc_target); return false; } @@ -5094,7 +5094,8 @@ static void gen_srs(DisasContext *s, * For the UNPREDICTABLE cases we choose to UNDEF. */ if (s->current_el == 1 && !s->ns && mode == ARM_CPU_MODE_MON) { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), 3); + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, + syn_uncategorized(), 3); return; } @@ -8479,8 +8480,8 @@ static bool trans_WLS(DisasContext *s, arg_WLS *a) * Do the check-and-raise-exception by hand. */ if (s->fp_excp_el) { - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, - syn_uncategorized(), s->fp_excp_el); + gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), s->fp_excp_el); return true; } } @@ -8582,8 +8583,8 @@ static bool trans_LE(DisasContext *s, arg_LE *a) tmp = load_cpu_field(v7m.ltpsize); tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc); tcg_temp_free_i32(tmp); - gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), - default_exception_el(s)); + gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), + default_exception_el(s)); gen_set_label(skipexc); } @@ -9053,8 +9054,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) * UsageFault exception. */ if (arm_dc_feature(s, ARM_FEATURE_M)) { - gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), - default_exception_el(s)); + gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), + default_exception_el(s)); return; } @@ -9063,8 +9064,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) * Illegal execution state. This has priority over BTI * exceptions, but comes after instruction abort exceptions. */ - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_illegalstate(), default_exception_el(s)); + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, + syn_illegalstate(), default_exception_el(s)); return; } @@ -9633,8 +9634,8 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) * Illegal execution state. This has priority over BTI * exceptions, but comes after instruction abort exceptions. */ - gen_exception_insn(dc, dc->pc_curr, EXCP_UDEF, - syn_illegalstate(), default_exception_el(dc)); + gen_exception_insn_el(dc, dc->pc_curr, EXCP_UDEF, + syn_illegalstate(), default_exception_el(dc)); return; } @@ -9707,8 +9708,8 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) */ tcg_remove_ops_after(dc->insn_eci_rewind); dc->condjmp = 0; - gen_exception_insn(dc, dc->pc_curr, EXCP_INVSTATE, syn_uncategorized(), - default_exception_el(dc)); + gen_exception_insn_el(dc, dc->pc_curr, EXCP_INVSTATE, syn_uncategorized(), + default_exception_el(dc)); } arm_post_translate_insn(dc); From patchwork Tue Jun 7 02:47:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 579308 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp4673086max; Mon, 6 Jun 2022 20:05:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwUA/7bqErAR1n6+8vssOMCD9nepI9hcRZphryfMrfHAUmNREoldLkz1Q8WiIgbInT+IJVh X-Received: by 2002:a05:620a:2414:b0:6a6:49ad:79b1 with SMTP id d20-20020a05620a241400b006a649ad79b1mr17638067qkn.663.1654571152774; Mon, 06 Jun 2022 20:05:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654571152; cv=none; d=google.com; s=arc-20160816; b=xK9R+6gfcGZx0q+YTN3DnFswHerSDGcN0QEkwHHwfZxaJlaDgXsSde+nyCfSSJciG3 8PIArg2jupkapMnEj2RQ6h1sT7Um/VUhiKJEFBhybQBnp+os7nIL4IlvnkaJzEaL+OkA sSyWM8cbLc8LRvHzPVPcBwogdDSAbC/VE/EcNkYTG7ZlzsraeKgMfj3jNLb7Y/ahgrRD 3kz3kVTiNVgKrd3VRM8zy8b5nAZg4tzcSAXttV36QyIBgPWfKg6E7rHjEBfcwhtL8drj dAeDldaIC/m4UBDGQgzawHq226HFKzyIIXXCtABxM84YKosiQipcDTXggImcOlTghWX0 Gm5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=SJsPBjgxAIzmv4HQ3HMK84E2HfNlE6G2yY4SYv05x4E=; b=GIy88CaF8WZ/t2Da0heSrhDf5WqpeCOkclMa+xp84RmvdN3txIPwMC4bpYb9RwyM7o NITvi0oUAjMtv1Fwfk9dt0dKlvftsRsmSrg65t7HrV0D4fwlB2EbVhubTa2hVTVAQ8T9 PNt9PpHpQPIuumdIoQ8gGRokTKHZoa90SPfaanxKRk5Fl/bF+akVM/SilQN5Jiou1owP DqSPdwTpZX73N/ZUDjL9yWYfpHS/D+vo3IQmiKOyNsOR/qWQwb84fQf0Kr7yNHlnGeGj wUSe2crGVacaKyoYzYVReDgvOsnYvZOen+k2hXXuhy2GHJIQEfQcqsB1rs5yNdFRvJ2k bBig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="b+jR/wV2"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:d3db:cca:e5c9:6531]) by smtp.gmail.com with ESMTPSA id y26-20020aa7805a000000b0051876d83714sm7476904pfm.196.2022.06.06.19.47.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 19:47:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 13/25] target/arm: Introduce gen_exception_insn Date: Mon, 6 Jun 2022 19:47:22 -0700 Message-Id: <20220607024734.541321-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607024734.541321-1-richard.henderson@linaro.org> References: <20220607024734.541321-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a new wrapper function that passes the default exception target to gen_exception_insn_el. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.h | 1 + target/arm/translate-a64.c | 15 ++++++--------- target/arm/translate-m-nocp.c | 3 +-- target/arm/translate-mve.c | 3 +-- target/arm/translate.c | 29 +++++++++++++---------------- 5 files changed, 22 insertions(+), 29 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index c54db51d70..04d45da54e 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -281,6 +281,7 @@ MemOp pow2_align(unsigned i); void unallocated_encoding(DisasContext *s); void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp, uint32_t syn, uint32_t target_el); +void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn); /* Return state of Alternate Half-precision flag, caller frees result */ static inline TCGv_i32 get_ahp_flag(void) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index cc96535fae..a5c66ce085 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1815,8 +1815,7 @@ static void gen_sysreg_undef(DisasContext *s, bool isread, } else { syndrome = syn_uncategorized(); } - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syndrome, - default_exception_el(s)); + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syndrome); } /* MRS - move from system register @@ -2068,8 +2067,8 @@ static void disas_exc(DisasContext *s, uint32_t insn) switch (op2_ll) { case 1: /* SVC */ gen_ss_advance(s); - gen_exception_insn_el(s, s->base.pc_next, EXCP_SWI, - syn_aa64_svc(imm16), default_exception_el(s)); + gen_exception_insn(s, s->base.pc_next, EXCP_SWI, + syn_aa64_svc(imm16)); break; case 2: /* HVC */ if (s->current_el == 0) { @@ -14724,8 +14723,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) * Illegal execution state. This has priority over BTI * exceptions, but comes after instruction abort exceptions. */ - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, - syn_illegalstate(), default_exception_el(s)); + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_illegalstate()); return; } @@ -14756,9 +14754,8 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) if (s->btype != 0 && s->guarded_page && !btype_destination_ok(insn, s->bt, s->btype)) { - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, - syn_btitrap(s->btype), - default_exception_el(s)); + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_btitrap(s->btype)); return; } } else { diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c index 636bfb1788..4029d7fdd4 100644 --- a/target/arm/translate-m-nocp.c +++ b/target/arm/translate-m-nocp.c @@ -765,8 +765,7 @@ static bool trans_NOCP(DisasContext *s, arg_nocp *a) } if (a->cp != 10) { - gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, - syn_uncategorized(), default_exception_el(s)); + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized()); return true; } diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 5aec2a1555..0cf1b5ea4f 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -100,8 +100,7 @@ bool mve_eci_check(DisasContext *s) return true; default: /* Reserved value: INVSTATE UsageFault */ - gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), - default_exception_el(s)); + gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized()); return false; } } diff --git a/target/arm/translate.c b/target/arm/translate.c index 44f462a3a3..c7d422b541 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1106,6 +1106,11 @@ void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp, gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el)); } +void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn) +{ + gen_exception_insn_el(s, pc, excp, syn, default_exception_el(s)); +} + static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) { gen_set_condexec(s); @@ -1117,8 +1122,7 @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) void unallocated_encoding(DisasContext *s) { /* Unallocated and reserved encodings are uncategorized */ - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), - default_exception_el(s)); + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized()); } /* Force a TB lookup after an instruction that changes the CPU state. */ @@ -2731,8 +2735,6 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, * an exception and return false. Otherwise it will return true, * and set *tgtmode and *regno appropriately. */ - int exc_target = default_exception_el(s); - /* These instructions are present only in ARMv8, or in ARMv7 with the * Virtualization Extensions. */ @@ -2869,8 +2871,7 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, undef: /* If we get here then some access check did not pass */ - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, - syn_uncategorized(), exc_target); + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized()); return false; } @@ -8583,8 +8584,7 @@ static bool trans_LE(DisasContext *s, arg_LE *a) tmp = load_cpu_field(v7m.ltpsize); tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc); tcg_temp_free_i32(tmp); - gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), - default_exception_el(s)); + gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized()); gen_set_label(skipexc); } @@ -9054,8 +9054,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) * UsageFault exception. */ if (arm_dc_feature(s, ARM_FEATURE_M)) { - gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), - default_exception_el(s)); + gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized()); return; } @@ -9064,8 +9063,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) * Illegal execution state. This has priority over BTI * exceptions, but comes after instruction abort exceptions. */ - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, - syn_illegalstate(), default_exception_el(s)); + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_illegalstate()); return; } @@ -9634,8 +9632,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) * Illegal execution state. This has priority over BTI * exceptions, but comes after instruction abort exceptions. */ - gen_exception_insn_el(dc, dc->pc_curr, EXCP_UDEF, - syn_illegalstate(), default_exception_el(dc)); + gen_exception_insn(dc, dc->pc_curr, EXCP_UDEF, syn_illegalstate()); return; } @@ -9708,8 +9705,8 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) */ tcg_remove_ops_after(dc->insn_eci_rewind); dc->condjmp = 0; - gen_exception_insn_el(dc, dc->pc_curr, EXCP_INVSTATE, syn_uncategorized(), - default_exception_el(dc)); + gen_exception_insn(dc, dc->pc_curr, EXCP_INVSTATE, + syn_uncategorized()); } arm_post_translate_insn(dc); From patchwork Tue Jun 7 02:47:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 579300 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp4667899max; Mon, 6 Jun 2022 19:56:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxGyMvPkqdU4N9pdEhoSSguqY7iC42LKkpQUWvJGY5WhIrmROVl72eQdf8ac/NM0pVUHRwW X-Received: by 2002:ac8:5a07:0:b0:304:f1aa:b8e8 with SMTP id n7-20020ac85a07000000b00304f1aab8e8mr4040604qta.540.1654570597786; Mon, 06 Jun 2022 19:56:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654570597; cv=none; d=google.com; s=arc-20160816; b=s2XKyYV/+C2VSvkfKnad8UaU416fBHe8h582z9JK1tcIEkmBnYlVdFUhBGLyARVKjQ qMed1+58Mbk+qm4QazCcT2AvmDRLNFMjxb91ZFEhNOHIOylqNXX9PyMgwy45MBNmJiw2 YkeHvn2ekbY42aVxgpxeo6zQ3NtWsv6kF5gmfVFDQ2SQX+v+6f1+ZvxummoLsaXrPfkO hWNhjkMwcJ+sWyyH5oQQpMoe273bQQ8FT9DDMJ490NA4K3ID9PBy7yV1/VCqc2r2vF/9 eGOjydwVMd5Aibhzt3p90eziahf96Ufl8iibvVezfK7xCeF7DmZ4bfywiRA+iI3hV/l1 9muw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=aAUg0t4CNRhFnxvoa04tRoC0cuTYTfVxatS7xBTko0w=; b=Wgll3Y7OoV305N6pxZeDU37MgBRqR2UQNEYoRXvjp5MfVXCFAzs//E42ZlnfzFLeHg HSLtGxX+i+gbu2vA7TsaeDp1gmJPHeUfUyQxrtt7Drdni1vSo6azY2UWHmSr/NFSaE3d ptYTi+ZPfFX8d3fWe5vHgBnTv4iJK87PWKjbopI/CS91DGIRkRgRt7rimWqcbsHS1VB2 yfFJFctoqUbeoO6YKwX5WveSX+ej06kp9wao8goHbds/iMPxE4nUUWRsXwWTZxbHXL59 0OJ65/Z/hnJzWU/bnIALclE5GhtPsrxPhq+YY5m1kJbwrHGNRm4h286GxkB8iluX6irt 9aeQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sa0KsQxp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:d3db:cca:e5c9:6531]) by smtp.gmail.com with ESMTPSA id y26-20020aa7805a000000b0051876d83714sm7476904pfm.196.2022.06.06.19.47.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 19:47:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 14/25] target/arm: Create helper_exception_swstep Date: Mon, 6 Jun 2022 19:47:23 -0700 Message-Id: <20220607024734.541321-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607024734.541321-1-richard.henderson@linaro.org> References: <20220607024734.541321-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the computation from gen_swstep_exception into a helper. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.h | 1 + target/arm/translate.h | 12 +++--------- target/arm/debug_helper.c | 16 ++++++++++++++++ 3 files changed, 20 insertions(+), 9 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index aca86612b4..afc0f1a462 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -48,6 +48,7 @@ DEF_HELPER_2(exception_internal, noreturn, env, i32) DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32) DEF_HELPER_3(exception_advsimdfp_access, noreturn, env, i32, i32) DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) +DEF_HELPER_2(exception_swstep, noreturn, env, i32) DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) DEF_HELPER_1(setend, void, env) DEF_HELPER_2(wfi, void, env, i32) diff --git a/target/arm/translate.h b/target/arm/translate.h index 04d45da54e..c720a7e26c 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -350,15 +350,9 @@ static inline void gen_exception_advsimdfp_access(DisasContext *s, /* Generate an architectural singlestep exception */ static inline void gen_swstep_exception(DisasContext *s, int isv, int ex) { - bool same_el = (s->debug_target_el == s->current_el); - - /* - * If singlestep is targeting a lower EL than the current one, - * then s->ss_active must be false and we can never get here. - */ - assert(s->debug_target_el >= s->current_el); - - gen_exception(EXCP_UDEF, syn_swstep(same_el, isv, ex), s->debug_target_el); + /* Fill in the same_el field of the syndrome in the helper. */ + uint32_t syn = syn_swstep(false, isv, ex); + gen_helper_exception_swstep(cpu_env, tcg_constant_i32(syn)); } /* diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index a743061e89..a3a1b98de2 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -487,6 +487,22 @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) raise_exception(env, EXCP_BKPT, syndrome, debug_el); } +void HELPER(exception_swstep)(CPUARMState *env, uint32_t syndrome) +{ + int debug_el = arm_debug_target_el(env); + int cur_el = arm_current_el(env); + + /* + * If singlestep is targeting a lower EL than the current one, then + * DisasContext.ss_active must be false and we can never get here. + */ + assert(debug_el >= cur_el); + if (debug_el == cur_el) { + syndrome |= 1 << ARM_EL_EC_SHIFT; + } + raise_exception(env, EXCP_UDEF, syndrome, debug_el); +} + #if !defined(CONFIG_USER_ONLY) vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) From patchwork Tue Jun 7 02:47:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 579297 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp4666130max; Mon, 6 Jun 2022 19:53:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx0MFfx0suG+1hnvw2tfNwk0KMxbxr6tP0cjvGSoD8YtKSbolxWe0kh/RIAJ003n6OnKD8h X-Received: by 2002:a05:6214:2a89:b0:464:b97d:b686 with SMTP id jr9-20020a0562142a8900b00464b97db686mr22468134qvb.65.1654570400962; Mon, 06 Jun 2022 19:53:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654570400; cv=none; d=google.com; s=arc-20160816; b=ZTQ51lwba8YYrkpFzPeuRMdP6ARuGAKGjW3fnf7MP7IrRNRqd64kpGHeVvcmy52pmQ 2CTq6iOVimFSp41my8E83Gs5DTQimxSxIO/kZt29MH+CODKHET6Y9x1YqSzoRdsNs0Bh umCTv2Ii6aiHv90lN+HmqDw0xUbW6Y6p6Bq+XmtxjbTN69jm5pdgTgUBVCHnBaDuoG2k GnrcJ2ADCLaNcArl1SFZIYOFY6ALjnNb3xsr6OjPHXRm/b7ToVLnGfHg0nCP1o/1boWy X5cAogYLfgKtV8pSc4tE+IwlhR4rsFbFdyQNoWlc146O7Lyo+loxMLuET737gxnpkIx2 uJmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=QmQpF4c3kmNYfBUp2TaNf+q5uPwew90N4u3cCME1guM=; b=y4IRY/o+voJn4dWTeggjU2Wimhcgc8hWfDsIVrGkYDbyAPLX/Wtoc/d3+RMKnp8yJD bDv+ZM15fPtvIUV9rJmJP0TJQOrSRx4eiDR5HUdkqwrAUvG0Ci2bxljGW1m9Cau8VqiY 491AqDjfOMH7OEwk+ISQ3PSYkaKHoR0bfU8K+TXBhxlLQ8R35x5dv2tufmsCajwVvfNE wt8LN3ewlIfa032deqsmaujwJE2F12VIQA5VD9NI6r7peRYsfHEV4bjughQS3kF9PCsU 9HS7Txj7EDsf80lmy7gwXysuH7SZDjRCxkBjfGBvAnPr++uICFl0sXVTU5HrQR67QaeT VvRA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=S75OyDrH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:d3db:cca:e5c9:6531]) by smtp.gmail.com with ESMTPSA id y26-20020aa7805a000000b0051876d83714sm7476904pfm.196.2022.06.06.19.47.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 19:47:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 15/25] target/arm: Remove TBFLAG_ANY.DEBUG_TARGET_EL Date: Mon, 6 Jun 2022 19:47:24 -0700 Message-Id: <20220607024734.541321-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607024734.541321-1-richard.henderson@linaro.org> References: <20220607024734.541321-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We no longer need this value during translation, as it is now handled within the helpers. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 6 ++---- target/arm/translate.h | 2 -- target/arm/helper.c | 12 ++---------- target/arm/translate-a64.c | 1 - target/arm/translate.c | 1 - 5 files changed, 4 insertions(+), 18 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 92c9758e86..5224dc2c85 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3085,11 +3085,9 @@ FIELD(TBFLAG_ANY, BE_DATA, 3, 1) FIELD(TBFLAG_ANY, MMUIDX, 4, 4) /* Target EL if we take a floating-point-disabled exception */ FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) -/* For A-profile only, target EL for debug exceptions. */ -FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2) /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ -FIELD(TBFLAG_ANY, ALIGN_MEM, 12, 1) -FIELD(TBFLAG_ANY, PSTATE__IL, 13, 1) +FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) +FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) /* * Bit usage when in AArch32 state, both A- and M-profile. diff --git a/target/arm/translate.h b/target/arm/translate.h index c720a7e26c..4a93cac65f 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -59,8 +59,6 @@ typedef struct DisasContext { */ uint32_t svc_imm; int current_el; - /* Debug target exception level for single-step exceptions */ - int debug_target_el; GHashTable *cp_regs; uint64_t features; /* CPU features bits */ bool aarch64; diff --git a/target/arm/helper.c b/target/arm/helper.c index 40da63913c..eeca1a5dc8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13630,18 +13630,10 @@ static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el, return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } -static CPUARMTBFlags rebuild_hflags_aprofile(CPUARMState *env) -{ - CPUARMTBFlags flags = {}; - - DP_TBFLAG_ANY(flags, DEBUG_TARGET_EL, arm_debug_target_el(env)); - return flags; -} - static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx) { - CPUARMTBFlags flags = rebuild_hflags_aprofile(env); + CPUARMTBFlags flags = {}; int el = arm_current_el(env); if (arm_sctlr(env, el) & SCTLR_A) { @@ -13667,7 +13659,7 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, ARMMMUIdx mmu_idx) { - CPUARMTBFlags flags = rebuild_hflags_aprofile(env); + CPUARMTBFlags flags = {}; ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; uint64_t sctlr; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a5c66ce085..b45039a124 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14644,7 +14644,6 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->ss_active = EX_TBFLAG_ANY(tb_flags, SS_ACTIVE); dc->pstate_ss = EX_TBFLAG_ANY(tb_flags, PSTATE__SS); dc->is_ldex = false; - dc->debug_target_el = EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL); /* Bound the number of insns to execute to those left on the page. */ bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; diff --git a/target/arm/translate.c b/target/arm/translate.c index c7d422b541..b8a8972bac 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9350,7 +9350,6 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->v7m_lspact = EX_TBFLAG_M32(tb_flags, LSPACT); dc->mve_no_pred = EX_TBFLAG_M32(tb_flags, MVE_NO_PRED); } else { - dc->debug_target_el = EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL); dc->sctlr_b = EX_TBFLAG_A32(tb_flags, SCTLR__B); dc->hstr_active = EX_TBFLAG_A32(tb_flags, HSTR_ACTIVE); dc->ns = EX_TBFLAG_A32(tb_flags, NS); From patchwork Tue Jun 7 02:47:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 579303 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp4669057max; Mon, 6 Jun 2022 19:59:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz5nQbact379CpI1Gurg0FQnWcseIETmBl2ZWLXyHHEF9HAuJikjzajNMpidg4soVPej3y5 X-Received: by 2002:a05:6214:2a89:b0:464:b97d:b686 with SMTP id jr9-20020a0562142a8900b00464b97db686mr22477020qvb.65.1654570762087; Mon, 06 Jun 2022 19:59:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654570762; cv=none; d=google.com; s=arc-20160816; b=fbxDrGZSW+tqCkH3tP0EQmv0DFJQJ98hoTd7HbDD/ACIRZ5KLug08f8jwD4YmAeTU2 coP1kNTSu3nZH9faL2tMMDmGXX9C3UNES85I0VQPML54TB1gl5huuPcSQIdyiWYbY59L uHJB0IQhXvODdy2Vx3gqQ11VtehiHGPWqNMlKPnB83Hpt5X911TqeN4NrcG0C5KBgpBH aqXxzOsMt9JcSl7bE5LmPgZI4TEh8DjooxEO4+82jyWSIjuGn5XLbG4LdDV429bLHF6B NlA7cTN54w/5a5d+PGjKMkvDjeg3FppuNLAVa8LOHM6huQu7u8jqtJ4lzH1e+N9JYCd7 QXfQ== ARC-Message-Signature: i=1; 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([2602:ae:1547:e101:d3db:cca:e5c9:6531]) by smtp.gmail.com with ESMTPSA id y26-20020aa7805a000000b0051876d83714sm7476904pfm.196.2022.06.06.19.47.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 19:47:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 16/25] target/arm: Move gen_exception to translate.c Date: Mon, 6 Jun 2022 19:47:25 -0700 Message-Id: <20220607024734.541321-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607024734.541321-1-richard.henderson@linaro.org> References: <20220607024734.541321-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This function is not required by any other translation file. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.h | 8 -------- target/arm/translate.c | 7 +++++++ 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 4a93cac65f..d7a9acf5a9 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -328,14 +328,6 @@ static inline void gen_ss_advance(DisasContext *s) } } -static inline void gen_exception(int excp, uint32_t syndrome, - uint32_t target_el) -{ - gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), - tcg_constant_i32(syndrome), - tcg_constant_i32(target_el)); -} - static inline void gen_exception_advsimdfp_access(DisasContext *s, uint32_t syndrome) { diff --git a/target/arm/translate.c b/target/arm/translate.c index b8a8972bac..fc5eafaeeb 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1086,6 +1086,13 @@ static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp) s->base.is_jmp = DISAS_NORETURN; } +static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el) +{ + gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), + tcg_constant_i32(syndrome), + tcg_constant_i32(target_el)); +} + static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp, uint32_t syn, TCGv_i32 tcg_el) { From patchwork Tue Jun 7 02:47:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 579304 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp4669206max; Mon, 6 Jun 2022 19:59:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwkOzsyras16zZrZI+FgbwPyzt9qUdcDQ6g9Dv5Yl13sIrPuSqtkNocQ6mC49CMIUBCMKPm X-Received: by 2002:a05:622a:188:b0:304:f343:bba2 with SMTP id s8-20020a05622a018800b00304f343bba2mr3576750qtw.377.1654570783331; Mon, 06 Jun 2022 19:59:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654570783; cv=none; d=google.com; s=arc-20160816; b=pkfsdH48u9TfUaW+ha8Vczf7xtbZAW8jmKUQieuPITfunv5oUVZXenhitwn04Z2FuD Am8KghLRP0YhWXaZTiPg9sjM0BYwJnRkUB7liFd9NWnw3EW01mPhPZmawIHporbENs/v M3siSiz5XRcHXKzqmmj06iVw66ImNnzKu/VCFp2xuBYZ79UIHOmtQlldd8L8dM+4nPiC 79AL6A18AQm0xerMzt54Ld5aVbh/5WKQyD1zLHqR4vgs5qLmNpb2DBfmt+u/tTrfiHMo ZOHbI+gZ8JeQ++sjsaHGEZ8hNE8xEqdS8JSi081vSh6hVRY+b8bmh47RW1tVQ20TFHsM Gt2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=hm5AJJ9rtEtZQmXdNnCESF6lpmFEuqmd0isJFAw5U8U=; b=o2ilMCfrFOXIxuHaNSn4W10pRhnh+OESg5ILbYBMskGPPFAuUWDs/olCCeqamKjC5I nz6QHHxMCMsDP6a7PY+o/Z2R6mPFWOcZMXsNxRjkzY4JICVgmQkzNCifbGosC2S1aZJM OeD4lKasJsD4ggTB4vzrZldhEzPr9hIN83lu8RZ818LuEcGl1DwTQBTV7CmYsy6gbf9d ROOSZfeFwrJjgyeYP8yjIsHsUAXPZuOFAGBIUkWV3869rfaYufgK2VDWeOx6Wnwi48El 27IenZIOpDFzBT43kTOm3VKMjat3M9Q2O7/49uw7dlvhtIsoxn4zssLelb4JoE4eVCef S8Mg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MVRno+eq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:d3db:cca:e5c9:6531]) by smtp.gmail.com with ESMTPSA id y26-20020aa7805a000000b0051876d83714sm7476904pfm.196.2022.06.06.19.47.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 19:47:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 17/25] target/arm: Rename gen_exception to gen_exception_el Date: Mon, 6 Jun 2022 19:47:26 -0700 Message-Id: <20220607024734.541321-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607024734.541321-1-richard.henderson@linaro.org> References: <20220607024734.541321-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index fc5eafaeeb..edb7d3f394 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1086,7 +1086,7 @@ static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp) s->base.is_jmp = DISAS_NORETURN; } -static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el) +static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el) { gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), tcg_constant_i32(syndrome), @@ -9758,16 +9758,16 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) switch (dc->base.is_jmp) { case DISAS_SWI: gen_ss_advance(dc); - gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), - default_exception_el(dc)); + gen_exception_el(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), + default_exception_el(dc)); break; case DISAS_HVC: gen_ss_advance(dc); - gen_exception(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2); + gen_exception_el(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2); break; case DISAS_SMC: gen_ss_advance(dc); - gen_exception(EXCP_SMC, syn_aa32_smc(), 3); + gen_exception_el(EXCP_SMC, syn_aa32_smc(), 3); break; case DISAS_NEXT: case DISAS_TOO_MANY: @@ -9828,14 +9828,14 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) gen_helper_yield(cpu_env); break; case DISAS_SWI: - gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), - default_exception_el(dc)); + gen_exception_el(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), + default_exception_el(dc)); break; case DISAS_HVC: - gen_exception(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2); + gen_exception_el(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2); break; case DISAS_SMC: - gen_exception(EXCP_SMC, syn_aa32_smc(), 3); + gen_exception_el(EXCP_SMC, syn_aa32_smc(), 3); break; } } From patchwork Tue Jun 7 02:47:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 579309 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp4673840max; Mon, 6 Jun 2022 20:07:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxRggL4LGMvJ5Lhg3FzR1/R/cxsRA3mVl4iNL0VzSHOziplEb3oXv9zzj8y8BfV6zmyiKsU X-Received: by 2002:ad4:5c84:0:b0:464:5827:c6a7 with SMTP id o4-20020ad45c84000000b004645827c6a7mr30929269qvh.37.1654571249555; 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([2602:ae:1547:e101:d3db:cca:e5c9:6531]) by smtp.gmail.com with ESMTPSA id y26-20020aa7805a000000b0051876d83714sm7476904pfm.196.2022.06.06.19.47.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 19:47:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 18/25] target/arm: Introduce gen_exception Date: Mon, 6 Jun 2022 19:47:27 -0700 Message-Id: <20220607024734.541321-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607024734.541321-1-richard.henderson@linaro.org> References: <20220607024734.541321-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a new wrapper function that passes the default exception target to gen_exception_el. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index edb7d3f394..5a48937ede 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1093,6 +1093,11 @@ static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el) tcg_constant_i32(target_el)); } +static void gen_exception(DisasContext *s, int excp, uint32_t syndrome) +{ + gen_exception_el(excp, syndrome, default_exception_el(s)); +} + static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp, uint32_t syn, TCGv_i32 tcg_el) { @@ -9758,8 +9763,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) switch (dc->base.is_jmp) { case DISAS_SWI: gen_ss_advance(dc); - gen_exception_el(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), - default_exception_el(dc)); + gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb)); break; case DISAS_HVC: gen_ss_advance(dc); @@ -9828,8 +9832,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) gen_helper_yield(cpu_env); break; case DISAS_SWI: - gen_exception_el(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), - default_exception_el(dc)); + gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb)); break; case DISAS_HVC: gen_exception_el(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2); From patchwork Tue Jun 7 02:47:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 579311 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp4675816max; Mon, 6 Jun 2022 20:11:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx3iGC1krOwJp7zFSLc85hgNfngu+qkg88INc+vVFFb444RQGrzEtbnS1X4UNAYmTdwURig X-Received: by 2002:a05:620a:2907:b0:6a5:723a:e291 with SMTP id m7-20020a05620a290700b006a5723ae291mr17830834qkp.36.1654571479235; Mon, 06 Jun 2022 20:11:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654571479; cv=none; d=google.com; s=arc-20160816; b=UbFLLn0+O5Ln7Fv6kZkp4f9D9bKmC6M3GP4a4ImDn4OSzJRQhVFY7UoOc0k4bUzgmc SOkawm9jmixr4MsGub1yk9JXRc3waKJq67GO0RrtQK01ynZDn2vJE5AkLypYmtH4O7mZ oKGzIP2H33VAPgJAE3LOA1yP7g8Hp2MoLzu0TH8oFpcQqydhv/knaX8s5EKNNiQoAgsm gX5pV+aj7RjBAi0/csMEhWbUtj+6bXSlm1+gGyESAU9e5wdiDQFBXxUO6YaMjogLriBu RctIB+AXISrYPtcSRcwHUElzO2x/dxLO2wufy86lU6wy/kbjhCGiZjT7wM2DJXRgIuwW xHqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=sDCwZBt9IIzx83ZkNxq+1Z/y6VvrCzl9tcBCjhjfsAo=; b=e6pz08X3UDZL8onZumaW37JW5Kz8ndHEXznrLQ4+AGmGCELQ8Ll7aLksBMUXs6zAyQ N+cVBU9HlUOtnpfBYHTjXobdC/d3IFt4vpePB8blGjZJCPBT/fa+PqYyibqAvGtMMQ58 mcjcB9NeRR9bYF7rx0ja0B09vh1W6UL7P0VaRxAtWv2vPBxuWrOAxpfrXBKhcNEqpjtL r6c/tGyLl+rXVrceP/6ZdalLJQQxHkqpgIh85b5PP/DtZVi7sIC7WmexGEbRb1sO9wXq MEqnwBdb9oekmC6UWdMBATonOygBk1828i3arrrLELtyh6tTwEoNBKme6bjcNnKBBHjt Tg0w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WRptN6pd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:d3db:cca:e5c9:6531]) by smtp.gmail.com with ESMTPSA id y26-20020aa7805a000000b0051876d83714sm7476904pfm.196.2022.06.06.19.47.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 19:47:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 19/25] target/arm: Introduce gen_exception_el_v Date: Mon, 6 Jun 2022 19:47:28 -0700 Message-Id: <20220607024734.541321-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607024734.541321-1-richard.henderson@linaro.org> References: <20220607024734.541321-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split out a common helper function for gen_exception_el and gen_exception_insn_el_v. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 5a48937ede..fcb6ee648b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1086,11 +1086,15 @@ static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp) s->base.is_jmp = DISAS_NORETURN; } -static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el) +static void gen_exception_el_v(int excp, uint32_t syndrome, TCGv_i32 tcg_el) { gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), - tcg_constant_i32(syndrome), - tcg_constant_i32(target_el)); + tcg_constant_i32(syndrome), tcg_el); +} + +static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el) +{ + gen_exception_el_v(excp, syndrome, tcg_constant_i32(target_el)); } static void gen_exception(DisasContext *s, int excp, uint32_t syndrome) @@ -1107,8 +1111,7 @@ static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp, gen_set_condexec(s); gen_set_pc_im(s, pc); } - gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), - tcg_constant_i32(syn), tcg_el); + gen_exception_el_v(excp, syn, tcg_el); s->base.is_jmp = DISAS_NORETURN; } From patchwork Tue Jun 7 02:47:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 579313 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp4679177max; Mon, 6 Jun 2022 20:16:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy8oxit41ZblVPPGDdxoYvquR5jZvSjpC4etliLCKVIcw9E5lyNcOHkp7d+PBKccDlniYdG X-Received: by 2002:a05:620a:1535:b0:6a6:8fdb:29e4 with SMTP id n21-20020a05620a153500b006a68fdb29e4mr15372451qkk.126.1654571812785; Mon, 06 Jun 2022 20:16:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654571812; cv=none; d=google.com; s=arc-20160816; b=TTkctOWAVhH8sn2NwoIQ5UmlUOvreOsDRKDpjH2YwGydfiGUyII5WSfY/6oPWEoPuw 1qfbB8g/A8YnJU1QrEPeKYydWQXgz9um77w5c/iq+3LlaOD5kjYSs55vAu/UrK87fCLb LtmXPzQI5pmI1jcKsWSR9XCDPy2Y8UpgwmGkgergScMiA5P9pis50ZqjHGlaroIjNXA6 Fj6PRmgvSJ39HRG86ufWBvg5sAX1P6K1NJeYjuRbxd7hAPbLxuNcUrpXCe/ZpnynnUVD 14z2SYEIF3tXTHcEud6wCJ95sMT7JQOw1cCpjILnMlMrlU5p03qDE5jxFkHTCagm9gb+ glPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=fmcSScOvBsLp1FCuWvkHw14JpRNt+9SUrqF6b0wzTB4=; b=WV9gecBtiBNqW5ad4Sr1VcJHfeLPYB8rzezc60G/hvJTdTsxRRnletRQcWPv0CKJmo t2WNjotpVseQJltEXjc2ZKhrYR6WVROQdimtC3TCJmbUSJUZkAKrBHOk4PKwGaSYxs2M IH50wHSHUqndOI6WZUjdDz9JAZ8iiLNf9Mul+cjpAJcFKXbePg955HtEHsz+MFBfT2aM m6vsep4qYqSqybUXLNPp3gEDU+HTxWhY8W8uslYXNnNriXlL0ardjnqqUepSDXm9F3lG H1I1ArpuLcjZJ+NCC8B7Ewbe8niBRz+QtZDUOL/IMAN1zNG+7nJc+StuIKc1pGib9Wxn JJjg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gQCRtQE9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:d3db:cca:e5c9:6531]) by smtp.gmail.com with ESMTPSA id y26-20020aa7805a000000b0051876d83714sm7476904pfm.196.2022.06.06.19.47.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 19:47:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 20/25] target/arm: Introduce helper_exception_with_syndrome Date: Mon, 6 Jun 2022 19:47:29 -0700 Message-Id: <20220607024734.541321-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607024734.541321-1-richard.henderson@linaro.org> References: <20220607024734.541321-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" With the helper we can use exception_target_el at runtime, instead of default_exception_el at translate time. While we're at it, remove the DisasContext parameter from gen_exception, as it is no longer used. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.h | 1 + target/arm/op_helper.c | 10 ++++++++++ target/arm/translate.c | 18 +++++++++++++----- 3 files changed, 24 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index afc0f1a462..7c8133f83a 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -45,6 +45,7 @@ DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32) DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(exception_internal, noreturn, env, i32) +DEF_HELPER_3(exception_with_syndrome, noreturn, env, i32, i32) DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32) DEF_HELPER_3(exception_advsimdfp_access, noreturn, env, i32, i32) DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 1c4e6753f6..32e2a92ff4 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -391,6 +391,16 @@ void HELPER(exception_with_syndrome_el)(CPUARMState *env, uint32_t excp, raise_exception(env, excp, syndrome, target_el); } +/* + * Raise an exception with the specified syndrome register value + * to the default target el. + */ +void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp, + uint32_t syndrome) +{ + raise_exception(env, excp, syndrome, exception_target_el(env)); +} + /* Raise an exception with EC_ADVSIMDFPACCESS. */ void HELPER(exception_advsimdfp_access)(CPUARMState *env, uint32_t syndrome, uint32_t target_el) diff --git a/target/arm/translate.c b/target/arm/translate.c index fcb6ee648b..81c27e7c70 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1097,9 +1097,10 @@ static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el) gen_exception_el_v(excp, syndrome, tcg_constant_i32(target_el)); } -static void gen_exception(DisasContext *s, int excp, uint32_t syndrome) +static void gen_exception(int excp, uint32_t syndrome) { - gen_exception_el(excp, syndrome, default_exception_el(s)); + gen_helper_exception_with_syndrome(cpu_env, tcg_constant_i32(excp), + tcg_constant_i32(syndrome)); } static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp, @@ -1123,7 +1124,14 @@ void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp, void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn) { - gen_exception_insn_el(s, pc, excp, syn, default_exception_el(s)); + if (s->aarch64) { + gen_a64_set_pc_im(pc); + } else { + gen_set_condexec(s); + gen_set_pc_im(s, pc); + } + gen_exception(excp, syn); + s->base.is_jmp = DISAS_NORETURN; } static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) @@ -9766,7 +9774,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) switch (dc->base.is_jmp) { case DISAS_SWI: gen_ss_advance(dc); - gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb)); + gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb)); break; case DISAS_HVC: gen_ss_advance(dc); @@ -9835,7 +9843,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) gen_helper_yield(cpu_env); break; case DISAS_SWI: - gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb)); + gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb)); break; case DISAS_HVC: gen_exception_el(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2); From patchwork Tue Jun 7 02:47:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 579314 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp4680551max; Mon, 6 Jun 2022 20:19:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJybnTaknQK/rosOwnlK0gosfrloE+INFpzzbJ/ofKNPRlHzM0WzTpLLcxEBH1qBD+odOkT9 X-Received: by 2002:a05:620a:2a14:b0:6a3:8820:283e with SMTP id o20-20020a05620a2a1400b006a38820283emr18345312qkp.53.1654571970976; Mon, 06 Jun 2022 20:19:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654571970; cv=none; d=google.com; s=arc-20160816; b=Xp+SSeboekdEbrL2cHUWa0ANr5EPa14qfqGV03PvhUbo+4uO3P54404h8jxMalc2bJ yfDXgCcfOKFZXG2WcRwY2p5rwf9fynZMH/hZKUiaig/4S5COj0Cd2TmBNROFQBRx4Om5 yP/8ceXAkRvYMLsUzv16mC0zBWmUzWJCsxUeRs9mMyS/8koWSiVVTHclEXbniccgrUfQ z/F9fhifsPlZCNgDFdRP1nON8e0s412KsMFIQdgwbB4khg0DbDnWI5UDRq31Rzp+Msw3 7Yow4BJzZDhATk8+pX8JuczShze/YRWAC3RSZNfthv7Cdf1WEPkgfHaRwrzYMSnWbU3o APuw== ARC-Message-Signature: i=1; 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([2602:ae:1547:e101:d3db:cca:e5c9:6531]) by smtp.gmail.com with ESMTPSA id y26-20020aa7805a000000b0051876d83714sm7476904pfm.196.2022.06.06.19.47.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 19:47:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 21/25] target/arm: Remove default_exception_el Date: Mon, 6 Jun 2022 19:47:30 -0700 Message-Id: <20220607024734.541321-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607024734.541321-1-richard.henderson@linaro.org> References: <20220607024734.541321-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This function is no longer used. At the same time, remove DisasContext.secure_routed_to_el3, as it in turn becomes unused. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.h | 16 ---------------- target/arm/translate-a64.c | 5 ----- target/arm/translate.c | 5 ----- 3 files changed, 26 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index d7a9acf5a9..b01a58653e 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -43,8 +43,6 @@ typedef struct DisasContext { int fp_excp_el; /* FP exception EL or 0 if enabled */ int sve_excp_el; /* SVE exception EL or 0 if enabled */ int sve_len; /* SVE vector length in bytes */ - /* Flag indicating that exceptions from secure mode are routed to EL3. */ - bool secure_routed_to_el3; bool vfp_enabled; /* FP enabled via FPSCR.EN */ int vec_len; int vec_stride; @@ -199,20 +197,6 @@ static inline int get_mem_index(DisasContext *s) return arm_to_core_mmu_idx(s->mmu_idx); } -/* Function used to determine the target exception EL when otherwise not known - * or default. - */ -static inline int default_exception_el(DisasContext *s) -{ - /* If we are coming from secure EL0 in a system with a 32-bit EL3, then - * there is no secure EL1, so we route exceptions to EL3. Otherwise, - * exceptions can only be routed to ELs above 1, so we target the higher of - * 1 or the current EL. - */ - return (s->mmu_idx == ARMMMUIdx_SE10_0 && s->secure_routed_to_el3) - ? 3 : MAX(1, s->current_el); -} - static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) { /* We don't need to save all of the syndrome so we mask and shift diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b45039a124..8da2ca8324 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14584,11 +14584,6 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->condjmp = 0; dc->aarch64 = true; - /* If we are coming from secure EL0 in a system with a 32-bit EL3, then - * there is no secure EL1, so we route exceptions to EL3. - */ - dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) && - !arm_el_is_aa64(env, 3); dc->thumb = false; dc->sctlr_b = 0; dc->be_data = EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE; diff --git a/target/arm/translate.c b/target/arm/translate.c index 81c27e7c70..6617de775f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9319,11 +9319,6 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->condjmp = 0; dc->aarch64 = false; - /* If we are coming from secure EL0 in a system with a 32-bit EL3, then - * there is no secure EL1, so we route exceptions to EL3. - */ - dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) && - !arm_el_is_aa64(env, 3); dc->thumb = EX_TBFLAG_AM32(tb_flags, THUMB); dc->be_data = EX_TBFLAG_ANY(tb_flags, BE_DATA) ? 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([2602:ae:1547:e101:d3db:cca:e5c9:6531]) by smtp.gmail.com with ESMTPSA id y26-20020aa7805a000000b0051876d83714sm7476904pfm.196.2022.06.06.19.47.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 19:47:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 22/25] target/arm: Create raise_exception_debug Date: Mon, 6 Jun 2022 19:47:31 -0700 Message-Id: <20220607024734.541321-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607024734.541321-1-richard.henderson@linaro.org> References: <20220607024734.541321-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Handle the debug vs current el exception test in one place. Leave EXCP_BKPT alone, since that treats debug < current differently. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/debug_helper.c | 44 +++++++++++++++++++++------------------ 1 file changed, 24 insertions(+), 20 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index a3a1b98de2..26004df99b 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -12,6 +12,26 @@ #include "exec/helper-proto.h" +/* + * Raise an exception to the debug target el. + * Modify syndrome to indicate when origin and target EL are the same. + */ +G_NORETURN static void +raise_exception_debug(CPUARMState *env, uint32_t excp, uint32_t syndrome) +{ + int debug_el = arm_debug_target_el(env); + int cur_el = arm_current_el(env); + + /* + * If singlestep is targeting a lower EL than the current one, then + * DisasContext.ss_active must be false and we can never get here. + * Similarly for watchpoint and breakpoint matches. + */ + assert(debug_el >= cur_el); + syndrome |= (debug_el == cur_el) << ARM_EL_EC_SHIFT; + raise_exception(env, excp, syndrome, debug_el); +} + /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ static bool aa64_generate_debug_exceptions(CPUARMState *env) { @@ -418,19 +438,16 @@ void arm_debug_excp_handler(CPUState *cs) if (wp_hit) { if (wp_hit->flags & BP_CPU) { bool wnr = (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) != 0; - bool same_el = arm_debug_target_el(env) == arm_current_el(env); cs->watchpoint_hit = NULL; env->exception.fsr = arm_debug_exception_fsr(env); env->exception.vaddress = wp_hit->hitaddr; - raise_exception(env, EXCP_DATA_ABORT, - syn_watchpoint(same_el, 0, wnr), - arm_debug_target_el(env)); + raise_exception_debug(env, EXCP_DATA_ABORT, + syn_watchpoint(0, 0, wnr)); } } else { uint64_t pc = is_a64(env) ? env->pc : env->regs[15]; - bool same_el = (arm_debug_target_el(env) == arm_current_el(env)); /* * (1) GDB breakpoints should be handled first. @@ -450,9 +467,7 @@ void arm_debug_excp_handler(CPUState *cs) * exception/security level. */ env->exception.vaddress = 0; - raise_exception(env, EXCP_PREFETCH_ABORT, - syn_breakpoint(same_el), - arm_debug_target_el(env)); + raise_exception_debug(env, EXCP_PREFETCH_ABORT, syn_breakpoint(0)); } } @@ -489,18 +504,7 @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) void HELPER(exception_swstep)(CPUARMState *env, uint32_t syndrome) { - int debug_el = arm_debug_target_el(env); - int cur_el = arm_current_el(env); - - /* - * If singlestep is targeting a lower EL than the current one, then - * DisasContext.ss_active must be false and we can never get here. - */ - assert(debug_el >= cur_el); - if (debug_el == cur_el) { - syndrome |= 1 << ARM_EL_EC_SHIFT; - } - raise_exception(env, EXCP_UDEF, syndrome, debug_el); + raise_exception_debug(env, EXCP_UDEF, syndrome); } #if !defined(CONFIG_USER_ONLY) From patchwork Tue Jun 7 02:47:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 579312 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp4678752max; Mon, 6 Jun 2022 20:16:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxfoOY8GvgFthK0pNYLbUmgPGbWp0JxGZapwzoqEjp4AzQ+3hj3Xnq+HTzUsLZ/fVD2Sm/d X-Received: by 2002:a05:620a:4150:b0:6a3:7c8b:9796 with SMTP id k16-20020a05620a415000b006a37c8b9796mr18263655qko.18.1654571766373; Mon, 06 Jun 2022 20:16:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654571766; cv=none; d=google.com; s=arc-20160816; b=D0cGowQDplgtYUYR8RCVOWH3c34A5hQRjHbL/KYG5jE446weOmx0RI4wwo6kfoUkqK QliVZwZ+P39gvEW2nY9QuY2tSjEcygxxuc4dtmvQkgwd30wPsGBIshYxbbMhavCQ3Tl8 j4mA2U6H4MmCIq31PPketkw99VoLwGKFiqn0A4MNmhwmV+Tbn//L/PtqjlqHz4N7BEAr IJmMMt3G8mQmZIJ97zcCHZkY3xRml1o2pCiPr366CXC4Ng5g9L4/AW0ilgy5CCwaGPk3 7PDhG63Vdz7gGKDyr2/aQExfRMJGMG8iXz6PbfiRCJxi2SEO4pTeCWy2KZK0lrs2Nkqw nePA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=DResuf4yvFSsZX3asYb/x0WdRbn6myIqroBLohdXR6s=; b=Ea12KWf6zUmadMUD16+BSQS2iomEVs02AoRQJrNXZ0Sc80UYc6++JcchOrBhZRCEDI zkVccNxxnRez/u2BB1zBMoeNO7sk85h7dnjVpZJURvD5KgvUUaimoj6cGp2bRDyYuBB8 Y6kwVsdt7mHfsBXxW+tHEWgZg6yEoXSDZ0L9Sha3Y5Yqhx6/BNYHIxkQM9if4d1VnzpG UqGws2lHIIbvsHfTqv+8r782yKbHqxIVdvwL4h4ugbk93eCQ7cG4YtV4Vm758LhCRHU6 HG2kTZqLgteapIwaTW4yaSqIK59/s5WKP22Ku6F9k+EhqWny4HsI89xGf9ApafDfBw97 NwKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="T1iGVGo/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:d3db:cca:e5c9:6531]) by smtp.gmail.com with ESMTPSA id y26-20020aa7805a000000b0051876d83714sm7476904pfm.196.2022.06.06.19.47.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 19:47:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 23/25] target/arm: Move arm_debug_target_el to debug_helper.c Date: Mon, 6 Jun 2022 19:47:32 -0700 Message-Id: <20220607024734.541321-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607024734.541321-1-richard.henderson@linaro.org> References: <20220607024734.541321-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This function is no longer used outside debug_helper.c. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 21 --------------------- target/arm/debug_helper.c | 21 +++++++++++++++++++++ 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5224dc2c85..5bc6382fce 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2967,27 +2967,6 @@ typedef enum ARMASIdx { ARMASIdx_TagS = 3, } ARMASIdx; -/* Return the Exception Level targeted by debug exceptions. */ -static inline int arm_debug_target_el(CPUARMState *env) -{ - bool secure = arm_is_secure(env); - bool route_to_el2 = false; - - if (arm_is_el2_enabled(env)) { - route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || - env->cp15.mdcr_el2 & MDCR_TDE; - } - - if (route_to_el2) { - return 2; - } else if (arm_feature(env, ARM_FEATURE_EL3) && - !arm_el_is_aa64(env, 3) && secure) { - return 3; - } else { - return 1; - } -} - static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) { /* If all the CLIDR.Ctypem bits are 0 there are no caches, and diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 26004df99b..b18a6bd3a2 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -12,6 +12,27 @@ #include "exec/helper-proto.h" +/* Return the Exception Level targeted by debug exceptions. */ +static int arm_debug_target_el(CPUARMState *env) +{ + bool secure = arm_is_secure(env); + bool route_to_el2 = false; + + if (arm_is_el2_enabled(env)) { + route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || + env->cp15.mdcr_el2 & MDCR_TDE; + } + + if (route_to_el2) { + return 2; + } else if (arm_feature(env, ARM_FEATURE_EL3) && + !arm_el_is_aa64(env, 3) && secure) { + return 3; + } else { + return 1; + } +} + /* * Raise an exception to the debug target el. * Modify syndrome to indicate when origin and target EL are the same. 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([2602:ae:1547:e101:d3db:cca:e5c9:6531]) by smtp.gmail.com with ESMTPSA id y26-20020aa7805a000000b0051876d83714sm7476904pfm.196.2022.06.06.19.47.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 19:47:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 24/25] target/arm: Rearrange Secure PL1 test in arm_debug_target_el Date: Mon, 6 Jun 2022 19:47:33 -0700 Message-Id: <20220607024734.541321-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607024734.541321-1-richard.henderson@linaro.org> References: <20220607024734.541321-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Not a bug, because arm_is_el2_enabled tests for secure, and SCR_EL3.EEL2 cannot be set for AArch32, however the ordering of the tests looks odd. Mirror the structure over in exception_target_el(). Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/debug_helper.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index b18a6bd3a2..59dfcb5d5c 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -15,22 +15,24 @@ /* Return the Exception Level targeted by debug exceptions. */ static int arm_debug_target_el(CPUARMState *env) { - bool secure = arm_is_secure(env); - bool route_to_el2 = false; - - if (arm_is_el2_enabled(env)) { - route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || - env->cp15.mdcr_el2 & MDCR_TDE; - } - - if (route_to_el2) { - return 2; - } else if (arm_feature(env, ARM_FEATURE_EL3) && - !arm_el_is_aa64(env, 3) && secure) { + /* + * No such thing as secure EL1 if EL3 is AArch32. + * Remap Secure PL1 to EL3. + */ + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { return 3; - } else { - return 1; } + + /* + * HCR.TGE redirects EL0 exceptions from EL1 to EL2. + * MDCR.TDE redirects both EL0 and EL1 debug exceptions to EL2. + */ + if (arm_is_el2_enabled(env) && + (env->cp15.hcr_el2 & HCR_TGE || env->cp15.mdcr_el2 & MDCR_TDE)) { + return 2; + } + + return 1; } /* From patchwork Tue Jun 7 02:47:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 579315 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp4681466max; Mon, 6 Jun 2022 20:21:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyducO6NwTeMZJYRe4ZY/UMG2iNu/OLbDzIwEhIoq+u62LWjFrnxYud6yXd9uaUwoD1QfXZ X-Received: by 2002:a37:2750:0:b0:6a6:9ee2:5f5c with SMTP id n77-20020a372750000000b006a69ee25f5cmr13034474qkn.558.1654572084425; Mon, 06 Jun 2022 20:21:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654572084; cv=none; d=google.com; s=arc-20160816; b=AjsemDcnSyvlrtIv/OnQW49p0IJ7mT1pCKlYSkeGVLO0qdY307ipwODCxNfMGswmSC 6mGIrnnzvWf8E5dH9FuUcnPhHjjTc1TCSrOLLh69hr110xof0Dmi8aJ29KuJay82M1Zg cqmnntNfRVKaLtNfwoNFDaVKWT0jPHIrp5kwsDfDMsnEuKbf+1YzPopevbXgynZIxtZ5 +iIy2Jv6hc0QGKjy2F/7eNpzZej7aL86c2iez6kSkLRPJKwdvlcYRvxpwaKQwLcqu7Sp oU7p+0cx2gyCPIo/QRE0cy3fYjY1+dzgT5LqxauTPjPbeTPG4jf8oQuL6aaOxooEWzTU ozNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=wQ71nJahwuqq+z7DVE0+r1oElsGD+n7N1FiHPA9m6ck=; b=Yzq+PZcPDnFfFuUR+NPnh4lZqx8Ui1TENCrgKQGLoaAS3jmobPtORP/6vX4pggOZPL 16dLQG4qoVDddIZZmffb5HtSEDac+Kn9dH4swiutfTXtVAi6FPwzjUu+EhjwIaHbMdE9 2NYzvkaqtLMYEkG+bizZZOc2Js6wpcROaCm5+UI2H7NhqdwDajSDqVCMTUyoPAoz5mQ6 x0L5RcYsmQ0kmhugpxbKgR8/XeMbaDa2lOWfXjuAZ+N4u0X/zDzi6KnZmm2uUrCwFDLw TNlM4hEb/AszvJSNxkWhqh8XypGPihj/9V4euFvmcuHBpq3AbIJm4AkIfx8M4GfnyjYl +/Ow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vAFIFBzf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:d3db:cca:e5c9:6531]) by smtp.gmail.com with ESMTPSA id y26-20020aa7805a000000b0051876d83714sm7476904pfm.196.2022.06.06.19.47.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 19:47:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 25/25] target/arm: Fix Secure PL1 tests in fp_exception_el Date: Mon, 6 Jun 2022 19:47:34 -0700 Message-Id: <20220607024734.541321-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607024734.541321-1-richard.henderson@linaro.org> References: <20220607024734.541321-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We were using arm_is_secure and is_a64, which are tests against the current EL, as opposed to arm_el_is_aa64 and arm_is_secure_below_el3, which can be applied to a different EL than current. Consolidate the two tests. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 23 +++++++++-------------- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index eeca1a5dc8..1d81a01c94 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13400,27 +13400,22 @@ int fp_exception_el(CPUARMState *env, int cur_el) int fpen = FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, FPEN); switch (fpen) { + case 1: + if (cur_el != 0) { + break; + } + /* fall through */ case 0: case 2: - if (cur_el == 0 || cur_el == 1) { - /* Trap to PL1, which might be EL1 or EL3 */ - if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { - return 3; - } - return 1; - } - if (cur_el == 3 && !is_a64(env)) { - /* Secure PL1 running at EL3 */ + /* Trap from Secure PL0 or PL1 to Secure PL1. */ + if (!arm_el_is_aa64(env, 3) + && (cur_el == 3 || arm_is_secure_below_el3(env))) { return 3; } - break; - case 1: - if (cur_el == 0) { + if (cur_el <= 1) { return 1; } break; - case 3: - break; } }