From patchwork Wed Jun 8 08:35:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 579999 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40933CCA47B for ; Wed, 8 Jun 2022 09:16:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234691AbiFHJQC (ORCPT ); Wed, 8 Jun 2022 05:16:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36906 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235093AbiFHJOa (ORCPT ); Wed, 8 Jun 2022 05:14:30 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8BE871D82F4; Wed, 8 Jun 2022 01:36:10 -0700 (PDT) X-UUID: b566a5b6eae447c9897858eace2fbdea-20220608 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5, REQID:0d5b83aa-2477-46cd-b412-e843e534e382, OB:0, LO B:20,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,AC TION:release,TS:95 X-CID-INFO: VERSION:1.1.5, REQID:0d5b83aa-2477-46cd-b412-e843e534e382, OB:0, LOB: 20,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,AC TION:quarantine,TS:95 X-CID-META: VersionHash:2a19b09, CLOUDID:ac2415e5-2ba2-4dc1-b6c5-11feb6c769e0, C OID:ab9fe7398c47,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:0,BEC:nil X-UUID: b566a5b6eae447c9897858eace2fbdea-20220608 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 788356503; Wed, 08 Jun 2022 16:36:03 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 8 Jun 2022 16:36:02 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 8 Jun 2022 16:36:02 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Matthias Brugger , Lee Jones , Benson Leung , "Guenter Roeck" , Sebastian Reichel , Daisuke Nojiri , Kees Cook , Tinghan Shen , "Gustavo A. R. Silva" , Prashant Malani , Enric Balletbo i Serra CC: , , , , , , , Subject: [PATCH v2 1/9] dt-binding: remoteproc: mediatek: Support dual-core SCP Date: Wed, 8 Jun 2022 16:35:45 +0800 Message-ID: <20220608083553.8697-2-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220608083553.8697-1-tinghan.shen@mediatek.com> References: <20220608083553.8697-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The MT8195 SCP co-processor is a dual-core RISC-V MCU. Add a new property to reference the sibling core and to assign core id to SCP nodes. Also add a new compatile for the driver of SCP 2nd core. Signed-off-by: Tinghan Shen Reviewed-by: Rob Herring --- .../devicetree/bindings/remoteproc/mtk,scp.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml index eec3b9c4c713..4576ff9b1f2d 100644 --- a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml +++ b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml @@ -20,6 +20,7 @@ properties: - mediatek,mt8186-scp - mediatek,mt8192-scp - mediatek,mt8195-scp + - mediatek,mt8195-scp-dual reg: description: @@ -57,6 +58,17 @@ properties: memory-region: maxItems: 1 + mediatek,scp-core: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + description: + Reference to the sibling SCP core. This is required to + enable support for dual-core SCP. + items: + - items: + - description: Phandle of sibling SCP node. + - description: Core id of this SCP node + enum: [0, 1] + required: - compatible - reg @@ -115,6 +127,7 @@ examples: reg-names = "sram", "cfg", "l1tcm"; clocks = <&infracfg CLK_INFRA_SCPSYS>; clock-names = "main"; + mediatek,scp-core = <&scp_dual 0>; cros_ec { mediatek,rpmsg-name = "cros-ec-rpmsg"; From patchwork Wed Jun 8 08:35:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 579997 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B207C433EF for ; Wed, 8 Jun 2022 09:16:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234789AbiFHJQG (ORCPT ); Wed, 8 Jun 2022 05:16:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235262AbiFHJOt (ORCPT ); Wed, 8 Jun 2022 05:14:49 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8D5C01DB1DF; Wed, 8 Jun 2022 01:37:25 -0700 (PDT) X-UUID: a7cb309ee8e24eb09d43e1b2af1509dd-20220608 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5, REQID:1e3e44ea-f46a-4ea5-8e99-c65a970772f7, OB:0, LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,ACT ION:release,TS:95 X-CID-INFO: VERSION:1.1.5, REQID:1e3e44ea-f46a-4ea5-8e99-c65a970772f7, OB:0, LOB: 0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,ACT ION:quarantine,TS:95 X-CID-META: VersionHash:2a19b09, CLOUDID:b03a15e5-2ba2-4dc1-b6c5-11feb6c769e0, C OID:8f91e81df6c9,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:0,BEC:nil X-UUID: a7cb309ee8e24eb09d43e1b2af1509dd-20220608 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 212095045; Wed, 08 Jun 2022 16:37:21 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 8 Jun 2022 16:36:02 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 8 Jun 2022 16:36:02 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Lee Jones , Benson Leung , Guenter Roeck , Sebastian Reichel , Daisuke Nojiri , Kees Cook , Tinghan Shen , "Gustavo A. R. Silva" , Prashant Malani , Enric Balletbo i Serra CC: , , , , , , , Subject: [PATCH v2 2/9] remoteproc: mediatek: Support hanlding scp core 1 wdt timeout Date: Wed, 8 Jun 2022 16:35:46 +0800 Message-ID: <20220608083553.8697-3-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220608083553.8697-1-tinghan.shen@mediatek.com> References: <20220608083553.8697-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org MT8195 SCP is a dual-core processor. The SCP core 1 watchdog timeout interrupt uses the same interrupt line of SCP core 0 watchdog timeout interrupt. Add support for handling SCP core 1 watchdog timeout interrupt in the SCP IRQ handler. Signed-off-by: Tinghan Shen --- drivers/remoteproc/mtk_common.h | 4 ++++ drivers/remoteproc/mtk_scp.c | 27 ++++++++++++++++++++++++++- 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h index ea6fa1100a00..73e8adf00de3 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -54,6 +54,10 @@ #define MT8192_CORE0_WDT_IRQ 0x10030 #define MT8192_CORE0_WDT_CFG 0x10034 +#define MT8195_SYS_STATUS 0x4004 +#define MT8195_CORE0_WDT BIT(16) +#define MT8195_CORE1_WDT BIT(17) + #define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4) #define SCP_FW_VER_LEN 32 diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 47b2a40e1b4a..3510c6d0bbc8 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -212,6 +212,31 @@ static void mt8192_scp_irq_handler(struct mtk_scp *scp) } } +static void mt8195_scp_irq_handler(struct mtk_scp *scp) +{ + u32 scp_to_host; + + scp_to_host = readl(scp->reg_base + MT8192_SCP2APMCU_IPC_SET); + + if (scp_to_host & MT8192_SCP_IPC_INT_BIT) { + scp_ipi_handler(scp); + + /* + * SCP won't send another interrupt until we clear + * MT8192_SCP2APMCU_IPC. + */ + writel(MT8192_SCP_IPC_INT_BIT, + scp->reg_base + MT8192_SCP2APMCU_IPC_CLR); + } else { + if (readl(scp->reg_base + MT8195_SYS_STATUS) & MT8195_CORE1_WDT) { + writel(1, scp->reg_base + MT8195_CORE1_WDT_IRQ); + } else { + writel(1, scp->reg_base + MT8192_CORE0_WDT_IRQ); + scp_wdt_handler(scp, scp_to_host); + } + } +} + static irqreturn_t scp_irq_handler(int irq, void *priv) { struct mtk_scp *scp = priv; @@ -961,7 +986,7 @@ static const struct mtk_scp_of_data mt8192_of_data = { static const struct mtk_scp_of_data mt8195_of_data = { .scp_clk_get = mt8195_scp_clk_get, .scp_before_load = mt8195_scp_before_load, - .scp_irq_handler = mt8192_scp_irq_handler, + .scp_irq_handler = mt8195_scp_irq_handler, .scp_reset_assert = mt8192_scp_reset_assert, .scp_reset_deassert = mt8192_scp_reset_deassert, .scp_stop = mt8195_scp_stop, From patchwork Wed Jun 8 08:35:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 579996 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD068C433EF for ; Wed, 8 Jun 2022 09:16:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234804AbiFHJQL (ORCPT ); Wed, 8 Jun 2022 05:16:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235108AbiFHJOb (ORCPT ); Wed, 8 Jun 2022 05:14:31 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4164B1285C9; Wed, 8 Jun 2022 01:36:12 -0700 (PDT) X-UUID: c835ab158e284bddb1877ac900538f02-20220608 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5, REQID:f3055498-72a6-4c8e-b6f1-c622fac0ef7e, OB:20, L OB:10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:95 X-CID-INFO: VERSION:1.1.5, REQID:f3055498-72a6-4c8e-b6f1-c622fac0ef7e, OB:20, LOB :10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:95 X-CID-META: VersionHash:2a19b09, CLOUDID:577d9f7e-c8dc-403a-96e8-6237210dceee, C OID:ab9fe7398c47,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:0,BEC:nil X-UUID: c835ab158e284bddb1877ac900538f02-20220608 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 18680939; Wed, 08 Jun 2022 16:36:04 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 8 Jun 2022 16:36:02 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 8 Jun 2022 16:36:02 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Matthias Brugger , Lee Jones , Benson Leung , "Guenter Roeck" , Sebastian Reichel , Daisuke Nojiri , Kees Cook , Tinghan Shen , "Gustavo A. R. Silva" , Prashant Malani , Enric Balletbo i Serra CC: , , , , , , , Subject: [PATCH v2 5/9] remoteproc: mediatek: Add chip dependent operations for SCP core 1 Date: Wed, 8 Jun 2022 16:35:49 +0800 Message-ID: <20220608083553.8697-6-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220608083553.8697-1-tinghan.shen@mediatek.com> References: <20220608083553.8697-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SCP rproc operations has chip dependent callbacks. Implement a version of these callbacks for MT8195 SCP core 1. Signed-off-by: Tinghan Shen --- drivers/remoteproc/mtk_scp.c | 65 ++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 91b4aefde4ac..731a8094c373 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -180,6 +180,16 @@ static void mt8192_scp_reset_deassert(struct mtk_scp *scp) writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_CLR); } +static void mt8195_scp_dual_reset_assert(struct mtk_scp *scp) +{ + writel(1, scp->reg_base + MT8195_CORE1_SW_RSTN_SET); +} + +static void mt8195_scp_dual_reset_deassert(struct mtk_scp *scp) +{ + writel(1, scp->reg_base + MT8195_CORE1_SW_RSTN_CLR); +} + static void mt8183_scp_irq_handler(struct mtk_scp *scp) { u32 scp_to_host; @@ -241,6 +251,24 @@ static void mt8195_scp_irq_handler(struct mtk_scp *scp) } } +static void mt8195_scp_dual_irq_handler(struct mtk_scp *scp) +{ + u32 scp_to_host; + + scp_to_host = readl(scp->reg_base + MT8195_SSHUB2APMCU_IPC_SET); + + if (scp_to_host & MT8192_SCP_IPC_INT_BIT) { + scp_ipi_handler(scp); + + /* + * SCP won't send another interrupt until we clear + * MT8195_SSHUB2APMCU_IPC_CLR. + */ + writel(MT8192_SCP_IPC_INT_BIT, + scp->reg_base + MT8195_SSHUB2APMCU_IPC_CLR); + } +} + static irqreturn_t scp_irq_handler(int irq, void *priv) { struct mtk_scp *scp = priv; @@ -474,6 +502,21 @@ static int mt8195_scp_before_load(struct mtk_scp *scp) return 0; } +static int mt8195_scp_dual_before_load(struct mtk_scp *scp) +{ + u32 sec_ctrl; + + scp_sram_power_on(scp->reg_base + MT8195_CPU1_SRAM_PD, 0); + + /* hold SCP in reset while loading FW. */ + scp->data->scp_reset_assert(scp); + + /* enable MPU for all memory regions */ + writel(0xff, scp->reg_base + MT8195_CORE1_MEM_ATT_PREDEF); + + return 0; +} + static int scp_load(struct rproc *rproc, const struct firmware *fw) { struct mtk_scp *scp = rproc->priv; @@ -646,6 +689,15 @@ static void mt8195_scp_stop(struct mtk_scp *scp) writel(0, scp->reg_base + MT8192_CORE0_WDT_CFG); } +static void mt8195_scp_dual_stop(struct mtk_scp *scp) +{ + /* Power off CPU SRAM */ + scp_sram_power_off(scp->reg_base + MT8195_CPU1_SRAM_PD, 0); + + /* Disable SCP watchdog */ + writel(0, scp->reg_base + MT8195_CORE1_WDT_CFG); +} + static int scp_stop(struct rproc *rproc) { struct mtk_scp *scp = (struct mtk_scp *)rproc->priv; @@ -1013,11 +1065,24 @@ static const struct mtk_scp_of_data mt8195_of_data = { .host_to_scp_int_bit = MT8192_HOST_IPC_INT_BIT, }; +static const struct mtk_scp_of_data mt8195_scp_dual_of_data = { + .scp_clk_get = mt8195_scp_clk_get, + .scp_before_load = mt8195_scp_dual_before_load, + .scp_irq_handler = mt8195_scp_dual_irq_handler, + .scp_reset_assert = mt8195_scp_dual_reset_assert, + .scp_reset_deassert = mt8195_scp_dual_reset_deassert, + .scp_stop = mt8195_scp_dual_stop, + .scp_da_to_va = mt8192_scp_da_to_va, + .host_to_scp_reg = MT8192_GIPC_IN_SET, + .host_to_scp_int_bit = MT8195_CORE1_HOST_IPC_INT_BIT, +}; + static const struct of_device_id mtk_scp_of_match[] = { { .compatible = "mediatek,mt8183-scp", .data = &mt8183_of_data }, { .compatible = "mediatek,mt8186-scp", .data = &mt8186_of_data }, { .compatible = "mediatek,mt8192-scp", .data = &mt8192_of_data }, { .compatible = "mediatek,mt8195-scp", .data = &mt8195_of_data }, + { .compatible = "mediatek,mt8195-scp-dual", .data = &mt8195_scp_dual_of_data }, {}, }; MODULE_DEVICE_TABLE(of, mtk_scp_of_match); From patchwork Wed Jun 8 08:35:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 580005 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54DFAC433EF for ; Wed, 8 Jun 2022 09:15:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229671AbiFHJPm (ORCPT ); Wed, 8 Jun 2022 05:15:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58980 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235090AbiFHJOa (ORCPT ); Wed, 8 Jun 2022 05:14:30 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 566EF1D81A8; Wed, 8 Jun 2022 01:36:10 -0700 (PDT) X-UUID: d6de6976b3ba4611902d7eb46160c50d-20220608 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5, REQID:fdf95160-d3b8-466b-9dce-cb9891f2b2ea, OB:30, L OB:10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:95 X-CID-INFO: VERSION:1.1.5, REQID:fdf95160-d3b8-466b-9dce-cb9891f2b2ea, OB:30, LOB :10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:95 X-CID-META: VersionHash:2a19b09, CLOUDID:3f2515e5-2ba2-4dc1-b6c5-11feb6c769e0, C OID:ab9fe7398c47,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:0,BEC:nil X-UUID: d6de6976b3ba4611902d7eb46160c50d-20220608 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1726167700; Wed, 08 Jun 2022 16:36:04 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 8 Jun 2022 16:36:02 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 8 Jun 2022 16:36:02 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Matthias Brugger , Lee Jones , Benson Leung , "Guenter Roeck" , Sebastian Reichel , Daisuke Nojiri , Kees Cook , Tinghan Shen , "Gustavo A. R. Silva" , Prashant Malani , Enric Balletbo i Serra CC: , , , , , , , Subject: [PATCH v2 6/9] remoteproc: mediatek: Add SCP core 1 SRAM offset Date: Wed, 8 Jun 2022 16:35:50 +0800 Message-ID: <20220608083553.8697-7-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220608083553.8697-1-tinghan.shen@mediatek.com> References: <20220608083553.8697-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Because SCP core 0 and core 1 both boot from address 0 and have the same viewpoint of memory, HW has a set of registers, "SRAM offset", to add offset to accessed address for SCP core 1 to solve this problem. The "SRAM offset" configuration is composed by specifying a range and an offset. The value of range is from the viewpoint of SCP core 1. When SCP core 1 accessing addresses in the configured range, SCP bus adds an offset to shift the destination on SCP SRAM. This shift is transparent to the software running on SCP core 1. Signed-off-by: Tinghan Shen --- drivers/remoteproc/mtk_scp.c | 42 ++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 731a8094c373..b8a4db581179 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -505,6 +505,27 @@ static int mt8195_scp_before_load(struct mtk_scp *scp) static int mt8195_scp_dual_before_load(struct mtk_scp *scp) { u32 sec_ctrl; + struct device *dev = scp->dev; + struct device_node *main_np; + struct platform_device *main_pdev; + struct mtk_scp *scp_core0; + + /* Get sram start address from SCP core 0 */ + main_np = of_parse_phandle(dev->of_node, "mediatek,scp-core", 0); + if (!main_np) { + dev_warn(dev, "Invalid SCP main core phandle\n"); + return -EINVAL; + } + + main_pdev = of_find_device_by_node(main_np); + of_node_put(main_np); + + if (!main_pdev) { + dev_err(dev, "Cannot find SCP core 0 device\n"); + return -ENODEV; + } + scp_core0 = platform_get_drvdata(main_pdev); + put_device(&main_pdev->dev); scp_sram_power_on(scp->reg_base + MT8195_CPU1_SRAM_PD, 0); @@ -514,6 +535,27 @@ static int mt8195_scp_dual_before_load(struct mtk_scp *scp) /* enable MPU for all memory regions */ writel(0xff, scp->reg_base + MT8195_CORE1_MEM_ATT_PREDEF); + /* The value of SRAM offset range is from the viewpoint of SCP core 1. + * This configuration adds an offset on SCP bus when SCP core 1 accesses SCP SRAM + * to solve the SCP core 0 and core 1 both fetch the 1st instruction from the same + * SRAM address. + * + * Because SCP core 0 and core 1 both boot from address 0, this must be configured + * before boot SCP core 1. + * + * Configure the range of SRAM addresses will be added offset. + */ + writel(0, scp->reg_base + MT8195_L2TCM_OFFSET_RANGE_0_LOW); + writel(scp->sram_size, scp->reg_base + MT8195_L2TCM_OFFSET_RANGE_0_HIGH); + + /* configure the offset value */ + writel(scp->sram_phys - scp_core0->sram_phys, scp->reg_base + MT8195_L2TCM_OFFSET); + + /* enable adding sram offset when fetching instruction and data */ + sec_ctrl = readl(scp->reg_base + MT8195_SEC_CTRL); + sec_ctrl |= MT8195_CORE_OFFSET_ENABLE_I | MT8195_CORE_OFFSET_ENABLE_D; + writel(sec_ctrl, scp->reg_base + MT8195_SEC_CTRL); + return 0; } From patchwork Wed Jun 8 08:35:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 580004 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFE43C433EF for ; Wed, 8 Jun 2022 09:15:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233604AbiFHJPo (ORCPT ); Wed, 8 Jun 2022 05:15:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55812 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235263AbiFHJOt (ORCPT ); Wed, 8 Jun 2022 05:14:49 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9729B1DAE5D; Wed, 8 Jun 2022 01:37:26 -0700 (PDT) X-UUID: f5c1e9e9b2634d548c8b7d0de3b55509-20220608 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5, REQID:1a601765-eea6-4ef0-9d17-adc775769923, OB:10, L OB:10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:95 X-CID-INFO: VERSION:1.1.5, REQID:1a601765-eea6-4ef0-9d17-adc775769923, OB:10, LOB :10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:95 X-CID-META: VersionHash:2a19b09, CLOUDID:b73a15e5-2ba2-4dc1-b6c5-11feb6c769e0, C OID:8f91e81df6c9,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:0,BEC:nil X-UUID: f5c1e9e9b2634d548c8b7d0de3b55509-20220608 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 265310191; Wed, 08 Jun 2022 16:37:21 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 8 Jun 2022 16:36:02 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 8 Jun 2022 16:36:02 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Lee Jones , Benson Leung , Guenter Roeck , Sebastian Reichel , Daisuke Nojiri , Kees Cook , Tinghan Shen , "Gustavo A. R. Silva" , Prashant Malani , Enric Balletbo i Serra CC: , , , , , , , Subject: [PATCH v2 7/9] remoteproc: mediatek: Add SCP core 1 as a rproc subdevice Date: Wed, 8 Jun 2022 16:35:51 +0800 Message-ID: <20220608083553.8697-8-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220608083553.8697-1-tinghan.shen@mediatek.com> References: <20220608083553.8697-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Because the clock and SRAM power is controlled by SCP core 0, SCP core 1 has to be boot after SCP core 0. We use the rproc subdev to achieve this purpose. The watchdog timeout handler of SCP core 1 is added as part of the rproc subdevice. This allows SCP core 0 to handle watchdog timeout coming from SCP core 1. Signed-off-by: Tinghan Shen --- drivers/remoteproc/mtk_common.h | 9 +++ drivers/remoteproc/mtk_scp.c | 130 ++++++++++++++++++++++++++++++++ 2 files changed, 139 insertions(+) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h index 5582f4207fbf..67b41866a100 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -99,6 +99,14 @@ struct scp_ipi_desc { void *priv; }; +struct scp_subdev_core { + struct rproc_subdev subdev; + struct mtk_scp *main_scp; + void (*scp_dual_wdt_timeout)(struct mtk_scp *scp, u32 scp_to_host); +}; + +#define to_subdev_core(d) container_of(d, struct scp_subdev_core, subdev) + struct mtk_scp; struct mtk_scp_of_data { @@ -144,6 +152,7 @@ struct mtk_scp { size_t dram_size; struct rproc_subdev *rpmsg_subdev; + struct rproc_subdev *dual_subdev; }; /** diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index b8a4db581179..d0e9e19e251f 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -244,6 +244,13 @@ static void mt8195_scp_irq_handler(struct mtk_scp *scp) } else { if (readl(scp->reg_base + MT8195_SYS_STATUS) & MT8195_CORE1_WDT) { writel(1, scp->reg_base + MT8195_CORE1_WDT_IRQ); + + if (scp->dual_subdev) { + struct scp_subdev_core *subdev_core; + + subdev_core = to_subdev_core(scp->dual_subdev); + subdev_core->scp_dual_wdt_timeout(scp, scp_to_host); + } } else { writel(1, scp->reg_base + MT8192_CORE0_WDT_IRQ); scp_wdt_handler(scp, scp_to_host); @@ -925,6 +932,118 @@ static void scp_remove_rpmsg_subdev(struct mtk_scp *scp) } } +static struct mtk_scp *scp_dual_get(struct mtk_scp *scp) +{ + struct device *dev = scp->dev; + struct device_node *np; + struct platform_device *dual_pdev; + + np = of_parse_phandle(dev->of_node, "mediatek,scp-core", 0); + dual_pdev = of_find_device_by_node(np); + of_node_put(np); + + if (!dual_pdev) { + dev_err(dev, "No scp-dual pdev\n"); + return NULL; + } + + return platform_get_drvdata(dual_pdev); +} + +static void scp_dual_put(struct mtk_scp *scp) +{ + put_device(scp->dev); +} + +static int scp_dual_rproc_start(struct rproc_subdev *subdev) +{ + struct scp_subdev_core *subdev_core = to_subdev_core(subdev); + struct mtk_scp *scp_dual; + + scp_dual = scp_dual_get(subdev_core->main_scp); + if (!scp_dual) + return -ENODEV; + + rproc_boot(scp_dual->rproc); + scp_dual_put(scp_dual); + + return 0; +} + +static void scp_dual_rproc_stop(struct rproc_subdev *subdev, bool crashed) +{ + struct scp_subdev_core *subdev_core = to_subdev_core(subdev); + struct mtk_scp *scp_dual; + + scp_dual = scp_dual_get(subdev_core->main_scp); + if (!scp_dual) + return; + + rproc_shutdown(scp_dual->rproc); + scp_dual_put(scp_dual); +} + +static void scp_dual_wdt_handler(struct mtk_scp *scp, u32 scp_to_host) +{ + struct mtk_scp *scp_dual; + + scp_dual = scp_dual_get(scp); + if (!scp_dual) + return; + + dev_err(scp_dual->dev, "SCP watchdog timeout! 0x%x\n", scp_to_host); + rproc_report_crash(scp_dual->rproc, RPROC_WATCHDOG); + scp_dual_put(scp_dual); +} + +static struct rproc_subdev *scp_dual_create_subdev(struct mtk_scp *scp) +{ + struct device *dev = scp->dev; + struct scp_subdev_core *subdev_core; + struct device_node *np; + + np = of_parse_phandle(dev->of_node, "mediatek,scp-core", 0); + if (!np) + return NULL; + + of_node_put(np); + + subdev_core = devm_kzalloc(dev, sizeof(*subdev_core), GFP_KERNEL); + if (!subdev_core) + return NULL; + + subdev_core->main_scp = scp; + subdev_core->scp_dual_wdt_timeout = scp_dual_wdt_handler; + subdev_core->subdev.start = scp_dual_rproc_start; + subdev_core->subdev.stop = scp_dual_rproc_stop; + + return &subdev_core->subdev; +} + +static void scp_dual_destroy_subdev(struct rproc_subdev *subdev) +{ + struct scp_subdev_core *subdev_core = to_subdev_core(subdev); + + devm_kfree(subdev_core->main_scp->dev, subdev_core); +} + +static void scp_add_dual_subdev(struct mtk_scp *scp) +{ + scp->dual_subdev = scp_dual_create_subdev(scp); + + if (scp->dual_subdev) + rproc_add_subdev(scp->rproc, scp->dual_subdev); +} + +static void scp_remove_dual_subdev(struct mtk_scp *scp) +{ + if (scp->dual_subdev) { + rproc_remove_subdev(scp->rproc, scp->dual_subdev); + scp_dual_destroy_subdev(scp->dual_subdev); + scp->dual_subdev = NULL; + } +} + static int scp_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1014,6 +1133,9 @@ static int scp_probe(struct platform_device *pdev) scp_add_rpmsg_subdev(scp); + if (core_id == SCP_CORE_0) + scp_add_dual_subdev(scp); + ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0), NULL, scp_irq_handler, IRQF_ONESHOT, pdev->name, scp); @@ -1023,6 +1145,12 @@ static int scp_probe(struct platform_device *pdev) goto remove_subdev; } + /* disable auto boot before register rproc. + * scp core 1 is booted as a subdevice of scp core 0. + */ + if (core_id == SCP_CORE_1) + rproc->auto_boot = false; + ret = rproc_add(rproc); if (ret) goto remove_subdev; @@ -1030,6 +1158,7 @@ static int scp_probe(struct platform_device *pdev) return 0; remove_subdev: + scp_remove_dual_subdev(scp); scp_remove_rpmsg_subdev(scp); scp_ipi_unregister(scp, SCP_IPI_INIT); release_dev_mem: @@ -1047,6 +1176,7 @@ static int scp_remove(struct platform_device *pdev) int i; rproc_del(scp->rproc); + scp_remove_dual_subdev(scp); scp_remove_rpmsg_subdev(scp); scp_ipi_unregister(scp, SCP_IPI_INIT); scp_unmap_memory_region(scp);