From patchwork Sat Jun 18 21:39:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 582793 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88B33CCA483 for ; Sat, 18 Jun 2022 21:40:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232940AbiFRVkB (ORCPT ); Sat, 18 Jun 2022 17:40:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230078AbiFRVkA (ORCPT ); Sat, 18 Jun 2022 17:40:00 -0400 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 660EAEE04; Sat, 18 Jun 2022 14:39:59 -0700 (PDT) Received: by mail-ed1-x52e.google.com with SMTP id o10so10359641edi.1; Sat, 18 Jun 2022 14:39:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UTY/s32m0Wtb8ceiKoFbYE3NzsS87wWfGqUvXHlMqlU=; b=glDzJ1XuBItb+SjA7RGVPzxgTYN4TWodLSVBNGz4fwxTefjyMMS0MnuR06XKXwzeHW ijgyo0VoQlGz3n3L4jhMK+sltwllUw9VWhqIZ4iNHlfLvcTjnKavakKfLPVWYZzb4TMY BBfcG5rV/0b9PjnnIPEOzzLbBPv6whwY3Y57i56y3wZV+eLyWouGUEEhDDz1bUcNYEeV 95L+28bWYqftxEKE4Yi12yfE3Hs3StfwuXmSP+seyo8Qcql+fkWIZMlUkGLklYg1NGOQ 9n2rKvStm+TZmFT0nzzzhG70EXzDglYbKEVMuAXlGXDdy1o5EoIXq0ZWSeJOaBgiVHOn RlQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UTY/s32m0Wtb8ceiKoFbYE3NzsS87wWfGqUvXHlMqlU=; b=dKyFMObDwIiabeZ7v+AiOa/heWtw0XUK+RwbbgD3TNHRP/1UD8+XA+8CKtuU97kN+1 9fYZUYnPIY95bQ2Jsh26cYsKDVwzrJLJa5EsA199R+i7HnThASkxCe7QG+C8NYRiRPO/ BS1/cywd2zO3b8nnIs9P7tICdUbyry9pjXUM/MSY5Vfxc/7/1NK635GOFpbVNVDzqxlV GrpX7TXgsCTIsTVVB4oRz1TF2tFAgWNhNM5JvrsotVAOoKdRBT0v9jyfgIFiUcZv85Ud BSJdrcsYjf6l/sIcUNztUEeE5RJS7Nf4JBC/vZXo0ZzZqsOUxn1Yv13uEmfCFky68Jau K5Tg== X-Gm-Message-State: AJIora8twa0bnt8ybOtqhOO+7mBL284tNFZj25IaffENXjgtDFokk6Q7 1wkqMFXGgI4sJbSv1xNQliM= X-Google-Smtp-Source: AGRyM1uIncf3FCatoVZbEOcZy057dosvVm1M+HIBG4nrUYcL0Q/BuqU45yNz80UbSPowQ+m5JKQClw== X-Received: by 2002:a05:6402:2399:b0:42e:1400:818b with SMTP id j25-20020a056402239900b0042e1400818bmr20741818eda.159.1655588398061; Sat, 18 Jun 2022 14:39:58 -0700 (PDT) Received: from localhost (92.40.169.177.threembb.co.uk. [92.40.169.177]) by smtp.gmail.com with ESMTPSA id c6-20020a170906170600b00706242d297fsm3738302eje.212.2022.06.18.14.39.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jun 2022 14:39:57 -0700 (PDT) From: Aidan MacDonald To: linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, wens@csie.org, jic23@kernel.org, lee.jones@linaro.org, sre@kernel.org, broonie@kernel.org, gregkh@linuxfoundation.org, lgirdwood@gmail.com Cc: lars@metafoo.de, rafael@kernel.org, quic_gurus@quicinc.com, sebastian.reichel@collabora.com, andy.shevchenko@gmail.com, michael@walle.cc, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v3 01/16] regmap-irq: Use sub_irq_reg() to calculate unmask register address Date: Sat, 18 Jun 2022 22:39:54 +0100 Message-Id: <20220618214009.2178567-2-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220618214009.2178567-1-aidanmacdonald.0x0@gmail.com> References: <20220618214009.2178567-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Call sub_irq_reg() instead of calculating the offset of the register to avoid relying on the fact that sub_irq_reg() is a linear function of "base_reg" and "i". Unmask registers were the only type that didn't use sub_irq_reg() for address calculation; thus, sub_irq_reg() is now the only method used to obtain register addresses. This prepares for allowing drivers to override the default sub_irq_reg implementation if the default behavior is unsuitable. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index 400c7412a7dc..4a2e1f6aa94d 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -97,7 +97,6 @@ static void regmap_irq_sync_unlock(struct irq_data *data) struct regmap *map = d->map; int i, j, ret; u32 reg; - u32 unmask_offset; u32 val; if (d->chip->runtime_pm) { @@ -141,11 +140,11 @@ static void regmap_irq_sync_unlock(struct irq_data *data) dev_err(d->map->dev, "Failed to sync unmasks in %x\n", reg); - unmask_offset = d->chip->unmask_base - - d->chip->mask_base; + /* clear mask with unmask_base register */ + reg = sub_irq_reg(d, d->chip->unmask_base, i); ret = regmap_irq_update_bits(d, - reg + unmask_offset, + reg, d->mask_buf_def[i], d->mask_buf[i]); } else { @@ -632,7 +631,6 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, int ret = -ENOMEM; int num_type_reg; u32 reg; - u32 unmask_offset; if (chip->num_regs <= 0) return -EINVAL; @@ -773,10 +771,9 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, ret = regmap_irq_update_bits(d, reg, d->mask_buf[i], ~d->mask_buf[i]); else if (d->chip->unmask_base) { - unmask_offset = d->chip->unmask_base - - d->chip->mask_base; + reg = sub_irq_reg(d, d->chip->unmask_base, i); ret = regmap_irq_update_bits(d, - reg + unmask_offset, + reg, d->mask_buf[i], d->mask_buf[i]); } else From patchwork Sat Jun 18 21:39:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 582792 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0977CCA480 for ; Sat, 18 Jun 2022 21:40:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234721AbiFRVkP (ORCPT ); Sat, 18 Jun 2022 17:40:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43492 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233671AbiFRVkE (ORCPT ); Sat, 18 Jun 2022 17:40:04 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6A3DBB7D6; Sat, 18 Jun 2022 14:40:02 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id y19so14586514ejq.6; Sat, 18 Jun 2022 14:40:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SsvIUi5Mx2lkt+N5FiHvaXdtimrUSlx4XN7ieZ+PNqI=; b=Xn6SQ7YDy255jmHCT0Ra/4r1e/4aekKOjNILyMBbGUk603Cz3ZizrIsC/W9WeRI0cr BETFFGOVQxLjQTdRyP3MTBnySOBa9s0I19psP0NRv5lGeCvJ3iDm7+ilVikWJkmxsEtw eNezxWDw5yUAx6ljIAClJJIvrfoS38iR+B8fzOiU658vHfaBfp59BpOtXF7Q3d4p7iCv w92FebCLEjMssuc/uMVhXPN8Mz4vxLMSqjWgFqK8sZyWBnWS4v4aW/OIvf92qCC5bq9F 1gn1PLAtZsBD/Cqf8yZZ1nhgatLcXz6VA9d+GIfSN0XsJcfo6PEo7gflyAbdy0UgHrqh ysFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SsvIUi5Mx2lkt+N5FiHvaXdtimrUSlx4XN7ieZ+PNqI=; b=Aj8xXHkwyhVtwc6Ug28mqvnP86KlxqDSbawpZqb1wYoZWEdDBdFZxodvlegKfFjIxR XQL0cuyQvdTuBt5ehYB33qiKwohZXrEilE7x/ckTMO/RukDyF8gYvcdgl8+UQQ6Sd9VL 129hiF5nQPlYykCKZX2SLoAb8+QXPXE/1pwidy+EX9Fhr7Glwu59TA0BMGbyq4TCB3fl K2SsiKv3E5EpNte7nNaSYJi54Bij2WFzLZyDuzPZS1Hj3HUiwfw5QJXOD/ZRIw3R4CbX D3akM5VY1fearF+lpSTNXyhPEi9+DhRZ34aLKYhgnEOJ2DUSIxzu2CF8NJvKcFVTFEQp 83cA== X-Gm-Message-State: AJIora/wuSlPoBDjab3VuNqk83OvMr4oBwe8ZT2u/8xW8vXgQ/HA1TT1 YgFVlyqM8ZUj+2OnZmyJ31w= X-Google-Smtp-Source: AGRyM1vmc/SfZVszFum5RYiz7S8VKAtbdVhVZyu8vXNCkghou0XQh1EPjszy7/HU5TQ5sg/8RjKZqA== X-Received: by 2002:a17:907:d05:b0:6f4:3729:8e36 with SMTP id gn5-20020a1709070d0500b006f437298e36mr14309985ejc.475.1655588401047; Sat, 18 Jun 2022 14:40:01 -0700 (PDT) Received: from localhost (92.40.169.177.threembb.co.uk. [92.40.169.177]) by smtp.gmail.com with ESMTPSA id ff10-20020a1709069c0a00b006fec69696a0sm3784240ejc.220.2022.06.18.14.40.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jun 2022 14:40:00 -0700 (PDT) From: Aidan MacDonald To: linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, wens@csie.org, jic23@kernel.org, lee.jones@linaro.org, sre@kernel.org, broonie@kernel.org, gregkh@linuxfoundation.org, lgirdwood@gmail.com Cc: lars@metafoo.de, rafael@kernel.org, quic_gurus@quicinc.com, sebastian.reichel@collabora.com, andy.shevchenko@gmail.com, michael@walle.cc, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-pm@vger.kernel.org, Rob Herring Subject: [PATCH v3 03/16] dt-bindings: mfd: add bindings for AXP192 MFD device Date: Sat, 18 Jun 2022 22:39:56 +0100 Message-Id: <20220618214009.2178567-4-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220618214009.2178567-1-aidanmacdonald.0x0@gmail.com> References: <20220618214009.2178567-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The AXP192 is another X-Powers PMIC similar to the existing ones. Acked-by: Rob Herring Signed-off-by: Aidan MacDonald --- Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml b/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml index 3a53bae611bc..33c9b1b3cc04 100644 --- a/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml +++ b/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml @@ -84,6 +84,7 @@ properties: oneOf: - enum: - x-powers,axp152 + - x-powers,axp192 - x-powers,axp202 - x-powers,axp209 - x-powers,axp221 From patchwork Sat Jun 18 21:39:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 582791 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C99C1CCA483 for ; Sat, 18 Jun 2022 21:40:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235349AbiFRVkS (ORCPT ); Sat, 18 Jun 2022 17:40:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43770 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234130AbiFRVkO (ORCPT ); Sat, 18 Jun 2022 17:40:14 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F34FEEE10; Sat, 18 Jun 2022 14:40:05 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id me5so14614983ejb.2; Sat, 18 Jun 2022 14:40:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0YNmYIukGGfykI+FtYFbZdPS5Nw7Xun3tGXTmtw+hKk=; b=LmuSRxF3BkGn/vNWWXv5fOudLr4rbnKQ1yhSNm9kXRoOGC9Y/cnJYwfy47qRGwKUi6 uZhUHgh3XWLEVIkaP6kdOHpA3cGszo+nYvRuSgOFXIf3XcQhhmryS9F0+OYz0DhGPFIC Z5B4Iulrlt67ID8WM5DrP7kOFOivk7YFfAoUcYTul+9SsgSEL3CJGhwSJj/QmfujXypX EKD2Oi3q9A0FkjJi5bf18nw3FuL2RhD5Iby4uzcbmJtanHo5lmdbERe6S9jDmVH+AVOJ Zro9HgnNr1yMCIdsBAqSoqMwtqAQzs0UHjClBCkZd6Nfwp6IHjqEaxg9p1WSbMBfQFpS OE9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0YNmYIukGGfykI+FtYFbZdPS5Nw7Xun3tGXTmtw+hKk=; b=3g5a55/vpHHFqty4VY0EGchCJVIRYEatYrWjQxz/Jo2coK8nI0N2Jc1/86Iec5o0s4 3sAzL3S7JLY2SHqwPFJzcYA9XTaz0yxn0/aBzg0QYSz6ZBStCV4DiLvqRA+ZbdbmjM29 13ObzhHgMq0YiM1wWj1shGy2lxInUmGsb2enf8HxuicABdeSRp16cmBwtOPJk8iAsCVa TlTTvB0c3Qzzp3nfR8u6q9V1mSqjdWnGQtyt/xWw68Ow5hbKV1KStVzQIQ3NeCDgfxjG z6aK8usV0lyYiq51lhN171UpKuksFl01hgyhSdrPbp4+ptQXyQ8ZQKVvcCBbynDucLmE Grtw== X-Gm-Message-State: AJIora+OWAQkF1gr5/JTguyLU6KtsbwsdcLaccQd2kXnMOAJvrLtDXD5 qvWxwACKq504c99G3JqiiCY= X-Google-Smtp-Source: AGRyM1sKUnzY6BfzCuQwM6IhZ2fXFb0cfw9f33VUewZUTPkwkjDirQDnd2IyYoOSM7Vte+xEFk+Faw== X-Received: by 2002:a17:907:7d8e:b0:711:cf4b:9c5 with SMTP id oz14-20020a1709077d8e00b00711cf4b09c5mr14621433ejc.637.1655588404011; Sat, 18 Jun 2022 14:40:04 -0700 (PDT) Received: from localhost (92.40.169.177.threembb.co.uk. [92.40.169.177]) by smtp.gmail.com with ESMTPSA id bx25-20020a170906a1d900b006fe8d8c54a7sm3827586ejb.87.2022.06.18.14.40.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jun 2022 14:40:03 -0700 (PDT) From: Aidan MacDonald To: linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, wens@csie.org, jic23@kernel.org, lee.jones@linaro.org, sre@kernel.org, broonie@kernel.org, gregkh@linuxfoundation.org, lgirdwood@gmail.com Cc: lars@metafoo.de, rafael@kernel.org, quic_gurus@quicinc.com, sebastian.reichel@collabora.com, andy.shevchenko@gmail.com, michael@walle.cc, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-pm@vger.kernel.org, Rob Herring Subject: [PATCH v3 05/16] dt-bindings: power: supply: axp20x: Add AXP192 compatible Date: Sat, 18 Jun 2022 22:39:58 +0100 Message-Id: <20220618214009.2178567-6-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220618214009.2178567-1-aidanmacdonald.0x0@gmail.com> References: <20220618214009.2178567-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The AXP192's USB power supply is similar to the AXP202 but it has different USB current limits. Acked-by: Rob Herring Signed-off-by: Aidan MacDonald --- .../bindings/power/supply/x-powers,axp20x-usb-power-supply.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/power/supply/x-powers,axp20x-usb-power-supply.yaml b/Documentation/devicetree/bindings/power/supply/x-powers,axp20x-usb-power-supply.yaml index 0c371b55c9e1..e800b3b97f0d 100644 --- a/Documentation/devicetree/bindings/power/supply/x-powers,axp20x-usb-power-supply.yaml +++ b/Documentation/devicetree/bindings/power/supply/x-powers,axp20x-usb-power-supply.yaml @@ -22,6 +22,7 @@ properties: compatible: oneOf: - enum: + - x-powers,axp192-usb-power-supply - x-powers,axp202-usb-power-supply - x-powers,axp221-usb-power-supply - x-powers,axp223-usb-power-supply From patchwork Sat Jun 18 21:40:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 582790 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4567C43334 for ; Sat, 18 Jun 2022 21:40:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235341AbiFRVk1 (ORCPT ); Sat, 18 Jun 2022 17:40:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43840 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234771AbiFRVkQ (ORCPT ); Sat, 18 Jun 2022 17:40:16 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 098A0FD05; Sat, 18 Jun 2022 14:40:08 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id y19so14586514ejq.6; Sat, 18 Jun 2022 14:40:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OgpC4kpL1jnVa3FqPHc/m0xfqS7Yw2ROKq8YORXq2o0=; b=pn4kIYl/RrsGpMpENloZJlrkUsTUnf2xjvs7o0Q6aQJ/yPYrpmyTnriY6wwkB5hm1A lJUBE7QoEdgEURbPwlWApUe9EIL0jn+SBXFceWjn3tMDuJSRaeba0MBHbfHyUO+i4VXO PCX3DLy0bDk6q6yW7OAeRxvnrEE5qMEcY6gwAIL1IADmHGgftpGzTHbWpYcLD2hdlrjp epiGZAJAFaFLOXdoRZWdznyaujtmSYWf6t/D0OiIUTjakCfveDdcozWotY5u8a2rhRwN LR56NQnOUIju3GtihsXSH4fFr/D0861QLxJDIK/AQ9uiOx9q+Mxvv4toV2eGAqLDsyum LPTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OgpC4kpL1jnVa3FqPHc/m0xfqS7Yw2ROKq8YORXq2o0=; b=QaXFVNQ9/6FSy+A+P6RujFDcM0e8YCEUtSbW3z31yUmokvY+FYVtGohe8rD/XR7r+H e9hV/s+aTKGi1NQ3tjxHHgFr3p92cYAnbvjzCa8zLp8bkQmjEbu7nxPUh5J0PiwCBdsM Uz5BzxBhY5qbk+QW9v222aTjGvXZQJRF5O5xr5HlCoepoGj56erFOB0QZrHykSgUcjG9 dEcbGeiHqRZWnlkn1/6cO39D6cA8Z7qWBIkfzSJS8oop/OGMycREUR1RkX3ONo060BSB oiE+nCw9vy3yBOeQpFmyKWw+ncWiuiOeqcWau+rmXNp2UINVFeKyklqZs+2dROqNYXno qgww== X-Gm-Message-State: AJIora9nBpQvhpVqtbDZkCgB9K3c2670OwgbImIqqbsjClul5S/yk7J3 IFIZyw/XF1QVoXGcBf5QzRQ= X-Google-Smtp-Source: AGRyM1viPs8J1txtWH4Q+WHIJWACKsMY5zuq2XR6ANNdVbATRMlFDt6O4rFzkYNTnxOpVuzuD2kLUQ== X-Received: by 2002:a17:907:1b20:b0:6da:649b:d99e with SMTP id mp32-20020a1709071b2000b006da649bd99emr14622713ejc.712.1655588408506; Sat, 18 Jun 2022 14:40:08 -0700 (PDT) Received: from localhost (92.40.169.177.threembb.co.uk. [92.40.169.177]) by smtp.gmail.com with ESMTPSA id hb44-20020a170907162c00b006ff59151e34sm3834540ejc.39.2022.06.18.14.40.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jun 2022 14:40:08 -0700 (PDT) From: Aidan MacDonald To: linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, wens@csie.org, jic23@kernel.org, lee.jones@linaro.org, sre@kernel.org, broonie@kernel.org, gregkh@linuxfoundation.org, lgirdwood@gmail.com Cc: lars@metafoo.de, rafael@kernel.org, quic_gurus@quicinc.com, sebastian.reichel@collabora.com, andy.shevchenko@gmail.com, michael@walle.cc, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v3 08/16] mfd: axp20x: Add support for AXP192 Date: Sat, 18 Jun 2022 22:40:01 +0100 Message-Id: <20220618214009.2178567-9-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220618214009.2178567-1-aidanmacdonald.0x0@gmail.com> References: <20220618214009.2178567-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The AXP192 PMIC is similar to the AXP202/AXP209, but with different regulators, additional GPIOs, and a different IRQ register layout. Signed-off-by: Aidan MacDonald --- drivers/mfd/axp20x-i2c.c | 2 + drivers/mfd/axp20x.c | 153 +++++++++++++++++++++++++++++++++++++ include/linux/mfd/axp20x.h | 84 ++++++++++++++++++++ 3 files changed, 239 insertions(+) diff --git a/drivers/mfd/axp20x-i2c.c b/drivers/mfd/axp20x-i2c.c index 00ab48018d8d..9ada58fad77f 100644 --- a/drivers/mfd/axp20x-i2c.c +++ b/drivers/mfd/axp20x-i2c.c @@ -62,6 +62,7 @@ static int axp20x_i2c_remove(struct i2c_client *i2c) #ifdef CONFIG_OF static const struct of_device_id axp20x_i2c_of_match[] = { { .compatible = "x-powers,axp152", .data = (void *)AXP152_ID }, + { .compatible = "x-powers,axp192", .data = (void *)AXP192_ID }, { .compatible = "x-powers,axp202", .data = (void *)AXP202_ID }, { .compatible = "x-powers,axp209", .data = (void *)AXP209_ID }, { .compatible = "x-powers,axp221", .data = (void *)AXP221_ID }, @@ -75,6 +76,7 @@ MODULE_DEVICE_TABLE(of, axp20x_i2c_of_match); static const struct i2c_device_id axp20x_i2c_id[] = { { "axp152", 0 }, + { "axp192", 0 }, { "axp202", 0 }, { "axp209", 0 }, { "axp221", 0 }, diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c index 8161a5dc68e8..1011e668589a 100644 --- a/drivers/mfd/axp20x.c +++ b/drivers/mfd/axp20x.c @@ -34,6 +34,7 @@ static const char * const axp20x_model_names[] = { "AXP152", + "AXP192", "AXP202", "AXP209", "AXP221", @@ -92,6 +93,35 @@ static const struct regmap_access_table axp20x_volatile_table = { .n_yes_ranges = ARRAY_SIZE(axp20x_volatile_ranges), }; +static const struct regmap_range axp192_writeable_ranges[] = { + regmap_reg_range(AXP192_DATACACHE(0), AXP192_DATACACHE(5)), + regmap_reg_range(AXP192_PWR_OUT_CTRL, AXP192_IRQ5_STATE), + regmap_reg_range(AXP20X_DCDC_MODE, AXP192_N_RSTO_CTRL), + regmap_reg_range(AXP20X_CC_CTRL, AXP20X_CC_CTRL), +}; + +static const struct regmap_range axp192_volatile_ranges[] = { + regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP192_USB_OTG_STATUS), + regmap_reg_range(AXP192_IRQ1_STATE, AXP192_IRQ4_STATE), + regmap_reg_range(AXP192_IRQ5_STATE, AXP192_IRQ5_STATE), + regmap_reg_range(AXP20X_ACIN_V_ADC_H, AXP20X_IPSOUT_V_HIGH_L), + regmap_reg_range(AXP20X_TIMER_CTRL, AXP20X_TIMER_CTRL), + regmap_reg_range(AXP192_GPIO2_0_STATE, AXP192_GPIO2_0_STATE), + regmap_reg_range(AXP192_GPIO4_3_STATE, AXP192_GPIO4_3_STATE), + regmap_reg_range(AXP192_N_RSTO_CTRL, AXP192_N_RSTO_CTRL), + regmap_reg_range(AXP20X_CHRG_CC_31_24, AXP20X_CC_CTRL), +}; + +static const struct regmap_access_table axp192_writeable_table = { + .yes_ranges = axp192_writeable_ranges, + .n_yes_ranges = ARRAY_SIZE(axp192_writeable_ranges), +}; + +static const struct regmap_access_table axp192_volatile_table = { + .yes_ranges = axp192_volatile_ranges, + .n_yes_ranges = ARRAY_SIZE(axp192_volatile_ranges), +}; + /* AXP22x ranges are shared with the AXP809, as they cover the same range */ static const struct regmap_range axp22x_writeable_ranges[] = { regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE), @@ -173,6 +203,25 @@ static const struct resource axp152_pek_resources[] = { DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_FAL_EDGE, "PEK_DBF"), }; +static const struct resource axp192_gpio_resources[] = { + DEFINE_RES_IRQ_NAMED(AXP192_IRQ_GPIO0_INPUT, "GPIO0"), + DEFINE_RES_IRQ_NAMED(AXP192_IRQ_GPIO1_INPUT, "GPIO1"), + DEFINE_RES_IRQ_NAMED(AXP192_IRQ_GPIO2_INPUT, "GPIO2"), +}; + +static const struct resource axp192_ac_power_supply_resources[] = { + DEFINE_RES_IRQ_NAMED(AXP192_IRQ_ACIN_PLUGIN, "ACIN_PLUGIN"), + DEFINE_RES_IRQ_NAMED(AXP192_IRQ_ACIN_REMOVAL, "ACIN_REMOVAL"), + DEFINE_RES_IRQ_NAMED(AXP192_IRQ_ACIN_OVER_V, "ACIN_OVER_V"), +}; + +static const struct resource axp192_usb_power_supply_resources[] = { + DEFINE_RES_IRQ_NAMED(AXP192_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"), + DEFINE_RES_IRQ_NAMED(AXP192_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"), + DEFINE_RES_IRQ_NAMED(AXP192_IRQ_VBUS_VALID, "VBUS_VALID"), + DEFINE_RES_IRQ_NAMED(AXP192_IRQ_VBUS_NOT_VALID, "VBUS_NOT_VALID"), +}; + static const struct resource axp20x_ac_power_supply_resources[] = { DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_PLUGIN, "ACIN_PLUGIN"), DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_REMOVAL, "ACIN_REMOVAL"), @@ -245,6 +294,15 @@ static const struct regmap_config axp152_regmap_config = { .cache_type = REGCACHE_RBTREE, }; +static const struct regmap_config axp192_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .wr_table = &axp192_writeable_table, + .volatile_table = &axp192_volatile_table, + .max_register = AXP20X_CC_CTRL, + .cache_type = REGCACHE_RBTREE, +}; + static const struct regmap_config axp20x_regmap_config = { .reg_bits = 8, .val_bits = 8, @@ -304,6 +362,55 @@ static const struct regmap_irq axp152_regmap_irqs[] = { INIT_REGMAP_IRQ(AXP152, GPIO0_INPUT, 2, 0), }; +static const struct regmap_irq axp192_regmap_irqs[] = { + INIT_REGMAP_IRQ(AXP192, ACIN_OVER_V, 0, 7), + INIT_REGMAP_IRQ(AXP192, ACIN_PLUGIN, 0, 6), + INIT_REGMAP_IRQ(AXP192, ACIN_REMOVAL, 0, 5), + INIT_REGMAP_IRQ(AXP192, VBUS_OVER_V, 0, 4), + INIT_REGMAP_IRQ(AXP192, VBUS_PLUGIN, 0, 3), + INIT_REGMAP_IRQ(AXP192, VBUS_REMOVAL, 0, 2), + INIT_REGMAP_IRQ(AXP192, VBUS_V_LOW, 0, 1), + INIT_REGMAP_IRQ(AXP192, BATT_PLUGIN, 1, 7), + INIT_REGMAP_IRQ(AXP192, BATT_REMOVAL, 1, 6), + INIT_REGMAP_IRQ(AXP192, BATT_ENT_ACT_MODE, 1, 5), + INIT_REGMAP_IRQ(AXP192, BATT_EXIT_ACT_MODE, 1, 4), + INIT_REGMAP_IRQ(AXP192, CHARG, 1, 3), + INIT_REGMAP_IRQ(AXP192, CHARG_DONE, 1, 2), + INIT_REGMAP_IRQ(AXP192, BATT_TEMP_HIGH, 1, 1), + INIT_REGMAP_IRQ(AXP192, BATT_TEMP_LOW, 1, 0), + INIT_REGMAP_IRQ(AXP192, DIE_TEMP_HIGH, 2, 7), + INIT_REGMAP_IRQ(AXP192, CHARG_I_LOW, 2, 6), + INIT_REGMAP_IRQ(AXP192, DCDC1_V_LONG, 2, 5), + INIT_REGMAP_IRQ(AXP192, DCDC2_V_LONG, 2, 4), + INIT_REGMAP_IRQ(AXP192, DCDC3_V_LONG, 2, 3), + INIT_REGMAP_IRQ(AXP192, PEK_SHORT, 2, 1), + INIT_REGMAP_IRQ(AXP192, PEK_LONG, 2, 0), + INIT_REGMAP_IRQ(AXP192, N_OE_PWR_ON, 3, 7), + INIT_REGMAP_IRQ(AXP192, N_OE_PWR_OFF, 3, 6), + INIT_REGMAP_IRQ(AXP192, VBUS_VALID, 3, 5), + INIT_REGMAP_IRQ(AXP192, VBUS_NOT_VALID, 3, 4), + INIT_REGMAP_IRQ(AXP192, VBUS_SESS_VALID, 3, 3), + INIT_REGMAP_IRQ(AXP192, VBUS_SESS_END, 3, 2), + INIT_REGMAP_IRQ(AXP192, LOW_PWR_LVL, 3, 0), + INIT_REGMAP_IRQ(AXP192, TIMER, 4, 7), + INIT_REGMAP_IRQ(AXP192, GPIO2_INPUT, 4, 2), + INIT_REGMAP_IRQ(AXP192, GPIO1_INPUT, 4, 1), + INIT_REGMAP_IRQ(AXP192, GPIO0_INPUT, 4, 0), +}; + +static int axp192_get_irq_reg(unsigned int base_reg, int i) +{ + /* linear mapping for IRQ1 to IRQ4 */ + if (i < 4) + return base_reg + i; + + /* handle IRQ5 separately */ + if (base_reg == AXP192_IRQ1_EN) + return AXP192_IRQ5_EN; + else + return AXP192_IRQ5_STATE; +} + static const struct regmap_irq axp20x_regmap_irqs[] = { INIT_REGMAP_IRQ(AXP20X, ACIN_OVER_V, 0, 7), INIT_REGMAP_IRQ(AXP20X, ACIN_PLUGIN, 0, 6), @@ -514,6 +621,19 @@ static const struct regmap_irq_chip axp152_regmap_irq_chip = { .num_regs = 3, }; +static const struct regmap_irq_chip axp192_regmap_irq_chip = { + .name = "axp192_irq_chip", + .status_base = AXP192_IRQ1_STATE, + .ack_base = AXP192_IRQ1_STATE, + .mask_base = AXP192_IRQ1_EN, + .mask_invert = true, + .init_ack_masked = true, + .irqs = axp192_regmap_irqs, + .num_irqs = ARRAY_SIZE(axp192_regmap_irqs), + .num_regs = 5, + .get_irq_reg = axp192_get_irq_reg, +}; + static const struct regmap_irq_chip axp20x_regmap_irq_chip = { .name = "axp20x_irq_chip", .status_base = AXP20X_IRQ1_STATE, @@ -588,6 +708,33 @@ static const struct regmap_irq_chip axp809_regmap_irq_chip = { .num_regs = 5, }; +static const struct mfd_cell axp192_cells[] = { + { + .name = "axp192-gpio", + .of_compatible = "x-powers,axp192-gpio", + .num_resources = ARRAY_SIZE(axp192_gpio_resources), + .resources = axp192_gpio_resources, + }, { + .name = "axp20x-regulator", + }, { + .name = "axp192-adc", + .of_compatible = "x-powers,axp192-adc", + }, { + .name = "axp20x-battery-power-supply", + .of_compatible = "x-powers,axp192-battery-power-supply", + }, { + .name = "axp20x-ac-power-supply", + .of_compatible = "x-powers,axp202-ac-power-supply", + .num_resources = ARRAY_SIZE(axp192_ac_power_supply_resources), + .resources = axp192_ac_power_supply_resources, + }, { + .name = "axp20x-usb-power-supply", + .of_compatible = "x-powers,axp192-usb-power-supply", + .num_resources = ARRAY_SIZE(axp192_usb_power_supply_resources), + .resources = axp192_usb_power_supply_resources, + } +}; + static const struct mfd_cell axp20x_cells[] = { { .name = "axp20x-gpio", @@ -865,6 +1012,12 @@ int axp20x_match_device(struct axp20x_dev *axp20x) axp20x->regmap_cfg = &axp152_regmap_config; axp20x->regmap_irq_chip = &axp152_regmap_irq_chip; break; + case AXP192_ID: + axp20x->nr_cells = ARRAY_SIZE(axp192_cells); + axp20x->cells = axp192_cells; + axp20x->regmap_cfg = &axp192_regmap_config; + axp20x->regmap_irq_chip = &axp192_regmap_irq_chip; + break; case AXP202_ID: case AXP209_ID: axp20x->nr_cells = ARRAY_SIZE(axp20x_cells); diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h index 9ab0e2fca7ea..18546e124919 100644 --- a/include/linux/mfd/axp20x.h +++ b/include/linux/mfd/axp20x.h @@ -12,6 +12,7 @@ enum axp20x_variants { AXP152_ID = 0, + AXP192_ID, AXP202_ID, AXP209_ID, AXP221_ID, @@ -24,6 +25,7 @@ enum axp20x_variants { NR_AXP20X_VARIANTS, }; +#define AXP192_DATACACHE(m) (0x06 + (m)) #define AXP20X_DATACACHE(m) (0x04 + (m)) /* Power supply */ @@ -45,6 +47,13 @@ enum axp20x_variants { #define AXP152_DCDC_FREQ 0x37 #define AXP152_DCDC_MODE 0x80 +#define AXP192_USB_OTG_STATUS 0x04 +#define AXP192_PWR_OUT_CTRL 0x12 +#define AXP192_DCDC2_V_OUT 0x23 +#define AXP192_DCDC1_V_OUT 0x26 +#define AXP192_DCDC3_V_OUT 0x27 +#define AXP192_LDO2_3_V_OUT 0x28 + #define AXP20X_PWR_INPUT_STATUS 0x00 #define AXP20X_PWR_OP_MODE 0x01 #define AXP20X_USB_OTG_STATUS 0x02 @@ -139,6 +148,17 @@ enum axp20x_variants { #define AXP152_IRQ2_STATE 0x49 #define AXP152_IRQ3_STATE 0x4a +#define AXP192_IRQ1_EN 0x40 +#define AXP192_IRQ2_EN 0x41 +#define AXP192_IRQ3_EN 0x42 +#define AXP192_IRQ4_EN 0x43 +#define AXP192_IRQ1_STATE 0x44 +#define AXP192_IRQ2_STATE 0x45 +#define AXP192_IRQ3_STATE 0x46 +#define AXP192_IRQ4_STATE 0x47 +#define AXP192_IRQ5_EN 0x4a +#define AXP192_IRQ5_STATE 0x4d + #define AXP20X_IRQ1_EN 0x40 #define AXP20X_IRQ2_EN 0x41 #define AXP20X_IRQ3_EN 0x42 @@ -153,6 +173,11 @@ enum axp20x_variants { #define AXP20X_IRQ6_STATE 0x4d /* ADC */ +#define AXP192_GPIO2_V_ADC_H 0x68 +#define AXP192_GPIO2_V_ADC_L 0x69 +#define AXP192_GPIO3_V_ADC_H 0x6a +#define AXP192_GPIO3_V_ADC_L 0x6b + #define AXP20X_ACIN_V_ADC_H 0x56 #define AXP20X_ACIN_V_ADC_L 0x57 #define AXP20X_ACIN_I_ADC_H 0x58 @@ -182,6 +207,8 @@ enum axp20x_variants { #define AXP20X_IPSOUT_V_HIGH_L 0x7f /* Power supply */ +#define AXP192_GPIO30_IN_RANGE 0x85 + #define AXP20X_DCDC_MODE 0x80 #define AXP20X_ADC_EN1 0x82 #define AXP20X_ADC_EN2 0x83 @@ -210,6 +237,16 @@ enum axp20x_variants { #define AXP152_PWM1_FREQ_Y 0x9c #define AXP152_PWM1_DUTY_CYCLE 0x9d +#define AXP192_GPIO0_CTRL 0x90 +#define AXP192_LDO_IO0_V_OUT 0x91 +#define AXP192_GPIO1_CTRL 0x92 +#define AXP192_GPIO2_CTRL 0x93 +#define AXP192_GPIO2_0_STATE 0x94 +#define AXP192_GPIO4_3_CTRL 0x95 +#define AXP192_GPIO4_3_STATE 0x96 +#define AXP192_GPIO2_0_PULL 0x97 +#define AXP192_N_RSTO_CTRL 0x9e + #define AXP20X_GPIO0_CTRL 0x90 #define AXP20X_LDO5_V_OUT 0x91 #define AXP20X_GPIO1_CTRL 0x92 @@ -287,6 +324,17 @@ enum axp20x_variants { #define AXP288_FG_TUNE5 0xed /* Regulators IDs */ +enum { + AXP192_DCDC1 = 0, + AXP192_DCDC2, + AXP192_DCDC3, + AXP192_LDO1, + AXP192_LDO2, + AXP192_LDO3, + AXP192_LDO_IO0, + AXP192_REG_ID_MAX, +}; + enum { AXP20X_LDO1 = 0, AXP20X_LDO2, @@ -440,6 +488,42 @@ enum { AXP152_IRQ_GPIO0_INPUT, }; +enum axp192_irqs { + AXP192_IRQ_ACIN_OVER_V = 1, + AXP192_IRQ_ACIN_PLUGIN, + AXP192_IRQ_ACIN_REMOVAL, + AXP192_IRQ_VBUS_OVER_V, + AXP192_IRQ_VBUS_PLUGIN, + AXP192_IRQ_VBUS_REMOVAL, + AXP192_IRQ_VBUS_V_LOW, + AXP192_IRQ_BATT_PLUGIN, + AXP192_IRQ_BATT_REMOVAL, + AXP192_IRQ_BATT_ENT_ACT_MODE, + AXP192_IRQ_BATT_EXIT_ACT_MODE, + AXP192_IRQ_CHARG, + AXP192_IRQ_CHARG_DONE, + AXP192_IRQ_BATT_TEMP_HIGH, + AXP192_IRQ_BATT_TEMP_LOW, + AXP192_IRQ_DIE_TEMP_HIGH, + AXP192_IRQ_CHARG_I_LOW, + AXP192_IRQ_DCDC1_V_LONG, + AXP192_IRQ_DCDC2_V_LONG, + AXP192_IRQ_DCDC3_V_LONG, + AXP192_IRQ_PEK_SHORT = 22, + AXP192_IRQ_PEK_LONG, + AXP192_IRQ_N_OE_PWR_ON, + AXP192_IRQ_N_OE_PWR_OFF, + AXP192_IRQ_VBUS_VALID, + AXP192_IRQ_VBUS_NOT_VALID, + AXP192_IRQ_VBUS_SESS_VALID, + AXP192_IRQ_VBUS_SESS_END, + AXP192_IRQ_LOW_PWR_LVL = 31, + AXP192_IRQ_TIMER, + AXP192_IRQ_GPIO2_INPUT = 37, + AXP192_IRQ_GPIO1_INPUT, + AXP192_IRQ_GPIO0_INPUT, +}; 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[92.40.169.177]) by smtp.gmail.com with ESMTPSA id y4-20020aa7ccc4000000b004316f94ec4esm6459638edt.66.2022.06.18.14.40.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jun 2022 14:40:11 -0700 (PDT) From: Aidan MacDonald To: linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, wens@csie.org, jic23@kernel.org, lee.jones@linaro.org, sre@kernel.org, broonie@kernel.org, gregkh@linuxfoundation.org, lgirdwood@gmail.com Cc: lars@metafoo.de, rafael@kernel.org, quic_gurus@quicinc.com, sebastian.reichel@collabora.com, andy.shevchenko@gmail.com, michael@walle.cc, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v3 10/16] iio: adc: axp20x_adc: Minor code cleanups Date: Sat, 18 Jun 2022 22:40:03 +0100 Message-Id: <20220618214009.2178567-11-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220618214009.2178567-1-aidanmacdonald.0x0@gmail.com> References: <20220618214009.2178567-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The code may be clearer if parameters are not re-purposed to hold temporary results like register values, so introduce local variables as necessary to avoid that. Also, use the common FIELD_PREP macro instead of a hand-rolled version. Suggested-by: Jonathan Cameron Signed-off-by: Aidan MacDonald --- drivers/iio/adc/axp20x_adc.c | 61 +++++++++++++++++++----------------- 1 file changed, 33 insertions(+), 28 deletions(-) diff --git a/drivers/iio/adc/axp20x_adc.c b/drivers/iio/adc/axp20x_adc.c index 53bf7d4899d2..041511280e1e 100644 --- a/drivers/iio/adc/axp20x_adc.c +++ b/drivers/iio/adc/axp20x_adc.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -22,20 +23,20 @@ #include #define AXP20X_ADC_EN1_MASK GENMASK(7, 0) - #define AXP20X_ADC_EN2_MASK (GENMASK(3, 2) | BIT(7)) + #define AXP22X_ADC_EN1_MASK (GENMASK(7, 5) | BIT(0)) #define AXP20X_GPIO10_IN_RANGE_GPIO0 BIT(0) #define AXP20X_GPIO10_IN_RANGE_GPIO1 BIT(1) -#define AXP20X_GPIO10_IN_RANGE_GPIO0_VAL(x) ((x) & BIT(0)) -#define AXP20X_GPIO10_IN_RANGE_GPIO1_VAL(x) (((x) & BIT(0)) << 1) #define AXP20X_ADC_RATE_MASK GENMASK(7, 6) -#define AXP813_V_I_ADC_RATE_MASK GENMASK(5, 4) -#define AXP813_ADC_RATE_MASK (AXP20X_ADC_RATE_MASK | AXP813_V_I_ADC_RATE_MASK) #define AXP20X_ADC_RATE_HZ(x) ((ilog2((x) / 25) << 6) & AXP20X_ADC_RATE_MASK) + #define AXP22X_ADC_RATE_HZ(x) ((ilog2((x) / 100) << 6) & AXP20X_ADC_RATE_MASK) + +#define AXP813_V_I_ADC_RATE_MASK GENMASK(5, 4) +#define AXP813_ADC_RATE_MASK (AXP20X_ADC_RATE_MASK | AXP813_V_I_ADC_RATE_MASK) #define AXP813_TS_GPIO0_ADC_RATE_HZ(x) AXP20X_ADC_RATE_HZ(x) #define AXP813_V_I_ADC_RATE_HZ(x) ((ilog2((x) / 100) << 4) & AXP813_V_I_ADC_RATE_MASK) #define AXP813_ADC_RATE_HZ(x) (AXP20X_ADC_RATE_HZ(x) | AXP813_V_I_ADC_RATE_HZ(x)) @@ -234,7 +235,7 @@ static int axp20x_adc_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val) { struct axp20x_adc_iio *info = iio_priv(indio_dev); - int size = 12; + int ret, size; /* * N.B.: Unlike the Chinese datasheets tell, the charging current is @@ -246,10 +247,11 @@ static int axp20x_adc_raw(struct iio_dev *indio_dev, else size = 12; - *val = axp20x_read_variable_width(info->regmap, chan->address, size); - if (*val < 0) - return *val; + ret = axp20x_read_variable_width(info->regmap, chan->address, size); + if (ret < 0) + return ret; + *val = ret; return IIO_VAL_INT; } @@ -257,11 +259,13 @@ static int axp22x_adc_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val) { struct axp20x_adc_iio *info = iio_priv(indio_dev); + int ret; - *val = axp20x_read_variable_width(info->regmap, chan->address, 12); - if (*val < 0) - return *val; + ret = axp20x_read_variable_width(info->regmap, chan->address, 12); + if (ret < 0) + return ret; + *val = ret; return IIO_VAL_INT; } @@ -269,11 +273,13 @@ static int axp813_adc_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val) { struct axp20x_adc_iio *info = iio_priv(indio_dev); + int ret; - *val = axp20x_read_variable_width(info->regmap, chan->address, 12); - if (*val < 0) - return *val; + ret = axp20x_read_variable_width(info->regmap, chan->address, 12); + if (ret < 0) + return ret; + *val = ret; return IIO_VAL_INT; } @@ -443,27 +449,27 @@ static int axp20x_adc_offset_voltage(struct iio_dev *indio_dev, int channel, int *val) { struct axp20x_adc_iio *info = iio_priv(indio_dev); + unsigned int regval; int ret; - ret = regmap_read(info->regmap, AXP20X_GPIO10_IN_RANGE, val); + ret = regmap_read(info->regmap, AXP20X_GPIO10_IN_RANGE, ®val); if (ret < 0) return ret; switch (channel) { case AXP20X_GPIO0_V: - *val &= AXP20X_GPIO10_IN_RANGE_GPIO0; + regval = FIELD_GET(AXP20X_GPIO10_IN_RANGE_GPIO0, regval); break; case AXP20X_GPIO1_V: - *val &= AXP20X_GPIO10_IN_RANGE_GPIO1; + regval = FIELD_GET(AXP20X_GPIO10_IN_RANGE_GPIO1, regval); break; default: return -EINVAL; } - *val = *val ? 700000 : 0; - + *val = regval ? 700000 : 0; return IIO_VAL_INT; } @@ -548,7 +554,7 @@ static int axp20x_write_raw(struct iio_dev *indio_dev, long mask) { struct axp20x_adc_iio *info = iio_priv(indio_dev); - unsigned int reg, regval; + unsigned int regmask, regval; /* * The AXP20X PMIC allows the user to choose between 0V and 0.7V offsets @@ -560,25 +566,24 @@ static int axp20x_write_raw(struct iio_dev *indio_dev, if (val != 0 && val != 700000) return -EINVAL; - val = val ? 1 : 0; + regval = val ? 1 : 0; switch (chan->channel) { case AXP20X_GPIO0_V: - reg = AXP20X_GPIO10_IN_RANGE_GPIO0; - regval = AXP20X_GPIO10_IN_RANGE_GPIO0_VAL(val); + regmask = AXP20X_GPIO10_IN_RANGE_GPIO0; + regval = FIELD_PREP(AXP20X_GPIO10_IN_RANGE_GPIO0, regval); break; case AXP20X_GPIO1_V: - reg = AXP20X_GPIO10_IN_RANGE_GPIO1; - regval = AXP20X_GPIO10_IN_RANGE_GPIO1_VAL(val); + regmask = AXP20X_GPIO10_IN_RANGE_GPIO1; + regval = FIELD_PREP(AXP20X_GPIO10_IN_RANGE_GPIO1, regval); break; default: return -EINVAL; } - return regmap_update_bits(info->regmap, AXP20X_GPIO10_IN_RANGE, reg, - regval); + return regmap_update_bits(info->regmap, AXP20X_GPIO10_IN_RANGE, regmask, regval); } static const struct iio_info axp20x_adc_iio_info = { From patchwork Sat Jun 18 21:40:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 582788 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A81C0CCA480 for ; Sat, 18 Jun 2022 21:40:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235557AbiFRVkf (ORCPT ); Sat, 18 Jun 2022 17:40:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43856 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235650AbiFRVkV (ORCPT ); Sat, 18 Jun 2022 17:40:21 -0400 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E53CDEE10; Sat, 18 Jun 2022 14:40:14 -0700 (PDT) Received: by mail-ej1-x62a.google.com with SMTP id hj18so13987150ejb.0; Sat, 18 Jun 2022 14:40:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ICL0c0x7JA7wnpSBszOQ6Yn0R6i5pAULi57Tw1maK9s=; b=AcCll0DXTsqIQ7OUB0Mpm3PYSLNKZUHfmVc1RDDgkZyt/goNecf0iphGS4Fkx3pevG G2g3WqforVJgheeyEw+18Iw090n7TBolToKN6wnUwy88B3SG/D5N7e5ednpWez5ndD+5 1RqtP+R1LodTnoHtnlXstFiomMU5mytwosphYHH0THxam0l5KXk07S1h6ptN7E5NkmZt Cuj11JJA93McNZbvRlhNHS/kcX2m+TMdPPVZVAMcz2Oj+HWFs+5z22VWSisJlgXMUeVK T6DJQxVoYaElT/4bMR5bn28b4HPrj7EkdjyzMc8QiMyjLhEByXdtTedZ+V5O7kN4Eybs pQrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ICL0c0x7JA7wnpSBszOQ6Yn0R6i5pAULi57Tw1maK9s=; b=rJZseTlfiaEDD6u4ydJkK118pH0qPrbS+hqYIKf63TEg5nWOQmQAQtgoatUVx7wuk+ 93538Cy0e+WbZIVEkaGcUbwZPwt/CTabhnJuJYwJS+kuT6sIEqk0cvX9YSltrbrJkBSR btmQpiSg27vFi8RlWerbv1fJyjSuGM/0xsYsMkn6VNPnMtVtqy6WPGL/wMGNfqL6+f3J /Na7eB33jqlPiOV2ihvj6VgaASQxNRJ/IfaG//g3ensZwtq8YLDgorpwjLGh6dmbNF3h OCAAnFHSx8rIoR4uLMEXidHNabxQMhImEG8oBq6G6TBP37q3QEU8ghVWjWqwMc2Id0/i gefg== X-Gm-Message-State: AJIora9KTxbmV3hT1ix++B/61fBlaCWOQJix+K4/E5sRpBnxkpGBFs6F zxhvqY/OeZHxUgFACi2oUA0= X-Google-Smtp-Source: AGRyM1u72XuZH/cBRb4Se7yesdvVgYIC2JRfxukEgUPmDxRidh+XG3aGnmxsbJ1C6mVsP03JMfNN/g== X-Received: by 2002:a17:907:9005:b0:718:391:45e with SMTP id ay5-20020a170907900500b007180391045emr14981295ejc.616.1655588413344; Sat, 18 Jun 2022 14:40:13 -0700 (PDT) Received: from localhost (92.40.169.177.threembb.co.uk. [92.40.169.177]) by smtp.gmail.com with ESMTPSA id s19-20020a056402521300b0042617ba637bsm6823652edd.5.2022.06.18.14.40.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jun 2022 14:40:12 -0700 (PDT) From: Aidan MacDonald To: linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, wens@csie.org, jic23@kernel.org, lee.jones@linaro.org, sre@kernel.org, broonie@kernel.org, gregkh@linuxfoundation.org, lgirdwood@gmail.com Cc: lars@metafoo.de, rafael@kernel.org, quic_gurus@quicinc.com, sebastian.reichel@collabora.com, andy.shevchenko@gmail.com, michael@walle.cc, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v3 11/16] iio: adc: axp20x_adc: Add support for AXP192 Date: Sat, 18 Jun 2022 22:40:04 +0100 Message-Id: <20220618214009.2178567-12-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220618214009.2178567-1-aidanmacdonald.0x0@gmail.com> References: <20220618214009.2178567-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The AXP192 is identical to the AXP20x, except for the addition of two more GPIO ADC channels. Signed-off-by: Aidan MacDonald Reviewed-by: Jonathan Cameron --- drivers/iio/adc/axp20x_adc.c | 298 +++++++++++++++++++++++++++++++++-- 1 file changed, 289 insertions(+), 9 deletions(-) diff --git a/drivers/iio/adc/axp20x_adc.c b/drivers/iio/adc/axp20x_adc.c index 041511280e1e..929aa14f9cf3 100644 --- a/drivers/iio/adc/axp20x_adc.c +++ b/drivers/iio/adc/axp20x_adc.c @@ -22,11 +22,19 @@ #include #include +#define AXP192_ADC_EN1_MASK GENMASK(7, 0) +#define AXP192_ADC_EN2_MASK (GENMASK(3, 0) | BIT(7)) + #define AXP20X_ADC_EN1_MASK GENMASK(7, 0) #define AXP20X_ADC_EN2_MASK (GENMASK(3, 2) | BIT(7)) #define AXP22X_ADC_EN1_MASK (GENMASK(7, 5) | BIT(0)) +#define AXP192_GPIO30_IN_RANGE_GPIO0 BIT(0) +#define AXP192_GPIO30_IN_RANGE_GPIO1 BIT(1) +#define AXP192_GPIO30_IN_RANGE_GPIO2 BIT(2) +#define AXP192_GPIO30_IN_RANGE_GPIO3 BIT(3) + #define AXP20X_GPIO10_IN_RANGE_GPIO0 BIT(0) #define AXP20X_GPIO10_IN_RANGE_GPIO1 BIT(1) @@ -71,6 +79,25 @@ struct axp20x_adc_iio { const struct axp_data *data; }; +enum axp192_adc_channel_v { + AXP192_ACIN_V = 0, + AXP192_VBUS_V, + AXP192_TS_IN, + AXP192_GPIO0_V, + AXP192_GPIO1_V, + AXP192_GPIO2_V, + AXP192_GPIO3_V, + AXP192_IPSOUT_V, + AXP192_BATT_V, +}; + +enum axp192_adc_channel_i { + AXP192_ACIN_I = 0, + AXP192_VBUS_I, + AXP192_BATT_CHRG_I, + AXP192_BATT_DISCHRG_I, +}; + enum axp20x_adc_channel_v { AXP20X_ACIN_V = 0, AXP20X_VBUS_V, @@ -158,6 +185,43 @@ static struct iio_map axp22x_maps[] = { * The only exception is for the battery. batt_v will be in_voltage6_raw and * charge current in_current6_raw and discharge current will be in_current7_raw. */ +static const struct iio_chan_spec axp192_adc_channels[] = { + AXP20X_ADC_CHANNEL(AXP192_ACIN_V, "acin_v", IIO_VOLTAGE, + AXP20X_ACIN_V_ADC_H), + AXP20X_ADC_CHANNEL(AXP192_ACIN_I, "acin_i", IIO_CURRENT, + AXP20X_ACIN_I_ADC_H), + AXP20X_ADC_CHANNEL(AXP192_VBUS_V, "vbus_v", IIO_VOLTAGE, + AXP20X_VBUS_V_ADC_H), + AXP20X_ADC_CHANNEL(AXP192_VBUS_I, "vbus_i", IIO_CURRENT, + AXP20X_VBUS_I_ADC_H), + { + .type = IIO_TEMP, + .address = AXP20X_TEMP_ADC_H, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE) | + BIT(IIO_CHAN_INFO_OFFSET), + .datasheet_name = "pmic_temp", + }, + AXP20X_ADC_CHANNEL_OFFSET(AXP192_GPIO0_V, "gpio0_v", IIO_VOLTAGE, + AXP20X_GPIO0_V_ADC_H), + AXP20X_ADC_CHANNEL_OFFSET(AXP192_GPIO1_V, "gpio1_v", IIO_VOLTAGE, + AXP20X_GPIO1_V_ADC_H), + AXP20X_ADC_CHANNEL_OFFSET(AXP192_GPIO2_V, "gpio2_v", IIO_VOLTAGE, + AXP192_GPIO2_V_ADC_H), + AXP20X_ADC_CHANNEL_OFFSET(AXP192_GPIO3_V, "gpio3_v", IIO_VOLTAGE, + AXP192_GPIO3_V_ADC_H), + AXP20X_ADC_CHANNEL(AXP192_IPSOUT_V, "ipsout_v", IIO_VOLTAGE, + AXP20X_IPSOUT_V_HIGH_H), + AXP20X_ADC_CHANNEL(AXP192_BATT_V, "batt_v", IIO_VOLTAGE, + AXP20X_BATT_V_H), + AXP20X_ADC_CHANNEL(AXP192_BATT_CHRG_I, "batt_chrg_i", IIO_CURRENT, + AXP20X_BATT_CHRG_I_H), + AXP20X_ADC_CHANNEL(AXP192_BATT_DISCHRG_I, "batt_dischrg_i", IIO_CURRENT, + AXP20X_BATT_DISCHRG_I_H), + AXP20X_ADC_CHANNEL(AXP192_TS_IN, "ts_v", IIO_VOLTAGE, + AXP20X_TS_IN_H), +}; + static const struct iio_chan_spec axp20x_adc_channels[] = { AXP20X_ADC_CHANNEL(AXP20X_ACIN_V, "acin_v", IIO_VOLTAGE, AXP20X_ACIN_V_ADC_H), @@ -231,6 +295,27 @@ static const struct iio_chan_spec axp813_adc_channels[] = { AXP288_TS_ADC_H), }; +static int axp192_adc_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val) +{ + struct axp20x_adc_iio *info = iio_priv(indio_dev); + int ret, size; + + if (chan->type == IIO_CURRENT && + (chan->channel == AXP192_BATT_CHRG_I || + chan->channel == AXP192_BATT_DISCHRG_I)) + size = 13; + else + size = 12; + + ret = axp20x_read_variable_width(info->regmap, chan->address, size); + if (ret < 0) + return ret; + + *val = ret; + return IIO_VAL_INT; +} + static int axp20x_adc_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val) { @@ -283,6 +368,44 @@ static int axp813_adc_raw(struct iio_dev *indio_dev, return IIO_VAL_INT; } +static int axp192_adc_scale_voltage(int channel, int *val, int *val2) +{ + switch (channel) { + case AXP192_ACIN_V: + case AXP192_VBUS_V: + *val = 1; + *val2 = 700000; + return IIO_VAL_INT_PLUS_MICRO; + + case AXP192_GPIO0_V: + case AXP192_GPIO1_V: + case AXP192_GPIO2_V: + case AXP192_GPIO3_V: + *val = 0; + *val2 = 500000; + return IIO_VAL_INT_PLUS_MICRO; + + case AXP192_BATT_V: + *val = 1; + *val2 = 100000; + return IIO_VAL_INT_PLUS_MICRO; + + case AXP192_IPSOUT_V: + *val = 1; + *val2 = 400000; + return IIO_VAL_INT_PLUS_MICRO; + + case AXP192_TS_IN: + /* 0.8 mV per LSB */ + *val = 0; + *val2 = 800000; + return IIO_VAL_INT_PLUS_MICRO; + + default: + return -EINVAL; + } +} + static int axp20x_adc_scale_voltage(int channel, int *val, int *val2) { switch (channel) { @@ -386,6 +509,29 @@ static int axp20x_adc_scale_current(int channel, int *val, int *val2) } } +static int axp192_adc_scale(struct iio_chan_spec const *chan, int *val, + int *val2) +{ + switch (chan->type) { + case IIO_VOLTAGE: + return axp192_adc_scale_voltage(chan->channel, val, val2); + + case IIO_CURRENT: + /* + * AXP192 current channels are identical to the AXP20x, + * therefore we can re-use the scaling function. + */ + return axp20x_adc_scale_current(chan->channel, val, val2); + + case IIO_TEMP: + *val = 100; + return IIO_VAL_INT; + + default: + return -EINVAL; + } +} + static int axp20x_adc_scale(struct iio_chan_spec const *chan, int *val, int *val2) { @@ -445,6 +591,42 @@ static int axp813_adc_scale(struct iio_chan_spec const *chan, int *val, } } +static int axp192_adc_offset_voltage(struct iio_dev *indio_dev, int channel, + int *val) +{ + struct axp20x_adc_iio *info = iio_priv(indio_dev); + unsigned int regval; + int ret; + + ret = regmap_read(info->regmap, AXP192_GPIO30_IN_RANGE, ®val); + if (ret < 0) + return ret; + + switch (channel) { + case AXP192_GPIO0_V: + regval = FIELD_GET(AXP192_GPIO30_IN_RANGE_GPIO0, regval); + break; + + case AXP192_GPIO1_V: + regval = FIELD_GET(AXP192_GPIO30_IN_RANGE_GPIO1, regval); + break; + + case AXP192_GPIO2_V: + regval = FIELD_GET(AXP192_GPIO30_IN_RANGE_GPIO2, regval); + break; + + case AXP192_GPIO3_V: + regval = FIELD_GET(AXP192_GPIO30_IN_RANGE_GPIO3, regval); + break; + + default: + return -EINVAL; + } + + *val = regval ? 700000 : 0; + return IIO_VAL_INT; +} + static int axp20x_adc_offset_voltage(struct iio_dev *indio_dev, int channel, int *val) { @@ -473,6 +655,22 @@ static int axp20x_adc_offset_voltage(struct iio_dev *indio_dev, int channel, return IIO_VAL_INT; } +static int axp192_adc_offset(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val) +{ + switch (chan->type) { + case IIO_VOLTAGE: + return axp192_adc_offset_voltage(indio_dev, chan->channel, val); + + case IIO_TEMP: + *val = -1447; + return IIO_VAL_INT; + + default: + return -EINVAL; + } +} + static int axp20x_adc_offset(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val) { @@ -489,6 +687,25 @@ static int axp20x_adc_offset(struct iio_dev *indio_dev, } } +static int axp192_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long mask) +{ + switch (mask) { + case IIO_CHAN_INFO_OFFSET: + return axp192_adc_offset(indio_dev, chan, val); + + case IIO_CHAN_INFO_SCALE: + return axp192_adc_scale(chan, val, val2); + + case IIO_CHAN_INFO_RAW: + return axp192_adc_raw(indio_dev, chan, val); + + default: + return -EINVAL; + } +} + static int axp20x_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) @@ -549,6 +766,53 @@ static int axp813_read_raw(struct iio_dev *indio_dev, } } +static int axp192_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int val, int val2, + long mask) +{ + struct axp20x_adc_iio *info = iio_priv(indio_dev); + unsigned int regmask, regval; + + /* + * The AXP192 PMIC allows the user to choose between 0V and 0.7V offsets + * for (independently) GPIO0-3 when in ADC mode. + */ + if (mask != IIO_CHAN_INFO_OFFSET) + return -EINVAL; + + if (val != 0 && val != 700000) + return -EINVAL; + + regval = val ? 1 : 0; + + switch (chan->channel) { + case AXP192_GPIO0_V: + regmask = AXP192_GPIO30_IN_RANGE_GPIO0; + regval = FIELD_PREP(AXP192_GPIO30_IN_RANGE_GPIO0, regval); + break; + + case AXP192_GPIO1_V: + regmask = AXP192_GPIO30_IN_RANGE_GPIO1; + regval = FIELD_PREP(AXP192_GPIO30_IN_RANGE_GPIO1, regval); + break; + + case AXP192_GPIO2_V: + regmask = AXP192_GPIO30_IN_RANGE_GPIO2; + regval = FIELD_PREP(AXP192_GPIO30_IN_RANGE_GPIO2, regval); + break; + + case AXP192_GPIO3_V: + regmask = AXP192_GPIO30_IN_RANGE_GPIO3; + regval = FIELD_PREP(AXP192_GPIO30_IN_RANGE_GPIO3, regval); + break; + + default: + return -EINVAL; + } + + return regmap_update_bits(info->regmap, AXP192_GPIO30_IN_RANGE, regmask, regval); +} + static int axp20x_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) @@ -586,6 +850,11 @@ static int axp20x_write_raw(struct iio_dev *indio_dev, return regmap_update_bits(info->regmap, AXP20X_GPIO10_IN_RANGE, regmask, regval); } +static const struct iio_info axp192_adc_iio_info = { + .read_raw = axp192_read_raw, + .write_raw = axp192_write_raw, +}; + static const struct iio_info axp20x_adc_iio_info = { .read_raw = axp20x_read_raw, .write_raw = axp20x_write_raw, @@ -625,19 +894,29 @@ struct axp_data { int num_channels; struct iio_chan_spec const *channels; unsigned long adc_en1_mask; + unsigned long adc_en2_mask; int (*adc_rate)(struct axp20x_adc_iio *info, int rate); - bool adc_en2; struct iio_map *maps; }; +static const struct axp_data axp192_data = { + .iio_info = &axp192_adc_iio_info, + .num_channels = ARRAY_SIZE(axp192_adc_channels), + .channels = axp192_adc_channels, + .adc_en1_mask = AXP192_ADC_EN1_MASK, + .adc_en2_mask = AXP192_ADC_EN2_MASK, + .adc_rate = axp20x_adc_rate, + .maps = axp20x_maps, +}; + static const struct axp_data axp20x_data = { .iio_info = &axp20x_adc_iio_info, .num_channels = ARRAY_SIZE(axp20x_adc_channels), .channels = axp20x_adc_channels, .adc_en1_mask = AXP20X_ADC_EN1_MASK, + .adc_en2_mask = AXP20X_ADC_EN2_MASK, .adc_rate = axp20x_adc_rate, - .adc_en2 = true, .maps = axp20x_maps, }; @@ -647,7 +926,6 @@ static const struct axp_data axp22x_data = { .channels = axp22x_adc_channels, .adc_en1_mask = AXP22X_ADC_EN1_MASK, .adc_rate = axp22x_adc_rate, - .adc_en2 = false, .maps = axp22x_maps, }; @@ -657,11 +935,11 @@ static const struct axp_data axp813_data = { .channels = axp813_adc_channels, .adc_en1_mask = AXP22X_ADC_EN1_MASK, .adc_rate = axp813_adc_rate, - .adc_en2 = false, .maps = axp22x_maps, }; static const struct of_device_id axp20x_adc_of_match[] = { + { .compatible = "x-powers,axp192-adc", .data = (void *)&axp192_data, }, { .compatible = "x-powers,axp209-adc", .data = (void *)&axp20x_data, }, { .compatible = "x-powers,axp221-adc", .data = (void *)&axp22x_data, }, { .compatible = "x-powers,axp813-adc", .data = (void *)&axp813_data, }, @@ -670,6 +948,7 @@ static const struct of_device_id axp20x_adc_of_match[] = { MODULE_DEVICE_TABLE(of, axp20x_adc_of_match); static const struct platform_device_id axp20x_adc_id_match[] = { + { .name = "axp192-adc", .driver_data = (kernel_ulong_t)&axp192_data, }, { .name = "axp20x-adc", .driver_data = (kernel_ulong_t)&axp20x_data, }, { .name = "axp22x-adc", .driver_data = (kernel_ulong_t)&axp22x_data, }, { .name = "axp813-adc", .driver_data = (kernel_ulong_t)&axp813_data, }, @@ -715,10 +994,11 @@ static int axp20x_probe(struct platform_device *pdev) /* Enable the ADCs on IP */ regmap_write(info->regmap, AXP20X_ADC_EN1, info->data->adc_en1_mask); - if (info->data->adc_en2) - /* Enable GPIO0/1 and internal temperature ADCs */ + if (info->data->adc_en2_mask) + /* Enable GPIO and internal temperature ADCs */ regmap_update_bits(info->regmap, AXP20X_ADC_EN2, - AXP20X_ADC_EN2_MASK, AXP20X_ADC_EN2_MASK); + info->data->adc_en2_mask, + info->data->adc_en2_mask); /* Configure ADCs rate */ info->data->adc_rate(info, 100); @@ -743,7 +1023,7 @@ static int axp20x_probe(struct platform_device *pdev) fail_map: regmap_write(info->regmap, AXP20X_ADC_EN1, 0); - if (info->data->adc_en2) + if (info->data->adc_en2_mask) regmap_write(info->regmap, AXP20X_ADC_EN2, 0); return ret; @@ -759,7 +1039,7 @@ static int axp20x_remove(struct platform_device *pdev) regmap_write(info->regmap, AXP20X_ADC_EN1, 0); - if (info->data->adc_en2) + if (info->data->adc_en2_mask) regmap_write(info->regmap, AXP20X_ADC_EN2, 0); return 0; From patchwork Sat Jun 18 21:40:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 582787 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3483FC43334 for ; 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[92.40.169.177]) by smtp.gmail.com with ESMTPSA id z6-20020a17090665c600b0070bdc059ab2sm3826993ejn.138.2022.06.18.14.40.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jun 2022 14:40:16 -0700 (PDT) From: Aidan MacDonald To: linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, wens@csie.org, jic23@kernel.org, lee.jones@linaro.org, sre@kernel.org, broonie@kernel.org, gregkh@linuxfoundation.org, lgirdwood@gmail.com Cc: lars@metafoo.de, rafael@kernel.org, quic_gurus@quicinc.com, sebastian.reichel@collabora.com, andy.shevchenko@gmail.com, michael@walle.cc, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v3 13/16] pinctrl: Add AXP192 pin control driver Date: Sat, 18 Jun 2022 22:40:06 +0100 Message-Id: <20220618214009.2178567-14-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220618214009.2178567-1-aidanmacdonald.0x0@gmail.com> References: <20220618214009.2178567-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The AXP192 PMIC's GPIO registers are much different from the GPIO registers of the AXP20x and AXP813 PMICs supported by the existing pinctrl-axp209 driver. It makes more sense to add a new driver for the AXP192, rather than add support in the existing axp20x driver. The pinctrl-axp192 driver is considerably more flexible in terms of register layout and should be able to support other X-Powers PMICs. Interrupts and pull down resistor configuration are supported too. Signed-off-by: Aidan MacDonald --- drivers/pinctrl/Kconfig | 14 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-axp192.c | 562 +++++++++++++++++++++++++++++++ 3 files changed, 577 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-axp192.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index f52960d2dfbe..a71e35de333d 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -113,6 +113,20 @@ config PINCTRL_AT91PIO4 Say Y here to enable the at91 pinctrl/gpio driver for Atmel PIO4 controller available on sama5d2 SoC. +config PINCTRL_AXP192 + tristate "X-Powers AXP192 PMIC pinctrl and GPIO Support" + depends on MFD_AXP20X + depends on OF + select PINMUX + select GENERIC_PINCONF + select GPIOLIB + help + AXP PMICs provides multiple GPIOs that can be muxed for different + functions. This driver bundles a pinctrl driver to select the function + muxing and a GPIO driver to handle the GPIO when the GPIO function is + selected. + Say Y to enable pinctrl and GPIO support for the AXP192 PMIC. + config PINCTRL_AXP209 tristate "X-Powers AXP209 PMIC pinctrl and GPIO Support" depends on MFD_AXP20X diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index e76f5cdc64b0..9d2b6420c5dd 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PINCTRL_ARTPEC6) += pinctrl-artpec6.o obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o +obj-$(CONFIG_PINCTRL_AXP192) += pinctrl-axp192.o obj-$(CONFIG_PINCTRL_AXP209) += pinctrl-axp209.o obj-$(CONFIG_PINCTRL_BM1880) += pinctrl-bm1880.o obj-$(CONFIG_PINCTRL_DA850_PUPD) += pinctrl-da850-pupd.o diff --git a/drivers/pinctrl/pinctrl-axp192.c b/drivers/pinctrl/pinctrl-axp192.c new file mode 100644 index 000000000000..6a920258662d --- /dev/null +++ b/drivers/pinctrl/pinctrl-axp192.c @@ -0,0 +1,562 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * AXP192 pinctrl and GPIO driver + * + * Copyright (C) 2022 Aidan MacDonald + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +enum { + AXP192_FUNC_OUTPUT = 0, + AXP192_FUNC_INPUT, + AXP192_FUNC_LDO, + AXP192_FUNC_PWM, + AXP192_FUNC_ADC, + AXP192_FUNC_LOW_OUTPUT, + AXP192_FUNC_FLOATING, + AXP192_FUNC_EXT_CHG_CTL, + AXP192_FUNC_LDO_STATUS, + AXP192_FUNCS_NB, +}; + +struct axp192_pctl_function { + const char *name; + /* Mux value written to the control register to select the function (-1 if unsupported) */ + const u8 *muxvals; + const char * const *groups; + unsigned int ngroups; +}; + +struct axp192_pctl_reg_info { + u8 reg; + u8 mask; +}; + +struct axp192_pctl_desc { + unsigned int npins; + const struct pinctrl_pin_desc *pins; + /* Description of the function control register for each pin */ + const struct axp192_pctl_reg_info *ctrl_regs; + /* Description of the output signal register for each pin */ + const struct axp192_pctl_reg_info *out_regs; + /* Description of the input signal register for each pin */ + const struct axp192_pctl_reg_info *in_regs; + /* Description of the pull down resistor config register for each pin */ + const struct axp192_pctl_reg_info *pull_down_regs; + + unsigned int nfunctions; + const struct axp192_pctl_function *functions; +}; + +static const struct pinctrl_pin_desc axp192_pins[] = { + PINCTRL_PIN(0, "GPIO0"), + PINCTRL_PIN(1, "GPIO1"), + PINCTRL_PIN(2, "GPIO2"), + PINCTRL_PIN(3, "GPIO3"), + PINCTRL_PIN(4, "GPIO4"), + PINCTRL_PIN(5, "N_RSTO"), +}; + +static const char * const axp192_io_groups[] = { "GPIO0", "GPIO1", "GPIO2", + "GPIO3", "GPIO4", "N_RSTO" }; +static const char * const axp192_ldo_groups[] = { "GPIO0" }; +static const char * const axp192_pwm_groups[] = { "GPIO1", "GPIO2" }; +static const char * const axp192_adc_groups[] = { "GPIO0", "GPIO1", "GPIO2", "GPIO3" }; +static const char * const axp192_extended_io_groups[] = { "GPIO0", "GPIO1", "GPIO2" }; +static const char * const axp192_ext_chg_ctl_groups[] = { "GPIO3", "GPIO4" }; +static const char * const axp192_ldo_status_groups[] = { "N_RSTO" }; + +static const u8 axp192_output_muxvals[] = { 0, 0, 0, 1, 1, 2 }; +static const u8 axp192_input_muxvals[] = { 1, 1, 1, 2, 2, 3 }; +static const u8 axp192_ldo_muxvals[] = { 2, -1, -1, -1, -1, -1 }; +static const u8 axp192_pwm_muxvals[] = { -1, 2, 2, -1, -1, -1 }; +static const u8 axp192_adc_muxvals[] = { 4, 4, 4, 3, -1, -1 }; +static const u8 axp192_low_output_muxvals[] = { 5, 5, 5, -1, -1, -1 }; +static const u8 axp192_floating_muxvals[] = { 6, 6, 6, -1, -1, -1 }; +static const u8 axp192_ext_chg_ctl_muxvals[] = { -1, -1, -1, 0, 0, -1 }; +static const u8 axp192_ldo_status_muxvals[] = { -1, -1, -1, -1, -1, 0 }; + +static const struct axp192_pctl_function axp192_functions[AXP192_FUNCS_NB] = { + [AXP192_FUNC_OUTPUT] = { + .name = "output", + .muxvals = axp192_output_muxvals, + .groups = axp192_io_groups, + .ngroups = ARRAY_SIZE(axp192_io_groups), + }, + [AXP192_FUNC_INPUT] = { + .name = "input", + .muxvals = axp192_input_muxvals, + .groups = axp192_io_groups, + .ngroups = ARRAY_SIZE(axp192_io_groups), + }, + [AXP192_FUNC_LDO] = { + .name = "ldo", + .muxvals = axp192_ldo_muxvals, + .groups = axp192_ldo_groups, + .ngroups = ARRAY_SIZE(axp192_ldo_groups), + }, + [AXP192_FUNC_PWM] = { + .name = "pwm", + .muxvals = axp192_pwm_muxvals, + .groups = axp192_pwm_groups, + .ngroups = ARRAY_SIZE(axp192_pwm_groups), + }, + [AXP192_FUNC_ADC] = { + .name = "adc", + .muxvals = axp192_adc_muxvals, + .groups = axp192_adc_groups, + .ngroups = ARRAY_SIZE(axp192_adc_groups), + }, + [AXP192_FUNC_LOW_OUTPUT] = { + .name = "low_output", + .muxvals = axp192_low_output_muxvals, + .groups = axp192_extended_io_groups, + .ngroups = ARRAY_SIZE(axp192_extended_io_groups), + }, + [AXP192_FUNC_FLOATING] = { + .name = "floating", + .muxvals = axp192_floating_muxvals, + .groups = axp192_extended_io_groups, + .ngroups = ARRAY_SIZE(axp192_extended_io_groups), + }, + [AXP192_FUNC_EXT_CHG_CTL] = { + .name = "ext_chg_ctl", + .muxvals = axp192_ext_chg_ctl_muxvals, + .groups = axp192_ext_chg_ctl_groups, + .ngroups = ARRAY_SIZE(axp192_ext_chg_ctl_groups), + }, + [AXP192_FUNC_LDO_STATUS] = { + .name = "ldo_status", + .muxvals = axp192_ldo_status_muxvals, + .groups = axp192_ldo_groups, + .ngroups = ARRAY_SIZE(axp192_ldo_status_groups), + }, +}; + +static const struct axp192_pctl_reg_info axp192_pin_ctrl_regs[] = { + { .reg = AXP192_GPIO0_CTRL, .mask = GENMASK(2, 0) }, + { .reg = AXP192_GPIO1_CTRL, .mask = GENMASK(2, 0) }, + { .reg = AXP192_GPIO2_CTRL, .mask = GENMASK(2, 0) }, + { .reg = AXP192_GPIO4_3_CTRL, .mask = GENMASK(1, 0) }, + { .reg = AXP192_GPIO4_3_CTRL, .mask = GENMASK(3, 2) }, + { .reg = AXP192_N_RSTO_CTRL, .mask = GENMASK(7, 6) }, +}; + +static const struct axp192_pctl_reg_info axp192_pin_in_regs[] = { + { .reg = AXP192_GPIO2_0_STATE, .mask = BIT(4) }, + { .reg = AXP192_GPIO2_0_STATE, .mask = BIT(5) }, + { .reg = AXP192_GPIO2_0_STATE, .mask = BIT(6) }, + { .reg = AXP192_GPIO4_3_STATE, .mask = BIT(4) }, + { .reg = AXP192_GPIO4_3_STATE, .mask = BIT(5) }, + { .reg = AXP192_N_RSTO_CTRL, .mask = BIT(4) }, +}; + +static const struct axp192_pctl_reg_info axp192_pin_out_regs[] = { + { .reg = AXP192_GPIO2_0_STATE, .mask = BIT(0) }, + { .reg = AXP192_GPIO2_0_STATE, .mask = BIT(1) }, + { .reg = AXP192_GPIO2_0_STATE, .mask = BIT(2) }, + { .reg = AXP192_GPIO4_3_STATE, .mask = BIT(0) }, + { .reg = AXP192_GPIO4_3_STATE, .mask = BIT(1) }, + { .reg = AXP192_N_RSTO_CTRL, .mask = BIT(5) }, +}; + +static const struct axp192_pctl_reg_info axp192_pull_down_regs[] = { + { .reg = AXP192_GPIO2_0_PULL, .mask = BIT(0) }, + { .reg = AXP192_GPIO2_0_PULL, .mask = BIT(1) }, + { .reg = AXP192_GPIO2_0_PULL, .mask = BIT(2) }, + { .reg = 0, .mask = 0 /* unsupported */ }, + { .reg = 0, .mask = 0 /* unsupported */ }, + { .reg = 0, .mask = 0 /* unsupported */ }, +}; + +static const struct axp192_pctl_desc axp192_data = { + .npins = ARRAY_SIZE(axp192_pins), + .pins = axp192_pins, + .ctrl_regs = axp192_pin_ctrl_regs, + .out_regs = axp192_pin_out_regs, + .in_regs = axp192_pin_in_regs, + .pull_down_regs = axp192_pull_down_regs, + + .nfunctions = ARRAY_SIZE(axp192_functions), + .functions = axp192_functions, +}; + + +struct axp192_pctl { + struct gpio_chip chip; + struct regmap *regmap; + struct regmap_irq_chip_data *regmap_irqc; + struct pinctrl_dev *pctl_dev; + struct device *dev; + const struct axp192_pctl_desc *desc; + int *irqs; +}; + +static int axp192_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct axp192_pctl *pctl = gpiochip_get_data(chip); + const struct axp192_pctl_reg_info *reginfo = &pctl->desc->in_regs[offset]; + unsigned int val; + int ret; + + ret = regmap_read(pctl->regmap, reginfo->reg, &val); + if (ret) + return ret; + + return !!(val & reginfo->mask); +} + +static int axp192_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) +{ + struct axp192_pctl *pctl = gpiochip_get_data(chip); + const struct axp192_pctl_reg_info *reginfo = &pctl->desc->ctrl_regs[offset]; + const u8 *input_muxvals = pctl->desc->functions[AXP192_FUNC_INPUT].muxvals; + unsigned int val; + int ret; + + ret = regmap_read(pctl->regmap, reginfo->reg, &val); + if (ret) + return ret; + + if ((val & reginfo->mask) == (input_muxvals[offset] << (ffs(reginfo->mask) - 1))) + return GPIO_LINE_DIRECTION_IN; + + return GPIO_LINE_DIRECTION_OUT; +} + +static void axp192_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) +{ + struct axp192_pctl *pctl = gpiochip_get_data(chip); + const struct axp192_pctl_reg_info *reginfo = &pctl->desc->out_regs[offset]; + + regmap_update_bits(pctl->regmap, reginfo->reg, reginfo->mask, value ? reginfo->mask : 0); +} + +static int axp192_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + return pinctrl_gpio_direction_input(chip->base + offset); +} + +static int axp192_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value) +{ + chip->set(chip, offset, value); + return 0; +} + +static int axp192_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) +{ + struct axp192_pctl *pctl = gpiochip_get_data(chip); + + /* GPIO IRQs are optional */ + if (!pctl->irqs[offset]) + return 0; + + return regmap_irq_get_virq(pctl->regmap_irqc, pctl->irqs[offset]); +} + +static int axp192_pinconf_get_pull_down(struct pinctrl_dev *pctldev, unsigned int pin) +{ + struct axp192_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); + const struct axp192_pctl_reg_info *reginfo = &pctl->desc->pull_down_regs[pin]; + unsigned int val; + int ret; + + if (!reginfo->mask) + return -ENOTSUPP; + + ret = regmap_read(pctl->regmap, reginfo->reg, &val); + if (ret) + return ret; + + return !!(val & reginfo->mask); +} + +static int axp192_pinconf_set_pull_down(struct pinctrl_dev *pctldev, unsigned int pin, int value) +{ + struct axp192_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); + const struct axp192_pctl_reg_info *reginfo = &pctl->desc->pull_down_regs[pin]; + + if (!reginfo->mask) + return -ENOTSUPP; + + return regmap_update_bits(pctl->regmap, reginfo->reg, reginfo->mask, + value ? reginfo->mask : 0); +} + +static int axp192_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) +{ + enum pin_config_param param = pinconf_to_config_param(*config); + unsigned int arg = 1; + int ret; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + ret = axp192_pinconf_get_pull_down(pctldev, pin); + if (ret < 0) + return ret; + else if (ret != 0) + return -EINVAL; + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + ret = axp192_pinconf_get_pull_down(pctldev, pin); + if (ret < 0) + return ret; + else if (ret == 0) + return -EINVAL; + break; + + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + return 0; +} + +static int axp192_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + int ret; + unsigned int cfg; + + for (cfg = 0; cfg < num_configs; ++cfg) { + switch (pinconf_to_config_param(configs[cfg])) { + case PIN_CONFIG_BIAS_DISABLE: + ret = axp192_pinconf_set_pull_down(pctldev, pin, 0); + if (ret) + return ret; + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + ret = axp192_pinconf_set_pull_down(pctldev, pin, 1); + if (ret) + return ret; + break; + + default: + return -ENOTSUPP; + } + } + + return 0; +} + +static const struct pinconf_ops axp192_conf_ops = { + .is_generic = true, + .pin_config_get = axp192_pinconf_get, + .pin_config_set = axp192_pinconf_set, + .pin_config_group_get = axp192_pinconf_get, + .pin_config_group_set = axp192_pinconf_set, +}; + +static int axp192_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset, u8 config) +{ + struct axp192_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); + const struct axp192_pctl_reg_info *reginfo = &pctl->desc->ctrl_regs[offset]; + unsigned int regval = config << (ffs(reginfo->mask) - 1); + + return regmap_update_bits(pctl->regmap, reginfo->reg, reginfo->mask, regval); +} + +static int axp192_pmx_func_cnt(struct pinctrl_dev *pctldev) +{ + struct axp192_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->desc->nfunctions; +} + +static const char *axp192_pmx_func_name(struct pinctrl_dev *pctldev, unsigned int selector) +{ + struct axp192_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->desc->functions[selector].name; +} + +static int axp192_pmx_func_groups(struct pinctrl_dev *pctldev, unsigned int selector, + const char * const **groups, unsigned int *num_groups) +{ + struct axp192_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); + + *groups = pctl->desc->functions[selector].groups; + *num_groups = pctl->desc->functions[selector].ngroups; + + return 0; +} + +static int axp192_pmx_set_mux(struct pinctrl_dev *pctldev, + unsigned int function, unsigned int group) +{ + struct axp192_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); + const u8 *muxvals = pctl->desc->functions[function].muxvals; + + if (muxvals[group] == U8_MAX) + return -EINVAL; + + /* + * Switching to LDO or PWM function will enable LDO/PWM output, so it's + * better to ignore these requests and let the regulator or PWM drivers + * handle muxing to avoid interfering with them. + */ + if (function == AXP192_FUNC_LDO || function == AXP192_FUNC_PWM) + return 0; + + return axp192_pmx_set(pctldev, group, muxvals[group]); +} + +static int axp192_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset, bool input) +{ + struct axp192_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); + const u8 *muxvals = input ? pctl->desc->functions[AXP192_FUNC_INPUT].muxvals + : pctl->desc->functions[AXP192_FUNC_OUTPUT].muxvals; + + return axp192_pmx_set(pctldev, offset, muxvals[offset]); +} + +static const struct pinmux_ops axp192_pmx_ops = { + .get_functions_count = axp192_pmx_func_cnt, + .get_function_name = axp192_pmx_func_name, + .get_function_groups = axp192_pmx_func_groups, + .set_mux = axp192_pmx_set_mux, + .gpio_set_direction = axp192_pmx_gpio_set_direction, + .strict = true, +}; + +static int axp192_groups_cnt(struct pinctrl_dev *pctldev) +{ + struct axp192_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->desc->npins; +} + +static const char *axp192_group_name(struct pinctrl_dev *pctldev, unsigned int selector) +{ + struct axp192_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->desc->pins[selector].name; +} + +static int axp192_group_pins(struct pinctrl_dev *pctldev, unsigned int selector, + const unsigned int **pins, unsigned int *num_pins) +{ + struct axp192_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); + + *pins = &pctl->desc->pins[selector].number; + *num_pins = 1; + + return 0; +} + +static const struct pinctrl_ops axp192_pctrl_ops = { + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_free_map = pinconf_generic_dt_free_map, + .get_groups_count = axp192_groups_cnt, + .get_group_name = axp192_group_name, + .get_group_pins = axp192_group_pins, +}; + +static int axp192_pctl_probe(struct platform_device *pdev) +{ + struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent); + struct axp192_pctl *pctl; + struct pinctrl_desc *pctrl_desc; + int ret, i; + + pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); + if (!pctl) + return -ENOMEM; + + pctl->desc = device_get_match_data(&pdev->dev); + pctl->regmap = axp20x->regmap; + pctl->regmap_irqc = axp20x->regmap_irqc; + pctl->dev = &pdev->dev; + + pctl->chip.base = -1; + pctl->chip.can_sleep = true; + pctl->chip.request = gpiochip_generic_request; + pctl->chip.free = gpiochip_generic_free; + pctl->chip.parent = &pdev->dev; + pctl->chip.label = dev_name(&pdev->dev); + pctl->chip.owner = THIS_MODULE; + pctl->chip.get = axp192_gpio_get; + pctl->chip.get_direction = axp192_gpio_get_direction; + pctl->chip.set = axp192_gpio_set; + pctl->chip.direction_input = axp192_gpio_direction_input; + pctl->chip.direction_output = axp192_gpio_direction_output; + pctl->chip.to_irq = axp192_gpio_to_irq; + pctl->chip.ngpio = pctl->desc->npins; + + pctl->irqs = devm_kcalloc(&pdev->dev, pctl->desc->npins, sizeof(int), GFP_KERNEL); + if (!pctl->irqs) + return -ENOMEM; + + for (i = 0; i < pctl->desc->npins; ++i) { + ret = platform_get_irq_byname_optional(pdev, pctl->desc->pins[i].name); + if (ret > 0) + pctl->irqs[i] = ret; + } + + platform_set_drvdata(pdev, pctl); + + pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL); + if (!pctrl_desc) + return -ENOMEM; + + pctrl_desc->name = dev_name(&pdev->dev); + pctrl_desc->owner = THIS_MODULE; + pctrl_desc->pins = pctl->desc->pins; + pctrl_desc->npins = pctl->desc->npins; + pctrl_desc->pctlops = &axp192_pctrl_ops; + pctrl_desc->pmxops = &axp192_pmx_ops; + pctrl_desc->confops = &axp192_conf_ops; + + pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl); + if (IS_ERR(pctl->pctl_dev)) + dev_err_probe(&pdev->dev, PTR_ERR(pctl->pctl_dev), + "couldn't register pinctrl driver\n"); + + ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl); + if (ret) + dev_err_probe(&pdev->dev, ret, "Failed to register GPIO chip\n"); + + return 0; +} + +static const struct of_device_id axp192_pctl_match[] = { + { .compatible = "x-powers,axp192-gpio", .data = &axp192_data, }, + { } +}; +MODULE_DEVICE_TABLE(of, axp192_pctl_match); + +static struct platform_driver axp192_pctl_driver = { + .probe = axp192_pctl_probe, + .driver = { + .name = "axp192-gpio", + .of_match_table = axp192_pctl_match, + }, +}; +module_platform_driver(axp192_pctl_driver); + +MODULE_AUTHOR("Aidan MacDonald "); +MODULE_DESCRIPTION("AXP192 PMIC pinctrl and GPIO driver"); +MODULE_LICENSE("GPL"); From patchwork Sat Jun 18 21:40:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 582786 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5E37CCA473 for ; Sat, 18 Jun 2022 21:40:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237324AbiFRVk4 (ORCPT ); Sat, 18 Jun 2022 17:40:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43840 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236329AbiFRVk3 (ORCPT ); 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[92.40.169.177]) by smtp.gmail.com with ESMTPSA id f2-20020a17090631c200b007120e9573b4sm3847382ejf.169.2022.06.18.14.40.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jun 2022 14:40:19 -0700 (PDT) From: Aidan MacDonald To: linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, wens@csie.org, jic23@kernel.org, lee.jones@linaro.org, sre@kernel.org, broonie@kernel.org, gregkh@linuxfoundation.org, lgirdwood@gmail.com Cc: lars@metafoo.de, rafael@kernel.org, quic_gurus@quicinc.com, sebastian.reichel@collabora.com, andy.shevchenko@gmail.com, michael@walle.cc, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v3 15/16] power: axp20x_battery: Support battery status without fuel gauge Date: Sat, 18 Jun 2022 22:40:08 +0100 Message-Id: <20220618214009.2178567-16-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220618214009.2178567-1-aidanmacdonald.0x0@gmail.com> References: <20220618214009.2178567-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a "has_fg" flag to indicate that the chip has a fuel gauge. Report battery full status on chips with no fuel gauge using the battery voltage. Acked-by: Sebastian Reichel Signed-off-by: Aidan MacDonald --- drivers/power/supply/axp20x_battery.c | 34 ++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c index ce22c0a92878..f2c57fd1329b 100644 --- a/drivers/power/supply/axp20x_battery.c +++ b/drivers/power/supply/axp20x_battery.c @@ -69,6 +69,7 @@ struct axp_data { * must have AXP20X_CHRG_CTRL1_TGT_CURR+1 elements. */ const int *ccc_table; + bool has_fg; bool has_fg_valid; int (*get_max_voltage)(struct axp20x_batt_ps *batt, int *val); int (*set_max_voltage)(struct axp20x_batt_ps *batt, int val); @@ -197,7 +198,7 @@ static int axp20x_battery_get_prop(struct power_supply *psy, union power_supply_propval *val) { struct axp20x_batt_ps *axp20x_batt = power_supply_get_drvdata(psy); - int ret = 0, reg, val1; + int ret = 0, reg, val1, val2; switch (psp) { case POWER_SUPPLY_PROP_PRESENT: @@ -231,6 +232,34 @@ static int axp20x_battery_get_prop(struct power_supply *psy, return 0; } + /* + * If the chip does not have a fuel gauge, we check battery full status + * using voltage instead. + */ + if (!axp20x_batt->data->has_fg) { + ret = axp20x_batt->data->get_max_voltage(axp20x_batt, &val1); + if (ret) + return ret; + + ret = iio_read_channel_processed(axp20x_batt->batt_v, &val2); + if (ret) + return ret; + + /* IIO subsystem reports voltage in mV but we need uV */ + val2 *= 1000; + + /* + * According to the AXP192 datasheet, charging will restart if + * the battery voltage drops below V_rch = V_tgt - 0.1 V, so we + * report the battery is full if its voltage is at least V_rch. + */ + if (val2 >= val1 - 100000) + val->intval = POWER_SUPPLY_STATUS_FULL; + else + val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; + break; + } + ret = regmap_read(axp20x_batt->regmap, AXP20X_FG_RES, &val1); if (ret) return ret; @@ -553,6 +582,7 @@ static const struct power_supply_desc axp20x_batt_ps_desc = { static const struct axp_data axp209_data = { .ccc_scale = 100000, .ccc_offset = 300000, + .has_fg = true, .get_max_voltage = axp20x_battery_get_max_voltage, .set_max_voltage = axp20x_battery_set_max_voltage, }; @@ -560,6 +590,7 @@ static const struct axp_data axp209_data = { static const struct axp_data axp221_data = { .ccc_scale = 150000, .ccc_offset = 300000, + .has_fg = true, .has_fg_valid = true, .get_max_voltage = axp22x_battery_get_max_voltage, .set_max_voltage = axp22x_battery_set_max_voltage, @@ -568,6 +599,7 @@ static const struct axp_data axp221_data = { static const struct axp_data axp813_data = { .ccc_scale = 200000, .ccc_offset = 200000, + .has_fg = true, .has_fg_valid = true, .get_max_voltage = axp813_battery_get_max_voltage, .set_max_voltage = axp20x_battery_set_max_voltage,