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[35.190.215.205]) by smtp.gmail.com with ESMTPSA id j19-20020a05600c1c1300b0039c5645c60fsm30368302wms.3.2022.06.21.03.07.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jun 2022 03:07:35 -0700 (PDT) From: Lee Jones To: lee.jones@linaro.org, sjg@chromium.org, philipp.tomsich@vrull.eu, kever.yang@rock-chips.com Cc: cym@rock-chips.com, u-boot@lists.denx.de Subject: [PATCH 1/3] ram: rk3399: Fix .set_rate_index() error handling Date: Tue, 21 Jun 2022 10:07:27 +0000 Message-Id: <20220621100729.979275-1-lee.jones@linaro.org> X-Mailer: git-send-email 2.37.0.rc0.104.g0611611a94-goog MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Functions pointed to by this op pointer can return non-zero values indicating an error. Ensure any error value is propagated back up the call-chain. Signed-off-by: Lee Jones Reviewed-by: Kever Yang Tested-by: Xavier Drudis Ferran --- drivers/ram/rockchip/sdram_rk3399.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index c0a06dcaed..0af0fa9e7b 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -3005,7 +3005,9 @@ static int sdram_init(struct dram_info *dram, params->base.stride = calculate_stride(params); dram_all_config(dram, params); - dram->ops->set_rate_index(dram, params); + ret = dram->ops->set_rate_index(dram, params); + if (ret) + return ret; debug("Finish SDRAM initialization...\n"); return 0; From patchwork Tue Jun 21 10:07:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lee Jones X-Patchwork-Id: 583612 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp1481695mab; Tue, 21 Jun 2022 03:08:02 -0700 (PDT) X-Google-Smtp-Source: AGRyM1shBNoKcTZP9zq96maGs6u38TX4awb5/yI2jvfrNGwk6wP+0aApCZPZ89YtGPjDXQ+/CMAf X-Received: by 2002:a62:b514:0:b0:525:1ccd:4506 with SMTP id y20-20020a62b514000000b005251ccd4506mr12358901pfe.8.1655806081773; Tue, 21 Jun 2022 03:08:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1655806081; cv=none; d=google.com; s=arc-20160816; b=PrjRllLboVzNIXU81K10xpZ5BSjW+lv6wOsBzFLUhG5U02s/EfYpiF9w/npxfTdG5o 2zZKWjqJTp+7ZDaA2+GbFftVupbR52n1iQxOPp0gVIeMfwxuqFclONCJmn6qQsu2euy7 X3tgTfwHPyyvqY6/cC+xM4n/ClHG88MPqH55BAVnv6Nsg8Gts4BhULOiifUwfFxMnpHd 6HXVUZWp29ADfGZJA+gjV8lDwzc8IrNRSVN6egOqhx7aDFtl8LnGMdP4HO5ED8qTiOIv yPLJZXRGqx7DU8VQfQ8iNNbdtsZhtOXyjUziCvCVj0v7p0WgGT8IKv1b04ssxTIUeF8P 5Ykg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=UsIQ7csyBJwRcYc0ptEtHopXzRqx4ZG4z/ztYxIySPA=; b=UcaFQg3ElsjHIg8c0ESsyw+eofTlh0kEXSQK+a0rBUtfQCUdCm+jtLvoo81ndoc9j4 uEnMoQd4P12zr7bysuiKjiv9H7mZcGVkbB4Fov41GeZqstghUx4kqA3cPjZEjz56n+Zd 0JnafBddyNwELABdTbAmzDToV3A8g1CuFCVspGCQdOVBEjuLhg7sw3LgvcmojX9a6sLV aRZSGedqNNVcl9VKOg279qtQtLtIFmY4LhVWvBdZsZa8iDvcNe/bCB8qifF1jGVopWqm fTW2n5vx5Ug5r0/+W2v8SOw+Y2pONdKu8sZVBGGvUt+h+NQtLxeuk2KhDT/weww3IoRQ j9xA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kQSoGEGh; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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[35.190.215.205]) by smtp.gmail.com with ESMTPSA id j19-20020a05600c1c1300b0039c5645c60fsm30368302wms.3.2022.06.21.03.07.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jun 2022 03:07:36 -0700 (PDT) From: Lee Jones To: lee.jones@linaro.org, sjg@chromium.org, philipp.tomsich@vrull.eu, kever.yang@rock-chips.com Cc: cym@rock-chips.com, u-boot@lists.denx.de Subject: [PATCH 2/3] ram: rk3399: Fix faulty frequency change reports Date: Tue, 21 Jun 2022 10:07:28 +0000 Message-Id: <20220621100729.979275-2-lee.jones@linaro.org> X-Mailer: git-send-email 2.37.0.rc0.104.g0611611a94-goog In-Reply-To: <20220621100729.979275-1-lee.jones@linaro.org> References: <20220621100729.979275-1-lee.jones@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Frequency changes to 400MHz are presently reported as: lpddr4_set_rate_0: change freq to 400000000 mhz 0, 1 This is obviously wrong by 6 orders of magnitude. Ensure frequency changes are reported accurately. Signed-off-by: Lee Jones Reviewed-by: Kever Yang Tested-by: Xavier Drudis Ferran --- drivers/ram/rockchip/sdram_rk3399.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 0af0fa9e7b..34d6c93f95 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -2552,8 +2552,8 @@ static int lpddr4_set_rate(struct dram_info *dram, dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq); if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG)) - printf("%s: change freq to %d mhz %d, %d\n", __func__, - dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq, + printf("%s: change freq to %dMHz %d, %d\n", __func__, + dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq / MHz, ctl_fn, phy_fn); } From patchwork Tue Jun 21 10:07:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lee Jones X-Patchwork-Id: 583613 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp1481871mab; Tue, 21 Jun 2022 03:08:17 -0700 (PDT) X-Google-Smtp-Source: AGRyM1vwSBaHzT4MBGhzES7E3TvbZdDdcicxAFmVSfL28JWFSsucFY0vycc1BWNvN2/4PSSY+NL6 X-Received: by 2002:a05:6a00:d49:b0:525:273a:f6c5 with SMTP id n9-20020a056a000d4900b00525273af6c5mr8097083pfv.25.1655806097340; Tue, 21 Jun 2022 03:08:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1655806097; cv=none; d=google.com; s=arc-20160816; b=0xE0OeMHBXZi0QIS1DFODg/djd/boD7+3BJeQyK+lt2aKSDFF/ARakE81sFpXpHDLL TPNVAwot6dwv9yi8UdQvA7M1MHpYbbE7f4Lh5Z2vbEhIygaZy9BUIpIgkYKazKYXUEIb T5yQ3vHqdKB1C7Vmc0fIoRMxnxmDEjrC9peHNEG0oxuIZLjcDWuvznOspmP2LQg/nMkc GfomGIcmbPtkfp4wxZcaN0LChxx4t7gff3ctHH+JfmogkKQzCVMlQ6JgOX0ytLgU6Kbw WYs8Ylo+BEqYmFC6ytkns+0ebQ6Iai98+6XigU4f2VES5DSIBg8zD/b80rdtJnQmb+Lk VyVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Hm5+f+UCieW/RP46BXn2BZ6sVQc82WO3wWo6e0nQBpA=; b=DmTFDDJ5CD/3fy1bit0cSA4dSb+G+6AuFL9hVA7qzUWkcXlO0HOlIZHLcMLhsvohJy yqTDeqCX7x7PrWoHSASqFQSzJbXP3Gx2bXxCfrQoUplq+AmeCdahSMxJchuAB9AiPeVw dNordZsyrWpsodD2kjZwv94PSfodrUO71rt9Js+cGyVGhQgcBFeFySSPvhguUjD5KVQ7 AcunyJILFUBJTjlwyVAjQGdz+xJPGJxpiDry37CDMMyRvkuPubP0hOErd3Y00LS2bvwT uIf14DvEv19U4tn0j6PgzrGtnC8oCZ2Ld7I/2CkIMyWYrsbcQjTKj+sVViFeqHQWRFyA hmYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zXJiEQTA; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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[35.190.215.205]) by smtp.gmail.com with ESMTPSA id j19-20020a05600c1c1300b0039c5645c60fsm30368302wms.3.2022.06.21.03.07.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jun 2022 03:07:37 -0700 (PDT) From: Lee Jones To: lee.jones@linaro.org, sjg@chromium.org, philipp.tomsich@vrull.eu, kever.yang@rock-chips.com Cc: cym@rock-chips.com, u-boot@lists.denx.de Subject: [PATCH 3/3] ram: rk3399: Conduct memory training at 400MHz Date: Tue, 21 Jun 2022 10:07:29 +0000 Message-Id: <20220621100729.979275-3-lee.jones@linaro.org> X-Mailer: git-send-email 2.37.0.rc0.104.g0611611a94-goog In-Reply-To: <20220621100729.979275-1-lee.jones@linaro.org> References: <20220621100729.979275-1-lee.jones@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Currently the default initialisation frequency is 50MHz. Although this does appear to be suitable for some LPDDR4 RAM chips, training at this low frequency has been seen to cause Column errors, leading to Capacity check errors on others. Here we force RAM initialisation to happen at 400MHz before ramping up to the final value running value of 800MHz after everything has been successfully configured. Link: https://lore.kernel.org/u-boot/Yo4v3jUeHXTovjOH@google.com/ Suggested-by: YouMin Chen Signed-off-by: Lee Jones Reviewed-by: Kever Yang Tested-by: Xavier Drudis Ferran --- drivers/ram/rockchip/sdram_rk3399.c | 36 +++++++++++++++++------------ 1 file changed, 21 insertions(+), 15 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 34d6c93f95..b05c5925d5 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -85,7 +85,7 @@ struct sdram_rk3399_ops { int (*data_training_first)(struct dram_info *dram, u32 channel, u8 rank, struct rk3399_sdram_params *sdram); int (*set_rate_index)(struct dram_info *dram, - struct rk3399_sdram_params *params); + struct rk3399_sdram_params *params, u32 ctl_fn); void (*modify_param)(const struct chan_info *chan, struct rk3399_sdram_params *params); struct rk3399_sdram_params * @@ -1644,7 +1644,8 @@ static int data_training_first(struct dram_info *dram, u32 channel, u8 rank, } static int switch_to_phy_index1(struct dram_info *dram, - struct rk3399_sdram_params *params) + struct rk3399_sdram_params *params, + u32 unused) { u32 channel; u32 *denali_phy; @@ -2539,26 +2540,25 @@ static int lpddr4_set_ctl(struct dram_info *dram, } static int lpddr4_set_rate(struct dram_info *dram, - struct rk3399_sdram_params *params) + struct rk3399_sdram_params *params, + u32 ctl_fn) { - u32 ctl_fn; u32 phy_fn; - for (ctl_fn = 0; ctl_fn < 2; ctl_fn++) { - phy_fn = lpddr4_get_phy_fn(params, ctl_fn); + phy_fn = lpddr4_get_phy_fn(params, ctl_fn); - lpddr4_set_phy(dram, params, phy_fn, &dfs_cfgs_lpddr4[ctl_fn]); - lpddr4_set_ctl(dram, params, ctl_fn, - dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq); + lpddr4_set_phy(dram, params, phy_fn, &dfs_cfgs_lpddr4[ctl_fn]); + lpddr4_set_ctl(dram, params, ctl_fn, + dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq); - if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG)) - printf("%s: change freq to %dMHz %d, %d\n", __func__, - dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq / MHz, - ctl_fn, phy_fn); - } + if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG)) + printf("%s: change freq to %dMHz %d, %d\n", __func__, + dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq / MHz, + ctl_fn, phy_fn); return 0; } + #endif /* CONFIG_RAM_RK3399_LPDDR4 */ /* CS0,n=1 @@ -2955,6 +2955,12 @@ static int sdram_init(struct dram_info *dram, params->ch[ch].cap_info.rank = rank; } +#if defined(CONFIG_RAM_RK3399_LPDDR4) + /* LPDDR4 needs to be trained at 400MHz */ + lpddr4_set_rate(dram, params, 0); + params->base.ddr_freq = dfs_cfgs_lpddr4[0].base.ddr_freq / MHz; +#endif + params->base.num_channels = 0; for (channel = 0; channel < 2; channel++) { const struct chan_info *chan = &dram->chan[channel]; @@ -3005,7 +3011,7 @@ static int sdram_init(struct dram_info *dram, params->base.stride = calculate_stride(params); dram_all_config(dram, params); - ret = dram->ops->set_rate_index(dram, params); + ret = dram->ops->set_rate_index(dram, params, 1); if (ret) return ret;