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Fri, 24 Jun 2022 05:05:46 -0700 Envelope-to: git@amd.com, michal.simek@amd.com, linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Received: from [172.23.64.2] (port=47730 helo=xhdvnc102.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1o4i4H-00056G-EJ; Fri, 24 Jun 2022 05:05:46 -0700 Received: by xhdvnc102.xilinx.com (Postfix, from userid 90444) id 62D65104545; Fri, 24 Jun 2022 17:35:33 +0530 (IST) From: Manikanta Guntupalli To: , , , , , CC: Raviteja Narayanam , Manikanta Guntupalli Subject: [PATCH 01/12] i2c: xiic: Add standard mode support for > 255 byte read transfers Date: Fri, 24 Jun 2022 17:35:16 +0530 Message-ID: <1656072327-13628-2-git-send-email-manikanta.guntupalli@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1656072327-13628-1-git-send-email-manikanta.guntupalli@xilinx.com> References: <1656072327-13628-1-git-send-email-manikanta.guntupalli@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 243351e8-3dd0-43a9-c5ec-08da55d9df23 X-MS-TrafficTypeDiagnostic: DM5PR02MB3292:EE_ X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SFV:NSPM; H:xsj-pvapexch02.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(13230016)(4636009)(396003)(346002)(136003)(39860400002)(376002)(40470700004)(36840700001)(46966006)(110136005)(316002)(42186006)(54906003)(47076005)(70206006)(6266002)(70586007)(8676002)(41300700001)(336012)(2616005)(107886003)(6666004)(426003)(186003)(4326008)(478600001)(26005)(83380400001)(40460700003)(8936002)(7636003)(82740400003)(356005)(40480700001)(5660300002)(82310400005)(2906002)(30864003)(36756003)(44832011)(36860700001)(102446001)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2022 12:05:46.5335 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 243351e8-3dd0-43a9-c5ec-08da55d9df23 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0056.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR02MB3292 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Raviteja Narayanam Added standard mode for AXI I2C controller to enable read transfers of size more than 255 bytes. The driver selects standard mode in the following scenarios. 1. If a single message request comes from user space, requesting a read of more than 255 bytes 2. If a message set request comes from user space consisting of many messages and if any one of them is a read operation, irrespective of the size of transfer. (This is done because it is observed that repeated start operation is not happening in dynamic mode read as expected in a message set request from user space.) Signed-off-by: Raviteja Narayanam Signed-off-by: Manikanta Guntupalli --- drivers/i2c/busses/i2c-xiic.c | 326 +++++++++++++++++++++++++++++----- 1 file changed, 280 insertions(+), 46 deletions(-) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index 9a1c3f8b7048..fb2443623844 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -60,6 +60,8 @@ enum xiic_endian { * @clk: Pointer to AXI4-lite input clock * @state: See STATE_ * @singlemaster: Indicates bus is single master + * @dynamic: Mode of controller + * @repeated_start: Repeated start operation */ struct xiic_i2c { struct device *dev; @@ -76,6 +78,8 @@ struct xiic_i2c { struct clk *clk; enum xilinx_i2c_state state; bool singlemaster; + bool dynamic; + bool repeated_start; }; #define XIIC_MSB_OFFSET 0 @@ -143,6 +147,9 @@ struct xiic_i2c { #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */ #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */ +/* Dynamic mode constants */ +#define MAX_READ_LENGTH_DYNAMIC 255 /* Max length for dynamic read */ + /* * The following constants define the register offsets for the Interrupt * registers. There are some holes in the memory map for reserved addresses @@ -316,13 +323,14 @@ static void xiic_deinit(struct xiic_i2c *i2c) static void xiic_read_rx(struct xiic_i2c *i2c) { - u8 bytes_in_fifo; + u8 bytes_in_fifo, cr = 0, bytes_to_read = 0; + u32 bytes_rem = 0; int i; bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; dev_dbg(i2c->adap.dev.parent, - "%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n", + "%s entry, bytes in fifo: %d, rem: %d, SR: 0x%x, CR: 0x%x\n", __func__, bytes_in_fifo, xiic_rx_space(i2c), xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); @@ -330,13 +338,52 @@ static void xiic_read_rx(struct xiic_i2c *i2c) if (bytes_in_fifo > xiic_rx_space(i2c)) bytes_in_fifo = xiic_rx_space(i2c); - for (i = 0; i < bytes_in_fifo; i++) + bytes_to_read = bytes_in_fifo; + + if (!i2c->dynamic) { + bytes_rem = xiic_rx_space(i2c) - bytes_in_fifo; + + if (bytes_rem > IIC_RX_FIFO_DEPTH) { + bytes_to_read = bytes_in_fifo; + } else if (bytes_rem > 1) { + bytes_to_read = bytes_rem - 1; + } else if (bytes_rem == 1) { + bytes_to_read = 1; + /* Set NACK in CR to indicate slave transmitter */ + cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); + xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr | + XIIC_CR_NO_ACK_MASK); + } else if (bytes_rem == 0) { + bytes_to_read = bytes_in_fifo; + + /* Generate stop on the bus if it is last message */ + if (i2c->nmsgs == 1) { + cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); + xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & + ~XIIC_CR_MSMS_MASK); + } + + /* Make TXACK=0, clean up for next transaction */ + cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); + xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & + ~XIIC_CR_NO_ACK_MASK); + } + } + + /* Read the fifo */ + for (i = 0; i < bytes_to_read; i++) { i2c->rx_msg->buf[i2c->rx_pos++] = xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); + } + + if (i2c->dynamic) { + u8 bytes; - xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, - (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ? - IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1); + /* Receive remaining bytes if less than fifo depth */ + bytes = min_t(u8, xiic_rx_space(i2c), IIC_RX_FIFO_DEPTH); + bytes--; + xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes); + } } static int xiic_tx_fifo_space(struct xiic_i2c *i2c) @@ -367,6 +414,56 @@ static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) } } +static void xiic_std_fill_tx_fifo(struct xiic_i2c *i2c) +{ + u8 fifo_space = xiic_tx_fifo_space(i2c); + u16 data = 0; + int len = xiic_tx_space(i2c); + + dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", + __func__, len, fifo_space); + + if (len > fifo_space) + len = fifo_space; + else if (len && !(i2c->repeated_start)) + len--; + + while (len--) { + data = i2c->tx_msg->buf[i2c->tx_pos++]; + xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); + } +} + +static void xiic_send_tx(struct xiic_i2c *i2c) +{ + dev_dbg(i2c->adap.dev.parent, + "%s entry, rem: %d, SR: 0x%x, CR: 0x%x\n", + __func__, xiic_tx_space(i2c), + xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), + xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); + + if (xiic_tx_space(i2c) > 1) { + xiic_std_fill_tx_fifo(i2c); + return; + } + + if ((xiic_tx_space(i2c) == 1)) { + u16 data; + + if (i2c->nmsgs == 1) { + u8 cr; + + /* Write to CR to stop */ + cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); + xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & + ~XIIC_CR_MSMS_MASK); + } + /* Send last byte */ + data = i2c->tx_msg->buf[i2c->tx_pos++]; + xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); + } +} + static void xiic_wakeup(struct xiic_i2c *i2c, int code) { i2c->tx_msg = NULL; @@ -401,7 +498,9 @@ static irqreturn_t xiic_process(int irq, void *dev_id) dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n", __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), i2c->tx_msg, i2c->nmsgs); - + dev_dbg(i2c->adap.dev.parent, "%s, ISR: 0x%x, CR: 0x%x\n", + __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), + xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); /* Service requesting interrupt */ if ((pend & XIIC_INTR_ARB_LOST_MASK) || @@ -480,7 +579,10 @@ static irqreturn_t xiic_process(int irq, void *dev_id) goto out; } - xiic_fill_tx_fifo(i2c); + if (i2c->dynamic) + xiic_fill_tx_fifo(i2c); + else + xiic_send_tx(i2c); /* current message sent and there is space in the fifo */ if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) { @@ -579,31 +681,99 @@ static int xiic_busy(struct xiic_i2c *i2c) static void xiic_start_recv(struct xiic_i2c *i2c) { u16 rx_watermark; + u8 cr = 0, rfd_set = 0; struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; + unsigned long flags; - /* Clear and enable Rx full interrupt. */ - xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK); + dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", + __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), + xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); - /* we want to get all but last byte, because the TX_ERROR IRQ is used - * to inidicate error ACK on the address, and negative ack on the last - * received byte, so to not mix them receive all but last. - * In the case where there is only one byte to receive - * we can check if ERROR and RX full is set at the same time - */ - rx_watermark = msg->len; - if (rx_watermark > IIC_RX_FIFO_DEPTH) - rx_watermark = IIC_RX_FIFO_DEPTH; - xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, (u8)(rx_watermark - 1)); + /* Disable Tx interrupts */ + xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK | XIIC_INTR_TX_EMPTY_MASK); - if (!(msg->flags & I2C_M_NOSTART)) - /* write the address */ - xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, - i2c_8bit_addr_from_msg(msg) | XIIC_TX_DYN_START_MASK); - xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); + if (i2c->dynamic) { + u8 bytes; + u16 val; - xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, - msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0)); + /* Clear and enable Rx full interrupt. */ + xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | + XIIC_INTR_TX_ERROR_MASK); + + /* + * We want to get all but last byte, because the TX_ERROR IRQ + * is used to indicate error ACK on the address, and + * negative ack on the last received byte, so to not mix + * them receive all but last. + * In the case where there is only one byte to receive + * we can check if ERROR and RX full is set at the same time + */ + rx_watermark = msg->len; + bytes = min_t(u8, rx_watermark, IIC_RX_FIFO_DEPTH); + bytes--; + + xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes); + + local_irq_save(flags); + if (!(msg->flags & I2C_M_NOSTART)) + /* write the address */ + xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, + i2c_8bit_addr_from_msg(msg) | + XIIC_TX_DYN_START_MASK); + + xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); + + /* If last message, include dynamic stop bit with length */ + val = (i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0; + val |= msg->len; + + xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, val); + local_irq_restore(flags); + } else { + cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); + + /* Set Receive fifo depth */ + rx_watermark = msg->len; + if (rx_watermark > IIC_RX_FIFO_DEPTH) { + rfd_set = IIC_RX_FIFO_DEPTH - 1; + } else if ((rx_watermark == 1) || (rx_watermark == 0)) { + rfd_set = rx_watermark - 1; + /* Handle single byte transfer separately */ + cr |= XIIC_CR_NO_ACK_MASK; + } else { + rfd_set = rx_watermark - 2; + } + /* Check if RSTA should be set */ + if (cr & XIIC_CR_MSMS_MASK) { + i2c->repeated_start = true; + /* Already a master, RSTA should be set */ + xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | + XIIC_CR_REPEATED_START_MASK) & + ~(XIIC_CR_DIR_IS_TX_MASK)); + } + + xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set); + + /* Clear and enable Rx full and transmit complete interrupts */ + xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | + XIIC_INTR_TX_ERROR_MASK); + + /* Write the address */ + xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, + i2c_8bit_addr_from_msg(msg)); + + /* Write to Control Register,to start transaction in Rx mode */ + if ((cr & XIIC_CR_MSMS_MASK) == 0) { + i2c->repeated_start = false; + xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | + XIIC_CR_MSMS_MASK) + & ~(XIIC_CR_DIR_IS_TX_MASK)); + } + dev_dbg(i2c->adap.dev.parent, "%s end, ISR: 0x%x, CR: 0x%x\n", + __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), + xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); + } if (i2c->nmsgs == 1) /* very last, enable bus not busy as well */ @@ -611,10 +781,15 @@ static void xiic_start_recv(struct xiic_i2c *i2c) /* the message is tx:ed */ i2c->tx_pos = msg->len; + + /* Enable interrupts */ + xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); } static void xiic_start_send(struct xiic_i2c *i2c) { + u8 cr = 0; + u16 data; struct i2c_msg *msg = i2c->tx_msg; dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d", @@ -623,24 +798,61 @@ static void xiic_start_send(struct xiic_i2c *i2c) __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); - if (!(msg->flags & I2C_M_NOSTART)) { - /* write the address */ - u16 data = i2c_8bit_addr_from_msg(msg) | - XIIC_TX_DYN_START_MASK; - if ((i2c->nmsgs == 1) && msg->len == 0) - /* no data and last message -> add STOP */ - data |= XIIC_TX_DYN_STOP_MASK; + if (i2c->dynamic) { + if (!(msg->flags & I2C_M_NOSTART)) { + /* write the address */ + data = i2c_8bit_addr_from_msg(msg) | + XIIC_TX_DYN_START_MASK; + + if (i2c->nmsgs == 1 && msg->len == 0) + /* no data and last message -> add STOP */ + data |= XIIC_TX_DYN_STOP_MASK; + + xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); + } + + /* Clear any pending Tx empty, Tx Error and then enable them */ + xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | + XIIC_INTR_TX_ERROR_MASK | + XIIC_INTR_BNB_MASK | + ((i2c->nmsgs > 1 || xiic_tx_space(i2c)) ? + XIIC_INTR_TX_HALF_MASK : 0)); + + xiic_fill_tx_fifo(i2c); + } else { + /* Check if RSTA should be set */ + cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); + if (cr & XIIC_CR_MSMS_MASK) { + i2c->repeated_start = true; + /* Already a master, RSTA should be set */ + xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | + XIIC_CR_REPEATED_START_MASK | + XIIC_CR_DIR_IS_TX_MASK) & + ~(XIIC_CR_NO_ACK_MASK)); + } + /* Write address to FIFO */ + data = i2c_8bit_addr_from_msg(msg); xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); - } - /* Clear any pending Tx empty, Tx Error and then enable them. */ - xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK | - XIIC_INTR_BNB_MASK | - ((i2c->nmsgs > 1 || xiic_tx_space(i2c)) ? - XIIC_INTR_TX_HALF_MASK : 0)); + /* Fill fifo */ + xiic_std_fill_tx_fifo(i2c); + + if ((cr & XIIC_CR_MSMS_MASK) == 0) { + i2c->repeated_start = false; + + /* Start Tx by writing to CR */ + cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); + xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr | + XIIC_CR_MSMS_MASK | + XIIC_CR_DIR_IS_TX_MASK); + } - xiic_fill_tx_fifo(i2c); + /* Clear any pending Tx empty, Tx Error and then enable them */ + xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | + XIIC_INTR_TX_ERROR_MASK | + XIIC_INTR_BNB_MASK); + } } static void __xiic_start_xfer(struct xiic_i2c *i2c) @@ -701,6 +913,33 @@ static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) if (err < 0) return err; + /* Decide standard mode or Dynamic mode */ + i2c->dynamic = true; + + /* + * If number of messages is 1 and read length is > 255 bytes, + * enter standard mode + */ + + if (i2c->nmsgs == 1 && (i2c->tx_msg->flags & I2C_M_RD) && + i2c->tx_msg->len > MAX_READ_LENGTH_DYNAMIC) { + i2c->dynamic = false; + } else if (i2c->nmsgs > 1) { + int count; + + /* + * If number of messages is more than 1 and one of them is + * a read message, enter standard mode. Since repeated start + * operation in dynamic mode read is not happenning + */ + for (count = 0; count < i2c->nmsgs; count++) { + if (i2c->tx_msg[count].flags & I2C_M_RD) { + i2c->dynamic = false; + break; + } + } + } + err = xiic_start_xfer(i2c, msgs, num); if (err < 0) { dev_err(adap->dev.parent, "Error xiic_start_xfer\n"); @@ -737,15 +976,10 @@ static const struct i2c_algorithm xiic_algorithm = { .functionality = xiic_func, }; -static const struct i2c_adapter_quirks xiic_quirks = { - .max_read_len = 255, -}; - static const struct i2c_adapter xiic_adapter = { .owner = THIS_MODULE, .class = I2C_CLASS_DEPRECATED, .algo = &xiic_algorithm, - .quirks = &xiic_quirks, }; static int xiic_i2c_probe(struct platform_device *pdev) From patchwork Fri Jun 24 12:05:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Guntupalli X-Patchwork-Id: 585006 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5AB6FC43334 for ; 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SFV:NSPM; H:xsj-pvapexch01.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(13230016)(4636009)(396003)(39860400002)(346002)(136003)(376002)(40470700004)(36840700001)(46966006)(47076005)(54906003)(36860700001)(186003)(336012)(110136005)(8676002)(107886003)(40460700003)(70586007)(82740400003)(36756003)(316002)(426003)(2616005)(4326008)(42186006)(6666004)(40480700001)(6266002)(44832011)(41300700001)(26005)(83380400001)(8936002)(7636003)(478600001)(82310400005)(356005)(70206006)(2906002)(5660300002)(102446001)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2022 12:05:59.9290 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8a84927d-940c-4e5f-e574-08da55d9e726 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT053.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR02MB5278 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Raviteja Narayanam To maintain backward compatibility the default transfer mode is dynamic mode. Enter standard mode only when the size of read transfer is > 255 bytes. Signed-off-by: Raviteja Narayanam Signed-off-by: Manikanta Guntupalli --- drivers/i2c/busses/i2c-xiic.c | 29 +++++++---------------------- 1 file changed, 7 insertions(+), 22 deletions(-) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index fb2443623844..c8b68176427c 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -904,7 +904,7 @@ static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num) static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) { struct xiic_i2c *i2c = i2c_get_adapdata(adap); - int err; + int err, count; dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)); @@ -916,27 +916,12 @@ static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) /* Decide standard mode or Dynamic mode */ i2c->dynamic = true; - /* - * If number of messages is 1 and read length is > 255 bytes, - * enter standard mode - */ - - if (i2c->nmsgs == 1 && (i2c->tx_msg->flags & I2C_M_RD) && - i2c->tx_msg->len > MAX_READ_LENGTH_DYNAMIC) { - i2c->dynamic = false; - } else if (i2c->nmsgs > 1) { - int count; - - /* - * If number of messages is more than 1 and one of them is - * a read message, enter standard mode. Since repeated start - * operation in dynamic mode read is not happenning - */ - for (count = 0; count < i2c->nmsgs; count++) { - if (i2c->tx_msg[count].flags & I2C_M_RD) { - i2c->dynamic = false; - break; - } + /* Enter standard mode only when read length is > 255 bytes */ + for (count = 0; count < i2c->nmsgs; count++) { + if ((i2c->tx_msg[count].flags & I2C_M_RD) && + i2c->tx_msg[count].len > MAX_READ_LENGTH_DYNAMIC) { + i2c->dynamic = false; + break; } } From patchwork Fri Jun 24 12:05:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Guntupalli X-Patchwork-Id: 584770 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94E2BC43334 for ; Fri, 24 Jun 2022 12:06:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229615AbiFXMGR (ORCPT ); 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SFV:NSPM; H:xsj-pvapexch01.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(13230016)(4636009)(376002)(136003)(39860400002)(396003)(346002)(46966006)(36840700001)(40470700004)(82310400005)(40480700001)(7636003)(110136005)(83380400001)(8676002)(107886003)(82740400003)(36860700001)(2616005)(42186006)(336012)(6666004)(186003)(478600001)(356005)(47076005)(70206006)(2906002)(6266002)(8936002)(54906003)(5660300002)(44832011)(316002)(426003)(70586007)(36756003)(41300700001)(40460700003)(4326008)(26005)(102446001)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2022 12:06:13.4592 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fef2375c-ccc5-4728-bcbe-08da55d9ef45 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT053.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR02MB8876 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Raviteja Narayanam When a combined message request comes from user space, the controller has to initiate repeated start sequence. In standard mode, this repeated start sequence is corrupted if there is still data in the Tx FIFO. So, always make sure that all the bytes are completely transmitted out of the FIFO by waiting for TXEMPTY, if the previous message is of Tx type. Signed-off-by: Raviteja Narayanam Signed-off-by: Manikanta Guntupalli --- drivers/i2c/busses/i2c-xiic.c | 54 +++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index c8b68176427c..2d5214f1ba03 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -62,6 +62,7 @@ enum xiic_endian { * @singlemaster: Indicates bus is single master * @dynamic: Mode of controller * @repeated_start: Repeated start operation + * @prev_msg_tx: Previous message is Tx */ struct xiic_i2c { struct device *dev; @@ -80,6 +81,7 @@ struct xiic_i2c { bool singlemaster; bool dynamic; bool repeated_start; + bool prev_msg_tx; }; #define XIIC_MSB_OFFSET 0 @@ -282,6 +284,24 @@ static int xiic_clear_rx_fifo(struct xiic_i2c *i2c) return 0; } +static int xiic_wait_tx_empty(struct xiic_i2c *i2c) +{ + u8 isr; + unsigned long timeout; + + timeout = jiffies + XIIC_I2C_TIMEOUT; + for (isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); + !(isr & XIIC_INTR_TX_EMPTY_MASK); + isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET)) { + if (time_after(jiffies, timeout)) { + dev_err(i2c->dev, "Timeout waiting at Tx empty\n"); + return -ETIMEDOUT; + } + } + + return 0; +} + static int xiic_reinit(struct xiic_i2c *i2c) { int ret; @@ -731,6 +751,20 @@ static void xiic_start_recv(struct xiic_i2c *i2c) xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, val); local_irq_restore(flags); } else { + /* + * If previous message is Tx, make sure that Tx FIFO is empty + * before starting a new transfer as the repeated start in + * standard mode can corrupt the transaction if there are + * still bytes to be transmitted in FIFO + */ + if (i2c->prev_msg_tx) { + int status; + + status = xiic_wait_tx_empty(i2c); + if (status) + return; + } + cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); /* Set Receive fifo depth */ @@ -784,6 +818,8 @@ static void xiic_start_recv(struct xiic_i2c *i2c) /* Enable interrupts */ xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); + + i2c->prev_msg_tx = false; } static void xiic_start_send(struct xiic_i2c *i2c) @@ -820,6 +856,20 @@ static void xiic_start_send(struct xiic_i2c *i2c) xiic_fill_tx_fifo(i2c); } else { + /* + * If previous message is Tx, make sure that Tx FIFO is empty + * before starting a new transfer as the repeated start in + * standard mode can corrupt the transaction if there are + * still bytes to be transmitted in FIFO + */ + if (i2c->prev_msg_tx) { + int status; + + status = xiic_wait_tx_empty(i2c); + if (status) + return; + } + /* Check if RSTA should be set */ cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); if (cr & XIIC_CR_MSMS_MASK) { @@ -853,6 +903,7 @@ static void xiic_start_send(struct xiic_i2c *i2c) XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_BNB_MASK); } + i2c->prev_msg_tx = true; } static void __xiic_start_xfer(struct xiic_i2c *i2c) @@ -916,6 +967,9 @@ static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) /* Decide standard mode or Dynamic mode */ i2c->dynamic = true; + /* Initialize prev message type */ + i2c->prev_msg_tx = false; + /* Enter standard mode only when read length is > 255 bytes */ for (count = 0; count < i2c->nmsgs; count++) { if ((i2c->tx_msg[count].flags & I2C_M_RD) && From patchwork Fri Jun 24 12:05:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Guntupalli X-Patchwork-Id: 584769 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D1EBC433EF for ; Fri, 24 Jun 2022 12:06:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231344AbiFXMGz (ORCPT ); Fri, 24 Jun 2022 08:06:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231847AbiFXMGx (ORCPT ); Fri, 24 Jun 2022 08:06:53 -0400 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2048.outbound.protection.outlook.com [40.107.93.48]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BCBC87FD1F; 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SFV:NSPM; H:xsj-pvapexch01.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(13230016)(4636009)(396003)(39860400002)(376002)(346002)(136003)(40470700004)(46966006)(36840700001)(8936002)(36860700001)(41300700001)(2906002)(40480700001)(110136005)(42186006)(70206006)(5660300002)(8676002)(70586007)(316002)(107886003)(478600001)(186003)(4326008)(2616005)(356005)(6266002)(7636003)(26005)(426003)(54906003)(336012)(6666004)(82740400003)(82310400005)(40460700003)(44832011)(36756003)(47076005)(102446001)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2022 12:06:47.3527 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fba88ecf-ba2c-4f8b-2f85-08da55da036b X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT023.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1PR02MB3853 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Raviteja Narayanam If the tx_half_empty interrupt comes first instead of tx_empty, STOP bit is generated even before all the bytes are transmitted out on the bus. STOP bit should be sent only after all the bytes in the FIFO are transmitted out of the FIFO. So wait until FIFO is empty before sending the STOP bit. Signed-off-by: Raviteja Narayanam Signed-off-by: Manikanta Guntupalli --- drivers/i2c/busses/i2c-xiic.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index 2d5214f1ba03..9c3266ac209e 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -472,6 +472,12 @@ static void xiic_send_tx(struct xiic_i2c *i2c) if (i2c->nmsgs == 1) { u8 cr; + int status; + + /* Wait till FIFO is empty so STOP is sent last */ + status = xiic_wait_tx_empty(i2c); + if (status) + return; /* Write to CR to stop */ cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); From patchwork Fri Jun 24 12:05:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Guntupalli X-Patchwork-Id: 585005 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2724DC43334 for ; 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SFV:NSPM; H:xsj-pvapexch02.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(13230016)(4636009)(39860400002)(376002)(396003)(346002)(136003)(46966006)(40470700004)(36840700001)(44832011)(7636003)(316002)(2906002)(54906003)(70586007)(8936002)(110136005)(8676002)(356005)(5660300002)(70206006)(40460700003)(82740400003)(4326008)(478600001)(83380400001)(41300700001)(26005)(6266002)(42186006)(40480700001)(47076005)(2616005)(107886003)(6666004)(186003)(82310400005)(36860700001)(426003)(336012)(36756003)(102446001)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2022 12:06:39.5971 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bdbe2081-03e0-405d-61ae-08da55d9fec9 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0025.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR02MB2810 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Raviteja Narayanam Remove the redundant repeated_start variable as it is setup at different places, and read at only one place which can be decided by 'nmsgs' variable alone. Signed-off-by: Raviteja Narayanam Signed-off-by: Manikanta Guntupalli --- drivers/i2c/busses/i2c-xiic.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index 9c3266ac209e..3debb44608cf 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -61,7 +61,6 @@ enum xiic_endian { * @state: See STATE_ * @singlemaster: Indicates bus is single master * @dynamic: Mode of controller - * @repeated_start: Repeated start operation * @prev_msg_tx: Previous message is Tx */ struct xiic_i2c { @@ -80,7 +79,6 @@ struct xiic_i2c { enum xilinx_i2c_state state; bool singlemaster; bool dynamic; - bool repeated_start; bool prev_msg_tx; }; @@ -445,7 +443,7 @@ static void xiic_std_fill_tx_fifo(struct xiic_i2c *i2c) if (len > fifo_space) len = fifo_space; - else if (len && !(i2c->repeated_start)) + else if (len && !(i2c->nmsgs > 1)) len--; while (len--) { @@ -786,7 +784,6 @@ static void xiic_start_recv(struct xiic_i2c *i2c) } /* Check if RSTA should be set */ if (cr & XIIC_CR_MSMS_MASK) { - i2c->repeated_start = true; /* Already a master, RSTA should be set */ xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | XIIC_CR_REPEATED_START_MASK) & @@ -805,7 +802,6 @@ static void xiic_start_recv(struct xiic_i2c *i2c) /* Write to Control Register,to start transaction in Rx mode */ if ((cr & XIIC_CR_MSMS_MASK) == 0) { - i2c->repeated_start = false; xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | XIIC_CR_MSMS_MASK) & ~(XIIC_CR_DIR_IS_TX_MASK)); @@ -879,7 +875,6 @@ static void xiic_start_send(struct xiic_i2c *i2c) /* Check if RSTA should be set */ cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); if (cr & XIIC_CR_MSMS_MASK) { - i2c->repeated_start = true; /* Already a master, RSTA should be set */ xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | XIIC_CR_REPEATED_START_MASK | @@ -895,7 +890,6 @@ static void xiic_start_send(struct xiic_i2c *i2c) xiic_std_fill_tx_fifo(i2c); if ((cr & XIIC_CR_MSMS_MASK) == 0) { - i2c->repeated_start = false; /* Start Tx by writing to CR */ cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); From patchwork Fri Jun 24 12:05:21 2022 Content-Type: text/plain; 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Fri, 24 Jun 2022 05:06:52 -0700 Envelope-to: git@amd.com, michal.simek@amd.com, linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Received: from [172.23.64.2] (port=47735 helo=xhdvnc102.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1o4i5L-0005Mt-OS; Fri, 24 Jun 2022 05:06:52 -0700 Received: by xhdvnc102.xilinx.com (Postfix, from userid 90444) id 53B9E104545; Fri, 24 Jun 2022 17:35:48 +0530 (IST) From: Manikanta Guntupalli To: , , , , , CC: Raviteja Narayanam , Manikanta Guntupalli Subject: [PATCH 06/12] i2c: xiic: Add smbus_block_read functionality Date: Fri, 24 Jun 2022 17:35:21 +0530 Message-ID: <1656072327-13628-7-git-send-email-manikanta.guntupalli@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1656072327-13628-1-git-send-email-manikanta.guntupalli@xilinx.com> References: <1656072327-13628-1-git-send-email-manikanta.guntupalli@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3e0ad034-d185-405d-1831-08da55da0696 X-MS-TrafficTypeDiagnostic: BL0PR02MB4963:EE_ X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch02.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(13230016)(4636009)(346002)(39860400002)(136003)(396003)(376002)(36840700001)(46966006)(40470700004)(40480700001)(36756003)(2906002)(41300700001)(70206006)(83380400001)(40460700003)(44832011)(8936002)(316002)(70586007)(54906003)(42186006)(110136005)(5660300002)(478600001)(2616005)(47076005)(4326008)(336012)(26005)(107886003)(8676002)(82310400005)(6666004)(82740400003)(7636003)(36860700001)(356005)(43170500006)(6266002)(186003)(426003)(102446001)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2022 12:06:52.7296 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3e0ad034-d185-405d-1831-08da55da0696 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0049.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR02MB4963 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Raviteja Narayanam smbus_block_read is added to xiic driver to read from few sensors which support this command. Since the number of bytes to read is not known prior to transfer, we are using xiic standard mode for low level control of IP. Signed-off-by: Raviteja Narayanam Signed-off-by: Manikanta Guntupalli Tested-by: Krzysztof Adamski --- drivers/i2c/busses/i2c-xiic.c | 82 ++++++++++++++++++++++++++++++++--- 1 file changed, 76 insertions(+), 6 deletions(-) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index 3debb44608cf..57ede62de67d 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -62,6 +62,7 @@ enum xiic_endian { * @singlemaster: Indicates bus is single master * @dynamic: Mode of controller * @prev_msg_tx: Previous message is Tx + * @smbus_block_read: Flag to handle block read */ struct xiic_i2c { struct device *dev; @@ -80,6 +81,7 @@ struct xiic_i2c { bool singlemaster; bool dynamic; bool prev_msg_tx; + bool smbus_block_read; }; #define XIIC_MSB_OFFSET 0 @@ -339,6 +341,54 @@ static void xiic_deinit(struct xiic_i2c *i2c) xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK); } +static void xiic_smbus_block_read_setup(struct xiic_i2c *i2c) +{ + u8 rxmsg_len; + u8 rfd_set = 0; + + /* + * Clear the I2C_M_RECV_LEN flag to avoid setting + * message length again + */ + i2c->rx_msg->flags &= ~I2C_M_RECV_LEN; + + /* Set smbus_block_read flag to identify in isr */ + i2c->smbus_block_read = true; + + /* Read byte from rx fifo and set message length */ + rxmsg_len = xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); + + i2c->rx_msg->buf[i2c->rx_pos++] = rxmsg_len; + + /* Check if received length is valid */ + if (rxmsg_len <= I2C_SMBUS_BLOCK_MAX) { + /* Set Receive fifo depth */ + if (rxmsg_len > IIC_RX_FIFO_DEPTH) { + rfd_set = IIC_RX_FIFO_DEPTH - 1; + i2c->rx_msg->len = rxmsg_len + 1; + } else if ((rxmsg_len == 1) || + (rxmsg_len == 0)) { + /* + * Minimum of 3 bytes required to exit cleanly. 1 byte + * already received, Second byte is being received. Have + * to set NACK in read_rx before receiving the last byte + */ + i2c->rx_msg->len = 3; + } else { + rfd_set = rxmsg_len - 2; + i2c->rx_msg->len = rxmsg_len + 1; + } + xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set); + + return; + } + + /* Invalid message length, trigger STATE_ERROR with tx_msg_len in ISR */ + i2c->tx_msg->len = 3; + i2c->smbus_block_read = false; + dev_err(i2c->adap.dev.parent, "smbus_block_read Invalid msg length\n"); +} + static void xiic_read_rx(struct xiic_i2c *i2c) { u8 bytes_in_fifo, cr = 0, bytes_to_read = 0; @@ -361,6 +411,12 @@ static void xiic_read_rx(struct xiic_i2c *i2c) if (!i2c->dynamic) { bytes_rem = xiic_rx_space(i2c) - bytes_in_fifo; + /* Set msg length if smbus_block_read */ + if (i2c->rx_msg->flags & I2C_M_RECV_LEN) { + xiic_smbus_block_read_setup(i2c); + return; + } + if (bytes_rem > IIC_RX_FIFO_DEPTH) { bytes_to_read = bytes_in_fifo; } else if (bytes_rem > 1) { @@ -638,6 +694,12 @@ static irqreturn_t xiic_process(int irq, void *dev_id) /* The bus is not busy, disable BusNotBusy interrupt */ xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); + if (i2c->tx_msg && i2c->smbus_block_read) { + i2c->smbus_block_read = false; + /* Set requested message len=1 to indicate STATE_DONE */ + i2c->tx_msg->len = 1; + } + if (!i2c->tx_msg) goto out; @@ -777,8 +839,12 @@ static void xiic_start_recv(struct xiic_i2c *i2c) rfd_set = IIC_RX_FIFO_DEPTH - 1; } else if ((rx_watermark == 1) || (rx_watermark == 0)) { rfd_set = rx_watermark - 1; - /* Handle single byte transfer separately */ - cr |= XIIC_CR_NO_ACK_MASK; + + /* Set No_ACK, except for smbus_block_read */ + if (!(i2c->rx_msg->flags & I2C_M_RECV_LEN)) { + /* Handle single byte transfer separately */ + cr |= XIIC_CR_NO_ACK_MASK; + } } else { rfd_set = rx_watermark - 2; } @@ -970,10 +1036,14 @@ static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) /* Initialize prev message type */ i2c->prev_msg_tx = false; - /* Enter standard mode only when read length is > 255 bytes */ + /* + * Enter standard mode only when read length is > 255 bytes or + * for smbus_block_read transaction + */ for (count = 0; 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Fri, 24 Jun 2022 05:07:05 -0700 Envelope-to: git@amd.com, michal.simek@amd.com, linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Received: from [172.23.64.2] (port=47736 helo=xhdvnc102.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1o4i5Z-000BXd-17; Fri, 24 Jun 2022 05:07:05 -0700 Received: by xhdvnc102.xilinx.com (Postfix, from userid 90444) id 60FA110454A; Fri, 24 Jun 2022 17:35:50 +0530 (IST) From: Manikanta Guntupalli To: , , , , , CC: Raviteja Narayanam , Manikanta Guntupalli Subject: [PATCH 07/12] i2c: xiic: Switch to Xiic standard mode for i2c-read Date: Fri, 24 Jun 2022 17:35:22 +0530 Message-ID: <1656072327-13628-8-git-send-email-manikanta.guntupalli@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1656072327-13628-1-git-send-email-manikanta.guntupalli@xilinx.com> References: <1656072327-13628-1-git-send-email-manikanta.guntupalli@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7402fd42-74e0-4585-15a1-08da55da16d9 X-MS-TrafficTypeDiagnostic: PH0PR02MB8389:EE_ X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SFV:NSPM; H:xsj-pvapexch01.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(13230016)(4636009)(376002)(346002)(396003)(136003)(39860400002)(36840700001)(40470700004)(46966006)(70206006)(4326008)(70586007)(8676002)(316002)(41300700001)(82310400005)(44832011)(36860700001)(7636003)(42186006)(336012)(110136005)(356005)(36756003)(47076005)(54906003)(426003)(5660300002)(82740400003)(40480700001)(478600001)(26005)(6266002)(186003)(83380400001)(40460700003)(2906002)(8936002)(107886003)(6666004)(2616005)(102446001)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2022 12:07:19.9497 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7402fd42-74e0-4585-15a1-08da55da16d9 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT062.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR02MB8389 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Raviteja Narayanam Xilinx I2C IP has two modes of operation, both of which implement I2C transactions. The only difference from sw perspective is the programming sequence for these modes. Dynamic mode -> Simple to program, less number of steps in sequence. Standard mode -> Gives flexibility, more number of steps in sequence. In dynamic mode, during the i2c-read transactions, if there is a delay(> 200us) between the register writes (address & byte count), read transaction fails. On a system with load, this scenario is occurring frequently. To avoid this, switch to standard mode if there is a read request. Added a quirk to identify the IP version effected by this and follow the standard mode. Signed-off-by: Raviteja Narayanam Signed-off-by: Manikanta Guntupalli --- drivers/i2c/busses/i2c-xiic.c | 87 +++++++++++++++++++++++------------ 1 file changed, 58 insertions(+), 29 deletions(-) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index 57ede62de67d..74cd50478694 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -32,6 +32,7 @@ #include #define DRIVER_NAME "xiic-i2c" +#define DYNAMIC_MODE_READ_BROKEN_BIT BIT(0) enum xilinx_i2c_state { STATE_DONE, @@ -63,6 +64,7 @@ enum xiic_endian { * @dynamic: Mode of controller * @prev_msg_tx: Previous message is Tx * @smbus_block_read: Flag to handle block read + * @quirks: To hold platform specific bug info */ struct xiic_i2c { struct device *dev; @@ -82,6 +84,11 @@ struct xiic_i2c { bool dynamic; bool prev_msg_tx; bool smbus_block_read; + u32 quirks; +}; + +struct xiic_version_data { + u32 quirks; }; #define XIIC_MSB_OFFSET 0 @@ -995,7 +1002,8 @@ static void __xiic_start_xfer(struct xiic_i2c *i2c) static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num) { - int ret; + bool broken_read, max_read_len, smbus_blk_read; + int ret, count; mutex_lock(&i2c->lock); @@ -1008,6 +1016,34 @@ static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num) i2c->nmsgs = num; init_completion(&i2c->completion); + /* Decide standard mode or Dynamic mode */ + i2c->dynamic = true; + + /* Initialize prev message type */ + i2c->prev_msg_tx = false; + + /* + * Scan through nmsgs, use dynamic mode when none of the below three + * conditions occur. We need standard mode even if one condition holds + * true in the entire array of messages in a single transfer. + * If read transaction as dynamic mode is broken for delayed reads + * in xlnx,axi-iic-2.0 / xlnx,xps-iic-2.00.a IP versions. + * If read length is > 255 bytes. + * If smbus_block_read transaction. + */ + for (count = 0; count < i2c->nmsgs; count++) { + broken_read = (i2c->quirks & DYNAMIC_MODE_READ_BROKEN_BIT) && + (i2c->tx_msg[count].flags & I2C_M_RD); + max_read_len = (i2c->tx_msg[count].flags & I2C_M_RD) && + (i2c->tx_msg[count].len > MAX_READ_LENGTH_DYNAMIC); + smbus_blk_read = (i2c->tx_msg[count].flags & I2C_M_RECV_LEN); + + if (broken_read || max_read_len || smbus_blk_read) { + i2c->dynamic = false; + break; + } + } + ret = xiic_reinit(i2c); if (!ret) __xiic_start_xfer(i2c); @@ -1021,7 +1057,7 @@ static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num) static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) { struct xiic_i2c *i2c = i2c_get_adapdata(adap); - int err, count; + int err; dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)); @@ -1030,25 +1066,6 @@ static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) if (err < 0) return err; - /* Decide standard mode or Dynamic mode */ - i2c->dynamic = true; - - /* Initialize prev message type */ - i2c->prev_msg_tx = false; - - /* - * Enter standard mode only when read length is > 255 bytes or - * for smbus_block_read transaction - */ - for (count = 0; count < i2c->nmsgs; count++) { - if (((i2c->tx_msg[count].flags & I2C_M_RD) && - i2c->tx_msg[count].len > MAX_READ_LENGTH_DYNAMIC) || - (i2c->tx_msg[count].flags & I2C_M_RECV_LEN)) { - i2c->dynamic = false; - break; - } - } - err = xiic_start_xfer(i2c, msgs, num); if (err < 0) { dev_err(adap->dev.parent, "Error xiic_start_xfer\n"); @@ -1091,10 +1108,23 @@ static const struct i2c_adapter xiic_adapter = { .algo = &xiic_algorithm, }; +static const struct xiic_version_data xiic_2_00 = { + .quirks = DYNAMIC_MODE_READ_BROKEN_BIT, +}; + +#if defined(CONFIG_OF) +static const struct of_device_id xiic_of_match[] = { + { .compatible = "xlnx,xps-iic-2.00.a", .data = &xiic_2_00 }, + {}, +}; +MODULE_DEVICE_TABLE(of, xiic_of_match); +#endif + static int xiic_i2c_probe(struct platform_device *pdev) { struct xiic_i2c *i2c; struct xiic_i2c_platform_data *pdata; + const struct of_device_id *match; struct resource *res; int ret, irq; u8 i; @@ -1104,6 +1134,13 @@ static int xiic_i2c_probe(struct platform_device *pdev) if (!i2c) return -ENOMEM; + match = of_match_node(xiic_of_match, pdev->dev.of_node); + if (match && match->data) { + const struct xiic_version_data *data = match->data; + + i2c->quirks = data->quirks; + } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); i2c->base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(i2c->base)) @@ -1215,14 +1252,6 @@ static int xiic_i2c_remove(struct platform_device *pdev) return 0; } -#if defined(CONFIG_OF) -static const struct of_device_id xiic_of_match[] = { - { .compatible = "xlnx,xps-iic-2.00.a", }, - {}, -}; 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Fri, 24 Jun 2022 05:07:18 -0700 Envelope-to: git@amd.com, michal.simek@amd.com, linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Received: from [172.23.64.2] (port=47737 helo=xhdvnc102.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1o4i5m-0005OP-DX; Fri, 24 Jun 2022 05:07:18 -0700 Received: by xhdvnc102.xilinx.com (Postfix, from userid 90444) id 7362210454B; Fri, 24 Jun 2022 17:35:52 +0530 (IST) From: Manikanta Guntupalli To: , , , , , CC: Raviteja Narayanam , Manikanta Guntupalli Subject: [PATCH 08/12] i2c: xiic: Remove interrupt enable/disable in Rx path Date: Fri, 24 Jun 2022 17:35:23 +0530 Message-ID: <1656072327-13628-9-git-send-email-manikanta.guntupalli@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1656072327-13628-1-git-send-email-manikanta.guntupalli@xilinx.com> References: <1656072327-13628-1-git-send-email-manikanta.guntupalli@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 16833a2a-5a4a-4290-5dd1-08da55da165c X-MS-TrafficTypeDiagnostic: CO6PR02MB8771:EE_ X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SFV:NSPM; H:xsj-pvapexch02.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(13230016)(4636009)(39860400002)(376002)(396003)(136003)(346002)(46966006)(40470700004)(36840700001)(70586007)(2906002)(356005)(41300700001)(82310400005)(40460700003)(70206006)(83380400001)(4326008)(6266002)(316002)(42186006)(8676002)(82740400003)(6666004)(7636003)(36756003)(8936002)(36860700001)(40480700001)(54906003)(478600001)(186003)(26005)(426003)(5660300002)(44832011)(110136005)(47076005)(336012)(107886003)(2616005)(102446001)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2022 12:07:19.1792 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 16833a2a-5a4a-4290-5dd1-08da55da165c X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0020.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR02MB8771 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Raviteja Narayanam As the 'DYNAMIC_MODE_READ_BROKEN_BIT' quirk is added in the driver, we no longer enter dynamic mode for the effected IP versions. So, remove local_irq_save/local_irq_restore APIs from driver. Signed-off-by: Raviteja Narayanam Signed-off-by: Manikanta Guntupalli --- drivers/i2c/busses/i2c-xiic.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index 74cd50478694..720aa671f74b 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -776,7 +776,6 @@ static void xiic_start_recv(struct xiic_i2c *i2c) u16 rx_watermark; u8 cr = 0, rfd_set = 0; struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; - unsigned long flags; dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), @@ -808,7 +807,6 @@ static void xiic_start_recv(struct xiic_i2c *i2c) xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes); - local_irq_save(flags); if (!(msg->flags & I2C_M_NOSTART)) /* write the address */ xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, @@ -822,7 +820,6 @@ static void xiic_start_recv(struct xiic_i2c *i2c) val |= msg->len; xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, val); 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Fri, 24 Jun 2022 05:07:31 -0700 Envelope-to: git@amd.com, michal.simek@amd.com, linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Received: from [172.23.64.2] (port=47738 helo=xhdvnc102.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1o4i5z-0005Oz-Gr; Fri, 24 Jun 2022 05:07:31 -0700 Received: by xhdvnc102.xilinx.com (Postfix, from userid 90444) id 928C010454C; Fri, 24 Jun 2022 17:35:54 +0530 (IST) From: Manikanta Guntupalli To: , , , , , CC: Raviteja Narayanam , Manikanta Guntupalli Subject: [PATCH 09/12] dt-bindings: i2c: xiic: Add 'xlnx,axi-iic-2.1' to compatible Date: Fri, 24 Jun 2022 17:35:24 +0530 Message-ID: <1656072327-13628-10-git-send-email-manikanta.guntupalli@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1656072327-13628-1-git-send-email-manikanta.guntupalli@xilinx.com> References: <1656072327-13628-1-git-send-email-manikanta.guntupalli@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f2853b89-ffc6-4e5e-cdc9-08da55da1ebe X-MS-TrafficTypeDiagnostic: SN1PR02MB3758:EE_ X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SFV:NSPM; H:xsj-pvapexch02.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(13230016)(4636009)(376002)(346002)(136003)(39860400002)(396003)(36840700001)(40470700004)(46966006)(4326008)(478600001)(2906002)(82310400005)(8676002)(70206006)(2616005)(40480700001)(8936002)(36860700001)(70586007)(41300700001)(7636003)(5660300002)(6266002)(82740400003)(26005)(44832011)(54906003)(42186006)(36756003)(83380400001)(426003)(356005)(107886003)(110136005)(6666004)(47076005)(40460700003)(336012)(316002)(186003)(102446001)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2022 12:07:33.2461 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f2853b89-ffc6-4e5e-cdc9-08da55da1ebe X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0039.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1PR02MB3758 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Raviteja Narayanam Xilinx AXI I2C IP is updated with a bug fix for dynamic mode reads. Older IPs are handled with a workaround in which they are using xiic standard mode for all these effected use cases. Added the xilinx I2C new version 'xlnx,axi-iic-2.1' string to compatible. Signed-off-by: Raviteja Narayanam Signed-off-by: Manikanta Guntupalli --- .../devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml b/Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml index 715dcfa5a922..e516c1ed358c 100644 --- a/Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml +++ b/Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml @@ -14,7 +14,9 @@ allOf: properties: compatible: - const: xlnx,xps-iic-2.00.a + enum: + - xlnx,xps-iic-2.00.a + - xlnx,axi-iic-2.1 reg: maxItems: 1 From patchwork Fri Jun 24 12:05:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Guntupalli X-Patchwork-Id: 585002 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95A9FC43334 for ; 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Fri, 24 Jun 2022 05:07:44 -0700 Envelope-to: git@amd.com, michal.simek@amd.com, linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Received: from [172.23.64.2] (port=47739 helo=xhdvnc102.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1o4i6C-000BZC-Jo; Fri, 24 Jun 2022 05:07:44 -0700 Received: by xhdvnc102.xilinx.com (Postfix, from userid 90444) id 8111B10454D; Fri, 24 Jun 2022 17:35:56 +0530 (IST) From: Manikanta Guntupalli To: , , , , , CC: Raviteja Narayanam , Manikanta Guntupalli Subject: [PATCH 10/12] i2c: xiic: Update compatible with new IP version Date: Fri, 24 Jun 2022 17:35:25 +0530 Message-ID: <1656072327-13628-11-git-send-email-manikanta.guntupalli@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1656072327-13628-1-git-send-email-manikanta.guntupalli@xilinx.com> References: <1656072327-13628-1-git-send-email-manikanta.guntupalli@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d24a4ffd-4658-4487-c700-08da55da25f8 X-MS-TrafficTypeDiagnostic: BL0PR02MB6513:EE_ X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SFV:NSPM; H:xsj-pvapexch02.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(13230016)(4636009)(396003)(376002)(136003)(346002)(39860400002)(46966006)(40470700004)(36840700001)(110136005)(26005)(316002)(6266002)(41300700001)(70206006)(82310400005)(6666004)(356005)(7636003)(36756003)(4326008)(36860700001)(70586007)(54906003)(2906002)(8676002)(336012)(5660300002)(47076005)(8936002)(42186006)(107886003)(426003)(40460700003)(2616005)(82740400003)(478600001)(15650500001)(83380400001)(4744005)(40480700001)(186003)(44832011)(102446001)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2022 12:07:45.3701 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d24a4ffd-4658-4487-c700-08da55da25f8 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0051.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR02MB6513 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Raviteja Narayanam Xilinx AXI I2C IP is updated with a bug fix for dynamic mode reads. Older IPs are handled with a workaround in which they are using xiic standard mode for all these effected use cases. Added the new IP version to compatible. Signed-off-by: Raviteja Narayanam Signed-off-by: Manikanta Guntupalli --- drivers/i2c/busses/i2c-xiic.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index 720aa671f74b..f9492c39d3c7 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -1112,6 +1112,7 @@ static const struct xiic_version_data xiic_2_00 = { #if defined(CONFIG_OF) static const struct of_device_id xiic_of_match[] = { { .compatible = "xlnx,xps-iic-2.00.a", .data = &xiic_2_00 }, + { .compatible = "xlnx,axi-iic-2.1", }, {}, }; MODULE_DEVICE_TABLE(of, xiic_of_match); From patchwork Fri Jun 24 12:05:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Guntupalli X-Patchwork-Id: 585001 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5B9AC433EF for ; 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Fri, 24 Jun 2022 05:08:11 -0700 Envelope-to: git@amd.com, michal.simek@amd.com, linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Received: from [172.23.64.2] (port=47741 helo=xhdvnc102.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1o4i6c-0005Qv-Vx; Fri, 24 Jun 2022 05:08:11 -0700 Received: by xhdvnc102.xilinx.com (Postfix, from userid 90444) id 7B663104546; Fri, 24 Jun 2022 17:35:59 +0530 (IST) From: Manikanta Guntupalli To: , , , , , CC: Srinivas Goud , Manikanta Guntupalli Subject: [PATCH 12/12] i2c: xiic: Correct the BNB interrupt enable sequence Date: Fri, 24 Jun 2022 17:35:27 +0530 Message-ID: <1656072327-13628-13-git-send-email-manikanta.guntupalli@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1656072327-13628-1-git-send-email-manikanta.guntupalli@xilinx.com> References: <1656072327-13628-1-git-send-email-manikanta.guntupalli@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4ee012a8-ee2a-46ee-664f-08da55da365c X-MS-TrafficTypeDiagnostic: BYAPR02MB5606:EE_ X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SFV:NSPM; H:xsj-pvapexch01.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(13230016)(4636009)(39860400002)(376002)(136003)(346002)(396003)(36840700001)(46966006)(40470700004)(478600001)(82740400003)(4326008)(356005)(42186006)(44832011)(83380400001)(70586007)(40460700003)(54906003)(186003)(6266002)(41300700001)(2616005)(336012)(70206006)(110136005)(6666004)(8676002)(316002)(36756003)(107886003)(7636003)(26005)(47076005)(5660300002)(426003)(8936002)(2906002)(82310400005)(36860700001)(40480700001)(102446001)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2022 12:08:12.8040 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4ee012a8-ee2a-46ee-664f-08da55da365c X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT007.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR02MB5606 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Srinivas Goud With updated AXI IIC IP core(v2.1)there is change in IP behavior in dynamic mode, where controller initiate read transfer on IIC bus only after getting the value for the number of bytes to receive. In the existing xiic_start_recv function Bus Not Busy(BNB) interrupt is enabled just after "slave address + start" write to FIFO and before the "count + stop"write to FIFO. Since IIC controller drives the start address of a transaction on the bus only after it has received the byte count information the above sequence can lead to spurious BNB interrupt in case there is any delay after "slave address + start" write to FIFO. This is fixed by ensuring that BNB interrupt is enabled only after "count + stop" has been written to FIFO. Signed-off-by: Srinivas Goud Signed-off-by: Manikanta Guntupalli --- drivers/i2c/busses/i2c-xiic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index f29acabba5e7..0a34daa9e372 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -851,13 +851,13 @@ static void xiic_start_recv(struct xiic_i2c *i2c) i2c_8bit_addr_from_msg(msg) | XIIC_TX_DYN_START_MASK); - xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); - /* If last message, include dynamic stop bit with length */ val = (i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0; val |= msg->len; xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, val); + + xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); } else { /* * If previous message is Tx, make sure that Tx FIFO is empty